mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 124:6a4a5b7d7324

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_tim.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	124:6a4a5b7d7324	5	* @version V1.0.4
mbed_official	124:6a4a5b7d7324	6	* @date 29-April-2016
mbed_official	124:6a4a5b7d7324	7	* @brief TIM HAL module driver
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Timer (TIM) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Time Base Initialization
bogdanm	0:9b334a45a8ff	11	* + Time Base Start
bogdanm	0:9b334a45a8ff	12	* + Time Base Start Interruption
bogdanm	0:9b334a45a8ff	13	* + Time Base Start DMA
bogdanm	0:9b334a45a8ff	14	* + Time Output Compare/PWM Initialization
bogdanm	0:9b334a45a8ff	15	* + Time Output Compare/PWM Channel Configuration
bogdanm	0:9b334a45a8ff	16	* + Time Output Compare/PWM Start
bogdanm	0:9b334a45a8ff	17	* + Time Output Compare/PWM Start Interruption
bogdanm	0:9b334a45a8ff	18	* + Time Output Compare/PWM Start DMA
bogdanm	0:9b334a45a8ff	19	* + Time Input Capture Initialization
bogdanm	0:9b334a45a8ff	20	* + Time Input Capture Channel Configuration
bogdanm	0:9b334a45a8ff	21	* + Time Input Capture Start
bogdanm	0:9b334a45a8ff	22	* + Time Input Capture Start Interruption
bogdanm	0:9b334a45a8ff	23	* + Time Input Capture Start DMA
bogdanm	0:9b334a45a8ff	24	* + Time One Pulse Initialization
bogdanm	0:9b334a45a8ff	25	* + Time One Pulse Channel Configuration
bogdanm	0:9b334a45a8ff	26	* + Time One Pulse Start
bogdanm	0:9b334a45a8ff	27	* + Time Encoder Interface Initialization
bogdanm	0:9b334a45a8ff	28	* + Time Encoder Interface Start
bogdanm	0:9b334a45a8ff	29	* + Time Encoder Interface Start Interruption
bogdanm	0:9b334a45a8ff	30	* + Time Encoder Interface Start DMA
bogdanm	0:9b334a45a8ff	31	* + Commutation Event configuration with Interruption and DMA
bogdanm	0:9b334a45a8ff	32	* + Time OCRef clear configuration
bogdanm	0:9b334a45a8ff	33	* + Time External Clock configuration
bogdanm	0:9b334a45a8ff	34	@verbatim
bogdanm	0:9b334a45a8ff	35	==============================================================================
bogdanm	0:9b334a45a8ff	36	##### TIMER Generic features #####
bogdanm	0:9b334a45a8ff	37	==============================================================================
bogdanm	0:9b334a45a8ff	38	[..] The Timer features include:
bogdanm	0:9b334a45a8ff	39	(#) 16-bit up, down, up/down auto-reload counter.
bogdanm	0:9b334a45a8ff	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
bogdanm	0:9b334a45a8ff	41	counter clock frequency either by any factor between 1 and 65536.
bogdanm	0:9b334a45a8ff	42	(#) Up to 4 independent channels for:
bogdanm	0:9b334a45a8ff	43	(++) Input Capture
bogdanm	0:9b334a45a8ff	44	(++) Output Compare
bogdanm	0:9b334a45a8ff	45	(++) PWM generation (Edge and Center-aligned Mode)
bogdanm	0:9b334a45a8ff	46	(++) One-pulse mode output
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	49	==============================================================================
bogdanm	0:9b334a45a8ff	50	[..]
bogdanm	0:9b334a45a8ff	51	(#) Initialize the TIM low level resources by implementing the following functions
bogdanm	0:9b334a45a8ff	52	depending from feature used :
bogdanm	0:9b334a45a8ff	53	(++) Time Base : HAL_TIM_Base_MspInit()
bogdanm	0:9b334a45a8ff	54	(++) Input Capture : HAL_TIM_IC_MspInit()
bogdanm	0:9b334a45a8ff	55	(++) Output Compare : HAL_TIM_OC_MspInit()
bogdanm	0:9b334a45a8ff	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
bogdanm	0:9b334a45a8ff	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm	0:9b334a45a8ff	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	(#) Initialize the TIM low level resources :
bogdanm	0:9b334a45a8ff	61	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	62	(##) TIM pins configuration
bogdanm	0:9b334a45a8ff	63	(+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official	124:6a4a5b7d7324	64	__HAL_RCC_GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	(#) The external Clock can be configured, if needed (the default clock is the
bogdanm	0:9b334a45a8ff	68	internal clock from the APBx), using the following function:
bogdanm	0:9b334a45a8ff	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm	0:9b334a45a8ff	70	any start function.
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	(#) Configure the TIM in the desired functioning mode using one of the
bogdanm	0:9b334a45a8ff	73	Initialization function of this driver:
bogdanm	0:9b334a45a8ff	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
bogdanm	0:9b334a45a8ff	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
bogdanm	0:9b334a45a8ff	76	Output Compare signal.
bogdanm	0:9b334a45a8ff	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
bogdanm	0:9b334a45a8ff	78	PWM signal.
bogdanm	0:9b334a45a8ff	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
bogdanm	0:9b334a45a8ff	80	external signal.
bogdanm	0:9b334a45a8ff	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
bogdanm	0:9b334a45a8ff	82	in One Pulse Mode.
bogdanm	0:9b334a45a8ff	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
bogdanm	0:9b334a45a8ff	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
bogdanm	0:9b334a45a8ff	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
bogdanm	0:9b334a45a8ff	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
bogdanm	0:9b334a45a8ff	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
bogdanm	0:9b334a45a8ff	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
bogdanm	0:9b334a45a8ff	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	(#) The DMA Burst is managed with the two following functions:
bogdanm	0:9b334a45a8ff	94	HAL_TIM_DMABurst_WriteStart()
bogdanm	0:9b334a45a8ff	95	HAL_TIM_DMABurst_ReadStart()
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	@endverbatim
bogdanm	0:9b334a45a8ff	98	******************************************************************************
bogdanm	0:9b334a45a8ff	99	* @attention
bogdanm	0:9b334a45a8ff	100	*
mbed_official	124:6a4a5b7d7324	101	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	102	*
bogdanm	0:9b334a45a8ff	103	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	104	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	105	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	106	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	108	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	109	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	111	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	112	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	124	*
bogdanm	0:9b334a45a8ff	125	******************************************************************************
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	129	#include "stm32f1xx_hal.h"
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	132	* @{
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup TIM TIM
bogdanm	0:9b334a45a8ff	136	* @brief TIM HAL module driver
bogdanm	0:9b334a45a8ff	137	* @{
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	#ifdef HAL_TIM_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	143	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	144	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	145	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	146	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	147	/** @defgroup TIM_Private_Functions TIM Private Functions
bogdanm	0:9b334a45a8ff	148	* @{
bogdanm	0:9b334a45a8ff	149	*/
bogdanm	0:9b334a45a8ff	150	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	151	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	152	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	153	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	154	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	155	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	156	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	157	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	158	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	159	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	160	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	161	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	162	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
bogdanm	0:9b334a45a8ff	163	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
bogdanm	0:9b334a45a8ff	164	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	165	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	166	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	167	TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/**
bogdanm	0:9b334a45a8ff	170	* @}
bogdanm	0:9b334a45a8ff	171	*/
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	174
bogdanm	0:9b334a45a8ff	175	/** @defgroup TIM_Exported_Functions TIM Exported Functions
bogdanm	0:9b334a45a8ff	176	* @{
bogdanm	0:9b334a45a8ff	177	*/
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm	0:9b334a45a8ff	180	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	181	*
bogdanm	0:9b334a45a8ff	182	@verbatim
bogdanm	0:9b334a45a8ff	183	==============================================================================
bogdanm	0:9b334a45a8ff	184	##### Time Base functions #####
bogdanm	0:9b334a45a8ff	185	==============================================================================
bogdanm	0:9b334a45a8ff	186	[..]
bogdanm	0:9b334a45a8ff	187	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	188	(+) Initialize and configure the TIM base.
bogdanm	0:9b334a45a8ff	189	(+) De-initialize the TIM base.
bogdanm	0:9b334a45a8ff	190	(+) Start the Time Base.
bogdanm	0:9b334a45a8ff	191	(+) Stop the Time Base.
bogdanm	0:9b334a45a8ff	192	(+) Start the Time Base and enable interrupt.
bogdanm	0:9b334a45a8ff	193	(+) Stop the Time Base and disable interrupt.
bogdanm	0:9b334a45a8ff	194	(+) Start the Time Base and enable DMA transfer.
bogdanm	0:9b334a45a8ff	195	(+) Stop the Time Base and disable DMA transfer.
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	@endverbatim
bogdanm	0:9b334a45a8ff	198	* @{
bogdanm	0:9b334a45a8ff	199	*/
bogdanm	0:9b334a45a8ff	200	/**
bogdanm	0:9b334a45a8ff	201	* @brief Initializes the TIM Time base Unit according to the specified
bogdanm	0:9b334a45a8ff	202	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	203	* @param htim : TIM Base handle
bogdanm	0:9b334a45a8ff	204	* @retval HAL status
bogdanm	0:9b334a45a8ff	205	*/
bogdanm	0:9b334a45a8ff	206	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	207	{
bogdanm	0:9b334a45a8ff	208	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	209	if(htim == NULL)
bogdanm	0:9b334a45a8ff	210	{
bogdanm	0:9b334a45a8ff	211	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	212	}
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/* Check the parameters */
bogdanm	0:9b334a45a8ff	215	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	216	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	217	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	220	{
bogdanm	0:9b334a45a8ff	221	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	222	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	223
bogdanm	0:9b334a45a8ff	224	/* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	225	HAL_TIM_Base_MspInit(htim);
bogdanm	0:9b334a45a8ff	226	}
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	229	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	/* Set the Time Base configuration */
bogdanm	0:9b334a45a8ff	232	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	235	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	return HAL_OK;
bogdanm	0:9b334a45a8ff	238	}
bogdanm	0:9b334a45a8ff	239
bogdanm	0:9b334a45a8ff	240	/**
bogdanm	0:9b334a45a8ff	241	* @brief DeInitializes the TIM Base peripheral
bogdanm	0:9b334a45a8ff	242	* @param htim : TIM Base handle
bogdanm	0:9b334a45a8ff	243	* @retval HAL status
bogdanm	0:9b334a45a8ff	244	*/
bogdanm	0:9b334a45a8ff	245	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	246	{
bogdanm	0:9b334a45a8ff	247	/* Check the parameters */
bogdanm	0:9b334a45a8ff	248	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	251
bogdanm	0:9b334a45a8ff	252	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	253	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	254
bogdanm	0:9b334a45a8ff	255	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	256	HAL_TIM_Base_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	/* Change TIM state */
bogdanm	0:9b334a45a8ff	259	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/* Release Lock */
bogdanm	0:9b334a45a8ff	262	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	return HAL_OK;
bogdanm	0:9b334a45a8ff	265	}
bogdanm	0:9b334a45a8ff	266
bogdanm	0:9b334a45a8ff	267	/**
bogdanm	0:9b334a45a8ff	268	* @brief Initializes the TIM Base MSP.
bogdanm	0:9b334a45a8ff	269	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	270	* @retval None
bogdanm	0:9b334a45a8ff	271	*/
bogdanm	0:9b334a45a8ff	272	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	273	{
mbed_official	124:6a4a5b7d7324	274	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	275	UNUSED(htim);
bogdanm	0:9b334a45a8ff	276	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	277	the HAL_TIM_Base_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	278	*/
bogdanm	0:9b334a45a8ff	279	}
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/**
bogdanm	0:9b334a45a8ff	282	* @brief DeInitializes TIM Base MSP.
bogdanm	0:9b334a45a8ff	283	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	284	* @retval None
bogdanm	0:9b334a45a8ff	285	*/
bogdanm	0:9b334a45a8ff	286	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	287	{
mbed_official	124:6a4a5b7d7324	288	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	289	UNUSED(htim);
bogdanm	0:9b334a45a8ff	290	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	291	the HAL_TIM_Base_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	292	*/
bogdanm	0:9b334a45a8ff	293	}
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	/**
bogdanm	0:9b334a45a8ff	297	* @brief Starts the TIM Base generation.
bogdanm	0:9b334a45a8ff	298	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	299	* @retval HAL status
bogdanm	0:9b334a45a8ff	300	*/
bogdanm	0:9b334a45a8ff	301	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	302	{
bogdanm	0:9b334a45a8ff	303	/* Check the parameters */
bogdanm	0:9b334a45a8ff	304	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	307	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	310	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	313	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/* Return function status */
bogdanm	0:9b334a45a8ff	316	return HAL_OK;
bogdanm	0:9b334a45a8ff	317	}
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	/**
bogdanm	0:9b334a45a8ff	320	* @brief Stops the TIM Base generation.
bogdanm	0:9b334a45a8ff	321	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	322	* @retval HAL status
bogdanm	0:9b334a45a8ff	323	*/
bogdanm	0:9b334a45a8ff	324	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	325	{
bogdanm	0:9b334a45a8ff	326	/* Check the parameters */
bogdanm	0:9b334a45a8ff	327	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	330	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	333	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	336	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/* Return function status */
bogdanm	0:9b334a45a8ff	339	return HAL_OK;
bogdanm	0:9b334a45a8ff	340	}
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/**
bogdanm	0:9b334a45a8ff	343	* @brief Starts the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	344	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	345	* @retval HAL status
bogdanm	0:9b334a45a8ff	346	*/
bogdanm	0:9b334a45a8ff	347	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	348	{
bogdanm	0:9b334a45a8ff	349	/* Check the parameters */
bogdanm	0:9b334a45a8ff	350	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/* Enable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	353	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	356	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	/* Return function status */
bogdanm	0:9b334a45a8ff	359	return HAL_OK;
bogdanm	0:9b334a45a8ff	360	}
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	/**
bogdanm	0:9b334a45a8ff	363	* @brief Stops the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	364	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	365	* @retval HAL status
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	368	{
bogdanm	0:9b334a45a8ff	369	/* Check the parameters */
bogdanm	0:9b334a45a8ff	370	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	371	/* Disable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	372	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	375	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	/* Return function status */
bogdanm	0:9b334a45a8ff	378	return HAL_OK;
bogdanm	0:9b334a45a8ff	379	}
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/**
bogdanm	0:9b334a45a8ff	382	* @brief Starts the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	383	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	384	* @param pData : The source Buffer address.
bogdanm	0:9b334a45a8ff	385	* @param Length : The length of data to be transferred from memory to peripheral.
bogdanm	0:9b334a45a8ff	386	* @retval HAL status
bogdanm	0:9b334a45a8ff	387	*/
bogdanm	0:9b334a45a8ff	388	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	389	{
bogdanm	0:9b334a45a8ff	390	/* Check the parameters */
bogdanm	0:9b334a45a8ff	391	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	394	{
bogdanm	0:9b334a45a8ff	395	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	396	}
bogdanm	0:9b334a45a8ff	397	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	398	{
bogdanm	0:9b334a45a8ff	399	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	400	{
bogdanm	0:9b334a45a8ff	401	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	402	}
bogdanm	0:9b334a45a8ff	403	else
bogdanm	0:9b334a45a8ff	404	{
bogdanm	0:9b334a45a8ff	405	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	406	}
bogdanm	0:9b334a45a8ff	407	}
bogdanm	0:9b334a45a8ff	408	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	409	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	412	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	415	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
bogdanm	0:9b334a45a8ff	416
bogdanm	0:9b334a45a8ff	417	/* Enable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	418	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	421	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/* Return function status */
bogdanm	0:9b334a45a8ff	424	return HAL_OK;
bogdanm	0:9b334a45a8ff	425	}
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/**
bogdanm	0:9b334a45a8ff	428	* @brief Stops the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	429	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	430	* @retval HAL status
bogdanm	0:9b334a45a8ff	431	*/
bogdanm	0:9b334a45a8ff	432	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	433	{
bogdanm	0:9b334a45a8ff	434	/* Check the parameters */
bogdanm	0:9b334a45a8ff	435	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	438	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	441	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	/* Change the htim state */
bogdanm	0:9b334a45a8ff	444	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	/* Return function status */
bogdanm	0:9b334a45a8ff	447	return HAL_OK;
bogdanm	0:9b334a45a8ff	448	}
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/**
bogdanm	0:9b334a45a8ff	451	* @}
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm	0:9b334a45a8ff	455	* @brief Time Output Compare functions
bogdanm	0:9b334a45a8ff	456	*
bogdanm	0:9b334a45a8ff	457	@verbatim
bogdanm	0:9b334a45a8ff	458	==============================================================================
bogdanm	0:9b334a45a8ff	459	##### Time Output Compare functions #####
bogdanm	0:9b334a45a8ff	460	==============================================================================
bogdanm	0:9b334a45a8ff	461	[..]
bogdanm	0:9b334a45a8ff	462	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	463	(+) Initialize and configure the TIM Output Compare.
bogdanm	0:9b334a45a8ff	464	(+) De-initialize the TIM Output Compare.
bogdanm	0:9b334a45a8ff	465	(+) Start the Time Output Compare.
bogdanm	0:9b334a45a8ff	466	(+) Stop the Time Output Compare.
bogdanm	0:9b334a45a8ff	467	(+) Start the Time Output Compare and enable interrupt.
bogdanm	0:9b334a45a8ff	468	(+) Stop the Time Output Compare and disable interrupt.
bogdanm	0:9b334a45a8ff	469	(+) Start the Time Output Compare and enable DMA transfer.
bogdanm	0:9b334a45a8ff	470	(+) Stop the Time Output Compare and disable DMA transfer.
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	@endverbatim
bogdanm	0:9b334a45a8ff	473	* @{
bogdanm	0:9b334a45a8ff	474	*/
bogdanm	0:9b334a45a8ff	475	/**
bogdanm	0:9b334a45a8ff	476	* @brief Initializes the TIM Output Compare according to the specified
bogdanm	0:9b334a45a8ff	477	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	478	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	479	* @retval HAL status
bogdanm	0:9b334a45a8ff	480	*/
bogdanm	0:9b334a45a8ff	481	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
bogdanm	0:9b334a45a8ff	482	{
bogdanm	0:9b334a45a8ff	483	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	484	if(htim == NULL)
bogdanm	0:9b334a45a8ff	485	{
bogdanm	0:9b334a45a8ff	486	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	487	}
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	/* Check the parameters */
bogdanm	0:9b334a45a8ff	490	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	491	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	492	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	495	{
bogdanm	0:9b334a45a8ff	496	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	497	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	500	HAL_TIM_OC_MspInit(htim);
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	504	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	505
bogdanm	0:9b334a45a8ff	506	/* Init the base time for the Output Compare */
bogdanm	0:9b334a45a8ff	507	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	510	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	return HAL_OK;
bogdanm	0:9b334a45a8ff	513	}
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	/**
bogdanm	0:9b334a45a8ff	516	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	517	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	518	* @retval HAL status
bogdanm	0:9b334a45a8ff	519	*/
bogdanm	0:9b334a45a8ff	520	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	521	{
bogdanm	0:9b334a45a8ff	522	/* Check the parameters */
bogdanm	0:9b334a45a8ff	523	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	528	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	531	HAL_TIM_OC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	/* Change TIM state */
bogdanm	0:9b334a45a8ff	534	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/* Release Lock */
bogdanm	0:9b334a45a8ff	537	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	return HAL_OK;
bogdanm	0:9b334a45a8ff	540	}
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	/**
bogdanm	0:9b334a45a8ff	543	* @brief Initializes the TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	544	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	545	* @retval None
bogdanm	0:9b334a45a8ff	546	*/
bogdanm	0:9b334a45a8ff	547	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	548	{
mbed_official	124:6a4a5b7d7324	549	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	550	UNUSED(htim);
bogdanm	0:9b334a45a8ff	551	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	552	the HAL_TIM_OC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	553	*/
bogdanm	0:9b334a45a8ff	554	}
bogdanm	0:9b334a45a8ff	555
bogdanm	0:9b334a45a8ff	556	/**
bogdanm	0:9b334a45a8ff	557	* @brief DeInitializes TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	558	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	559	* @retval None
bogdanm	0:9b334a45a8ff	560	*/
bogdanm	0:9b334a45a8ff	561	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	562	{
mbed_official	124:6a4a5b7d7324	563	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	564	UNUSED(htim);
bogdanm	0:9b334a45a8ff	565	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	566	the HAL_TIM_OC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	567	*/
bogdanm	0:9b334a45a8ff	568	}
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	/**
bogdanm	0:9b334a45a8ff	571	* @brief Starts the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	572	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	573	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	574	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	575	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	576	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	577	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	578	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	579	* @retval HAL status
bogdanm	0:9b334a45a8ff	580	*/
bogdanm	0:9b334a45a8ff	581	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	582	{
bogdanm	0:9b334a45a8ff	583	/* Check the parameters */
bogdanm	0:9b334a45a8ff	584	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	585
bogdanm	0:9b334a45a8ff	586	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	587	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	588
bogdanm	0:9b334a45a8ff	589	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	590	{
bogdanm	0:9b334a45a8ff	591	/* Enable the main output */
bogdanm	0:9b334a45a8ff	592	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	593	}
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	596	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	/* Return function status */
bogdanm	0:9b334a45a8ff	599	return HAL_OK;
bogdanm	0:9b334a45a8ff	600	}
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/**
bogdanm	0:9b334a45a8ff	603	* @brief Stops the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	604	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	605	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	606	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	607	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	608	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	609	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	610	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	611	* @retval HAL status
bogdanm	0:9b334a45a8ff	612	*/
bogdanm	0:9b334a45a8ff	613	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	614	{
bogdanm	0:9b334a45a8ff	615	/* Check the parameters */
bogdanm	0:9b334a45a8ff	616	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	619	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	622	{
bogdanm	0:9b334a45a8ff	623	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	624	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	625	}
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	628	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	/* Return function status */
bogdanm	0:9b334a45a8ff	631	return HAL_OK;
bogdanm	0:9b334a45a8ff	632	}
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	/**
bogdanm	0:9b334a45a8ff	635	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	636	* @param htim : TIM OC handle
bogdanm	0:9b334a45a8ff	637	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	638	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	639	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	640	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	641	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	642	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	643	* @retval HAL status
bogdanm	0:9b334a45a8ff	644	*/
bogdanm	0:9b334a45a8ff	645	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	646	{
bogdanm	0:9b334a45a8ff	647	/* Check the parameters */
bogdanm	0:9b334a45a8ff	648	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	switch (Channel)
bogdanm	0:9b334a45a8ff	651	{
bogdanm	0:9b334a45a8ff	652	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	653	{
bogdanm	0:9b334a45a8ff	654	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	655	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657	break;
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	660	{
bogdanm	0:9b334a45a8ff	661	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	662	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	663	}
bogdanm	0:9b334a45a8ff	664	break;
bogdanm	0:9b334a45a8ff	665
bogdanm	0:9b334a45a8ff	666	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	667	{
bogdanm	0:9b334a45a8ff	668	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	669	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	670	}
bogdanm	0:9b334a45a8ff	671	break;
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	674	{
bogdanm	0:9b334a45a8ff	675	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	676	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	677	}
bogdanm	0:9b334a45a8ff	678	break;
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	default:
bogdanm	0:9b334a45a8ff	681	break;
bogdanm	0:9b334a45a8ff	682	}
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	685	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	686
bogdanm	0:9b334a45a8ff	687	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	688	{
bogdanm	0:9b334a45a8ff	689	/* Enable the main output */
bogdanm	0:9b334a45a8ff	690	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	691	}
bogdanm	0:9b334a45a8ff	692
bogdanm	0:9b334a45a8ff	693	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	694	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/* Return function status */
bogdanm	0:9b334a45a8ff	697	return HAL_OK;
bogdanm	0:9b334a45a8ff	698	}
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/**
bogdanm	0:9b334a45a8ff	701	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	702	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	703	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	704	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	705	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	706	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	707	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	708	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	709	* @retval HAL status
bogdanm	0:9b334a45a8ff	710	*/
bogdanm	0:9b334a45a8ff	711	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	712	{
bogdanm	0:9b334a45a8ff	713	/* Check the parameters */
bogdanm	0:9b334a45a8ff	714	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	715
bogdanm	0:9b334a45a8ff	716	switch (Channel)
bogdanm	0:9b334a45a8ff	717	{
bogdanm	0:9b334a45a8ff	718	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	719	{
bogdanm	0:9b334a45a8ff	720	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	721	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	722	}
bogdanm	0:9b334a45a8ff	723	break;
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	726	{
bogdanm	0:9b334a45a8ff	727	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	728	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	729	}
bogdanm	0:9b334a45a8ff	730	break;
bogdanm	0:9b334a45a8ff	731
bogdanm	0:9b334a45a8ff	732	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	733	{
bogdanm	0:9b334a45a8ff	734	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	735	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	736	}
bogdanm	0:9b334a45a8ff	737	break;
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	740	{
bogdanm	0:9b334a45a8ff	741	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	742	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	743	}
bogdanm	0:9b334a45a8ff	744	break;
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	default:
bogdanm	0:9b334a45a8ff	747	break;
bogdanm	0:9b334a45a8ff	748	}
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	751	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	754	{
bogdanm	0:9b334a45a8ff	755	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	756	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	757	}
bogdanm	0:9b334a45a8ff	758
bogdanm	0:9b334a45a8ff	759	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	760	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	/* Return function status */
bogdanm	0:9b334a45a8ff	763	return HAL_OK;
bogdanm	0:9b334a45a8ff	764	}
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	/**
bogdanm	0:9b334a45a8ff	767	* @brief Starts the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	768	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	769	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	770	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	771	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	772	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	773	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	774	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	775	* @param pData : The source Buffer address.
bogdanm	0:9b334a45a8ff	776	* @param Length : The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	777	* @retval HAL status
bogdanm	0:9b334a45a8ff	778	*/
bogdanm	0:9b334a45a8ff	779	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	780	{
bogdanm	0:9b334a45a8ff	781	/* Check the parameters */
bogdanm	0:9b334a45a8ff	782	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	785	{
bogdanm	0:9b334a45a8ff	786	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	787	}
bogdanm	0:9b334a45a8ff	788	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	789	{
bogdanm	0:9b334a45a8ff	790	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	791	{
bogdanm	0:9b334a45a8ff	792	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	793	}
bogdanm	0:9b334a45a8ff	794	else
bogdanm	0:9b334a45a8ff	795	{
bogdanm	0:9b334a45a8ff	796	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	797	}
bogdanm	0:9b334a45a8ff	798	}
bogdanm	0:9b334a45a8ff	799	switch (Channel)
bogdanm	0:9b334a45a8ff	800	{
bogdanm	0:9b334a45a8ff	801	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	804	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	807	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	810	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	811
bogdanm	0:9b334a45a8ff	812	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	813	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	814	}
bogdanm	0:9b334a45a8ff	815	break;
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	818	{
bogdanm	0:9b334a45a8ff	819	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	820	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	823	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	826	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	829	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	830	}
bogdanm	0:9b334a45a8ff	831	break;
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	834	{
bogdanm	0:9b334a45a8ff	835	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	836	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	839	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	842	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	845	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	846	}
bogdanm	0:9b334a45a8ff	847	break;
bogdanm	0:9b334a45a8ff	848
bogdanm	0:9b334a45a8ff	849	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	850	{
bogdanm	0:9b334a45a8ff	851	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	852	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	855	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	858	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	861	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	862	}
bogdanm	0:9b334a45a8ff	863	break;
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	default:
bogdanm	0:9b334a45a8ff	866	break;
bogdanm	0:9b334a45a8ff	867	}
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	870	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	/* Enable the main output */
bogdanm	0:9b334a45a8ff	875	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	876	}
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	879	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	/* Return function status */
bogdanm	0:9b334a45a8ff	882	return HAL_OK;
bogdanm	0:9b334a45a8ff	883	}
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/**
bogdanm	0:9b334a45a8ff	886	* @brief Stops the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	887	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	888	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	889	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	890	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	891	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	892	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	893	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	894	* @retval HAL status
bogdanm	0:9b334a45a8ff	895	*/
bogdanm	0:9b334a45a8ff	896	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	897	{
bogdanm	0:9b334a45a8ff	898	/* Check the parameters */
bogdanm	0:9b334a45a8ff	899	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	switch (Channel)
bogdanm	0:9b334a45a8ff	902	{
bogdanm	0:9b334a45a8ff	903	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	904	{
bogdanm	0:9b334a45a8ff	905	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	906	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	907	}
bogdanm	0:9b334a45a8ff	908	break;
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	911	{
bogdanm	0:9b334a45a8ff	912	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	913	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	914	}
bogdanm	0:9b334a45a8ff	915	break;
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	918	{
bogdanm	0:9b334a45a8ff	919	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	920	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	921	}
bogdanm	0:9b334a45a8ff	922	break;
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	925	{
bogdanm	0:9b334a45a8ff	926	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	927	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	928	}
bogdanm	0:9b334a45a8ff	929	break;
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931	default:
bogdanm	0:9b334a45a8ff	932	break;
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	936	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	939	{
bogdanm	0:9b334a45a8ff	940	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	941	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	942	}
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	945	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	/* Change the htim state */
bogdanm	0:9b334a45a8ff	948	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	/* Return function status */
bogdanm	0:9b334a45a8ff	951	return HAL_OK;
bogdanm	0:9b334a45a8ff	952	}
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	/**
bogdanm	0:9b334a45a8ff	955	* @}
bogdanm	0:9b334a45a8ff	956	*/
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm	0:9b334a45a8ff	959	* @brief Time PWM functions
bogdanm	0:9b334a45a8ff	960	*
bogdanm	0:9b334a45a8ff	961	@verbatim
bogdanm	0:9b334a45a8ff	962	==============================================================================
bogdanm	0:9b334a45a8ff	963	##### Time PWM functions #####
bogdanm	0:9b334a45a8ff	964	==============================================================================
bogdanm	0:9b334a45a8ff	965	[..]
bogdanm	0:9b334a45a8ff	966	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	967	(+) Initialize and configure the TIM PWM.
bogdanm	0:9b334a45a8ff	968	(+) De-initialize the TIM PWM.
bogdanm	0:9b334a45a8ff	969	(+) Start the Time PWM.
bogdanm	0:9b334a45a8ff	970	(+) Stop the Time PWM.
bogdanm	0:9b334a45a8ff	971	(+) Start the Time PWM and enable interrupt.
bogdanm	0:9b334a45a8ff	972	(+) Stop the Time PWM and disable interrupt.
bogdanm	0:9b334a45a8ff	973	(+) Start the Time PWM and enable DMA transfer.
bogdanm	0:9b334a45a8ff	974	(+) Stop the Time PWM and disable DMA transfer.
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	@endverbatim
bogdanm	0:9b334a45a8ff	977	* @{
bogdanm	0:9b334a45a8ff	978	*/
bogdanm	0:9b334a45a8ff	979	/**
bogdanm	0:9b334a45a8ff	980	* @brief Initializes the TIM PWM Time Base according to the specified
bogdanm	0:9b334a45a8ff	981	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	982	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	983	* @retval HAL status
bogdanm	0:9b334a45a8ff	984	*/
bogdanm	0:9b334a45a8ff	985	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	986	{
bogdanm	0:9b334a45a8ff	987	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	988	if(htim == NULL)
bogdanm	0:9b334a45a8ff	989	{
bogdanm	0:9b334a45a8ff	990	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	991	}
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	/* Check the parameters */
bogdanm	0:9b334a45a8ff	994	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	995	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	996	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	999	{
bogdanm	0:9b334a45a8ff	1000	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	1001	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1004	HAL_TIM_PWM_MspInit(htim);
bogdanm	0:9b334a45a8ff	1005	}
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1008	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	/* Init the base time for the PWM */
bogdanm	0:9b334a45a8ff	1011	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1014	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	return HAL_OK;
bogdanm	0:9b334a45a8ff	1017	}
bogdanm	0:9b334a45a8ff	1018
bogdanm	0:9b334a45a8ff	1019	/**
bogdanm	0:9b334a45a8ff	1020	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	1021	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1022	* @retval HAL status
bogdanm	0:9b334a45a8ff	1023	*/
bogdanm	0:9b334a45a8ff	1024	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1025	{
bogdanm	0:9b334a45a8ff	1026	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1027	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1032	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1033
bogdanm	0:9b334a45a8ff	1034	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1035	HAL_TIM_PWM_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1038	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	/* Release Lock */
bogdanm	0:9b334a45a8ff	1041	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	return HAL_OK;
bogdanm	0:9b334a45a8ff	1044	}
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	/**
bogdanm	0:9b334a45a8ff	1047	* @brief Initializes the TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1048	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1049	* @retval None
bogdanm	0:9b334a45a8ff	1050	*/
bogdanm	0:9b334a45a8ff	1051	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1052	{
mbed_official	124:6a4a5b7d7324	1053	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1054	UNUSED(htim);
bogdanm	0:9b334a45a8ff	1055	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1056	the HAL_TIM_PWM_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1057	*/
bogdanm	0:9b334a45a8ff	1058	}
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/**
bogdanm	0:9b334a45a8ff	1061	* @brief DeInitializes TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1062	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1063	* @retval None
bogdanm	0:9b334a45a8ff	1064	*/
bogdanm	0:9b334a45a8ff	1065	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1066	{
mbed_official	124:6a4a5b7d7324	1067	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1068	UNUSED(htim);
bogdanm	0:9b334a45a8ff	1069	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1070	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1071	*/
bogdanm	0:9b334a45a8ff	1072	}
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074	/**
bogdanm	0:9b334a45a8ff	1075	* @brief Starts the PWM signal generation.
bogdanm	0:9b334a45a8ff	1076	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1077	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1078	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1079	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1080	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1081	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1082	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1083	* @retval HAL status
bogdanm	0:9b334a45a8ff	1084	*/
bogdanm	0:9b334a45a8ff	1085	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1086	{
bogdanm	0:9b334a45a8ff	1087	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1088	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1089
bogdanm	0:9b334a45a8ff	1090	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1091	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1092
bogdanm	0:9b334a45a8ff	1093	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1094	{
bogdanm	0:9b334a45a8ff	1095	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1096	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1097	}
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1100	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1101
bogdanm	0:9b334a45a8ff	1102	/* Return function status */
bogdanm	0:9b334a45a8ff	1103	return HAL_OK;
bogdanm	0:9b334a45a8ff	1104	}
bogdanm	0:9b334a45a8ff	1105
bogdanm	0:9b334a45a8ff	1106	/**
bogdanm	0:9b334a45a8ff	1107	* @brief Stops the PWM signal generation.
bogdanm	0:9b334a45a8ff	1108	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1109	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1110	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1111	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1112	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1113	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1114	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1115	* @retval HAL status
bogdanm	0:9b334a45a8ff	1116	*/
bogdanm	0:9b334a45a8ff	1117	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1118	{
bogdanm	0:9b334a45a8ff	1119	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1120	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1121
bogdanm	0:9b334a45a8ff	1122	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1123	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1126	{
bogdanm	0:9b334a45a8ff	1127	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1128	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1129	}
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1132	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1135	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/* Return function status */
bogdanm	0:9b334a45a8ff	1138	return HAL_OK;
bogdanm	0:9b334a45a8ff	1139	}
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	/**
bogdanm	0:9b334a45a8ff	1142	* @brief Starts the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1143	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1144	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1145	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1146	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1147	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1148	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1149	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1150	* @retval HAL status
bogdanm	0:9b334a45a8ff	1151	*/
bogdanm	0:9b334a45a8ff	1152	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1153	{
bogdanm	0:9b334a45a8ff	1154	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1155	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	switch (Channel)
bogdanm	0:9b334a45a8ff	1158	{
bogdanm	0:9b334a45a8ff	1159	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1160	{
bogdanm	0:9b334a45a8ff	1161	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1162	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1163	}
bogdanm	0:9b334a45a8ff	1164	break;
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1167	{
bogdanm	0:9b334a45a8ff	1168	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1169	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1170	}
bogdanm	0:9b334a45a8ff	1171	break;
bogdanm	0:9b334a45a8ff	1172
bogdanm	0:9b334a45a8ff	1173	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1174	{
bogdanm	0:9b334a45a8ff	1175	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1176	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1177	}
bogdanm	0:9b334a45a8ff	1178	break;
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1181	{
bogdanm	0:9b334a45a8ff	1182	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1183	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1184	}
bogdanm	0:9b334a45a8ff	1185	break;
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	default:
bogdanm	0:9b334a45a8ff	1188	break;
bogdanm	0:9b334a45a8ff	1189	}
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1192	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1195	{
bogdanm	0:9b334a45a8ff	1196	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1197	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1198	}
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1201	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/* Return function status */
bogdanm	0:9b334a45a8ff	1204	return HAL_OK;
bogdanm	0:9b334a45a8ff	1205	}
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/**
bogdanm	0:9b334a45a8ff	1208	* @brief Stops the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1209	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1210	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1211	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1212	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1213	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1214	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1215	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1216	* @retval HAL status
bogdanm	0:9b334a45a8ff	1217	*/
bogdanm	0:9b334a45a8ff	1218	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1219	{
bogdanm	0:9b334a45a8ff	1220	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1221	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	switch (Channel)
bogdanm	0:9b334a45a8ff	1224	{
bogdanm	0:9b334a45a8ff	1225	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1226	{
bogdanm	0:9b334a45a8ff	1227	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1228	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1229	}
bogdanm	0:9b334a45a8ff	1230	break;
bogdanm	0:9b334a45a8ff	1231
bogdanm	0:9b334a45a8ff	1232	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1233	{
bogdanm	0:9b334a45a8ff	1234	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1235	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1236	}
bogdanm	0:9b334a45a8ff	1237	break;
bogdanm	0:9b334a45a8ff	1238
bogdanm	0:9b334a45a8ff	1239	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1240	{
bogdanm	0:9b334a45a8ff	1241	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1242	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1243	}
bogdanm	0:9b334a45a8ff	1244	break;
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1247	{
bogdanm	0:9b334a45a8ff	1248	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1249	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1250	}
bogdanm	0:9b334a45a8ff	1251	break;
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	default:
bogdanm	0:9b334a45a8ff	1254	break;
bogdanm	0:9b334a45a8ff	1255	}
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1258	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1261	{
bogdanm	0:9b334a45a8ff	1262	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1263	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1264	}
bogdanm	0:9b334a45a8ff	1265
bogdanm	0:9b334a45a8ff	1266	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1267	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	/* Return function status */
bogdanm	0:9b334a45a8ff	1270	return HAL_OK;
bogdanm	0:9b334a45a8ff	1271	}
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	/**
bogdanm	0:9b334a45a8ff	1274	* @brief Starts the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1275	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1276	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1277	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1278	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1279	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1280	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1281	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1282	* @param pData : The source Buffer address.
bogdanm	0:9b334a45a8ff	1283	* @param Length : The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	1284	* @retval HAL status
bogdanm	0:9b334a45a8ff	1285	*/
bogdanm	0:9b334a45a8ff	1286	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1287	{
bogdanm	0:9b334a45a8ff	1288	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1289	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1292	{
bogdanm	0:9b334a45a8ff	1293	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1294	}
bogdanm	0:9b334a45a8ff	1295	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1296	{
bogdanm	0:9b334a45a8ff	1297	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1298	{
bogdanm	0:9b334a45a8ff	1299	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1300	}
bogdanm	0:9b334a45a8ff	1301	else
bogdanm	0:9b334a45a8ff	1302	{
bogdanm	0:9b334a45a8ff	1303	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1304	}
bogdanm	0:9b334a45a8ff	1305	}
bogdanm	0:9b334a45a8ff	1306	switch (Channel)
bogdanm	0:9b334a45a8ff	1307	{
bogdanm	0:9b334a45a8ff	1308	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1309	{
bogdanm	0:9b334a45a8ff	1310	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1311	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1314	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1315
bogdanm	0:9b334a45a8ff	1316	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1317	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	1318
bogdanm	0:9b334a45a8ff	1319	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1320	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1321	}
bogdanm	0:9b334a45a8ff	1322	break;
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1325	{
bogdanm	0:9b334a45a8ff	1326	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1327	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1330	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1331
bogdanm	0:9b334a45a8ff	1332	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1333	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	1334
bogdanm	0:9b334a45a8ff	1335	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1336	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1337	}
bogdanm	0:9b334a45a8ff	1338	break;
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1341	{
bogdanm	0:9b334a45a8ff	1342	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1343	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1346	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1349	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	/* Enable the TIM Output Capture/Compare 3 request */
bogdanm	0:9b334a45a8ff	1352	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1353	}
bogdanm	0:9b334a45a8ff	1354	break;
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1357	{
bogdanm	0:9b334a45a8ff	1358	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1359	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1360
bogdanm	0:9b334a45a8ff	1361	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1362	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1365	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1368	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1369	}
bogdanm	0:9b334a45a8ff	1370	break;
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	default:
bogdanm	0:9b334a45a8ff	1373	break;
bogdanm	0:9b334a45a8ff	1374	}
bogdanm	0:9b334a45a8ff	1375
bogdanm	0:9b334a45a8ff	1376	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1377	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1378
bogdanm	0:9b334a45a8ff	1379	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1380	{
bogdanm	0:9b334a45a8ff	1381	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1382	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1383	}
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1386	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	/* Return function status */
bogdanm	0:9b334a45a8ff	1389	return HAL_OK;
bogdanm	0:9b334a45a8ff	1390	}
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	/**
bogdanm	0:9b334a45a8ff	1393	* @brief Stops the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1394	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1395	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1396	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1397	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1398	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1399	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1400	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1401	* @retval HAL status
bogdanm	0:9b334a45a8ff	1402	*/
bogdanm	0:9b334a45a8ff	1403	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1404	{
bogdanm	0:9b334a45a8ff	1405	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1406	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	switch (Channel)
bogdanm	0:9b334a45a8ff	1409	{
bogdanm	0:9b334a45a8ff	1410	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1411	{
bogdanm	0:9b334a45a8ff	1412	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1413	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1414	}
bogdanm	0:9b334a45a8ff	1415	break;
bogdanm	0:9b334a45a8ff	1416
bogdanm	0:9b334a45a8ff	1417	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1418	{
bogdanm	0:9b334a45a8ff	1419	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1420	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1421	}
bogdanm	0:9b334a45a8ff	1422	break;
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1425	{
bogdanm	0:9b334a45a8ff	1426	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1427	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1428	}
bogdanm	0:9b334a45a8ff	1429	break;
bogdanm	0:9b334a45a8ff	1430
bogdanm	0:9b334a45a8ff	1431	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1432	{
bogdanm	0:9b334a45a8ff	1433	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1434	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1435	}
bogdanm	0:9b334a45a8ff	1436	break;
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	default:
bogdanm	0:9b334a45a8ff	1439	break;
bogdanm	0:9b334a45a8ff	1440	}
bogdanm	0:9b334a45a8ff	1441
bogdanm	0:9b334a45a8ff	1442	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1443	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1446	{
bogdanm	0:9b334a45a8ff	1447	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1448	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1449	}
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1452	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1453
bogdanm	0:9b334a45a8ff	1454	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1455	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	/* Return function status */
bogdanm	0:9b334a45a8ff	1458	return HAL_OK;
bogdanm	0:9b334a45a8ff	1459	}
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/**
bogdanm	0:9b334a45a8ff	1462	* @}
bogdanm	0:9b334a45a8ff	1463	*/
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm	0:9b334a45a8ff	1466	* @brief Time Input Capture functions
bogdanm	0:9b334a45a8ff	1467	*
bogdanm	0:9b334a45a8ff	1468	@verbatim
bogdanm	0:9b334a45a8ff	1469	==============================================================================
bogdanm	0:9b334a45a8ff	1470	##### Time Input Capture functions #####
bogdanm	0:9b334a45a8ff	1471	==============================================================================
bogdanm	0:9b334a45a8ff	1472	[..]
bogdanm	0:9b334a45a8ff	1473	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1474	(+) Initialize and configure the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1475	(+) De-initialize the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1476	(+) Start the Time Input Capture.
bogdanm	0:9b334a45a8ff	1477	(+) Stop the Time Input Capture.
bogdanm	0:9b334a45a8ff	1478	(+) Start the Time Input Capture and enable interrupt.
bogdanm	0:9b334a45a8ff	1479	(+) Stop the Time Input Capture and disable interrupt.
bogdanm	0:9b334a45a8ff	1480	(+) Start the Time Input Capture and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1481	(+) Stop the Time Input Capture and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1482
bogdanm	0:9b334a45a8ff	1483	@endverbatim
bogdanm	0:9b334a45a8ff	1484	* @{
bogdanm	0:9b334a45a8ff	1485	*/
bogdanm	0:9b334a45a8ff	1486	/**
bogdanm	0:9b334a45a8ff	1487	* @brief Initializes the TIM Input Capture Time base according to the specified
bogdanm	0:9b334a45a8ff	1488	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1489	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1490	* @retval HAL status
bogdanm	0:9b334a45a8ff	1491	*/
bogdanm	0:9b334a45a8ff	1492	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1493	{
bogdanm	0:9b334a45a8ff	1494	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1495	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1496	{
bogdanm	0:9b334a45a8ff	1497	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1498	}
bogdanm	0:9b334a45a8ff	1499
bogdanm	0:9b334a45a8ff	1500	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1501	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1502	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1503	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1506	{
bogdanm	0:9b334a45a8ff	1507	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	1508	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1509
bogdanm	0:9b334a45a8ff	1510	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1511	HAL_TIM_IC_MspInit(htim);
bogdanm	0:9b334a45a8ff	1512	}
bogdanm	0:9b334a45a8ff	1513
bogdanm	0:9b334a45a8ff	1514	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1515	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1516
bogdanm	0:9b334a45a8ff	1517	/* Init the base time for the input capture */
bogdanm	0:9b334a45a8ff	1518	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1519
bogdanm	0:9b334a45a8ff	1520	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1521	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1522
bogdanm	0:9b334a45a8ff	1523	return HAL_OK;
bogdanm	0:9b334a45a8ff	1524	}
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	/**
bogdanm	0:9b334a45a8ff	1527	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	1528	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1529	* @retval HAL status
bogdanm	0:9b334a45a8ff	1530	*/
bogdanm	0:9b334a45a8ff	1531	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1532	{
bogdanm	0:9b334a45a8ff	1533	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1534	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1535
bogdanm	0:9b334a45a8ff	1536	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1537
bogdanm	0:9b334a45a8ff	1538	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1539	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1542	HAL_TIM_IC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1543
bogdanm	0:9b334a45a8ff	1544	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1545	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	/* Release Lock */
bogdanm	0:9b334a45a8ff	1548	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1549
bogdanm	0:9b334a45a8ff	1550	return HAL_OK;
bogdanm	0:9b334a45a8ff	1551	}
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	/**
bogdanm	0:9b334a45a8ff	1554	* @brief Initializes the TIM Input Capture MSP.
bogdanm	0:9b334a45a8ff	1555	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1556	* @retval None
bogdanm	0:9b334a45a8ff	1557	*/
bogdanm	0:9b334a45a8ff	1558	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1559	{
mbed_official	124:6a4a5b7d7324	1560	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1561	UNUSED(htim);
bogdanm	0:9b334a45a8ff	1562	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1563	the HAL_TIM_IC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1564	*/
bogdanm	0:9b334a45a8ff	1565	}
bogdanm	0:9b334a45a8ff	1566
bogdanm	0:9b334a45a8ff	1567	/**
bogdanm	0:9b334a45a8ff	1568	* @brief DeInitializes TIM Input Capture MSP.
bogdanm	0:9b334a45a8ff	1569	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1570	* @retval None
bogdanm	0:9b334a45a8ff	1571	*/
bogdanm	0:9b334a45a8ff	1572	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1573	{
mbed_official	124:6a4a5b7d7324	1574	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1575	UNUSED(htim);
bogdanm	0:9b334a45a8ff	1576	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1577	the HAL_TIM_IC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1578	*/
bogdanm	0:9b334a45a8ff	1579	}
bogdanm	0:9b334a45a8ff	1580
bogdanm	0:9b334a45a8ff	1581	/**
bogdanm	0:9b334a45a8ff	1582	* @brief Starts the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1583	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1584	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1585	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1586	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1587	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1588	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1589	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1590	* @retval HAL status
bogdanm	0:9b334a45a8ff	1591	*/
bogdanm	0:9b334a45a8ff	1592	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1593	{
bogdanm	0:9b334a45a8ff	1594	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1595	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1596
bogdanm	0:9b334a45a8ff	1597	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1598	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1599
bogdanm	0:9b334a45a8ff	1600	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1601	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/* Return function status */
bogdanm	0:9b334a45a8ff	1604	return HAL_OK;
bogdanm	0:9b334a45a8ff	1605	}
bogdanm	0:9b334a45a8ff	1606
bogdanm	0:9b334a45a8ff	1607	/**
bogdanm	0:9b334a45a8ff	1608	* @brief Stops the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1609	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1610	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1611	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1612	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1613	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1614	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1615	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1616	* @retval HAL status
bogdanm	0:9b334a45a8ff	1617	*/
bogdanm	0:9b334a45a8ff	1618	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1619	{
bogdanm	0:9b334a45a8ff	1620	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1621	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1622
bogdanm	0:9b334a45a8ff	1623	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1624	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1625
bogdanm	0:9b334a45a8ff	1626	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1627	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1628
bogdanm	0:9b334a45a8ff	1629	/* Return function status */
bogdanm	0:9b334a45a8ff	1630	return HAL_OK;
bogdanm	0:9b334a45a8ff	1631	}
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633	/**
bogdanm	0:9b334a45a8ff	1634	* @brief Starts the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1635	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1636	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1637	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1638	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1639	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1640	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1641	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1642	* @retval HAL status
bogdanm	0:9b334a45a8ff	1643	*/
bogdanm	0:9b334a45a8ff	1644	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1645	{
bogdanm	0:9b334a45a8ff	1646	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1647	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	switch (Channel)
bogdanm	0:9b334a45a8ff	1650	{
bogdanm	0:9b334a45a8ff	1651	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1652	{
bogdanm	0:9b334a45a8ff	1653	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1654	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1655	}
bogdanm	0:9b334a45a8ff	1656	break;
bogdanm	0:9b334a45a8ff	1657
bogdanm	0:9b334a45a8ff	1658	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1659	{
bogdanm	0:9b334a45a8ff	1660	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1661	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1662	}
bogdanm	0:9b334a45a8ff	1663	break;
bogdanm	0:9b334a45a8ff	1664
bogdanm	0:9b334a45a8ff	1665	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1666	{
bogdanm	0:9b334a45a8ff	1667	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1668	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1669	}
bogdanm	0:9b334a45a8ff	1670	break;
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1673	{
bogdanm	0:9b334a45a8ff	1674	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1675	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1676	}
bogdanm	0:9b334a45a8ff	1677	break;
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	default:
bogdanm	0:9b334a45a8ff	1680	break;
bogdanm	0:9b334a45a8ff	1681	}
bogdanm	0:9b334a45a8ff	1682	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1683	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1684
bogdanm	0:9b334a45a8ff	1685	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1686	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1687
bogdanm	0:9b334a45a8ff	1688	/* Return function status */
bogdanm	0:9b334a45a8ff	1689	return HAL_OK;
bogdanm	0:9b334a45a8ff	1690	}
bogdanm	0:9b334a45a8ff	1691
bogdanm	0:9b334a45a8ff	1692	/**
bogdanm	0:9b334a45a8ff	1693	* @brief Stops the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1694	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1695	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1696	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1697	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1698	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1699	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1700	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1701	* @retval HAL status
bogdanm	0:9b334a45a8ff	1702	*/
bogdanm	0:9b334a45a8ff	1703	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1704	{
bogdanm	0:9b334a45a8ff	1705	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1706	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1707
bogdanm	0:9b334a45a8ff	1708	switch (Channel)
bogdanm	0:9b334a45a8ff	1709	{
bogdanm	0:9b334a45a8ff	1710	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1711	{
bogdanm	0:9b334a45a8ff	1712	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1713	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1714	}
bogdanm	0:9b334a45a8ff	1715	break;
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1718	{
bogdanm	0:9b334a45a8ff	1719	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1720	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1721	}
bogdanm	0:9b334a45a8ff	1722	break;
bogdanm	0:9b334a45a8ff	1723
bogdanm	0:9b334a45a8ff	1724	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1725	{
bogdanm	0:9b334a45a8ff	1726	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1727	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1728	}
bogdanm	0:9b334a45a8ff	1729	break;
bogdanm	0:9b334a45a8ff	1730
bogdanm	0:9b334a45a8ff	1731	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1732	{
bogdanm	0:9b334a45a8ff	1733	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1734	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1735	}
bogdanm	0:9b334a45a8ff	1736	break;
bogdanm	0:9b334a45a8ff	1737
bogdanm	0:9b334a45a8ff	1738	default:
bogdanm	0:9b334a45a8ff	1739	break;
bogdanm	0:9b334a45a8ff	1740	}
bogdanm	0:9b334a45a8ff	1741
bogdanm	0:9b334a45a8ff	1742	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1743	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1744
bogdanm	0:9b334a45a8ff	1745	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1746	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1747
bogdanm	0:9b334a45a8ff	1748	/* Return function status */
bogdanm	0:9b334a45a8ff	1749	return HAL_OK;
bogdanm	0:9b334a45a8ff	1750	}
bogdanm	0:9b334a45a8ff	1751
bogdanm	0:9b334a45a8ff	1752	/**
bogdanm	0:9b334a45a8ff	1753	* @brief Starts the TIM Input Capture measurement in DMA mode.
bogdanm	0:9b334a45a8ff	1754	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1755	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1756	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1757	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1758	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1759	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1760	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1761	* @param pData : The destination Buffer address.
bogdanm	0:9b334a45a8ff	1762	* @param Length : The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	1763	* @retval HAL status
bogdanm	0:9b334a45a8ff	1764	*/
bogdanm	0:9b334a45a8ff	1765	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1766	{
bogdanm	0:9b334a45a8ff	1767	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1768	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1769	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1772	{
bogdanm	0:9b334a45a8ff	1773	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1774	}
bogdanm	0:9b334a45a8ff	1775	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1776	{
bogdanm	0:9b334a45a8ff	1777	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1778	{
bogdanm	0:9b334a45a8ff	1779	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1780	}
bogdanm	0:9b334a45a8ff	1781	else
bogdanm	0:9b334a45a8ff	1782	{
bogdanm	0:9b334a45a8ff	1783	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1784	}
bogdanm	0:9b334a45a8ff	1785	}
bogdanm	0:9b334a45a8ff	1786
bogdanm	0:9b334a45a8ff	1787	switch (Channel)
bogdanm	0:9b334a45a8ff	1788	{
bogdanm	0:9b334a45a8ff	1789	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1790	{
bogdanm	0:9b334a45a8ff	1791	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1792	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1795	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1798	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1799
bogdanm	0:9b334a45a8ff	1800	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1801	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1802	}
bogdanm	0:9b334a45a8ff	1803	break;
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1806	{
bogdanm	0:9b334a45a8ff	1807	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1808	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1809
bogdanm	0:9b334a45a8ff	1810	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1811	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1812
bogdanm	0:9b334a45a8ff	1813	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1814	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1815
bogdanm	0:9b334a45a8ff	1816	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1817	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1818	}
bogdanm	0:9b334a45a8ff	1819	break;
bogdanm	0:9b334a45a8ff	1820
bogdanm	0:9b334a45a8ff	1821	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1822	{
bogdanm	0:9b334a45a8ff	1823	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1824	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1825
bogdanm	0:9b334a45a8ff	1826	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1827	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1828
bogdanm	0:9b334a45a8ff	1829	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1830	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1831
bogdanm	0:9b334a45a8ff	1832	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1833	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1834	}
bogdanm	0:9b334a45a8ff	1835	break;
bogdanm	0:9b334a45a8ff	1836
bogdanm	0:9b334a45a8ff	1837	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1838	{
bogdanm	0:9b334a45a8ff	1839	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1840	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1841
bogdanm	0:9b334a45a8ff	1842	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1843	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1844
bogdanm	0:9b334a45a8ff	1845	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1846	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1847
bogdanm	0:9b334a45a8ff	1848	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1849	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1850	}
bogdanm	0:9b334a45a8ff	1851	break;
bogdanm	0:9b334a45a8ff	1852
bogdanm	0:9b334a45a8ff	1853	default:
bogdanm	0:9b334a45a8ff	1854	break;
bogdanm	0:9b334a45a8ff	1855	}
bogdanm	0:9b334a45a8ff	1856
bogdanm	0:9b334a45a8ff	1857	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1858	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1859
bogdanm	0:9b334a45a8ff	1860	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1861	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1862
bogdanm	0:9b334a45a8ff	1863	/* Return function status */
bogdanm	0:9b334a45a8ff	1864	return HAL_OK;
bogdanm	0:9b334a45a8ff	1865	}
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/**
bogdanm	0:9b334a45a8ff	1868	* @brief Stops the TIM Input Capture measurement in DMA mode.
bogdanm	0:9b334a45a8ff	1869	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1870	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1871	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1872	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1873	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1874	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1875	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1876	* @retval HAL status
bogdanm	0:9b334a45a8ff	1877	*/
bogdanm	0:9b334a45a8ff	1878	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1879	{
bogdanm	0:9b334a45a8ff	1880	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1881	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1882	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1883
bogdanm	0:9b334a45a8ff	1884	switch (Channel)
bogdanm	0:9b334a45a8ff	1885	{
bogdanm	0:9b334a45a8ff	1886	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1887	{
bogdanm	0:9b334a45a8ff	1888	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1889	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1890	}
bogdanm	0:9b334a45a8ff	1891	break;
bogdanm	0:9b334a45a8ff	1892
bogdanm	0:9b334a45a8ff	1893	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1894	{
bogdanm	0:9b334a45a8ff	1895	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1896	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1897	}
bogdanm	0:9b334a45a8ff	1898	break;
bogdanm	0:9b334a45a8ff	1899
bogdanm	0:9b334a45a8ff	1900	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1901	{
bogdanm	0:9b334a45a8ff	1902	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1903	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1904	}
bogdanm	0:9b334a45a8ff	1905	break;
bogdanm	0:9b334a45a8ff	1906
bogdanm	0:9b334a45a8ff	1907	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1908	{
bogdanm	0:9b334a45a8ff	1909	/* Disable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1910	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1911	}
bogdanm	0:9b334a45a8ff	1912	break;
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	default:
bogdanm	0:9b334a45a8ff	1915	break;
bogdanm	0:9b334a45a8ff	1916	}
bogdanm	0:9b334a45a8ff	1917
bogdanm	0:9b334a45a8ff	1918	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1919	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1920
bogdanm	0:9b334a45a8ff	1921	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1922	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1923
bogdanm	0:9b334a45a8ff	1924	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1925	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1926
bogdanm	0:9b334a45a8ff	1927	/* Return function status */
bogdanm	0:9b334a45a8ff	1928	return HAL_OK;
bogdanm	0:9b334a45a8ff	1929	}
bogdanm	0:9b334a45a8ff	1930	/**
bogdanm	0:9b334a45a8ff	1931	* @}
bogdanm	0:9b334a45a8ff	1932	*/
bogdanm	0:9b334a45a8ff	1933
bogdanm	0:9b334a45a8ff	1934	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm	0:9b334a45a8ff	1935	* @brief Time One Pulse functions
bogdanm	0:9b334a45a8ff	1936	*
bogdanm	0:9b334a45a8ff	1937	@verbatim
bogdanm	0:9b334a45a8ff	1938	==============================================================================
bogdanm	0:9b334a45a8ff	1939	##### Time One Pulse functions #####
bogdanm	0:9b334a45a8ff	1940	==============================================================================
bogdanm	0:9b334a45a8ff	1941	[..]
bogdanm	0:9b334a45a8ff	1942	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1943	(+) Initialize and configure the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1944	(+) De-initialize the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1945	(+) Start the Time One Pulse.
bogdanm	0:9b334a45a8ff	1946	(+) Stop the Time One Pulse.
bogdanm	0:9b334a45a8ff	1947	(+) Start the Time One Pulse and enable interrupt.
bogdanm	0:9b334a45a8ff	1948	(+) Stop the Time One Pulse and disable interrupt.
bogdanm	0:9b334a45a8ff	1949	(+) Start the Time One Pulse and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1950	(+) Stop the Time One Pulse and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1951
bogdanm	0:9b334a45a8ff	1952	@endverbatim
bogdanm	0:9b334a45a8ff	1953	* @{
bogdanm	0:9b334a45a8ff	1954	*/
bogdanm	0:9b334a45a8ff	1955	/**
bogdanm	0:9b334a45a8ff	1956	* @brief Initializes the TIM One Pulse Time Base according to the specified
bogdanm	0:9b334a45a8ff	1957	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1958	* @param htim : TIM OnePulse handle
bogdanm	0:9b334a45a8ff	1959	* @param OnePulseMode : Select the One pulse mode.
bogdanm	0:9b334a45a8ff	1960	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1961	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
bogdanm	0:9b334a45a8ff	1962	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
bogdanm	0:9b334a45a8ff	1963	* @retval HAL status
bogdanm	0:9b334a45a8ff	1964	*/
bogdanm	0:9b334a45a8ff	1965	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
bogdanm	0:9b334a45a8ff	1966	{
bogdanm	0:9b334a45a8ff	1967	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1968	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1969	{
bogdanm	0:9b334a45a8ff	1970	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1971	}
bogdanm	0:9b334a45a8ff	1972
bogdanm	0:9b334a45a8ff	1973	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1974	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1975	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1976	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1977	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
bogdanm	0:9b334a45a8ff	1978
bogdanm	0:9b334a45a8ff	1979	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1980	{
bogdanm	0:9b334a45a8ff	1981	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	1982	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1985	HAL_TIM_OnePulse_MspInit(htim);
bogdanm	0:9b334a45a8ff	1986	}
bogdanm	0:9b334a45a8ff	1987
bogdanm	0:9b334a45a8ff	1988	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1989	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1990
bogdanm	0:9b334a45a8ff	1991	/* Configure the Time base in the One Pulse Mode */
bogdanm	0:9b334a45a8ff	1992	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	/* Reset the OPM Bit */
bogdanm	0:9b334a45a8ff	1995	htim->Instance->CR1 &= ~TIM_CR1_OPM;
bogdanm	0:9b334a45a8ff	1996
bogdanm	0:9b334a45a8ff	1997	/* Configure the OPM Mode */
bogdanm	0:9b334a45a8ff	1998	htim->Instance->CR1 \|= OnePulseMode;
bogdanm	0:9b334a45a8ff	1999
bogdanm	0:9b334a45a8ff	2000	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2001	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2002
bogdanm	0:9b334a45a8ff	2003	return HAL_OK;
bogdanm	0:9b334a45a8ff	2004	}
bogdanm	0:9b334a45a8ff	2005
bogdanm	0:9b334a45a8ff	2006	/**
bogdanm	0:9b334a45a8ff	2007	* @brief DeInitializes the TIM One Pulse
bogdanm	0:9b334a45a8ff	2008	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2009	* @retval HAL status
bogdanm	0:9b334a45a8ff	2010	*/
bogdanm	0:9b334a45a8ff	2011	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2012	{
bogdanm	0:9b334a45a8ff	2013	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2014	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2015
bogdanm	0:9b334a45a8ff	2016	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2017
bogdanm	0:9b334a45a8ff	2018	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2019	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2020
bogdanm	0:9b334a45a8ff	2021	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2022	HAL_TIM_OnePulse_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2023
bogdanm	0:9b334a45a8ff	2024	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2025	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2026
bogdanm	0:9b334a45a8ff	2027	/* Release Lock */
bogdanm	0:9b334a45a8ff	2028	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2029
bogdanm	0:9b334a45a8ff	2030	return HAL_OK;
bogdanm	0:9b334a45a8ff	2031	}
bogdanm	0:9b334a45a8ff	2032
bogdanm	0:9b334a45a8ff	2033	/**
bogdanm	0:9b334a45a8ff	2034	* @brief Initializes the TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2035	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2036	* @retval None
bogdanm	0:9b334a45a8ff	2037	*/
bogdanm	0:9b334a45a8ff	2038	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2039	{
mbed_official	124:6a4a5b7d7324	2040	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	2041	UNUSED(htim);
bogdanm	0:9b334a45a8ff	2042	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2043	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2044	*/
bogdanm	0:9b334a45a8ff	2045	}
bogdanm	0:9b334a45a8ff	2046
bogdanm	0:9b334a45a8ff	2047	/**
bogdanm	0:9b334a45a8ff	2048	* @brief DeInitializes TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2049	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2050	* @retval None
bogdanm	0:9b334a45a8ff	2051	*/
bogdanm	0:9b334a45a8ff	2052	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2053	{
mbed_official	124:6a4a5b7d7324	2054	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	2055	UNUSED(htim);
bogdanm	0:9b334a45a8ff	2056	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2057	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2058	*/
bogdanm	0:9b334a45a8ff	2059	}
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	/**
bogdanm	0:9b334a45a8ff	2062	* @brief Starts the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2063	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2064	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2065	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2066	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2067	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2068	* @retval HAL status
bogdanm	0:9b334a45a8ff	2069	*/
bogdanm	0:9b334a45a8ff	2070	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2071	{
bogdanm	0:9b334a45a8ff	2072	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2073	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2074	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2075	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2076	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2077
bogdanm	0:9b334a45a8ff	2078	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2079	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2080
bogdanm	0:9b334a45a8ff	2081	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2082	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2083
bogdanm	0:9b334a45a8ff	2084	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2085	{
bogdanm	0:9b334a45a8ff	2086	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2087	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2088	}
bogdanm	0:9b334a45a8ff	2089
bogdanm	0:9b334a45a8ff	2090	/* Return function status */
bogdanm	0:9b334a45a8ff	2091	return HAL_OK;
bogdanm	0:9b334a45a8ff	2092	}
bogdanm	0:9b334a45a8ff	2093
bogdanm	0:9b334a45a8ff	2094	/**
bogdanm	0:9b334a45a8ff	2095	* @brief Stops the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2096	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2097	* @param OutputChannel : TIM Channels to be disable
bogdanm	0:9b334a45a8ff	2098	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2099	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2100	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2101	* @retval HAL status
bogdanm	0:9b334a45a8ff	2102	*/
bogdanm	0:9b334a45a8ff	2103	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2104	{
bogdanm	0:9b334a45a8ff	2105	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2106	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2107	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2108	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2109	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2110
bogdanm	0:9b334a45a8ff	2111	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2112	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2113
bogdanm	0:9b334a45a8ff	2114	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2115	{
bogdanm	0:9b334a45a8ff	2116	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	2117	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2118	}
bogdanm	0:9b334a45a8ff	2119
bogdanm	0:9b334a45a8ff	2120	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2121	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2122
bogdanm	0:9b334a45a8ff	2123	/* Return function status */
bogdanm	0:9b334a45a8ff	2124	return HAL_OK;
bogdanm	0:9b334a45a8ff	2125	}
bogdanm	0:9b334a45a8ff	2126
bogdanm	0:9b334a45a8ff	2127	/**
bogdanm	0:9b334a45a8ff	2128	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2129	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2130	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2131	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2132	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2133	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2134	* @retval HAL status
bogdanm	0:9b334a45a8ff	2135	*/
bogdanm	0:9b334a45a8ff	2136	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2137	{
bogdanm	0:9b334a45a8ff	2138	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2139	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2140	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2141	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2142	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2143
bogdanm	0:9b334a45a8ff	2144	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2145	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2146
bogdanm	0:9b334a45a8ff	2147	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2148	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2149
bogdanm	0:9b334a45a8ff	2150	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2151	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2152
bogdanm	0:9b334a45a8ff	2153	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2154	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2155
bogdanm	0:9b334a45a8ff	2156	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2157	{
bogdanm	0:9b334a45a8ff	2158	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2159	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2160	}
bogdanm	0:9b334a45a8ff	2161
bogdanm	0:9b334a45a8ff	2162	/* Return function status */
bogdanm	0:9b334a45a8ff	2163	return HAL_OK;
bogdanm	0:9b334a45a8ff	2164	}
bogdanm	0:9b334a45a8ff	2165
bogdanm	0:9b334a45a8ff	2166	/**
bogdanm	0:9b334a45a8ff	2167	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2168	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2169	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2170	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2171	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2172	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2173	* @retval HAL status
bogdanm	0:9b334a45a8ff	2174	*/
bogdanm	0:9b334a45a8ff	2175	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2176	{
bogdanm	0:9b334a45a8ff	2177	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2178	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2179
bogdanm	0:9b334a45a8ff	2180	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2181	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2182
bogdanm	0:9b334a45a8ff	2183	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2184	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2185	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2186	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2187	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2188	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2189	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2190
bogdanm	0:9b334a45a8ff	2191	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2192	{
bogdanm	0:9b334a45a8ff	2193	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	2194	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2195	}
bogdanm	0:9b334a45a8ff	2196
bogdanm	0:9b334a45a8ff	2197	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2198	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2199
bogdanm	0:9b334a45a8ff	2200	/* Return function status */
bogdanm	0:9b334a45a8ff	2201	return HAL_OK;
bogdanm	0:9b334a45a8ff	2202	}
bogdanm	0:9b334a45a8ff	2203
bogdanm	0:9b334a45a8ff	2204	/**
bogdanm	0:9b334a45a8ff	2205	* @}
bogdanm	0:9b334a45a8ff	2206	*/
bogdanm	0:9b334a45a8ff	2207
bogdanm	0:9b334a45a8ff	2208	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm	0:9b334a45a8ff	2209	* @brief Time Encoder functions
bogdanm	0:9b334a45a8ff	2210	*
bogdanm	0:9b334a45a8ff	2211	@verbatim
bogdanm	0:9b334a45a8ff	2212	==============================================================================
bogdanm	0:9b334a45a8ff	2213	##### Time Encoder functions #####
bogdanm	0:9b334a45a8ff	2214	==============================================================================
bogdanm	0:9b334a45a8ff	2215	[..]
bogdanm	0:9b334a45a8ff	2216	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2217	(+) Initialize and configure the TIM Encoder.
bogdanm	0:9b334a45a8ff	2218	(+) De-initialize the TIM Encoder.
bogdanm	0:9b334a45a8ff	2219	(+) Start the Time Encoder.
bogdanm	0:9b334a45a8ff	2220	(+) Stop the Time Encoder.
bogdanm	0:9b334a45a8ff	2221	(+) Start the Time Encoder and enable interrupt.
bogdanm	0:9b334a45a8ff	2222	(+) Stop the Time Encoder and disable interrupt.
bogdanm	0:9b334a45a8ff	2223	(+) Start the Time Encoder and enable DMA transfer.
bogdanm	0:9b334a45a8ff	2224	(+) Stop the Time Encoder and disable DMA transfer.
bogdanm	0:9b334a45a8ff	2225
bogdanm	0:9b334a45a8ff	2226	@endverbatim
bogdanm	0:9b334a45a8ff	2227	* @{
bogdanm	0:9b334a45a8ff	2228	*/
bogdanm	0:9b334a45a8ff	2229	/**
bogdanm	0:9b334a45a8ff	2230	* @brief Initializes the TIM Encoder Interface and create the associated handle.
bogdanm	0:9b334a45a8ff	2231	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2232	* @param sConfig : TIM Encoder Interface configuration structure
bogdanm	0:9b334a45a8ff	2233	* @retval HAL status
bogdanm	0:9b334a45a8ff	2234	*/
bogdanm	0:9b334a45a8ff	2235	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
bogdanm	0:9b334a45a8ff	2236	{
bogdanm	0:9b334a45a8ff	2237	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	2238	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	2239	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	2240
bogdanm	0:9b334a45a8ff	2241	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	2242	if(htim == NULL)
bogdanm	0:9b334a45a8ff	2243	{
bogdanm	0:9b334a45a8ff	2244	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2245	}
bogdanm	0:9b334a45a8ff	2246
bogdanm	0:9b334a45a8ff	2247	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2248	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2249	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
bogdanm	0:9b334a45a8ff	2250	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
bogdanm	0:9b334a45a8ff	2251	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
bogdanm	0:9b334a45a8ff	2252	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm	0:9b334a45a8ff	2253	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
bogdanm	0:9b334a45a8ff	2254	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm	0:9b334a45a8ff	2255	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
bogdanm	0:9b334a45a8ff	2256	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm	0:9b334a45a8ff	2257	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
bogdanm	0:9b334a45a8ff	2258
bogdanm	0:9b334a45a8ff	2259	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	2260	{
bogdanm	0:9b334a45a8ff	2261	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	2262	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	2263
bogdanm	0:9b334a45a8ff	2264	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	2265	HAL_TIM_Encoder_MspInit(htim);
bogdanm	0:9b334a45a8ff	2266	}
bogdanm	0:9b334a45a8ff	2267
bogdanm	0:9b334a45a8ff	2268	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	2269	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2270
bogdanm	0:9b334a45a8ff	2271	/* Reset the SMS bits */
bogdanm	0:9b334a45a8ff	2272	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	2273
bogdanm	0:9b334a45a8ff	2274	/* Configure the Time base in the Encoder Mode */
bogdanm	0:9b334a45a8ff	2275	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	2276
bogdanm	0:9b334a45a8ff	2277	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	2278	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	2279
bogdanm	0:9b334a45a8ff	2280	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	2281	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	2282
bogdanm	0:9b334a45a8ff	2283	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	2284	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	2285
bogdanm	0:9b334a45a8ff	2286	/* Set the encoder Mode */
bogdanm	0:9b334a45a8ff	2287	tmpsmcr \|= sConfig->EncoderMode;
bogdanm	0:9b334a45a8ff	2288
bogdanm	0:9b334a45a8ff	2289	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
bogdanm	0:9b334a45a8ff	2290	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
bogdanm	0:9b334a45a8ff	2291	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
bogdanm	0:9b334a45a8ff	2292
bogdanm	0:9b334a45a8ff	2293	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
bogdanm	0:9b334a45a8ff	2294	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
bogdanm	0:9b334a45a8ff	2295	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	2296	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
bogdanm	0:9b334a45a8ff	2297	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
bogdanm	0:9b334a45a8ff	2298
bogdanm	0:9b334a45a8ff	2299	/* Set the TI1 and the TI2 Polarities */
bogdanm	0:9b334a45a8ff	2300	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
bogdanm	0:9b334a45a8ff	2301	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	2302	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
bogdanm	0:9b334a45a8ff	2303
bogdanm	0:9b334a45a8ff	2304	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	2305	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	2306
bogdanm	0:9b334a45a8ff	2307	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	2308	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	2309
bogdanm	0:9b334a45a8ff	2310	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	2311	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	2312
bogdanm	0:9b334a45a8ff	2313	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2314	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2315
bogdanm	0:9b334a45a8ff	2316	return HAL_OK;
bogdanm	0:9b334a45a8ff	2317	}
bogdanm	0:9b334a45a8ff	2318
bogdanm	0:9b334a45a8ff	2319
bogdanm	0:9b334a45a8ff	2320	/**
bogdanm	0:9b334a45a8ff	2321	* @brief DeInitializes the TIM Encoder interface
bogdanm	0:9b334a45a8ff	2322	* @param htim : TIM Encoder handle
bogdanm	0:9b334a45a8ff	2323	* @retval HAL status
bogdanm	0:9b334a45a8ff	2324	*/
bogdanm	0:9b334a45a8ff	2325	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2326	{
bogdanm	0:9b334a45a8ff	2327	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2328	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2329
bogdanm	0:9b334a45a8ff	2330	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2331
bogdanm	0:9b334a45a8ff	2332	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2333	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2334
bogdanm	0:9b334a45a8ff	2335	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2336	HAL_TIM_Encoder_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2337
bogdanm	0:9b334a45a8ff	2338	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2339	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2340
bogdanm	0:9b334a45a8ff	2341	/* Release Lock */
bogdanm	0:9b334a45a8ff	2342	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2343
bogdanm	0:9b334a45a8ff	2344	return HAL_OK;
bogdanm	0:9b334a45a8ff	2345	}
bogdanm	0:9b334a45a8ff	2346
bogdanm	0:9b334a45a8ff	2347	/**
bogdanm	0:9b334a45a8ff	2348	* @brief Initializes the TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2349	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2350	* @retval None
bogdanm	0:9b334a45a8ff	2351	*/
bogdanm	0:9b334a45a8ff	2352	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2353	{
mbed_official	124:6a4a5b7d7324	2354	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	2355	UNUSED(htim);
bogdanm	0:9b334a45a8ff	2356	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2357	the HAL_TIM_Encoder_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2358	*/
bogdanm	0:9b334a45a8ff	2359	}
bogdanm	0:9b334a45a8ff	2360
bogdanm	0:9b334a45a8ff	2361	/**
bogdanm	0:9b334a45a8ff	2362	* @brief DeInitializes TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2363	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2364	* @retval None
bogdanm	0:9b334a45a8ff	2365	*/
bogdanm	0:9b334a45a8ff	2366	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2367	{
mbed_official	124:6a4a5b7d7324	2368	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	2369	UNUSED(htim);
bogdanm	0:9b334a45a8ff	2370	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2371	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2372	*/
bogdanm	0:9b334a45a8ff	2373	}
bogdanm	0:9b334a45a8ff	2374
bogdanm	0:9b334a45a8ff	2375	/**
bogdanm	0:9b334a45a8ff	2376	* @brief Starts the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2377	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2378	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2379	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2380	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2381	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2382	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2383	* @retval HAL status
bogdanm	0:9b334a45a8ff	2384	*/
bogdanm	0:9b334a45a8ff	2385	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2386	{
bogdanm	0:9b334a45a8ff	2387	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2388	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2389
bogdanm	0:9b334a45a8ff	2390	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2391	switch (Channel)
bogdanm	0:9b334a45a8ff	2392	{
bogdanm	0:9b334a45a8ff	2393	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2394	{
bogdanm	0:9b334a45a8ff	2395	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2396	break;
bogdanm	0:9b334a45a8ff	2397	}
bogdanm	0:9b334a45a8ff	2398	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2399	{
bogdanm	0:9b334a45a8ff	2400	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2401	break;
bogdanm	0:9b334a45a8ff	2402	}
bogdanm	0:9b334a45a8ff	2403	default :
bogdanm	0:9b334a45a8ff	2404	{
bogdanm	0:9b334a45a8ff	2405	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2406	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2407	break;
bogdanm	0:9b334a45a8ff	2408	}
bogdanm	0:9b334a45a8ff	2409	}
bogdanm	0:9b334a45a8ff	2410	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2411	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2412
bogdanm	0:9b334a45a8ff	2413	/* Return function status */
bogdanm	0:9b334a45a8ff	2414	return HAL_OK;
bogdanm	0:9b334a45a8ff	2415	}
bogdanm	0:9b334a45a8ff	2416
bogdanm	0:9b334a45a8ff	2417	/**
bogdanm	0:9b334a45a8ff	2418	* @brief Stops the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2419	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2420	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	2421	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2422	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2423	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2424	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2425	* @retval HAL status
bogdanm	0:9b334a45a8ff	2426	*/
bogdanm	0:9b334a45a8ff	2427	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2428	{
bogdanm	0:9b334a45a8ff	2429	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2430	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2431
bogdanm	0:9b334a45a8ff	2432	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2433	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2434	switch (Channel)
bogdanm	0:9b334a45a8ff	2435	{
bogdanm	0:9b334a45a8ff	2436	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2437	{
bogdanm	0:9b334a45a8ff	2438	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2439	break;
bogdanm	0:9b334a45a8ff	2440	}
bogdanm	0:9b334a45a8ff	2441	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2442	{
bogdanm	0:9b334a45a8ff	2443	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2444	break;
bogdanm	0:9b334a45a8ff	2445	}
bogdanm	0:9b334a45a8ff	2446	default :
bogdanm	0:9b334a45a8ff	2447	{
bogdanm	0:9b334a45a8ff	2448	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2449	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2450	break;
bogdanm	0:9b334a45a8ff	2451	}
bogdanm	0:9b334a45a8ff	2452	}
bogdanm	0:9b334a45a8ff	2453
bogdanm	0:9b334a45a8ff	2454	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2455	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2456
bogdanm	0:9b334a45a8ff	2457	/* Return function status */
bogdanm	0:9b334a45a8ff	2458	return HAL_OK;
bogdanm	0:9b334a45a8ff	2459	}
bogdanm	0:9b334a45a8ff	2460
bogdanm	0:9b334a45a8ff	2461	/**
bogdanm	0:9b334a45a8ff	2462	* @brief Starts the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2463	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2464	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2465	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2466	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2467	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2468	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2469	* @retval HAL status
bogdanm	0:9b334a45a8ff	2470	*/
bogdanm	0:9b334a45a8ff	2471	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2472	{
bogdanm	0:9b334a45a8ff	2473	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2474	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2475
bogdanm	0:9b334a45a8ff	2476	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2477	/* Enable the capture compare Interrupts 1 and/or 2 */
bogdanm	0:9b334a45a8ff	2478	switch (Channel)
bogdanm	0:9b334a45a8ff	2479	{
bogdanm	0:9b334a45a8ff	2480	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2481	{
bogdanm	0:9b334a45a8ff	2482	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2483	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2484	break;
bogdanm	0:9b334a45a8ff	2485	}
bogdanm	0:9b334a45a8ff	2486	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2487	{
bogdanm	0:9b334a45a8ff	2488	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2489	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2490	break;
bogdanm	0:9b334a45a8ff	2491	}
bogdanm	0:9b334a45a8ff	2492	default :
bogdanm	0:9b334a45a8ff	2493	{
bogdanm	0:9b334a45a8ff	2494	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2495	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2496	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2497	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2498	break;
bogdanm	0:9b334a45a8ff	2499	}
bogdanm	0:9b334a45a8ff	2500	}
bogdanm	0:9b334a45a8ff	2501
bogdanm	0:9b334a45a8ff	2502	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2503	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2504
bogdanm	0:9b334a45a8ff	2505	/* Return function status */
bogdanm	0:9b334a45a8ff	2506	return HAL_OK;
bogdanm	0:9b334a45a8ff	2507	}
bogdanm	0:9b334a45a8ff	2508
bogdanm	0:9b334a45a8ff	2509	/**
bogdanm	0:9b334a45a8ff	2510	* @brief Stops the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2511	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2512	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	2513	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2514	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2515	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2516	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2517	* @retval HAL status
bogdanm	0:9b334a45a8ff	2518	*/
bogdanm	0:9b334a45a8ff	2519	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2520	{
bogdanm	0:9b334a45a8ff	2521	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2522	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2523
bogdanm	0:9b334a45a8ff	2524	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2525	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2526	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2527	{
bogdanm	0:9b334a45a8ff	2528	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2529
bogdanm	0:9b334a45a8ff	2530	/* Disable the capture compare Interrupts 1 */
bogdanm	0:9b334a45a8ff	2531	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2532	}
bogdanm	0:9b334a45a8ff	2533	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2534	{
bogdanm	0:9b334a45a8ff	2535	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2536
bogdanm	0:9b334a45a8ff	2537	/* Disable the capture compare Interrupts 2 */
bogdanm	0:9b334a45a8ff	2538	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2539	}
bogdanm	0:9b334a45a8ff	2540	else
bogdanm	0:9b334a45a8ff	2541	{
bogdanm	0:9b334a45a8ff	2542	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2543	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2544
bogdanm	0:9b334a45a8ff	2545	/* Disable the capture compare Interrupts 1 and 2 */
bogdanm	0:9b334a45a8ff	2546	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2547	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2548	}
bogdanm	0:9b334a45a8ff	2549
bogdanm	0:9b334a45a8ff	2550	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2551	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2552
bogdanm	0:9b334a45a8ff	2553	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2554	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2555
bogdanm	0:9b334a45a8ff	2556	/* Return function status */
bogdanm	0:9b334a45a8ff	2557	return HAL_OK;
bogdanm	0:9b334a45a8ff	2558	}
bogdanm	0:9b334a45a8ff	2559
bogdanm	0:9b334a45a8ff	2560	/**
bogdanm	0:9b334a45a8ff	2561	* @brief Starts the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2562	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2563	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2564	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2565	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2566	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2567	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2568	* @param pData1 : The destination Buffer address for IC1.
bogdanm	0:9b334a45a8ff	2569	* @param pData2 : The destination Buffer address for IC2.
bogdanm	0:9b334a45a8ff	2570	* @param Length : The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	2571	* @retval HAL status
bogdanm	0:9b334a45a8ff	2572	*/
bogdanm	0:9b334a45a8ff	2573	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
bogdanm	0:9b334a45a8ff	2574	{
bogdanm	0:9b334a45a8ff	2575	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2576	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2577
bogdanm	0:9b334a45a8ff	2578	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	2579	{
bogdanm	0:9b334a45a8ff	2580	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2581	}
bogdanm	0:9b334a45a8ff	2582	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	2583	{
bogdanm	0:9b334a45a8ff	2584	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
bogdanm	0:9b334a45a8ff	2585	{
bogdanm	0:9b334a45a8ff	2586	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2587	}
bogdanm	0:9b334a45a8ff	2588	else
bogdanm	0:9b334a45a8ff	2589	{
bogdanm	0:9b334a45a8ff	2590	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2591	}
bogdanm	0:9b334a45a8ff	2592	}
bogdanm	0:9b334a45a8ff	2593
bogdanm	0:9b334a45a8ff	2594	switch (Channel)
bogdanm	0:9b334a45a8ff	2595	{
bogdanm	0:9b334a45a8ff	2596	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2597	{
bogdanm	0:9b334a45a8ff	2598	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2599	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2600
bogdanm	0:9b334a45a8ff	2601	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2602	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2603
bogdanm	0:9b334a45a8ff	2604	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2605	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
bogdanm	0:9b334a45a8ff	2606
bogdanm	0:9b334a45a8ff	2607	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2608	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2609
bogdanm	0:9b334a45a8ff	2610	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2611	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2612
bogdanm	0:9b334a45a8ff	2613	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2614	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2615	}
bogdanm	0:9b334a45a8ff	2616	break;
bogdanm	0:9b334a45a8ff	2617
bogdanm	0:9b334a45a8ff	2618	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2619	{
bogdanm	0:9b334a45a8ff	2620	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2621	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2622
bogdanm	0:9b334a45a8ff	2623	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2624	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
bogdanm	0:9b334a45a8ff	2625	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2626	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2627
bogdanm	0:9b334a45a8ff	2628	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2629	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2630
bogdanm	0:9b334a45a8ff	2631	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2632	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2633
bogdanm	0:9b334a45a8ff	2634	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2635	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2636	}
bogdanm	0:9b334a45a8ff	2637	break;
bogdanm	0:9b334a45a8ff	2638
bogdanm	0:9b334a45a8ff	2639	case TIM_CHANNEL_ALL:
bogdanm	0:9b334a45a8ff	2640	{
bogdanm	0:9b334a45a8ff	2641	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2642	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2643
bogdanm	0:9b334a45a8ff	2644	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2645	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2646
bogdanm	0:9b334a45a8ff	2647	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2648	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
bogdanm	0:9b334a45a8ff	2649
bogdanm	0:9b334a45a8ff	2650	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2651	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2652
bogdanm	0:9b334a45a8ff	2653	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2654	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2655
bogdanm	0:9b334a45a8ff	2656	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2657	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2658
bogdanm	0:9b334a45a8ff	2659	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2660	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2661
bogdanm	0:9b334a45a8ff	2662	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2663	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2664	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2665
bogdanm	0:9b334a45a8ff	2666	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2667	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2668	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2669	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2670	}
bogdanm	0:9b334a45a8ff	2671	break;
bogdanm	0:9b334a45a8ff	2672
bogdanm	0:9b334a45a8ff	2673	default:
bogdanm	0:9b334a45a8ff	2674	break;
bogdanm	0:9b334a45a8ff	2675	}
bogdanm	0:9b334a45a8ff	2676	/* Return function status */
bogdanm	0:9b334a45a8ff	2677	return HAL_OK;
bogdanm	0:9b334a45a8ff	2678	}
bogdanm	0:9b334a45a8ff	2679
bogdanm	0:9b334a45a8ff	2680	/**
bogdanm	0:9b334a45a8ff	2681	* @brief Stops the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2682	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2683	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2684	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2685	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2686	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2687	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2688	* @retval HAL status
bogdanm	0:9b334a45a8ff	2689	*/
bogdanm	0:9b334a45a8ff	2690	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2691	{
bogdanm	0:9b334a45a8ff	2692	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2693	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2694
bogdanm	0:9b334a45a8ff	2695	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2696	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2697	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2698	{
bogdanm	0:9b334a45a8ff	2699	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2700
bogdanm	0:9b334a45a8ff	2701	/* Disable the capture compare DMA Request 1 */
bogdanm	0:9b334a45a8ff	2702	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2703	}
bogdanm	0:9b334a45a8ff	2704	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2705	{
bogdanm	0:9b334a45a8ff	2706	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2707
bogdanm	0:9b334a45a8ff	2708	/* Disable the capture compare DMA Request 2 */
bogdanm	0:9b334a45a8ff	2709	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2710	}
bogdanm	0:9b334a45a8ff	2711	else
bogdanm	0:9b334a45a8ff	2712	{
bogdanm	0:9b334a45a8ff	2713	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2714	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2715
bogdanm	0:9b334a45a8ff	2716	/* Disable the capture compare DMA Request 1 and 2 */
bogdanm	0:9b334a45a8ff	2717	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2718	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2719	}
bogdanm	0:9b334a45a8ff	2720
bogdanm	0:9b334a45a8ff	2721	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2722	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2723
bogdanm	0:9b334a45a8ff	2724	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2725	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2726
bogdanm	0:9b334a45a8ff	2727	/* Return function status */
bogdanm	0:9b334a45a8ff	2728	return HAL_OK;
bogdanm	0:9b334a45a8ff	2729	}
bogdanm	0:9b334a45a8ff	2730
bogdanm	0:9b334a45a8ff	2731	/**
bogdanm	0:9b334a45a8ff	2732	* @}
bogdanm	0:9b334a45a8ff	2733	*/
bogdanm	0:9b334a45a8ff	2734	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm	0:9b334a45a8ff	2735	* @brief IRQ handler management
bogdanm	0:9b334a45a8ff	2736	*
bogdanm	0:9b334a45a8ff	2737	@verbatim
bogdanm	0:9b334a45a8ff	2738	==============================================================================
bogdanm	0:9b334a45a8ff	2739	##### IRQ handler management #####
bogdanm	0:9b334a45a8ff	2740	==============================================================================
bogdanm	0:9b334a45a8ff	2741	[..]
bogdanm	0:9b334a45a8ff	2742	This section provides Timer IRQ handler function.
bogdanm	0:9b334a45a8ff	2743
bogdanm	0:9b334a45a8ff	2744	@endverbatim
bogdanm	0:9b334a45a8ff	2745	* @{
bogdanm	0:9b334a45a8ff	2746	*/
bogdanm	0:9b334a45a8ff	2747	/**
bogdanm	0:9b334a45a8ff	2748	* @brief This function handles TIM interrupts requests.
bogdanm	0:9b334a45a8ff	2749	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2750	* @retval None
bogdanm	0:9b334a45a8ff	2751	*/
bogdanm	0:9b334a45a8ff	2752	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2753	{
bogdanm	0:9b334a45a8ff	2754	/* Capture compare 1 event */
bogdanm	0:9b334a45a8ff	2755	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
bogdanm	0:9b334a45a8ff	2756	{
bogdanm	0:9b334a45a8ff	2757	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
bogdanm	0:9b334a45a8ff	2758	{
bogdanm	0:9b334a45a8ff	2759	{
bogdanm	0:9b334a45a8ff	2760	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2761	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	2762
bogdanm	0:9b334a45a8ff	2763	/* Input capture event */
bogdanm	0:9b334a45a8ff	2764	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
bogdanm	0:9b334a45a8ff	2765	{
bogdanm	0:9b334a45a8ff	2766	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2767	}
bogdanm	0:9b334a45a8ff	2768	/* Output compare event */
bogdanm	0:9b334a45a8ff	2769	else
bogdanm	0:9b334a45a8ff	2770	{
bogdanm	0:9b334a45a8ff	2771	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2772	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2773	}
bogdanm	0:9b334a45a8ff	2774	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2775	}
bogdanm	0:9b334a45a8ff	2776	}
bogdanm	0:9b334a45a8ff	2777	}
bogdanm	0:9b334a45a8ff	2778	/* Capture compare 2 event */
bogdanm	0:9b334a45a8ff	2779	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
bogdanm	0:9b334a45a8ff	2780	{
bogdanm	0:9b334a45a8ff	2781	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
bogdanm	0:9b334a45a8ff	2782	{
bogdanm	0:9b334a45a8ff	2783	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2784	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	2785	/* Input capture event */
bogdanm	0:9b334a45a8ff	2786	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
bogdanm	0:9b334a45a8ff	2787	{
bogdanm	0:9b334a45a8ff	2788	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2789	}
bogdanm	0:9b334a45a8ff	2790	/* Output compare event */
bogdanm	0:9b334a45a8ff	2791	else
bogdanm	0:9b334a45a8ff	2792	{
bogdanm	0:9b334a45a8ff	2793	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2794	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2795	}
bogdanm	0:9b334a45a8ff	2796	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2797	}
bogdanm	0:9b334a45a8ff	2798	}
bogdanm	0:9b334a45a8ff	2799	/* Capture compare 3 event */
bogdanm	0:9b334a45a8ff	2800	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
bogdanm	0:9b334a45a8ff	2801	{
bogdanm	0:9b334a45a8ff	2802	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
bogdanm	0:9b334a45a8ff	2803	{
bogdanm	0:9b334a45a8ff	2804	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	2805	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	2806	/* Input capture event */
bogdanm	0:9b334a45a8ff	2807	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
bogdanm	0:9b334a45a8ff	2808	{
bogdanm	0:9b334a45a8ff	2809	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2810	}
bogdanm	0:9b334a45a8ff	2811	/* Output compare event */
bogdanm	0:9b334a45a8ff	2812	else
bogdanm	0:9b334a45a8ff	2813	{
bogdanm	0:9b334a45a8ff	2814	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2815	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2816	}
bogdanm	0:9b334a45a8ff	2817	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2818	}
bogdanm	0:9b334a45a8ff	2819	}
bogdanm	0:9b334a45a8ff	2820	/* Capture compare 4 event */
bogdanm	0:9b334a45a8ff	2821	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
bogdanm	0:9b334a45a8ff	2822	{
bogdanm	0:9b334a45a8ff	2823	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
bogdanm	0:9b334a45a8ff	2824	{
bogdanm	0:9b334a45a8ff	2825	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	2826	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	2827	/* Input capture event */
bogdanm	0:9b334a45a8ff	2828	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
bogdanm	0:9b334a45a8ff	2829	{
bogdanm	0:9b334a45a8ff	2830	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2831	}
bogdanm	0:9b334a45a8ff	2832	/* Output compare event */
bogdanm	0:9b334a45a8ff	2833	else
bogdanm	0:9b334a45a8ff	2834	{
bogdanm	0:9b334a45a8ff	2835	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2836	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2837	}
bogdanm	0:9b334a45a8ff	2838	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2839	}
bogdanm	0:9b334a45a8ff	2840	}
bogdanm	0:9b334a45a8ff	2841	/* TIM Update event */
bogdanm	0:9b334a45a8ff	2842	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
bogdanm	0:9b334a45a8ff	2843	{
bogdanm	0:9b334a45a8ff	2844	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
bogdanm	0:9b334a45a8ff	2845	{
bogdanm	0:9b334a45a8ff	2846	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	2847	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2848	}
bogdanm	0:9b334a45a8ff	2849	}
bogdanm	0:9b334a45a8ff	2850	/* TIM Break input event */
bogdanm	0:9b334a45a8ff	2851	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
bogdanm	0:9b334a45a8ff	2852	{
bogdanm	0:9b334a45a8ff	2853	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
bogdanm	0:9b334a45a8ff	2854	{
bogdanm	0:9b334a45a8ff	2855	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	2856	HAL_TIMEx_BreakCallback(htim);
bogdanm	0:9b334a45a8ff	2857	}
bogdanm	0:9b334a45a8ff	2858	}
bogdanm	0:9b334a45a8ff	2859	/* TIM Trigger detection event */
bogdanm	0:9b334a45a8ff	2860	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
bogdanm	0:9b334a45a8ff	2861	{
bogdanm	0:9b334a45a8ff	2862	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
bogdanm	0:9b334a45a8ff	2863	{
bogdanm	0:9b334a45a8ff	2864	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	2865	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	2866	}
bogdanm	0:9b334a45a8ff	2867	}
bogdanm	0:9b334a45a8ff	2868	/* TIM commutation event */
bogdanm	0:9b334a45a8ff	2869	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
bogdanm	0:9b334a45a8ff	2870	{
bogdanm	0:9b334a45a8ff	2871	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
bogdanm	0:9b334a45a8ff	2872	{
bogdanm	0:9b334a45a8ff	2873	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
bogdanm	0:9b334a45a8ff	2874	HAL_TIMEx_CommutationCallback(htim);
bogdanm	0:9b334a45a8ff	2875	}
bogdanm	0:9b334a45a8ff	2876	}
bogdanm	0:9b334a45a8ff	2877	}
bogdanm	0:9b334a45a8ff	2878
bogdanm	0:9b334a45a8ff	2879	/**
bogdanm	0:9b334a45a8ff	2880	* @}
bogdanm	0:9b334a45a8ff	2881	*/
bogdanm	0:9b334a45a8ff	2882
bogdanm	0:9b334a45a8ff	2883	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	0:9b334a45a8ff	2884	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	2885	*
bogdanm	0:9b334a45a8ff	2886	@verbatim
bogdanm	0:9b334a45a8ff	2887	==============================================================================
bogdanm	0:9b334a45a8ff	2888	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	2889	==============================================================================
bogdanm	0:9b334a45a8ff	2890	[..]
bogdanm	0:9b334a45a8ff	2891	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2892	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
bogdanm	0:9b334a45a8ff	2893	(+) Configure External Clock source.
bogdanm	0:9b334a45a8ff	2894	(+) Configure Complementary channels, break features and dead time.
bogdanm	0:9b334a45a8ff	2895	(+) Configure Master and the Slave synchronization.
bogdanm	0:9b334a45a8ff	2896	(+) Configure the DMA Burst Mode.
bogdanm	0:9b334a45a8ff	2897
bogdanm	0:9b334a45a8ff	2898	@endverbatim
bogdanm	0:9b334a45a8ff	2899	* @{
bogdanm	0:9b334a45a8ff	2900	*/
bogdanm	0:9b334a45a8ff	2901
bogdanm	0:9b334a45a8ff	2902	/**
bogdanm	0:9b334a45a8ff	2903	* @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm	0:9b334a45a8ff	2904	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2905	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	2906	* @param sConfig : TIM Output Compare configuration structure
bogdanm	0:9b334a45a8ff	2907	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2908	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2909	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2910	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2911	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2912	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2913	* @retval HAL status
bogdanm	0:9b334a45a8ff	2914	*/
bogdanm	0:9b334a45a8ff	2915	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2916	{
bogdanm	0:9b334a45a8ff	2917	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2918	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	2919	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	2920	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	2921
bogdanm	0:9b334a45a8ff	2922	/* Check input state */
bogdanm	0:9b334a45a8ff	2923	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2924
bogdanm	0:9b334a45a8ff	2925	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2926
bogdanm	0:9b334a45a8ff	2927	switch (Channel)
bogdanm	0:9b334a45a8ff	2928	{
bogdanm	0:9b334a45a8ff	2929	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2930	{
bogdanm	0:9b334a45a8ff	2931	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2932	/* Configure the TIM Channel 1 in Output Compare */
bogdanm	0:9b334a45a8ff	2933	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2934	}
bogdanm	0:9b334a45a8ff	2935	break;
bogdanm	0:9b334a45a8ff	2936
bogdanm	0:9b334a45a8ff	2937	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2938	{
bogdanm	0:9b334a45a8ff	2939	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2940	/* Configure the TIM Channel 2 in Output Compare */
bogdanm	0:9b334a45a8ff	2941	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2942	}
bogdanm	0:9b334a45a8ff	2943	break;
bogdanm	0:9b334a45a8ff	2944
bogdanm	0:9b334a45a8ff	2945	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	2946	{
bogdanm	0:9b334a45a8ff	2947	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2948	/* Configure the TIM Channel 3 in Output Compare */
bogdanm	0:9b334a45a8ff	2949	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2950	}
bogdanm	0:9b334a45a8ff	2951	break;
bogdanm	0:9b334a45a8ff	2952
bogdanm	0:9b334a45a8ff	2953	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	2954	{
bogdanm	0:9b334a45a8ff	2955	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2956	/* Configure the TIM Channel 4 in Output Compare */
bogdanm	0:9b334a45a8ff	2957	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2958	}
bogdanm	0:9b334a45a8ff	2959	break;
bogdanm	0:9b334a45a8ff	2960
bogdanm	0:9b334a45a8ff	2961	default:
bogdanm	0:9b334a45a8ff	2962	break;
bogdanm	0:9b334a45a8ff	2963	}
bogdanm	0:9b334a45a8ff	2964	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2965
bogdanm	0:9b334a45a8ff	2966	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2967
bogdanm	0:9b334a45a8ff	2968	return HAL_OK;
bogdanm	0:9b334a45a8ff	2969	}
bogdanm	0:9b334a45a8ff	2970
bogdanm	0:9b334a45a8ff	2971	/**
bogdanm	0:9b334a45a8ff	2972	* @brief Initializes the TIM Input Capture Channels according to the specified
bogdanm	0:9b334a45a8ff	2973	* parameters in the TIM_IC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2974	* @param htim : TIM IC handle
bogdanm	0:9b334a45a8ff	2975	* @param sConfig : TIM Input Capture configuration structure
bogdanm	0:9b334a45a8ff	2976	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2977	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2978	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2979	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2980	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2981	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2982	* @retval HAL status
bogdanm	0:9b334a45a8ff	2983	*/
bogdanm	0:9b334a45a8ff	2984	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2985	{
bogdanm	0:9b334a45a8ff	2986	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2987	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2988	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
bogdanm	0:9b334a45a8ff	2989	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
bogdanm	0:9b334a45a8ff	2990	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
bogdanm	0:9b334a45a8ff	2991	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
bogdanm	0:9b334a45a8ff	2992
bogdanm	0:9b334a45a8ff	2993	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2994
bogdanm	0:9b334a45a8ff	2995	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2996
bogdanm	0:9b334a45a8ff	2997	if (Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2998	{
bogdanm	0:9b334a45a8ff	2999	/* TI1 Configuration */
bogdanm	0:9b334a45a8ff	3000	TIM_TI1_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3001	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3002	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3003	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3004
bogdanm	0:9b334a45a8ff	3005	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3006	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3007
bogdanm	0:9b334a45a8ff	3008	/* Set the IC1PSC value */
bogdanm	0:9b334a45a8ff	3009	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	3010	}
bogdanm	0:9b334a45a8ff	3011	else if (Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	3012	{
bogdanm	0:9b334a45a8ff	3013	/* TI2 Configuration */
bogdanm	0:9b334a45a8ff	3014	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3015
bogdanm	0:9b334a45a8ff	3016	TIM_TI2_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3017	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3018	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3019	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3020
bogdanm	0:9b334a45a8ff	3021	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3022	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3023
bogdanm	0:9b334a45a8ff	3024	/* Set the IC2PSC value */
bogdanm	0:9b334a45a8ff	3025	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	3026	}
bogdanm	0:9b334a45a8ff	3027	else if (Channel == TIM_CHANNEL_3)
bogdanm	0:9b334a45a8ff	3028	{
bogdanm	0:9b334a45a8ff	3029	/* TI3 Configuration */
bogdanm	0:9b334a45a8ff	3030	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3031
bogdanm	0:9b334a45a8ff	3032	TIM_TI3_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3033	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3034	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3035	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3036
bogdanm	0:9b334a45a8ff	3037	/* Reset the IC3PSC Bits */
bogdanm	0:9b334a45a8ff	3038	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
bogdanm	0:9b334a45a8ff	3039
bogdanm	0:9b334a45a8ff	3040	/* Set the IC3PSC value */
bogdanm	0:9b334a45a8ff	3041	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	3042	}
bogdanm	0:9b334a45a8ff	3043	else
bogdanm	0:9b334a45a8ff	3044	{
bogdanm	0:9b334a45a8ff	3045	/* TI4 Configuration */
bogdanm	0:9b334a45a8ff	3046	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3047
bogdanm	0:9b334a45a8ff	3048	TIM_TI4_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3049	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3050	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3051	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3052
bogdanm	0:9b334a45a8ff	3053	/* Reset the IC4PSC Bits */
bogdanm	0:9b334a45a8ff	3054	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
bogdanm	0:9b334a45a8ff	3055
bogdanm	0:9b334a45a8ff	3056	/* Set the IC4PSC value */
bogdanm	0:9b334a45a8ff	3057	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	3058	}
bogdanm	0:9b334a45a8ff	3059
bogdanm	0:9b334a45a8ff	3060	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3061
bogdanm	0:9b334a45a8ff	3062	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3063
bogdanm	0:9b334a45a8ff	3064	return HAL_OK;
bogdanm	0:9b334a45a8ff	3065	}
bogdanm	0:9b334a45a8ff	3066
bogdanm	0:9b334a45a8ff	3067	/**
bogdanm	0:9b334a45a8ff	3068	* @brief Initializes the TIM PWM channels according to the specified
bogdanm	0:9b334a45a8ff	3069	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	3070	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3071	* @param sConfig : TIM PWM configuration structure
bogdanm	0:9b334a45a8ff	3072	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3073	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3074	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3075	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3076	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3077	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3078	* @retval HAL status
bogdanm	0:9b334a45a8ff	3079	*/
bogdanm	0:9b334a45a8ff	3080	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3081	{
bogdanm	0:9b334a45a8ff	3082	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3083
bogdanm	0:9b334a45a8ff	3084	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3085	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3086	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	3087	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	3088	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm	0:9b334a45a8ff	3089
bogdanm	0:9b334a45a8ff	3090	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3091
bogdanm	0:9b334a45a8ff	3092	switch (Channel)
bogdanm	0:9b334a45a8ff	3093	{
bogdanm	0:9b334a45a8ff	3094	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3095	{
bogdanm	0:9b334a45a8ff	3096	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3097	/* Configure the Channel 1 in PWM mode */
bogdanm	0:9b334a45a8ff	3098	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3099
bogdanm	0:9b334a45a8ff	3100	/* Set the Preload enable bit for channel1 */
bogdanm	0:9b334a45a8ff	3101	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
bogdanm	0:9b334a45a8ff	3102
bogdanm	0:9b334a45a8ff	3103	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3104	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm	0:9b334a45a8ff	3105	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3106	}
bogdanm	0:9b334a45a8ff	3107	break;
bogdanm	0:9b334a45a8ff	3108
bogdanm	0:9b334a45a8ff	3109	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3110	{
bogdanm	0:9b334a45a8ff	3111	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3112	/* Configure the Channel 2 in PWM mode */
bogdanm	0:9b334a45a8ff	3113	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3114
bogdanm	0:9b334a45a8ff	3115	/* Set the Preload enable bit for channel2 */
bogdanm	0:9b334a45a8ff	3116	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
bogdanm	0:9b334a45a8ff	3117
bogdanm	0:9b334a45a8ff	3118	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3119	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm	0:9b334a45a8ff	3120	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3121	}
bogdanm	0:9b334a45a8ff	3122	break;
bogdanm	0:9b334a45a8ff	3123
bogdanm	0:9b334a45a8ff	3124	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3125	{
bogdanm	0:9b334a45a8ff	3126	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3127	/* Configure the Channel 3 in PWM mode */
bogdanm	0:9b334a45a8ff	3128	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3129
bogdanm	0:9b334a45a8ff	3130	/* Set the Preload enable bit for channel3 */
bogdanm	0:9b334a45a8ff	3131	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
bogdanm	0:9b334a45a8ff	3132
bogdanm	0:9b334a45a8ff	3133	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3134	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm	0:9b334a45a8ff	3135	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3136	}
bogdanm	0:9b334a45a8ff	3137	break;
bogdanm	0:9b334a45a8ff	3138
bogdanm	0:9b334a45a8ff	3139	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3140	{
bogdanm	0:9b334a45a8ff	3141	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3142	/* Configure the Channel 4 in PWM mode */
bogdanm	0:9b334a45a8ff	3143	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3144
bogdanm	0:9b334a45a8ff	3145	/* Set the Preload enable bit for channel4 */
bogdanm	0:9b334a45a8ff	3146	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
bogdanm	0:9b334a45a8ff	3147
bogdanm	0:9b334a45a8ff	3148	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3149	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm	0:9b334a45a8ff	3150	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3151	}
bogdanm	0:9b334a45a8ff	3152	break;
bogdanm	0:9b334a45a8ff	3153
bogdanm	0:9b334a45a8ff	3154	default:
bogdanm	0:9b334a45a8ff	3155	break;
bogdanm	0:9b334a45a8ff	3156	}
bogdanm	0:9b334a45a8ff	3157
bogdanm	0:9b334a45a8ff	3158	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3159
bogdanm	0:9b334a45a8ff	3160	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3161
bogdanm	0:9b334a45a8ff	3162	return HAL_OK;
bogdanm	0:9b334a45a8ff	3163	}
bogdanm	0:9b334a45a8ff	3164
bogdanm	0:9b334a45a8ff	3165	/**
bogdanm	0:9b334a45a8ff	3166	* @brief Initializes the TIM One Pulse Channels according to the specified
bogdanm	0:9b334a45a8ff	3167	* parameters in the TIM_OnePulse_InitTypeDef.
bogdanm	0:9b334a45a8ff	3168	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	3169	* @param sConfig : TIM One Pulse configuration structure
bogdanm	0:9b334a45a8ff	3170	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3171	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3172	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3173	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3174	* @param InputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3175	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3176	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3177	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3178	* @retval HAL status
bogdanm	0:9b334a45a8ff	3179	*/
bogdanm	0:9b334a45a8ff	3180	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
bogdanm	0:9b334a45a8ff	3181	{
bogdanm	0:9b334a45a8ff	3182	TIM_OC_InitTypeDef temp1;
bogdanm	0:9b334a45a8ff	3183
bogdanm	0:9b334a45a8ff	3184	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3185	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
bogdanm	0:9b334a45a8ff	3186	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
bogdanm	0:9b334a45a8ff	3187
bogdanm	0:9b334a45a8ff	3188	if(OutputChannel != InputChannel)
bogdanm	0:9b334a45a8ff	3189	{
bogdanm	0:9b334a45a8ff	3190	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3191
bogdanm	0:9b334a45a8ff	3192	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3193
bogdanm	0:9b334a45a8ff	3194	/* Extract the Ouput compare configuration from sConfig structure */
bogdanm	0:9b334a45a8ff	3195	temp1.OCMode = sConfig->OCMode;
bogdanm	0:9b334a45a8ff	3196	temp1.Pulse = sConfig->Pulse;
bogdanm	0:9b334a45a8ff	3197	temp1.OCPolarity = sConfig->OCPolarity;
bogdanm	0:9b334a45a8ff	3198	temp1.OCNPolarity = sConfig->OCNPolarity;
bogdanm	0:9b334a45a8ff	3199	temp1.OCIdleState = sConfig->OCIdleState;
bogdanm	0:9b334a45a8ff	3200	temp1.OCNIdleState = sConfig->OCNIdleState;
bogdanm	0:9b334a45a8ff	3201
bogdanm	0:9b334a45a8ff	3202	switch (OutputChannel)
bogdanm	0:9b334a45a8ff	3203	{
bogdanm	0:9b334a45a8ff	3204	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3205	{
bogdanm	0:9b334a45a8ff	3206	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3207
bogdanm	0:9b334a45a8ff	3208	TIM_OC1_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3209	}
bogdanm	0:9b334a45a8ff	3210	break;
bogdanm	0:9b334a45a8ff	3211	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3212	{
bogdanm	0:9b334a45a8ff	3213	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3214
bogdanm	0:9b334a45a8ff	3215	TIM_OC2_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3216	}
bogdanm	0:9b334a45a8ff	3217	break;
bogdanm	0:9b334a45a8ff	3218	default:
bogdanm	0:9b334a45a8ff	3219	break;
bogdanm	0:9b334a45a8ff	3220	}
bogdanm	0:9b334a45a8ff	3221	switch (InputChannel)
bogdanm	0:9b334a45a8ff	3222	{
bogdanm	0:9b334a45a8ff	3223	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3224	{
bogdanm	0:9b334a45a8ff	3225	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3226
bogdanm	0:9b334a45a8ff	3227	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3228	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3229
bogdanm	0:9b334a45a8ff	3230	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3231	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3232
bogdanm	0:9b334a45a8ff	3233	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3234	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3235	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
bogdanm	0:9b334a45a8ff	3236
bogdanm	0:9b334a45a8ff	3237	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3238	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3239	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3240	}
bogdanm	0:9b334a45a8ff	3241	break;
bogdanm	0:9b334a45a8ff	3242	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3243	{
bogdanm	0:9b334a45a8ff	3244	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3245
bogdanm	0:9b334a45a8ff	3246	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3247	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3248
bogdanm	0:9b334a45a8ff	3249	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3250	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3251
bogdanm	0:9b334a45a8ff	3252	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3253	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3254	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
bogdanm	0:9b334a45a8ff	3255
bogdanm	0:9b334a45a8ff	3256	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3257	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3258	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3259	}
bogdanm	0:9b334a45a8ff	3260	break;
bogdanm	0:9b334a45a8ff	3261
bogdanm	0:9b334a45a8ff	3262	default:
bogdanm	0:9b334a45a8ff	3263	break;
bogdanm	0:9b334a45a8ff	3264	}
bogdanm	0:9b334a45a8ff	3265
bogdanm	0:9b334a45a8ff	3266	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3267
bogdanm	0:9b334a45a8ff	3268	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3269
bogdanm	0:9b334a45a8ff	3270	return HAL_OK;
bogdanm	0:9b334a45a8ff	3271	}
bogdanm	0:9b334a45a8ff	3272	else
bogdanm	0:9b334a45a8ff	3273	{
bogdanm	0:9b334a45a8ff	3274	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3275	}
bogdanm	0:9b334a45a8ff	3276	}
bogdanm	0:9b334a45a8ff	3277
bogdanm	0:9b334a45a8ff	3278	/**
bogdanm	0:9b334a45a8ff	3279	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
bogdanm	0:9b334a45a8ff	3280	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3281	* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
bogdanm	0:9b334a45a8ff	3282	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3283	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3284	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3285	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3286	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3287	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3288	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3289	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3290	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3291	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3292	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3293	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3294	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3295	* @arg TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	3296	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3297	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3298	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3299	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3300	* @arg TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	3301	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3302	* @param BurstRequestSrc : TIM DMA Request sources
bogdanm	0:9b334a45a8ff	3303	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3304	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3305	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3306	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3307	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3308	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3309	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3310	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3311	* @param BurstBuffer : The Buffer address.
bogdanm	0:9b334a45a8ff	3312	* @param BurstLength : DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3313	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
bogdanm	0:9b334a45a8ff	3314	* @retval HAL status
bogdanm	0:9b334a45a8ff	3315	*/
bogdanm	0:9b334a45a8ff	3316	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3317	uint32_t* BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3318	{
bogdanm	0:9b334a45a8ff	3319	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3320	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3321	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3322	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3323	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3324
bogdanm	0:9b334a45a8ff	3325	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3326	{
bogdanm	0:9b334a45a8ff	3327	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3328	}
bogdanm	0:9b334a45a8ff	3329	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3330	{
bogdanm	0:9b334a45a8ff	3331	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3332	{
bogdanm	0:9b334a45a8ff	3333	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3334	}
bogdanm	0:9b334a45a8ff	3335	else
bogdanm	0:9b334a45a8ff	3336	{
bogdanm	0:9b334a45a8ff	3337	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3338	}
bogdanm	0:9b334a45a8ff	3339	}
bogdanm	0:9b334a45a8ff	3340	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3341	{
bogdanm	0:9b334a45a8ff	3342	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3343	{
bogdanm	0:9b334a45a8ff	3344	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3345	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3346
bogdanm	0:9b334a45a8ff	3347	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3348	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3349
bogdanm	0:9b334a45a8ff	3350	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3351	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3352	}
bogdanm	0:9b334a45a8ff	3353	break;
bogdanm	0:9b334a45a8ff	3354	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3355	{
bogdanm	0:9b334a45a8ff	3356	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3357	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3358
bogdanm	0:9b334a45a8ff	3359	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3360	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3361
bogdanm	0:9b334a45a8ff	3362	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3363	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3364	}
bogdanm	0:9b334a45a8ff	3365	break;
bogdanm	0:9b334a45a8ff	3366	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3367	{
bogdanm	0:9b334a45a8ff	3368	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3369	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3370
bogdanm	0:9b334a45a8ff	3371	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3372	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3373
bogdanm	0:9b334a45a8ff	3374	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3375	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3376	}
bogdanm	0:9b334a45a8ff	3377	break;
bogdanm	0:9b334a45a8ff	3378	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3379	{
bogdanm	0:9b334a45a8ff	3380	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3381	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3382
bogdanm	0:9b334a45a8ff	3383	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3384	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3385
bogdanm	0:9b334a45a8ff	3386	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3387	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3388	}
bogdanm	0:9b334a45a8ff	3389	break;
bogdanm	0:9b334a45a8ff	3390	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3391	{
bogdanm	0:9b334a45a8ff	3392	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3393	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3394
bogdanm	0:9b334a45a8ff	3395	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3396	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3397
bogdanm	0:9b334a45a8ff	3398	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3399	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3400	}
bogdanm	0:9b334a45a8ff	3401	break;
bogdanm	0:9b334a45a8ff	3402	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3403	{
bogdanm	0:9b334a45a8ff	3404	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3405	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3406
bogdanm	0:9b334a45a8ff	3407	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3408	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3409
bogdanm	0:9b334a45a8ff	3410	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3411	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3412	}
bogdanm	0:9b334a45a8ff	3413	break;
bogdanm	0:9b334a45a8ff	3414	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3415	{
bogdanm	0:9b334a45a8ff	3416	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3417	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3418
bogdanm	0:9b334a45a8ff	3419	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3420	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3421
bogdanm	0:9b334a45a8ff	3422	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3423	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3424	}
bogdanm	0:9b334a45a8ff	3425	break;
bogdanm	0:9b334a45a8ff	3426	default:
bogdanm	0:9b334a45a8ff	3427	break;
bogdanm	0:9b334a45a8ff	3428	}
bogdanm	0:9b334a45a8ff	3429	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3430	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3431
bogdanm	0:9b334a45a8ff	3432	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3433	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3434
bogdanm	0:9b334a45a8ff	3435	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3436
bogdanm	0:9b334a45a8ff	3437	/* Return function status */
bogdanm	0:9b334a45a8ff	3438	return HAL_OK;
bogdanm	0:9b334a45a8ff	3439	}
bogdanm	0:9b334a45a8ff	3440
bogdanm	0:9b334a45a8ff	3441	/**
bogdanm	0:9b334a45a8ff	3442	* @brief Stops the TIM DMA Burst mode
bogdanm	0:9b334a45a8ff	3443	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3444	* @param BurstRequestSrc : TIM DMA Request sources to disable
bogdanm	0:9b334a45a8ff	3445	* @retval HAL status
bogdanm	0:9b334a45a8ff	3446	*/
bogdanm	0:9b334a45a8ff	3447	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3448	{
bogdanm	0:9b334a45a8ff	3449	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3450	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3451
bogdanm	0:9b334a45a8ff	3452	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3453	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3454	{
bogdanm	0:9b334a45a8ff	3455	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3456	{
bogdanm	0:9b334a45a8ff	3457	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3458	}
bogdanm	0:9b334a45a8ff	3459	break;
bogdanm	0:9b334a45a8ff	3460	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3461	{
bogdanm	0:9b334a45a8ff	3462	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3463	}
bogdanm	0:9b334a45a8ff	3464	break;
bogdanm	0:9b334a45a8ff	3465	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3466	{
bogdanm	0:9b334a45a8ff	3467	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3468	}
bogdanm	0:9b334a45a8ff	3469	break;
bogdanm	0:9b334a45a8ff	3470	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3471	{
bogdanm	0:9b334a45a8ff	3472	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3473	}
bogdanm	0:9b334a45a8ff	3474	break;
bogdanm	0:9b334a45a8ff	3475	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3476	{
bogdanm	0:9b334a45a8ff	3477	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3478	}
bogdanm	0:9b334a45a8ff	3479	break;
bogdanm	0:9b334a45a8ff	3480	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3481	{
bogdanm	0:9b334a45a8ff	3482	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3483	}
bogdanm	0:9b334a45a8ff	3484	break;
bogdanm	0:9b334a45a8ff	3485	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3486	{
bogdanm	0:9b334a45a8ff	3487	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3488	}
bogdanm	0:9b334a45a8ff	3489	break;
bogdanm	0:9b334a45a8ff	3490	default:
bogdanm	0:9b334a45a8ff	3491	break;
bogdanm	0:9b334a45a8ff	3492	}
bogdanm	0:9b334a45a8ff	3493
bogdanm	0:9b334a45a8ff	3494	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3495	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3496
bogdanm	0:9b334a45a8ff	3497	/* Return function status */
bogdanm	0:9b334a45a8ff	3498	return HAL_OK;
bogdanm	0:9b334a45a8ff	3499	}
bogdanm	0:9b334a45a8ff	3500
bogdanm	0:9b334a45a8ff	3501	/**
bogdanm	0:9b334a45a8ff	3502	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
bogdanm	0:9b334a45a8ff	3503	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3504	* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
bogdanm	0:9b334a45a8ff	3505	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3506	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3507	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3508	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3509	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3510	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3511	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3512	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3513	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3514	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3515	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3516	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3517	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3518	* @arg TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	3519	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3520	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3521	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3522	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3523	* @arg TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	3524	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3525	* @param BurstRequestSrc : TIM DMA Request sources
bogdanm	0:9b334a45a8ff	3526	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3527	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3528	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3529	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3530	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3531	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3532	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3533	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3534	* @param BurstBuffer : The Buffer address.
bogdanm	0:9b334a45a8ff	3535	* @param BurstLength : DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3536	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
bogdanm	0:9b334a45a8ff	3537	* @retval HAL status
bogdanm	0:9b334a45a8ff	3538	*/
bogdanm	0:9b334a45a8ff	3539	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3540	uint32_t *BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3541	{
bogdanm	0:9b334a45a8ff	3542	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3543	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3544	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3545	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3546	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3547
bogdanm	0:9b334a45a8ff	3548	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3549	{
bogdanm	0:9b334a45a8ff	3550	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3551	}
bogdanm	0:9b334a45a8ff	3552	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3553	{
bogdanm	0:9b334a45a8ff	3554	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3555	{
bogdanm	0:9b334a45a8ff	3556	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3557	}
bogdanm	0:9b334a45a8ff	3558	else
bogdanm	0:9b334a45a8ff	3559	{
bogdanm	0:9b334a45a8ff	3560	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3561	}
bogdanm	0:9b334a45a8ff	3562	}
bogdanm	0:9b334a45a8ff	3563	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3564	{
bogdanm	0:9b334a45a8ff	3565	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3566	{
bogdanm	0:9b334a45a8ff	3567	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3568	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3569
bogdanm	0:9b334a45a8ff	3570	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3571	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3572
bogdanm	0:9b334a45a8ff	3573	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3574	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3575	}
bogdanm	0:9b334a45a8ff	3576	break;
bogdanm	0:9b334a45a8ff	3577	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3578	{
bogdanm	0:9b334a45a8ff	3579	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3580	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3581
bogdanm	0:9b334a45a8ff	3582	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3583	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3584
bogdanm	0:9b334a45a8ff	3585	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3586	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3587	}
bogdanm	0:9b334a45a8ff	3588	break;
bogdanm	0:9b334a45a8ff	3589	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3590	{
bogdanm	0:9b334a45a8ff	3591	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3592	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3593
bogdanm	0:9b334a45a8ff	3594	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3595	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3596
bogdanm	0:9b334a45a8ff	3597	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3598	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3599	}
bogdanm	0:9b334a45a8ff	3600	break;
bogdanm	0:9b334a45a8ff	3601	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3602	{
bogdanm	0:9b334a45a8ff	3603	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3604	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3605
bogdanm	0:9b334a45a8ff	3606	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3607	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3608
bogdanm	0:9b334a45a8ff	3609	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3610	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3611	}
bogdanm	0:9b334a45a8ff	3612	break;
bogdanm	0:9b334a45a8ff	3613	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3614	{
bogdanm	0:9b334a45a8ff	3615	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3616	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3617
bogdanm	0:9b334a45a8ff	3618	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3619	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3620
bogdanm	0:9b334a45a8ff	3621	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3622	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3623	}
bogdanm	0:9b334a45a8ff	3624	break;
bogdanm	0:9b334a45a8ff	3625	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3626	{
bogdanm	0:9b334a45a8ff	3627	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3628	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3629
bogdanm	0:9b334a45a8ff	3630	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3631	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3632
bogdanm	0:9b334a45a8ff	3633	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3634	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3635	}
bogdanm	0:9b334a45a8ff	3636	break;
bogdanm	0:9b334a45a8ff	3637	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3638	{
bogdanm	0:9b334a45a8ff	3639	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3640	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3641
bogdanm	0:9b334a45a8ff	3642	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3643	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3644
bogdanm	0:9b334a45a8ff	3645	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3646	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3647	}
bogdanm	0:9b334a45a8ff	3648	break;
bogdanm	0:9b334a45a8ff	3649	default:
bogdanm	0:9b334a45a8ff	3650	break;
bogdanm	0:9b334a45a8ff	3651	}
bogdanm	0:9b334a45a8ff	3652
bogdanm	0:9b334a45a8ff	3653	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3654	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3655
bogdanm	0:9b334a45a8ff	3656	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3657	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3658
bogdanm	0:9b334a45a8ff	3659	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3660
bogdanm	0:9b334a45a8ff	3661	/* Return function status */
bogdanm	0:9b334a45a8ff	3662	return HAL_OK;
bogdanm	0:9b334a45a8ff	3663	}
bogdanm	0:9b334a45a8ff	3664
bogdanm	0:9b334a45a8ff	3665	/**
bogdanm	0:9b334a45a8ff	3666	* @brief Stop the DMA burst reading
bogdanm	0:9b334a45a8ff	3667	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3668	* @param BurstRequestSrc : TIM DMA Request sources to disable.
bogdanm	0:9b334a45a8ff	3669	* @retval HAL status
bogdanm	0:9b334a45a8ff	3670	*/
bogdanm	0:9b334a45a8ff	3671	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3672	{
bogdanm	0:9b334a45a8ff	3673	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3674	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3675
bogdanm	0:9b334a45a8ff	3676	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3677	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3678	{
bogdanm	0:9b334a45a8ff	3679	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3680	{
bogdanm	0:9b334a45a8ff	3681	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3682	}
bogdanm	0:9b334a45a8ff	3683	break;
bogdanm	0:9b334a45a8ff	3684	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3685	{
bogdanm	0:9b334a45a8ff	3686	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3687	}
bogdanm	0:9b334a45a8ff	3688	break;
bogdanm	0:9b334a45a8ff	3689	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3690	{
bogdanm	0:9b334a45a8ff	3691	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3692	}
bogdanm	0:9b334a45a8ff	3693	break;
bogdanm	0:9b334a45a8ff	3694	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3695	{
bogdanm	0:9b334a45a8ff	3696	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3697	}
bogdanm	0:9b334a45a8ff	3698	break;
bogdanm	0:9b334a45a8ff	3699	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3700	{
bogdanm	0:9b334a45a8ff	3701	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3702	}
bogdanm	0:9b334a45a8ff	3703	break;
bogdanm	0:9b334a45a8ff	3704	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3705	{
bogdanm	0:9b334a45a8ff	3706	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3707	}
bogdanm	0:9b334a45a8ff	3708	break;
bogdanm	0:9b334a45a8ff	3709	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3710	{
bogdanm	0:9b334a45a8ff	3711	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3712	}
bogdanm	0:9b334a45a8ff	3713	break;
bogdanm	0:9b334a45a8ff	3714	default:
bogdanm	0:9b334a45a8ff	3715	break;
bogdanm	0:9b334a45a8ff	3716	}
bogdanm	0:9b334a45a8ff	3717
bogdanm	0:9b334a45a8ff	3718	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3719	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3720
bogdanm	0:9b334a45a8ff	3721	/* Return function status */
bogdanm	0:9b334a45a8ff	3722	return HAL_OK;
bogdanm	0:9b334a45a8ff	3723	}
bogdanm	0:9b334a45a8ff	3724
bogdanm	0:9b334a45a8ff	3725	/**
bogdanm	0:9b334a45a8ff	3726	* @brief Generate a software event
bogdanm	0:9b334a45a8ff	3727	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3728	* @param EventSource : specifies the event source.
bogdanm	0:9b334a45a8ff	3729	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3730	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
bogdanm	0:9b334a45a8ff	3731	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
bogdanm	0:9b334a45a8ff	3732	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
bogdanm	0:9b334a45a8ff	3733	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
bogdanm	0:9b334a45a8ff	3734	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
bogdanm	0:9b334a45a8ff	3735	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
bogdanm	0:9b334a45a8ff	3736	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
bogdanm	0:9b334a45a8ff	3737	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
bogdanm	0:9b334a45a8ff	3738	* @note TIM6 and TIM7 can only generate an update event.
bogdanm	0:9b334a45a8ff	3739	* @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
bogdanm	0:9b334a45a8ff	3740	* @retval HAL status
bogdanm	0:9b334a45a8ff	3741	*/
bogdanm	0:9b334a45a8ff	3742
bogdanm	0:9b334a45a8ff	3743	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
bogdanm	0:9b334a45a8ff	3744	{
bogdanm	0:9b334a45a8ff	3745	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3746	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3747	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
bogdanm	0:9b334a45a8ff	3748
bogdanm	0:9b334a45a8ff	3749	/* Process Locked */
bogdanm	0:9b334a45a8ff	3750	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3751
bogdanm	0:9b334a45a8ff	3752	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3753	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3754
bogdanm	0:9b334a45a8ff	3755	/* Set the event sources */
bogdanm	0:9b334a45a8ff	3756	htim->Instance->EGR = EventSource;
bogdanm	0:9b334a45a8ff	3757
bogdanm	0:9b334a45a8ff	3758	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3759	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3760
bogdanm	0:9b334a45a8ff	3761	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3762
bogdanm	0:9b334a45a8ff	3763	/* Return function status */
bogdanm	0:9b334a45a8ff	3764	return HAL_OK;
bogdanm	0:9b334a45a8ff	3765	}
bogdanm	0:9b334a45a8ff	3766
bogdanm	0:9b334a45a8ff	3767	/**
bogdanm	0:9b334a45a8ff	3768	* @brief Configures the OCRef clear feature
bogdanm	0:9b334a45a8ff	3769	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3770	* @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3771	* contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3772	* @param Channel : specifies the TIM Channel
bogdanm	0:9b334a45a8ff	3773	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	3774	* @arg TIM_CHANNEL_1: TIM Channel 1
mbed_official	124:6a4a5b7d7324	3775	* @arg TIM_CHANNEL_2: TIM Channel 2
mbed_official	124:6a4a5b7d7324	3776	* @arg TIM_CHANNEL_3: TIM Channel 3
mbed_official	124:6a4a5b7d7324	3777	* @arg TIM_CHANNEL_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	3778	* @retval HAL status
bogdanm	0:9b334a45a8ff	3779	*/
bogdanm	0:9b334a45a8ff	3780	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3781	{
bogdanm	0:9b334a45a8ff	3782	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	3783
bogdanm	0:9b334a45a8ff	3784	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3785	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3786	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm	0:9b334a45a8ff	3787	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm	0:9b334a45a8ff	3788	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm	0:9b334a45a8ff	3789	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm	0:9b334a45a8ff	3790
bogdanm	0:9b334a45a8ff	3791	/* Process Locked */
bogdanm	0:9b334a45a8ff	3792	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3793
bogdanm	0:9b334a45a8ff	3794	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3795
bogdanm	0:9b334a45a8ff	3796	switch (sClearInputConfig->ClearInputSource)
bogdanm	0:9b334a45a8ff	3797	{
bogdanm	0:9b334a45a8ff	3798	case TIM_CLEARINPUTSOURCE_NONE:
bogdanm	0:9b334a45a8ff	3799	{
bogdanm	0:9b334a45a8ff	3800	/* Clear the OCREF clear selection bit */
bogdanm	0:9b334a45a8ff	3801	tmpsmcr &= ~TIM_SMCR_OCCS;
bogdanm	0:9b334a45a8ff	3802
bogdanm	0:9b334a45a8ff	3803	/* Clear the ETR Bits */
bogdanm	0:9b334a45a8ff	3804	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	3805
bogdanm	0:9b334a45a8ff	3806	/* Set TIMx_SMCR */
bogdanm	0:9b334a45a8ff	3807	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3808	}
bogdanm	0:9b334a45a8ff	3809	break;
bogdanm	0:9b334a45a8ff	3810
bogdanm	0:9b334a45a8ff	3811	case TIM_CLEARINPUTSOURCE_ETR:
bogdanm	0:9b334a45a8ff	3812	{
bogdanm	0:9b334a45a8ff	3813	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3814	sClearInputConfig->ClearInputPrescaler,
bogdanm	0:9b334a45a8ff	3815	sClearInputConfig->ClearInputPolarity,
bogdanm	0:9b334a45a8ff	3816	sClearInputConfig->ClearInputFilter);
bogdanm	0:9b334a45a8ff	3817
bogdanm	0:9b334a45a8ff	3818	/* Set the OCREF clear selection bit */
bogdanm	0:9b334a45a8ff	3819	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
bogdanm	0:9b334a45a8ff	3820	}
bogdanm	0:9b334a45a8ff	3821	break;
bogdanm	0:9b334a45a8ff	3822	default:
bogdanm	0:9b334a45a8ff	3823	break;
bogdanm	0:9b334a45a8ff	3824	}
bogdanm	0:9b334a45a8ff	3825
bogdanm	0:9b334a45a8ff	3826	switch (Channel)
bogdanm	0:9b334a45a8ff	3827	{
bogdanm	0:9b334a45a8ff	3828	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3829	{
bogdanm	0:9b334a45a8ff	3830	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3831	{
bogdanm	0:9b334a45a8ff	3832	/* Enable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3833	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3834	}
bogdanm	0:9b334a45a8ff	3835	else
bogdanm	0:9b334a45a8ff	3836	{
bogdanm	0:9b334a45a8ff	3837	/* Disable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3838	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3839	}
bogdanm	0:9b334a45a8ff	3840	}
bogdanm	0:9b334a45a8ff	3841	break;
bogdanm	0:9b334a45a8ff	3842	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3843	{
bogdanm	0:9b334a45a8ff	3844	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3845	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3846	{
bogdanm	0:9b334a45a8ff	3847	/* Enable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3848	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3849	}
bogdanm	0:9b334a45a8ff	3850	else
bogdanm	0:9b334a45a8ff	3851	{
bogdanm	0:9b334a45a8ff	3852	/* Disable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3853	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3854	}
bogdanm	0:9b334a45a8ff	3855	}
bogdanm	0:9b334a45a8ff	3856	break;
bogdanm	0:9b334a45a8ff	3857	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3858	{
bogdanm	0:9b334a45a8ff	3859	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3860	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3861	{
bogdanm	0:9b334a45a8ff	3862	/* Enable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3863	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3864	}
bogdanm	0:9b334a45a8ff	3865	else
bogdanm	0:9b334a45a8ff	3866	{
bogdanm	0:9b334a45a8ff	3867	/* Disable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3868	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3869	}
bogdanm	0:9b334a45a8ff	3870	}
bogdanm	0:9b334a45a8ff	3871	break;
bogdanm	0:9b334a45a8ff	3872	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3873	{
bogdanm	0:9b334a45a8ff	3874	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3875	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3876	{
bogdanm	0:9b334a45a8ff	3877	/* Enable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3878	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3879	}
bogdanm	0:9b334a45a8ff	3880	else
bogdanm	0:9b334a45a8ff	3881	{
bogdanm	0:9b334a45a8ff	3882	/* Disable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3883	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3884	}
bogdanm	0:9b334a45a8ff	3885	}
bogdanm	0:9b334a45a8ff	3886	break;
bogdanm	0:9b334a45a8ff	3887	default:
bogdanm	0:9b334a45a8ff	3888	break;
bogdanm	0:9b334a45a8ff	3889	}
bogdanm	0:9b334a45a8ff	3890
bogdanm	0:9b334a45a8ff	3891	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3892
bogdanm	0:9b334a45a8ff	3893	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3894
bogdanm	0:9b334a45a8ff	3895	return HAL_OK;
bogdanm	0:9b334a45a8ff	3896	}
bogdanm	0:9b334a45a8ff	3897
bogdanm	0:9b334a45a8ff	3898	/**
bogdanm	0:9b334a45a8ff	3899	* @brief Configures the clock source to be used
bogdanm	0:9b334a45a8ff	3900	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3901	* @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3902	* contains the clock source information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3903	* @retval HAL status
bogdanm	0:9b334a45a8ff	3904	*/
bogdanm	0:9b334a45a8ff	3905	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
bogdanm	0:9b334a45a8ff	3906	{
bogdanm	0:9b334a45a8ff	3907	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	3908
bogdanm	0:9b334a45a8ff	3909	/* Process Locked */
bogdanm	0:9b334a45a8ff	3910	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3911
bogdanm	0:9b334a45a8ff	3912	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3913
bogdanm	0:9b334a45a8ff	3914	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3915	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
bogdanm	0:9b334a45a8ff	3916
bogdanm	0:9b334a45a8ff	3917	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
bogdanm	0:9b334a45a8ff	3918	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3919	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3920	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	3921	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3922
bogdanm	0:9b334a45a8ff	3923	switch (sClockSourceConfig->ClockSource)
bogdanm	0:9b334a45a8ff	3924	{
bogdanm	0:9b334a45a8ff	3925	case TIM_CLOCKSOURCE_INTERNAL:
bogdanm	0:9b334a45a8ff	3926	{
bogdanm	0:9b334a45a8ff	3927	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3928	/* Disable slave mode to clock the prescaler directly with the internal clock */
bogdanm	0:9b334a45a8ff	3929	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3930	}
bogdanm	0:9b334a45a8ff	3931	break;
bogdanm	0:9b334a45a8ff	3932
bogdanm	0:9b334a45a8ff	3933	case TIM_CLOCKSOURCE_ETRMODE1:
bogdanm	0:9b334a45a8ff	3934	{
bogdanm	0:9b334a45a8ff	3935	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
bogdanm	0:9b334a45a8ff	3936	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3937
mbed_official	124:6a4a5b7d7324	3938	/* Check ETR input conditioning related parameters */
mbed_official	124:6a4a5b7d7324	3939	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	124:6a4a5b7d7324	3940	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	124:6a4a5b7d7324	3941	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	124:6a4a5b7d7324	3942
bogdanm	0:9b334a45a8ff	3943	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3944	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3945	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3946	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3947	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3948	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	3949	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3950	/* Reset the SMS and TS Bits */
bogdanm	0:9b334a45a8ff	3951	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3952	/* Select the External clock mode1 and the ETRF trigger */
bogdanm	0:9b334a45a8ff	3953	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
bogdanm	0:9b334a45a8ff	3954	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	3955	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3956	}
bogdanm	0:9b334a45a8ff	3957	break;
bogdanm	0:9b334a45a8ff	3958
bogdanm	0:9b334a45a8ff	3959	case TIM_CLOCKSOURCE_ETRMODE2:
bogdanm	0:9b334a45a8ff	3960	{
bogdanm	0:9b334a45a8ff	3961	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
bogdanm	0:9b334a45a8ff	3962	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3963
mbed_official	124:6a4a5b7d7324	3964	/* Check ETR input conditioning related parameters */
mbed_official	124:6a4a5b7d7324	3965	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	124:6a4a5b7d7324	3966	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	124:6a4a5b7d7324	3967	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	124:6a4a5b7d7324	3968
bogdanm	0:9b334a45a8ff	3969	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3970	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3971	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3972	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3973	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3974	/* Enable the External clock mode2 */
bogdanm	0:9b334a45a8ff	3975	htim->Instance->SMCR \|= TIM_SMCR_ECE;
bogdanm	0:9b334a45a8ff	3976	}
bogdanm	0:9b334a45a8ff	3977	break;
bogdanm	0:9b334a45a8ff	3978
bogdanm	0:9b334a45a8ff	3979	case TIM_CLOCKSOURCE_TI1:
bogdanm	0:9b334a45a8ff	3980	{
bogdanm	0:9b334a45a8ff	3981	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3982	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3983
mbed_official	124:6a4a5b7d7324	3984	/* Check TI1 input conditioning related parameters */
mbed_official	124:6a4a5b7d7324	3985	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	124:6a4a5b7d7324	3986	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	124:6a4a5b7d7324	3987
bogdanm	0:9b334a45a8ff	3988	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3989	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3990	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3991	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
bogdanm	0:9b334a45a8ff	3992	}
bogdanm	0:9b334a45a8ff	3993	break;
bogdanm	0:9b334a45a8ff	3994	case TIM_CLOCKSOURCE_TI2:
bogdanm	0:9b334a45a8ff	3995	{
bogdanm	0:9b334a45a8ff	3996	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
bogdanm	0:9b334a45a8ff	3997	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3998
mbed_official	124:6a4a5b7d7324	3999	/* Check TI2 input conditioning related parameters */
mbed_official	124:6a4a5b7d7324	4000	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	124:6a4a5b7d7324	4001	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	124:6a4a5b7d7324	4002
bogdanm	0:9b334a45a8ff	4003	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4004	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	4005	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	4006	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
bogdanm	0:9b334a45a8ff	4007	}
bogdanm	0:9b334a45a8ff	4008	break;
bogdanm	0:9b334a45a8ff	4009	case TIM_CLOCKSOURCE_TI1ED:
bogdanm	0:9b334a45a8ff	4010	{
bogdanm	0:9b334a45a8ff	4011	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	4012	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4013
mbed_official	124:6a4a5b7d7324	4014	/* Check TI1 input conditioning related parameters */
mbed_official	124:6a4a5b7d7324	4015	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	124:6a4a5b7d7324	4016	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	124:6a4a5b7d7324	4017
bogdanm	0:9b334a45a8ff	4018	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4019	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	4020	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	4021	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
bogdanm	0:9b334a45a8ff	4022	}
bogdanm	0:9b334a45a8ff	4023	break;
bogdanm	0:9b334a45a8ff	4024	case TIM_CLOCKSOURCE_ITR0:
bogdanm	0:9b334a45a8ff	4025	{
bogdanm	0:9b334a45a8ff	4026	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	4027	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4028
bogdanm	0:9b334a45a8ff	4029	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
bogdanm	0:9b334a45a8ff	4030	}
bogdanm	0:9b334a45a8ff	4031	break;
bogdanm	0:9b334a45a8ff	4032	case TIM_CLOCKSOURCE_ITR1:
bogdanm	0:9b334a45a8ff	4033	{
bogdanm	0:9b334a45a8ff	4034	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	4035	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4036
bogdanm	0:9b334a45a8ff	4037	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
bogdanm	0:9b334a45a8ff	4038	}
bogdanm	0:9b334a45a8ff	4039	break;
bogdanm	0:9b334a45a8ff	4040	case TIM_CLOCKSOURCE_ITR2:
bogdanm	0:9b334a45a8ff	4041	{
bogdanm	0:9b334a45a8ff	4042	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	4043	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4044
bogdanm	0:9b334a45a8ff	4045	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
bogdanm	0:9b334a45a8ff	4046	}
bogdanm	0:9b334a45a8ff	4047	break;
bogdanm	0:9b334a45a8ff	4048	case TIM_CLOCKSOURCE_ITR3:
bogdanm	0:9b334a45a8ff	4049	{
bogdanm	0:9b334a45a8ff	4050	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	4051	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4052
bogdanm	0:9b334a45a8ff	4053	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
bogdanm	0:9b334a45a8ff	4054	}
bogdanm	0:9b334a45a8ff	4055	break;
bogdanm	0:9b334a45a8ff	4056
bogdanm	0:9b334a45a8ff	4057	default:
bogdanm	0:9b334a45a8ff	4058	break;
bogdanm	0:9b334a45a8ff	4059	}
bogdanm	0:9b334a45a8ff	4060	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4061
bogdanm	0:9b334a45a8ff	4062	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4063
bogdanm	0:9b334a45a8ff	4064	return HAL_OK;
bogdanm	0:9b334a45a8ff	4065	}
bogdanm	0:9b334a45a8ff	4066
bogdanm	0:9b334a45a8ff	4067	/**
bogdanm	0:9b334a45a8ff	4068	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
bogdanm	0:9b334a45a8ff	4069	* or a XOR combination between CH1_input, CH2_input & CH3_input
bogdanm	0:9b334a45a8ff	4070	* @param htim : TIM handle.
bogdanm	0:9b334a45a8ff	4071	* @param TI1_Selection : Indicate whether or not channel 1 is connected to the
bogdanm	0:9b334a45a8ff	4072	* output of a XOR gate.
bogdanm	0:9b334a45a8ff	4073	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4074	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
bogdanm	0:9b334a45a8ff	4075	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
bogdanm	0:9b334a45a8ff	4076	* pins are connected to the TI1 input (XOR combination)
bogdanm	0:9b334a45a8ff	4077	* @retval HAL status
bogdanm	0:9b334a45a8ff	4078	*/
bogdanm	0:9b334a45a8ff	4079	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
bogdanm	0:9b334a45a8ff	4080	{
bogdanm	0:9b334a45a8ff	4081	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4082
bogdanm	0:9b334a45a8ff	4083	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4084	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4085	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
bogdanm	0:9b334a45a8ff	4086
bogdanm	0:9b334a45a8ff	4087	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4088	tmpcr2 = htim->Instance->CR2;
bogdanm	0:9b334a45a8ff	4089
bogdanm	0:9b334a45a8ff	4090	/* Reset the TI1 selection */
bogdanm	0:9b334a45a8ff	4091	tmpcr2 &= ~TIM_CR2_TI1S;
bogdanm	0:9b334a45a8ff	4092
bogdanm	0:9b334a45a8ff	4093	/* Set the the TI1 selection */
bogdanm	0:9b334a45a8ff	4094	tmpcr2 \|= TI1_Selection;
bogdanm	0:9b334a45a8ff	4095
bogdanm	0:9b334a45a8ff	4096	/* Write to TIMxCR2 */
bogdanm	0:9b334a45a8ff	4097	htim->Instance->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4098
bogdanm	0:9b334a45a8ff	4099	return HAL_OK;
bogdanm	0:9b334a45a8ff	4100	}
bogdanm	0:9b334a45a8ff	4101
bogdanm	0:9b334a45a8ff	4102	/**
bogdanm	0:9b334a45a8ff	4103	* @brief Configures the TIM in Slave mode
bogdanm	0:9b334a45a8ff	4104	* @param htim : TIM handle.
bogdanm	0:9b334a45a8ff	4105	* @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4106	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4107	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4108	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4109	* @retval HAL status
bogdanm	0:9b334a45a8ff	4110	*/
bogdanm	0:9b334a45a8ff	4111	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
bogdanm	0:9b334a45a8ff	4112	{
bogdanm	0:9b334a45a8ff	4113	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4114	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4115	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4116	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4117
bogdanm	0:9b334a45a8ff	4118	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4119
bogdanm	0:9b334a45a8ff	4120	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4121
bogdanm	0:9b334a45a8ff	4122	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm	0:9b334a45a8ff	4123
bogdanm	0:9b334a45a8ff	4124	/* Disable Trigger Interrupt */
bogdanm	0:9b334a45a8ff	4125	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	4126
bogdanm	0:9b334a45a8ff	4127	/* Disable Trigger DMA request */
bogdanm	0:9b334a45a8ff	4128	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm	0:9b334a45a8ff	4129
bogdanm	0:9b334a45a8ff	4130	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4131
bogdanm	0:9b334a45a8ff	4132	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4133
bogdanm	0:9b334a45a8ff	4134	return HAL_OK;
bogdanm	0:9b334a45a8ff	4135	}
bogdanm	0:9b334a45a8ff	4136
bogdanm	0:9b334a45a8ff	4137	/**
bogdanm	0:9b334a45a8ff	4138	* @brief Configures the TIM in Slave mode in interrupt mode
bogdanm	0:9b334a45a8ff	4139	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4140	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4141	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4142	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4143	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4144	* @retval HAL status
bogdanm	0:9b334a45a8ff	4145	*/
bogdanm	0:9b334a45a8ff	4146	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	4147	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	4148	{
bogdanm	0:9b334a45a8ff	4149	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4150	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4151	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4152	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4153
bogdanm	0:9b334a45a8ff	4154	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4155
bogdanm	0:9b334a45a8ff	4156	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4157
bogdanm	0:9b334a45a8ff	4158	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm	0:9b334a45a8ff	4159
bogdanm	0:9b334a45a8ff	4160	/* Enable Trigger Interrupt */
bogdanm	0:9b334a45a8ff	4161	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	4162
bogdanm	0:9b334a45a8ff	4163	/* Disable Trigger DMA request */
bogdanm	0:9b334a45a8ff	4164	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm	0:9b334a45a8ff	4165
bogdanm	0:9b334a45a8ff	4166	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4167
bogdanm	0:9b334a45a8ff	4168	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4169
bogdanm	0:9b334a45a8ff	4170	return HAL_OK;
bogdanm	0:9b334a45a8ff	4171	}
bogdanm	0:9b334a45a8ff	4172
bogdanm	0:9b334a45a8ff	4173	/**
bogdanm	0:9b334a45a8ff	4174	* @brief Read the captured value from Capture Compare unit
bogdanm	0:9b334a45a8ff	4175	* @param htim : TIM handle.
bogdanm	0:9b334a45a8ff	4176	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	4177	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4178	* @arg TIM_CHANNEL_1 : TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	4179	* @arg TIM_CHANNEL_2 : TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	4180	* @arg TIM_CHANNEL_3 : TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	4181	* @arg TIM_CHANNEL_4 : TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	4182	* @retval Captured value
bogdanm	0:9b334a45a8ff	4183	*/
bogdanm	0:9b334a45a8ff	4184	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	4185	{
bogdanm	0:9b334a45a8ff	4186	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	4187
bogdanm	0:9b334a45a8ff	4188	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4189
bogdanm	0:9b334a45a8ff	4190	switch (Channel)
bogdanm	0:9b334a45a8ff	4191	{
bogdanm	0:9b334a45a8ff	4192	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	4193	{
bogdanm	0:9b334a45a8ff	4194	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4195	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4196
bogdanm	0:9b334a45a8ff	4197	/* Return the capture 1 value */
bogdanm	0:9b334a45a8ff	4198	tmpreg = htim->Instance->CCR1;
bogdanm	0:9b334a45a8ff	4199
bogdanm	0:9b334a45a8ff	4200	break;
bogdanm	0:9b334a45a8ff	4201	}
bogdanm	0:9b334a45a8ff	4202	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	4203	{
bogdanm	0:9b334a45a8ff	4204	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4205	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4206
bogdanm	0:9b334a45a8ff	4207	/* Return the capture 2 value */
bogdanm	0:9b334a45a8ff	4208	tmpreg = htim->Instance->CCR2;
bogdanm	0:9b334a45a8ff	4209
bogdanm	0:9b334a45a8ff	4210	break;
bogdanm	0:9b334a45a8ff	4211	}
bogdanm	0:9b334a45a8ff	4212
bogdanm	0:9b334a45a8ff	4213	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	4214	{
bogdanm	0:9b334a45a8ff	4215	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4216	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4217
bogdanm	0:9b334a45a8ff	4218	/* Return the capture 3 value */
bogdanm	0:9b334a45a8ff	4219	tmpreg = htim->Instance->CCR3;
bogdanm	0:9b334a45a8ff	4220
bogdanm	0:9b334a45a8ff	4221	break;
bogdanm	0:9b334a45a8ff	4222	}
bogdanm	0:9b334a45a8ff	4223
bogdanm	0:9b334a45a8ff	4224	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	4225	{
bogdanm	0:9b334a45a8ff	4226	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4227	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4228
bogdanm	0:9b334a45a8ff	4229	/* Return the capture 4 value */
bogdanm	0:9b334a45a8ff	4230	tmpreg = htim->Instance->CCR4;
bogdanm	0:9b334a45a8ff	4231
bogdanm	0:9b334a45a8ff	4232	break;
bogdanm	0:9b334a45a8ff	4233	}
bogdanm	0:9b334a45a8ff	4234
bogdanm	0:9b334a45a8ff	4235	default:
bogdanm	0:9b334a45a8ff	4236	break;
bogdanm	0:9b334a45a8ff	4237	}
bogdanm	0:9b334a45a8ff	4238
bogdanm	0:9b334a45a8ff	4239	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4240	return tmpreg;
bogdanm	0:9b334a45a8ff	4241	}
bogdanm	0:9b334a45a8ff	4242
bogdanm	0:9b334a45a8ff	4243	/**
bogdanm	0:9b334a45a8ff	4244	* @}
bogdanm	0:9b334a45a8ff	4245	*/
bogdanm	0:9b334a45a8ff	4246
bogdanm	0:9b334a45a8ff	4247	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4248	* @brief TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4249	*
bogdanm	0:9b334a45a8ff	4250	@verbatim
bogdanm	0:9b334a45a8ff	4251	==============================================================================
bogdanm	0:9b334a45a8ff	4252	##### TIM Callbacks functions #####
bogdanm	0:9b334a45a8ff	4253	==============================================================================
bogdanm	0:9b334a45a8ff	4254	[..]
bogdanm	0:9b334a45a8ff	4255	This section provides TIM callback functions:
bogdanm	0:9b334a45a8ff	4256	(+) Timer Period elapsed callback
bogdanm	0:9b334a45a8ff	4257	(+) Timer Output Compare callback
bogdanm	0:9b334a45a8ff	4258	(+) Timer Input capture callback
bogdanm	0:9b334a45a8ff	4259	(+) Timer Trigger callback
bogdanm	0:9b334a45a8ff	4260	(+) Timer Error callback
bogdanm	0:9b334a45a8ff	4261
bogdanm	0:9b334a45a8ff	4262	@endverbatim
bogdanm	0:9b334a45a8ff	4263	* @{
bogdanm	0:9b334a45a8ff	4264	*/
bogdanm	0:9b334a45a8ff	4265
bogdanm	0:9b334a45a8ff	4266	/**
bogdanm	0:9b334a45a8ff	4267	* @brief Period elapsed callback in non blocking mode
bogdanm	0:9b334a45a8ff	4268	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4269	* @retval None
bogdanm	0:9b334a45a8ff	4270	*/
bogdanm	0:9b334a45a8ff	4271	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4272	{
mbed_official	124:6a4a5b7d7324	4273	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	4274	UNUSED(htim);
bogdanm	0:9b334a45a8ff	4275	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4276	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4277	*/
bogdanm	0:9b334a45a8ff	4278
bogdanm	0:9b334a45a8ff	4279	}
bogdanm	0:9b334a45a8ff	4280	/**
bogdanm	0:9b334a45a8ff	4281	* @brief Output Compare callback in non blocking mode
bogdanm	0:9b334a45a8ff	4282	* @param htim : TIM OC handle
bogdanm	0:9b334a45a8ff	4283	* @retval None
bogdanm	0:9b334a45a8ff	4284	*/
bogdanm	0:9b334a45a8ff	4285	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4286	{
mbed_official	124:6a4a5b7d7324	4287	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	4288	UNUSED(htim);
bogdanm	0:9b334a45a8ff	4289	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4290	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4291	*/
bogdanm	0:9b334a45a8ff	4292	}
bogdanm	0:9b334a45a8ff	4293	/**
bogdanm	0:9b334a45a8ff	4294	* @brief Input Capture callback in non blocking mode
bogdanm	0:9b334a45a8ff	4295	* @param htim : TIM IC handle
bogdanm	0:9b334a45a8ff	4296	* @retval None
bogdanm	0:9b334a45a8ff	4297	*/
bogdanm	0:9b334a45a8ff	4298	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4299	{
mbed_official	124:6a4a5b7d7324	4300	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	4301	UNUSED(htim);
bogdanm	0:9b334a45a8ff	4302	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4303	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4304	*/
bogdanm	0:9b334a45a8ff	4305	}
bogdanm	0:9b334a45a8ff	4306
bogdanm	0:9b334a45a8ff	4307	/**
bogdanm	0:9b334a45a8ff	4308	* @brief PWM Pulse finished callback in non blocking mode
bogdanm	0:9b334a45a8ff	4309	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4310	* @retval None
bogdanm	0:9b334a45a8ff	4311	*/
bogdanm	0:9b334a45a8ff	4312	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4313	{
mbed_official	124:6a4a5b7d7324	4314	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	4315	UNUSED(htim);
bogdanm	0:9b334a45a8ff	4316	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4317	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4318	*/
bogdanm	0:9b334a45a8ff	4319	}
bogdanm	0:9b334a45a8ff	4320
bogdanm	0:9b334a45a8ff	4321	/**
bogdanm	0:9b334a45a8ff	4322	* @brief Hall Trigger detection callback in non blocking mode
bogdanm	0:9b334a45a8ff	4323	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4324	* @retval None
bogdanm	0:9b334a45a8ff	4325	*/
bogdanm	0:9b334a45a8ff	4326	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4327	{
mbed_official	124:6a4a5b7d7324	4328	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	4329	UNUSED(htim);
bogdanm	0:9b334a45a8ff	4330	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4331	the HAL_TIM_TriggerCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4332	*/
bogdanm	0:9b334a45a8ff	4333	}
bogdanm	0:9b334a45a8ff	4334
bogdanm	0:9b334a45a8ff	4335	/**
bogdanm	0:9b334a45a8ff	4336	* @brief Timer error callback in non blocking mode
bogdanm	0:9b334a45a8ff	4337	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4338	* @retval None
bogdanm	0:9b334a45a8ff	4339	*/
bogdanm	0:9b334a45a8ff	4340	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4341	{
mbed_official	124:6a4a5b7d7324	4342	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	4343	UNUSED(htim);
bogdanm	0:9b334a45a8ff	4344	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4345	the HAL_TIM_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4346	*/
bogdanm	0:9b334a45a8ff	4347	}
bogdanm	0:9b334a45a8ff	4348
bogdanm	0:9b334a45a8ff	4349	/**
bogdanm	0:9b334a45a8ff	4350	* @}
bogdanm	0:9b334a45a8ff	4351	*/
bogdanm	0:9b334a45a8ff	4352
bogdanm	0:9b334a45a8ff	4353	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm	0:9b334a45a8ff	4354	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	4355	*
bogdanm	0:9b334a45a8ff	4356	@verbatim
bogdanm	0:9b334a45a8ff	4357	==============================================================================
bogdanm	0:9b334a45a8ff	4358	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	4359	==============================================================================
bogdanm	0:9b334a45a8ff	4360	[..]
bogdanm	0:9b334a45a8ff	4361	This subsection permit to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	4362	and the data flow.
bogdanm	0:9b334a45a8ff	4363
bogdanm	0:9b334a45a8ff	4364	@endverbatim
bogdanm	0:9b334a45a8ff	4365	* @{
bogdanm	0:9b334a45a8ff	4366	*/
bogdanm	0:9b334a45a8ff	4367
bogdanm	0:9b334a45a8ff	4368	/**
bogdanm	0:9b334a45a8ff	4369	* @brief Return the TIM Base state
bogdanm	0:9b334a45a8ff	4370	* @param htim : TIM Base handle
bogdanm	0:9b334a45a8ff	4371	* @retval HAL state
bogdanm	0:9b334a45a8ff	4372	*/
bogdanm	0:9b334a45a8ff	4373	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4374	{
bogdanm	0:9b334a45a8ff	4375	return htim->State;
bogdanm	0:9b334a45a8ff	4376	}
bogdanm	0:9b334a45a8ff	4377
bogdanm	0:9b334a45a8ff	4378	/**
bogdanm	0:9b334a45a8ff	4379	* @brief Return the TIM OC state
bogdanm	0:9b334a45a8ff	4380	* @param htim : TIM Ouput Compare handle
bogdanm	0:9b334a45a8ff	4381	* @retval HAL state
bogdanm	0:9b334a45a8ff	4382	*/
bogdanm	0:9b334a45a8ff	4383	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4384	{
bogdanm	0:9b334a45a8ff	4385	return htim->State;
bogdanm	0:9b334a45a8ff	4386	}
bogdanm	0:9b334a45a8ff	4387
bogdanm	0:9b334a45a8ff	4388	/**
bogdanm	0:9b334a45a8ff	4389	* @brief Return the TIM PWM state
bogdanm	0:9b334a45a8ff	4390	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4391	* @retval HAL state
bogdanm	0:9b334a45a8ff	4392	*/
bogdanm	0:9b334a45a8ff	4393	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4394	{
bogdanm	0:9b334a45a8ff	4395	return htim->State;
bogdanm	0:9b334a45a8ff	4396	}
bogdanm	0:9b334a45a8ff	4397
bogdanm	0:9b334a45a8ff	4398	/**
bogdanm	0:9b334a45a8ff	4399	* @brief Return the TIM Input Capture state
bogdanm	0:9b334a45a8ff	4400	* @param htim : TIM IC handle
bogdanm	0:9b334a45a8ff	4401	* @retval HAL state
bogdanm	0:9b334a45a8ff	4402	*/
bogdanm	0:9b334a45a8ff	4403	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4404	{
bogdanm	0:9b334a45a8ff	4405	return htim->State;
bogdanm	0:9b334a45a8ff	4406	}
bogdanm	0:9b334a45a8ff	4407
bogdanm	0:9b334a45a8ff	4408	/**
bogdanm	0:9b334a45a8ff	4409	* @brief Return the TIM One Pulse Mode state
bogdanm	0:9b334a45a8ff	4410	* @param htim : TIM OPM handle
bogdanm	0:9b334a45a8ff	4411	* @retval HAL state
bogdanm	0:9b334a45a8ff	4412	*/
bogdanm	0:9b334a45a8ff	4413	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4414	{
bogdanm	0:9b334a45a8ff	4415	return htim->State;
bogdanm	0:9b334a45a8ff	4416	}
bogdanm	0:9b334a45a8ff	4417
bogdanm	0:9b334a45a8ff	4418	/**
bogdanm	0:9b334a45a8ff	4419	* @brief Return the TIM Encoder Mode state
bogdanm	0:9b334a45a8ff	4420	* @param htim : TIM Encoder handle
bogdanm	0:9b334a45a8ff	4421	* @retval HAL state
bogdanm	0:9b334a45a8ff	4422	*/
bogdanm	0:9b334a45a8ff	4423	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4424	{
bogdanm	0:9b334a45a8ff	4425	return htim->State;
bogdanm	0:9b334a45a8ff	4426	}
bogdanm	0:9b334a45a8ff	4427
bogdanm	0:9b334a45a8ff	4428	/**
bogdanm	0:9b334a45a8ff	4429	* @}
bogdanm	0:9b334a45a8ff	4430	*/
bogdanm	0:9b334a45a8ff	4431
bogdanm	0:9b334a45a8ff	4432	/**
bogdanm	0:9b334a45a8ff	4433	* @}
bogdanm	0:9b334a45a8ff	4434	*/
bogdanm	0:9b334a45a8ff	4435
mbed_official	124:6a4a5b7d7324	4436	/** @addtogroup TIM_Private_Functions
bogdanm	0:9b334a45a8ff	4437	* @{
bogdanm	0:9b334a45a8ff	4438	*/
bogdanm	0:9b334a45a8ff	4439
bogdanm	0:9b334a45a8ff	4440	/**
bogdanm	0:9b334a45a8ff	4441	* @brief TIM DMA error callback
bogdanm	0:9b334a45a8ff	4442	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4443	* @retval None
bogdanm	0:9b334a45a8ff	4444	*/
bogdanm	0:9b334a45a8ff	4445	void TIM_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4446	{
bogdanm	0:9b334a45a8ff	4447	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4448
bogdanm	0:9b334a45a8ff	4449	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4450
bogdanm	0:9b334a45a8ff	4451	HAL_TIM_ErrorCallback(htim);
bogdanm	0:9b334a45a8ff	4452	}
bogdanm	0:9b334a45a8ff	4453
bogdanm	0:9b334a45a8ff	4454	/**
bogdanm	0:9b334a45a8ff	4455	* @brief TIM DMA Delay Pulse complete callback.
bogdanm	0:9b334a45a8ff	4456	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4457	* @retval None
bogdanm	0:9b334a45a8ff	4458	*/
bogdanm	0:9b334a45a8ff	4459	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4460	{
bogdanm	0:9b334a45a8ff	4461	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4462
bogdanm	0:9b334a45a8ff	4463	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4464
bogdanm	0:9b334a45a8ff	4465	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4466	{
bogdanm	0:9b334a45a8ff	4467	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4468	}
bogdanm	0:9b334a45a8ff	4469	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4470	{
bogdanm	0:9b334a45a8ff	4471	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4472	}
bogdanm	0:9b334a45a8ff	4473	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4474	{
bogdanm	0:9b334a45a8ff	4475	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4476	}
bogdanm	0:9b334a45a8ff	4477	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4478	{
bogdanm	0:9b334a45a8ff	4479	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4480	}
bogdanm	0:9b334a45a8ff	4481
bogdanm	0:9b334a45a8ff	4482	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	4483
bogdanm	0:9b334a45a8ff	4484	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4485	}
bogdanm	0:9b334a45a8ff	4486	/**
bogdanm	0:9b334a45a8ff	4487	* @brief TIM DMA Capture complete callback.
bogdanm	0:9b334a45a8ff	4488	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4489	* @retval None
bogdanm	0:9b334a45a8ff	4490	*/
bogdanm	0:9b334a45a8ff	4491	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4492	{
bogdanm	0:9b334a45a8ff	4493	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4494
bogdanm	0:9b334a45a8ff	4495	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4496
bogdanm	0:9b334a45a8ff	4497	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4498	{
bogdanm	0:9b334a45a8ff	4499	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4500	}
bogdanm	0:9b334a45a8ff	4501	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4502	{
bogdanm	0:9b334a45a8ff	4503	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4504	}
bogdanm	0:9b334a45a8ff	4505	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4506	{
bogdanm	0:9b334a45a8ff	4507	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4508	}
bogdanm	0:9b334a45a8ff	4509	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4510	{
bogdanm	0:9b334a45a8ff	4511	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4512	}
bogdanm	0:9b334a45a8ff	4513
bogdanm	0:9b334a45a8ff	4514	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	4515
bogdanm	0:9b334a45a8ff	4516	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4517	}
bogdanm	0:9b334a45a8ff	4518
bogdanm	0:9b334a45a8ff	4519	/**
bogdanm	0:9b334a45a8ff	4520	* @brief TIM DMA Period Elapse complete callback.
bogdanm	0:9b334a45a8ff	4521	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4522	* @retval None
bogdanm	0:9b334a45a8ff	4523	*/
bogdanm	0:9b334a45a8ff	4524	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4525	{
bogdanm	0:9b334a45a8ff	4526	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4527
bogdanm	0:9b334a45a8ff	4528	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4529
bogdanm	0:9b334a45a8ff	4530	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	4531	}
bogdanm	0:9b334a45a8ff	4532
bogdanm	0:9b334a45a8ff	4533	/**
bogdanm	0:9b334a45a8ff	4534	* @brief TIM DMA Trigger callback.
bogdanm	0:9b334a45a8ff	4535	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4536	* @retval None
bogdanm	0:9b334a45a8ff	4537	*/
bogdanm	0:9b334a45a8ff	4538	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4539	{
bogdanm	0:9b334a45a8ff	4540	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4541
bogdanm	0:9b334a45a8ff	4542	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4543
bogdanm	0:9b334a45a8ff	4544	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	4545	}
bogdanm	0:9b334a45a8ff	4546
bogdanm	0:9b334a45a8ff	4547	/**
bogdanm	0:9b334a45a8ff	4548	* @brief Time Base configuration
bogdanm	0:9b334a45a8ff	4549	* @param TIMx : TIM periheral
bogdanm	0:9b334a45a8ff	4550	* @param Structure : TIM Base configuration structure
bogdanm	0:9b334a45a8ff	4551	* @retval None
bogdanm	0:9b334a45a8ff	4552	*/
bogdanm	0:9b334a45a8ff	4553	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
bogdanm	0:9b334a45a8ff	4554	{
bogdanm	0:9b334a45a8ff	4555	uint32_t tmpcr1 = 0;
bogdanm	0:9b334a45a8ff	4556	tmpcr1 = TIMx->CR1;
bogdanm	0:9b334a45a8ff	4557
bogdanm	0:9b334a45a8ff	4558	/* Set TIM Time Base Unit parameters ---------------------------------------*/
bogdanm	0:9b334a45a8ff	4559	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4560	{
bogdanm	0:9b334a45a8ff	4561	/* Select the Counter Mode */
bogdanm	0:9b334a45a8ff	4562	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
bogdanm	0:9b334a45a8ff	4563	tmpcr1 \|= Structure->CounterMode;
bogdanm	0:9b334a45a8ff	4564	}
bogdanm	0:9b334a45a8ff	4565
bogdanm	0:9b334a45a8ff	4566	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4567	{
bogdanm	0:9b334a45a8ff	4568	/* Set the clock division */
bogdanm	0:9b334a45a8ff	4569	tmpcr1 &= ~TIM_CR1_CKD;
bogdanm	0:9b334a45a8ff	4570	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
bogdanm	0:9b334a45a8ff	4571	}
bogdanm	0:9b334a45a8ff	4572
bogdanm	0:9b334a45a8ff	4573	TIMx->CR1 = tmpcr1;
bogdanm	0:9b334a45a8ff	4574
bogdanm	0:9b334a45a8ff	4575	/* Set the Autoreload value */
bogdanm	0:9b334a45a8ff	4576	TIMx->ARR = (uint32_t)Structure->Period ;
bogdanm	0:9b334a45a8ff	4577
bogdanm	0:9b334a45a8ff	4578	/* Set the Prescaler value */
bogdanm	0:9b334a45a8ff	4579	TIMx->PSC = (uint32_t)Structure->Prescaler;
bogdanm	0:9b334a45a8ff	4580
bogdanm	0:9b334a45a8ff	4581	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4582	{
bogdanm	0:9b334a45a8ff	4583	/* Set the Repetition Counter value */
bogdanm	0:9b334a45a8ff	4584	TIMx->RCR = Structure->RepetitionCounter;
bogdanm	0:9b334a45a8ff	4585	}
bogdanm	0:9b334a45a8ff	4586
bogdanm	0:9b334a45a8ff	4587	/* Generate an update event to reload the Prescaler
bogdanm	0:9b334a45a8ff	4588	and the repetition counter(only for TIM1 and TIM8) value immediatly */
bogdanm	0:9b334a45a8ff	4589	TIMx->EGR = TIM_EGR_UG;
bogdanm	0:9b334a45a8ff	4590	}
bogdanm	0:9b334a45a8ff	4591
bogdanm	0:9b334a45a8ff	4592	/**
bogdanm	0:9b334a45a8ff	4593	* @brief Time Ouput Compare 1 configuration
bogdanm	0:9b334a45a8ff	4594	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4595	* @param OC_Config : The ouput configuration structure
bogdanm	0:9b334a45a8ff	4596	* @retval None
bogdanm	0:9b334a45a8ff	4597	*/
bogdanm	0:9b334a45a8ff	4598	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4599	{
bogdanm	0:9b334a45a8ff	4600	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4601	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4602	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4603
bogdanm	0:9b334a45a8ff	4604	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4605	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4606
bogdanm	0:9b334a45a8ff	4607	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4608	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4609	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4610	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4611
bogdanm	0:9b334a45a8ff	4612	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4613	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4614
bogdanm	0:9b334a45a8ff	4615	/* Reset the Output Compare Mode Bits */
bogdanm	0:9b334a45a8ff	4616	tmpccmrx &= ~TIM_CCMR1_OC1M;
bogdanm	0:9b334a45a8ff	4617	tmpccmrx &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4618	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4619	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4620
bogdanm	0:9b334a45a8ff	4621	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4622	tmpccer &= ~TIM_CCER_CC1P;
bogdanm	0:9b334a45a8ff	4623	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4624	tmpccer \|= OC_Config->OCPolarity;
bogdanm	0:9b334a45a8ff	4625
bogdanm	0:9b334a45a8ff	4626	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
bogdanm	0:9b334a45a8ff	4627	{
bogdanm	0:9b334a45a8ff	4628	/* Check parameters */
bogdanm	0:9b334a45a8ff	4629	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4630
bogdanm	0:9b334a45a8ff	4631	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4632	tmpccer &= ~TIM_CCER_CC1NP;
bogdanm	0:9b334a45a8ff	4633	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4634	tmpccer \|= OC_Config->OCNPolarity;
bogdanm	0:9b334a45a8ff	4635	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4636	tmpccer &= ~TIM_CCER_CC1NE;
bogdanm	0:9b334a45a8ff	4637	}
bogdanm	0:9b334a45a8ff	4638
bogdanm	0:9b334a45a8ff	4639	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4640	{
bogdanm	0:9b334a45a8ff	4641	/* Check parameters */
bogdanm	0:9b334a45a8ff	4642	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4643	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4644
bogdanm	0:9b334a45a8ff	4645	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4646	tmpcr2 &= ~TIM_CR2_OIS1;
bogdanm	0:9b334a45a8ff	4647	tmpcr2 &= ~TIM_CR2_OIS1N;
bogdanm	0:9b334a45a8ff	4648	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4649	tmpcr2 \|= OC_Config->OCIdleState;
bogdanm	0:9b334a45a8ff	4650	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4651	tmpcr2 \|= OC_Config->OCNIdleState;
bogdanm	0:9b334a45a8ff	4652	}
bogdanm	0:9b334a45a8ff	4653	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4654	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4655
bogdanm	0:9b334a45a8ff	4656	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4657	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4658
bogdanm	0:9b334a45a8ff	4659	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4660	TIMx->CCR1 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4661
bogdanm	0:9b334a45a8ff	4662	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4663	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4664	}
bogdanm	0:9b334a45a8ff	4665
bogdanm	0:9b334a45a8ff	4666	/**
bogdanm	0:9b334a45a8ff	4667	* @brief Time Ouput Compare 2 configuration
bogdanm	0:9b334a45a8ff	4668	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4669	* @param OC_Config : The ouput configuration structure
bogdanm	0:9b334a45a8ff	4670	* @retval None
bogdanm	0:9b334a45a8ff	4671	*/
bogdanm	0:9b334a45a8ff	4672	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4673	{
bogdanm	0:9b334a45a8ff	4674	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4675	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4676	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4677
bogdanm	0:9b334a45a8ff	4678	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4679	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4680
bogdanm	0:9b334a45a8ff	4681	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4682	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4683	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4684	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4685
bogdanm	0:9b334a45a8ff	4686	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4687	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4688
bogdanm	0:9b334a45a8ff	4689	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4690	tmpccmrx &= ~TIM_CCMR1_OC2M;
bogdanm	0:9b334a45a8ff	4691	tmpccmrx &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	4692
bogdanm	0:9b334a45a8ff	4693	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4694	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4695
bogdanm	0:9b334a45a8ff	4696	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4697	tmpccer &= ~TIM_CCER_CC2P;
bogdanm	0:9b334a45a8ff	4698	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4699	tmpccer \|= (OC_Config->OCPolarity << 4);
bogdanm	0:9b334a45a8ff	4700
bogdanm	0:9b334a45a8ff	4701	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	4702	{
bogdanm	0:9b334a45a8ff	4703	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4704
bogdanm	0:9b334a45a8ff	4705	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4706	tmpccer &= ~TIM_CCER_CC2NP;
bogdanm	0:9b334a45a8ff	4707	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4708	tmpccer \|= (OC_Config->OCNPolarity << 4);
bogdanm	0:9b334a45a8ff	4709	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4710	tmpccer &= ~TIM_CCER_CC2NE;
bogdanm	0:9b334a45a8ff	4711
bogdanm	0:9b334a45a8ff	4712	}
bogdanm	0:9b334a45a8ff	4713
bogdanm	0:9b334a45a8ff	4714	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4715	{
bogdanm	0:9b334a45a8ff	4716	/* Check parameters */
bogdanm	0:9b334a45a8ff	4717	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4718	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4719
bogdanm	0:9b334a45a8ff	4720	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4721	tmpcr2 &= ~TIM_CR2_OIS2;
bogdanm	0:9b334a45a8ff	4722	tmpcr2 &= ~TIM_CR2_OIS2N;
bogdanm	0:9b334a45a8ff	4723	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4724	tmpcr2 \|= (OC_Config->OCIdleState << 2);
bogdanm	0:9b334a45a8ff	4725	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4726	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
bogdanm	0:9b334a45a8ff	4727	}
bogdanm	0:9b334a45a8ff	4728
bogdanm	0:9b334a45a8ff	4729	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4730	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4731
bogdanm	0:9b334a45a8ff	4732	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4733	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4734
bogdanm	0:9b334a45a8ff	4735	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4736	TIMx->CCR2 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4737
bogdanm	0:9b334a45a8ff	4738	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4739	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4740	}
bogdanm	0:9b334a45a8ff	4741
bogdanm	0:9b334a45a8ff	4742	/**
bogdanm	0:9b334a45a8ff	4743	* @brief Time Ouput Compare 3 configuration
bogdanm	0:9b334a45a8ff	4744	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4745	* @param OC_Config : The ouput configuration structure
bogdanm	0:9b334a45a8ff	4746	* @retval None
bogdanm	0:9b334a45a8ff	4747	*/
bogdanm	0:9b334a45a8ff	4748	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4749	{
bogdanm	0:9b334a45a8ff	4750	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4751	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4752	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4753
bogdanm	0:9b334a45a8ff	4754	/* Disable the Channel 3: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4755	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	4756
bogdanm	0:9b334a45a8ff	4757	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4758	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4759	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4760	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4761
bogdanm	0:9b334a45a8ff	4762	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4763	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4764
bogdanm	0:9b334a45a8ff	4765	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4766	tmpccmrx &= ~TIM_CCMR2_OC3M;
bogdanm	0:9b334a45a8ff	4767	tmpccmrx &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	4768	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4769	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4770
bogdanm	0:9b334a45a8ff	4771	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4772	tmpccer &= ~TIM_CCER_CC3P;
bogdanm	0:9b334a45a8ff	4773	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4774	tmpccer \|= (OC_Config->OCPolarity << 8);
bogdanm	0:9b334a45a8ff	4775
bogdanm	0:9b334a45a8ff	4776	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
bogdanm	0:9b334a45a8ff	4777	{
bogdanm	0:9b334a45a8ff	4778	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4779
bogdanm	0:9b334a45a8ff	4780	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4781	tmpccer &= ~TIM_CCER_CC3NP;
bogdanm	0:9b334a45a8ff	4782	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4783	tmpccer \|= (OC_Config->OCNPolarity << 8);
bogdanm	0:9b334a45a8ff	4784	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4785	tmpccer &= ~TIM_CCER_CC3NE;
bogdanm	0:9b334a45a8ff	4786	}
bogdanm	0:9b334a45a8ff	4787
bogdanm	0:9b334a45a8ff	4788	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4789	{
bogdanm	0:9b334a45a8ff	4790	/* Check parameters */
bogdanm	0:9b334a45a8ff	4791	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4792	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4793
bogdanm	0:9b334a45a8ff	4794	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4795	tmpcr2 &= ~TIM_CR2_OIS3;
bogdanm	0:9b334a45a8ff	4796	tmpcr2 &= ~TIM_CR2_OIS3N;
bogdanm	0:9b334a45a8ff	4797	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4798	tmpcr2 \|= (OC_Config->OCIdleState << 4);
bogdanm	0:9b334a45a8ff	4799	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4800	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
bogdanm	0:9b334a45a8ff	4801	}
bogdanm	0:9b334a45a8ff	4802
bogdanm	0:9b334a45a8ff	4803	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4804	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4805
bogdanm	0:9b334a45a8ff	4806	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4807	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4808
bogdanm	0:9b334a45a8ff	4809	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4810	TIMx->CCR3 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4811
bogdanm	0:9b334a45a8ff	4812	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4813	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4814	}
bogdanm	0:9b334a45a8ff	4815
bogdanm	0:9b334a45a8ff	4816	/**
bogdanm	0:9b334a45a8ff	4817	* @brief Time Ouput Compare 4 configuration
bogdanm	0:9b334a45a8ff	4818	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4819	* @param OC_Config : The ouput configuration structure
bogdanm	0:9b334a45a8ff	4820	* @retval None
bogdanm	0:9b334a45a8ff	4821	*/
bogdanm	0:9b334a45a8ff	4822	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4823	{
bogdanm	0:9b334a45a8ff	4824	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4825	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4826	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4827
bogdanm	0:9b334a45a8ff	4828	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	4829	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	4830
bogdanm	0:9b334a45a8ff	4831	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4832	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4833	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4834	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4835
bogdanm	0:9b334a45a8ff	4836	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4837	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4838
bogdanm	0:9b334a45a8ff	4839	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4840	tmpccmrx &= ~TIM_CCMR2_OC4M;
bogdanm	0:9b334a45a8ff	4841	tmpccmrx &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	4842
bogdanm	0:9b334a45a8ff	4843	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4844	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4845
bogdanm	0:9b334a45a8ff	4846	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4847	tmpccer &= ~TIM_CCER_CC4P;
bogdanm	0:9b334a45a8ff	4848	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4849	tmpccer \|= (OC_Config->OCPolarity << 12);
bogdanm	0:9b334a45a8ff	4850
bogdanm	0:9b334a45a8ff	4851	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4852	{
bogdanm	0:9b334a45a8ff	4853	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4854
bogdanm	0:9b334a45a8ff	4855	/* Reset the Output Compare IDLE State */
bogdanm	0:9b334a45a8ff	4856	tmpcr2 &= ~TIM_CR2_OIS4;
bogdanm	0:9b334a45a8ff	4857	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4858	tmpcr2 \|= (OC_Config->OCIdleState << 6);
bogdanm	0:9b334a45a8ff	4859	}
bogdanm	0:9b334a45a8ff	4860
bogdanm	0:9b334a45a8ff	4861	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4862	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4863
bogdanm	0:9b334a45a8ff	4864	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4865	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4866
bogdanm	0:9b334a45a8ff	4867	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4868	TIMx->CCR4 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4869
bogdanm	0:9b334a45a8ff	4870	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4871	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4872	}
bogdanm	0:9b334a45a8ff	4873
mbed_official	124:6a4a5b7d7324	4874
mbed_official	124:6a4a5b7d7324	4875	/**
mbed_official	124:6a4a5b7d7324	4876	* @brief Time Slave configuration
mbed_official	124:6a4a5b7d7324	4877	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	124:6a4a5b7d7324	4878	* the configuration information for TIM module.
mbed_official	124:6a4a5b7d7324	4879	* @param sSlaveConfig: The slave configuration structure
mbed_official	124:6a4a5b7d7324	4880	* @retval None
mbed_official	124:6a4a5b7d7324	4881	*/
bogdanm	0:9b334a45a8ff	4882	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	4883	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	4884	{
bogdanm	0:9b334a45a8ff	4885	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4886	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4887	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4888
bogdanm	0:9b334a45a8ff	4889	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4890	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	4891
bogdanm	0:9b334a45a8ff	4892	/* Reset the Trigger Selection Bits */
bogdanm	0:9b334a45a8ff	4893	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	4894	/* Set the Input Trigger source */
bogdanm	0:9b334a45a8ff	4895	tmpsmcr \|= sSlaveConfig->InputTrigger;
bogdanm	0:9b334a45a8ff	4896
bogdanm	0:9b334a45a8ff	4897	/* Reset the slave mode Bits */
bogdanm	0:9b334a45a8ff	4898	tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	4899	/* Set the slave mode */
bogdanm	0:9b334a45a8ff	4900	tmpsmcr \|= sSlaveConfig->SlaveMode;
bogdanm	0:9b334a45a8ff	4901
bogdanm	0:9b334a45a8ff	4902	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4903	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4904
bogdanm	0:9b334a45a8ff	4905	/* Configure the trigger prescaler, filter, and polarity */
bogdanm	0:9b334a45a8ff	4906	switch (sSlaveConfig->InputTrigger)
bogdanm	0:9b334a45a8ff	4907	{
bogdanm	0:9b334a45a8ff	4908	case TIM_TS_ETRF:
bogdanm	0:9b334a45a8ff	4909	{
bogdanm	0:9b334a45a8ff	4910	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4911	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4912	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm	0:9b334a45a8ff	4913	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4914	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4915	/* Configure the ETR Trigger source */
bogdanm	0:9b334a45a8ff	4916	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	4917	sSlaveConfig->TriggerPrescaler,
bogdanm	0:9b334a45a8ff	4918	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4919	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4920	}
bogdanm	0:9b334a45a8ff	4921	break;
bogdanm	0:9b334a45a8ff	4922
bogdanm	0:9b334a45a8ff	4923	case TIM_TS_TI1F_ED:
bogdanm	0:9b334a45a8ff	4924	{
bogdanm	0:9b334a45a8ff	4925	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4926	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4927	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4928
bogdanm	0:9b334a45a8ff	4929	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4930	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	4931	htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4932	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	4933
bogdanm	0:9b334a45a8ff	4934	/* Set the filter */
bogdanm	0:9b334a45a8ff	4935	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4936	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm	0:9b334a45a8ff	4937
bogdanm	0:9b334a45a8ff	4938	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4939	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4940	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4941
bogdanm	0:9b334a45a8ff	4942	}
bogdanm	0:9b334a45a8ff	4943	break;
bogdanm	0:9b334a45a8ff	4944
bogdanm	0:9b334a45a8ff	4945	case TIM_TS_TI1FP1:
bogdanm	0:9b334a45a8ff	4946	{
bogdanm	0:9b334a45a8ff	4947	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4948	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4949	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4950	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4951
bogdanm	0:9b334a45a8ff	4952	/* Configure TI1 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4953	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4954	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4955	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4956	}
bogdanm	0:9b334a45a8ff	4957	break;
bogdanm	0:9b334a45a8ff	4958
bogdanm	0:9b334a45a8ff	4959	case TIM_TS_TI2FP2:
bogdanm	0:9b334a45a8ff	4960	{
bogdanm	0:9b334a45a8ff	4961	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4962	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4963	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4964	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4965
bogdanm	0:9b334a45a8ff	4966	/* Configure TI2 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4967	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4968	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4969	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4970	}
bogdanm	0:9b334a45a8ff	4971	break;
bogdanm	0:9b334a45a8ff	4972
bogdanm	0:9b334a45a8ff	4973	case TIM_TS_ITR0:
bogdanm	0:9b334a45a8ff	4974	{
bogdanm	0:9b334a45a8ff	4975	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4976	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4977	}
bogdanm	0:9b334a45a8ff	4978	break;
bogdanm	0:9b334a45a8ff	4979
bogdanm	0:9b334a45a8ff	4980	case TIM_TS_ITR1:
bogdanm	0:9b334a45a8ff	4981	{
bogdanm	0:9b334a45a8ff	4982	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4983	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4984	}
bogdanm	0:9b334a45a8ff	4985	break;
bogdanm	0:9b334a45a8ff	4986
bogdanm	0:9b334a45a8ff	4987	case TIM_TS_ITR2:
bogdanm	0:9b334a45a8ff	4988	{
bogdanm	0:9b334a45a8ff	4989	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4990	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4991	}
bogdanm	0:9b334a45a8ff	4992	break;
bogdanm	0:9b334a45a8ff	4993
bogdanm	0:9b334a45a8ff	4994	case TIM_TS_ITR3:
bogdanm	0:9b334a45a8ff	4995	{
bogdanm	0:9b334a45a8ff	4996	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4997	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4998	}
bogdanm	0:9b334a45a8ff	4999	break;
bogdanm	0:9b334a45a8ff	5000
bogdanm	0:9b334a45a8ff	5001	default:
bogdanm	0:9b334a45a8ff	5002	break;
bogdanm	0:9b334a45a8ff	5003	}
bogdanm	0:9b334a45a8ff	5004	}
bogdanm	0:9b334a45a8ff	5005
bogdanm	0:9b334a45a8ff	5006	/**
bogdanm	0:9b334a45a8ff	5007	* @brief Configure the TI1 as Input.
bogdanm	0:9b334a45a8ff	5008	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5009	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5010	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5011	* @arg TIM_ICPOLARITY_RISING
mbed_official	124:6a4a5b7d7324	5012	* @arg TIM_ICPOLARITY_FALLING
mbed_official	124:6a4a5b7d7324	5013	* @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	5014	* @param TIM_ICSelection : specifies the input to be used.
bogdanm	0:9b334a45a8ff	5015	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5016	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
mbed_official	124:6a4a5b7d7324	5017	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
mbed_official	124:6a4a5b7d7324	5018	* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5019	* @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5020	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5021	* @retval None
bogdanm	0:9b334a45a8ff	5022	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
bogdanm	0:9b334a45a8ff	5023	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	5024	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5025	*/
bogdanm	0:9b334a45a8ff	5026	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5027	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5028	{
bogdanm	0:9b334a45a8ff	5029	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5030	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5031
bogdanm	0:9b334a45a8ff	5032	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5033	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5034	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5035	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5036
bogdanm	0:9b334a45a8ff	5037	/* Select the Input */
bogdanm	0:9b334a45a8ff	5038	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	5039	{
bogdanm	0:9b334a45a8ff	5040	tmpccmr1 &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	5041	tmpccmr1 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	5042	}
bogdanm	0:9b334a45a8ff	5043	else
bogdanm	0:9b334a45a8ff	5044	{
bogdanm	0:9b334a45a8ff	5045	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
bogdanm	0:9b334a45a8ff	5046	}
bogdanm	0:9b334a45a8ff	5047
bogdanm	0:9b334a45a8ff	5048	/* Set the filter */
bogdanm	0:9b334a45a8ff	5049	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5050	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
bogdanm	0:9b334a45a8ff	5051
bogdanm	0:9b334a45a8ff	5052	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	5053	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	5054	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
bogdanm	0:9b334a45a8ff	5055
bogdanm	0:9b334a45a8ff	5056	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5057	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5058	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5059	}
bogdanm	0:9b334a45a8ff	5060
bogdanm	0:9b334a45a8ff	5061	/**
bogdanm	0:9b334a45a8ff	5062	* @brief Configure the Polarity and Filter for TI1.
bogdanm	0:9b334a45a8ff	5063	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5064	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5065	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5066	* @arg TIM_ICPOLARITY_RISING
mbed_official	124:6a4a5b7d7324	5067	* @arg TIM_ICPOLARITY_FALLING
mbed_official	124:6a4a5b7d7324	5068	* @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	5069	* @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5070	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5071	* @retval None
bogdanm	0:9b334a45a8ff	5072	*/
bogdanm	0:9b334a45a8ff	5073	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5074	{
bogdanm	0:9b334a45a8ff	5075	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5076	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5077
bogdanm	0:9b334a45a8ff	5078	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5079	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5080	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5081	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5082
bogdanm	0:9b334a45a8ff	5083	/* Set the filter */
bogdanm	0:9b334a45a8ff	5084	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5085	tmpccmr1 \|= (TIM_ICFilter << 4);
bogdanm	0:9b334a45a8ff	5086
bogdanm	0:9b334a45a8ff	5087	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	5088	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	5089	tmpccer \|= TIM_ICPolarity;
bogdanm	0:9b334a45a8ff	5090
bogdanm	0:9b334a45a8ff	5091	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5092	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5093	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5094	}
bogdanm	0:9b334a45a8ff	5095
bogdanm	0:9b334a45a8ff	5096	/**
bogdanm	0:9b334a45a8ff	5097	* @brief Configure the TI2 as Input.
bogdanm	0:9b334a45a8ff	5098	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5099	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5100	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5101	* @arg TIM_ICPOLARITY_RISING
mbed_official	124:6a4a5b7d7324	5102	* @arg TIM_ICPOLARITY_FALLING
mbed_official	124:6a4a5b7d7324	5103	* @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	5104	* @param TIM_ICSelection : specifies the input to be used.
bogdanm	0:9b334a45a8ff	5105	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5106	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
mbed_official	124:6a4a5b7d7324	5107	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
mbed_official	124:6a4a5b7d7324	5108	* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5109	* @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5110	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5111	* @retval None
bogdanm	0:9b334a45a8ff	5112	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
bogdanm	0:9b334a45a8ff	5113	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	5114	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5115	*/
bogdanm	0:9b334a45a8ff	5116	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5117	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5118	{
bogdanm	0:9b334a45a8ff	5119	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5120	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5121
bogdanm	0:9b334a45a8ff	5122	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	5123	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	5124	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5125	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5126
bogdanm	0:9b334a45a8ff	5127	/* Select the Input */
bogdanm	0:9b334a45a8ff	5128	tmpccmr1 &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	5129	tmpccmr1 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5130
bogdanm	0:9b334a45a8ff	5131	/* Set the filter */
bogdanm	0:9b334a45a8ff	5132	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5133	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	5134
bogdanm	0:9b334a45a8ff	5135	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5136	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5137	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
bogdanm	0:9b334a45a8ff	5138
bogdanm	0:9b334a45a8ff	5139	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5140	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5141	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5142	}
bogdanm	0:9b334a45a8ff	5143
bogdanm	0:9b334a45a8ff	5144	/**
bogdanm	0:9b334a45a8ff	5145	* @brief Configure the Polarity and Filter for TI2.
bogdanm	0:9b334a45a8ff	5146	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5147	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5148	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5149	* @arg TIM_ICPOLARITY_RISING
mbed_official	124:6a4a5b7d7324	5150	* @arg TIM_ICPOLARITY_FALLING
mbed_official	124:6a4a5b7d7324	5151	* @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	5152	* @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5153	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5154	* @retval None
bogdanm	0:9b334a45a8ff	5155	*/
bogdanm	0:9b334a45a8ff	5156	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5157	{
bogdanm	0:9b334a45a8ff	5158	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5159	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5160
bogdanm	0:9b334a45a8ff	5161	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	5162	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	5163	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5164	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5165
bogdanm	0:9b334a45a8ff	5166	/* Set the filter */
bogdanm	0:9b334a45a8ff	5167	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5168	tmpccmr1 \|= (TIM_ICFilter << 12);
bogdanm	0:9b334a45a8ff	5169
bogdanm	0:9b334a45a8ff	5170	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5171	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5172	tmpccer \|= (TIM_ICPolarity << 4);
bogdanm	0:9b334a45a8ff	5173
bogdanm	0:9b334a45a8ff	5174	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5175	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5176	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5177	}
bogdanm	0:9b334a45a8ff	5178
bogdanm	0:9b334a45a8ff	5179	/**
bogdanm	0:9b334a45a8ff	5180	* @brief Configure the TI3 as Input.
bogdanm	0:9b334a45a8ff	5181	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5182	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5183	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5184	* @arg TIM_ICPOLARITY_RISING
mbed_official	124:6a4a5b7d7324	5185	* @arg TIM_ICPOLARITY_FALLING
mbed_official	124:6a4a5b7d7324	5186	* @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	5187	* @param TIM_ICSelection : specifies the input to be used.
bogdanm	0:9b334a45a8ff	5188	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5189	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
mbed_official	124:6a4a5b7d7324	5190	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
mbed_official	124:6a4a5b7d7324	5191	* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5192	* @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5193	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5194	* @retval None
bogdanm	0:9b334a45a8ff	5195	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
bogdanm	0:9b334a45a8ff	5196	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5197	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5198	*/
bogdanm	0:9b334a45a8ff	5199	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5200	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5201	{
bogdanm	0:9b334a45a8ff	5202	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5203	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5204
bogdanm	0:9b334a45a8ff	5205	/* Disable the Channel 3: Reset the CC3E Bit */
bogdanm	0:9b334a45a8ff	5206	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	5207	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5208	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5209
bogdanm	0:9b334a45a8ff	5210	/* Select the Input */
bogdanm	0:9b334a45a8ff	5211	tmpccmr2 &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	5212	tmpccmr2 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	5213
bogdanm	0:9b334a45a8ff	5214	/* Set the filter */
bogdanm	0:9b334a45a8ff	5215	tmpccmr2 &= ~TIM_CCMR2_IC3F;
bogdanm	0:9b334a45a8ff	5216	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
bogdanm	0:9b334a45a8ff	5217
bogdanm	0:9b334a45a8ff	5218	/* Select the Polarity and set the CC3E Bit */
bogdanm	0:9b334a45a8ff	5219	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
bogdanm	0:9b334a45a8ff	5220	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
bogdanm	0:9b334a45a8ff	5221
bogdanm	0:9b334a45a8ff	5222	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5223	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5224	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5225	}
bogdanm	0:9b334a45a8ff	5226
bogdanm	0:9b334a45a8ff	5227	/**
bogdanm	0:9b334a45a8ff	5228	* @brief Configure the TI4 as Input.
bogdanm	0:9b334a45a8ff	5229	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5230	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5231	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5232	* @arg TIM_ICPOLARITY_RISING
mbed_official	124:6a4a5b7d7324	5233	* @arg TIM_ICPOLARITY_FALLING
mbed_official	124:6a4a5b7d7324	5234	* @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	5235	* @param TIM_ICSelection : specifies the input to be used.
bogdanm	0:9b334a45a8ff	5236	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5237	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
mbed_official	124:6a4a5b7d7324	5238	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
mbed_official	124:6a4a5b7d7324	5239	* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5240	* @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5241	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5242	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
bogdanm	0:9b334a45a8ff	5243	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5244	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5245	* @retval None
bogdanm	0:9b334a45a8ff	5246	*/
bogdanm	0:9b334a45a8ff	5247	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5248	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5249	{
bogdanm	0:9b334a45a8ff	5250	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5251	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5252
bogdanm	0:9b334a45a8ff	5253	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	5254	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	5255	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5256	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5257
bogdanm	0:9b334a45a8ff	5258	/* Select the Input */
bogdanm	0:9b334a45a8ff	5259	tmpccmr2 &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	5260	tmpccmr2 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5261
bogdanm	0:9b334a45a8ff	5262	/* Set the filter */
bogdanm	0:9b334a45a8ff	5263	tmpccmr2 &= ~TIM_CCMR2_IC4F;
bogdanm	0:9b334a45a8ff	5264	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
bogdanm	0:9b334a45a8ff	5265
bogdanm	0:9b334a45a8ff	5266	/* Select the Polarity and set the CC4E Bit */
bogdanm	0:9b334a45a8ff	5267	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
bogdanm	0:9b334a45a8ff	5268	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
bogdanm	0:9b334a45a8ff	5269
bogdanm	0:9b334a45a8ff	5270	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5271	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5272	TIMx->CCER = tmpccer ;
bogdanm	0:9b334a45a8ff	5273	}
bogdanm	0:9b334a45a8ff	5274
bogdanm	0:9b334a45a8ff	5275	/**
bogdanm	0:9b334a45a8ff	5276	* @brief Selects the Input Trigger source
bogdanm	0:9b334a45a8ff	5277	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5278	* @param InputTriggerSource : The Input Trigger source.
bogdanm	0:9b334a45a8ff	5279	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5280	* @arg TIM_TS_ITR0 : Internal Trigger 0
bogdanm	0:9b334a45a8ff	5281	* @arg TIM_TS_ITR1 : Internal Trigger 1
bogdanm	0:9b334a45a8ff	5282	* @arg TIM_TS_ITR2 : Internal Trigger 2
bogdanm	0:9b334a45a8ff	5283	* @arg TIM_TS_ITR3 : Internal Trigger 3
bogdanm	0:9b334a45a8ff	5284	* @arg TIM_TS_TI1F_ED : TI1 Edge Detector
bogdanm	0:9b334a45a8ff	5285	* @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
bogdanm	0:9b334a45a8ff	5286	* @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
bogdanm	0:9b334a45a8ff	5287	* @arg TIM_TS_ETRF : External Trigger input
bogdanm	0:9b334a45a8ff	5288	* @retval None
bogdanm	0:9b334a45a8ff	5289	*/
bogdanm	0:9b334a45a8ff	5290	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
bogdanm	0:9b334a45a8ff	5291	{
bogdanm	0:9b334a45a8ff	5292	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5293
bogdanm	0:9b334a45a8ff	5294	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	5295	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5296	/* Reset the TS Bits */
bogdanm	0:9b334a45a8ff	5297	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	5298	/* Set the Input Trigger source and the slave mode*/
bogdanm	0:9b334a45a8ff	5299	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
bogdanm	0:9b334a45a8ff	5300	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5301	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5302	}
bogdanm	0:9b334a45a8ff	5303	/**
bogdanm	0:9b334a45a8ff	5304	* @brief Configures the TIMx External Trigger (ETR).
bogdanm	0:9b334a45a8ff	5305	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5306	* @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
bogdanm	0:9b334a45a8ff	5307	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5308	* @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
mbed_official	124:6a4a5b7d7324	5309	* @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
mbed_official	124:6a4a5b7d7324	5310	* @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
mbed_official	124:6a4a5b7d7324	5311	* @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
bogdanm	0:9b334a45a8ff	5312	* @param TIM_ExtTRGPolarity : The external Trigger Polarity.
bogdanm	0:9b334a45a8ff	5313	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5314	* @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
mbed_official	124:6a4a5b7d7324	5315	* @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
bogdanm	0:9b334a45a8ff	5316	* @param ExtTRGFilter : External Trigger Filter.
bogdanm	0:9b334a45a8ff	5317	* This parameter must be a value between 0x00 and 0x0F
bogdanm	0:9b334a45a8ff	5318	* @retval None
bogdanm	0:9b334a45a8ff	5319	*/
bogdanm	0:9b334a45a8ff	5320	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	5321	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
bogdanm	0:9b334a45a8ff	5322	{
bogdanm	0:9b334a45a8ff	5323	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5324
bogdanm	0:9b334a45a8ff	5325	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5326
bogdanm	0:9b334a45a8ff	5327	/* Reset the ETR Bits */
bogdanm	0:9b334a45a8ff	5328	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	5329
bogdanm	0:9b334a45a8ff	5330	/* Set the Prescaler, the Filter value and the Polarity */
bogdanm	0:9b334a45a8ff	5331	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
bogdanm	0:9b334a45a8ff	5332
bogdanm	0:9b334a45a8ff	5333	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5334	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5335	}
bogdanm	0:9b334a45a8ff	5336
bogdanm	0:9b334a45a8ff	5337	/**
bogdanm	0:9b334a45a8ff	5338	* @brief Enables or disables the TIM Capture Compare Channel x.
bogdanm	0:9b334a45a8ff	5339	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5340	* @param Channel : specifies the TIM Channel
bogdanm	0:9b334a45a8ff	5341	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	5342	* @arg TIM_CHANNEL_1: TIM Channel 1
mbed_official	124:6a4a5b7d7324	5343	* @arg TIM_CHANNEL_2: TIM Channel 2
mbed_official	124:6a4a5b7d7324	5344	* @arg TIM_CHANNEL_3: TIM Channel 3
mbed_official	124:6a4a5b7d7324	5345	* @arg TIM_CHANNEL_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	5346	* @param ChannelState : specifies the TIM Channel CCxE bit new state.
bogdanm	0:9b334a45a8ff	5347	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
bogdanm	0:9b334a45a8ff	5348	* @retval None
bogdanm	0:9b334a45a8ff	5349	*/
bogdanm	0:9b334a45a8ff	5350	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
bogdanm	0:9b334a45a8ff	5351	{
bogdanm	0:9b334a45a8ff	5352	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	5353
bogdanm	0:9b334a45a8ff	5354	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5355	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
bogdanm	0:9b334a45a8ff	5356	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	5357
bogdanm	0:9b334a45a8ff	5358	tmp = TIM_CCER_CC1E << Channel;
bogdanm	0:9b334a45a8ff	5359
bogdanm	0:9b334a45a8ff	5360	/* Reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5361	TIMx->CCER &= ~tmp;
bogdanm	0:9b334a45a8ff	5362
bogdanm	0:9b334a45a8ff	5363	/* Set or reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5364	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
bogdanm	0:9b334a45a8ff	5365	}
bogdanm	0:9b334a45a8ff	5366
bogdanm	0:9b334a45a8ff	5367	/**
bogdanm	0:9b334a45a8ff	5368	* @}
bogdanm	0:9b334a45a8ff	5369	*/
bogdanm	0:9b334a45a8ff	5370
bogdanm	0:9b334a45a8ff	5371	#endif /* HAL_TIM_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	5372	/**
bogdanm	0:9b334a45a8ff	5373	* @}
bogdanm	0:9b334a45a8ff	5374	*/
bogdanm	0:9b334a45a8ff	5375
bogdanm	0:9b334a45a8ff	5376	/**
bogdanm	0:9b334a45a8ff	5377	* @}
bogdanm	0:9b334a45a8ff	5378	*/
bogdanm	0:9b334a45a8ff	5379	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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