en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
124:6a4a5b7d7324 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_spi_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 124:6a4a5b7d7324 5 * @version V1.0.4
mbed_official 124:6a4a5b7d7324 6 * @date 29-April-2016
bogdanm 0:9b334a45a8ff 7 * @brief Extended SPI HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities SPI extension peripheral:
bogdanm 0:9b334a45a8ff 11 * + Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 ******************************************************************************
bogdanm 0:9b334a45a8ff 14 * @attention
bogdanm 0:9b334a45a8ff 15 *
mbed_official 124:6a4a5b7d7324 16 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 19 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 20 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 21 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 23 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 24 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 26 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 27 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 39 *
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 44 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 */
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /** @addtogroup SPI
bogdanm 0:9b334a45a8ff 51 * @{
bogdanm 0:9b334a45a8ff 52 */
bogdanm 0:9b334a45a8ff 53 #ifdef HAL_SPI_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 /** @defgroup SPI_Private_Variables SPI Private Variables
bogdanm 0:9b334a45a8ff 56 * @{
bogdanm 0:9b334a45a8ff 57 */
bogdanm 0:9b334a45a8ff 58 /* Variable used to determine if device is impacted by implementation of workaround
bogdanm 0:9b334a45a8ff 59 related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
bogdanm 0:9b334a45a8ff 60 - STM32F101CDE/STM32F103CDE
bogdanm 0:9b334a45a8ff 61 - Revision ID : Z
bogdanm 0:9b334a45a8ff 62 - SPI2
bogdanm 0:9b334a45a8ff 63 - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
bogdanm 0:9b334a45a8ff 64 the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
bogdanm 0:9b334a45a8ff 65 + If the value is 0, the complete data transfer is successful.
bogdanm 0:9b334a45a8ff 66 + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
bogdanm 0:9b334a45a8ff 67 If CRCERR is found reset, the complete data transfer is considered successful.
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69 uint8_t uCRCErrorWorkaroundCheck = 0;
bogdanm 0:9b334a45a8ff 70 /**
bogdanm 0:9b334a45a8ff 71 * @}
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 76 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 77 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 78 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 79 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 80 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 /** @addtogroup SPI_Exported_Functions
bogdanm 0:9b334a45a8ff 83 * @{
bogdanm 0:9b334a45a8ff 84 */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 /** @addtogroup SPI_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 87 *
bogdanm 0:9b334a45a8ff 88 * @{
bogdanm 0:9b334a45a8ff 89 */
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /**
bogdanm 0:9b334a45a8ff 92 * @brief Initializes the SPI according to the specified parameters
bogdanm 0:9b334a45a8ff 93 * in the SPI_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 94 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 95 * the configuration information for SPI module.
bogdanm 0:9b334a45a8ff 96 * @retval HAL status
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm 0:9b334a45a8ff 99 {
bogdanm 0:9b334a45a8ff 100 /* Check the SPI handle allocation */
bogdanm 0:9b334a45a8ff 101 if(hspi == NULL)
bogdanm 0:9b334a45a8ff 102 {
bogdanm 0:9b334a45a8ff 103 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 104 }
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /* Check the parameters */
bogdanm 0:9b334a45a8ff 107 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm 0:9b334a45a8ff 108 assert_param(IS_SPI_MODE(hspi->Init.Mode));
bogdanm 0:9b334a45a8ff 109 assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
bogdanm 0:9b334a45a8ff 110 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
bogdanm 0:9b334a45a8ff 111 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
bogdanm 0:9b334a45a8ff 112 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
bogdanm 0:9b334a45a8ff 113 assert_param(IS_SPI_NSS(hspi->Init.NSS));
bogdanm 0:9b334a45a8ff 114 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
bogdanm 0:9b334a45a8ff 115 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
bogdanm 0:9b334a45a8ff 116 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
bogdanm 0:9b334a45a8ff 117 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
bogdanm 0:9b334a45a8ff 118 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 if(hspi->State == HAL_SPI_STATE_RESET)
bogdanm 0:9b334a45a8ff 121 {
bogdanm 0:9b334a45a8ff 122 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
bogdanm 0:9b334a45a8ff 123 HAL_SPI_MspInit(hspi);
bogdanm 0:9b334a45a8ff 124 }
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 hspi->State = HAL_SPI_STATE_BUSY;
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Disble the selected SPI peripheral */
bogdanm 0:9b334a45a8ff 129 __HAL_SPI_DISABLE(hspi);
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
bogdanm 0:9b334a45a8ff 132 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
bogdanm 0:9b334a45a8ff 133 Communication speed, First bit and CRC calculation state */
bogdanm 0:9b334a45a8ff 134 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
bogdanm 0:9b334a45a8ff 135 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
bogdanm 0:9b334a45a8ff 136 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Configure : NSS management */
bogdanm 0:9b334a45a8ff 139 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode));
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
bogdanm 0:9b334a45a8ff 142 /* Configure : CRC Polynomial */
bogdanm 0:9b334a45a8ff 143 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 #if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
bogdanm 0:9b334a45a8ff 146 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
bogdanm 0:9b334a45a8ff 147 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
bogdanm 0:9b334a45a8ff 148 #endif
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 #if defined (STM32F101xE) || defined (STM32F103xE)
bogdanm 0:9b334a45a8ff 151 /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
bogdanm 0:9b334a45a8ff 152 CRC errors wrongly detected */
bogdanm 0:9b334a45a8ff 153 /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
bogdanm 0:9b334a45a8ff 154 Revision ID information is only available in Debug mode, so Workaround could not be implemented
bogdanm 0:9b334a45a8ff 155 to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
bogdanm 0:9b334a45a8ff 156 So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
bogdanm 0:9b334a45a8ff 157 uCRCErrorWorkaroundCheck = 0;
bogdanm 0:9b334a45a8ff 158 #else
bogdanm 0:9b334a45a8ff 159 uCRCErrorWorkaroundCheck = 0;
bogdanm 0:9b334a45a8ff 160 #endif
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm 0:9b334a45a8ff 163 hspi->State = HAL_SPI_STATE_READY;
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 return HAL_OK;
bogdanm 0:9b334a45a8ff 166 }
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /**
bogdanm 0:9b334a45a8ff 169 * @}
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /**
bogdanm 0:9b334a45a8ff 173 * @}
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /** @addtogroup SPI_Private_Functions
bogdanm 0:9b334a45a8ff 177 * @{
bogdanm 0:9b334a45a8ff 178 */
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /**
bogdanm 0:9b334a45a8ff 181 * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
bogdanm 0:9b334a45a8ff 182 * according to SPI instance, Device type, and revision ID.
bogdanm 0:9b334a45a8ff 183 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 184 * the configuration information for SPI module.
bogdanm 0:9b334a45a8ff 185 * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
bogdanm 0:9b334a45a8ff 186 */
bogdanm 0:9b334a45a8ff 187 uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
bogdanm 0:9b334a45a8ff 188 {
bogdanm 0:9b334a45a8ff 189 #if defined (STM32F101xE) || defined (STM32F103xE)
bogdanm 0:9b334a45a8ff 190 /* Check how to handle this CRC error (workaround to be applied or not) */
bogdanm 0:9b334a45a8ff 191 /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
bogdanm 0:9b334a45a8ff 192 if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) )
bogdanm 0:9b334a45a8ff 193 {
bogdanm 0:9b334a45a8ff 194 if (hspi->Instance->RXCRCR == 0)
bogdanm 0:9b334a45a8ff 195 {
bogdanm 0:9b334a45a8ff 196 return (SPI_INVALID_CRC_ERROR);
bogdanm 0:9b334a45a8ff 197 }
bogdanm 0:9b334a45a8ff 198 }
bogdanm 0:9b334a45a8ff 199 return (SPI_VALID_CRC_ERROR);
bogdanm 0:9b334a45a8ff 200 #else
bogdanm 0:9b334a45a8ff 201 return (SPI_VALID_CRC_ERROR);
bogdanm 0:9b334a45a8ff 202 #endif
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204 /**
bogdanm 0:9b334a45a8ff 205 * @}
bogdanm 0:9b334a45a8ff 206 */
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 #endif /* HAL_SPI_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 209 /**
bogdanm 0:9b334a45a8ff 210 * @}
bogdanm 0:9b334a45a8ff 211 */
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /**
bogdanm 0:9b334a45a8ff 214 * @}
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/