mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 124:6a4a5b7d7324

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_spi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	124:6a4a5b7d7324	5	* @version V1.0.4
mbed_official	124:6a4a5b7d7324	6	* @date 29-April-2016
bogdanm	0:9b334a45a8ff	7	* @brief SPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
bogdanm	0:9b334a45a8ff	11	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	12	* + IO operation functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	14	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	The SPI HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	21
bogdanm	0:9b334a45a8ff	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	23	SPI_HandleTypeDef hspi;
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
bogdanm	0:9b334a45a8ff	26	(##) Enable the SPIx interface clock
bogdanm	0:9b334a45a8ff	27	(##) SPI pins configuration
bogdanm	0:9b334a45a8ff	28	(+++) Enable the clock for the SPI GPIOs
bogdanm	0:9b334a45a8ff	29	(+++) Configure these SPI pins as alternate function push-pull
bogdanm	0:9b334a45a8ff	30	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	31	(+++) Configure the SPIx interrupt priority
bogdanm	0:9b334a45a8ff	32	(+++) Enable the NVIC SPI IRQ handle
bogdanm	0:9b334a45a8ff	33	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
bogdanm	0:9b334a45a8ff	35	(+++) Enable the DMAx clock
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	37	(+++) Configure the DMA Tx or Rx Channel
bogdanm	0:9b334a45a8ff	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
bogdanm	0:9b334a45a8ff	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
bogdanm	0:9b334a45a8ff	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
bogdanm	0:9b334a45a8ff	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	46	by calling the customed HAL_SPI_MspInit() API.
bogdanm	0:9b334a45a8ff	47	[..]
bogdanm	0:9b334a45a8ff	48	Circular mode restriction:
bogdanm	0:9b334a45a8ff	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
bogdanm	0:9b334a45a8ff	50	(##) Master 2Lines RxOnly
bogdanm	0:9b334a45a8ff	51	(##) Master 1Line Rx
bogdanm	0:9b334a45a8ff	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
bogdanm	0:9b334a45a8ff	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
bogdanm	0:9b334a45a8ff	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
bogdanm	0:9b334a45a8ff	55
mbed_official	124:6a4a5b7d7324	56	@endverbatim
mbed_official	124:6a4a5b7d7324	57	******************************************************************************
mbed_official	124:6a4a5b7d7324	58	* @attention
mbed_official	124:6a4a5b7d7324	59	*
mbed_official	124:6a4a5b7d7324	60	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
mbed_official	124:6a4a5b7d7324	61	*
mbed_official	124:6a4a5b7d7324	62	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	124:6a4a5b7d7324	63	* are permitted provided that the following conditions are met:
mbed_official	124:6a4a5b7d7324	64	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	124:6a4a5b7d7324	65	* this list of conditions and the following disclaimer.
mbed_official	124:6a4a5b7d7324	66	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	124:6a4a5b7d7324	67	* this list of conditions and the following disclaimer in the documentation
mbed_official	124:6a4a5b7d7324	68	* and/or other materials provided with the distribution.
mbed_official	124:6a4a5b7d7324	69	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	124:6a4a5b7d7324	70	* may be used to endorse or promote products derived from this software
mbed_official	124:6a4a5b7d7324	71	* without specific prior written permission.
mbed_official	124:6a4a5b7d7324	72	*
mbed_official	124:6a4a5b7d7324	73	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	124:6a4a5b7d7324	74	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	124:6a4a5b7d7324	75	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	124:6a4a5b7d7324	76	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	124:6a4a5b7d7324	77	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	124:6a4a5b7d7324	78	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	124:6a4a5b7d7324	79	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	124:6a4a5b7d7324	80	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	124:6a4a5b7d7324	81	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	124:6a4a5b7d7324	82	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	124:6a4a5b7d7324	83	*
mbed_official	124:6a4a5b7d7324	84	******************************************************************************
mbed_official	124:6a4a5b7d7324	85	*/
mbed_official	124:6a4a5b7d7324	86
mbed_official	124:6a4a5b7d7324	87	/*
bogdanm	0:9b334a45a8ff	88	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
bogdanm	0:9b334a45a8ff	89	the following table resume the max SPI frequency reached with data size 8bits/16bits,
bogdanm	0:9b334a45a8ff	90	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	For 8 bits SPI data size transfers :
bogdanm	0:9b334a45a8ff	93	+--------------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	94	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
bogdanm	0:9b334a45a8ff	95	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
bogdanm	0:9b334a45a8ff	96	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
bogdanm	0:9b334a45a8ff	97	\|==================================================================================================\|
bogdanm	0:9b334a45a8ff	98	\| T \| Polling \| fPCLK/8 \| fPCLK/8 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	99	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	100	\| / \| Interrupt \| fPCLK/32 \| fPCLK/32 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	101	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	102	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	103	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
bogdanm	0:9b334a45a8ff	104	\| \| Polling \| fPCLK/4 \| fPCLK/8 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/8 \|
bogdanm	0:9b334a45a8ff	105	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	106	\| R \| Interrupt \| fPCLK/32 \| fPCLK/16 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/16 \|
bogdanm	0:9b334a45a8ff	107	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	108	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/2 \|
bogdanm	0:9b334a45a8ff	109	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
bogdanm	0:9b334a45a8ff	110	\| \| Polling \| fPCLK/4 \| fPCLK/4 \| NA \| NA \| fPCLK/4 \| fPCLK/64 \|
bogdanm	0:9b334a45a8ff	111	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	112	\| T \| Interrupt \| fPCLK/8 \| fPCLK/16 \| NA \| NA \| fPCLK/8 \| fPCLK/128 \|
bogdanm	0:9b334a45a8ff	113	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	114	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
bogdanm	0:9b334a45a8ff	115	+--------------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	For 16 bits SPI data size transfers :
bogdanm	0:9b334a45a8ff	118	+--------------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	119	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
bogdanm	0:9b334a45a8ff	120	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
bogdanm	0:9b334a45a8ff	121	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
bogdanm	0:9b334a45a8ff	122	\|==================================================================================================\|
bogdanm	0:9b334a45a8ff	123	\| T \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	124	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	125	\| / \| Interrupt \| fPCLK/16 \| fPCLK/16 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	126	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	127	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	128	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
bogdanm	0:9b334a45a8ff	129	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| fPCLK/64 \| fPCLK/8 \| fPCLK/64 \| fPCLK/4 \|
bogdanm	0:9b334a45a8ff	130	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	131	\| R \| Interrupt \| fPCLK/16 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \|
bogdanm	0:9b334a45a8ff	132	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	133	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/2 \|
bogdanm	0:9b334a45a8ff	134	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
bogdanm	0:9b334a45a8ff	135	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
bogdanm	0:9b334a45a8ff	136	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	137	\| T \| Interrupt \| fPCLK/4 \| fPCLK/8 \| NA \| NA \| fPCLK/4 \| fPCLK/256 \|
bogdanm	0:9b334a45a8ff	138	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	139	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/32 \|
bogdanm	0:9b334a45a8ff	140	+--------------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	141
mbed_official	124:6a4a5b7d7324	142	note:
mbed_official	124:6a4a5b7d7324	143	The max SPI frequency depend on SPI data size (8bits, 16bits),
mbed_official	124:6a4a5b7d7324	144	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
bogdanm	0:9b334a45a8ff	145
mbed_official	124:6a4a5b7d7324	146	note:
mbed_official	124:6a4a5b7d7324	147	TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
mbed_official	124:6a4a5b7d7324	148	RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
mbed_official	124:6a4a5b7d7324	149	TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
mbed_official	124:6a4a5b7d7324	150
mbed_official	124:6a4a5b7d7324	151	*/
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	154	#include "stm32f1xx_hal.h"
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	157	* @{
bogdanm	0:9b334a45a8ff	158	*/
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	/** @defgroup SPI SPI
bogdanm	0:9b334a45a8ff	161	* @brief SPI HAL module driver
bogdanm	0:9b334a45a8ff	162	* @{
bogdanm	0:9b334a45a8ff	163	*/
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	#ifdef HAL_SPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	168	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	169	/** @defgroup SPI_Private_Constants SPI Private Constants
bogdanm	0:9b334a45a8ff	170	* @{
bogdanm	0:9b334a45a8ff	171	*/
bogdanm	0:9b334a45a8ff	172	#define SPI_TIMEOUT_VALUE 10
bogdanm	0:9b334a45a8ff	173	/**
bogdanm	0:9b334a45a8ff	174	* @}
bogdanm	0:9b334a45a8ff	175	*/
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	178	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	179	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	180	/** @defgroup SPI_Private_Functions SPI Private Functions
bogdanm	0:9b334a45a8ff	181	* @{
bogdanm	0:9b334a45a8ff	182	*/
bogdanm	0:9b334a45a8ff	183	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	184	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	185	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	186	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	187	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	188	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	189	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	190	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	191	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	192	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	193	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	194	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	195	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	196	/**
bogdanm	0:9b334a45a8ff	197	* @}
bogdanm	0:9b334a45a8ff	198	*/
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	/** @defgroup SPI_Exported_Functions SPI Exported Functions
bogdanm	0:9b334a45a8ff	203	* @{
bogdanm	0:9b334a45a8ff	204	*/
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	207	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	208	*
bogdanm	0:9b334a45a8ff	209	@verbatim
bogdanm	0:9b334a45a8ff	210	===============================================================================
bogdanm	0:9b334a45a8ff	211	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	212	===============================================================================
bogdanm	0:9b334a45a8ff	213	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	214	de-initialiaze the SPIx peripheral:
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	(+) User must implement HAL_SPI_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	217	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	(+) Call the function HAL_SPI_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	220	the selected configuration:
bogdanm	0:9b334a45a8ff	221	(++) Mode
bogdanm	0:9b334a45a8ff	222	(++) Direction
bogdanm	0:9b334a45a8ff	223	(++) Data Size
bogdanm	0:9b334a45a8ff	224	(++) Clock Polarity and Phase
bogdanm	0:9b334a45a8ff	225	(++) NSS Management
bogdanm	0:9b334a45a8ff	226	(++) BaudRate Prescaler
bogdanm	0:9b334a45a8ff	227	(++) FirstBit
bogdanm	0:9b334a45a8ff	228	(++) TIMode
bogdanm	0:9b334a45a8ff	229	(++) CRC Calculation
bogdanm	0:9b334a45a8ff	230	(++) CRC Polynomial if CRC enabled
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	233	of the selected SPIx periperal.
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	@endverbatim
bogdanm	0:9b334a45a8ff	236	* @{
bogdanm	0:9b334a45a8ff	237	*/
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	/**
bogdanm	0:9b334a45a8ff	240	* @brief Initializes the SPI according to the specified parameters
bogdanm	0:9b334a45a8ff	241	* in the SPI_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	242	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	243	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	244	* @retval HAL status
bogdanm	0:9b334a45a8ff	245	*/
bogdanm	0:9b334a45a8ff	246	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	247	{
bogdanm	0:9b334a45a8ff	248	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	249	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	250	{
bogdanm	0:9b334a45a8ff	251	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	252	}
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/* Check the parameters */
bogdanm	0:9b334a45a8ff	255	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	256	assert_param(IS_SPI_MODE(hspi->Init.Mode));
bogdanm	0:9b334a45a8ff	257	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	258	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
bogdanm	0:9b334a45a8ff	259	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
bogdanm	0:9b334a45a8ff	260	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
bogdanm	0:9b334a45a8ff	261	assert_param(IS_SPI_NSS(hspi->Init.NSS));
bogdanm	0:9b334a45a8ff	262	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
bogdanm	0:9b334a45a8ff	263	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
bogdanm	0:9b334a45a8ff	264	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	265	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
bogdanm	0:9b334a45a8ff	266	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	if(hspi->State == HAL_SPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	269	{
bogdanm	0:9b334a45a8ff	270	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	271	hspi->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	274	HAL_SPI_MspInit(hspi);
bogdanm	0:9b334a45a8ff	275	}
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/* Disble the selected SPI peripheral */
bogdanm	0:9b334a45a8ff	280	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
bogdanm	0:9b334a45a8ff	283	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
bogdanm	0:9b334a45a8ff	284	Communication speed, First bit and CRC calculation state */
bogdanm	0:9b334a45a8ff	285	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
bogdanm	0:9b334a45a8ff	286	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
bogdanm	0:9b334a45a8ff	287	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	/* Configure : NSS management */
bogdanm	0:9b334a45a8ff	290	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/---------------------------- SPIx CRCPOLY Configuration ------------------/
bogdanm	0:9b334a45a8ff	293	/* Configure : CRC Polynomial */
bogdanm	0:9b334a45a8ff	294	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	297	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	return HAL_OK;
bogdanm	0:9b334a45a8ff	300	}
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/**
bogdanm	0:9b334a45a8ff	303	* @brief DeInitializes the SPI peripheral
bogdanm	0:9b334a45a8ff	304	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	305	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	306	* @retval HAL status
bogdanm	0:9b334a45a8ff	307	*/
bogdanm	0:9b334a45a8ff	308	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	309	{
bogdanm	0:9b334a45a8ff	310	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	311	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	312	{
bogdanm	0:9b334a45a8ff	313	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	314	}
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/* Disable the SPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	319	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	322	HAL_SPI_MspDeInit(hspi);
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	325	hspi->State = HAL_SPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Release Lock */
bogdanm	0:9b334a45a8ff	328	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	return HAL_OK;
bogdanm	0:9b334a45a8ff	331	}
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/**
bogdanm	0:9b334a45a8ff	334	* @brief SPI MSP Init
bogdanm	0:9b334a45a8ff	335	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	336	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	337	* @retval None
bogdanm	0:9b334a45a8ff	338	*/
bogdanm	0:9b334a45a8ff	339	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	340	{
mbed_official	124:6a4a5b7d7324	341	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	342	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	343	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	344	the HAL_SPI_MspInit could be implenetd in the user file
bogdanm	0:9b334a45a8ff	345	*/
bogdanm	0:9b334a45a8ff	346	}
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/**
bogdanm	0:9b334a45a8ff	349	* @brief SPI MSP DeInit
bogdanm	0:9b334a45a8ff	350	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	351	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	352	* @retval None
bogdanm	0:9b334a45a8ff	353	*/
bogdanm	0:9b334a45a8ff	354	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	355	{
mbed_official	124:6a4a5b7d7324	356	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	357	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	358	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	359	the HAL_SPI_MspDeInit could be implenetd in the user file
bogdanm	0:9b334a45a8ff	360	*/
bogdanm	0:9b334a45a8ff	361	}
bogdanm	0:9b334a45a8ff	362
bogdanm	0:9b334a45a8ff	363	/**
bogdanm	0:9b334a45a8ff	364	* @}
bogdanm	0:9b334a45a8ff	365	*/
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	368	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	369	*
bogdanm	0:9b334a45a8ff	370	@verbatim
bogdanm	0:9b334a45a8ff	371	==============================================================================
bogdanm	0:9b334a45a8ff	372	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	373	===============================================================================
bogdanm	0:9b334a45a8ff	374	This subsection provides a set of functions allowing to manage the SPI
bogdanm	0:9b334a45a8ff	375	data transfers.
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	[..] The SPI supports master and slave mode :
bogdanm	0:9b334a45a8ff	378
bogdanm	0:9b334a45a8ff	379	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	380	(++) Blocking mode: The communication is performed in polling mode.
bogdanm	0:9b334a45a8ff	381	The HAL status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	382	after finishing transfer.
bogdanm	0:9b334a45a8ff	383	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	384	or DMA, These APIs return the HAL status.
bogdanm	0:9b334a45a8ff	385	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	386	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	387	using DMA mode.
bogdanm	0:9b334a45a8ff	388	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
bogdanm	0:9b334a45a8ff	389	will be executed respectivelly at the end of the transmit or Receive process
bogdanm	0:9b334a45a8ff	390	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
bogdanm	0:9b334a45a8ff	393	exist for 1Line (simplex) and 2Lines (full duplex) modes.
bogdanm	0:9b334a45a8ff	394
bogdanm	0:9b334a45a8ff	395	@endverbatim
bogdanm	0:9b334a45a8ff	396	* @{
bogdanm	0:9b334a45a8ff	397	*/
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	/**
bogdanm	0:9b334a45a8ff	400	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	401	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	402	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	403	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	404	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	405	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	406	* @retval HAL status
bogdanm	0:9b334a45a8ff	407	*/
bogdanm	0:9b334a45a8ff	408	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	409	{
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	412	{
bogdanm	0:9b334a45a8ff	413	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	414	{
bogdanm	0:9b334a45a8ff	415	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	416	}
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/* Check the parameters */
bogdanm	0:9b334a45a8ff	419	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/* Process Locked */
bogdanm	0:9b334a45a8ff	422	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/* Configure communication */
bogdanm	0:9b334a45a8ff	425	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	426	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	429	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	430	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	433	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	434	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	435	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	436	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	437	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	440	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	441	{
bogdanm	0:9b334a45a8ff	442	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	443	}
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	446	{
bogdanm	0:9b334a45a8ff	447	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	448	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	449	}
bogdanm	0:9b334a45a8ff	450
bogdanm	0:9b334a45a8ff	451	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	452	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	453	{
bogdanm	0:9b334a45a8ff	454	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	455	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	456	}
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	459	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	462	{
bogdanm	0:9b334a45a8ff	463	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	464	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	465	}
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	468	{
bogdanm	0:9b334a45a8ff	469	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	470	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	471	{
bogdanm	0:9b334a45a8ff	472	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	473	}
bogdanm	0:9b334a45a8ff	474	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	475	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	476	}
bogdanm	0:9b334a45a8ff	477	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	478	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	481	}
bogdanm	0:9b334a45a8ff	482	}
bogdanm	0:9b334a45a8ff	483	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	484	else
bogdanm	0:9b334a45a8ff	485	{
bogdanm	0:9b334a45a8ff	486	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	487	{
bogdanm	0:9b334a45a8ff	488	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	489	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	490	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	491	}
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	494	{
bogdanm	0:9b334a45a8ff	495	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	496	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	497	{
bogdanm	0:9b334a45a8ff	498	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	499	}
bogdanm	0:9b334a45a8ff	500	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	501	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	502	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	503	}
bogdanm	0:9b334a45a8ff	504	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	505	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	506	{
bogdanm	0:9b334a45a8ff	507	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	508	}
bogdanm	0:9b334a45a8ff	509	}
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	512	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	513	{
bogdanm	0:9b334a45a8ff	514	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	515	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	516	}
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	519	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	520	{
bogdanm	0:9b334a45a8ff	521	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	522	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	523	}
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	526	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	527	{
bogdanm	0:9b334a45a8ff	528	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	534	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	return HAL_OK;
bogdanm	0:9b334a45a8ff	537	}
bogdanm	0:9b334a45a8ff	538	else
bogdanm	0:9b334a45a8ff	539	{
bogdanm	0:9b334a45a8ff	540	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	541	}
bogdanm	0:9b334a45a8ff	542	}
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/**
bogdanm	0:9b334a45a8ff	545	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	546	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	547	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	548	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	549	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	550	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	551	* @retval HAL status
bogdanm	0:9b334a45a8ff	552	*/
bogdanm	0:9b334a45a8ff	553	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	554	{
bogdanm	0:9b334a45a8ff	555	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	558	{
bogdanm	0:9b334a45a8ff	559	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	560	{
bogdanm	0:9b334a45a8ff	561	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	562	}
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564	/* Process Locked */
bogdanm	0:9b334a45a8ff	565	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/* Configure communication */
bogdanm	0:9b334a45a8ff	568	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	569	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	572	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	573	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	576	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	577	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	578	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	579	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	580	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	581
bogdanm	0:9b334a45a8ff	582	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	583	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	584	{
bogdanm	0:9b334a45a8ff	585	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	586	}
bogdanm	0:9b334a45a8ff	587
bogdanm	0:9b334a45a8ff	588	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	589	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	590	{
bogdanm	0:9b334a45a8ff	591	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	592	}
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	595	{
bogdanm	0:9b334a45a8ff	596	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	597	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	600	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
bogdanm	0:9b334a45a8ff	601	}
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	604	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	605	{
bogdanm	0:9b334a45a8ff	606	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	607	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	608	}
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	611	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	612	{
bogdanm	0:9b334a45a8ff	613	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	614	{
bogdanm	0:9b334a45a8ff	615	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	616	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	617	{
bogdanm	0:9b334a45a8ff	618	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	619	}
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	622	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	623	}
bogdanm	0:9b334a45a8ff	624	/* Enable CRC Reception */
bogdanm	0:9b334a45a8ff	625	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	626	{
bogdanm	0:9b334a45a8ff	627	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	628	}
bogdanm	0:9b334a45a8ff	629	}
bogdanm	0:9b334a45a8ff	630	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	631	else
bogdanm	0:9b334a45a8ff	632	{
bogdanm	0:9b334a45a8ff	633	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	634	{
bogdanm	0:9b334a45a8ff	635	/* Wait until RXNE flag is set to read data */
bogdanm	0:9b334a45a8ff	636	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	637	{
bogdanm	0:9b334a45a8ff	638	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	639	}
bogdanm	0:9b334a45a8ff	640
bogdanm	0:9b334a45a8ff	641	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	642	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	643	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	644	}
bogdanm	0:9b334a45a8ff	645	/* Enable CRC Reception */
bogdanm	0:9b334a45a8ff	646	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	647	{
bogdanm	0:9b334a45a8ff	648	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	649	}
bogdanm	0:9b334a45a8ff	650	}
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	653	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	654	{
bogdanm	0:9b334a45a8ff	655	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	/* Receive last data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	659	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	660	{
bogdanm	0:9b334a45a8ff	661	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	662	}
bogdanm	0:9b334a45a8ff	663	/* Receive last data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	664	else
bogdanm	0:9b334a45a8ff	665	{
bogdanm	0:9b334a45a8ff	666	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	667	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	668	}
bogdanm	0:9b334a45a8ff	669	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* If CRC computation is enabled */
bogdanm	0:9b334a45a8ff	672	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	/* Wait until RXNE flag is set: CRC Received */
bogdanm	0:9b334a45a8ff	675	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	676	{
bogdanm	0:9b334a45a8ff	677	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	678	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	679	}
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	/* Read CRC to clear RXNE flag */
bogdanm	0:9b334a45a8ff	682	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	683	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	684	}
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	687	{
bogdanm	0:9b334a45a8ff	688	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	689	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	690	}
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	695	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
bogdanm	0:9b334a45a8ff	696	{
bogdanm	0:9b334a45a8ff	697	/* Check if CRC error is valid or not (workaround to be applied or not) */
bogdanm	0:9b334a45a8ff	698	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
bogdanm	0:9b334a45a8ff	699	{
bogdanm	0:9b334a45a8ff	700	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	701
bogdanm	0:9b334a45a8ff	702	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	703	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	706	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	709	}
bogdanm	0:9b334a45a8ff	710	else
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	713	}
bogdanm	0:9b334a45a8ff	714	}
bogdanm	0:9b334a45a8ff	715
bogdanm	0:9b334a45a8ff	716	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	717	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	return HAL_OK;
bogdanm	0:9b334a45a8ff	720	}
bogdanm	0:9b334a45a8ff	721	else
bogdanm	0:9b334a45a8ff	722	{
bogdanm	0:9b334a45a8ff	723	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	724	}
bogdanm	0:9b334a45a8ff	725	}
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	/**
bogdanm	0:9b334a45a8ff	728	* @brief Transmit and Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	729	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	730	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	731	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	732	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	733	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	734	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	735	* @retval HAL status
bogdanm	0:9b334a45a8ff	736	*/
bogdanm	0:9b334a45a8ff	737	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	738	{
bogdanm	0:9b334a45a8ff	739	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	740
bogdanm	0:9b334a45a8ff	741	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
bogdanm	0:9b334a45a8ff	742	{
bogdanm	0:9b334a45a8ff	743	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	744	{
bogdanm	0:9b334a45a8ff	745	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	746	}
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	/* Check the parameters */
bogdanm	0:9b334a45a8ff	749	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	750
bogdanm	0:9b334a45a8ff	751	/* Process Locked */
bogdanm	0:9b334a45a8ff	752	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	755	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	756	{
bogdanm	0:9b334a45a8ff	757	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	758	}
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	/* Configure communication */
bogdanm	0:9b334a45a8ff	761	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	764	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	765	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	768	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	769	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	772	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	773	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	776	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	777	{
bogdanm	0:9b334a45a8ff	778	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	779	}
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	782	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	783	{
bogdanm	0:9b334a45a8ff	784	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	785	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	/* Transmit and Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	789	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	790	{
bogdanm	0:9b334a45a8ff	791	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	792	{
bogdanm	0:9b334a45a8ff	793	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	794	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	795	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	796	}
bogdanm	0:9b334a45a8ff	797	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	798	{
bogdanm	0:9b334a45a8ff	799	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	800	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	803	}
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	806	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	807	{
bogdanm	0:9b334a45a8ff	808	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	812	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	813	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	814	}
bogdanm	0:9b334a45a8ff	815	else
bogdanm	0:9b334a45a8ff	816	{
bogdanm	0:9b334a45a8ff	817	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	818	{
bogdanm	0:9b334a45a8ff	819	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	820	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	821	{
bogdanm	0:9b334a45a8ff	822	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	823	}
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	826	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	827	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	830	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	831	{
bogdanm	0:9b334a45a8ff	832	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	833	}
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	836	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	837	{
bogdanm	0:9b334a45a8ff	838	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	839	}
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	842	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	843	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	844	}
bogdanm	0:9b334a45a8ff	845	/* Receive the last byte */
bogdanm	0:9b334a45a8ff	846	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	847	{
bogdanm	0:9b334a45a8ff	848	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	849	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	850	{
bogdanm	0:9b334a45a8ff	851	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	852	}
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	855	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	856	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	857	}
bogdanm	0:9b334a45a8ff	858	}
bogdanm	0:9b334a45a8ff	859	}
bogdanm	0:9b334a45a8ff	860	/* Transmit and Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	861	else
bogdanm	0:9b334a45a8ff	862	{
bogdanm	0:9b334a45a8ff	863	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	864	{
bogdanm	0:9b334a45a8ff	865	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	866	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	867	}
bogdanm	0:9b334a45a8ff	868	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	869	{
bogdanm	0:9b334a45a8ff	870	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	871	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	872	{
bogdanm	0:9b334a45a8ff	873	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	874	}
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	877	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	878	{
bogdanm	0:9b334a45a8ff	879	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	880	}
bogdanm	0:9b334a45a8ff	881
bogdanm	0:9b334a45a8ff	882	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	883	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	884	}
bogdanm	0:9b334a45a8ff	885	else
bogdanm	0:9b334a45a8ff	886	{
bogdanm	0:9b334a45a8ff	887	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	888	{
bogdanm	0:9b334a45a8ff	889	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	890	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	891	{
bogdanm	0:9b334a45a8ff	892	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	893	}
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	896	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	897
bogdanm	0:9b334a45a8ff	898	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	899	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	900	{
bogdanm	0:9b334a45a8ff	901	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	902	}
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	905	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	906	{
bogdanm	0:9b334a45a8ff	907	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	908	}
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	911	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	912	}
bogdanm	0:9b334a45a8ff	913	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	914	{
bogdanm	0:9b334a45a8ff	915	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	916	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	917	{
bogdanm	0:9b334a45a8ff	918	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	919	}
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	922	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	923	}
bogdanm	0:9b334a45a8ff	924	}
bogdanm	0:9b334a45a8ff	925	}
bogdanm	0:9b334a45a8ff	926
bogdanm	0:9b334a45a8ff	927	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	928	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	929	{
bogdanm	0:9b334a45a8ff	930	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	931	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	932	{
bogdanm	0:9b334a45a8ff	933	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	934	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	935	}
bogdanm	0:9b334a45a8ff	936	/* Read CRC */
bogdanm	0:9b334a45a8ff	937	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	938	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	939	}
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	942	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	943	{
bogdanm	0:9b334a45a8ff	944	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	945	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	946	}
bogdanm	0:9b334a45a8ff	947
bogdanm	0:9b334a45a8ff	948	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	951	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
bogdanm	0:9b334a45a8ff	952	{
bogdanm	0:9b334a45a8ff	953	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	958	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	961	}
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	964	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	return HAL_OK;
bogdanm	0:9b334a45a8ff	967	}
bogdanm	0:9b334a45a8ff	968	else
bogdanm	0:9b334a45a8ff	969	{
bogdanm	0:9b334a45a8ff	970	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	971	}
bogdanm	0:9b334a45a8ff	972	}
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	/**
bogdanm	0:9b334a45a8ff	975	* @brief Transmit an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	976	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	977	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	978	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	979	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	980	* @retval HAL status
bogdanm	0:9b334a45a8ff	981	*/
bogdanm	0:9b334a45a8ff	982	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	983	{
bogdanm	0:9b334a45a8ff	984	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	985	{
bogdanm	0:9b334a45a8ff	986	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	987	{
bogdanm	0:9b334a45a8ff	988	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	989	}
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/* Check the parameters */
bogdanm	0:9b334a45a8ff	992	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/* Process Locked */
bogdanm	0:9b334a45a8ff	995	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/* Configure communication */
bogdanm	0:9b334a45a8ff	998	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	999	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	1002	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1003	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1004	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1005
bogdanm	0:9b334a45a8ff	1006	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1007	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1008	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1009	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1010	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1013	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1014	{
bogdanm	0:9b334a45a8ff	1015	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1016	}
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1019	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1020	{
bogdanm	0:9b334a45a8ff	1021	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1022	}
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1025	{
bogdanm	0:9b334a45a8ff	1026	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1027	}
bogdanm	0:9b334a45a8ff	1028	else
bogdanm	0:9b334a45a8ff	1029	{
bogdanm	0:9b334a45a8ff	1030	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1031	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1032	}
bogdanm	0:9b334a45a8ff	1033	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1034	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1037	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1038	{
bogdanm	0:9b334a45a8ff	1039	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1040	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1041	}
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	return HAL_OK;
bogdanm	0:9b334a45a8ff	1044	}
bogdanm	0:9b334a45a8ff	1045	else
bogdanm	0:9b334a45a8ff	1046	{
bogdanm	0:9b334a45a8ff	1047	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1048	}
bogdanm	0:9b334a45a8ff	1049	}
bogdanm	0:9b334a45a8ff	1050
bogdanm	0:9b334a45a8ff	1051	/**
bogdanm	0:9b334a45a8ff	1052	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1053	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1054	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1055	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1056	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1057	* @retval HAL status
bogdanm	0:9b334a45a8ff	1058	*/
bogdanm	0:9b334a45a8ff	1059	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1060	{
bogdanm	0:9b334a45a8ff	1061	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1062	{
bogdanm	0:9b334a45a8ff	1063	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1064	{
bogdanm	0:9b334a45a8ff	1065	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1066	}
bogdanm	0:9b334a45a8ff	1067
bogdanm	0:9b334a45a8ff	1068	/* Process Locked */
bogdanm	0:9b334a45a8ff	1069	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1070
bogdanm	0:9b334a45a8ff	1071	/* Configure communication */
bogdanm	0:9b334a45a8ff	1072	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1073	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	hspi->RxISR = &SPI_RxISR;
bogdanm	0:9b334a45a8ff	1076	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1077	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1078	hspi->RxXferCount = Size ;
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1081	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1082	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1083	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1084	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1087	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1088	{
bogdanm	0:9b334a45a8ff	1089	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1090	}
bogdanm	0:9b334a45a8ff	1091	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1092	{
bogdanm	0:9b334a45a8ff	1093	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1094	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1097	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1098	}
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1101	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1102	{
bogdanm	0:9b334a45a8ff	1103	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1104	}
bogdanm	0:9b334a45a8ff	1105
bogdanm	0:9b334a45a8ff	1106	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1107	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1110	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1113	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1114	process unlock */
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1117	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1118	{
bogdanm	0:9b334a45a8ff	1119	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1120	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1121	}
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	return HAL_OK;
bogdanm	0:9b334a45a8ff	1124	}
bogdanm	0:9b334a45a8ff	1125	else
bogdanm	0:9b334a45a8ff	1126	{
bogdanm	0:9b334a45a8ff	1127	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1128	}
bogdanm	0:9b334a45a8ff	1129	}
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/**
bogdanm	0:9b334a45a8ff	1132	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1133	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1134	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1135	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1136	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	1137	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1138	* @retval HAL status
bogdanm	0:9b334a45a8ff	1139	*/
bogdanm	0:9b334a45a8ff	1140	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1141	{
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1144	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1145	{
bogdanm	0:9b334a45a8ff	1146	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1147	{
bogdanm	0:9b334a45a8ff	1148	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1149	}
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1152	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/* Process locked */
bogdanm	0:9b334a45a8ff	1155	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1158	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1159	{
bogdanm	0:9b334a45a8ff	1160	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1161	}
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	/* Configure communication */
bogdanm	0:9b334a45a8ff	1164	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	1167	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1168	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1169	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	hspi->RxISR = &SPI_2LinesRxISR;
bogdanm	0:9b334a45a8ff	1172	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1173	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1174	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1177	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1178	{
bogdanm	0:9b334a45a8ff	1179	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1180	}
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/* Enable TXE, RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1183	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1186	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1189	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1190	{
bogdanm	0:9b334a45a8ff	1191	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1192	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1193	}
bogdanm	0:9b334a45a8ff	1194
bogdanm	0:9b334a45a8ff	1195	return HAL_OK;
bogdanm	0:9b334a45a8ff	1196	}
bogdanm	0:9b334a45a8ff	1197	else
bogdanm	0:9b334a45a8ff	1198	{
bogdanm	0:9b334a45a8ff	1199	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1200	}
bogdanm	0:9b334a45a8ff	1201	}
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/**
bogdanm	0:9b334a45a8ff	1204	* @brief Transmit an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1205	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1206	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1207	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1208	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1209	* @retval HAL status
bogdanm	0:9b334a45a8ff	1210	*/
bogdanm	0:9b334a45a8ff	1211	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1212	{
bogdanm	0:9b334a45a8ff	1213	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1214	{
bogdanm	0:9b334a45a8ff	1215	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1216	{
bogdanm	0:9b334a45a8ff	1217	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1218	}
bogdanm	0:9b334a45a8ff	1219
bogdanm	0:9b334a45a8ff	1220	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1221	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	/* Process Locked */
bogdanm	0:9b334a45a8ff	1224	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	/* Configure communication */
bogdanm	0:9b334a45a8ff	1227	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1228	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1231	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1232	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1235	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1236	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1237	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1238	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1239	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1242	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1243	{
bogdanm	0:9b334a45a8ff	1244	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1245	}
bogdanm	0:9b334a45a8ff	1246
bogdanm	0:9b334a45a8ff	1247	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1248	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1249	{
bogdanm	0:9b334a45a8ff	1250	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1251	}
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	/* Set the SPI TxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1254	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/* Set the SPI TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1257	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1260	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1263	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1264
bogdanm	0:9b334a45a8ff	1265	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1266	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1269	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1272	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1273	{
bogdanm	0:9b334a45a8ff	1274	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1275	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1276	}
bogdanm	0:9b334a45a8ff	1277
bogdanm	0:9b334a45a8ff	1278	return HAL_OK;
bogdanm	0:9b334a45a8ff	1279	}
bogdanm	0:9b334a45a8ff	1280	else
bogdanm	0:9b334a45a8ff	1281	{
bogdanm	0:9b334a45a8ff	1282	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1283	}
bogdanm	0:9b334a45a8ff	1284	}
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/**
bogdanm	0:9b334a45a8ff	1287	* @brief Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1288	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1289	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1290	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1291	* @note When the CRC feature is enabled the pData Length must be Size + 1.
bogdanm	0:9b334a45a8ff	1292	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1293	* @retval HAL status
bogdanm	0:9b334a45a8ff	1294	*/
bogdanm	0:9b334a45a8ff	1295	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1296	{
bogdanm	0:9b334a45a8ff	1297	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1298	{
bogdanm	0:9b334a45a8ff	1299	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1300	{
bogdanm	0:9b334a45a8ff	1301	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1302	}
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	/* Process Locked */
bogdanm	0:9b334a45a8ff	1305	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	/* Configure communication */
bogdanm	0:9b334a45a8ff	1308	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1309	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1312	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1313	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1316	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1317	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1318	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1319	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1320	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1321
bogdanm	0:9b334a45a8ff	1322	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1323	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1324	{
bogdanm	0:9b334a45a8ff	1325	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1326	}
bogdanm	0:9b334a45a8ff	1327	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1328	{
bogdanm	0:9b334a45a8ff	1329	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1330	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1331
bogdanm	0:9b334a45a8ff	1332	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1333	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1334	}
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1337	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1338	{
bogdanm	0:9b334a45a8ff	1339	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1340	}
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/* Set the SPI RxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1343	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/* Set the SPI Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1346	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1349	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1352	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1353
bogdanm	0:9b334a45a8ff	1354	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1355	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1358	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1361	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1362	{
bogdanm	0:9b334a45a8ff	1363	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1364	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1365	}
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	return HAL_OK;
bogdanm	0:9b334a45a8ff	1368	}
bogdanm	0:9b334a45a8ff	1369	else
bogdanm	0:9b334a45a8ff	1370	{
bogdanm	0:9b334a45a8ff	1371	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1372	}
bogdanm	0:9b334a45a8ff	1373	}
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	/**
bogdanm	0:9b334a45a8ff	1376	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1377	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1378	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1379	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1380	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1381	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
bogdanm	0:9b334a45a8ff	1382	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1383	* @retval HAL status
bogdanm	0:9b334a45a8ff	1384	*/
bogdanm	0:9b334a45a8ff	1385	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1386	{
bogdanm	0:9b334a45a8ff	1387	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1388	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1389	{
bogdanm	0:9b334a45a8ff	1390	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1391	{
bogdanm	0:9b334a45a8ff	1392	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1393	}
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1396	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1397
bogdanm	0:9b334a45a8ff	1398	/* Process locked */
bogdanm	0:9b334a45a8ff	1399	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1402	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1403	{
bogdanm	0:9b334a45a8ff	1404	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1405	}
bogdanm	0:9b334a45a8ff	1406
bogdanm	0:9b334a45a8ff	1407	/* Configure communication */
bogdanm	0:9b334a45a8ff	1408	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	hspi->pTxBuffPtr = (uint8_t*)pTxData;
bogdanm	0:9b334a45a8ff	1411	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1412	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	hspi->pRxBuffPtr = (uint8_t*)pRxData;
bogdanm	0:9b334a45a8ff	1415	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1416	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1419	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1420	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1423	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1424	{
bogdanm	0:9b334a45a8ff	1425	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1426	}
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1429	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1430	{
bogdanm	0:9b334a45a8ff	1431	/* Set the SPI Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1432	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1435	}
bogdanm	0:9b334a45a8ff	1436	else
bogdanm	0:9b334a45a8ff	1437	{
bogdanm	0:9b334a45a8ff	1438	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1439	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1442	}
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1445	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1446
bogdanm	0:9b334a45a8ff	1447	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1448	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1449
bogdanm	0:9b334a45a8ff	1450	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1451	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
bogdanm	0:9b334a45a8ff	1454	is performed in DMA reception complete callback */
bogdanm	0:9b334a45a8ff	1455	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1456	{
bogdanm	0:9b334a45a8ff	1457	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1458	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1459	}
bogdanm	0:9b334a45a8ff	1460	else
bogdanm	0:9b334a45a8ff	1461	{
bogdanm	0:9b334a45a8ff	1462	hspi->hdmatx->XferErrorCallback = NULL;
bogdanm	0:9b334a45a8ff	1463	}
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1466	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1467
bogdanm	0:9b334a45a8ff	1468	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1469	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1470	{
bogdanm	0:9b334a45a8ff	1471	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1472	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1473	}
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1476	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1477
bogdanm	0:9b334a45a8ff	1478	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1479	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	return HAL_OK;
bogdanm	0:9b334a45a8ff	1482	}
bogdanm	0:9b334a45a8ff	1483	else
bogdanm	0:9b334a45a8ff	1484	{
bogdanm	0:9b334a45a8ff	1485	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1486	}
bogdanm	0:9b334a45a8ff	1487	}
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489
bogdanm	0:9b334a45a8ff	1490	/**
bogdanm	0:9b334a45a8ff	1491	* @brief Pauses the DMA Transfer.
bogdanm	0:9b334a45a8ff	1492	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1493	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1494	* @retval HAL status
bogdanm	0:9b334a45a8ff	1495	*/
bogdanm	0:9b334a45a8ff	1496	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1497	{
bogdanm	0:9b334a45a8ff	1498	/* Process Locked */
bogdanm	0:9b334a45a8ff	1499	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1500
bogdanm	0:9b334a45a8ff	1501	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1502	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1503	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1506	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1507
bogdanm	0:9b334a45a8ff	1508	return HAL_OK;
bogdanm	0:9b334a45a8ff	1509	}
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	/**
bogdanm	0:9b334a45a8ff	1512	* @brief Resumes the DMA Transfer.
bogdanm	0:9b334a45a8ff	1513	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1514	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1515	* @retval HAL status
bogdanm	0:9b334a45a8ff	1516	*/
bogdanm	0:9b334a45a8ff	1517	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1518	{
bogdanm	0:9b334a45a8ff	1519	/* Process Locked */
bogdanm	0:9b334a45a8ff	1520	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	/* Enable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1523	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1524	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1527	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1528
bogdanm	0:9b334a45a8ff	1529	return HAL_OK;
bogdanm	0:9b334a45a8ff	1530	}
bogdanm	0:9b334a45a8ff	1531
bogdanm	0:9b334a45a8ff	1532	/**
bogdanm	0:9b334a45a8ff	1533	* @brief Stops the DMA Transfer.
bogdanm	0:9b334a45a8ff	1534	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1535	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1536	* @retval HAL status
bogdanm	0:9b334a45a8ff	1537	*/
bogdanm	0:9b334a45a8ff	1538	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1539	{
bogdanm	0:9b334a45a8ff	1540	/* The Lock is not implemented on this API to allow the user application
bogdanm	0:9b334a45a8ff	1541	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
bogdanm	0:9b334a45a8ff	1542	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
bogdanm	0:9b334a45a8ff	1543	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	1544	*/
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	/* Abort the SPI DMA tx Channel */
bogdanm	0:9b334a45a8ff	1547	if(hspi->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1548	{
bogdanm	0:9b334a45a8ff	1549	HAL_DMA_Abort(hspi->hdmatx);
bogdanm	0:9b334a45a8ff	1550	}
bogdanm	0:9b334a45a8ff	1551	/* Abort the SPI DMA rx Channel */
bogdanm	0:9b334a45a8ff	1552	if(hspi->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1553	{
bogdanm	0:9b334a45a8ff	1554	HAL_DMA_Abort(hspi->hdmarx);
bogdanm	0:9b334a45a8ff	1555	}
bogdanm	0:9b334a45a8ff	1556
bogdanm	0:9b334a45a8ff	1557	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1558	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1559	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	return HAL_OK;
bogdanm	0:9b334a45a8ff	1564	}
bogdanm	0:9b334a45a8ff	1565
bogdanm	0:9b334a45a8ff	1566	/**
bogdanm	0:9b334a45a8ff	1567	* @brief This function handles SPI interrupt request.
bogdanm	0:9b334a45a8ff	1568	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1569	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1570	* @retval None
bogdanm	0:9b334a45a8ff	1571	*/
bogdanm	0:9b334a45a8ff	1572	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1573	{
bogdanm	0:9b334a45a8ff	1574	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
bogdanm	0:9b334a45a8ff	1575	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
bogdanm	0:9b334a45a8ff	1576	{
bogdanm	0:9b334a45a8ff	1577	hspi->RxISR(hspi);
bogdanm	0:9b334a45a8ff	1578	return;
bogdanm	0:9b334a45a8ff	1579	}
bogdanm	0:9b334a45a8ff	1580
bogdanm	0:9b334a45a8ff	1581	/* SPI in mode Tramitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1582	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1583	{
bogdanm	0:9b334a45a8ff	1584	hspi->TxISR(hspi);
bogdanm	0:9b334a45a8ff	1585	return;
bogdanm	0:9b334a45a8ff	1586	}
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
bogdanm	0:9b334a45a8ff	1589	{
bogdanm	0:9b334a45a8ff	1590	/* SPI CRC error interrupt occurred ---------------------------------------*/
bogdanm	0:9b334a45a8ff	1591	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1592	{
bogdanm	0:9b334a45a8ff	1593	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	1594	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1595	}
bogdanm	0:9b334a45a8ff	1596	/* SPI Mode Fault error interrupt occurred --------------------------------*/
bogdanm	0:9b334a45a8ff	1597	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
bogdanm	0:9b334a45a8ff	1598	{
bogdanm	0:9b334a45a8ff	1599	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
bogdanm	0:9b334a45a8ff	1600	__HAL_SPI_CLEAR_MODFFLAG(hspi);
bogdanm	0:9b334a45a8ff	1601	}
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/* SPI Overrun error interrupt occurred -----------------------------------*/
bogdanm	0:9b334a45a8ff	1604	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
bogdanm	0:9b334a45a8ff	1605	{
bogdanm	0:9b334a45a8ff	1606	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1607	{
bogdanm	0:9b334a45a8ff	1608	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
bogdanm	0:9b334a45a8ff	1609	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1610	}
bogdanm	0:9b334a45a8ff	1611	}
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	/* Call the Error call Back in case of Errors */
bogdanm	0:9b334a45a8ff	1614	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1615	{
bogdanm	0:9b334a45a8ff	1616	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	1617	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1618	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1619	}
bogdanm	0:9b334a45a8ff	1620	}
bogdanm	0:9b334a45a8ff	1621	}
bogdanm	0:9b334a45a8ff	1622
bogdanm	0:9b334a45a8ff	1623	/**
bogdanm	0:9b334a45a8ff	1624	* @brief Tx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1625	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1626	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1627	* @retval None
bogdanm	0:9b334a45a8ff	1628	*/
bogdanm	0:9b334a45a8ff	1629	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1630	{
mbed_official	124:6a4a5b7d7324	1631	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1632	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	1633	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1634	the HAL_SPI_TxCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1635	*/
bogdanm	0:9b334a45a8ff	1636	}
bogdanm	0:9b334a45a8ff	1637
bogdanm	0:9b334a45a8ff	1638	/**
bogdanm	0:9b334a45a8ff	1639	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1640	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1641	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1642	* @retval None
bogdanm	0:9b334a45a8ff	1643	*/
bogdanm	0:9b334a45a8ff	1644	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1645	{
mbed_official	124:6a4a5b7d7324	1646	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1647	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	1648	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1649	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1650	*/
bogdanm	0:9b334a45a8ff	1651	}
bogdanm	0:9b334a45a8ff	1652
bogdanm	0:9b334a45a8ff	1653	/**
bogdanm	0:9b334a45a8ff	1654	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1655	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1656	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1657	* @retval None
bogdanm	0:9b334a45a8ff	1658	*/
bogdanm	0:9b334a45a8ff	1659	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1660	{
mbed_official	124:6a4a5b7d7324	1661	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1662	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	1663	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1664	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1665	*/
bogdanm	0:9b334a45a8ff	1666	}
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	/**
bogdanm	0:9b334a45a8ff	1669	* @brief Tx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1670	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1671	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1672	* @retval None
bogdanm	0:9b334a45a8ff	1673	*/
bogdanm	0:9b334a45a8ff	1674	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1675	{
mbed_official	124:6a4a5b7d7324	1676	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1677	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	1678	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1679	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1680	*/
bogdanm	0:9b334a45a8ff	1681	}
bogdanm	0:9b334a45a8ff	1682
bogdanm	0:9b334a45a8ff	1683	/**
bogdanm	0:9b334a45a8ff	1684	* @brief Rx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1685	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1686	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1687	* @retval None
bogdanm	0:9b334a45a8ff	1688	*/
bogdanm	0:9b334a45a8ff	1689	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1690	{
mbed_official	124:6a4a5b7d7324	1691	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1692	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	1693	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1694	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1695	*/
bogdanm	0:9b334a45a8ff	1696	}
bogdanm	0:9b334a45a8ff	1697
bogdanm	0:9b334a45a8ff	1698	/**
bogdanm	0:9b334a45a8ff	1699	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1700	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1701	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1702	* @retval None
bogdanm	0:9b334a45a8ff	1703	*/
bogdanm	0:9b334a45a8ff	1704	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1705	{
mbed_official	124:6a4a5b7d7324	1706	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1707	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	1708	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1709	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1710	*/
bogdanm	0:9b334a45a8ff	1711	}
bogdanm	0:9b334a45a8ff	1712
bogdanm	0:9b334a45a8ff	1713	/**
bogdanm	0:9b334a45a8ff	1714	* @brief SPI error callbacks
bogdanm	0:9b334a45a8ff	1715	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1716	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1717	* @retval None
bogdanm	0:9b334a45a8ff	1718	*/
bogdanm	0:9b334a45a8ff	1719	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1720	{
mbed_official	124:6a4a5b7d7324	1721	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1722	UNUSED(hspi);
bogdanm	0:9b334a45a8ff	1723	/* NOTE : - This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1724	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
bogdanm	0:9b334a45a8ff	1725	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
bogdanm	0:9b334a45a8ff	1726	and user can use HAL_SPI_GetError() API to check the latest error occurred.
bogdanm	0:9b334a45a8ff	1727	*/
bogdanm	0:9b334a45a8ff	1728	}
bogdanm	0:9b334a45a8ff	1729
bogdanm	0:9b334a45a8ff	1730	/**
bogdanm	0:9b334a45a8ff	1731	* @}
bogdanm	0:9b334a45a8ff	1732	*/
bogdanm	0:9b334a45a8ff	1733
bogdanm	0:9b334a45a8ff	1734	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1735	* @brief SPI control functions
bogdanm	0:9b334a45a8ff	1736	*
bogdanm	0:9b334a45a8ff	1737	@verbatim
bogdanm	0:9b334a45a8ff	1738	===============================================================================
bogdanm	0:9b334a45a8ff	1739	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1740	===============================================================================
bogdanm	0:9b334a45a8ff	1741	[..]
bogdanm	0:9b334a45a8ff	1742	This subsection provides a set of functions allowing to control the SPI.
bogdanm	0:9b334a45a8ff	1743	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
bogdanm	0:9b334a45a8ff	1744	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
bogdanm	0:9b334a45a8ff	1745	@endverbatim
bogdanm	0:9b334a45a8ff	1746	* @{
bogdanm	0:9b334a45a8ff	1747	*/
bogdanm	0:9b334a45a8ff	1748
bogdanm	0:9b334a45a8ff	1749	/**
bogdanm	0:9b334a45a8ff	1750	* @brief Return the SPI state
bogdanm	0:9b334a45a8ff	1751	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1752	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1753	* @retval SPI state
bogdanm	0:9b334a45a8ff	1754	*/
bogdanm	0:9b334a45a8ff	1755	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1756	{
bogdanm	0:9b334a45a8ff	1757	return hspi->State;
bogdanm	0:9b334a45a8ff	1758	}
bogdanm	0:9b334a45a8ff	1759
bogdanm	0:9b334a45a8ff	1760	/**
bogdanm	0:9b334a45a8ff	1761	* @brief Return the SPI error code
bogdanm	0:9b334a45a8ff	1762	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1763	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1764	* @retval SPI Error Code
bogdanm	0:9b334a45a8ff	1765	*/
bogdanm	0:9b334a45a8ff	1766	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1767	{
bogdanm	0:9b334a45a8ff	1768	return hspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1769	}
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	/**
bogdanm	0:9b334a45a8ff	1772	* @}
bogdanm	0:9b334a45a8ff	1773	*/
bogdanm	0:9b334a45a8ff	1774
bogdanm	0:9b334a45a8ff	1775	/**
bogdanm	0:9b334a45a8ff	1776	* @}
bogdanm	0:9b334a45a8ff	1777	*/
bogdanm	0:9b334a45a8ff	1778
bogdanm	0:9b334a45a8ff	1779
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	1782	* @{
bogdanm	0:9b334a45a8ff	1783	*/
bogdanm	0:9b334a45a8ff	1784
bogdanm	0:9b334a45a8ff	1785
bogdanm	0:9b334a45a8ff	1786	/**
bogdanm	0:9b334a45a8ff	1787	* @brief Interrupt Handler to close Tx transfer
bogdanm	0:9b334a45a8ff	1788	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1789	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1790	* @retval None
bogdanm	0:9b334a45a8ff	1791	*/
bogdanm	0:9b334a45a8ff	1792	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1793	{
bogdanm	0:9b334a45a8ff	1794	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	1795	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1796	{
bogdanm	0:9b334a45a8ff	1797	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1798	}
bogdanm	0:9b334a45a8ff	1799
bogdanm	0:9b334a45a8ff	1800	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	1801	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1802
bogdanm	0:9b334a45a8ff	1803	/* Disable ERR interrupt if Receive process is finished */
bogdanm	0:9b334a45a8ff	1804	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
bogdanm	0:9b334a45a8ff	1805	{
bogdanm	0:9b334a45a8ff	1806	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1807
bogdanm	0:9b334a45a8ff	1808	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	1809	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1810	{
bogdanm	0:9b334a45a8ff	1811	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1812	}
bogdanm	0:9b334a45a8ff	1813
bogdanm	0:9b334a45a8ff	1814	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	1815	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1816	{
bogdanm	0:9b334a45a8ff	1817	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1818	}
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1821	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1822	{
bogdanm	0:9b334a45a8ff	1823	/* Check if we are in Tx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1824	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1825	{
bogdanm	0:9b334a45a8ff	1826	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1827	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1828	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1829	}
bogdanm	0:9b334a45a8ff	1830	else
bogdanm	0:9b334a45a8ff	1831	{
bogdanm	0:9b334a45a8ff	1832	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1833	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1834	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1835	}
bogdanm	0:9b334a45a8ff	1836	}
bogdanm	0:9b334a45a8ff	1837	else
bogdanm	0:9b334a45a8ff	1838	{
bogdanm	0:9b334a45a8ff	1839	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1840	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1841	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1842	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1843	}
bogdanm	0:9b334a45a8ff	1844	}
bogdanm	0:9b334a45a8ff	1845	}
bogdanm	0:9b334a45a8ff	1846
bogdanm	0:9b334a45a8ff	1847	/**
bogdanm	0:9b334a45a8ff	1848	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1849	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1850	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1851	* @retval None
bogdanm	0:9b334a45a8ff	1852	*/
bogdanm	0:9b334a45a8ff	1853	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1854	{
bogdanm	0:9b334a45a8ff	1855	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1856	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1857	{
bogdanm	0:9b334a45a8ff	1858	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1859	}
bogdanm	0:9b334a45a8ff	1860	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1861	else
bogdanm	0:9b334a45a8ff	1862	{
bogdanm	0:9b334a45a8ff	1863	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	1864	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1865	}
bogdanm	0:9b334a45a8ff	1866	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	1867
bogdanm	0:9b334a45a8ff	1868	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1869	{
bogdanm	0:9b334a45a8ff	1870	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1871	{
bogdanm	0:9b334a45a8ff	1872	/* calculate and transfer CRC on Tx line */
bogdanm	0:9b334a45a8ff	1873	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	1874	}
bogdanm	0:9b334a45a8ff	1875	SPI_TxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1876	}
bogdanm	0:9b334a45a8ff	1877	}
bogdanm	0:9b334a45a8ff	1878
bogdanm	0:9b334a45a8ff	1879	/**
bogdanm	0:9b334a45a8ff	1880	* @brief Interrupt Handler to close Rx transfer
bogdanm	0:9b334a45a8ff	1881	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1882	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1883	* @retval None
bogdanm	0:9b334a45a8ff	1884	*/
bogdanm	0:9b334a45a8ff	1885	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1886	{
bogdanm	0:9b334a45a8ff	1887	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1888
bogdanm	0:9b334a45a8ff	1889	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1890	{
bogdanm	0:9b334a45a8ff	1891	/* Wait until RXNE flag is set to read CRC data */
bogdanm	0:9b334a45a8ff	1892	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1893	{
bogdanm	0:9b334a45a8ff	1894	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1895	}
bogdanm	0:9b334a45a8ff	1896
bogdanm	0:9b334a45a8ff	1897	/* Read CRC to reset RXNE flag */
bogdanm	0:9b334a45a8ff	1898	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1899	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	1900
bogdanm	0:9b334a45a8ff	1901	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	1902	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1903	{
bogdanm	0:9b334a45a8ff	1904	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1905	}
bogdanm	0:9b334a45a8ff	1906
bogdanm	0:9b334a45a8ff	1907	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1908	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1909	{
bogdanm	0:9b334a45a8ff	1910	/* Check if CRC error is valid or not (workaround to be applied or not) */
bogdanm	0:9b334a45a8ff	1911	if ( (hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1912	\|\| (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) )
bogdanm	0:9b334a45a8ff	1913	{
bogdanm	0:9b334a45a8ff	1914	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	1915
bogdanm	0:9b334a45a8ff	1916	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1917	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1918	}
bogdanm	0:9b334a45a8ff	1919	else
bogdanm	0:9b334a45a8ff	1920	{
bogdanm	0:9b334a45a8ff	1921	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1922	}
bogdanm	0:9b334a45a8ff	1923	}
bogdanm	0:9b334a45a8ff	1924	}
bogdanm	0:9b334a45a8ff	1925
bogdanm	0:9b334a45a8ff	1926	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	1927	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
bogdanm	0:9b334a45a8ff	1928
bogdanm	0:9b334a45a8ff	1929	/* if Transmit process is finished */
bogdanm	0:9b334a45a8ff	1930	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
bogdanm	0:9b334a45a8ff	1931	{
bogdanm	0:9b334a45a8ff	1932	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1933	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1934
bogdanm	0:9b334a45a8ff	1935	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	1936	{
bogdanm	0:9b334a45a8ff	1937	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	1938	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	1939	}
bogdanm	0:9b334a45a8ff	1940
bogdanm	0:9b334a45a8ff	1941	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1942	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1943	{
bogdanm	0:9b334a45a8ff	1944	/* Check if we are in Rx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1945	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1946	{
bogdanm	0:9b334a45a8ff	1947	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1948	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1949	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1950	}
bogdanm	0:9b334a45a8ff	1951	else
bogdanm	0:9b334a45a8ff	1952	{
bogdanm	0:9b334a45a8ff	1953	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1954	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1955	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1956	}
bogdanm	0:9b334a45a8ff	1957	}
bogdanm	0:9b334a45a8ff	1958	else
bogdanm	0:9b334a45a8ff	1959	{
bogdanm	0:9b334a45a8ff	1960	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1961	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1962	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1963	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1964	}
bogdanm	0:9b334a45a8ff	1965	}
bogdanm	0:9b334a45a8ff	1966	}
bogdanm	0:9b334a45a8ff	1967
bogdanm	0:9b334a45a8ff	1968	/**
bogdanm	0:9b334a45a8ff	1969	* @brief Interrupt Handler to receive amount of data in 2Lines mode
bogdanm	0:9b334a45a8ff	1970	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1971	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1972	* @retval None
bogdanm	0:9b334a45a8ff	1973	*/
bogdanm	0:9b334a45a8ff	1974	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1975	{
bogdanm	0:9b334a45a8ff	1976	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1977	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1978	{
bogdanm	0:9b334a45a8ff	1979	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1980	}
bogdanm	0:9b334a45a8ff	1981	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1982	else
bogdanm	0:9b334a45a8ff	1983	{
bogdanm	0:9b334a45a8ff	1984	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1985	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1986	}
bogdanm	0:9b334a45a8ff	1987	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	1988
bogdanm	0:9b334a45a8ff	1989	if(hspi->RxXferCount==0)
bogdanm	0:9b334a45a8ff	1990	{
bogdanm	0:9b334a45a8ff	1991	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1992	}
bogdanm	0:9b334a45a8ff	1993	}
bogdanm	0:9b334a45a8ff	1994
bogdanm	0:9b334a45a8ff	1995	/**
bogdanm	0:9b334a45a8ff	1996	* @brief Interrupt Handler to receive amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1997	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1998	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1999	* @retval None
bogdanm	0:9b334a45a8ff	2000	*/
bogdanm	0:9b334a45a8ff	2001	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2002	{
bogdanm	0:9b334a45a8ff	2003	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2004	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	2005	{
bogdanm	0:9b334a45a8ff	2006	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2007	}
bogdanm	0:9b334a45a8ff	2008	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2009	else
bogdanm	0:9b334a45a8ff	2010	{
bogdanm	0:9b334a45a8ff	2011	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2012	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	2013	}
bogdanm	0:9b334a45a8ff	2014	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2015
bogdanm	0:9b334a45a8ff	2016	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2017	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2018	{
bogdanm	0:9b334a45a8ff	2019	/* Set CRC Next to calculate CRC on Rx side */
bogdanm	0:9b334a45a8ff	2020	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	2021	}
bogdanm	0:9b334a45a8ff	2022
bogdanm	0:9b334a45a8ff	2023	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2024	{
bogdanm	0:9b334a45a8ff	2025	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	2026	}
bogdanm	0:9b334a45a8ff	2027	}
bogdanm	0:9b334a45a8ff	2028
bogdanm	0:9b334a45a8ff	2029	/**
bogdanm	0:9b334a45a8ff	2030	* @brief DMA SPI transmit process complete callback
bogdanm	0:9b334a45a8ff	2031	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2032	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2033	* @retval None
bogdanm	0:9b334a45a8ff	2034	*/
bogdanm	0:9b334a45a8ff	2035	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2036	{
bogdanm	0:9b334a45a8ff	2037	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2038
bogdanm	0:9b334a45a8ff	2039	/* DMA Normal Mode */
bogdanm	0:9b334a45a8ff	2040	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	2041	{
bogdanm	0:9b334a45a8ff	2042	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	2043	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2044	{
bogdanm	0:9b334a45a8ff	2045	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2046	}
bogdanm	0:9b334a45a8ff	2047
bogdanm	0:9b334a45a8ff	2048	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2049	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2050
bogdanm	0:9b334a45a8ff	2051	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	2052	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2053	{
bogdanm	0:9b334a45a8ff	2054	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2055	}
bogdanm	0:9b334a45a8ff	2056
bogdanm	0:9b334a45a8ff	2057	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2058	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2059	}
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	2062	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	2063	{
bogdanm	0:9b334a45a8ff	2064	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2065	}
bogdanm	0:9b334a45a8ff	2066
bogdanm	0:9b334a45a8ff	2067	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2068	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2069	{
bogdanm	0:9b334a45a8ff	2070	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2071	}
bogdanm	0:9b334a45a8ff	2072	else
bogdanm	0:9b334a45a8ff	2073	{
bogdanm	0:9b334a45a8ff	2074	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2075	}
bogdanm	0:9b334a45a8ff	2076	}
bogdanm	0:9b334a45a8ff	2077
bogdanm	0:9b334a45a8ff	2078	/**
bogdanm	0:9b334a45a8ff	2079	* @brief DMA SPI receive process complete callback
bogdanm	0:9b334a45a8ff	2080	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2081	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2082	* @retval None
bogdanm	0:9b334a45a8ff	2083	*/
bogdanm	0:9b334a45a8ff	2084	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2085	{
bogdanm	0:9b334a45a8ff	2086	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	2087	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2088
bogdanm	0:9b334a45a8ff	2089	/* DMA Normal mode */
bogdanm	0:9b334a45a8ff	2090	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	2091	{
bogdanm	0:9b334a45a8ff	2092	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2093	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2094
bogdanm	0:9b334a45a8ff	2095	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
bogdanm	0:9b334a45a8ff	2096	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2097
bogdanm	0:9b334a45a8ff	2098	/* CRC Calculation handling */
bogdanm	0:9b334a45a8ff	2099	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2100	{
bogdanm	0:9b334a45a8ff	2101	/* Wait until RXNE flag is set (CRC ready) */
bogdanm	0:9b334a45a8ff	2102	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2103	{
bogdanm	0:9b334a45a8ff	2104	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2105	}
bogdanm	0:9b334a45a8ff	2106
bogdanm	0:9b334a45a8ff	2107	/* Read CRC */
bogdanm	0:9b334a45a8ff	2108	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2109	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	2110
bogdanm	0:9b334a45a8ff	2111	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	2112	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2113	{
bogdanm	0:9b334a45a8ff	2114	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2115	}
bogdanm	0:9b334a45a8ff	2116
bogdanm	0:9b334a45a8ff	2117	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2118	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2119	{
bogdanm	0:9b334a45a8ff	2120	/* Check if CRC error is valid or not (workaround to be applied or not) */
bogdanm	0:9b334a45a8ff	2121	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
bogdanm	0:9b334a45a8ff	2122	{
bogdanm	0:9b334a45a8ff	2123	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	2124
bogdanm	0:9b334a45a8ff	2125	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2126	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2127	}
bogdanm	0:9b334a45a8ff	2128	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2129	}
bogdanm	0:9b334a45a8ff	2130	}
bogdanm	0:9b334a45a8ff	2131
bogdanm	0:9b334a45a8ff	2132	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2133	{
bogdanm	0:9b334a45a8ff	2134	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2135	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2136	}
bogdanm	0:9b334a45a8ff	2137
bogdanm	0:9b334a45a8ff	2138	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2139	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2140
bogdanm	0:9b334a45a8ff	2141	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2142	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2143	{
bogdanm	0:9b334a45a8ff	2144	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2145	}
bogdanm	0:9b334a45a8ff	2146	else
bogdanm	0:9b334a45a8ff	2147	{
bogdanm	0:9b334a45a8ff	2148	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2149	}
bogdanm	0:9b334a45a8ff	2150	}
bogdanm	0:9b334a45a8ff	2151	else
bogdanm	0:9b334a45a8ff	2152	{
bogdanm	0:9b334a45a8ff	2153	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2154	}
bogdanm	0:9b334a45a8ff	2155	}
bogdanm	0:9b334a45a8ff	2156
bogdanm	0:9b334a45a8ff	2157	/**
bogdanm	0:9b334a45a8ff	2158	* @brief DMA SPI transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2159	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2160	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2161	* @retval None
bogdanm	0:9b334a45a8ff	2162	*/
bogdanm	0:9b334a45a8ff	2163	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2164	{
bogdanm	0:9b334a45a8ff	2165	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	2166
bogdanm	0:9b334a45a8ff	2167	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2168
bogdanm	0:9b334a45a8ff	2169	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	2170	{
bogdanm	0:9b334a45a8ff	2171	/* CRC Calculation handling */
bogdanm	0:9b334a45a8ff	2172	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2173	{
bogdanm	0:9b334a45a8ff	2174	/* Check if CRC is done on going (RXNE flag set) */
bogdanm	0:9b334a45a8ff	2175	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
bogdanm	0:9b334a45a8ff	2176	{
bogdanm	0:9b334a45a8ff	2177	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	2178	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2179	{
bogdanm	0:9b334a45a8ff	2180	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2181	}
bogdanm	0:9b334a45a8ff	2182	}
bogdanm	0:9b334a45a8ff	2183	/* Read CRC */
bogdanm	0:9b334a45a8ff	2184	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2185	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	2186
bogdanm	0:9b334a45a8ff	2187	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2188	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2189	{
bogdanm	0:9b334a45a8ff	2190	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	2191	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2192	}
bogdanm	0:9b334a45a8ff	2193	}
bogdanm	0:9b334a45a8ff	2194
bogdanm	0:9b334a45a8ff	2195	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	2196	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2197	{
bogdanm	0:9b334a45a8ff	2198	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2199	}
bogdanm	0:9b334a45a8ff	2200
bogdanm	0:9b334a45a8ff	2201	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2202	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2203
bogdanm	0:9b334a45a8ff	2204	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	2205	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2206	{
bogdanm	0:9b334a45a8ff	2207	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2208	}
bogdanm	0:9b334a45a8ff	2209
bogdanm	0:9b334a45a8ff	2210	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2211	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2212
bogdanm	0:9b334a45a8ff	2213	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2214	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2215
bogdanm	0:9b334a45a8ff	2216	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2217
bogdanm	0:9b334a45a8ff	2218	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2219	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2220	{
bogdanm	0:9b334a45a8ff	2221	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2222	}
bogdanm	0:9b334a45a8ff	2223	else
bogdanm	0:9b334a45a8ff	2224	{
bogdanm	0:9b334a45a8ff	2225	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2226	}
bogdanm	0:9b334a45a8ff	2227	}
bogdanm	0:9b334a45a8ff	2228	else
bogdanm	0:9b334a45a8ff	2229	{
bogdanm	0:9b334a45a8ff	2230	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2231	}
bogdanm	0:9b334a45a8ff	2232	}
bogdanm	0:9b334a45a8ff	2233
bogdanm	0:9b334a45a8ff	2234	/**
bogdanm	0:9b334a45a8ff	2235	* @brief DMA SPI half transmit process complete callback
bogdanm	0:9b334a45a8ff	2236	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2237	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2238	* @retval None
bogdanm	0:9b334a45a8ff	2239	*/
bogdanm	0:9b334a45a8ff	2240	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2241	{
bogdanm	0:9b334a45a8ff	2242	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2243
bogdanm	0:9b334a45a8ff	2244	HAL_SPI_TxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2245	}
bogdanm	0:9b334a45a8ff	2246
bogdanm	0:9b334a45a8ff	2247	/**
bogdanm	0:9b334a45a8ff	2248	* @brief DMA SPI half receive process complete callback
bogdanm	0:9b334a45a8ff	2249	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2250	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2251	* @retval None
bogdanm	0:9b334a45a8ff	2252	*/
bogdanm	0:9b334a45a8ff	2253	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2254	{
bogdanm	0:9b334a45a8ff	2255	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2256
bogdanm	0:9b334a45a8ff	2257	HAL_SPI_RxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2258	}
bogdanm	0:9b334a45a8ff	2259
bogdanm	0:9b334a45a8ff	2260	/**
bogdanm	0:9b334a45a8ff	2261	* @brief DMA SPI Half transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2262	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2263	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2264	* @retval None
bogdanm	0:9b334a45a8ff	2265	*/
bogdanm	0:9b334a45a8ff	2266	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2267	{
bogdanm	0:9b334a45a8ff	2268	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2269
bogdanm	0:9b334a45a8ff	2270	HAL_SPI_TxRxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2271	}
bogdanm	0:9b334a45a8ff	2272
bogdanm	0:9b334a45a8ff	2273	/**
bogdanm	0:9b334a45a8ff	2274	* @brief DMA SPI communication error callback
bogdanm	0:9b334a45a8ff	2275	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2276	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2277	* @retval None
bogdanm	0:9b334a45a8ff	2278	*/
bogdanm	0:9b334a45a8ff	2279	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2280	{
bogdanm	0:9b334a45a8ff	2281	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2282	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2283	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2284	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2285	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
bogdanm	0:9b334a45a8ff	2286	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2287	}
bogdanm	0:9b334a45a8ff	2288
bogdanm	0:9b334a45a8ff	2289	/**
bogdanm	0:9b334a45a8ff	2290	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2291	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2292	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2293	* @param Flag: SPI flag to check
bogdanm	0:9b334a45a8ff	2294	* @param Status: Flag status to check: RESET or set
bogdanm	0:9b334a45a8ff	2295	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	2296	* @retval HAL status
bogdanm	0:9b334a45a8ff	2297	*/
bogdanm	0:9b334a45a8ff	2298	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2299	{
bogdanm	0:9b334a45a8ff	2300	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2301
bogdanm	0:9b334a45a8ff	2302	/* Get tick */
bogdanm	0:9b334a45a8ff	2303	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2304
bogdanm	0:9b334a45a8ff	2305	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	2306	if(Status == RESET)
bogdanm	0:9b334a45a8ff	2307	{
bogdanm	0:9b334a45a8ff	2308	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
bogdanm	0:9b334a45a8ff	2309	{
bogdanm	0:9b334a45a8ff	2310	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2311	{
bogdanm	0:9b334a45a8ff	2312	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2313	{
bogdanm	0:9b334a45a8ff	2314	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2315	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2316	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2317
bogdanm	0:9b334a45a8ff	2318	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2319	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2320
bogdanm	0:9b334a45a8ff	2321	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2322	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2323
bogdanm	0:9b334a45a8ff	2324	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2325	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2326	{
bogdanm	0:9b334a45a8ff	2327	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2328	}
bogdanm	0:9b334a45a8ff	2329
bogdanm	0:9b334a45a8ff	2330	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2331
bogdanm	0:9b334a45a8ff	2332	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2333	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2334
bogdanm	0:9b334a45a8ff	2335	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2336	}
bogdanm	0:9b334a45a8ff	2337	}
bogdanm	0:9b334a45a8ff	2338	}
bogdanm	0:9b334a45a8ff	2339	}
bogdanm	0:9b334a45a8ff	2340	else
bogdanm	0:9b334a45a8ff	2341	{
bogdanm	0:9b334a45a8ff	2342	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
bogdanm	0:9b334a45a8ff	2343	{
bogdanm	0:9b334a45a8ff	2344	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2345	{
bogdanm	0:9b334a45a8ff	2346	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2347	{
bogdanm	0:9b334a45a8ff	2348	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2349	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2350	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2351
bogdanm	0:9b334a45a8ff	2352	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2353	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2354
bogdanm	0:9b334a45a8ff	2355	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2356	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2357
bogdanm	0:9b334a45a8ff	2358	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2359	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2360	{
bogdanm	0:9b334a45a8ff	2361	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2362	}
bogdanm	0:9b334a45a8ff	2363
bogdanm	0:9b334a45a8ff	2364	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2365
bogdanm	0:9b334a45a8ff	2366	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2367	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2368
bogdanm	0:9b334a45a8ff	2369	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2370	}
bogdanm	0:9b334a45a8ff	2371	}
bogdanm	0:9b334a45a8ff	2372	}
bogdanm	0:9b334a45a8ff	2373	}
bogdanm	0:9b334a45a8ff	2374	return HAL_OK;
bogdanm	0:9b334a45a8ff	2375	}
bogdanm	0:9b334a45a8ff	2376
bogdanm	0:9b334a45a8ff	2377	/**
bogdanm	0:9b334a45a8ff	2378	* @}
bogdanm	0:9b334a45a8ff	2379	*/
bogdanm	0:9b334a45a8ff	2380
bogdanm	0:9b334a45a8ff	2381	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	2382	* @{
bogdanm	0:9b334a45a8ff	2383	*/
bogdanm	0:9b334a45a8ff	2384
bogdanm	0:9b334a45a8ff	2385	/**
bogdanm	0:9b334a45a8ff	2386	* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
bogdanm	0:9b334a45a8ff	2387	* according to SPI instance, Device type, and revision ID.
bogdanm	0:9b334a45a8ff	2388	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2389	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2390	* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
bogdanm	0:9b334a45a8ff	2391	*/
bogdanm	0:9b334a45a8ff	2392	__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2393	{
bogdanm	0:9b334a45a8ff	2394	return (SPI_VALID_CRC_ERROR);
bogdanm	0:9b334a45a8ff	2395	}
bogdanm	0:9b334a45a8ff	2396	/**
bogdanm	0:9b334a45a8ff	2397	* @}
bogdanm	0:9b334a45a8ff	2398	*/
bogdanm	0:9b334a45a8ff	2399
bogdanm	0:9b334a45a8ff	2400
bogdanm	0:9b334a45a8ff	2401	#endif /* HAL_SPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2402	/**
bogdanm	0:9b334a45a8ff	2403	* @}
bogdanm	0:9b334a45a8ff	2404	*/
bogdanm	0:9b334a45a8ff	2405
bogdanm	0:9b334a45a8ff	2406	/**
bogdanm	0:9b334a45a8ff	2407	* @}
bogdanm	0:9b334a45a8ff	2408	*/
bogdanm	0:9b334a45a8ff	2409
bogdanm	0:9b334a45a8ff	2410	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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