mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 124:6a4a5b7d7324

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_rcc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	124:6a4a5b7d7324	5	* @version V1.0.4
mbed_official	124:6a4a5b7d7324	6	* @date 29-April-2016
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
mbed_official	124:6a4a5b7d7324	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
mbed_official	124:6a4a5b7d7324	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F1xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F1xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f1xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup RCC
bogdanm	0:9b334a45a8ff	54	* @{
mbed_official	124:6a4a5b7d7324	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/** @addtogroup RCC_Private_Constants
bogdanm	0:9b334a45a8ff	58	* @{
bogdanm	0:9b334a45a8ff	59	*/
bogdanm	0:9b334a45a8ff	60
mbed_official	124:6a4a5b7d7324	61	/** @defgroup RCC_Timeout RCC Timeout
mbed_official	124:6a4a5b7d7324	62	* @{
mbed_official	124:6a4a5b7d7324	63	*/
mbed_official	124:6a4a5b7d7324	64
mbed_official	124:6a4a5b7d7324	65	/* Disable Backup domain write protection state change timeout */
mbed_official	124:6a4a5b7d7324	66	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	124:6a4a5b7d7324	67	/* LSE state change timeout */
mbed_official	124:6a4a5b7d7324	68	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
mbed_official	124:6a4a5b7d7324	69	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm	0:9b334a45a8ff	70	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	124:6a4a5b7d7324	71	#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
mbed_official	124:6a4a5b7d7324	72	#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
mbed_official	124:6a4a5b7d7324	73	#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
mbed_official	124:6a4a5b7d7324	74	#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
mbed_official	124:6a4a5b7d7324	75	/**
mbed_official	124:6a4a5b7d7324	76	* @}
mbed_official	124:6a4a5b7d7324	77	*/
mbed_official	124:6a4a5b7d7324	78
mbed_official	124:6a4a5b7d7324	79	/** @defgroup RCC_Register_Offset Register offsets
bogdanm	0:9b334a45a8ff	80	* @{
bogdanm	0:9b334a45a8ff	81	*/
bogdanm	0:9b334a45a8ff	82	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	0:9b334a45a8ff	83	#define RCC_CR_OFFSET 0x00
bogdanm	0:9b334a45a8ff	84	#define RCC_CFGR_OFFSET 0x04
bogdanm	0:9b334a45a8ff	85	#define RCC_CIR_OFFSET 0x08
bogdanm	0:9b334a45a8ff	86	#define RCC_BDCR_OFFSET 0x20
bogdanm	0:9b334a45a8ff	87	#define RCC_CSR_OFFSET 0x24
mbed_official	124:6a4a5b7d7324	88
mbed_official	124:6a4a5b7d7324	89	/**
mbed_official	124:6a4a5b7d7324	90	* @}
mbed_official	124:6a4a5b7d7324	91	*/
mbed_official	124:6a4a5b7d7324	92
mbed_official	124:6a4a5b7d7324	93	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
mbed_official	124:6a4a5b7d7324	94	* @brief RCC registers bit address in the alias region
mbed_official	124:6a4a5b7d7324	95	* @{
mbed_official	124:6a4a5b7d7324	96	*/
bogdanm	0:9b334a45a8ff	97	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
bogdanm	0:9b334a45a8ff	98	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
bogdanm	0:9b334a45a8ff	99	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
bogdanm	0:9b334a45a8ff	100	#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
bogdanm	0:9b334a45a8ff	101	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	/* --- CR Register ---*/
bogdanm	0:9b334a45a8ff	104	/* Alias word address of HSION bit */
mbed_official	124:6a4a5b7d7324	105	#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
mbed_official	124:6a4a5b7d7324	106	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	107	/* Alias word address of HSEON bit */
mbed_official	124:6a4a5b7d7324	108	#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
mbed_official	124:6a4a5b7d7324	109	#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	110	/* Alias word address of CSSON bit */
mbed_official	124:6a4a5b7d7324	111	#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
mbed_official	124:6a4a5b7d7324	112	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	113	/* Alias word address of PLLON bit */
mbed_official	124:6a4a5b7d7324	114	#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
mbed_official	124:6a4a5b7d7324	115	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	/* --- CSR Register ---*/
bogdanm	0:9b334a45a8ff	118	/* Alias word address of LSION bit */
mbed_official	124:6a4a5b7d7324	119	#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
mbed_official	124:6a4a5b7d7324	120	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	121
mbed_official	124:6a4a5b7d7324	122	/* Alias word address of RMVF bit */
mbed_official	124:6a4a5b7d7324	123	#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
mbed_official	124:6a4a5b7d7324	124	#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
mbed_official	124:6a4a5b7d7324	125
mbed_official	124:6a4a5b7d7324	126	/* --- BDCR Registers ---*/
bogdanm	0:9b334a45a8ff	127	/* Alias word address of LSEON bit */
mbed_official	124:6a4a5b7d7324	128	#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
mbed_official	124:6a4a5b7d7324	129	#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/* Alias word address of LSEON bit */
mbed_official	124:6a4a5b7d7324	132	#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
mbed_official	124:6a4a5b7d7324	133	#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/* Alias word address of RTCEN bit */
mbed_official	124:6a4a5b7d7324	136	#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
mbed_official	124:6a4a5b7d7324	137	#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	/* Alias word address of BDRST bit */
mbed_official	124:6a4a5b7d7324	140	#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
mbed_official	124:6a4a5b7d7324	141	#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
bogdanm	0:9b334a45a8ff	142
mbed_official	124:6a4a5b7d7324	143	/**
mbed_official	124:6a4a5b7d7324	144	* @}
mbed_official	124:6a4a5b7d7324	145	*/
mbed_official	124:6a4a5b7d7324	146
bogdanm	0:9b334a45a8ff	147	/* CR register byte 2 (Bits[23:16]) base address */
bogdanm	0:9b334a45a8ff	148	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150	/* CIR register byte 1 (Bits[15:8]) base address */
mbed_official	124:6a4a5b7d7324	151	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/* CIR register byte 2 (Bits[23:16]) base address */
mbed_official	124:6a4a5b7d7324	154	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/* Defines used for Flags */
mbed_official	124:6a4a5b7d7324	157	#define CR_REG_INDEX ((uint8_t)1)
mbed_official	124:6a4a5b7d7324	158	#define BDCR_REG_INDEX ((uint8_t)2)
mbed_official	124:6a4a5b7d7324	159	#define CSR_REG_INDEX ((uint8_t)3)
bogdanm	0:9b334a45a8ff	160
mbed_official	124:6a4a5b7d7324	161	#define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	/**
bogdanm	0:9b334a45a8ff	164	* @}
bogdanm	0:9b334a45a8ff	165	*/
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	/** @addtogroup RCC_Private_Macros
bogdanm	0:9b334a45a8ff	168	* @{
bogdanm	0:9b334a45a8ff	169	*/
bogdanm	0:9b334a45a8ff	170	/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
bogdanm	0:9b334a45a8ff	171	* @{
bogdanm	0:9b334a45a8ff	172	*/
bogdanm	0:9b334a45a8ff	173	#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	174	#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	175	#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
bogdanm	0:9b334a45a8ff	176	#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
bogdanm	0:9b334a45a8ff	177	/**
bogdanm	0:9b334a45a8ff	178	* @}
bogdanm	0:9b334a45a8ff	179	*/
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	182	((__SOURCE__) == RCC_PLLSOURCE_HSE))
bogdanm	0:9b334a45a8ff	183	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	184	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	185	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	186	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	187	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
mbed_official	124:6a4a5b7d7324	188	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
mbed_official	124:6a4a5b7d7324	189	((__HSE__) == RCC_HSE_BYPASS))
mbed_official	124:6a4a5b7d7324	190	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
mbed_official	124:6a4a5b7d7324	191	((__LSE__) == RCC_LSE_BYPASS))
mbed_official	124:6a4a5b7d7324	192	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
mbed_official	124:6a4a5b7d7324	193	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
bogdanm	0:9b334a45a8ff	194	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
bogdanm	0:9b334a45a8ff	195	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	196	((__PLL__) == RCC_PLL_ON))
bogdanm	0:9b334a45a8ff	197
mbed_official	124:6a4a5b7d7324	198	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
mbed_official	124:6a4a5b7d7324	199	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
mbed_official	124:6a4a5b7d7324	200	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
mbed_official	124:6a4a5b7d7324	201	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
bogdanm	0:9b334a45a8ff	202	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	203	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	204	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	124:6a4a5b7d7324	205	#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
mbed_official	124:6a4a5b7d7324	206	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
mbed_official	124:6a4a5b7d7324	207	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
bogdanm	0:9b334a45a8ff	208	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	209	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	210	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	0:9b334a45a8ff	211	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	0:9b334a45a8ff	212	((__HCLK__) == RCC_SYSCLK_DIV512))
bogdanm	0:9b334a45a8ff	213	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	214	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	215	((__PCLK__) == RCC_HCLK_DIV16))
mbed_official	124:6a4a5b7d7324	216	#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
bogdanm	0:9b334a45a8ff	217	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
mbed_official	124:6a4a5b7d7324	218	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
mbed_official	124:6a4a5b7d7324	219	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
mbed_official	124:6a4a5b7d7324	220	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
mbed_official	124:6a4a5b7d7324	221	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/**
bogdanm	0:9b334a45a8ff	224	* @}
bogdanm	0:9b334a45a8ff	225	*/
bogdanm	0:9b334a45a8ff	226
mbed_official	124:6a4a5b7d7324	227	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm	0:9b334a45a8ff	230	* @{
bogdanm	0:9b334a45a8ff	231	*/
bogdanm	0:9b334a45a8ff	232
bogdanm	0:9b334a45a8ff	233	/**
bogdanm	0:9b334a45a8ff	234	* @brief RCC PLL configuration structure definition
bogdanm	0:9b334a45a8ff	235	*/
bogdanm	0:9b334a45a8ff	236	typedef struct
bogdanm	0:9b334a45a8ff	237	{
mbed_official	124:6a4a5b7d7324	238	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
mbed_official	124:6a4a5b7d7324	239	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	0:9b334a45a8ff	240
mbed_official	124:6a4a5b7d7324	241	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
mbed_official	124:6a4a5b7d7324	242	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	0:9b334a45a8ff	243
mbed_official	124:6a4a5b7d7324	244	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
mbed_official	124:6a4a5b7d7324	245	This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
bogdanm	0:9b334a45a8ff	246	} RCC_PLLInitTypeDef;
bogdanm	0:9b334a45a8ff	247
mbed_official	124:6a4a5b7d7324	248	/**
bogdanm	0:9b334a45a8ff	249	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	0:9b334a45a8ff	250	*/
bogdanm	0:9b334a45a8ff	251	typedef struct
bogdanm	0:9b334a45a8ff	252	{
bogdanm	0:9b334a45a8ff	253	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	0:9b334a45a8ff	254	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	124:6a4a5b7d7324	255
bogdanm	0:9b334a45a8ff	256	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	0:9b334a45a8ff	257	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	0:9b334a45a8ff	260	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	124:6a4a5b7d7324	261
bogdanm	0:9b334a45a8ff	262	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	263	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	124:6a4a5b7d7324	264
bogdanm	0:9b334a45a8ff	265	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	266	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	267	} RCC_ClkInitTypeDef;
bogdanm	0:9b334a45a8ff	268
bogdanm	0:9b334a45a8ff	269	/**
bogdanm	0:9b334a45a8ff	270	* @}
bogdanm	0:9b334a45a8ff	271	*/
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	274	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	0:9b334a45a8ff	275	* @{
bogdanm	0:9b334a45a8ff	276	*/
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm	0:9b334a45a8ff	279	* @{
bogdanm	0:9b334a45a8ff	280	*/
bogdanm	0:9b334a45a8ff	281
mbed_official	124:6a4a5b7d7324	282	#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
mbed_official	124:6a4a5b7d7324	283	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /!< HSE clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/**
bogdanm	0:9b334a45a8ff	286	* @}
mbed_official	124:6a4a5b7d7324	287	*/
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	/** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm	0:9b334a45a8ff	290	* @{
bogdanm	0:9b334a45a8ff	291	*/
bogdanm	0:9b334a45a8ff	292	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	293	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	294	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	295	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	296	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	297	/**
bogdanm	0:9b334a45a8ff	298	* @}
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300
mbed_official	124:6a4a5b7d7324	301	/** @defgroup RCC_HSE_Config HSE Config
bogdanm	0:9b334a45a8ff	302	* @{
bogdanm	0:9b334a45a8ff	303	*/
mbed_official	124:6a4a5b7d7324	304	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
mbed_official	124:6a4a5b7d7324	305	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
mbed_official	124:6a4a5b7d7324	306	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
bogdanm	0:9b334a45a8ff	307	/**
bogdanm	0:9b334a45a8ff	308	* @}
bogdanm	0:9b334a45a8ff	309	*/
bogdanm	0:9b334a45a8ff	310
mbed_official	124:6a4a5b7d7324	311	/** @defgroup RCC_LSE_Config LSE Config
bogdanm	0:9b334a45a8ff	312	* @{
bogdanm	0:9b334a45a8ff	313	*/
mbed_official	124:6a4a5b7d7324	314	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
mbed_official	124:6a4a5b7d7324	315	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
mbed_official	124:6a4a5b7d7324	316	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/**
bogdanm	0:9b334a45a8ff	319	* @}
bogdanm	0:9b334a45a8ff	320	*/
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	/** @defgroup RCC_HSI_Config HSI Config
bogdanm	0:9b334a45a8ff	323	* @{
bogdanm	0:9b334a45a8ff	324	*/
mbed_official	124:6a4a5b7d7324	325	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
mbed_official	124:6a4a5b7d7324	326	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
bogdanm	0:9b334a45a8ff	327
bogdanm	0:9b334a45a8ff	328	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/**
bogdanm	0:9b334a45a8ff	331	* @}
bogdanm	0:9b334a45a8ff	332	*/
bogdanm	0:9b334a45a8ff	333
bogdanm	0:9b334a45a8ff	334	/** @defgroup RCC_LSI_Config LSI Config
bogdanm	0:9b334a45a8ff	335	* @{
bogdanm	0:9b334a45a8ff	336	*/
bogdanm	0:9b334a45a8ff	337	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
bogdanm	0:9b334a45a8ff	338	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/**
bogdanm	0:9b334a45a8ff	341	* @}
bogdanm	0:9b334a45a8ff	342	*/
bogdanm	0:9b334a45a8ff	343
mbed_official	124:6a4a5b7d7324	344	/** @defgroup RCC_PLL_Config PLL Config
bogdanm	0:9b334a45a8ff	345	* @{
bogdanm	0:9b334a45a8ff	346	*/
bogdanm	0:9b334a45a8ff	347	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
bogdanm	0:9b334a45a8ff	348	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
bogdanm	0:9b334a45a8ff	349	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/**
bogdanm	0:9b334a45a8ff	352	* @}
bogdanm	0:9b334a45a8ff	353	*/
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/** @defgroup RCC_System_Clock_Type System Clock Type
bogdanm	0:9b334a45a8ff	356	* @{
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
bogdanm	0:9b334a45a8ff	359	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
bogdanm	0:9b334a45a8ff	360	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
bogdanm	0:9b334a45a8ff	361	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
bogdanm	0:9b334a45a8ff	362
bogdanm	0:9b334a45a8ff	363	/**
bogdanm	0:9b334a45a8ff	364	* @}
bogdanm	0:9b334a45a8ff	365	*/
mbed_official	124:6a4a5b7d7324	366
bogdanm	0:9b334a45a8ff	367	/** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm	0:9b334a45a8ff	368	* @{
bogdanm	0:9b334a45a8ff	369	*/
mbed_official	124:6a4a5b7d7324	370	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
mbed_official	124:6a4a5b7d7324	371	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
mbed_official	124:6a4a5b7d7324	372	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/**
bogdanm	0:9b334a45a8ff	375	* @}
mbed_official	124:6a4a5b7d7324	376	*/
bogdanm	0:9b334a45a8ff	377
bogdanm	0:9b334a45a8ff	378	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
bogdanm	0:9b334a45a8ff	379	* @{
bogdanm	0:9b334a45a8ff	380	*/
mbed_official	124:6a4a5b7d7324	381	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
mbed_official	124:6a4a5b7d7324	382	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
mbed_official	124:6a4a5b7d7324	383	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	/**
bogdanm	0:9b334a45a8ff	386	* @}
bogdanm	0:9b334a45a8ff	387	*/
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
bogdanm	0:9b334a45a8ff	390	* @{
bogdanm	0:9b334a45a8ff	391	*/
mbed_official	124:6a4a5b7d7324	392	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
mbed_official	124:6a4a5b7d7324	393	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
mbed_official	124:6a4a5b7d7324	394	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
mbed_official	124:6a4a5b7d7324	395	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
mbed_official	124:6a4a5b7d7324	396	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
mbed_official	124:6a4a5b7d7324	397	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
mbed_official	124:6a4a5b7d7324	398	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
mbed_official	124:6a4a5b7d7324	399	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
mbed_official	124:6a4a5b7d7324	400	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	/**
bogdanm	0:9b334a45a8ff	403	* @}
mbed_official	124:6a4a5b7d7324	404	*/
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
bogdanm	0:9b334a45a8ff	407	* @{
bogdanm	0:9b334a45a8ff	408	*/
mbed_official	124:6a4a5b7d7324	409	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
mbed_official	124:6a4a5b7d7324	410	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
mbed_official	124:6a4a5b7d7324	411	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
mbed_official	124:6a4a5b7d7324	412	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
mbed_official	124:6a4a5b7d7324	413	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/**
bogdanm	0:9b334a45a8ff	416	* @}
mbed_official	124:6a4a5b7d7324	417	*/
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
bogdanm	0:9b334a45a8ff	420	* @{
bogdanm	0:9b334a45a8ff	421	*/
mbed_official	124:6a4a5b7d7324	422	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /!< No clock /
mbed_official	124:6a4a5b7d7324	423	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
mbed_official	124:6a4a5b7d7324	424	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
mbed_official	124:6a4a5b7d7324	425	#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /!< HSE oscillator clock divided by 128 used as RTC clock /
bogdanm	0:9b334a45a8ff	426	/**
bogdanm	0:9b334a45a8ff	427	* @}
mbed_official	124:6a4a5b7d7324	428	*/
mbed_official	124:6a4a5b7d7324	429
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	/** @defgroup RCC_MCO_Index MCO Index
bogdanm	0:9b334a45a8ff	432	* @{
bogdanm	0:9b334a45a8ff	433	*/
bogdanm	0:9b334a45a8ff	434	#define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	435	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	/**
bogdanm	0:9b334a45a8ff	438	* @}
bogdanm	0:9b334a45a8ff	439	*/
bogdanm	0:9b334a45a8ff	440
mbed_official	124:6a4a5b7d7324	441	/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
bogdanm	0:9b334a45a8ff	442	* @{
bogdanm	0:9b334a45a8ff	443	*/
bogdanm	0:9b334a45a8ff	444	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	/**
bogdanm	0:9b334a45a8ff	447	* @}
mbed_official	124:6a4a5b7d7324	448	*/
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/** @defgroup RCC_Interrupt Interrupts
bogdanm	0:9b334a45a8ff	451	* @{
bogdanm	0:9b334a45a8ff	452	*/
mbed_official	124:6a4a5b7d7324	453	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
mbed_official	124:6a4a5b7d7324	454	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
mbed_official	124:6a4a5b7d7324	455	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
mbed_official	124:6a4a5b7d7324	456	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
mbed_official	124:6a4a5b7d7324	457	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
mbed_official	124:6a4a5b7d7324	458	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	459	/**
bogdanm	0:9b334a45a8ff	460	* @}
mbed_official	124:6a4a5b7d7324	461	*/
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	/** @defgroup RCC_Flag Flags
mbed_official	124:6a4a5b7d7324	464	* Elements values convention: XXXYYYYYb
bogdanm	0:9b334a45a8ff	465	* - YYYYY : Flag position in the register
mbed_official	124:6a4a5b7d7324	466	* - XXX : Register index
mbed_official	124:6a4a5b7d7324	467	* - 001: CR register
mbed_official	124:6a4a5b7d7324	468	* - 010: BDCR register
mbed_official	124:6a4a5b7d7324	469	* - 011: CSR register
bogdanm	0:9b334a45a8ff	470	* @{
bogdanm	0:9b334a45a8ff	471	*/
bogdanm	0:9b334a45a8ff	472	/* Flags in the CR register */
bogdanm	0:9b334a45a8ff	473	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< Internal High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	474	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< External High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	475	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL clock ready flag /
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	/* Flags in the CSR register */
bogdanm	0:9b334a45a8ff	478	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< Internal Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	479	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
bogdanm	0:9b334a45a8ff	480	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PORRSTF))) /!< POR/PDR reset flag /
bogdanm	0:9b334a45a8ff	481	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
bogdanm	0:9b334a45a8ff	482	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
bogdanm	0:9b334a45a8ff	483	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
bogdanm	0:9b334a45a8ff	484	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
bogdanm	0:9b334a45a8ff	485
mbed_official	124:6a4a5b7d7324	486	/* Flags in the BDCR register */
mbed_official	124:6a4a5b7d7324	487	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< External Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	/**
bogdanm	0:9b334a45a8ff	490	* @}
mbed_official	124:6a4a5b7d7324	491	*/
mbed_official	124:6a4a5b7d7324	492
mbed_official	124:6a4a5b7d7324	493	/**
mbed_official	124:6a4a5b7d7324	494	* @}
mbed_official	124:6a4a5b7d7324	495	*/
mbed_official	124:6a4a5b7d7324	496
bogdanm	0:9b334a45a8ff	497	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm	0:9b334a45a8ff	500	* @{
bogdanm	0:9b334a45a8ff	501	*/
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
bogdanm	0:9b334a45a8ff	504	* @brief Enable or disable the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	505	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	506	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	507	* using it.
bogdanm	0:9b334a45a8ff	508	* @{
bogdanm	0:9b334a45a8ff	509	*/
bogdanm	0:9b334a45a8ff	510	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	511	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	512	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
mbed_official	124:6a4a5b7d7324	513	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	514	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	515	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	516	} while(0)
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	519	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	520	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
mbed_official	124:6a4a5b7d7324	521	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	522	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
bogdanm	0:9b334a45a8ff	523	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	524	} while(0)
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	527	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	528	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
mbed_official	124:6a4a5b7d7324	529	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	530	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
bogdanm	0:9b334a45a8ff	531	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	532	} while(0)
bogdanm	0:9b334a45a8ff	533
bogdanm	0:9b334a45a8ff	534	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	535	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	536	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
mbed_official	124:6a4a5b7d7324	537	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	538	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	539	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	540	} while(0)
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
bogdanm	0:9b334a45a8ff	543	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
bogdanm	0:9b334a45a8ff	544	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm	0:9b334a45a8ff	545	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	/**
bogdanm	0:9b334a45a8ff	548	* @}
bogdanm	0:9b334a45a8ff	549	*/
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	552	* @brief Get the enable or disable status of the AHB peripheral clock.
bogdanm	0:9b334a45a8ff	553	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	554	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	555	* using it.
bogdanm	0:9b334a45a8ff	556	* @{
bogdanm	0:9b334a45a8ff	557	*/
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
bogdanm	0:9b334a45a8ff	560	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
bogdanm	0:9b334a45a8ff	561	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
bogdanm	0:9b334a45a8ff	562	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
bogdanm	0:9b334a45a8ff	563	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
bogdanm	0:9b334a45a8ff	564	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
bogdanm	0:9b334a45a8ff	565	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
bogdanm	0:9b334a45a8ff	566	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
bogdanm	0:9b334a45a8ff	567
bogdanm	0:9b334a45a8ff	568	/**
bogdanm	0:9b334a45a8ff	569	* @}
bogdanm	0:9b334a45a8ff	570	*/
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
bogdanm	0:9b334a45a8ff	573	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	574	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	575	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	576	* using it.
bogdanm	0:9b334a45a8ff	577	* @{
bogdanm	0:9b334a45a8ff	578	*/
bogdanm	0:9b334a45a8ff	579	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	580	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	581	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official	124:6a4a5b7d7324	582	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	583	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm	0:9b334a45a8ff	584	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	585	} while(0)
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	588	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	589	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official	124:6a4a5b7d7324	590	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	591	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm	0:9b334a45a8ff	592	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	593	} while(0)
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	596	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	597	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
mbed_official	124:6a4a5b7d7324	598	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	599	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm	0:9b334a45a8ff	600	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	601	} while(0)
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	604	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	605	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official	124:6a4a5b7d7324	606	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	607	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm	0:9b334a45a8ff	608	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	609	} while(0)
bogdanm	0:9b334a45a8ff	610
bogdanm	0:9b334a45a8ff	611	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	612	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	613	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official	124:6a4a5b7d7324	614	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	615	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm	0:9b334a45a8ff	616	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	617	} while(0)
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	#define __HAL_RCC_BKP_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	620	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	621	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
mbed_official	124:6a4a5b7d7324	622	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	623	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
bogdanm	0:9b334a45a8ff	624	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	625	} while(0)
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	628	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	629	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
mbed_official	124:6a4a5b7d7324	630	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	631	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm	0:9b334a45a8ff	632	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	633	} while(0)
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	636	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	0:9b334a45a8ff	637	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	0:9b334a45a8ff	638	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	639	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	640
bogdanm	0:9b334a45a8ff	641	#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
bogdanm	0:9b334a45a8ff	642	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/**
bogdanm	0:9b334a45a8ff	645	* @}
bogdanm	0:9b334a45a8ff	646	*/
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	649	* @brief Get the enable or disable status of the APB1 peripheral clock.
bogdanm	0:9b334a45a8ff	650	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	651	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	652	* using it.
bogdanm	0:9b334a45a8ff	653	* @{
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
bogdanm	0:9b334a45a8ff	657	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
bogdanm	0:9b334a45a8ff	658	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
bogdanm	0:9b334a45a8ff	659	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
bogdanm	0:9b334a45a8ff	660	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
bogdanm	0:9b334a45a8ff	661	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
bogdanm	0:9b334a45a8ff	662	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
bogdanm	0:9b334a45a8ff	663	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
bogdanm	0:9b334a45a8ff	664	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
bogdanm	0:9b334a45a8ff	665	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
bogdanm	0:9b334a45a8ff	666	#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
bogdanm	0:9b334a45a8ff	667	#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
bogdanm	0:9b334a45a8ff	668	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
bogdanm	0:9b334a45a8ff	669	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/**
bogdanm	0:9b334a45a8ff	672	* @}
bogdanm	0:9b334a45a8ff	673	*/
bogdanm	0:9b334a45a8ff	674
bogdanm	0:9b334a45a8ff	675	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
bogdanm	0:9b334a45a8ff	676	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	677	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	678	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	679	* using it.
bogdanm	0:9b334a45a8ff	680	* @{
bogdanm	0:9b334a45a8ff	681	*/
bogdanm	0:9b334a45a8ff	682	#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	683	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	684	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
mbed_official	124:6a4a5b7d7324	685	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	686	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
bogdanm	0:9b334a45a8ff	687	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	688	} while(0)
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	691	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	692	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
mbed_official	124:6a4a5b7d7324	693	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	694	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
bogdanm	0:9b334a45a8ff	695	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	696	} while(0)
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	699	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	700	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
mbed_official	124:6a4a5b7d7324	701	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	702	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
bogdanm	0:9b334a45a8ff	703	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	704	} while(0)
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	707	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	708	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
mbed_official	124:6a4a5b7d7324	709	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	710	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
bogdanm	0:9b334a45a8ff	711	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	712	} while(0)
bogdanm	0:9b334a45a8ff	713
bogdanm	0:9b334a45a8ff	714	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	715	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	716	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
mbed_official	124:6a4a5b7d7324	717	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	718	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
bogdanm	0:9b334a45a8ff	719	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	720	} while(0)
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	723	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	724	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official	124:6a4a5b7d7324	725	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	726	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm	0:9b334a45a8ff	727	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	728	} while(0)
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	731	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	732	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official	124:6a4a5b7d7324	733	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	734	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm	0:9b334a45a8ff	735	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	736	} while(0)
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	739	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	740	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official	124:6a4a5b7d7324	741	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	742	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm	0:9b334a45a8ff	743	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	744	} while(0)
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	747	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	748	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official	124:6a4a5b7d7324	749	/* Delay after an RCC peripheral clock enabling */\
bogdanm	0:9b334a45a8ff	750	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm	0:9b334a45a8ff	751	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	752	} while(0)
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754	#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
bogdanm	0:9b334a45a8ff	755	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
bogdanm	0:9b334a45a8ff	756	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
bogdanm	0:9b334a45a8ff	757	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
bogdanm	0:9b334a45a8ff	758	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
bogdanm	0:9b334a45a8ff	759	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm	0:9b334a45a8ff	762	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	0:9b334a45a8ff	763	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	/**
bogdanm	0:9b334a45a8ff	766	* @}
bogdanm	0:9b334a45a8ff	767	*/
bogdanm	0:9b334a45a8ff	768
bogdanm	0:9b334a45a8ff	769	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	770	* @brief Get the enable or disable status of the APB2 peripheral clock.
bogdanm	0:9b334a45a8ff	771	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	772	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	773	* using it.
bogdanm	0:9b334a45a8ff	774	* @{
bogdanm	0:9b334a45a8ff	775	*/
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
bogdanm	0:9b334a45a8ff	778	#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
bogdanm	0:9b334a45a8ff	779	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
bogdanm	0:9b334a45a8ff	780	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
bogdanm	0:9b334a45a8ff	781	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
bogdanm	0:9b334a45a8ff	782	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
bogdanm	0:9b334a45a8ff	783	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
bogdanm	0:9b334a45a8ff	784	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
bogdanm	0:9b334a45a8ff	785	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
bogdanm	0:9b334a45a8ff	786	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
bogdanm	0:9b334a45a8ff	787	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
bogdanm	0:9b334a45a8ff	788	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
bogdanm	0:9b334a45a8ff	789	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
bogdanm	0:9b334a45a8ff	790	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
bogdanm	0:9b334a45a8ff	791	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
bogdanm	0:9b334a45a8ff	792	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
bogdanm	0:9b334a45a8ff	793	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
bogdanm	0:9b334a45a8ff	794	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796	/**
bogdanm	0:9b334a45a8ff	797	* @}
bogdanm	0:9b334a45a8ff	798	*/
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
bogdanm	0:9b334a45a8ff	801	* @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	802	* @{
bogdanm	0:9b334a45a8ff	803	*/
mbed_official	124:6a4a5b7d7324	804	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
bogdanm	0:9b334a45a8ff	805	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	806	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	807	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
bogdanm	0:9b334a45a8ff	808	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	809	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_BKPRST))
bogdanm	0:9b334a45a8ff	812	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm	0:9b334a45a8ff	815	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	816	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	817	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm	0:9b334a45a8ff	818	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	819	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
bogdanm	0:9b334a45a8ff	822	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/**
bogdanm	0:9b334a45a8ff	825	* @}
bogdanm	0:9b334a45a8ff	826	*/
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
bogdanm	0:9b334a45a8ff	829	* @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	830	* @{
bogdanm	0:9b334a45a8ff	831	*/
mbed_official	124:6a4a5b7d7324	832	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
bogdanm	0:9b334a45a8ff	833	#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_AFIORST))
bogdanm	0:9b334a45a8ff	834	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPARST))
bogdanm	0:9b334a45a8ff	835	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPBRST))
bogdanm	0:9b334a45a8ff	836	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPCRST))
bogdanm	0:9b334a45a8ff	837	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPDRST))
bogdanm	0:9b334a45a8ff	838	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
bogdanm	0:9b334a45a8ff	841	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	842	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm	0:9b334a45a8ff	845	#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
bogdanm	0:9b334a45a8ff	846	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
bogdanm	0:9b334a45a8ff	847	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
bogdanm	0:9b334a45a8ff	848	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
bogdanm	0:9b334a45a8ff	849	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
bogdanm	0:9b334a45a8ff	850	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm	0:9b334a45a8ff	853	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	854	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/**
bogdanm	0:9b334a45a8ff	857	* @}
bogdanm	0:9b334a45a8ff	858	*/
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/** @defgroup RCC_HSI_Configuration HSI Configuration
bogdanm	0:9b334a45a8ff	861	* @{
mbed_official	124:6a4a5b7d7324	862	*/
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	0:9b334a45a8ff	865	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	866	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	0:9b334a45a8ff	867	* you have to select another source of the system clock then stop the HSI.
bogdanm	0:9b334a45a8ff	868	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	0:9b334a45a8ff	869	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	0:9b334a45a8ff	870	* system clock source.
bogdanm	0:9b334a45a8ff	871	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	0:9b334a45a8ff	872	* clock cycles.
bogdanm	0:9b334a45a8ff	873	*/
bogdanm	0:9b334a45a8ff	874	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
bogdanm	0:9b334a45a8ff	875	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
bogdanm	0:9b334a45a8ff	876
mbed_official	124:6a4a5b7d7324	877	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	0:9b334a45a8ff	878	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	879	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	124:6a4a5b7d7324	880	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
bogdanm	0:9b334a45a8ff	881	* (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	882	* This parameter must be a number between 0 and 0x1F.
mbed_official	124:6a4a5b7d7324	883	*/
bogdanm	0:9b334a45a8ff	884	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
bogdanm	0:9b334a45a8ff	885	(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	/**
bogdanm	0:9b334a45a8ff	888	* @}
bogdanm	0:9b334a45a8ff	889	*/
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	/** @defgroup RCC_LSI_Configuration LSI Configuration
bogdanm	0:9b334a45a8ff	892	* @{
mbed_official	124:6a4a5b7d7324	893	*/
bogdanm	0:9b334a45a8ff	894
mbed_official	124:6a4a5b7d7324	895	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
bogdanm	0:9b334a45a8ff	896	* @note After enabling the LSI, the application software should wait on
bogdanm	0:9b334a45a8ff	897	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	0:9b334a45a8ff	898	* be used to clock the IWDG and/or the RTC.
mbed_official	124:6a4a5b7d7324	899	*/
mbed_official	124:6a4a5b7d7324	900	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
mbed_official	124:6a4a5b7d7324	901
mbed_official	124:6a4a5b7d7324	902	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
bogdanm	0:9b334a45a8ff	903	* @note LSI can not be disabled if the IWDG is running.
bogdanm	0:9b334a45a8ff	904	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	0:9b334a45a8ff	905	* clock cycles.
bogdanm	0:9b334a45a8ff	906	*/
bogdanm	0:9b334a45a8ff	907	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	/**
bogdanm	0:9b334a45a8ff	910	* @}
bogdanm	0:9b334a45a8ff	911	*/
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/** @defgroup RCC_HSE_Configuration HSE Configuration
bogdanm	0:9b334a45a8ff	914	* @{
mbed_official	124:6a4a5b7d7324	915	*/
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	/**
bogdanm	0:9b334a45a8ff	918	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	124:6a4a5b7d7324	919	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
mbed_official	124:6a4a5b7d7324	920	* supported by this macro. User should request a transition to HSE Off
mbed_official	124:6a4a5b7d7324	921	* first and then HSE On or HSE Bypass.
bogdanm	0:9b334a45a8ff	922	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	0:9b334a45a8ff	923	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	0:9b334a45a8ff	924	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	0:9b334a45a8ff	925	* @note HSE state can not be changed if it is used directly or through the
bogdanm	0:9b334a45a8ff	926	* PLL as system clock. In this case, you have to select another source
bogdanm	0:9b334a45a8ff	927	* of the system clock then change the HSE state (ex. disable it).
bogdanm	0:9b334a45a8ff	928	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	124:6a4a5b7d7324	929	* @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm	0:9b334a45a8ff	930	* was previously enabled you have to enable it again after calling this
bogdanm	0:9b334a45a8ff	931	* function.
mbed_official	124:6a4a5b7d7324	932	* @param __STATE__ specifies the new state of the HSE.
bogdanm	0:9b334a45a8ff	933	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	934	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	0:9b334a45a8ff	935	* 6 HSE oscillator clock cycles.
mbed_official	124:6a4a5b7d7324	936	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
mbed_official	124:6a4a5b7d7324	937	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
bogdanm	0:9b334a45a8ff	938	*/
mbed_official	124:6a4a5b7d7324	939	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
mbed_official	124:6a4a5b7d7324	940	do{ \
mbed_official	124:6a4a5b7d7324	941	if ((__STATE__) == RCC_HSE_ON) \
bogdanm	0:9b334a45a8ff	942	{ \
bogdanm	0:9b334a45a8ff	943	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	944	} \
mbed_official	124:6a4a5b7d7324	945	else if ((__STATE__) == RCC_HSE_OFF) \
bogdanm	0:9b334a45a8ff	946	{ \
mbed_official	124:6a4a5b7d7324	947	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	124:6a4a5b7d7324	948	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	124:6a4a5b7d7324	949	} \
mbed_official	124:6a4a5b7d7324	950	else if ((__STATE__) == RCC_HSE_BYPASS) \
mbed_official	124:6a4a5b7d7324	951	{ \
mbed_official	124:6a4a5b7d7324	952	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	124:6a4a5b7d7324	953	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	954	} \
bogdanm	0:9b334a45a8ff	955	else \
bogdanm	0:9b334a45a8ff	956	{ \
mbed_official	124:6a4a5b7d7324	957	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	958	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	959	} \
mbed_official	124:6a4a5b7d7324	960	}while(0)
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	/**
bogdanm	0:9b334a45a8ff	963	* @}
bogdanm	0:9b334a45a8ff	964	*/
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	/** @defgroup RCC_LSE_Configuration LSE Configuration
bogdanm	0:9b334a45a8ff	967	* @{
mbed_official	124:6a4a5b7d7324	968	*/
bogdanm	0:9b334a45a8ff	969
mbed_official	124:6a4a5b7d7324	970	/**
mbed_official	124:6a4a5b7d7324	971	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	124:6a4a5b7d7324	972	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
mbed_official	124:6a4a5b7d7324	973	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	124:6a4a5b7d7324	974	* this domain after reset, you have to enable write access using
mbed_official	124:6a4a5b7d7324	975	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	124:6a4a5b7d7324	976	* (to be done once after reset).
mbed_official	124:6a4a5b7d7324	977	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	124:6a4a5b7d7324	978	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	124:6a4a5b7d7324	979	* is stable and can be used to clock the RTC.
mbed_official	124:6a4a5b7d7324	980	* @param __STATE__ specifies the new state of the LSE.
mbed_official	124:6a4a5b7d7324	981	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	982	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	124:6a4a5b7d7324	983	* 6 LSE oscillator clock cycles.
mbed_official	124:6a4a5b7d7324	984	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
mbed_official	124:6a4a5b7d7324	985	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
bogdanm	0:9b334a45a8ff	986	*/
mbed_official	124:6a4a5b7d7324	987	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
mbed_official	124:6a4a5b7d7324	988	do{ \
mbed_official	124:6a4a5b7d7324	989	if ((__STATE__) == RCC_LSE_ON) \
mbed_official	124:6a4a5b7d7324	990	{ \
mbed_official	124:6a4a5b7d7324	991	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	124:6a4a5b7d7324	992	} \
mbed_official	124:6a4a5b7d7324	993	else if ((__STATE__) == RCC_LSE_OFF) \
mbed_official	124:6a4a5b7d7324	994	{ \
mbed_official	124:6a4a5b7d7324	995	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	124:6a4a5b7d7324	996	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	124:6a4a5b7d7324	997	} \
mbed_official	124:6a4a5b7d7324	998	else if ((__STATE__) == RCC_LSE_BYPASS) \
mbed_official	124:6a4a5b7d7324	999	{ \
mbed_official	124:6a4a5b7d7324	1000	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	124:6a4a5b7d7324	1001	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	124:6a4a5b7d7324	1002	} \
mbed_official	124:6a4a5b7d7324	1003	else \
mbed_official	124:6a4a5b7d7324	1004	{ \
mbed_official	124:6a4a5b7d7324	1005	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	124:6a4a5b7d7324	1006	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	124:6a4a5b7d7324	1007	} \
mbed_official	124:6a4a5b7d7324	1008	}while(0)
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	/**
bogdanm	0:9b334a45a8ff	1011	* @}
bogdanm	0:9b334a45a8ff	1012	*/
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/** @defgroup RCC_PLL_Configuration PLL Configuration
bogdanm	0:9b334a45a8ff	1015	* @{
mbed_official	124:6a4a5b7d7324	1016	*/
bogdanm	0:9b334a45a8ff	1017
mbed_official	124:6a4a5b7d7324	1018	/** @brief Macro to enable the main PLL.
bogdanm	0:9b334a45a8ff	1019	* @note After enabling the main PLL, the application software should wait on
bogdanm	0:9b334a45a8ff	1020	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	0:9b334a45a8ff	1021	* be used as system clock source.
bogdanm	0:9b334a45a8ff	1022	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1023	*/
bogdanm	0:9b334a45a8ff	1024	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
bogdanm	0:9b334a45a8ff	1025
mbed_official	124:6a4a5b7d7324	1026	/** @brief Macro to disable the main PLL.
bogdanm	0:9b334a45a8ff	1027	* @note The main PLL can not be disabled if it is used as system clock source
bogdanm	0:9b334a45a8ff	1028	*/
bogdanm	0:9b334a45a8ff	1029	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
bogdanm	0:9b334a45a8ff	1030
mbed_official	124:6a4a5b7d7324	1031	/** @brief Macro to configure the main PLL clock source and multiplication factors.
bogdanm	0:9b334a45a8ff	1032	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	1033	*
mbed_official	124:6a4a5b7d7324	1034	* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	1035	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1036	* @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
mbed_official	124:6a4a5b7d7324	1037	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
mbed_official	124:6a4a5b7d7324	1038	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
bogdanm	0:9b334a45a8ff	1039	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1040	* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
mbed_official	124:6a4a5b7d7324	1041	* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
mbed_official	124:6a4a5b7d7324	1042	@if STM32F105xC
mbed_official	124:6a4a5b7d7324	1043	* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
mbed_official	124:6a4a5b7d7324	1044	@elseif STM32F107xC
mbed_official	124:6a4a5b7d7324	1045	* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
mbed_official	124:6a4a5b7d7324	1046	@else
mbed_official	124:6a4a5b7d7324	1047	* @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
mbed_official	124:6a4a5b7d7324	1048	* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
mbed_official	124:6a4a5b7d7324	1049	* @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
mbed_official	124:6a4a5b7d7324	1050	* @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
mbed_official	124:6a4a5b7d7324	1051	* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
mbed_official	124:6a4a5b7d7324	1052	* @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
mbed_official	124:6a4a5b7d7324	1053	* @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
mbed_official	124:6a4a5b7d7324	1054	* @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
mbed_official	124:6a4a5b7d7324	1055	* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
mbed_official	124:6a4a5b7d7324	1056	@endif
mbed_official	124:6a4a5b7d7324	1057	* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
mbed_official	124:6a4a5b7d7324	1058	* @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
bogdanm	0:9b334a45a8ff	1059	*
bogdanm	0:9b334a45a8ff	1060	*/
bogdanm	0:9b334a45a8ff	1061	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
bogdanm	0:9b334a45a8ff	1062	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) \| (__PLLMUL__) ))
mbed_official	124:6a4a5b7d7324	1063
mbed_official	124:6a4a5b7d7324	1064	/** @brief Get oscillator clock selected as PLL input clock
mbed_official	124:6a4a5b7d7324	1065	* @retval The clock source used for PLL entry. The returned value can be one
mbed_official	124:6a4a5b7d7324	1066	* of the following:
mbed_official	124:6a4a5b7d7324	1067	* @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
mbed_official	124:6a4a5b7d7324	1068	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
mbed_official	124:6a4a5b7d7324	1069	*/
mbed_official	124:6a4a5b7d7324	1070	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
mbed_official	124:6a4a5b7d7324	1071
bogdanm	0:9b334a45a8ff	1072	/**
bogdanm	0:9b334a45a8ff	1073	* @}
bogdanm	0:9b334a45a8ff	1074	*/
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/** @defgroup RCC_Get_Clock_source Get Clock source
bogdanm	0:9b334a45a8ff	1077	* @{
mbed_official	124:6a4a5b7d7324	1078	*/
mbed_official	124:6a4a5b7d7324	1079
mbed_official	124:6a4a5b7d7324	1080	/**
mbed_official	124:6a4a5b7d7324	1081	* @brief Macro to configure the system clock source.
mbed_official	124:6a4a5b7d7324	1082	* @param __SYSCLKSOURCE__ specifies the system clock source.
mbed_official	124:6a4a5b7d7324	1083	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1084	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
mbed_official	124:6a4a5b7d7324	1085	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
mbed_official	124:6a4a5b7d7324	1086	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
mbed_official	124:6a4a5b7d7324	1087	*/
mbed_official	124:6a4a5b7d7324	1088	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
mbed_official	124:6a4a5b7d7324	1089	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
mbed_official	124:6a4a5b7d7324	1090
bogdanm	0:9b334a45a8ff	1091	/** @brief Macro to get the clock source used as system clock.
bogdanm	0:9b334a45a8ff	1092	* @retval The clock source used as system clock. The returned value can be one
bogdanm	0:9b334a45a8ff	1093	* of the following:
mbed_official	124:6a4a5b7d7324	1094	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
mbed_official	124:6a4a5b7d7324	1095	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
mbed_official	124:6a4a5b7d7324	1096	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
mbed_official	124:6a4a5b7d7324	1097	*/
bogdanm	0:9b334a45a8ff	1098	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	/**
bogdanm	0:9b334a45a8ff	1101	* @}
mbed_official	124:6a4a5b7d7324	1102	*/
mbed_official	124:6a4a5b7d7324	1103
mbed_official	124:6a4a5b7d7324	1104	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
bogdanm	0:9b334a45a8ff	1105	* @{
bogdanm	0:9b334a45a8ff	1106	*/
bogdanm	0:9b334a45a8ff	1107
mbed_official	124:6a4a5b7d7324	1108	#if defined(RCC_CFGR_MCO_3)
mbed_official	124:6a4a5b7d7324	1109	/** @brief Macro to configure the MCO clock.
mbed_official	124:6a4a5b7d7324	1110	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
mbed_official	124:6a4a5b7d7324	1111	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1112	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
mbed_official	124:6a4a5b7d7324	1113	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
mbed_official	124:6a4a5b7d7324	1114	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
mbed_official	124:6a4a5b7d7324	1115	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
mbed_official	124:6a4a5b7d7324	1116	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
mbed_official	124:6a4a5b7d7324	1117	* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
mbed_official	124:6a4a5b7d7324	1118	* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
mbed_official	124:6a4a5b7d7324	1119	* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
mbed_official	124:6a4a5b7d7324	1120	* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
mbed_official	124:6a4a5b7d7324	1121	* @param __MCODIV__ specifies the MCO clock prescaler.
mbed_official	124:6a4a5b7d7324	1122	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1123	* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
mbed_official	124:6a4a5b7d7324	1124	*/
mbed_official	124:6a4a5b7d7324	1125	#else
mbed_official	124:6a4a5b7d7324	1126	/** @brief Macro to configure the MCO clock.
mbed_official	124:6a4a5b7d7324	1127	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
mbed_official	124:6a4a5b7d7324	1128	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1129	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
mbed_official	124:6a4a5b7d7324	1130	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
mbed_official	124:6a4a5b7d7324	1131	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
mbed_official	124:6a4a5b7d7324	1132	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
mbed_official	124:6a4a5b7d7324	1133	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
mbed_official	124:6a4a5b7d7324	1134	* @param __MCODIV__ specifies the MCO clock prescaler.
mbed_official	124:6a4a5b7d7324	1135	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1136	* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
mbed_official	124:6a4a5b7d7324	1137	*/
mbed_official	124:6a4a5b7d7324	1138	#endif
mbed_official	124:6a4a5b7d7324	1139
mbed_official	124:6a4a5b7d7324	1140	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
mbed_official	124:6a4a5b7d7324	1141	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
mbed_official	124:6a4a5b7d7324	1142
mbed_official	124:6a4a5b7d7324	1143
mbed_official	124:6a4a5b7d7324	1144	/**
mbed_official	124:6a4a5b7d7324	1145	* @}
mbed_official	124:6a4a5b7d7324	1146	*/
mbed_official	124:6a4a5b7d7324	1147
mbed_official	124:6a4a5b7d7324	1148	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
mbed_official	124:6a4a5b7d7324	1149	* @{
mbed_official	124:6a4a5b7d7324	1150	*/
mbed_official	124:6a4a5b7d7324	1151
mbed_official	124:6a4a5b7d7324	1152	/** @brief Macro to configure the RTC clock (RTCCLK).
bogdanm	0:9b334a45a8ff	1153	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	0:9b334a45a8ff	1154	* access is denied to this domain after reset, you have to enable write
bogdanm	0:9b334a45a8ff	1155	* access using the Power Backup Access macro before to configure
bogdanm	0:9b334a45a8ff	1156	* the RTC clock source (to be done once after reset).
bogdanm	0:9b334a45a8ff	1157	* @note Once the RTC clock is configured it can't be changed unless the
mbed_official	124:6a4a5b7d7324	1158	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
bogdanm	0:9b334a45a8ff	1159	* a Power On Reset (POR).
bogdanm	0:9b334a45a8ff	1160	*
mbed_official	124:6a4a5b7d7324	1161	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
bogdanm	0:9b334a45a8ff	1162	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1163	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
mbed_official	124:6a4a5b7d7324	1164	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
mbed_official	124:6a4a5b7d7324	1165	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
mbed_official	124:6a4a5b7d7324	1166	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
bogdanm	0:9b334a45a8ff	1167	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	0:9b334a45a8ff	1168	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	0:9b334a45a8ff	1169	* However, when the HSE clock is used as RTC clock source, the RTC
bogdanm	0:9b334a45a8ff	1170	* cannot be used in STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1171	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm	0:9b334a45a8ff	1172	* RTC clock source).
bogdanm	0:9b334a45a8ff	1173	*/
bogdanm	0:9b334a45a8ff	1174	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1175
mbed_official	124:6a4a5b7d7324	1176	/** @brief Macro to get the RTC clock source.
mbed_official	124:6a4a5b7d7324	1177	* @retval The clock source can be one of the following values:
mbed_official	124:6a4a5b7d7324	1178	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
mbed_official	124:6a4a5b7d7324	1179	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
mbed_official	124:6a4a5b7d7324	1180	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
mbed_official	124:6a4a5b7d7324	1181	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
bogdanm	0:9b334a45a8ff	1182	*/
mbed_official	124:6a4a5b7d7324	1183	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
bogdanm	0:9b334a45a8ff	1184
mbed_official	124:6a4a5b7d7324	1185	/** @brief Macro to enable the the RTC clock.
mbed_official	124:6a4a5b7d7324	1186	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	0:9b334a45a8ff	1187	*/
bogdanm	0:9b334a45a8ff	1188	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
bogdanm	0:9b334a45a8ff	1189
mbed_official	124:6a4a5b7d7324	1190	/** @brief Macro to disable the the RTC clock.
mbed_official	124:6a4a5b7d7324	1191	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	0:9b334a45a8ff	1192	*/
bogdanm	0:9b334a45a8ff	1193	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
bogdanm	0:9b334a45a8ff	1194
mbed_official	124:6a4a5b7d7324	1195	/** @brief Macro to force the Backup domain reset.
mbed_official	124:6a4a5b7d7324	1196	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	124:6a4a5b7d7324	1197	* and the RTC clock source selection in RCC_BDCR register.
bogdanm	0:9b334a45a8ff	1198	*/
bogdanm	0:9b334a45a8ff	1199	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	/** @brief Macros to release the Backup domain reset.
bogdanm	0:9b334a45a8ff	1202	*/
bogdanm	0:9b334a45a8ff	1203	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	/**
bogdanm	0:9b334a45a8ff	1206	* @}
bogdanm	0:9b334a45a8ff	1207	*/
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm	0:9b334a45a8ff	1210	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	0:9b334a45a8ff	1211	* @{
bogdanm	0:9b334a45a8ff	1212	*/
bogdanm	0:9b334a45a8ff	1213
mbed_official	124:6a4a5b7d7324	1214	/** @brief Enable RCC interrupt.
mbed_official	124:6a4a5b7d7324	1215	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	1216	* This parameter can be any combination of the following values:
mbed_official	124:6a4a5b7d7324	1217	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
mbed_official	124:6a4a5b7d7324	1218	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
mbed_official	124:6a4a5b7d7324	1219	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
mbed_official	124:6a4a5b7d7324	1220	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
mbed_official	124:6a4a5b7d7324	1221	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
mbed_official	124:6a4a5b7d7324	1222	@if STM32F105xx
mbed_official	124:6a4a5b7d7324	1223	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
mbed_official	124:6a4a5b7d7324	1224	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
mbed_official	124:6a4a5b7d7324	1225	@elsif STM32F107xx
mbed_official	124:6a4a5b7d7324	1226	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
mbed_official	124:6a4a5b7d7324	1227	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
mbed_official	124:6a4a5b7d7324	1228	@endif
bogdanm	0:9b334a45a8ff	1229	*/
bogdanm	0:9b334a45a8ff	1230	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1231
mbed_official	124:6a4a5b7d7324	1232	/** @brief Disable RCC interrupt.
mbed_official	124:6a4a5b7d7324	1233	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	1234	* This parameter can be any combination of the following values:
mbed_official	124:6a4a5b7d7324	1235	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
mbed_official	124:6a4a5b7d7324	1236	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
mbed_official	124:6a4a5b7d7324	1237	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
mbed_official	124:6a4a5b7d7324	1238	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
mbed_official	124:6a4a5b7d7324	1239	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
mbed_official	124:6a4a5b7d7324	1240	@if STM32F105xx
mbed_official	124:6a4a5b7d7324	1241	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
mbed_official	124:6a4a5b7d7324	1242	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
mbed_official	124:6a4a5b7d7324	1243	@elsif STM32F107xx
mbed_official	124:6a4a5b7d7324	1244	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
mbed_official	124:6a4a5b7d7324	1245	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
mbed_official	124:6a4a5b7d7324	1246	@endif
bogdanm	0:9b334a45a8ff	1247	*/
mbed_official	124:6a4a5b7d7324	1248	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
bogdanm	0:9b334a45a8ff	1249
mbed_official	124:6a4a5b7d7324	1250	/** @brief Clear the RCC's interrupt pending bits.
mbed_official	124:6a4a5b7d7324	1251	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1252	* This parameter can be any combination of the following values:
mbed_official	124:6a4a5b7d7324	1253	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
mbed_official	124:6a4a5b7d7324	1254	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
mbed_official	124:6a4a5b7d7324	1255	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
mbed_official	124:6a4a5b7d7324	1256	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
mbed_official	124:6a4a5b7d7324	1257	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
mbed_official	124:6a4a5b7d7324	1258	@if STM32F105xx
mbed_official	124:6a4a5b7d7324	1259	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
mbed_official	124:6a4a5b7d7324	1260	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
mbed_official	124:6a4a5b7d7324	1261	@elsif STM32F107xx
mbed_official	124:6a4a5b7d7324	1262	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
mbed_official	124:6a4a5b7d7324	1263	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
mbed_official	124:6a4a5b7d7324	1264	@endif
mbed_official	124:6a4a5b7d7324	1265	* @arg @ref RCC_IT_CSS Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1266	*/
bogdanm	0:9b334a45a8ff	1267	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	124:6a4a5b7d7324	1270	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
bogdanm	0:9b334a45a8ff	1271	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1272	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
mbed_official	124:6a4a5b7d7324	1273	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
mbed_official	124:6a4a5b7d7324	1274	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
mbed_official	124:6a4a5b7d7324	1275	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
mbed_official	124:6a4a5b7d7324	1276	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
mbed_official	124:6a4a5b7d7324	1277	@if STM32F105xx
mbed_official	124:6a4a5b7d7324	1278	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
mbed_official	124:6a4a5b7d7324	1279	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
mbed_official	124:6a4a5b7d7324	1280	@elsif STM32F107xx
mbed_official	124:6a4a5b7d7324	1281	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
mbed_official	124:6a4a5b7d7324	1282	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
mbed_official	124:6a4a5b7d7324	1283	@endif
mbed_official	124:6a4a5b7d7324	1284	* @arg @ref RCC_IT_CSS Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1285	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1286	*/
bogdanm	0:9b334a45a8ff	1287	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1288
mbed_official	124:6a4a5b7d7324	1289	/** @brief Set RMVF bit to clear the reset flags.
mbed_official	124:6a4a5b7d7324	1290	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
mbed_official	124:6a4a5b7d7324	1291	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm	0:9b334a45a8ff	1292	*/
mbed_official	124:6a4a5b7d7324	1293	#define __HAL_RCC_CLEAR_RESET_FLAGS() ((__IO uint32_t )RCC_CSR_RMVF_BB = ENABLE)
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	/** @brief Check RCC flag is set or not.
mbed_official	124:6a4a5b7d7324	1296	* @param __FLAG__ specifies the flag to check.
bogdanm	0:9b334a45a8ff	1297	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	1298	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
mbed_official	124:6a4a5b7d7324	1299	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
mbed_official	124:6a4a5b7d7324	1300	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
mbed_official	124:6a4a5b7d7324	1301	@if STM32F105xx
mbed_official	124:6a4a5b7d7324	1302	* @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
mbed_official	124:6a4a5b7d7324	1303	* @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
mbed_official	124:6a4a5b7d7324	1304	@elsif STM32F107xx
mbed_official	124:6a4a5b7d7324	1305	* @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
mbed_official	124:6a4a5b7d7324	1306	* @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
mbed_official	124:6a4a5b7d7324	1307	@endif
mbed_official	124:6a4a5b7d7324	1308	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
mbed_official	124:6a4a5b7d7324	1309	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
mbed_official	124:6a4a5b7d7324	1310	* @arg @ref RCC_FLAG_PINRST Pin reset.
mbed_official	124:6a4a5b7d7324	1311	* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
mbed_official	124:6a4a5b7d7324	1312	* @arg @ref RCC_FLAG_SFTRST Software reset.
mbed_official	124:6a4a5b7d7324	1313	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
mbed_official	124:6a4a5b7d7324	1314	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
mbed_official	124:6a4a5b7d7324	1315	* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
bogdanm	0:9b334a45a8ff	1316	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1317	*/
mbed_official	124:6a4a5b7d7324	1318	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
mbed_official	124:6a4a5b7d7324	1319	((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
mbed_official	124:6a4a5b7d7324	1320	RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
mbed_official	124:6a4a5b7d7324	1321
bogdanm	0:9b334a45a8ff	1322	/**
bogdanm	0:9b334a45a8ff	1323	* @}
bogdanm	0:9b334a45a8ff	1324	*/
mbed_official	124:6a4a5b7d7324	1325
bogdanm	0:9b334a45a8ff	1326	/**
bogdanm	0:9b334a45a8ff	1327	* @}
mbed_official	124:6a4a5b7d7324	1328	*/
bogdanm	0:9b334a45a8ff	1329
bogdanm	0:9b334a45a8ff	1330	/* Include RCC HAL Extension module */
bogdanm	0:9b334a45a8ff	1331	#include "stm32f1xx_hal_rcc_ex.h"
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1334	/** @addtogroup RCC_Exported_Functions
bogdanm	0:9b334a45a8ff	1335	* @{
bogdanm	0:9b334a45a8ff	1336	*/
bogdanm	0:9b334a45a8ff	1337
bogdanm	0:9b334a45a8ff	1338	/** @addtogroup RCC_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	1339	* @{
bogdanm	0:9b334a45a8ff	1340	*/
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/* Initialization and de-initialization functions ******************************/
bogdanm	0:9b334a45a8ff	1343	void HAL_RCC_DeInit(void);
bogdanm	0:9b334a45a8ff	1344	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1345	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/**
bogdanm	0:9b334a45a8ff	1348	* @}
bogdanm	0:9b334a45a8ff	1349	*/
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	/** @addtogroup RCC_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	1352	* @{
bogdanm	0:9b334a45a8ff	1353	*/
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	/* Peripheral Control functions ************************************************/
bogdanm	0:9b334a45a8ff	1356	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	0:9b334a45a8ff	1357	void HAL_RCC_EnableCSS(void);
bogdanm	0:9b334a45a8ff	1358	void HAL_RCC_DisableCSS(void);
bogdanm	0:9b334a45a8ff	1359	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	0:9b334a45a8ff	1360	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	0:9b334a45a8ff	1361	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	0:9b334a45a8ff	1362	uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm	0:9b334a45a8ff	1363	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1364	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/* CSS NMI IRQ handler */
bogdanm	0:9b334a45a8ff	1367	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	0:9b334a45a8ff	1368
mbed_official	124:6a4a5b7d7324	1369	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	0:9b334a45a8ff	1370	void HAL_RCC_CSSCallback(void);
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	/**
bogdanm	0:9b334a45a8ff	1373	* @}
bogdanm	0:9b334a45a8ff	1374	*/
bogdanm	0:9b334a45a8ff	1375
bogdanm	0:9b334a45a8ff	1376	/**
bogdanm	0:9b334a45a8ff	1377	* @}
mbed_official	124:6a4a5b7d7324	1378	*/
bogdanm	0:9b334a45a8ff	1379
bogdanm	0:9b334a45a8ff	1380	/**
bogdanm	0:9b334a45a8ff	1381	* @}
mbed_official	124:6a4a5b7d7324	1382	*/
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	/**
bogdanm	0:9b334a45a8ff	1385	* @}
bogdanm	0:9b334a45a8ff	1386	*/
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1389	}
bogdanm	0:9b334a45a8ff	1390	#endif
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	#endif /* __STM32F1xx_HAL_RCC_H */
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	124:6a4a5b7d7324	1395

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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