en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
124:6a4a5b7d7324 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_pwr.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 124:6a4a5b7d7324 5 * @version V1.0.4
mbed_official 124:6a4a5b7d7324 6 * @date 29-April-2016
bogdanm 0:9b334a45a8ff 7 * @brief PWR HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Power Controller (PWR) peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 ******************************************************************************
bogdanm 0:9b334a45a8ff 15 * @attention
bogdanm 0:9b334a45a8ff 16 *
mbed_official 124:6a4a5b7d7324 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 20 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 22 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 25 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 27 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 28 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 29 *
bogdanm 0:9b334a45a8ff 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 40 *
bogdanm 0:9b334a45a8ff 41 ******************************************************************************
bogdanm 0:9b334a45a8ff 42 */
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 45 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 48 * @{
bogdanm 0:9b334a45a8ff 49 */
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /** @defgroup PWR PWR
bogdanm 0:9b334a45a8ff 52 * @brief PWR HAL module driver
bogdanm 0:9b334a45a8ff 53 * @{
bogdanm 0:9b334a45a8ff 54 */
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 #ifdef HAL_PWR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /** @defgroup PWR_Private_Constants PWR Private Constants
bogdanm 0:9b334a45a8ff 62 * @{
bogdanm 0:9b334a45a8ff 63 */
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
bogdanm 0:9b334a45a8ff 66 * @{
bogdanm 0:9b334a45a8ff 67 */
bogdanm 0:9b334a45a8ff 68 #define PVD_MODE_IT ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 69 #define PVD_MODE_EVT ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 70 #define PVD_RISING_EDGE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 71 #define PVD_FALLING_EDGE ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 72 /**
bogdanm 0:9b334a45a8ff 73 * @}
bogdanm 0:9b334a45a8ff 74 */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /** @defgroup PWR_register_alias_address PWR Register alias address
bogdanm 0:9b334a45a8ff 78 * @{
bogdanm 0:9b334a45a8ff 79 */
bogdanm 0:9b334a45a8ff 80 /* ------------- PWR registers bit address in the alias region ---------------*/
bogdanm 0:9b334a45a8ff 81 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
bogdanm 0:9b334a45a8ff 82 #define PWR_CR_OFFSET 0x00
bogdanm 0:9b334a45a8ff 83 #define PWR_CSR_OFFSET 0x04
bogdanm 0:9b334a45a8ff 84 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
bogdanm 0:9b334a45a8ff 85 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
bogdanm 0:9b334a45a8ff 86 /**
bogdanm 0:9b334a45a8ff 87 * @}
bogdanm 0:9b334a45a8ff 88 */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
bogdanm 0:9b334a45a8ff 91 * @{
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93 /* --- CR Register ---*/
bogdanm 0:9b334a45a8ff 94 /* Alias word address of LPSDSR bit */
bogdanm 0:9b334a45a8ff 95 #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPDS)
bogdanm 0:9b334a45a8ff 96 #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /* Alias word address of DBP bit */
bogdanm 0:9b334a45a8ff 99 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
bogdanm 0:9b334a45a8ff 100 #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /* Alias word address of PVDE bit */
bogdanm 0:9b334a45a8ff 103 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
bogdanm 0:9b334a45a8ff 104 #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /**
bogdanm 0:9b334a45a8ff 107 * @}
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
bogdanm 0:9b334a45a8ff 111 * @{
bogdanm 0:9b334a45a8ff 112 */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /* --- CSR Register ---*/
bogdanm 0:9b334a45a8ff 115 /* Alias word address of EWUP1 bit */
bogdanm 0:9b334a45a8ff 116 #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
bogdanm 0:9b334a45a8ff 117 /**
bogdanm 0:9b334a45a8ff 118 * @}
bogdanm 0:9b334a45a8ff 119 */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /**
bogdanm 0:9b334a45a8ff 122 * @}
bogdanm 0:9b334a45a8ff 123 */
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 126 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 127 /** @defgroup PWR_Private_Functions PWR Private Functions
bogdanm 0:9b334a45a8ff 128 * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
bogdanm 0:9b334a45a8ff 129 * @{
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131 static void PWR_OverloadWfe(void);
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 134 __NOINLINE
bogdanm 0:9b334a45a8ff 135 static void PWR_OverloadWfe(void)
bogdanm 0:9b334a45a8ff 136 {
bogdanm 0:9b334a45a8ff 137 __asm volatile( "wfe" );
bogdanm 0:9b334a45a8ff 138 __asm volatile( "nop" );
bogdanm 0:9b334a45a8ff 139 }
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /**
bogdanm 0:9b334a45a8ff 142 * @}
bogdanm 0:9b334a45a8ff 143 */
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /** @defgroup PWR_Exported_Functions PWR Exported Functions
bogdanm 0:9b334a45a8ff 147 * @{
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 151 * @brief Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 152 *
bogdanm 0:9b334a45a8ff 153 @verbatim
bogdanm 0:9b334a45a8ff 154 ===============================================================================
bogdanm 0:9b334a45a8ff 155 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 156 ===============================================================================
bogdanm 0:9b334a45a8ff 157 [..]
bogdanm 0:9b334a45a8ff 158 After reset, the backup domain (RTC registers, RTC backup data
bogdanm 0:9b334a45a8ff 159 registers) is protected against possible unwanted
bogdanm 0:9b334a45a8ff 160 write accesses.
bogdanm 0:9b334a45a8ff 161 To enable access to the RTC Domain and RTC registers, proceed as follows:
bogdanm 0:9b334a45a8ff 162 (+) Enable the Power Controller (PWR) APB1 interface clock using the
bogdanm 0:9b334a45a8ff 163 __HAL_RCC_PWR_CLK_ENABLE() macro.
bogdanm 0:9b334a45a8ff 164 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 @endverbatim
bogdanm 0:9b334a45a8ff 167 * @{
bogdanm 0:9b334a45a8ff 168 */
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /**
bogdanm 0:9b334a45a8ff 171 * @brief Deinitializes the PWR peripheral registers to their default reset values.
bogdanm 0:9b334a45a8ff 172 * @retval None
bogdanm 0:9b334a45a8ff 173 */
bogdanm 0:9b334a45a8ff 174 void HAL_PWR_DeInit(void)
bogdanm 0:9b334a45a8ff 175 {
bogdanm 0:9b334a45a8ff 176 __HAL_RCC_PWR_FORCE_RESET();
bogdanm 0:9b334a45a8ff 177 __HAL_RCC_PWR_RELEASE_RESET();
bogdanm 0:9b334a45a8ff 178 }
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /**
bogdanm 0:9b334a45a8ff 181 * @brief Enables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 182 * backup data registers ).
bogdanm 0:9b334a45a8ff 183 * @note If the HSE divided by 128 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 184 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 185 * @retval None
bogdanm 0:9b334a45a8ff 186 */
bogdanm 0:9b334a45a8ff 187 void HAL_PWR_EnableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 188 {
bogdanm 0:9b334a45a8ff 189 /* Enable access to RTC and backup registers */
bogdanm 0:9b334a45a8ff 190 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
bogdanm 0:9b334a45a8ff 191 }
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /**
bogdanm 0:9b334a45a8ff 194 * @brief Disables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 195 * backup data registers).
bogdanm 0:9b334a45a8ff 196 * @note If the HSE divided by 128 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 197 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 198 * @retval None
bogdanm 0:9b334a45a8ff 199 */
bogdanm 0:9b334a45a8ff 200 void HAL_PWR_DisableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 /* Disable access to RTC and backup registers */
bogdanm 0:9b334a45a8ff 203 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
bogdanm 0:9b334a45a8ff 204 }
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /**
bogdanm 0:9b334a45a8ff 207 * @}
bogdanm 0:9b334a45a8ff 208 */
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 211 * @brief Low Power modes configuration functions
bogdanm 0:9b334a45a8ff 212 *
bogdanm 0:9b334a45a8ff 213 @verbatim
bogdanm 0:9b334a45a8ff 214 ===============================================================================
bogdanm 0:9b334a45a8ff 215 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 216 ===============================================================================
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 *** PVD configuration ***
bogdanm 0:9b334a45a8ff 219 =========================
bogdanm 0:9b334a45a8ff 220 [..]
bogdanm 0:9b334a45a8ff 221 (+) The PVD is used to monitor the VDD power supply by comparing it to a
bogdanm 0:9b334a45a8ff 222 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
bogdanm 0:9b334a45a8ff 225 than the PVD threshold. This event is internally connected to the EXTI
bogdanm 0:9b334a45a8ff 226 line16 and can generate an interrupt if enabled. This is done through
bogdanm 0:9b334a45a8ff 227 __HAL_PVD_EXTI_ENABLE_IT() macro.
bogdanm 0:9b334a45a8ff 228 (+) The PVD is stopped in Standby mode.
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 *** WakeUp pin configuration ***
bogdanm 0:9b334a45a8ff 231 ================================
bogdanm 0:9b334a45a8ff 232 [..]
bogdanm 0:9b334a45a8ff 233 (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
bogdanm 0:9b334a45a8ff 234 forced in input pull-down configuration and is active on rising edges.
bogdanm 0:9b334a45a8ff 235 (+) There is one WakeUp pin:
bogdanm 0:9b334a45a8ff 236 WakeUp Pin 1 on PA.00.
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 [..]
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 *** Low Power modes configuration ***
bogdanm 0:9b334a45a8ff 241 =====================================
bogdanm 0:9b334a45a8ff 242 [..]
bogdanm 0:9b334a45a8ff 243 The device features 3 low-power modes:
bogdanm 0:9b334a45a8ff 244 (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
bogdanm 0:9b334a45a8ff 245 NVIC, SysTick, etc. are kept running
bogdanm 0:9b334a45a8ff 246 (+) Stop mode: All clocks are stopped
bogdanm 0:9b334a45a8ff 247 (+) Standby mode: 1.8V domain powered off
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 *** Sleep mode ***
bogdanm 0:9b334a45a8ff 251 ==================
bogdanm 0:9b334a45a8ff 252 [..]
bogdanm 0:9b334a45a8ff 253 (+) Entry:
bogdanm 0:9b334a45a8ff 254 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
bogdanm 0:9b334a45a8ff 255 functions with
bogdanm 0:9b334a45a8ff 256 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 257 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 (+) Exit:
bogdanm 0:9b334a45a8ff 260 (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
bogdanm 0:9b334a45a8ff 261 controller (NVIC) can wake up the device from Sleep mode.
bogdanm 0:9b334a45a8ff 262 (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
bogdanm 0:9b334a45a8ff 263 (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
bogdanm 0:9b334a45a8ff 264 (+++) Any EXTI Line (Internal or External) configured in Event mode
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 *** Stop mode ***
bogdanm 0:9b334a45a8ff 267 =================
bogdanm 0:9b334a45a8ff 268 [..]
bogdanm 0:9b334a45a8ff 269 The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
bogdanm 0:9b334a45a8ff 270 clock gating. The voltage regulator can be configured either in normal or low-power mode.
bogdanm 0:9b334a45a8ff 271 In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
bogdanm 0:9b334a45a8ff 272 oscillators are disabled. SRAM and register contents are preserved.
bogdanm 0:9b334a45a8ff 273 In Stop mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 (+) Entry:
bogdanm 0:9b334a45a8ff 276 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
bogdanm 0:9b334a45a8ff 277 function with:
bogdanm 0:9b334a45a8ff 278 (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
bogdanm 0:9b334a45a8ff 279 (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
bogdanm 0:9b334a45a8ff 280 (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
bogdanm 0:9b334a45a8ff 281 (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
bogdanm 0:9b334a45a8ff 282 (+) Exit:
bogdanm 0:9b334a45a8ff 283 (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
bogdanm 0:9b334a45a8ff 284 (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 *** Standby mode ***
bogdanm 0:9b334a45a8ff 287 ====================
bogdanm 0:9b334a45a8ff 288 [..]
bogdanm 0:9b334a45a8ff 289 The Standby mode allows to achieve the lowest power consumption. It is based on the
bogdanm 0:9b334a45a8ff 290 Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
bogdanm 0:9b334a45a8ff 291 consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
bogdanm 0:9b334a45a8ff 292 switched off. SRAM and register contents are lost except for registers in the Backup domain
bogdanm 0:9b334a45a8ff 293 and Standby circuitry
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 (+) Entry:
bogdanm 0:9b334a45a8ff 296 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
bogdanm 0:9b334a45a8ff 297 (+) Exit:
bogdanm 0:9b334a45a8ff 298 (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
bogdanm 0:9b334a45a8ff 299 NRSTpin, IWDG Reset
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 *** Auto-wakeup (AWU) from low-power mode ***
bogdanm 0:9b334a45a8ff 302 =============================================
bogdanm 0:9b334a45a8ff 303 [..]
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
bogdanm 0:9b334a45a8ff 306 without depending on an external interrupt (Auto-wakeup mode).
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
bogdanm 0:9b334a45a8ff 311 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 *** PWR Workarounds linked to Silicon Limitation ***
bogdanm 0:9b334a45a8ff 314 ====================================================
bogdanm 0:9b334a45a8ff 315 [..]
bogdanm 0:9b334a45a8ff 316 Below the list of all silicon limitations known on STM32F1xx prouct.
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 (#)Workarounds Implemented inside PWR HAL Driver
bogdanm 0:9b334a45a8ff 319 (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 @endverbatim
bogdanm 0:9b334a45a8ff 322 * @{
bogdanm 0:9b334a45a8ff 323 */
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 /**
bogdanm 0:9b334a45a8ff 326 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 327 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
bogdanm 0:9b334a45a8ff 328 * information for the PVD.
bogdanm 0:9b334a45a8ff 329 * @note Refer to the electrical characteristics of your device datasheet for
bogdanm 0:9b334a45a8ff 330 * more details about the voltage threshold corresponding to each
bogdanm 0:9b334a45a8ff 331 * detection level.
bogdanm 0:9b334a45a8ff 332 * @retval None
bogdanm 0:9b334a45a8ff 333 */
bogdanm 0:9b334a45a8ff 334 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 /* Check the parameters */
bogdanm 0:9b334a45a8ff 337 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
bogdanm 0:9b334a45a8ff 338 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /* Set PLS[7:5] bits according to PVDLevel value */
bogdanm 0:9b334a45a8ff 341 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
bogdanm 0:9b334a45a8ff 344 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
bogdanm 0:9b334a45a8ff 345 __HAL_PWR_PVD_EXTI_DISABLE_IT();
bogdanm 0:9b334a45a8ff 346 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 347 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /* Configure interrupt mode */
bogdanm 0:9b334a45a8ff 350 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
bogdanm 0:9b334a45a8ff 351 {
bogdanm 0:9b334a45a8ff 352 __HAL_PWR_PVD_EXTI_ENABLE_IT();
bogdanm 0:9b334a45a8ff 353 }
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /* Configure event mode */
bogdanm 0:9b334a45a8ff 356 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
bogdanm 0:9b334a45a8ff 357 {
bogdanm 0:9b334a45a8ff 358 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
bogdanm 0:9b334a45a8ff 359 }
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /* Configure the edge */
bogdanm 0:9b334a45a8ff 362 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
bogdanm 0:9b334a45a8ff 363 {
bogdanm 0:9b334a45a8ff 364 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 365 }
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
bogdanm 0:9b334a45a8ff 368 {
bogdanm 0:9b334a45a8ff 369 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 370 }
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /**
bogdanm 0:9b334a45a8ff 374 * @brief Enables the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 375 * @retval None
bogdanm 0:9b334a45a8ff 376 */
bogdanm 0:9b334a45a8ff 377 void HAL_PWR_EnablePVD(void)
bogdanm 0:9b334a45a8ff 378 {
bogdanm 0:9b334a45a8ff 379 /* Enable the power voltage detector */
bogdanm 0:9b334a45a8ff 380 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
bogdanm 0:9b334a45a8ff 381 }
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /**
bogdanm 0:9b334a45a8ff 384 * @brief Disables the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 385 * @retval None
bogdanm 0:9b334a45a8ff 386 */
bogdanm 0:9b334a45a8ff 387 void HAL_PWR_DisablePVD(void)
bogdanm 0:9b334a45a8ff 388 {
bogdanm 0:9b334a45a8ff 389 /* Disable the power voltage detector */
bogdanm 0:9b334a45a8ff 390 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
bogdanm 0:9b334a45a8ff 391 }
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /**
bogdanm 0:9b334a45a8ff 394 * @brief Enables the WakeUp PINx functionality.
bogdanm 0:9b334a45a8ff 395 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
bogdanm 0:9b334a45a8ff 396 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 397 * @arg PWR_WAKEUP_PIN1
bogdanm 0:9b334a45a8ff 398 * @retval None
bogdanm 0:9b334a45a8ff 399 */
bogdanm 0:9b334a45a8ff 400 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 401 {
bogdanm 0:9b334a45a8ff 402 /* Check the parameter */
bogdanm 0:9b334a45a8ff 403 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 404 /* Enable the EWUPx pin */
bogdanm 0:9b334a45a8ff 405 *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
bogdanm 0:9b334a45a8ff 406 }
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 /**
bogdanm 0:9b334a45a8ff 409 * @brief Disables the WakeUp PINx functionality.
bogdanm 0:9b334a45a8ff 410 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
bogdanm 0:9b334a45a8ff 411 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 412 * @arg PWR_WAKEUP_PIN1
bogdanm 0:9b334a45a8ff 413 * @retval None
bogdanm 0:9b334a45a8ff 414 */
bogdanm 0:9b334a45a8ff 415 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 416 {
bogdanm 0:9b334a45a8ff 417 /* Check the parameter */
bogdanm 0:9b334a45a8ff 418 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 419 /* Disable the EWUPx pin */
bogdanm 0:9b334a45a8ff 420 *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423 /**
bogdanm 0:9b334a45a8ff 424 * @brief Enters Sleep mode.
bogdanm 0:9b334a45a8ff 425 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 426 * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
bogdanm 0:9b334a45a8ff 427 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 428 * When WFI entry is used, tick interrupt have to be disabled if not desired as
bogdanm 0:9b334a45a8ff 429 * the interrupt wake up source.
bogdanm 0:9b334a45a8ff 430 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 431 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 432 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 433 * @retval None
bogdanm 0:9b334a45a8ff 434 */
bogdanm 0:9b334a45a8ff 435 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
bogdanm 0:9b334a45a8ff 436 {
bogdanm 0:9b334a45a8ff 437 /* Check the parameters */
bogdanm 0:9b334a45a8ff 438 /* No check on Regulator because parameter not used in SLEEP mode */
bogdanm 0:9b334a45a8ff 439 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 /* Clear SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 442 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /* Select SLEEP mode entry -------------------------------------------------*/
bogdanm 0:9b334a45a8ff 445 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
bogdanm 0:9b334a45a8ff 446 {
bogdanm 0:9b334a45a8ff 447 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 448 __WFI();
bogdanm 0:9b334a45a8ff 449 }
bogdanm 0:9b334a45a8ff 450 else
bogdanm 0:9b334a45a8ff 451 {
bogdanm 0:9b334a45a8ff 452 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 453 __SEV();
bogdanm 0:9b334a45a8ff 454 __WFE();
bogdanm 0:9b334a45a8ff 455 __WFE();
bogdanm 0:9b334a45a8ff 456 }
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 /**
bogdanm 0:9b334a45a8ff 460 * @brief Enters Stop mode.
bogdanm 0:9b334a45a8ff 461 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 462 * @note When exiting Stop mode by using an interrupt or a wakeup event,
bogdanm 0:9b334a45a8ff 463 * HSI RC oscillator is selected as system clock.
bogdanm 0:9b334a45a8ff 464 * @note When the voltage regulator operates in low power mode, an additional
bogdanm 0:9b334a45a8ff 465 * startup delay is incurred when waking up from Stop mode.
bogdanm 0:9b334a45a8ff 466 * By keeping the internal regulator ON during Stop mode, the consumption
bogdanm 0:9b334a45a8ff 467 * is higher although the startup time is reduced.
bogdanm 0:9b334a45a8ff 468 * @param Regulator: Specifies the regulator state in Stop mode.
bogdanm 0:9b334a45a8ff 469 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 470 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
bogdanm 0:9b334a45a8ff 471 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
bogdanm 0:9b334a45a8ff 472 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 473 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 474 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
bogdanm 0:9b334a45a8ff 475 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
bogdanm 0:9b334a45a8ff 476 * @retval None
bogdanm 0:9b334a45a8ff 477 */
bogdanm 0:9b334a45a8ff 478 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 /* Check the parameters */
bogdanm 0:9b334a45a8ff 481 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 482 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
bogdanm 0:9b334a45a8ff 485 CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
bogdanm 0:9b334a45a8ff 488 MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 491 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /* Select Stop mode entry --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 494 if(STOPEntry == PWR_STOPENTRY_WFI)
bogdanm 0:9b334a45a8ff 495 {
bogdanm 0:9b334a45a8ff 496 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 497 __WFI();
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499 else
bogdanm 0:9b334a45a8ff 500 {
bogdanm 0:9b334a45a8ff 501 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 502 __SEV();
bogdanm 0:9b334a45a8ff 503 PWR_OverloadWfe(); /* WFE redefine locally */
bogdanm 0:9b334a45a8ff 504 PWR_OverloadWfe(); /* WFE redefine locally */
bogdanm 0:9b334a45a8ff 505 }
bogdanm 0:9b334a45a8ff 506 /* Reset SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 507 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /**
bogdanm 0:9b334a45a8ff 511 * @brief Enters Standby mode.
bogdanm 0:9b334a45a8ff 512 * @note In Standby mode, all I/O pins are high impedance except for:
bogdanm 0:9b334a45a8ff 513 * - Reset pad (still available)
bogdanm 0:9b334a45a8ff 514 * - TAMPER pin if configured for tamper or calibration out.
bogdanm 0:9b334a45a8ff 515 * - WKUP pin (PA0) if enabled.
bogdanm 0:9b334a45a8ff 516 * @retval None
bogdanm 0:9b334a45a8ff 517 */
bogdanm 0:9b334a45a8ff 518 void HAL_PWR_EnterSTANDBYMode(void)
bogdanm 0:9b334a45a8ff 519 {
bogdanm 0:9b334a45a8ff 520 /* Select Standby mode */
bogdanm 0:9b334a45a8ff 521 SET_BIT(PWR->CR, PWR_CR_PDDS);
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 524 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 /* This option is used to ensure that store operations are completed */
bogdanm 0:9b334a45a8ff 527 #if defined ( __CC_ARM)
bogdanm 0:9b334a45a8ff 528 __force_stores();
bogdanm 0:9b334a45a8ff 529 #endif
bogdanm 0:9b334a45a8ff 530 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 531 __WFI();
bogdanm 0:9b334a45a8ff 532 }
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535 /**
bogdanm 0:9b334a45a8ff 536 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 537 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 538 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 539 * Setting this bit is useful when the processor is expected to run only on
bogdanm 0:9b334a45a8ff 540 * interruptions handling.
bogdanm 0:9b334a45a8ff 541 * @retval None
bogdanm 0:9b334a45a8ff 542 */
bogdanm 0:9b334a45a8ff 543 void HAL_PWR_EnableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 544 {
bogdanm 0:9b334a45a8ff 545 /* Set SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 546 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 547 }
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /**
bogdanm 0:9b334a45a8ff 551 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 552 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 553 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 554 * @retval None
bogdanm 0:9b334a45a8ff 555 */
bogdanm 0:9b334a45a8ff 556 void HAL_PWR_DisableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 557 {
bogdanm 0:9b334a45a8ff 558 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 559 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 560 }
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 /**
bogdanm 0:9b334a45a8ff 564 * @brief Enables CORTEX M3 SEVONPEND bit.
bogdanm 0:9b334a45a8ff 565 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 566 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 567 * @retval None
bogdanm 0:9b334a45a8ff 568 */
bogdanm 0:9b334a45a8ff 569 void HAL_PWR_EnableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 /* Set SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 572 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 573 }
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /**
bogdanm 0:9b334a45a8ff 577 * @brief Disables CORTEX M3 SEVONPEND bit.
bogdanm 0:9b334a45a8ff 578 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 579 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 580 * @retval None
bogdanm 0:9b334a45a8ff 581 */
bogdanm 0:9b334a45a8ff 582 void HAL_PWR_DisableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 583 {
bogdanm 0:9b334a45a8ff 584 /* Clear SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 585 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 586 }
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /**
bogdanm 0:9b334a45a8ff 591 * @brief This function handles the PWR PVD interrupt request.
bogdanm 0:9b334a45a8ff 592 * @note This API should be called under the PVD_IRQHandler().
bogdanm 0:9b334a45a8ff 593 * @retval None
bogdanm 0:9b334a45a8ff 594 */
bogdanm 0:9b334a45a8ff 595 void HAL_PWR_PVD_IRQHandler(void)
bogdanm 0:9b334a45a8ff 596 {
bogdanm 0:9b334a45a8ff 597 /* Check PWR exti flag */
bogdanm 0:9b334a45a8ff 598 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 599 {
bogdanm 0:9b334a45a8ff 600 /* PWR PVD interrupt user callback */
bogdanm 0:9b334a45a8ff 601 HAL_PWR_PVDCallback();
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 /* Clear PWR Exti pending bit */
bogdanm 0:9b334a45a8ff 604 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 605 }
bogdanm 0:9b334a45a8ff 606 }
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 /**
bogdanm 0:9b334a45a8ff 609 * @brief PWR PVD interrupt callback
bogdanm 0:9b334a45a8ff 610 * @retval None
bogdanm 0:9b334a45a8ff 611 */
bogdanm 0:9b334a45a8ff 612 __weak void HAL_PWR_PVDCallback(void)
bogdanm 0:9b334a45a8ff 613 {
bogdanm 0:9b334a45a8ff 614 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 615 the HAL_PWR_PVDCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 616 */
bogdanm 0:9b334a45a8ff 617 }
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 /**
bogdanm 0:9b334a45a8ff 620 * @}
bogdanm 0:9b334a45a8ff 621 */
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /**
bogdanm 0:9b334a45a8ff 624 * @}
bogdanm 0:9b334a45a8ff 625 */
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 #endif /* HAL_PWR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 628 /**
bogdanm 0:9b334a45a8ff 629 * @}
bogdanm 0:9b334a45a8ff 630 */
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 /**
bogdanm 0:9b334a45a8ff 633 * @}
bogdanm 0:9b334a45a8ff 634 */
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/