en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
124:6a4a5b7d7324 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_i2s.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 124:6a4a5b7d7324 5 * @version V1.0.4
mbed_official 124:6a4a5b7d7324 6 * @date 29-April-2016
bogdanm 0:9b334a45a8ff 7 * @brief I2S HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + IO operation functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 13 @verbatim
bogdanm 0:9b334a45a8ff 14 ===============================================================================
bogdanm 0:9b334a45a8ff 15 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 16 ===============================================================================
bogdanm 0:9b334a45a8ff 17 [..]
bogdanm 0:9b334a45a8ff 18 The I2S HAL driver can be used as follow:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (#) Declare a I2S_HandleTypeDef handle structure.
bogdanm 0:9b334a45a8ff 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
bogdanm 0:9b334a45a8ff 22 (##) Enable the SPIx interface clock.
bogdanm 0:9b334a45a8ff 23 (##) I2S pins configuration:
bogdanm 0:9b334a45a8ff 24 (+++) Enable the clock for the I2S GPIOs.
bogdanm 0:9b334a45a8ff 25 (+++) Configure these I2S pins as alternate function.
bogdanm 0:9b334a45a8ff 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
bogdanm 0:9b334a45a8ff 27 and HAL_I2S_Receive_IT() APIs).
bogdanm 0:9b334a45a8ff 28 (+++) Configure the I2Sx interrupt priority.
bogdanm 0:9b334a45a8ff 29 (+++) Enable the NVIC I2S IRQ handle.
bogdanm 0:9b334a45a8ff 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
bogdanm 0:9b334a45a8ff 31 and HAL_I2S_Receive_DMA() APIs:
bogdanm 0:9b334a45a8ff 32 (+++) Declare a DMA handle structure for the Tx/Rx Channel.
bogdanm 0:9b334a45a8ff 33 (+++) Enable the DMAx interface clock.
bogdanm 0:9b334a45a8ff 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
bogdanm 0:9b334a45a8ff 35 (+++) Configure the DMA Tx/Rx Channel.
bogdanm 0:9b334a45a8ff 36 (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
bogdanm 0:9b334a45a8ff 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
bogdanm 0:9b334a45a8ff 38 DMA Tx/Rx Channel.
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
bogdanm 0:9b334a45a8ff 41 using HAL_I2S_Init() function.
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 -@- The specific I2S interrupts (Transmission complete interrupt,
bogdanm 0:9b334a45a8ff 44 RXNE interrupt and Error Interrupts) will be managed using the macros
bogdanm 0:9b334a45a8ff 45 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
bogdanm 0:9b334a45a8ff 46 -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
bogdanm 0:9b334a45a8ff 47 For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock
bogdanm 0:9b334a45a8ff 48 in order to achieve the maximum accuracy.
bogdanm 0:9b334a45a8ff 49 -@- Make sure that either:
bogdanm 0:9b334a45a8ff 50 (+@) External clock source is configured after setting correctly
bogdanm 0:9b334a45a8ff 51 the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 (#) Three mode of operations are available within this driver :
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 56 =================================
bogdanm 0:9b334a45a8ff 57 [..]
bogdanm 0:9b334a45a8ff 58 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
bogdanm 0:9b334a45a8ff 59 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 62 ===================================
bogdanm 0:9b334a45a8ff 63 [..]
bogdanm 0:9b334a45a8ff 64 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
bogdanm 0:9b334a45a8ff 65 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 66 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm 0:9b334a45a8ff 67 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 68 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm 0:9b334a45a8ff 69 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
bogdanm 0:9b334a45a8ff 70 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 71 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm 0:9b334a45a8ff 72 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 73 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm 0:9b334a45a8ff 74 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm 0:9b334a45a8ff 75 add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 *** DMA mode IO operation ***
bogdanm 0:9b334a45a8ff 78 ==============================
bogdanm 0:9b334a45a8ff 79 [..]
bogdanm 0:9b334a45a8ff 80 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
bogdanm 0:9b334a45a8ff 81 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 82 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm 0:9b334a45a8ff 83 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 84 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm 0:9b334a45a8ff 85 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
bogdanm 0:9b334a45a8ff 86 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 87 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm 0:9b334a45a8ff 88 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 89 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm 0:9b334a45a8ff 90 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm 0:9b334a45a8ff 91 add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm 0:9b334a45a8ff 92 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
bogdanm 0:9b334a45a8ff 93 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
bogdanm 0:9b334a45a8ff 94 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 *** I2S HAL driver macros list ***
bogdanm 0:9b334a45a8ff 97 =============================================
bogdanm 0:9b334a45a8ff 98 [..]
bogdanm 0:9b334a45a8ff 99 Below the list of most used macros in USART HAL driver.
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
bogdanm 0:9b334a45a8ff 102 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
bogdanm 0:9b334a45a8ff 103 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
bogdanm 0:9b334a45a8ff 104 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
bogdanm 0:9b334a45a8ff 105 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 [..]
bogdanm 0:9b334a45a8ff 108 (@) You can refer to the I2S HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 *** I2C Workarounds linked to Silicon Limitation ***
bogdanm 0:9b334a45a8ff 112 ====================================================
bogdanm 0:9b334a45a8ff 113 [..]
bogdanm 0:9b334a45a8ff 114 (@) Only the 16-bit mode with no data extension can be used when the I2S
bogdanm 0:9b334a45a8ff 115 is in Master and used the PCM long synchronization mode.
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 @endverbatim
bogdanm 0:9b334a45a8ff 119 ******************************************************************************
bogdanm 0:9b334a45a8ff 120 * @attention
bogdanm 0:9b334a45a8ff 121 *
mbed_official 124:6a4a5b7d7324 122 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 123 *
bogdanm 0:9b334a45a8ff 124 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 125 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 126 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 127 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 128 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 129 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 130 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 131 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 132 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 133 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 134 *
bogdanm 0:9b334a45a8ff 135 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 136 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 137 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 138 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 139 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 140 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 141 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 142 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 143 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 145 *
bogdanm 0:9b334a45a8ff 146 ******************************************************************************
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 150 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 153 * @{
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 #ifdef HAL_I2S_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 157 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /** @defgroup I2S I2S
bogdanm 0:9b334a45a8ff 160 * @brief I2S HAL module driver
bogdanm 0:9b334a45a8ff 161 * @{
bogdanm 0:9b334a45a8ff 162 */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 165 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 166 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 167 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 168 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 169 /** @addtogroup I2S_Private_Functions I2S Private Functions
bogdanm 0:9b334a45a8ff 170 * @{
bogdanm 0:9b334a45a8ff 171 */
bogdanm 0:9b334a45a8ff 172 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 173 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 174 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 175 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 176 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 177 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
bogdanm 0:9b334a45a8ff 178 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
bogdanm 0:9b334a45a8ff 179 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 180 /**
bogdanm 0:9b334a45a8ff 181 * @}
bogdanm 0:9b334a45a8ff 182 */
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 185 /** @defgroup I2S_Exported_Functions I2S Exported Functions
bogdanm 0:9b334a45a8ff 186 * @{
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 190 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 191 *
bogdanm 0:9b334a45a8ff 192 @verbatim
bogdanm 0:9b334a45a8ff 193 ===============================================================================
bogdanm 0:9b334a45a8ff 194 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 195 ===============================================================================
bogdanm 0:9b334a45a8ff 196 [..] This subsection provides a set of functions allowing to initialize and
bogdanm 0:9b334a45a8ff 197 de-initialiaze the I2Sx peripheral in simplex mode:
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 (+) User must Implement HAL_I2S_MspInit() function in which he configures
bogdanm 0:9b334a45a8ff 200 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 (+) Call the function HAL_I2S_Init() to configure the selected device with
bogdanm 0:9b334a45a8ff 203 the selected configuration:
bogdanm 0:9b334a45a8ff 204 (++) Mode
bogdanm 0:9b334a45a8ff 205 (++) Standard
bogdanm 0:9b334a45a8ff 206 (++) Data Format
bogdanm 0:9b334a45a8ff 207 (++) MCLK Output
bogdanm 0:9b334a45a8ff 208 (++) Audio frequency
bogdanm 0:9b334a45a8ff 209 (++) Polarity
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
bogdanm 0:9b334a45a8ff 212 of the selected I2Sx periperal.
bogdanm 0:9b334a45a8ff 213 @endverbatim
bogdanm 0:9b334a45a8ff 214 * @{
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /**
bogdanm 0:9b334a45a8ff 218 * @brief Initializes the I2S according to the specified parameters
bogdanm 0:9b334a45a8ff 219 * in the I2S_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 220 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 221 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 222 * @retval HAL status
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 225 {
bogdanm 0:9b334a45a8ff 226 uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
bogdanm 0:9b334a45a8ff 227 uint32_t tmp = 0, i2sclk = 0;
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 /* Check the I2S handle allocation */
bogdanm 0:9b334a45a8ff 230 if(hi2s == NULL)
bogdanm 0:9b334a45a8ff 231 {
bogdanm 0:9b334a45a8ff 232 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 233 }
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /* Check the I2S parameters */
bogdanm 0:9b334a45a8ff 236 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
bogdanm 0:9b334a45a8ff 237 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
bogdanm 0:9b334a45a8ff 238 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
bogdanm 0:9b334a45a8ff 239 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
bogdanm 0:9b334a45a8ff 240 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
bogdanm 0:9b334a45a8ff 241 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
bogdanm 0:9b334a45a8ff 242 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 if(hi2s->State == HAL_I2S_STATE_RESET)
bogdanm 0:9b334a45a8ff 245 {
bogdanm 0:9b334a45a8ff 246 /* Allocate lock resource and initialize it */
mbed_official 124:6a4a5b7d7324 247 hi2s->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
bogdanm 0:9b334a45a8ff 250 HAL_I2S_MspInit(hi2s);
bogdanm 0:9b334a45a8ff 251 }
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
bogdanm 0:9b334a45a8ff 256 if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
bogdanm 0:9b334a45a8ff 257 {
bogdanm 0:9b334a45a8ff 258 i2sodd = (uint32_t)0;
bogdanm 0:9b334a45a8ff 259 i2sdiv = (uint32_t)2;
bogdanm 0:9b334a45a8ff 260 }
bogdanm 0:9b334a45a8ff 261 /* If the requested audio frequency is not the default, compute the prescaler */
bogdanm 0:9b334a45a8ff 262 else
bogdanm 0:9b334a45a8ff 263 {
bogdanm 0:9b334a45a8ff 264 /* Check the frame length (For the Prescaler computing) *******************/
bogdanm 0:9b334a45a8ff 265 if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
bogdanm 0:9b334a45a8ff 266 {
bogdanm 0:9b334a45a8ff 267 /* Packet length is 16 bits */
bogdanm 0:9b334a45a8ff 268 packetlength = 1;
bogdanm 0:9b334a45a8ff 269 }
bogdanm 0:9b334a45a8ff 270 else
bogdanm 0:9b334a45a8ff 271 {
bogdanm 0:9b334a45a8ff 272 /* Packet length is 32 bits */
bogdanm 0:9b334a45a8ff 273 packetlength = 2;
bogdanm 0:9b334a45a8ff 274 }
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 if(hi2s->Instance == SPI2)
bogdanm 0:9b334a45a8ff 277 {
bogdanm 0:9b334a45a8ff 278 /* Get the source clock value: based on SPI2 Instance */
bogdanm 0:9b334a45a8ff 279 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2);
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281 else if(hi2s->Instance == SPI3)
bogdanm 0:9b334a45a8ff 282 {
bogdanm 0:9b334a45a8ff 283 /* Get the source clock value: based on SPI3 Instance */
bogdanm 0:9b334a45a8ff 284 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S3);
bogdanm 0:9b334a45a8ff 285 }
bogdanm 0:9b334a45a8ff 286 else
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 /* Get the source clock value: based on System Clock value */
bogdanm 0:9b334a45a8ff 289 i2sclk = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 290 }
bogdanm 0:9b334a45a8ff 291 if(i2sclk == 0)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 294 }
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /* Compute the Real divider depending on the MCLK output state, with a floating point */
bogdanm 0:9b334a45a8ff 297 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
bogdanm 0:9b334a45a8ff 298 {
bogdanm 0:9b334a45a8ff 299 /* MCLK output is enabled */
bogdanm 0:9b334a45a8ff 300 tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302 else
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 /* MCLK output is disabled */
bogdanm 0:9b334a45a8ff 305 tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /* Remove the flatting point */
bogdanm 0:9b334a45a8ff 309 tmp = tmp / 10;
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /* Check the parity of the divider */
bogdanm 0:9b334a45a8ff 312 i2sodd = (uint32_t)(tmp & (uint32_t)1);
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 /* Compute the i2sdiv prescaler */
bogdanm 0:9b334a45a8ff 315 i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
bogdanm 0:9b334a45a8ff 318 i2sodd = (uint32_t) (i2sodd << 8);
bogdanm 0:9b334a45a8ff 319 }
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 /* Test if the divider is 1 or 0 or greater than 0xFF */
bogdanm 0:9b334a45a8ff 322 if((i2sdiv < 2) || (i2sdiv > 0xFF))
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 /* Set the default values */
bogdanm 0:9b334a45a8ff 325 i2sdiv = 2;
bogdanm 0:9b334a45a8ff 326 i2sodd = 0;
bogdanm 0:9b334a45a8ff 327 }
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
bogdanm 0:9b334a45a8ff 330 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm 0:9b334a45a8ff 331 /* And configure the I2S with the I2S_InitStruct values */
bogdanm 0:9b334a45a8ff 332 MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
bogdanm 0:9b334a45a8ff 333 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
bogdanm 0:9b334a45a8ff 334 SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
bogdanm 0:9b334a45a8ff 335 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\
bogdanm 0:9b334a45a8ff 336 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
bogdanm 0:9b334a45a8ff 337 hi2s->Init.Standard | hi2s->Init.DataFormat |\
bogdanm 0:9b334a45a8ff 338 hi2s->Init.CPOL));
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /* Write to SPIx I2SPR register the computed value */
bogdanm 0:9b334a45a8ff 341 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 344 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 return HAL_OK;
bogdanm 0:9b334a45a8ff 347 }
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /**
bogdanm 0:9b334a45a8ff 350 * @brief DeInitializes the I2S peripheral
bogdanm 0:9b334a45a8ff 351 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 352 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 353 * @retval HAL status
bogdanm 0:9b334a45a8ff 354 */
bogdanm 0:9b334a45a8ff 355 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 356 {
bogdanm 0:9b334a45a8ff 357 /* Check the I2S handle allocation */
bogdanm 0:9b334a45a8ff 358 if(hi2s == NULL)
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 361 }
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /* Disable the I2S Peripheral Clock */
bogdanm 0:9b334a45a8ff 366 __HAL_I2S_DISABLE(hi2s);
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm 0:9b334a45a8ff 369 HAL_I2S_MspDeInit(hi2s);
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 372 hi2s->State = HAL_I2S_STATE_RESET;
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /* Release Lock */
bogdanm 0:9b334a45a8ff 375 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 return HAL_OK;
bogdanm 0:9b334a45a8ff 378 }
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 /**
bogdanm 0:9b334a45a8ff 381 * @brief I2S MSP Init
bogdanm 0:9b334a45a8ff 382 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 383 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 384 * @retval None
bogdanm 0:9b334a45a8ff 385 */
bogdanm 0:9b334a45a8ff 386 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 387 {
mbed_official 124:6a4a5b7d7324 388 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 389 UNUSED(hi2s);
bogdanm 0:9b334a45a8ff 390 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 391 the HAL_I2S_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 392 */
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /**
bogdanm 0:9b334a45a8ff 396 * @brief I2S MSP DeInit
bogdanm 0:9b334a45a8ff 397 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 398 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 399 * @retval None
bogdanm 0:9b334a45a8ff 400 */
bogdanm 0:9b334a45a8ff 401 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 402 {
mbed_official 124:6a4a5b7d7324 403 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 404 UNUSED(hi2s);
bogdanm 0:9b334a45a8ff 405 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 406 the HAL_I2S_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 407 */
bogdanm 0:9b334a45a8ff 408 }
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /**
bogdanm 0:9b334a45a8ff 411 * @}
bogdanm 0:9b334a45a8ff 412 */
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
bogdanm 0:9b334a45a8ff 415 * @brief Data transfers functions
bogdanm 0:9b334a45a8ff 416 *
bogdanm 0:9b334a45a8ff 417 @verbatim
bogdanm 0:9b334a45a8ff 418 ===============================================================================
bogdanm 0:9b334a45a8ff 419 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 420 ===============================================================================
bogdanm 0:9b334a45a8ff 421 [..]
bogdanm 0:9b334a45a8ff 422 This subsection provides a set of functions allowing to manage the I2S data
bogdanm 0:9b334a45a8ff 423 transfers.
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 (#) There are two modes of transfer:
bogdanm 0:9b334a45a8ff 426 (++) Blocking mode : The communication is performed in the polling mode.
bogdanm 0:9b334a45a8ff 427 The status of all data processing is returned by the same function
bogdanm 0:9b334a45a8ff 428 after finishing transfer.
bogdanm 0:9b334a45a8ff 429 (++) No-Blocking mode : The communication is performed using Interrupts
bogdanm 0:9b334a45a8ff 430 or DMA. These functions return the status of the transfer startup.
bogdanm 0:9b334a45a8ff 431 The end of the data processing will be indicated through the
bogdanm 0:9b334a45a8ff 432 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
bogdanm 0:9b334a45a8ff 433 using DMA mode.
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 (#) Blocking mode functions are :
bogdanm 0:9b334a45a8ff 436 (++) HAL_I2S_Transmit()
bogdanm 0:9b334a45a8ff 437 (++) HAL_I2S_Receive()
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 (#) No-Blocking mode functions with Interrupt are :
bogdanm 0:9b334a45a8ff 440 (++) HAL_I2S_Transmit_IT()
bogdanm 0:9b334a45a8ff 441 (++) HAL_I2S_Receive_IT()
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 (#) No-Blocking mode functions with DMA are :
bogdanm 0:9b334a45a8ff 444 (++) HAL_I2S_Transmit_DMA()
bogdanm 0:9b334a45a8ff 445 (++) HAL_I2S_Receive_DMA()
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm 0:9b334a45a8ff 448 (++) HAL_I2S_TxCpltCallback()
bogdanm 0:9b334a45a8ff 449 (++) HAL_I2S_RxCpltCallback()
bogdanm 0:9b334a45a8ff 450 (++) HAL_I2S_ErrorCallback()
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 @endverbatim
bogdanm 0:9b334a45a8ff 453 * @{
bogdanm 0:9b334a45a8ff 454 */
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /**
bogdanm 0:9b334a45a8ff 457 * @brief Transmit an amount of data in blocking mode
bogdanm 0:9b334a45a8ff 458 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 459 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 460 * @param pData: a 16-bit pointer to data buffer.
bogdanm 0:9b334a45a8ff 461 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 462 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 463 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 464 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 465 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 466 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 467 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 468 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 469 * @retval HAL status
bogdanm 0:9b334a45a8ff 470 */
bogdanm 0:9b334a45a8ff 471 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 472 {
bogdanm 0:9b334a45a8ff 473 if((pData == NULL ) || (Size == 0))
bogdanm 0:9b334a45a8ff 474 {
bogdanm 0:9b334a45a8ff 475 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 476 }
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /* Process Locked */
bogdanm 0:9b334a45a8ff 479 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 482 {
bogdanm 0:9b334a45a8ff 483 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 484 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 485 {
bogdanm 0:9b334a45a8ff 486 hi2s->TxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 487 hi2s->TxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 488 }
bogdanm 0:9b334a45a8ff 489 else
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 492 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 493 }
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* Set state and reset error code */
bogdanm 0:9b334a45a8ff 496 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 497 hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm 0:9b334a45a8ff 498 hi2s->pTxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 501 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 502 {
bogdanm 0:9b334a45a8ff 503 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 504 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 505 }
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 while(hi2s->TxXferCount > 0)
bogdanm 0:9b334a45a8ff 508 {
bogdanm 0:9b334a45a8ff 509 /* Wait until TXE flag is set */
bogdanm 0:9b334a45a8ff 510 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 511 {
bogdanm 0:9b334a45a8ff 512 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 513 }
bogdanm 0:9b334a45a8ff 514 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm 0:9b334a45a8ff 515 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* Check if an underrun occurs */
bogdanm 0:9b334a45a8ff 518 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
bogdanm 0:9b334a45a8ff 519 {
bogdanm 0:9b334a45a8ff 520 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 521 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 524 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 /* Set the error code and execute error callback*/
bogdanm 0:9b334a45a8ff 527 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
bogdanm 0:9b334a45a8ff 528 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 529 }
bogdanm 0:9b334a45a8ff 530 }
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 /* Wait until TXE flag is set, to confirm the end of the transcation */
bogdanm 0:9b334a45a8ff 533 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 534 {
bogdanm 0:9b334a45a8ff 535 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 536 }
mbed_official 124:6a4a5b7d7324 537 /* Check if Slave mode is selected */
mbed_official 124:6a4a5b7d7324 538 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
bogdanm 0:9b334a45a8ff 539 {
mbed_official 124:6a4a5b7d7324 540 /* Wait until Busy flag is reset */
mbed_official 124:6a4a5b7d7324 541 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official 124:6a4a5b7d7324 542 {
mbed_official 124:6a4a5b7d7324 543 return HAL_TIMEOUT;
mbed_official 124:6a4a5b7d7324 544 }
bogdanm 0:9b334a45a8ff 545 }
bogdanm 0:9b334a45a8ff 546 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 549 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 return HAL_OK;
bogdanm 0:9b334a45a8ff 552 }
bogdanm 0:9b334a45a8ff 553 else
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 556 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 557 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 558 }
bogdanm 0:9b334a45a8ff 559 }
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 /**
bogdanm 0:9b334a45a8ff 562 * @brief Receive an amount of data in blocking mode
bogdanm 0:9b334a45a8ff 563 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 564 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 565 * @param pData: a 16-bit pointer to data buffer.
bogdanm 0:9b334a45a8ff 566 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 567 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 568 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 569 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 570 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 571 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 572 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 573 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 574 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
bogdanm 0:9b334a45a8ff 575 * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
bogdanm 0:9b334a45a8ff 576 * @retval HAL status
bogdanm 0:9b334a45a8ff 577 */
bogdanm 0:9b334a45a8ff 578 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 579 {
bogdanm 0:9b334a45a8ff 580 if((pData == NULL ) || (Size == 0))
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 583 }
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 /* Process Locked */
bogdanm 0:9b334a45a8ff 586 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 589 {
bogdanm 0:9b334a45a8ff 590 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 591 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 592 {
bogdanm 0:9b334a45a8ff 593 hi2s->RxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 594 hi2s->RxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 595 }
bogdanm 0:9b334a45a8ff 596 else
bogdanm 0:9b334a45a8ff 597 {
bogdanm 0:9b334a45a8ff 598 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 599 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 600 }
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /* Set state and reset error code */
bogdanm 0:9b334a45a8ff 603 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 604 hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm 0:9b334a45a8ff 605 hi2s->pRxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 608 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 609 {
bogdanm 0:9b334a45a8ff 610 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 611 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 612 }
bogdanm 0:9b334a45a8ff 613
bogdanm 0:9b334a45a8ff 614 /* Receive data */
bogdanm 0:9b334a45a8ff 615 while(hi2s->RxXferCount > 0)
bogdanm 0:9b334a45a8ff 616 {
bogdanm 0:9b334a45a8ff 617 /* Wait until RXNE flag is reset */
bogdanm 0:9b334a45a8ff 618 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 619 {
bogdanm 0:9b334a45a8ff 620 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 621 }
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm 0:9b334a45a8ff 624 hi2s->RxXferCount--;
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /* Check if an overrun occurs */
bogdanm 0:9b334a45a8ff 627 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
bogdanm 0:9b334a45a8ff 628 {
bogdanm 0:9b334a45a8ff 629 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 630 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 633 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635 /* Set the error code and execute error callback*/
bogdanm 0:9b334a45a8ff 636 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
bogdanm 0:9b334a45a8ff 637 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 638 }
bogdanm 0:9b334a45a8ff 639 }
bogdanm 0:9b334a45a8ff 640
bogdanm 0:9b334a45a8ff 641 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 644 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 645
bogdanm 0:9b334a45a8ff 646 return HAL_OK;
bogdanm 0:9b334a45a8ff 647 }
bogdanm 0:9b334a45a8ff 648 else
bogdanm 0:9b334a45a8ff 649 {
bogdanm 0:9b334a45a8ff 650 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 651 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 652 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 653 }
bogdanm 0:9b334a45a8ff 654 }
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 /**
bogdanm 0:9b334a45a8ff 657 * @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 658 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 659 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 660 * @param pData: a 16-bit pointer to data buffer.
bogdanm 0:9b334a45a8ff 661 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 662 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 663 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 664 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 665 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 666 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 667 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 668 * @retval HAL status
bogdanm 0:9b334a45a8ff 669 */
bogdanm 0:9b334a45a8ff 670 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
bogdanm 0:9b334a45a8ff 671 {
bogdanm 0:9b334a45a8ff 672 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 675 }
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* Process Locked */
bogdanm 0:9b334a45a8ff 678 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 681 {
bogdanm 0:9b334a45a8ff 682 hi2s->pTxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 683 hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm 0:9b334a45a8ff 684 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 687 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 688 {
bogdanm 0:9b334a45a8ff 689 hi2s->TxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 690 hi2s->TxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 691 }
bogdanm 0:9b334a45a8ff 692 else
bogdanm 0:9b334a45a8ff 693 {
bogdanm 0:9b334a45a8ff 694 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 695 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 696 }
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 /* Enable TXE and ERR interrupt */
bogdanm 0:9b334a45a8ff 699 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 702 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 703 {
bogdanm 0:9b334a45a8ff 704 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 705 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 706 }
bogdanm 0:9b334a45a8ff 707
bogdanm 0:9b334a45a8ff 708 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 709 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 return HAL_OK;
bogdanm 0:9b334a45a8ff 712 }
bogdanm 0:9b334a45a8ff 713 else
bogdanm 0:9b334a45a8ff 714 {
bogdanm 0:9b334a45a8ff 715 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 716 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 717 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 718 }
bogdanm 0:9b334a45a8ff 719 }
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 /**
bogdanm 0:9b334a45a8ff 722 * @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 723 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 724 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 725 * @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm 0:9b334a45a8ff 726 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 727 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 728 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 729 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 730 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 731 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 732 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 733 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
bogdanm 0:9b334a45a8ff 734 * between Master and Slave otherwise the I2S interrupt should be optimized.
bogdanm 0:9b334a45a8ff 735 * @retval HAL status
bogdanm 0:9b334a45a8ff 736 */
bogdanm 0:9b334a45a8ff 737 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
bogdanm 0:9b334a45a8ff 738 {
bogdanm 0:9b334a45a8ff 739 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 740 {
bogdanm 0:9b334a45a8ff 741 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 742 }
bogdanm 0:9b334a45a8ff 743
bogdanm 0:9b334a45a8ff 744 /* Process Locked */
bogdanm 0:9b334a45a8ff 745 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 748 {
bogdanm 0:9b334a45a8ff 749 hi2s->pRxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 750 hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm 0:9b334a45a8ff 751 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 752
bogdanm 0:9b334a45a8ff 753 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 754 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 755 {
bogdanm 0:9b334a45a8ff 756 hi2s->RxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 757 hi2s->RxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 758 }
bogdanm 0:9b334a45a8ff 759 else
bogdanm 0:9b334a45a8ff 760 {
bogdanm 0:9b334a45a8ff 761 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 762 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 763 }
bogdanm 0:9b334a45a8ff 764
bogdanm 0:9b334a45a8ff 765 /* Enable RXNE and ERR interrupt */
bogdanm 0:9b334a45a8ff 766 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 767
bogdanm 0:9b334a45a8ff 768 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 769 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 770 {
bogdanm 0:9b334a45a8ff 771 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 772 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 773 }
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 776 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 777
bogdanm 0:9b334a45a8ff 778 return HAL_OK;
bogdanm 0:9b334a45a8ff 779 }
bogdanm 0:9b334a45a8ff 780 else
bogdanm 0:9b334a45a8ff 781 {
bogdanm 0:9b334a45a8ff 782 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 783 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 784 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 785 }
bogdanm 0:9b334a45a8ff 786 }
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 /**
bogdanm 0:9b334a45a8ff 789 * @brief Transmit an amount of data in non-blocking mode with DMA
bogdanm 0:9b334a45a8ff 790 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 791 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 792 * @param pData: a 16-bit pointer to the Transmit data buffer.
bogdanm 0:9b334a45a8ff 793 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 794 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 795 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 796 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 797 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 798 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 799 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 800 * @retval HAL status
bogdanm 0:9b334a45a8ff 801 */
bogdanm 0:9b334a45a8ff 802 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
bogdanm 0:9b334a45a8ff 803 {
bogdanm 0:9b334a45a8ff 804 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 805 {
bogdanm 0:9b334a45a8ff 806 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808
bogdanm 0:9b334a45a8ff 809 /* Process Locked */
bogdanm 0:9b334a45a8ff 810 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 811
bogdanm 0:9b334a45a8ff 812 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 813 {
bogdanm 0:9b334a45a8ff 814 hi2s->pTxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 815 hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm 0:9b334a45a8ff 816 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 819 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 820 {
bogdanm 0:9b334a45a8ff 821 hi2s->TxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 822 hi2s->TxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 823 }
bogdanm 0:9b334a45a8ff 824 else
bogdanm 0:9b334a45a8ff 825 {
bogdanm 0:9b334a45a8ff 826 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 827 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 828 }
bogdanm 0:9b334a45a8ff 829
bogdanm 0:9b334a45a8ff 830 /* Set the I2S Tx DMA Half transfert complete callback */
bogdanm 0:9b334a45a8ff 831 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /* Set the I2S Tx DMA transfert complete callback */
bogdanm 0:9b334a45a8ff 834 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
bogdanm 0:9b334a45a8ff 835
bogdanm 0:9b334a45a8ff 836 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 837 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
bogdanm 0:9b334a45a8ff 838
bogdanm 0:9b334a45a8ff 839 /* Enable the Tx DMA Channel */
bogdanm 0:9b334a45a8ff 840 HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
bogdanm 0:9b334a45a8ff 841
bogdanm 0:9b334a45a8ff 842 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 843 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
bogdanm 0:9b334a45a8ff 844 {
bogdanm 0:9b334a45a8ff 845 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 846 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 847 }
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 /* Check if the I2S Tx request is already enabled */
bogdanm 0:9b334a45a8ff 850 if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
bogdanm 0:9b334a45a8ff 851 {
bogdanm 0:9b334a45a8ff 852 /* Enable Tx DMA Request */
bogdanm 0:9b334a45a8ff 853 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 854 }
bogdanm 0:9b334a45a8ff 855
bogdanm 0:9b334a45a8ff 856 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 857 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 858
bogdanm 0:9b334a45a8ff 859 return HAL_OK;
bogdanm 0:9b334a45a8ff 860 }
bogdanm 0:9b334a45a8ff 861 else
bogdanm 0:9b334a45a8ff 862 {
bogdanm 0:9b334a45a8ff 863 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 864 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 865 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 866 }
bogdanm 0:9b334a45a8ff 867 }
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 /**
bogdanm 0:9b334a45a8ff 870 * @brief Receive an amount of data in non-blocking mode with DMA
bogdanm 0:9b334a45a8ff 871 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 872 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 873 * @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm 0:9b334a45a8ff 874 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 875 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 876 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 877 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 878 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 879 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 880 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 881 * @retval HAL status
bogdanm 0:9b334a45a8ff 882 */
bogdanm 0:9b334a45a8ff 883 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
bogdanm 0:9b334a45a8ff 884 {
bogdanm 0:9b334a45a8ff 885 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 886 {
bogdanm 0:9b334a45a8ff 887 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 888 }
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /* Process Locked */
bogdanm 0:9b334a45a8ff 891 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 892
bogdanm 0:9b334a45a8ff 893 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 894 {
bogdanm 0:9b334a45a8ff 895 hi2s->pRxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 896 hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm 0:9b334a45a8ff 897 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 898
bogdanm 0:9b334a45a8ff 899 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 900 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 901 {
bogdanm 0:9b334a45a8ff 902 hi2s->RxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 903 hi2s->RxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 904 }
bogdanm 0:9b334a45a8ff 905 else
bogdanm 0:9b334a45a8ff 906 {
bogdanm 0:9b334a45a8ff 907 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 908 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 909 }
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911
bogdanm 0:9b334a45a8ff 912 /* Set the I2S Rx DMA Half transfert complete callback */
bogdanm 0:9b334a45a8ff 913 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
bogdanm 0:9b334a45a8ff 914
bogdanm 0:9b334a45a8ff 915 /* Set the I2S Rx DMA transfert complete callback */
bogdanm 0:9b334a45a8ff 916 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
bogdanm 0:9b334a45a8ff 917
bogdanm 0:9b334a45a8ff 918 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 919 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
bogdanm 0:9b334a45a8ff 920
bogdanm 0:9b334a45a8ff 921 /* Check if Master Receiver mode is selected */
bogdanm 0:9b334a45a8ff 922 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm 0:9b334a45a8ff 923 {
bogdanm 0:9b334a45a8ff 924 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
bogdanm 0:9b334a45a8ff 925 access to the SPI_SR register. */
bogdanm 0:9b334a45a8ff 926 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm 0:9b334a45a8ff 927 }
bogdanm 0:9b334a45a8ff 928
bogdanm 0:9b334a45a8ff 929 /* Enable the Rx DMA Channel */
bogdanm 0:9b334a45a8ff 930 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 933 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
bogdanm 0:9b334a45a8ff 934 {
bogdanm 0:9b334a45a8ff 935 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 936 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 937 }
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 /* Check if the I2S Rx request is already enabled */
bogdanm 0:9b334a45a8ff 940 if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
bogdanm 0:9b334a45a8ff 941 {
bogdanm 0:9b334a45a8ff 942 /* Enable Rx DMA Request */
bogdanm 0:9b334a45a8ff 943 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 944 }
bogdanm 0:9b334a45a8ff 945
bogdanm 0:9b334a45a8ff 946 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 947 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 948
bogdanm 0:9b334a45a8ff 949 return HAL_OK;
bogdanm 0:9b334a45a8ff 950 }
bogdanm 0:9b334a45a8ff 951 else
bogdanm 0:9b334a45a8ff 952 {
bogdanm 0:9b334a45a8ff 953 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 954 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 955 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 956 }
bogdanm 0:9b334a45a8ff 957 }
bogdanm 0:9b334a45a8ff 958
bogdanm 0:9b334a45a8ff 959 /**
bogdanm 0:9b334a45a8ff 960 * @brief Pauses the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 961 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 962 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 963 * @retval HAL status
bogdanm 0:9b334a45a8ff 964 */
bogdanm 0:9b334a45a8ff 965 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 966 {
bogdanm 0:9b334a45a8ff 967 /* Process Locked */
bogdanm 0:9b334a45a8ff 968 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 969
bogdanm 0:9b334a45a8ff 970 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm 0:9b334a45a8ff 971 {
bogdanm 0:9b334a45a8ff 972 /* Disable the I2S DMA Tx request */
bogdanm 0:9b334a45a8ff 973 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 974 }
bogdanm 0:9b334a45a8ff 975 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm 0:9b334a45a8ff 976 {
bogdanm 0:9b334a45a8ff 977 /* Disable the I2S DMA Rx request */
bogdanm 0:9b334a45a8ff 978 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 979 }
bogdanm 0:9b334a45a8ff 980
bogdanm 0:9b334a45a8ff 981 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 982 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 return HAL_OK;
bogdanm 0:9b334a45a8ff 985 }
bogdanm 0:9b334a45a8ff 986
bogdanm 0:9b334a45a8ff 987 /**
bogdanm 0:9b334a45a8ff 988 * @brief Resumes the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 989 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 990 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 991 * @retval HAL status
bogdanm 0:9b334a45a8ff 992 */
bogdanm 0:9b334a45a8ff 993 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 994 {
bogdanm 0:9b334a45a8ff 995 /* Process Locked */
bogdanm 0:9b334a45a8ff 996 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 997
bogdanm 0:9b334a45a8ff 998 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm 0:9b334a45a8ff 999 {
bogdanm 0:9b334a45a8ff 1000 /* Enable the I2S DMA Tx request */
bogdanm 0:9b334a45a8ff 1001 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 1002 }
bogdanm 0:9b334a45a8ff 1003 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm 0:9b334a45a8ff 1004 {
bogdanm 0:9b334a45a8ff 1005 /* Enable the I2S DMA Rx request */
bogdanm 0:9b334a45a8ff 1006 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 1007 }
bogdanm 0:9b334a45a8ff 1008
bogdanm 0:9b334a45a8ff 1009 /* If the I2S peripheral is still not enabled, enable it */
bogdanm 0:9b334a45a8ff 1010 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
bogdanm 0:9b334a45a8ff 1011 {
bogdanm 0:9b334a45a8ff 1012 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 1013 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 1014 }
bogdanm 0:9b334a45a8ff 1015
bogdanm 0:9b334a45a8ff 1016 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1017 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 1018
bogdanm 0:9b334a45a8ff 1019 return HAL_OK;
bogdanm 0:9b334a45a8ff 1020 }
bogdanm 0:9b334a45a8ff 1021
bogdanm 0:9b334a45a8ff 1022 /**
bogdanm 0:9b334a45a8ff 1023 * @brief Resumes the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 1024 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1025 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1026 * @retval HAL status
bogdanm 0:9b334a45a8ff 1027 */
bogdanm 0:9b334a45a8ff 1028 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1029 {
bogdanm 0:9b334a45a8ff 1030 /* Process Locked */
bogdanm 0:9b334a45a8ff 1031 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 1032
bogdanm 0:9b334a45a8ff 1033 /* Disable the I2S Tx/Rx DMA requests */
bogdanm 0:9b334a45a8ff 1034 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 1035 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 /* Abort the I2S DMA Channel tx */
bogdanm 0:9b334a45a8ff 1038 if(hi2s->hdmatx != NULL)
bogdanm 0:9b334a45a8ff 1039 {
bogdanm 0:9b334a45a8ff 1040 /* Disable the I2S DMA channel */
bogdanm 0:9b334a45a8ff 1041 __HAL_DMA_DISABLE(hi2s->hdmatx);
bogdanm 0:9b334a45a8ff 1042 HAL_DMA_Abort(hi2s->hdmatx);
bogdanm 0:9b334a45a8ff 1043 }
bogdanm 0:9b334a45a8ff 1044 /* Abort the I2S DMA Channel rx */
bogdanm 0:9b334a45a8ff 1045 if(hi2s->hdmarx != NULL)
bogdanm 0:9b334a45a8ff 1046 {
bogdanm 0:9b334a45a8ff 1047 /* Disable the I2S DMA channel */
bogdanm 0:9b334a45a8ff 1048 __HAL_DMA_DISABLE(hi2s->hdmarx);
bogdanm 0:9b334a45a8ff 1049 HAL_DMA_Abort(hi2s->hdmarx);
bogdanm 0:9b334a45a8ff 1050 }
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 /* Disable I2S peripheral */
bogdanm 0:9b334a45a8ff 1053 __HAL_I2S_DISABLE(hi2s);
bogdanm 0:9b334a45a8ff 1054
bogdanm 0:9b334a45a8ff 1055 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1058 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 1059
bogdanm 0:9b334a45a8ff 1060 return HAL_OK;
bogdanm 0:9b334a45a8ff 1061 }
bogdanm 0:9b334a45a8ff 1062
bogdanm 0:9b334a45a8ff 1063 /**
bogdanm 0:9b334a45a8ff 1064 * @brief This function handles I2S interrupt request.
bogdanm 0:9b334a45a8ff 1065 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1066 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1067 * @retval None
bogdanm 0:9b334a45a8ff 1068 */
bogdanm 0:9b334a45a8ff 1069 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1070 {
bogdanm 0:9b334a45a8ff 1071 uint32_t i2ssr = hi2s->Instance->SR;
bogdanm 0:9b334a45a8ff 1072
bogdanm 0:9b334a45a8ff 1073 /* I2S in mode Receiver ------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1074 if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
bogdanm 0:9b334a45a8ff 1075 ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
bogdanm 0:9b334a45a8ff 1076 {
bogdanm 0:9b334a45a8ff 1077 I2S_Receive_IT(hi2s);
bogdanm 0:9b334a45a8ff 1078 return;
bogdanm 0:9b334a45a8ff 1079 }
bogdanm 0:9b334a45a8ff 1080
bogdanm 0:9b334a45a8ff 1081 /* I2S in mode Tramitter -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1082 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
bogdanm 0:9b334a45a8ff 1083 {
bogdanm 0:9b334a45a8ff 1084 I2S_Transmit_IT(hi2s);
bogdanm 0:9b334a45a8ff 1085 return;
bogdanm 0:9b334a45a8ff 1086 }
bogdanm 0:9b334a45a8ff 1087
bogdanm 0:9b334a45a8ff 1088 /* I2S interrupt error -------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1089 if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
bogdanm 0:9b334a45a8ff 1090 {
bogdanm 0:9b334a45a8ff 1091 /* I2S Overrun error interrupt occured ---------------------------------*/
bogdanm 0:9b334a45a8ff 1092 if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
bogdanm 0:9b334a45a8ff 1093 {
bogdanm 0:9b334a45a8ff 1094 /* Disable RXNE and ERR interrupt */
bogdanm 0:9b334a45a8ff 1095 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 1096
bogdanm 0:9b334a45a8ff 1097 /* Set the error code and execute error callback*/
bogdanm 0:9b334a45a8ff 1098 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
bogdanm 0:9b334a45a8ff 1099 }
bogdanm 0:9b334a45a8ff 1100
bogdanm 0:9b334a45a8ff 1101 /* I2S Underrun error interrupt occured --------------------------------*/
bogdanm 0:9b334a45a8ff 1102 if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
bogdanm 0:9b334a45a8ff 1103 {
bogdanm 0:9b334a45a8ff 1104 /* Disable TXE and ERR interrupt */
bogdanm 0:9b334a45a8ff 1105 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 1106
bogdanm 0:9b334a45a8ff 1107 /* Set the error code and execute error callback*/
bogdanm 0:9b334a45a8ff 1108 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
bogdanm 0:9b334a45a8ff 1109 }
bogdanm 0:9b334a45a8ff 1110
bogdanm 0:9b334a45a8ff 1111 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 1112 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1113 /* Call the Error Callback */
bogdanm 0:9b334a45a8ff 1114 HAL_I2S_ErrorCallback(hi2s);
bogdanm 0:9b334a45a8ff 1115 }
bogdanm 0:9b334a45a8ff 1116 }
bogdanm 0:9b334a45a8ff 1117
bogdanm 0:9b334a45a8ff 1118 /**
bogdanm 0:9b334a45a8ff 1119 * @brief Tx Transfer Half completed callbacks
bogdanm 0:9b334a45a8ff 1120 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1121 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1122 * @retval None
bogdanm 0:9b334a45a8ff 1123 */
bogdanm 0:9b334a45a8ff 1124 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1125 {
mbed_official 124:6a4a5b7d7324 1126 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 1127 UNUSED(hi2s);
bogdanm 0:9b334a45a8ff 1128 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1129 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1130 */
bogdanm 0:9b334a45a8ff 1131 }
bogdanm 0:9b334a45a8ff 1132
bogdanm 0:9b334a45a8ff 1133 /**
bogdanm 0:9b334a45a8ff 1134 * @brief Tx Transfer completed callbacks
bogdanm 0:9b334a45a8ff 1135 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1136 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1137 * @retval None
bogdanm 0:9b334a45a8ff 1138 */
bogdanm 0:9b334a45a8ff 1139 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1140 {
mbed_official 124:6a4a5b7d7324 1141 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 1142 UNUSED(hi2s);
bogdanm 0:9b334a45a8ff 1143 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1144 the HAL_I2S_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1145 */
bogdanm 0:9b334a45a8ff 1146 }
bogdanm 0:9b334a45a8ff 1147
bogdanm 0:9b334a45a8ff 1148 /**
bogdanm 0:9b334a45a8ff 1149 * @brief Rx Transfer half completed callbacks
bogdanm 0:9b334a45a8ff 1150 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1151 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1152 * @retval None
bogdanm 0:9b334a45a8ff 1153 */
bogdanm 0:9b334a45a8ff 1154 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1155 {
mbed_official 124:6a4a5b7d7324 1156 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 1157 UNUSED(hi2s);
bogdanm 0:9b334a45a8ff 1158 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1159 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1160 */
bogdanm 0:9b334a45a8ff 1161 }
bogdanm 0:9b334a45a8ff 1162
bogdanm 0:9b334a45a8ff 1163 /**
bogdanm 0:9b334a45a8ff 1164 * @brief Rx Transfer completed callbacks
bogdanm 0:9b334a45a8ff 1165 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1166 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1167 * @retval None
bogdanm 0:9b334a45a8ff 1168 */
bogdanm 0:9b334a45a8ff 1169 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1170 {
mbed_official 124:6a4a5b7d7324 1171 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 1172 UNUSED(hi2s);
bogdanm 0:9b334a45a8ff 1173 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1174 the HAL_I2S_RxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1175 */
bogdanm 0:9b334a45a8ff 1176 }
bogdanm 0:9b334a45a8ff 1177
bogdanm 0:9b334a45a8ff 1178 /**
bogdanm 0:9b334a45a8ff 1179 * @brief I2S error callbacks
bogdanm 0:9b334a45a8ff 1180 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1181 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1182 * @retval None
bogdanm 0:9b334a45a8ff 1183 */
bogdanm 0:9b334a45a8ff 1184 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1185 {
mbed_official 124:6a4a5b7d7324 1186 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 1187 UNUSED(hi2s);
bogdanm 0:9b334a45a8ff 1188 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1189 the HAL_I2S_ErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1190 */
bogdanm 0:9b334a45a8ff 1191 }
bogdanm 0:9b334a45a8ff 1192
bogdanm 0:9b334a45a8ff 1193 /**
bogdanm 0:9b334a45a8ff 1194 * @}
bogdanm 0:9b334a45a8ff 1195 */
bogdanm 0:9b334a45a8ff 1196
bogdanm 0:9b334a45a8ff 1197 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 1198 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 1199 *
bogdanm 0:9b334a45a8ff 1200 @verbatim
bogdanm 0:9b334a45a8ff 1201 ===============================================================================
bogdanm 0:9b334a45a8ff 1202 ##### Peripheral State and Errors functions #####
bogdanm 0:9b334a45a8ff 1203 ===============================================================================
bogdanm 0:9b334a45a8ff 1204 [..]
bogdanm 0:9b334a45a8ff 1205 This subsection permits to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 1206 and the data flow.
bogdanm 0:9b334a45a8ff 1207
bogdanm 0:9b334a45a8ff 1208 @endverbatim
bogdanm 0:9b334a45a8ff 1209 * @{
bogdanm 0:9b334a45a8ff 1210 */
bogdanm 0:9b334a45a8ff 1211
bogdanm 0:9b334a45a8ff 1212 /**
bogdanm 0:9b334a45a8ff 1213 * @brief Return the I2S state
bogdanm 0:9b334a45a8ff 1214 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1215 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1216 * @retval HAL state
bogdanm 0:9b334a45a8ff 1217 */
bogdanm 0:9b334a45a8ff 1218 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1219 {
bogdanm 0:9b334a45a8ff 1220 return hi2s->State;
bogdanm 0:9b334a45a8ff 1221 }
bogdanm 0:9b334a45a8ff 1222
bogdanm 0:9b334a45a8ff 1223 /**
bogdanm 0:9b334a45a8ff 1224 * @brief Return the I2S error code
bogdanm 0:9b334a45a8ff 1225 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1226 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1227 * @retval I2S Error Code
bogdanm 0:9b334a45a8ff 1228 */
bogdanm 0:9b334a45a8ff 1229 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1230 {
bogdanm 0:9b334a45a8ff 1231 return hi2s->ErrorCode;
bogdanm 0:9b334a45a8ff 1232 }
bogdanm 0:9b334a45a8ff 1233 /**
bogdanm 0:9b334a45a8ff 1234 * @}
bogdanm 0:9b334a45a8ff 1235 */
bogdanm 0:9b334a45a8ff 1236
bogdanm 0:9b334a45a8ff 1237 /**
bogdanm 0:9b334a45a8ff 1238 * @}
bogdanm 0:9b334a45a8ff 1239 */
bogdanm 0:9b334a45a8ff 1240
bogdanm 0:9b334a45a8ff 1241 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1242 /** @addtogroup I2S_Private_Functions I2S Private Functions
bogdanm 0:9b334a45a8ff 1243 * @{
bogdanm 0:9b334a45a8ff 1244 */
bogdanm 0:9b334a45a8ff 1245 /**
bogdanm 0:9b334a45a8ff 1246 * @brief DMA I2S transmit process complete callback
bogdanm 0:9b334a45a8ff 1247 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1248 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1249 * @retval None
bogdanm 0:9b334a45a8ff 1250 */
bogdanm 0:9b334a45a8ff 1251 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1252 {
bogdanm 0:9b334a45a8ff 1253 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1254
bogdanm 0:9b334a45a8ff 1255 if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
bogdanm 0:9b334a45a8ff 1256 {
bogdanm 0:9b334a45a8ff 1257 /* Disable Tx DMA Request */
bogdanm 0:9b334a45a8ff 1258 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 1259
bogdanm 0:9b334a45a8ff 1260 hi2s->TxXferCount = 0;
bogdanm 0:9b334a45a8ff 1261 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1262 }
bogdanm 0:9b334a45a8ff 1263 HAL_I2S_TxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1264 }
bogdanm 0:9b334a45a8ff 1265
bogdanm 0:9b334a45a8ff 1266 /**
bogdanm 0:9b334a45a8ff 1267 * @brief DMA I2S transmit process half complete callback
bogdanm 0:9b334a45a8ff 1268 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1269 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1270 * @retval None
bogdanm 0:9b334a45a8ff 1271 */
bogdanm 0:9b334a45a8ff 1272 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1273 {
bogdanm 0:9b334a45a8ff 1274 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1275
bogdanm 0:9b334a45a8ff 1276 HAL_I2S_TxHalfCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1277 }
bogdanm 0:9b334a45a8ff 1278
bogdanm 0:9b334a45a8ff 1279 /**
bogdanm 0:9b334a45a8ff 1280 * @brief DMA I2S receive process complete callback
bogdanm 0:9b334a45a8ff 1281 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1282 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1283 * @retval None
bogdanm 0:9b334a45a8ff 1284 */
bogdanm 0:9b334a45a8ff 1285 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1286 {
bogdanm 0:9b334a45a8ff 1287 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1288
bogdanm 0:9b334a45a8ff 1289 if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
bogdanm 0:9b334a45a8ff 1290 {
bogdanm 0:9b334a45a8ff 1291 /* Disable Rx DMA Request */
bogdanm 0:9b334a45a8ff 1292 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 1293 hi2s->RxXferCount = 0;
bogdanm 0:9b334a45a8ff 1294 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1295 }
bogdanm 0:9b334a45a8ff 1296 HAL_I2S_RxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1297 }
bogdanm 0:9b334a45a8ff 1298
bogdanm 0:9b334a45a8ff 1299 /**
bogdanm 0:9b334a45a8ff 1300 * @brief DMA I2S receive process half complete callback
bogdanm 0:9b334a45a8ff 1301 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1302 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1303 * @retval None
bogdanm 0:9b334a45a8ff 1304 */
bogdanm 0:9b334a45a8ff 1305 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1306 {
bogdanm 0:9b334a45a8ff 1307 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1308
bogdanm 0:9b334a45a8ff 1309 HAL_I2S_RxHalfCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1310 }
bogdanm 0:9b334a45a8ff 1311
bogdanm 0:9b334a45a8ff 1312 /**
bogdanm 0:9b334a45a8ff 1313 * @brief DMA I2S communication error callback
bogdanm 0:9b334a45a8ff 1314 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1315 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1316 * @retval None
bogdanm 0:9b334a45a8ff 1317 */
bogdanm 0:9b334a45a8ff 1318 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1319 {
bogdanm 0:9b334a45a8ff 1320 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1321
bogdanm 0:9b334a45a8ff 1322 /* Disable Rx and Tx DMA Request */
bogdanm 0:9b334a45a8ff 1323 CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
bogdanm 0:9b334a45a8ff 1324 hi2s->TxXferCount = 0;
bogdanm 0:9b334a45a8ff 1325 hi2s->RxXferCount = 0;
bogdanm 0:9b334a45a8ff 1326
bogdanm 0:9b334a45a8ff 1327 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1328
bogdanm 0:9b334a45a8ff 1329 /* Set the error code and execute error callback*/
bogdanm 0:9b334a45a8ff 1330 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
bogdanm 0:9b334a45a8ff 1331 HAL_I2S_ErrorCallback(hi2s);
bogdanm 0:9b334a45a8ff 1332 }
bogdanm 0:9b334a45a8ff 1333
bogdanm 0:9b334a45a8ff 1334 /**
bogdanm 0:9b334a45a8ff 1335 * @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 1336 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1337 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1338 * @retval None
bogdanm 0:9b334a45a8ff 1339 */
bogdanm 0:9b334a45a8ff 1340 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1341 {
bogdanm 0:9b334a45a8ff 1342 /* Transmit data */
bogdanm 0:9b334a45a8ff 1343 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm 0:9b334a45a8ff 1344 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 1345
bogdanm 0:9b334a45a8ff 1346 if(hi2s->TxXferCount == 0)
bogdanm 0:9b334a45a8ff 1347 {
bogdanm 0:9b334a45a8ff 1348 /* Disable TXE and ERR interrupt */
bogdanm 0:9b334a45a8ff 1349 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 1350
bogdanm 0:9b334a45a8ff 1351 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1352 HAL_I2S_TxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1353 }
bogdanm 0:9b334a45a8ff 1354 }
bogdanm 0:9b334a45a8ff 1355
bogdanm 0:9b334a45a8ff 1356 /**
bogdanm 0:9b334a45a8ff 1357 * @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 1358 * @param hi2s: I2S handle
bogdanm 0:9b334a45a8ff 1359 * @retval None
bogdanm 0:9b334a45a8ff 1360 */
bogdanm 0:9b334a45a8ff 1361 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1362 {
bogdanm 0:9b334a45a8ff 1363 /* Receive data */
bogdanm 0:9b334a45a8ff 1364 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm 0:9b334a45a8ff 1365 hi2s->RxXferCount--;
bogdanm 0:9b334a45a8ff 1366
bogdanm 0:9b334a45a8ff 1367 if(hi2s->RxXferCount == 0)
bogdanm 0:9b334a45a8ff 1368 {
bogdanm 0:9b334a45a8ff 1369 /* Disable RXNE and ERR interrupt */
bogdanm 0:9b334a45a8ff 1370 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 1371
bogdanm 0:9b334a45a8ff 1372 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1373 HAL_I2S_RxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1374 }
bogdanm 0:9b334a45a8ff 1375 }
bogdanm 0:9b334a45a8ff 1376
bogdanm 0:9b334a45a8ff 1377
bogdanm 0:9b334a45a8ff 1378 /**
bogdanm 0:9b334a45a8ff 1379 * @brief This function handles I2S Communication Timeout.
bogdanm 0:9b334a45a8ff 1380 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1381 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1382 * @param Flag: Flag checked
bogdanm 0:9b334a45a8ff 1383 * @param Status: Value of the flag expected
bogdanm 0:9b334a45a8ff 1384 * @param Timeout: Duration of the timeout
bogdanm 0:9b334a45a8ff 1385 * @retval HAL status
bogdanm 0:9b334a45a8ff 1386 */
bogdanm 0:9b334a45a8ff 1387 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 1388 {
bogdanm 0:9b334a45a8ff 1389 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1390
bogdanm 0:9b334a45a8ff 1391 /* Get tick */
bogdanm 0:9b334a45a8ff 1392 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1393
bogdanm 0:9b334a45a8ff 1394 /* Wait until flag is set */
bogdanm 0:9b334a45a8ff 1395 if(Status == RESET)
bogdanm 0:9b334a45a8ff 1396 {
bogdanm 0:9b334a45a8ff 1397 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
bogdanm 0:9b334a45a8ff 1398 {
bogdanm 0:9b334a45a8ff 1399 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 1400 {
bogdanm 0:9b334a45a8ff 1401 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 1402 {
bogdanm 0:9b334a45a8ff 1403 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 1404 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1405
bogdanm 0:9b334a45a8ff 1406 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1407 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 1408
bogdanm 0:9b334a45a8ff 1409 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1410 }
bogdanm 0:9b334a45a8ff 1411 }
bogdanm 0:9b334a45a8ff 1412 }
bogdanm 0:9b334a45a8ff 1413 }
bogdanm 0:9b334a45a8ff 1414 else
bogdanm 0:9b334a45a8ff 1415 {
bogdanm 0:9b334a45a8ff 1416 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
bogdanm 0:9b334a45a8ff 1417 {
bogdanm 0:9b334a45a8ff 1418 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 1419 {
bogdanm 0:9b334a45a8ff 1420 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 1421 {
bogdanm 0:9b334a45a8ff 1422 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 1423 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1424
bogdanm 0:9b334a45a8ff 1425 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1426 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 1427
bogdanm 0:9b334a45a8ff 1428 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1429 }
bogdanm 0:9b334a45a8ff 1430 }
bogdanm 0:9b334a45a8ff 1431 }
bogdanm 0:9b334a45a8ff 1432 }
bogdanm 0:9b334a45a8ff 1433 return HAL_OK;
bogdanm 0:9b334a45a8ff 1434 }
bogdanm 0:9b334a45a8ff 1435
bogdanm 0:9b334a45a8ff 1436 /**
bogdanm 0:9b334a45a8ff 1437 * @}
bogdanm 0:9b334a45a8ff 1438 */
bogdanm 0:9b334a45a8ff 1439
bogdanm 0:9b334a45a8ff 1440 /**
bogdanm 0:9b334a45a8ff 1441 * @}
bogdanm 0:9b334a45a8ff 1442 */
bogdanm 0:9b334a45a8ff 1443
bogdanm 0:9b334a45a8ff 1444 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1445 #endif /* HAL_I2S_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1446
bogdanm 0:9b334a45a8ff 1447
bogdanm 0:9b334a45a8ff 1448 /**
bogdanm 0:9b334a45a8ff 1449 * @}
bogdanm 0:9b334a45a8ff 1450 */
bogdanm 0:9b334a45a8ff 1451
bogdanm 0:9b334a45a8ff 1452 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/