en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
124:6a4a5b7d7324 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_dma.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 124:6a4a5b7d7324 5 * @version V1.0.4
mbed_official 124:6a4a5b7d7324 6 * @date 29-April-2016
bogdanm 0:9b334a45a8ff 7 * @brief Header file of DMA HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
mbed_official 124:6a4a5b7d7324 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F1xx_HAL_DMA_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F1xx_HAL_DMA_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f1xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup DMA
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
mbed_official 124:6a4a5b7d7324 57 /* Exported types ------------------------------------------------------------*/
mbed_official 124:6a4a5b7d7324 58
bogdanm 0:9b334a45a8ff 59 /** @defgroup DMA_Exported_Types DMA Exported Types
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
mbed_official 124:6a4a5b7d7324 62
bogdanm 0:9b334a45a8ff 63 /**
mbed_official 124:6a4a5b7d7324 64 * @brief DMA Configuration Structure definition
bogdanm 0:9b334a45a8ff 65 */
bogdanm 0:9b334a45a8ff 66 typedef struct
bogdanm 0:9b334a45a8ff 67 {
bogdanm 0:9b334a45a8ff 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 0:9b334a45a8ff 69 from memory to memory or from peripheral to memory.
bogdanm 0:9b334a45a8ff 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 0:9b334a45a8ff 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 0:9b334a45a8ff 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 0:9b334a45a8ff 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 0:9b334a45a8ff 82 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 0:9b334a45a8ff 85 This parameter can be a value of @ref DMA_mode
bogdanm 0:9b334a45a8ff 86 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 0:9b334a45a8ff 87 data transfer is configured on the selected Channel */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 0:9b334a45a8ff 90 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 0:9b334a45a8ff 91 } DMA_InitTypeDef;
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /**
mbed_official 124:6a4a5b7d7324 94 * @brief DMA Configuration enumeration values definition
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96 typedef enum
bogdanm 0:9b334a45a8ff 97 {
bogdanm 0:9b334a45a8ff 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 0:9b334a45a8ff 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 } DMA_ControlTypeDef;
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /**
bogdanm 0:9b334a45a8ff 104 * @brief HAL DMA State structures definition
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106 typedef enum
bogdanm 0:9b334a45a8ff 107 {
mbed_official 124:6a4a5b7d7324 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
mbed_official 124:6a4a5b7d7324 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
bogdanm 0:9b334a45a8ff 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
mbed_official 124:6a4a5b7d7324 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
mbed_official 124:6a4a5b7d7324 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 0:9b334a45a8ff 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 0:9b334a45a8ff 114 }HAL_DMA_StateTypeDef;
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /**
mbed_official 124:6a4a5b7d7324 117 * @brief HAL DMA Error Code structure definition
mbed_official 124:6a4a5b7d7324 118 */
bogdanm 0:9b334a45a8ff 119 typedef enum
bogdanm 0:9b334a45a8ff 120 {
bogdanm 0:9b334a45a8ff 121 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 0:9b334a45a8ff 122 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
mbed_official 124:6a4a5b7d7324 123 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /**
mbed_official 124:6a4a5b7d7324 126 * @brief DMA handle Structure definition
mbed_official 124:6a4a5b7d7324 127 */
bogdanm 0:9b334a45a8ff 128 typedef struct __DMA_HandleTypeDef
mbed_official 124:6a4a5b7d7324 129 {
mbed_official 124:6a4a5b7d7324 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 0:9b334a45a8ff 131
mbed_official 124:6a4a5b7d7324 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 0:9b334a45a8ff 133
mbed_official 124:6a4a5b7d7324 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 0:9b334a45a8ff 135
mbed_official 124:6a4a5b7d7324 136 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 void *Parent; /*!< Parent object state */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 0:9b334a45a8ff 147 } DMA_HandleTypeDef;
bogdanm 0:9b334a45a8ff 148 /**
bogdanm 0:9b334a45a8ff 149 * @}
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /* Exported constants --------------------------------------------------------*/
mbed_official 124:6a4a5b7d7324 153
bogdanm 0:9b334a45a8ff 154 /** @defgroup DMA_Exported_Constants DMA Exported Constants
bogdanm 0:9b334a45a8ff 155 * @{
bogdanm 0:9b334a45a8ff 156 */
bogdanm 0:9b334a45a8ff 157
mbed_official 124:6a4a5b7d7324 158 /** @defgroup DMA_Error_Code DMA Error Code
bogdanm 0:9b334a45a8ff 159 * @{
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
bogdanm 0:9b334a45a8ff 162 #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
bogdanm 0:9b334a45a8ff 163 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /**
bogdanm 0:9b334a45a8ff 166 * @}
bogdanm 0:9b334a45a8ff 167 */
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
bogdanm 0:9b334a45a8ff 170 * @{
bogdanm 0:9b334a45a8ff 171 */
mbed_official 124:6a4a5b7d7324 172 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
mbed_official 124:6a4a5b7d7324 173 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
mbed_official 124:6a4a5b7d7324 174 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /**
bogdanm 0:9b334a45a8ff 177 * @}
bogdanm 0:9b334a45a8ff 178 */
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
bogdanm 0:9b334a45a8ff 181 * @{
bogdanm 0:9b334a45a8ff 182 */
mbed_official 124:6a4a5b7d7324 183 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
mbed_official 124:6a4a5b7d7324 184 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 0:9b334a45a8ff 185 /**
bogdanm 0:9b334a45a8ff 186 * @}
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
bogdanm 0:9b334a45a8ff 190 * @{
bogdanm 0:9b334a45a8ff 191 */
mbed_official 124:6a4a5b7d7324 192 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
mbed_official 124:6a4a5b7d7324 193 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 0:9b334a45a8ff 194 /**
bogdanm 0:9b334a45a8ff 195 * @}
bogdanm 0:9b334a45a8ff 196 */
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
bogdanm 0:9b334a45a8ff 199 * @{
bogdanm 0:9b334a45a8ff 200 */
mbed_official 124:6a4a5b7d7324 201 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
mbed_official 124:6a4a5b7d7324 202 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
mbed_official 124:6a4a5b7d7324 203 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
bogdanm 0:9b334a45a8ff 204 /**
bogdanm 0:9b334a45a8ff 205 * @}
bogdanm 0:9b334a45a8ff 206 */
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /** @defgroup DMA_Memory_data_size DMA Memory data size
bogdanm 0:9b334a45a8ff 209 * @{
bogdanm 0:9b334a45a8ff 210 */
mbed_official 124:6a4a5b7d7324 211 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
mbed_official 124:6a4a5b7d7324 212 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
mbed_official 124:6a4a5b7d7324 213 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
bogdanm 0:9b334a45a8ff 214 /**
bogdanm 0:9b334a45a8ff 215 * @}
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /** @defgroup DMA_mode DMA mode
bogdanm 0:9b334a45a8ff 219 * @{
bogdanm 0:9b334a45a8ff 220 */
mbed_official 124:6a4a5b7d7324 221 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
mbed_official 124:6a4a5b7d7324 222 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
bogdanm 0:9b334a45a8ff 223 /**
bogdanm 0:9b334a45a8ff 224 * @}
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /** @defgroup DMA_Priority_level DMA Priority level
bogdanm 0:9b334a45a8ff 228 * @{
bogdanm 0:9b334a45a8ff 229 */
mbed_official 124:6a4a5b7d7324 230 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
mbed_official 124:6a4a5b7d7324 231 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
mbed_official 124:6a4a5b7d7324 232 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
mbed_official 124:6a4a5b7d7324 233 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 0:9b334a45a8ff 234 /**
bogdanm 0:9b334a45a8ff 235 * @}
bogdanm 0:9b334a45a8ff 236 */
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
bogdanm 0:9b334a45a8ff 240 * @{
bogdanm 0:9b334a45a8ff 241 */
bogdanm 0:9b334a45a8ff 242 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 0:9b334a45a8ff 243 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 0:9b334a45a8ff 244 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 0:9b334a45a8ff 245 /**
bogdanm 0:9b334a45a8ff 246 * @}
bogdanm 0:9b334a45a8ff 247 */
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /** @defgroup DMA_flag_definitions DMA flag definitions
bogdanm 0:9b334a45a8ff 250 * @{
bogdanm 0:9b334a45a8ff 251 */
bogdanm 0:9b334a45a8ff 252 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 253 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 254 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 255 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 256 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 257 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 258 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 259 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 260 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 261 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 262 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 263 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 264 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 265 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 266 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 267 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 268 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 269 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 270 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 271 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 272 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 273 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 274 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 275 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 276 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 277 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 278 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 279 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 280 /**
bogdanm 0:9b334a45a8ff 281 * @}
bogdanm 0:9b334a45a8ff 282 */
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /**
bogdanm 0:9b334a45a8ff 285 * @}
bogdanm 0:9b334a45a8ff 286 */
mbed_official 124:6a4a5b7d7324 287
bogdanm 0:9b334a45a8ff 288
mbed_official 124:6a4a5b7d7324 289 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 290 /** @defgroup DMA_Exported_Macros DMA Exported Macros
bogdanm 0:9b334a45a8ff 291 * @{
bogdanm 0:9b334a45a8ff 292 */
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /** @brief Reset DMA handle state
bogdanm 0:9b334a45a8ff 295 * @param __HANDLE__: DMA handle.
bogdanm 0:9b334a45a8ff 296 * @retval None
bogdanm 0:9b334a45a8ff 297 */
bogdanm 0:9b334a45a8ff 298 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 /**
bogdanm 0:9b334a45a8ff 301 * @brief Enable the specified DMA Channel.
bogdanm 0:9b334a45a8ff 302 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 303 * @retval None.
bogdanm 0:9b334a45a8ff 304 */
bogdanm 0:9b334a45a8ff 305 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 /**
bogdanm 0:9b334a45a8ff 308 * @brief Disable the specified DMA Channel.
bogdanm 0:9b334a45a8ff 309 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 310 * @retval None.
bogdanm 0:9b334a45a8ff 311 */
bogdanm 0:9b334a45a8ff 312 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 /* Interrupt & Flag management */
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /**
bogdanm 0:9b334a45a8ff 318 * @brief Enables the specified DMA Channel interrupts.
bogdanm 0:9b334a45a8ff 319 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 320 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 321 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 322 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 323 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 324 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 325 * @retval None
bogdanm 0:9b334a45a8ff 326 */
bogdanm 0:9b334a45a8ff 327 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /**
bogdanm 0:9b334a45a8ff 330 * @brief Disables the specified DMA Channel interrupts.
bogdanm 0:9b334a45a8ff 331 * @param __HANDLE__: DMA handle
mbed_official 124:6a4a5b7d7324 332 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 333 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 334 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 335 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 336 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 337 * @retval None
bogdanm 0:9b334a45a8ff 338 */
bogdanm 0:9b334a45a8ff 339 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 /**
mbed_official 124:6a4a5b7d7324 342 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
bogdanm 0:9b334a45a8ff 343 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 344 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 0:9b334a45a8ff 345 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 346 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 347 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 348 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 349 * @retval The state of DMA_IT (SET or RESET).
bogdanm 0:9b334a45a8ff 350 */
bogdanm 0:9b334a45a8ff 351 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 /**
mbed_official 124:6a4a5b7d7324 354 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
mbed_official 124:6a4a5b7d7324 355 * @param __HANDLE__: DMA handle
mbed_official 124:6a4a5b7d7324 356 *
mbed_official 124:6a4a5b7d7324 357 * @retval The number of remaining data units in the current DMA Channel transfer.
mbed_official 124:6a4a5b7d7324 358 */
mbed_official 124:6a4a5b7d7324 359 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
mbed_official 124:6a4a5b7d7324 360
mbed_official 124:6a4a5b7d7324 361 /**
bogdanm 0:9b334a45a8ff 362 * @}
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /* Include DMA HAL Extension module */
bogdanm 0:9b334a45a8ff 366 #include "stm32f1xx_hal_dma_ex.h"
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 369 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
bogdanm 0:9b334a45a8ff 370 * @{
bogdanm 0:9b334a45a8ff 371 */
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 374 * @{
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376 /* Initialization and de-initialization functions *****************************/
bogdanm 0:9b334a45a8ff 377 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 378 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 379 /**
bogdanm 0:9b334a45a8ff 380 * @}
bogdanm 0:9b334a45a8ff 381 */
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
bogdanm 0:9b334a45a8ff 384 * @{
bogdanm 0:9b334a45a8ff 385 */
bogdanm 0:9b334a45a8ff 386 /* IO operation functions *****************************************************/
bogdanm 0:9b334a45a8ff 387 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 388 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 389 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 390 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
mbed_official 124:6a4a5b7d7324 391 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 392 /**
bogdanm 0:9b334a45a8ff 393 * @}
bogdanm 0:9b334a45a8ff 394 */
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
bogdanm 0:9b334a45a8ff 397 * @{
bogdanm 0:9b334a45a8ff 398 */
bogdanm 0:9b334a45a8ff 399 /* Peripheral State and Error functions ***************************************/
bogdanm 0:9b334a45a8ff 400 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 401 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 402 /**
bogdanm 0:9b334a45a8ff 403 * @}
bogdanm 0:9b334a45a8ff 404 */
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /**
bogdanm 0:9b334a45a8ff 407 * @}
bogdanm 0:9b334a45a8ff 408 */
bogdanm 0:9b334a45a8ff 409
mbed_official 124:6a4a5b7d7324 410 /* Private Constants -------------------------------------------------------------*/
mbed_official 124:6a4a5b7d7324 411 /** @defgroup DMA_Private_Constants DMA Private Constants
mbed_official 124:6a4a5b7d7324 412 * @brief DMA private defines and constants
mbed_official 124:6a4a5b7d7324 413 * @{
mbed_official 124:6a4a5b7d7324 414 */
mbed_official 124:6a4a5b7d7324 415 /**
mbed_official 124:6a4a5b7d7324 416 * @}
mbed_official 124:6a4a5b7d7324 417 */
mbed_official 124:6a4a5b7d7324 418
mbed_official 124:6a4a5b7d7324 419 /* Private macros ------------------------------------------------------------*/
mbed_official 124:6a4a5b7d7324 420 /** @defgroup DMA_Private_Macros DMA Private Macros
mbed_official 124:6a4a5b7d7324 421 * @brief DMA private macros
mbed_official 124:6a4a5b7d7324 422 * @{
mbed_official 124:6a4a5b7d7324 423 */
mbed_official 124:6a4a5b7d7324 424
mbed_official 124:6a4a5b7d7324 425 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
mbed_official 124:6a4a5b7d7324 426
mbed_official 124:6a4a5b7d7324 427 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
mbed_official 124:6a4a5b7d7324 428 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
mbed_official 124:6a4a5b7d7324 429 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
mbed_official 124:6a4a5b7d7324 430
mbed_official 124:6a4a5b7d7324 431 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
mbed_official 124:6a4a5b7d7324 432 ((STATE) == DMA_PINC_DISABLE))
mbed_official 124:6a4a5b7d7324 433
mbed_official 124:6a4a5b7d7324 434 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
mbed_official 124:6a4a5b7d7324 435 ((STATE) == DMA_MINC_DISABLE))
mbed_official 124:6a4a5b7d7324 436
mbed_official 124:6a4a5b7d7324 437 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
mbed_official 124:6a4a5b7d7324 438 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
mbed_official 124:6a4a5b7d7324 439 ((SIZE) == DMA_PDATAALIGN_WORD))
mbed_official 124:6a4a5b7d7324 440
mbed_official 124:6a4a5b7d7324 441 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
mbed_official 124:6a4a5b7d7324 442 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
mbed_official 124:6a4a5b7d7324 443 ((SIZE) == DMA_MDATAALIGN_WORD ))
mbed_official 124:6a4a5b7d7324 444
mbed_official 124:6a4a5b7d7324 445 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
mbed_official 124:6a4a5b7d7324 446 ((MODE) == DMA_CIRCULAR))
mbed_official 124:6a4a5b7d7324 447
mbed_official 124:6a4a5b7d7324 448 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
mbed_official 124:6a4a5b7d7324 449 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
mbed_official 124:6a4a5b7d7324 450 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
mbed_official 124:6a4a5b7d7324 451 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
mbed_official 124:6a4a5b7d7324 452
mbed_official 124:6a4a5b7d7324 453 /**
mbed_official 124:6a4a5b7d7324 454 * @}
mbed_official 124:6a4a5b7d7324 455 */
mbed_official 124:6a4a5b7d7324 456
mbed_official 124:6a4a5b7d7324 457 /* Private functions ---------------------------------------------------------*/
mbed_official 124:6a4a5b7d7324 458 /** @defgroup DMA_Private_Functions DMA Private Functions
mbed_official 124:6a4a5b7d7324 459 * @brief DMA private functions
mbed_official 124:6a4a5b7d7324 460 * @{
mbed_official 124:6a4a5b7d7324 461 */
mbed_official 124:6a4a5b7d7324 462 /**
mbed_official 124:6a4a5b7d7324 463 * @}
mbed_official 124:6a4a5b7d7324 464 */
mbed_official 124:6a4a5b7d7324 465
bogdanm 0:9b334a45a8ff 466 /**
bogdanm 0:9b334a45a8ff 467 * @}
bogdanm 0:9b334a45a8ff 468 */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /**
bogdanm 0:9b334a45a8ff 471 * @}
bogdanm 0:9b334a45a8ff 472 */
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 475 }
bogdanm 0:9b334a45a8ff 476 #endif
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 #endif /* __STM32F1xx_HAL_DMA_H */
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/