en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
124:6a4a5b7d7324 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_dma.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 124:6a4a5b7d7324 5 * @version V1.0.4
mbed_official 124:6a4a5b7d7324 6 * @date 29-April-2016
bogdanm 0:9b334a45a8ff 7 * @brief DMA HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
mbed_official 124:6a4a5b7d7324 9 * This file provides firmware functions to manage the following
mbed_official 124:6a4a5b7d7324 10 * functionalities of the Direct Memory Access (DMA) peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + IO operation functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State and errors functions
bogdanm 0:9b334a45a8ff 14 @verbatim
bogdanm 0:9b334a45a8ff 15 ==============================================================================
bogdanm 0:9b334a45a8ff 16 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 17 ==============================================================================
bogdanm 0:9b334a45a8ff 18 [..]
bogdanm 0:9b334a45a8ff 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
bogdanm 0:9b334a45a8ff 20 (except for internal SRAM / FLASH memories: no initialization is
bogdanm 0:9b334a45a8ff 21 necessary) please refer to Reference manual for connection between peripherals
mbed_official 124:6a4a5b7d7324 22 and DMA requests.
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 (#) For a given Channel, program the required configuration through the following parameters:
bogdanm 0:9b334a45a8ff 25 Transfer Direction, Source and Destination data formats,
bogdanm 0:9b334a45a8ff 26 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
bogdanm 0:9b334a45a8ff 27 using HAL_DMA_Init() function.
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
bogdanm 0:9b334a45a8ff 30 detection.
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 (#) Use HAL_DMA_Abort() function to abort the current transfer
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
bogdanm 0:9b334a45a8ff 35 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 36 =================================
bogdanm 0:9b334a45a8ff 37 [..]
bogdanm 0:9b334a45a8ff 38 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
bogdanm 0:9b334a45a8ff 39 address and destination address and the Length of data to be transferred
bogdanm 0:9b334a45a8ff 40 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
bogdanm 0:9b334a45a8ff 41 case a fixed Timeout can be configured by User depending from his application.
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 44 ===================================
bogdanm 0:9b334a45a8ff 45 [..]
bogdanm 0:9b334a45a8ff 46 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
bogdanm 0:9b334a45a8ff 47 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
bogdanm 0:9b334a45a8ff 48 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
bogdanm 0:9b334a45a8ff 49 Source address and destination address and the Length of data to be transferred.
bogdanm 0:9b334a45a8ff 50 In this case the DMA interrupt is configured
bogdanm 0:9b334a45a8ff 51 (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
bogdanm 0:9b334a45a8ff 52 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
bogdanm 0:9b334a45a8ff 53 add his own function by customization of function pointer XferCpltCallback and
bogdanm 0:9b334a45a8ff 54 XferErrorCallback (i.e a member of DMA handle structure).
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 *** DMA HAL driver macros list ***
bogdanm 0:9b334a45a8ff 57 =============================================
bogdanm 0:9b334a45a8ff 58 [..]
bogdanm 0:9b334a45a8ff 59 Below the list of most used macros in DMA HAL driver.
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
bogdanm 0:9b334a45a8ff 62 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
bogdanm 0:9b334a45a8ff 63 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
bogdanm 0:9b334a45a8ff 64 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
bogdanm 0:9b334a45a8ff 65 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
bogdanm 0:9b334a45a8ff 66 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
bogdanm 0:9b334a45a8ff 67 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 [..]
bogdanm 0:9b334a45a8ff 70 (@) You can refer to the DMA HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 @endverbatim
bogdanm 0:9b334a45a8ff 73 ******************************************************************************
bogdanm 0:9b334a45a8ff 74 * @attention
bogdanm 0:9b334a45a8ff 75 *
mbed_official 124:6a4a5b7d7324 76 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 77 *
bogdanm 0:9b334a45a8ff 78 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 79 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 80 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 81 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 82 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 83 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 84 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 85 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 86 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 87 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 88 *
bogdanm 0:9b334a45a8ff 89 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 90 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 91 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 92 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 93 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 94 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 95 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 96 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 97 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 98 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 99 *
bogdanm 0:9b334a45a8ff 100 ******************************************************************************
bogdanm 0:9b334a45a8ff 101 */
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 104 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /** @defgroup DMA DMA
bogdanm 0:9b334a45a8ff 111 * @brief DMA HAL module driver
bogdanm 0:9b334a45a8ff 112 * @{
bogdanm 0:9b334a45a8ff 113 */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 #ifdef HAL_DMA_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 118 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 119 /** @defgroup DMA_Private_Constants DMA Private Constants
bogdanm 0:9b334a45a8ff 120 * @{
bogdanm 0:9b334a45a8ff 121 */
mbed_official 124:6a4a5b7d7324 122 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
bogdanm 0:9b334a45a8ff 123 /**
bogdanm 0:9b334a45a8ff 124 * @}
bogdanm 0:9b334a45a8ff 125 */
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 128 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 129 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 130 /** @defgroup DMA_Private_Functions DMA Private Functions
bogdanm 0:9b334a45a8ff 131 * @{
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 134 /**
bogdanm 0:9b334a45a8ff 135 * @}
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /** @defgroup DMA_Exported_Functions DMA Exported Functions
bogdanm 0:9b334a45a8ff 141 * @{
bogdanm 0:9b334a45a8ff 142 */
bogdanm 0:9b334a45a8ff 143
mbed_official 124:6a4a5b7d7324 144 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 145 * @brief Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 146 *
bogdanm 0:9b334a45a8ff 147 @verbatim
bogdanm 0:9b334a45a8ff 148 ===============================================================================
bogdanm 0:9b334a45a8ff 149 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 150 ===============================================================================
bogdanm 0:9b334a45a8ff 151 [..]
bogdanm 0:9b334a45a8ff 152 This section provides functions allowing to initialize the DMA Channel source
bogdanm 0:9b334a45a8ff 153 and destination addresses, incrementation and data sizes, transfer direction,
bogdanm 0:9b334a45a8ff 154 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
bogdanm 0:9b334a45a8ff 155 [..]
bogdanm 0:9b334a45a8ff 156 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
bogdanm 0:9b334a45a8ff 157 reference manual.
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 @endverbatim
bogdanm 0:9b334a45a8ff 160 * @{
bogdanm 0:9b334a45a8ff 161 */
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /**
bogdanm 0:9b334a45a8ff 164 * @brief Initializes the DMA according to the specified
bogdanm 0:9b334a45a8ff 165 * parameters in the DMA_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 166 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 167 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 168 * @retval HAL status
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 171 {
bogdanm 0:9b334a45a8ff 172 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /* Check the DMA handle allocation */
bogdanm 0:9b334a45a8ff 175 if(hdma == NULL)
bogdanm 0:9b334a45a8ff 176 {
bogdanm 0:9b334a45a8ff 177 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 178 }
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /* Check the parameters */
bogdanm 0:9b334a45a8ff 181 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
bogdanm 0:9b334a45a8ff 182 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
bogdanm 0:9b334a45a8ff 183 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
bogdanm 0:9b334a45a8ff 184 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
bogdanm 0:9b334a45a8ff 185 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
bogdanm 0:9b334a45a8ff 186 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
bogdanm 0:9b334a45a8ff 187 assert_param(IS_DMA_MODE(hdma->Init.Mode));
bogdanm 0:9b334a45a8ff 188 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
mbed_official 124:6a4a5b7d7324 189
bogdanm 0:9b334a45a8ff 190 if(hdma->State == HAL_DMA_STATE_RESET)
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 /* Allocate lock resource and initialize it */
mbed_official 124:6a4a5b7d7324 193 hdma->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 197 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /* Get the CR register value */
bogdanm 0:9b334a45a8ff 200 tmp = hdma->Instance->CCR;
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
bogdanm 0:9b334a45a8ff 203 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
bogdanm 0:9b334a45a8ff 204 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
bogdanm 0:9b334a45a8ff 205 DMA_CCR_DIR));
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* Prepare the DMA Channel configuration */
bogdanm 0:9b334a45a8ff 208 tmp |= hdma->Init.Direction |
bogdanm 0:9b334a45a8ff 209 hdma->Init.PeriphInc | hdma->Init.MemInc |
bogdanm 0:9b334a45a8ff 210 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
bogdanm 0:9b334a45a8ff 211 hdma->Init.Mode | hdma->Init.Priority;
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /* Write to DMA Channel CR register */
bogdanm 0:9b334a45a8ff 214 hdma->Instance->CCR = tmp;
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* Initialise the error code */
bogdanm 0:9b334a45a8ff 217 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /* Initialize the DMA state*/
mbed_official 124:6a4a5b7d7324 220 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 return HAL_OK;
mbed_official 124:6a4a5b7d7324 223 }
mbed_official 124:6a4a5b7d7324 224
bogdanm 0:9b334a45a8ff 225 /**
bogdanm 0:9b334a45a8ff 226 * @brief DeInitializes the DMA peripheral
bogdanm 0:9b334a45a8ff 227 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 228 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 229 * @retval HAL status
bogdanm 0:9b334a45a8ff 230 */
bogdanm 0:9b334a45a8ff 231 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 232 {
bogdanm 0:9b334a45a8ff 233 /* Check the DMA handle allocation */
bogdanm 0:9b334a45a8ff 234 if(hdma == NULL)
bogdanm 0:9b334a45a8ff 235 {
bogdanm 0:9b334a45a8ff 236 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /* Check the parameters */
bogdanm 0:9b334a45a8ff 240 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 243 if(hdma->State == HAL_DMA_STATE_BUSY)
bogdanm 0:9b334a45a8ff 244 {
bogdanm 0:9b334a45a8ff 245 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /* Disable the selected DMA Channelx */
bogdanm 0:9b334a45a8ff 249 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Reset DMA Channel control register */
bogdanm 0:9b334a45a8ff 252 hdma->Instance->CCR = 0;
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 /* Reset DMA Channel Number of Data to Transfer register */
bogdanm 0:9b334a45a8ff 255 hdma->Instance->CNDTR = 0;
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Reset DMA Channel peripheral address register */
bogdanm 0:9b334a45a8ff 258 hdma->Instance->CPAR = 0;
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /* Reset DMA Channel memory address register */
bogdanm 0:9b334a45a8ff 261 hdma->Instance->CMAR = 0;
bogdanm 0:9b334a45a8ff 262
bogdanm 0:9b334a45a8ff 263 /* Clear all flags */
bogdanm 0:9b334a45a8ff 264 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 265 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 266 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 267
mbed_official 124:6a4a5b7d7324 268 /* Initialize the error code */
bogdanm 0:9b334a45a8ff 269 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* Initialize the DMA state */
bogdanm 0:9b334a45a8ff 272 hdma->State = HAL_DMA_STATE_RESET;
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Release Lock */
bogdanm 0:9b334a45a8ff 275 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 return HAL_OK;
bogdanm 0:9b334a45a8ff 278 }
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /**
bogdanm 0:9b334a45a8ff 281 * @}
bogdanm 0:9b334a45a8ff 282 */
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
bogdanm 0:9b334a45a8ff 285 * @brief I/O operation functions
bogdanm 0:9b334a45a8ff 286 *
bogdanm 0:9b334a45a8ff 287 @verbatim
bogdanm 0:9b334a45a8ff 288 ===============================================================================
bogdanm 0:9b334a45a8ff 289 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 290 ===============================================================================
bogdanm 0:9b334a45a8ff 291 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 292 (+) Configure the source, destination address and data length and Start DMA transfer
bogdanm 0:9b334a45a8ff 293 (+) Configure the source, destination address and data length and
bogdanm 0:9b334a45a8ff 294 Start DMA transfer with interrupt
bogdanm 0:9b334a45a8ff 295 (+) Abort DMA transfer
bogdanm 0:9b334a45a8ff 296 (+) Poll for transfer complete
bogdanm 0:9b334a45a8ff 297 (+) Handle DMA interrupt request
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 @endverbatim
bogdanm 0:9b334a45a8ff 300 * @{
bogdanm 0:9b334a45a8ff 301 */
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /**
bogdanm 0:9b334a45a8ff 304 * @brief Starts the DMA Transfer.
bogdanm 0:9b334a45a8ff 305 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 306 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 307 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 308 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 309 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 310 * @retval HAL status
bogdanm 0:9b334a45a8ff 311 */
bogdanm 0:9b334a45a8ff 312 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
mbed_official 124:6a4a5b7d7324 313 {
bogdanm 0:9b334a45a8ff 314 /* Process locked */
mbed_official 124:6a4a5b7d7324 315 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 316
mbed_official 124:6a4a5b7d7324 317 /* Change DMA peripheral state */
mbed_official 124:6a4a5b7d7324 318 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /* Check the parameters */
bogdanm 0:9b334a45a8ff 321 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /* Disable the peripheral */
mbed_official 124:6a4a5b7d7324 324 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 327 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Enable the Peripheral */
mbed_official 124:6a4a5b7d7324 330 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 return HAL_OK;
mbed_official 124:6a4a5b7d7324 333 }
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /**
bogdanm 0:9b334a45a8ff 336 * @brief Start the DMA Transfer with interrupt enabled.
bogdanm 0:9b334a45a8ff 337 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 338 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 339 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 340 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 341 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 342 * @retval HAL status
bogdanm 0:9b334a45a8ff 343 */
bogdanm 0:9b334a45a8ff 344 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 345 {
bogdanm 0:9b334a45a8ff 346 /* Process locked */
bogdanm 0:9b334a45a8ff 347 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 348
mbed_official 124:6a4a5b7d7324 349 /* Change DMA peripheral state */
mbed_official 124:6a4a5b7d7324 350 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /* Check the parameters */
bogdanm 0:9b334a45a8ff 353 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 356 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 357
mbed_official 124:6a4a5b7d7324 358 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 359 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /* Enable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 362 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Enable the Half transfer complete interrupt */
bogdanm 0:9b334a45a8ff 365 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /* Enable the transfer Error interrupt */
bogdanm 0:9b334a45a8ff 368 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /* Enable the Peripheral */
mbed_official 124:6a4a5b7d7324 371 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 372
mbed_official 124:6a4a5b7d7324 373 return HAL_OK;
bogdanm 0:9b334a45a8ff 374 }
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /**
bogdanm 0:9b334a45a8ff 377 * @brief Aborts the DMA Transfer.
bogdanm 0:9b334a45a8ff 378 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 379 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 380 *
bogdanm 0:9b334a45a8ff 381 * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
bogdanm 0:9b334a45a8ff 382 * effectively disabled is added. If a Channel is disabled
bogdanm 0:9b334a45a8ff 383 * while a data transfer is ongoing, the current data will be transferred
bogdanm 0:9b334a45a8ff 384 * and the Channel will be effectively disabled only after the transfer of
bogdanm 0:9b334a45a8ff 385 * this single data is finished.
bogdanm 0:9b334a45a8ff 386 * @retval HAL status
bogdanm 0:9b334a45a8ff 387 */
bogdanm 0:9b334a45a8ff 388 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 389 {
bogdanm 0:9b334a45a8ff 390 uint32_t tickstart = 0x00;
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /* Disable the channel */
bogdanm 0:9b334a45a8ff 393 __HAL_DMA_DISABLE(hdma);
mbed_official 124:6a4a5b7d7324 394
mbed_official 124:6a4a5b7d7324 395 /* Get tick */
bogdanm 0:9b334a45a8ff 396 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* Check if the DMA Channel is effectively disabled */
mbed_official 124:6a4a5b7d7324 399 while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
bogdanm 0:9b334a45a8ff 400 {
bogdanm 0:9b334a45a8ff 401 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 402 if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
bogdanm 0:9b334a45a8ff 403 {
bogdanm 0:9b334a45a8ff 404 /* Update error code */
bogdanm 0:9b334a45a8ff 405 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 408 hdma->State = HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 411 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 414 }
bogdanm 0:9b334a45a8ff 415 }
mbed_official 124:6a4a5b7d7324 416 /* Change the DMA state */
mbed_official 124:6a4a5b7d7324 417 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 420 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 421
mbed_official 124:6a4a5b7d7324 422 return HAL_OK;
bogdanm 0:9b334a45a8ff 423 }
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /**
bogdanm 0:9b334a45a8ff 426 * @brief Polling for transfer complete.
bogdanm 0:9b334a45a8ff 427 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 428 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 429 * @param CompleteLevel: Specifies the DMA level complete.
bogdanm 0:9b334a45a8ff 430 * @param Timeout: Timeout duration.
bogdanm 0:9b334a45a8ff 431 * @retval HAL status
bogdanm 0:9b334a45a8ff 432 */
bogdanm 0:9b334a45a8ff 433 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 434 {
bogdanm 0:9b334a45a8ff 435 uint32_t temp;
bogdanm 0:9b334a45a8ff 436 uint32_t tickstart = 0x00;
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /* Get the level transfer complete flag */
bogdanm 0:9b334a45a8ff 439 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 440 {
bogdanm 0:9b334a45a8ff 441 /* Transfer Complete flag */
bogdanm 0:9b334a45a8ff 442 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
bogdanm 0:9b334a45a8ff 443 }
bogdanm 0:9b334a45a8ff 444 else
bogdanm 0:9b334a45a8ff 445 {
bogdanm 0:9b334a45a8ff 446 /* Half Transfer Complete flag */
bogdanm 0:9b334a45a8ff 447 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449
mbed_official 124:6a4a5b7d7324 450 /* Get tick */
bogdanm 0:9b334a45a8ff 451 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
bogdanm 0:9b334a45a8ff 454 {
bogdanm 0:9b334a45a8ff 455 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 /* Clear the transfer error flags */
bogdanm 0:9b334a45a8ff 458 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* Update error code */
bogdanm 0:9b334a45a8ff 461 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /* Change the DMA state */
mbed_official 124:6a4a5b7d7324 464 hdma->State= HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 467 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 468
mbed_official 124:6a4a5b7d7324 469 return HAL_ERROR;
mbed_official 124:6a4a5b7d7324 470 }
bogdanm 0:9b334a45a8ff 471 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 472 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 473 {
bogdanm 0:9b334a45a8ff 474 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
bogdanm 0:9b334a45a8ff 475 {
bogdanm 0:9b334a45a8ff 476 /* Update error code */
bogdanm 0:9b334a45a8ff 477 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 480 hdma->State = HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 483 __HAL_UNLOCK(hdma);
mbed_official 124:6a4a5b7d7324 484
bogdanm 0:9b334a45a8ff 485 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 486 }
bogdanm 0:9b334a45a8ff 487 }
bogdanm 0:9b334a45a8ff 488 }
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 491 {
bogdanm 0:9b334a45a8ff 492 /* Clear the transfer complete flag */
bogdanm 0:9b334a45a8ff 493 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* The selected Channelx EN bit is cleared (DMA is disabled and
bogdanm 0:9b334a45a8ff 496 all transfers are complete) */
bogdanm 0:9b334a45a8ff 497 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 }
bogdanm 0:9b334a45a8ff 500 else
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 /* Clear the half transfer complete flag */
bogdanm 0:9b334a45a8ff 503 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /* The selected Channelx EN bit is cleared (DMA is disabled and
bogdanm 0:9b334a45a8ff 506 all transfers of half buffer are complete) */
bogdanm 0:9b334a45a8ff 507 hdma->State = HAL_DMA_STATE_READY_HALF;
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* Process unlocked */
mbed_official 124:6a4a5b7d7324 511 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 return HAL_OK;
bogdanm 0:9b334a45a8ff 514 }
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /**
bogdanm 0:9b334a45a8ff 517 * @brief Handles DMA interrupt request.
bogdanm 0:9b334a45a8ff 518 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 519 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 520 * @retval None
bogdanm 0:9b334a45a8ff 521 */
bogdanm 0:9b334a45a8ff 522 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
mbed_official 124:6a4a5b7d7324 523 {
bogdanm 0:9b334a45a8ff 524 /* Transfer Error Interrupt management ***************************************/
bogdanm 0:9b334a45a8ff 525 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 526 {
bogdanm 0:9b334a45a8ff 527 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
bogdanm 0:9b334a45a8ff 528 {
bogdanm 0:9b334a45a8ff 529 /* Disable the transfer error interrupt */
bogdanm 0:9b334a45a8ff 530 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
mbed_official 124:6a4a5b7d7324 531
bogdanm 0:9b334a45a8ff 532 /* Clear the transfer error flag */
bogdanm 0:9b334a45a8ff 533 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
mbed_official 124:6a4a5b7d7324 534
bogdanm 0:9b334a45a8ff 535 /* Update error code */
bogdanm 0:9b334a45a8ff 536 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
mbed_official 124:6a4a5b7d7324 537
bogdanm 0:9b334a45a8ff 538 /* Change the DMA state */
mbed_official 124:6a4a5b7d7324 539 hdma->State = HAL_DMA_STATE_ERROR;
mbed_official 124:6a4a5b7d7324 540
bogdanm 0:9b334a45a8ff 541 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 542 __HAL_UNLOCK(hdma);
mbed_official 124:6a4a5b7d7324 543
bogdanm 0:9b334a45a8ff 544 if (hdma->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 545 {
bogdanm 0:9b334a45a8ff 546 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 547 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 548 }
bogdanm 0:9b334a45a8ff 549 }
bogdanm 0:9b334a45a8ff 550 }
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 /* Half Transfer Complete Interrupt management ******************************/
bogdanm 0:9b334a45a8ff 553 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
bogdanm 0:9b334a45a8ff 556 {
bogdanm 0:9b334a45a8ff 557 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
bogdanm 0:9b334a45a8ff 558 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 559 {
bogdanm 0:9b334a45a8ff 560 /* Disable the half transfer interrupt */
bogdanm 0:9b334a45a8ff 561 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 562 }
bogdanm 0:9b334a45a8ff 563 /* Clear the half transfer complete flag */
bogdanm 0:9b334a45a8ff 564 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 565
bogdanm 0:9b334a45a8ff 566 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 567 hdma->State = HAL_DMA_STATE_READY_HALF;
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 if(hdma->XferHalfCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 /* Half transfer callback */
bogdanm 0:9b334a45a8ff 572 hdma->XferHalfCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 573 }
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575 }
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /* Transfer Complete Interrupt management ***********************************/
bogdanm 0:9b334a45a8ff 578 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 579 {
bogdanm 0:9b334a45a8ff 580 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 583 {
bogdanm 0:9b334a45a8ff 584 /* Disable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 585 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 586 }
bogdanm 0:9b334a45a8ff 587 /* Clear the transfer complete flag */
bogdanm 0:9b334a45a8ff 588 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /* Update error code */
bogdanm 0:9b334a45a8ff 591 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 /* Change the DMA state */
mbed_official 124:6a4a5b7d7324 594 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 597 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 if(hdma->XferCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 600 {
bogdanm 0:9b334a45a8ff 601 /* Transfer complete callback */
bogdanm 0:9b334a45a8ff 602 hdma->XferCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 603 }
bogdanm 0:9b334a45a8ff 604 }
bogdanm 0:9b334a45a8ff 605 }
mbed_official 124:6a4a5b7d7324 606 }
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 /**
bogdanm 0:9b334a45a8ff 609 * @}
bogdanm 0:9b334a45a8ff 610 */
bogdanm 0:9b334a45a8ff 611
bogdanm 0:9b334a45a8ff 612 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
bogdanm 0:9b334a45a8ff 613 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 614 *
bogdanm 0:9b334a45a8ff 615 @verbatim
bogdanm 0:9b334a45a8ff 616 ===============================================================================
bogdanm 0:9b334a45a8ff 617 ##### State and Errors functions #####
mbed_official 124:6a4a5b7d7324 618 ===============================================================================
bogdanm 0:9b334a45a8ff 619 [..]
bogdanm 0:9b334a45a8ff 620 This subsection provides functions allowing to
bogdanm 0:9b334a45a8ff 621 (+) Check the DMA state
bogdanm 0:9b334a45a8ff 622 (+) Get error code
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624 @endverbatim
bogdanm 0:9b334a45a8ff 625 * @{
mbed_official 124:6a4a5b7d7324 626 */
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 /**
bogdanm 0:9b334a45a8ff 629 * @brief Returns the DMA state.
bogdanm 0:9b334a45a8ff 630 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 631 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 632 * @retval HAL state
bogdanm 0:9b334a45a8ff 633 */
bogdanm 0:9b334a45a8ff 634 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 635 {
bogdanm 0:9b334a45a8ff 636 return hdma->State;
bogdanm 0:9b334a45a8ff 637 }
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 /**
bogdanm 0:9b334a45a8ff 640 * @brief Return the DMA error code
bogdanm 0:9b334a45a8ff 641 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 642 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 643 * @retval DMA Error Code
bogdanm 0:9b334a45a8ff 644 */
bogdanm 0:9b334a45a8ff 645 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 646 {
bogdanm 0:9b334a45a8ff 647 return hdma->ErrorCode;
bogdanm 0:9b334a45a8ff 648 }
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 /**
bogdanm 0:9b334a45a8ff 651 * @}
bogdanm 0:9b334a45a8ff 652 */
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /**
bogdanm 0:9b334a45a8ff 655 * @}
bogdanm 0:9b334a45a8ff 656 */
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658 /** @addtogroup DMA_Private_Functions DMA Private Functions
bogdanm 0:9b334a45a8ff 659 * @{
bogdanm 0:9b334a45a8ff 660 */
bogdanm 0:9b334a45a8ff 661
bogdanm 0:9b334a45a8ff 662 /**
bogdanm 0:9b334a45a8ff 663 * @brief Sets the DMA Transfer parameter.
bogdanm 0:9b334a45a8ff 664 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 665 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 666 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 667 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 668 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 669 * @retval HAL status
bogdanm 0:9b334a45a8ff 670 */
bogdanm 0:9b334a45a8ff 671 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
mbed_official 124:6a4a5b7d7324 672 {
bogdanm 0:9b334a45a8ff 673 /* Configure DMA Channel data length */
bogdanm 0:9b334a45a8ff 674 hdma->Instance->CNDTR = DataLength;
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 /* Peripheral to Memory */
bogdanm 0:9b334a45a8ff 677 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
mbed_official 124:6a4a5b7d7324 678 {
bogdanm 0:9b334a45a8ff 679 /* Configure DMA Channel destination address */
bogdanm 0:9b334a45a8ff 680 hdma->Instance->CPAR = DstAddress;
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 /* Configure DMA Channel source address */
bogdanm 0:9b334a45a8ff 683 hdma->Instance->CMAR = SrcAddress;
bogdanm 0:9b334a45a8ff 684 }
bogdanm 0:9b334a45a8ff 685 /* Memory to Peripheral */
bogdanm 0:9b334a45a8ff 686 else
bogdanm 0:9b334a45a8ff 687 {
bogdanm 0:9b334a45a8ff 688 /* Configure DMA Channel source address */
bogdanm 0:9b334a45a8ff 689 hdma->Instance->CPAR = SrcAddress;
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 /* Configure DMA Channel destination address */
bogdanm 0:9b334a45a8ff 692 hdma->Instance->CMAR = DstAddress;
bogdanm 0:9b334a45a8ff 693 }
bogdanm 0:9b334a45a8ff 694 }
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 /**
bogdanm 0:9b334a45a8ff 697 * @}
bogdanm 0:9b334a45a8ff 698 */
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700 #endif /* HAL_DMA_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 701 /**
bogdanm 0:9b334a45a8ff 702 * @}
bogdanm 0:9b334a45a8ff 703 */
bogdanm 0:9b334a45a8ff 704
bogdanm 0:9b334a45a8ff 705 /**
bogdanm 0:9b334a45a8ff 706 * @}
bogdanm 0:9b334a45a8ff 707 */
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/