en 129
fix LPC812 PWM
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mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.h@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 124:6a4a5b7d7324
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f1xx_hal_adc.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| mbed_official | 124:6a4a5b7d7324 | 5 | * @version V1.0.4 |
| mbed_official | 124:6a4a5b7d7324 | 6 | * @date 29-April-2016 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file containing functions prototypes of ADC HAL library. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| mbed_official | 124:6a4a5b7d7324 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32F1xx_HAL_ADC_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32F1xx_HAL_ADC_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32f1xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | /** @addtogroup STM32F1xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 49 | * @{ |
| bogdanm | 0:9b334a45a8ff | 50 | */ |
| bogdanm | 0:9b334a45a8ff | 51 | |
| bogdanm | 0:9b334a45a8ff | 52 | /** @addtogroup ADC |
| bogdanm | 0:9b334a45a8ff | 53 | * @{ |
| bogdanm | 0:9b334a45a8ff | 54 | */ |
| bogdanm | 0:9b334a45a8ff | 55 | |
| bogdanm | 0:9b334a45a8ff | 56 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 57 | /** @defgroup ADC_Exported_Types ADC Exported Types |
| bogdanm | 0:9b334a45a8ff | 58 | * @{ |
| bogdanm | 0:9b334a45a8ff | 59 | */ |
| bogdanm | 0:9b334a45a8ff | 60 | |
| bogdanm | 0:9b334a45a8ff | 61 | /** |
| bogdanm | 0:9b334a45a8ff | 62 | * @brief Structure definition of ADC and regular group initialization |
| bogdanm | 0:9b334a45a8ff | 63 | * @note Parameters of this structure are shared within 2 scopes: |
| bogdanm | 0:9b334a45a8ff | 64 | * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. |
| bogdanm | 0:9b334a45a8ff | 65 | * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. |
| bogdanm | 0:9b334a45a8ff | 66 | * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. |
| bogdanm | 0:9b334a45a8ff | 67 | * ADC can be either disabled or enabled without conversion on going on regular group. |
| bogdanm | 0:9b334a45a8ff | 68 | */ |
| bogdanm | 0:9b334a45a8ff | 69 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 70 | { |
| bogdanm | 0:9b334a45a8ff | 71 | uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) |
| bogdanm | 0:9b334a45a8ff | 72 | or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). |
| bogdanm | 0:9b334a45a8ff | 73 | This parameter can be a value of @ref ADC_Data_align */ |
| bogdanm | 0:9b334a45a8ff | 74 | uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. |
| bogdanm | 0:9b334a45a8ff | 75 | This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
| bogdanm | 0:9b334a45a8ff | 76 | If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). |
| bogdanm | 0:9b334a45a8ff | 77 | Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). |
| bogdanm | 0:9b334a45a8ff | 78 | If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). |
| bogdanm | 0:9b334a45a8ff | 79 | Scan direction is upward: from rank1 to rank 'n'. |
| bogdanm | 0:9b334a45a8ff | 80 | This parameter can be a value of @ref ADC_Scan_mode |
| bogdanm | 0:9b334a45a8ff | 81 | Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) |
| bogdanm | 0:9b334a45a8ff | 82 | or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the |
| bogdanm | 0:9b334a45a8ff | 83 | the last conversion of the sequence. All previous conversions would be overwritten by the last one. |
| bogdanm | 0:9b334a45a8ff | 84 | Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ |
| bogdanm | 0:9b334a45a8ff | 85 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, |
| bogdanm | 0:9b334a45a8ff | 86 | after the selected trigger occurred (software start or external trigger). |
| bogdanm | 0:9b334a45a8ff | 87 | This parameter can be set to ENABLE or DISABLE. */ |
| bogdanm | 0:9b334a45a8ff | 88 | uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. |
| bogdanm | 0:9b334a45a8ff | 89 | To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
| bogdanm | 0:9b334a45a8ff | 90 | This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ |
| bogdanm | 0:9b334a45a8ff | 91 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
| bogdanm | 0:9b334a45a8ff | 92 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
| bogdanm | 0:9b334a45a8ff | 93 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
| bogdanm | 0:9b334a45a8ff | 94 | This parameter can be set to ENABLE or DISABLE. */ |
| bogdanm | 0:9b334a45a8ff | 95 | uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. |
| bogdanm | 0:9b334a45a8ff | 96 | If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. |
| bogdanm | 0:9b334a45a8ff | 97 | This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ |
| bogdanm | 0:9b334a45a8ff | 98 | uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. |
| bogdanm | 0:9b334a45a8ff | 99 | If set to ADC_SOFTWARE_START, external triggers are disabled. |
| bogdanm | 0:9b334a45a8ff | 100 | If set to external trigger source, triggering is on event rising edge. |
| bogdanm | 0:9b334a45a8ff | 101 | This parameter can be a value of @ref ADC_External_trigger_source_Regular */ |
| bogdanm | 0:9b334a45a8ff | 102 | }ADC_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 103 | |
| bogdanm | 0:9b334a45a8ff | 104 | /** |
| bogdanm | 0:9b334a45a8ff | 105 | * @brief Structure definition of ADC channel for regular group |
| bogdanm | 0:9b334a45a8ff | 106 | * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
| bogdanm | 0:9b334a45a8ff | 107 | * ADC can be either disabled or enabled without conversion on going on regular group. |
| bogdanm | 0:9b334a45a8ff | 108 | */ |
| bogdanm | 0:9b334a45a8ff | 109 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 110 | { |
| bogdanm | 0:9b334a45a8ff | 111 | uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. |
| bogdanm | 0:9b334a45a8ff | 112 | This parameter can be a value of @ref ADC_channels |
| bogdanm | 0:9b334a45a8ff | 113 | Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. |
| bogdanm | 0:9b334a45a8ff | 114 | Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) |
| bogdanm | 0:9b334a45a8ff | 115 | Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. |
| bogdanm | 0:9b334a45a8ff | 116 | It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. |
| bogdanm | 0:9b334a45a8ff | 117 | Refer to errata sheet of these devices for more details. */ |
| bogdanm | 0:9b334a45a8ff | 118 | uint32_t Rank; /*!< Specifies the rank in the regular group sequencer |
| bogdanm | 0:9b334a45a8ff | 119 | This parameter can be a value of @ref ADC_regular_rank |
| bogdanm | 0:9b334a45a8ff | 120 | Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ |
| bogdanm | 0:9b334a45a8ff | 121 | uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. |
| bogdanm | 0:9b334a45a8ff | 122 | Unit: ADC clock cycles |
| bogdanm | 0:9b334a45a8ff | 123 | Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). |
| bogdanm | 0:9b334a45a8ff | 124 | This parameter can be a value of @ref ADC_sampling_times |
| bogdanm | 0:9b334a45a8ff | 125 | Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
| bogdanm | 0:9b334a45a8ff | 126 | If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
| bogdanm | 0:9b334a45a8ff | 127 | Note: In case of usage of internal measurement channels (VrefInt/TempSensor), |
| bogdanm | 0:9b334a45a8ff | 128 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
| bogdanm | 0:9b334a45a8ff | 129 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ |
| bogdanm | 0:9b334a45a8ff | 130 | }ADC_ChannelConfTypeDef; |
| bogdanm | 0:9b334a45a8ff | 131 | |
| bogdanm | 0:9b334a45a8ff | 132 | /** |
| bogdanm | 0:9b334a45a8ff | 133 | * @brief ADC Configuration analog watchdog definition |
| bogdanm | 0:9b334a45a8ff | 134 | * @note The setting of these parameters with function is conditioned to ADC state. |
| bogdanm | 0:9b334a45a8ff | 135 | * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. |
| bogdanm | 0:9b334a45a8ff | 136 | */ |
| bogdanm | 0:9b334a45a8ff | 137 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 138 | { |
| bogdanm | 0:9b334a45a8ff | 139 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. |
| bogdanm | 0:9b334a45a8ff | 140 | This parameter can be a value of @ref ADC_analog_watchdog_mode. */ |
| bogdanm | 0:9b334a45a8ff | 141 | uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. |
| bogdanm | 0:9b334a45a8ff | 142 | This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) |
| bogdanm | 0:9b334a45a8ff | 143 | This parameter can be a value of @ref ADC_channels. */ |
| bogdanm | 0:9b334a45a8ff | 144 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. |
| bogdanm | 0:9b334a45a8ff | 145 | This parameter can be set to ENABLE or DISABLE */ |
| bogdanm | 0:9b334a45a8ff | 146 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| bogdanm | 0:9b334a45a8ff | 147 | This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ |
| bogdanm | 0:9b334a45a8ff | 148 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| bogdanm | 0:9b334a45a8ff | 149 | This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ |
| bogdanm | 0:9b334a45a8ff | 150 | uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ |
| bogdanm | 0:9b334a45a8ff | 151 | }ADC_AnalogWDGConfTypeDef; |
| bogdanm | 0:9b334a45a8ff | 152 | |
| bogdanm | 0:9b334a45a8ff | 153 | /** |
| mbed_official | 124:6a4a5b7d7324 | 154 | * @brief HAL ADC state machine: ADC states definition (bitfields) |
| bogdanm | 0:9b334a45a8ff | 155 | */ |
| mbed_official | 124:6a4a5b7d7324 | 156 | /* States of ADC global scope */ |
| mbed_official | 124:6a4a5b7d7324 | 157 | #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ |
| mbed_official | 124:6a4a5b7d7324 | 158 | #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ |
| mbed_official | 124:6a4a5b7d7324 | 159 | #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */ |
| mbed_official | 124:6a4a5b7d7324 | 160 | #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ |
| mbed_official | 124:6a4a5b7d7324 | 161 | |
| mbed_official | 124:6a4a5b7d7324 | 162 | /* States of ADC errors */ |
| mbed_official | 124:6a4a5b7d7324 | 163 | #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ |
| mbed_official | 124:6a4a5b7d7324 | 164 | #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ |
| mbed_official | 124:6a4a5b7d7324 | 165 | #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ |
| mbed_official | 124:6a4a5b7d7324 | 166 | |
| mbed_official | 124:6a4a5b7d7324 | 167 | /* States of ADC group regular */ |
| mbed_official | 124:6a4a5b7d7324 | 168 | #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, |
| mbed_official | 124:6a4a5b7d7324 | 169 | external trigger, low power auto power-on, multimode ADC master control) */ |
| mbed_official | 124:6a4a5b7d7324 | 170 | #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ |
| mbed_official | 124:6a4a5b7d7324 | 171 | #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Not available on STM32F1 device: Overrun occurrence */ |
| mbed_official | 124:6a4a5b7d7324 | 172 | #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F1 device: End Of Sampling flag raised */ |
| mbed_official | 124:6a4a5b7d7324 | 173 | |
| mbed_official | 124:6a4a5b7d7324 | 174 | /* States of ADC group injected */ |
| mbed_official | 124:6a4a5b7d7324 | 175 | #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, |
| mbed_official | 124:6a4a5b7d7324 | 176 | external trigger, low power auto power-on, multimode ADC master control) */ |
| mbed_official | 124:6a4a5b7d7324 | 177 | #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */ |
| mbed_official | 124:6a4a5b7d7324 | 178 | #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ |
| mbed_official | 124:6a4a5b7d7324 | 179 | |
| mbed_official | 124:6a4a5b7d7324 | 180 | /* States of ADC analog watchdogs */ |
| mbed_official | 124:6a4a5b7d7324 | 181 | #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */ |
| mbed_official | 124:6a4a5b7d7324 | 182 | #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ |
| mbed_official | 124:6a4a5b7d7324 | 183 | #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ |
| mbed_official | 124:6a4a5b7d7324 | 184 | |
| mbed_official | 124:6a4a5b7d7324 | 185 | /* States of ADC multi-mode */ |
| mbed_official | 124:6a4a5b7d7324 | 186 | #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master ( */ |
| mbed_official | 124:6a4a5b7d7324 | 187 | |
| bogdanm | 0:9b334a45a8ff | 188 | |
| bogdanm | 0:9b334a45a8ff | 189 | /** |
| bogdanm | 0:9b334a45a8ff | 190 | * @brief ADC handle Structure definition |
| bogdanm | 0:9b334a45a8ff | 191 | */ |
| bogdanm | 0:9b334a45a8ff | 192 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 193 | { |
| bogdanm | 0:9b334a45a8ff | 194 | ADC_TypeDef *Instance; /*!< Register base address */ |
| bogdanm | 0:9b334a45a8ff | 195 | |
| bogdanm | 0:9b334a45a8ff | 196 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
| bogdanm | 0:9b334a45a8ff | 197 | |
| bogdanm | 0:9b334a45a8ff | 198 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
| bogdanm | 0:9b334a45a8ff | 199 | |
| bogdanm | 0:9b334a45a8ff | 200 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
| mbed_official | 124:6a4a5b7d7324 | 201 | |
| mbed_official | 124:6a4a5b7d7324 | 202 | __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ |
| bogdanm | 0:9b334a45a8ff | 203 | |
| bogdanm | 0:9b334a45a8ff | 204 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
| bogdanm | 0:9b334a45a8ff | 205 | }ADC_HandleTypeDef; |
| bogdanm | 0:9b334a45a8ff | 206 | /** |
| bogdanm | 0:9b334a45a8ff | 207 | * @} |
| bogdanm | 0:9b334a45a8ff | 208 | */ |
| bogdanm | 0:9b334a45a8ff | 209 | |
| bogdanm | 0:9b334a45a8ff | 210 | |
| bogdanm | 0:9b334a45a8ff | 211 | |
| bogdanm | 0:9b334a45a8ff | 212 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 213 | |
| bogdanm | 0:9b334a45a8ff | 214 | /** @defgroup ADC_Exported_Constants ADC Exported Constants |
| bogdanm | 0:9b334a45a8ff | 215 | * @{ |
| bogdanm | 0:9b334a45a8ff | 216 | */ |
| bogdanm | 0:9b334a45a8ff | 217 | |
| bogdanm | 0:9b334a45a8ff | 218 | /** @defgroup ADC_Error_Code ADC Error Code |
| bogdanm | 0:9b334a45a8ff | 219 | * @{ |
| bogdanm | 0:9b334a45a8ff | 220 | */ |
| bogdanm | 0:9b334a45a8ff | 221 | #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| bogdanm | 0:9b334a45a8ff | 222 | #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, |
| bogdanm | 0:9b334a45a8ff | 223 | enable/disable, erroneous state */ |
| bogdanm | 0:9b334a45a8ff | 224 | #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ |
| bogdanm | 0:9b334a45a8ff | 225 | #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ |
| bogdanm | 0:9b334a45a8ff | 226 | |
| bogdanm | 0:9b334a45a8ff | 227 | /** |
| bogdanm | 0:9b334a45a8ff | 228 | * @} |
| bogdanm | 0:9b334a45a8ff | 229 | */ |
| bogdanm | 0:9b334a45a8ff | 230 | |
| bogdanm | 0:9b334a45a8ff | 231 | |
| bogdanm | 0:9b334a45a8ff | 232 | /** @defgroup ADC_Data_align ADC data alignment |
| bogdanm | 0:9b334a45a8ff | 233 | * @{ |
| bogdanm | 0:9b334a45a8ff | 234 | */ |
| bogdanm | 0:9b334a45a8ff | 235 | #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 236 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) |
| bogdanm | 0:9b334a45a8ff | 237 | /** |
| bogdanm | 0:9b334a45a8ff | 238 | * @} |
| bogdanm | 0:9b334a45a8ff | 239 | */ |
| bogdanm | 0:9b334a45a8ff | 240 | |
| bogdanm | 0:9b334a45a8ff | 241 | /** @defgroup ADC_Scan_mode ADC scan mode |
| bogdanm | 0:9b334a45a8ff | 242 | * @{ |
| bogdanm | 0:9b334a45a8ff | 243 | */ |
| bogdanm | 0:9b334a45a8ff | 244 | /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ |
| bogdanm | 0:9b334a45a8ff | 245 | /* compatibility with other STM32 devices having a sequencer with */ |
| bogdanm | 0:9b334a45a8ff | 246 | /* additional options. */ |
| bogdanm | 0:9b334a45a8ff | 247 | #define ADC_SCAN_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 248 | #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) |
| bogdanm | 0:9b334a45a8ff | 249 | /** |
| bogdanm | 0:9b334a45a8ff | 250 | * @} |
| bogdanm | 0:9b334a45a8ff | 251 | */ |
| bogdanm | 0:9b334a45a8ff | 252 | |
| bogdanm | 0:9b334a45a8ff | 253 | /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group |
| bogdanm | 0:9b334a45a8ff | 254 | * @{ |
| bogdanm | 0:9b334a45a8ff | 255 | */ |
| bogdanm | 0:9b334a45a8ff | 256 | #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 257 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) |
| bogdanm | 0:9b334a45a8ff | 258 | /** |
| bogdanm | 0:9b334a45a8ff | 259 | * @} |
| bogdanm | 0:9b334a45a8ff | 260 | */ |
| bogdanm | 0:9b334a45a8ff | 261 | |
| bogdanm | 0:9b334a45a8ff | 262 | /** @defgroup ADC_channels ADC channels |
| bogdanm | 0:9b334a45a8ff | 263 | * @{ |
| bogdanm | 0:9b334a45a8ff | 264 | */ |
| bogdanm | 0:9b334a45a8ff | 265 | /* Note: Depending on devices, some channels may not be available on package */ |
| bogdanm | 0:9b334a45a8ff | 266 | /* pins. Refer to device datasheet for channels availability. */ |
| bogdanm | 0:9b334a45a8ff | 267 | #define ADC_CHANNEL_0 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 268 | #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 269 | #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) |
| bogdanm | 0:9b334a45a8ff | 270 | #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 271 | #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) |
| bogdanm | 0:9b334a45a8ff | 272 | #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 273 | #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) |
| bogdanm | 0:9b334a45a8ff | 274 | #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 275 | #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) |
| bogdanm | 0:9b334a45a8ff | 276 | #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 277 | #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) |
| bogdanm | 0:9b334a45a8ff | 278 | #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 279 | #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) |
| bogdanm | 0:9b334a45a8ff | 280 | #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 281 | #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) |
| bogdanm | 0:9b334a45a8ff | 282 | #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 283 | #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) |
| bogdanm | 0:9b334a45a8ff | 284 | #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) |
| bogdanm | 0:9b334a45a8ff | 285 | |
| bogdanm | 0:9b334a45a8ff | 286 | #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ |
| bogdanm | 0:9b334a45a8ff | 287 | #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ |
| bogdanm | 0:9b334a45a8ff | 288 | /** |
| bogdanm | 0:9b334a45a8ff | 289 | * @} |
| bogdanm | 0:9b334a45a8ff | 290 | */ |
| bogdanm | 0:9b334a45a8ff | 291 | |
| bogdanm | 0:9b334a45a8ff | 292 | /** @defgroup ADC_sampling_times ADC sampling times |
| bogdanm | 0:9b334a45a8ff | 293 | * @{ |
| bogdanm | 0:9b334a45a8ff | 294 | */ |
| bogdanm | 0:9b334a45a8ff | 295 | #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */ |
| bogdanm | 0:9b334a45a8ff | 296 | #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ |
| bogdanm | 0:9b334a45a8ff | 297 | #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ |
| bogdanm | 0:9b334a45a8ff | 298 | #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ |
| bogdanm | 0:9b334a45a8ff | 299 | #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ |
| bogdanm | 0:9b334a45a8ff | 300 | #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ |
| bogdanm | 0:9b334a45a8ff | 301 | #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ |
| bogdanm | 0:9b334a45a8ff | 302 | #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ |
| bogdanm | 0:9b334a45a8ff | 303 | /** |
| bogdanm | 0:9b334a45a8ff | 304 | * @} |
| bogdanm | 0:9b334a45a8ff | 305 | */ |
| bogdanm | 0:9b334a45a8ff | 306 | |
| bogdanm | 0:9b334a45a8ff | 307 | /** @defgroup ADC_regular_rank ADC rank into regular group |
| bogdanm | 0:9b334a45a8ff | 308 | * @{ |
| bogdanm | 0:9b334a45a8ff | 309 | */ |
| bogdanm | 0:9b334a45a8ff | 310 | #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 311 | #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) |
| bogdanm | 0:9b334a45a8ff | 312 | #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) |
| bogdanm | 0:9b334a45a8ff | 313 | #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) |
| bogdanm | 0:9b334a45a8ff | 314 | #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) |
| bogdanm | 0:9b334a45a8ff | 315 | #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) |
| bogdanm | 0:9b334a45a8ff | 316 | #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) |
| bogdanm | 0:9b334a45a8ff | 317 | #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) |
| bogdanm | 0:9b334a45a8ff | 318 | #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) |
| bogdanm | 0:9b334a45a8ff | 319 | #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) |
| bogdanm | 0:9b334a45a8ff | 320 | #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) |
| bogdanm | 0:9b334a45a8ff | 321 | #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) |
| bogdanm | 0:9b334a45a8ff | 322 | #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) |
| bogdanm | 0:9b334a45a8ff | 323 | #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) |
| bogdanm | 0:9b334a45a8ff | 324 | #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) |
| bogdanm | 0:9b334a45a8ff | 325 | #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) |
| bogdanm | 0:9b334a45a8ff | 326 | /** |
| bogdanm | 0:9b334a45a8ff | 327 | * @} |
| bogdanm | 0:9b334a45a8ff | 328 | */ |
| bogdanm | 0:9b334a45a8ff | 329 | |
| bogdanm | 0:9b334a45a8ff | 330 | /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode |
| bogdanm | 0:9b334a45a8ff | 331 | * @{ |
| bogdanm | 0:9b334a45a8ff | 332 | */ |
| bogdanm | 0:9b334a45a8ff | 333 | #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 334 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) |
| bogdanm | 0:9b334a45a8ff | 335 | #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) |
| bogdanm | 0:9b334a45a8ff | 336 | #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| bogdanm | 0:9b334a45a8ff | 337 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) |
| bogdanm | 0:9b334a45a8ff | 338 | #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) |
| bogdanm | 0:9b334a45a8ff | 339 | #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| bogdanm | 0:9b334a45a8ff | 340 | /** |
| bogdanm | 0:9b334a45a8ff | 341 | * @} |
| bogdanm | 0:9b334a45a8ff | 342 | */ |
| bogdanm | 0:9b334a45a8ff | 343 | |
| bogdanm | 0:9b334a45a8ff | 344 | /** @defgroup ADC_conversion_group ADC conversion group |
| bogdanm | 0:9b334a45a8ff | 345 | * @{ |
| bogdanm | 0:9b334a45a8ff | 346 | */ |
| bogdanm | 0:9b334a45a8ff | 347 | #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) |
| bogdanm | 0:9b334a45a8ff | 348 | #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) |
| bogdanm | 0:9b334a45a8ff | 349 | #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) |
| bogdanm | 0:9b334a45a8ff | 350 | /** |
| bogdanm | 0:9b334a45a8ff | 351 | * @} |
| bogdanm | 0:9b334a45a8ff | 352 | */ |
| bogdanm | 0:9b334a45a8ff | 353 | |
| bogdanm | 0:9b334a45a8ff | 354 | /** @defgroup ADC_Event_type ADC Event type |
| bogdanm | 0:9b334a45a8ff | 355 | * @{ |
| bogdanm | 0:9b334a45a8ff | 356 | */ |
| bogdanm | 0:9b334a45a8ff | 357 | #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ |
| bogdanm | 0:9b334a45a8ff | 358 | |
| bogdanm | 0:9b334a45a8ff | 359 | #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ |
| bogdanm | 0:9b334a45a8ff | 360 | /** |
| bogdanm | 0:9b334a45a8ff | 361 | * @} |
| bogdanm | 0:9b334a45a8ff | 362 | */ |
| bogdanm | 0:9b334a45a8ff | 363 | |
| bogdanm | 0:9b334a45a8ff | 364 | /** @defgroup ADC_interrupts_definition ADC interrupts definition |
| bogdanm | 0:9b334a45a8ff | 365 | * @{ |
| bogdanm | 0:9b334a45a8ff | 366 | */ |
| bogdanm | 0:9b334a45a8ff | 367 | #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ |
| bogdanm | 0:9b334a45a8ff | 368 | #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ |
| bogdanm | 0:9b334a45a8ff | 369 | #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ |
| bogdanm | 0:9b334a45a8ff | 370 | /** |
| bogdanm | 0:9b334a45a8ff | 371 | * @} |
| bogdanm | 0:9b334a45a8ff | 372 | */ |
| bogdanm | 0:9b334a45a8ff | 373 | |
| bogdanm | 0:9b334a45a8ff | 374 | /** @defgroup ADC_flags_definition ADC flags definition |
| bogdanm | 0:9b334a45a8ff | 375 | * @{ |
| bogdanm | 0:9b334a45a8ff | 376 | */ |
| bogdanm | 0:9b334a45a8ff | 377 | #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ |
| bogdanm | 0:9b334a45a8ff | 378 | #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ |
| bogdanm | 0:9b334a45a8ff | 379 | #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ |
| bogdanm | 0:9b334a45a8ff | 380 | #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ |
| bogdanm | 0:9b334a45a8ff | 381 | #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ |
| bogdanm | 0:9b334a45a8ff | 382 | /** |
| bogdanm | 0:9b334a45a8ff | 383 | * @} |
| bogdanm | 0:9b334a45a8ff | 384 | */ |
| bogdanm | 0:9b334a45a8ff | 385 | |
| bogdanm | 0:9b334a45a8ff | 386 | |
| bogdanm | 0:9b334a45a8ff | 387 | /** |
| bogdanm | 0:9b334a45a8ff | 388 | * @} |
| bogdanm | 0:9b334a45a8ff | 389 | */ |
| bogdanm | 0:9b334a45a8ff | 390 | |
| bogdanm | 0:9b334a45a8ff | 391 | /* Private constants ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 392 | |
| bogdanm | 0:9b334a45a8ff | 393 | /** @addtogroup ADC_Private_Constants ADC Private Constants |
| bogdanm | 0:9b334a45a8ff | 394 | * @{ |
| bogdanm | 0:9b334a45a8ff | 395 | */ |
| bogdanm | 0:9b334a45a8ff | 396 | |
| bogdanm | 0:9b334a45a8ff | 397 | /** @defgroup ADC_conversion_cycles ADC conversion cycles |
| bogdanm | 0:9b334a45a8ff | 398 | * @{ |
| bogdanm | 0:9b334a45a8ff | 399 | */ |
| bogdanm | 0:9b334a45a8ff | 400 | /* ADC conversion cycles (unit: ADC clock cycles) */ |
| bogdanm | 0:9b334a45a8ff | 401 | /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ |
| bogdanm | 0:9b334a45a8ff | 402 | /* resolution 12 bits) */ |
| bogdanm | 0:9b334a45a8ff | 403 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14) |
| bogdanm | 0:9b334a45a8ff | 404 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20) |
| bogdanm | 0:9b334a45a8ff | 405 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26) |
| bogdanm | 0:9b334a45a8ff | 406 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41) |
| bogdanm | 0:9b334a45a8ff | 407 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54) |
| bogdanm | 0:9b334a45a8ff | 408 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68) |
| bogdanm | 0:9b334a45a8ff | 409 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84) |
| bogdanm | 0:9b334a45a8ff | 410 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252) |
| bogdanm | 0:9b334a45a8ff | 411 | /** |
| bogdanm | 0:9b334a45a8ff | 412 | * @} |
| bogdanm | 0:9b334a45a8ff | 413 | */ |
| bogdanm | 0:9b334a45a8ff | 414 | |
| bogdanm | 0:9b334a45a8ff | 415 | /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels |
| bogdanm | 0:9b334a45a8ff | 416 | * @{ |
| bogdanm | 0:9b334a45a8ff | 417 | */ |
| bogdanm | 0:9b334a45a8ff | 418 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ |
| bogdanm | 0:9b334a45a8ff | 419 | (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ |
| bogdanm | 0:9b334a45a8ff | 420 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ |
| bogdanm | 0:9b334a45a8ff | 421 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) |
| bogdanm | 0:9b334a45a8ff | 422 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ |
| bogdanm | 0:9b334a45a8ff | 423 | (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ |
| bogdanm | 0:9b334a45a8ff | 424 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) |
| bogdanm | 0:9b334a45a8ff | 425 | |
| bogdanm | 0:9b334a45a8ff | 426 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ |
| bogdanm | 0:9b334a45a8ff | 427 | (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ |
| bogdanm | 0:9b334a45a8ff | 428 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ |
| bogdanm | 0:9b334a45a8ff | 429 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) |
| bogdanm | 0:9b334a45a8ff | 430 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ |
| bogdanm | 0:9b334a45a8ff | 431 | (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ |
| bogdanm | 0:9b334a45a8ff | 432 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) |
| bogdanm | 0:9b334a45a8ff | 433 | |
| bogdanm | 0:9b334a45a8ff | 434 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ |
| bogdanm | 0:9b334a45a8ff | 435 | (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ |
| bogdanm | 0:9b334a45a8ff | 436 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ |
| bogdanm | 0:9b334a45a8ff | 437 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) |
| bogdanm | 0:9b334a45a8ff | 438 | #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ |
| bogdanm | 0:9b334a45a8ff | 439 | (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ |
| bogdanm | 0:9b334a45a8ff | 440 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) |
| bogdanm | 0:9b334a45a8ff | 441 | |
| bogdanm | 0:9b334a45a8ff | 442 | #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 443 | #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| bogdanm | 0:9b334a45a8ff | 444 | #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) |
| bogdanm | 0:9b334a45a8ff | 445 | #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| bogdanm | 0:9b334a45a8ff | 446 | #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) |
| bogdanm | 0:9b334a45a8ff | 447 | #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| bogdanm | 0:9b334a45a8ff | 448 | #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) |
| bogdanm | 0:9b334a45a8ff | 449 | #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) |
| bogdanm | 0:9b334a45a8ff | 450 | |
| bogdanm | 0:9b334a45a8ff | 451 | #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 452 | #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| bogdanm | 0:9b334a45a8ff | 453 | #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) |
| bogdanm | 0:9b334a45a8ff | 454 | #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| bogdanm | 0:9b334a45a8ff | 455 | #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) |
| bogdanm | 0:9b334a45a8ff | 456 | #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| bogdanm | 0:9b334a45a8ff | 457 | #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) |
| bogdanm | 0:9b334a45a8ff | 458 | #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) |
| bogdanm | 0:9b334a45a8ff | 459 | /** |
| bogdanm | 0:9b334a45a8ff | 460 | * @} |
| bogdanm | 0:9b334a45a8ff | 461 | */ |
| bogdanm | 0:9b334a45a8ff | 462 | |
| bogdanm | 0:9b334a45a8ff | 463 | /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ |
| bogdanm | 0:9b334a45a8ff | 464 | #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) |
| bogdanm | 0:9b334a45a8ff | 465 | |
| bogdanm | 0:9b334a45a8ff | 466 | /** |
| bogdanm | 0:9b334a45a8ff | 467 | * @} |
| bogdanm | 0:9b334a45a8ff | 468 | */ |
| bogdanm | 0:9b334a45a8ff | 469 | |
| bogdanm | 0:9b334a45a8ff | 470 | |
| bogdanm | 0:9b334a45a8ff | 471 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 472 | |
| bogdanm | 0:9b334a45a8ff | 473 | /** @defgroup ADC_Exported_Macros ADC Exported Macros |
| bogdanm | 0:9b334a45a8ff | 474 | * @{ |
| bogdanm | 0:9b334a45a8ff | 475 | */ |
| bogdanm | 0:9b334a45a8ff | 476 | /* Macro for internal HAL driver usage, and possibly can be used into code of */ |
| bogdanm | 0:9b334a45a8ff | 477 | /* final user. */ |
| bogdanm | 0:9b334a45a8ff | 478 | |
| bogdanm | 0:9b334a45a8ff | 479 | /** |
| bogdanm | 0:9b334a45a8ff | 480 | * @brief Enable the ADC peripheral |
| bogdanm | 0:9b334a45a8ff | 481 | * @note ADC enable requires a delay for ADC stabilization time |
| bogdanm | 0:9b334a45a8ff | 482 | * (refer to device datasheet, parameter tSTAB) |
| bogdanm | 0:9b334a45a8ff | 483 | * @note On STM32F1, if ADC is already enabled this macro trigs a conversion |
| bogdanm | 0:9b334a45a8ff | 484 | * SW start on regular group. |
| bogdanm | 0:9b334a45a8ff | 485 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 486 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 487 | */ |
| bogdanm | 0:9b334a45a8ff | 488 | #define __HAL_ADC_ENABLE(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 489 | (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) |
| bogdanm | 0:9b334a45a8ff | 490 | |
| bogdanm | 0:9b334a45a8ff | 491 | /** |
| bogdanm | 0:9b334a45a8ff | 492 | * @brief Disable the ADC peripheral |
| bogdanm | 0:9b334a45a8ff | 493 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 494 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 495 | */ |
| bogdanm | 0:9b334a45a8ff | 496 | #define __HAL_ADC_DISABLE(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 497 | (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) |
| bogdanm | 0:9b334a45a8ff | 498 | |
| bogdanm | 0:9b334a45a8ff | 499 | /** @brief Enable the ADC end of conversion interrupt. |
| bogdanm | 0:9b334a45a8ff | 500 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 501 | * @param __INTERRUPT__: ADC Interrupt |
| bogdanm | 0:9b334a45a8ff | 502 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 503 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| bogdanm | 0:9b334a45a8ff | 504 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| bogdanm | 0:9b334a45a8ff | 505 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| bogdanm | 0:9b334a45a8ff | 506 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 507 | */ |
| bogdanm | 0:9b334a45a8ff | 508 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| bogdanm | 0:9b334a45a8ff | 509 | (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) |
| bogdanm | 0:9b334a45a8ff | 510 | |
| bogdanm | 0:9b334a45a8ff | 511 | /** @brief Disable the ADC end of conversion interrupt. |
| bogdanm | 0:9b334a45a8ff | 512 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 513 | * @param __INTERRUPT__: ADC Interrupt |
| bogdanm | 0:9b334a45a8ff | 514 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 515 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| bogdanm | 0:9b334a45a8ff | 516 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| bogdanm | 0:9b334a45a8ff | 517 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| bogdanm | 0:9b334a45a8ff | 518 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 519 | */ |
| bogdanm | 0:9b334a45a8ff | 520 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| bogdanm | 0:9b334a45a8ff | 521 | (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) |
| bogdanm | 0:9b334a45a8ff | 522 | |
| bogdanm | 0:9b334a45a8ff | 523 | /** @brief Checks if the specified ADC interrupt source is enabled or disabled. |
| bogdanm | 0:9b334a45a8ff | 524 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 525 | * @param __INTERRUPT__: ADC interrupt source to check |
| bogdanm | 0:9b334a45a8ff | 526 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 527 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| bogdanm | 0:9b334a45a8ff | 528 | * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source |
| bogdanm | 0:9b334a45a8ff | 529 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| bogdanm | 0:9b334a45a8ff | 530 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 531 | */ |
| bogdanm | 0:9b334a45a8ff | 532 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
| bogdanm | 0:9b334a45a8ff | 533 | (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 534 | |
| bogdanm | 0:9b334a45a8ff | 535 | /** @brief Get the selected ADC's flag status. |
| bogdanm | 0:9b334a45a8ff | 536 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 537 | * @param __FLAG__: ADC flag |
| bogdanm | 0:9b334a45a8ff | 538 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 539 | * @arg ADC_FLAG_STRT: ADC Regular group start flag |
| bogdanm | 0:9b334a45a8ff | 540 | * @arg ADC_FLAG_JSTRT: ADC Injected group start flag |
| bogdanm | 0:9b334a45a8ff | 541 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
| bogdanm | 0:9b334a45a8ff | 542 | * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag |
| bogdanm | 0:9b334a45a8ff | 543 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
| bogdanm | 0:9b334a45a8ff | 544 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 545 | */ |
| bogdanm | 0:9b334a45a8ff | 546 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ |
| bogdanm | 0:9b334a45a8ff | 547 | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 548 | |
| bogdanm | 0:9b334a45a8ff | 549 | /** @brief Clear the ADC's pending flags |
| bogdanm | 0:9b334a45a8ff | 550 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 551 | * @param __FLAG__: ADC flag |
| bogdanm | 0:9b334a45a8ff | 552 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 553 | * @arg ADC_FLAG_STRT: ADC Regular group start flag |
| bogdanm | 0:9b334a45a8ff | 554 | * @arg ADC_FLAG_JSTRT: ADC Injected group start flag |
| bogdanm | 0:9b334a45a8ff | 555 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
| bogdanm | 0:9b334a45a8ff | 556 | * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag |
| bogdanm | 0:9b334a45a8ff | 557 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
| bogdanm | 0:9b334a45a8ff | 558 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 559 | */ |
| bogdanm | 0:9b334a45a8ff | 560 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| mbed_official | 124:6a4a5b7d7324 | 561 | (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) |
| bogdanm | 0:9b334a45a8ff | 562 | |
| bogdanm | 0:9b334a45a8ff | 563 | /** @brief Reset ADC handle state |
| bogdanm | 0:9b334a45a8ff | 564 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 565 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 566 | */ |
| bogdanm | 0:9b334a45a8ff | 567 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 568 | ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
| bogdanm | 0:9b334a45a8ff | 569 | |
| bogdanm | 0:9b334a45a8ff | 570 | /** |
| bogdanm | 0:9b334a45a8ff | 571 | * @} |
| bogdanm | 0:9b334a45a8ff | 572 | */ |
| bogdanm | 0:9b334a45a8ff | 573 | |
| bogdanm | 0:9b334a45a8ff | 574 | /* Private macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 575 | |
| bogdanm | 0:9b334a45a8ff | 576 | /** @defgroup ADC_Private_Macros ADC Private Macros |
| bogdanm | 0:9b334a45a8ff | 577 | * @{ |
| bogdanm | 0:9b334a45a8ff | 578 | */ |
| bogdanm | 0:9b334a45a8ff | 579 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ |
| bogdanm | 0:9b334a45a8ff | 580 | /* code of final user. */ |
| bogdanm | 0:9b334a45a8ff | 581 | |
| bogdanm | 0:9b334a45a8ff | 582 | /** |
| bogdanm | 0:9b334a45a8ff | 583 | * @brief Verification of ADC state: enabled or disabled |
| bogdanm | 0:9b334a45a8ff | 584 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 585 | * @retval SET (ADC enabled) or RESET (ADC disabled) |
| bogdanm | 0:9b334a45a8ff | 586 | */ |
| bogdanm | 0:9b334a45a8ff | 587 | #define ADC_IS_ENABLE(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 588 | ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ |
| bogdanm | 0:9b334a45a8ff | 589 | ) ? SET : RESET) |
| bogdanm | 0:9b334a45a8ff | 590 | |
| bogdanm | 0:9b334a45a8ff | 591 | /** |
| bogdanm | 0:9b334a45a8ff | 592 | * @brief Test if conversion trigger of regular group is software start |
| bogdanm | 0:9b334a45a8ff | 593 | * or external trigger. |
| bogdanm | 0:9b334a45a8ff | 594 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 595 | * @retval SET (software start) or RESET (external trigger) |
| bogdanm | 0:9b334a45a8ff | 596 | */ |
| bogdanm | 0:9b334a45a8ff | 597 | #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 598 | (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) |
| bogdanm | 0:9b334a45a8ff | 599 | |
| bogdanm | 0:9b334a45a8ff | 600 | /** |
| bogdanm | 0:9b334a45a8ff | 601 | * @brief Test if conversion trigger of injected group is software start |
| bogdanm | 0:9b334a45a8ff | 602 | * or external trigger. |
| bogdanm | 0:9b334a45a8ff | 603 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 604 | * @retval SET (software start) or RESET (external trigger) |
| bogdanm | 0:9b334a45a8ff | 605 | */ |
| bogdanm | 0:9b334a45a8ff | 606 | #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 607 | (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) |
| mbed_official | 124:6a4a5b7d7324 | 608 | |
| mbed_official | 124:6a4a5b7d7324 | 609 | /** |
| mbed_official | 124:6a4a5b7d7324 | 610 | * @brief Simultaneously clears and sets specific bits of the handle State |
| mbed_official | 124:6a4a5b7d7324 | 611 | * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), |
| mbed_official | 124:6a4a5b7d7324 | 612 | * the first parameter is the ADC handle State, the second parameter is the |
| mbed_official | 124:6a4a5b7d7324 | 613 | * bit field to clear, the third and last parameter is the bit field to set. |
| mbed_official | 124:6a4a5b7d7324 | 614 | * @retval None |
| mbed_official | 124:6a4a5b7d7324 | 615 | */ |
| mbed_official | 124:6a4a5b7d7324 | 616 | #define ADC_STATE_CLR_SET MODIFY_REG |
| mbed_official | 124:6a4a5b7d7324 | 617 | |
| bogdanm | 0:9b334a45a8ff | 618 | /** |
| bogdanm | 0:9b334a45a8ff | 619 | * @brief Clear ADC error code (set it to error code: "no error") |
| bogdanm | 0:9b334a45a8ff | 620 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 621 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 622 | */ |
| bogdanm | 0:9b334a45a8ff | 623 | #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 624 | ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
| mbed_official | 124:6a4a5b7d7324 | 625 | |
| bogdanm | 0:9b334a45a8ff | 626 | /** |
| bogdanm | 0:9b334a45a8ff | 627 | * @brief Set ADC number of conversions into regular channel sequence length. |
| bogdanm | 0:9b334a45a8ff | 628 | * @param _NbrOfConversion_: Regular channel sequence length |
| bogdanm | 0:9b334a45a8ff | 629 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 630 | */ |
| bogdanm | 0:9b334a45a8ff | 631 | #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ |
| bogdanm | 0:9b334a45a8ff | 632 | (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) |
| bogdanm | 0:9b334a45a8ff | 633 | |
| bogdanm | 0:9b334a45a8ff | 634 | /** |
| bogdanm | 0:9b334a45a8ff | 635 | * @brief Set the ADC's sample time for channel numbers between 10 and 18. |
| bogdanm | 0:9b334a45a8ff | 636 | * @param _SAMPLETIME_: Sample time parameter. |
| bogdanm | 0:9b334a45a8ff | 637 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 638 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 639 | */ |
| bogdanm | 0:9b334a45a8ff | 640 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ |
| bogdanm | 0:9b334a45a8ff | 641 | ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR1_SMP11) * ((_CHANNELNB_) - 10))) |
| bogdanm | 0:9b334a45a8ff | 642 | |
| bogdanm | 0:9b334a45a8ff | 643 | /** |
| bogdanm | 0:9b334a45a8ff | 644 | * @brief Set the ADC's sample time for channel numbers between 0 and 9. |
| bogdanm | 0:9b334a45a8ff | 645 | * @param _SAMPLETIME_: Sample time parameter. |
| bogdanm | 0:9b334a45a8ff | 646 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 647 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 648 | */ |
| bogdanm | 0:9b334a45a8ff | 649 | #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ |
| bogdanm | 0:9b334a45a8ff | 650 | ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR2_SMP1) * (_CHANNELNB_))) |
| bogdanm | 0:9b334a45a8ff | 651 | |
| bogdanm | 0:9b334a45a8ff | 652 | /** |
| bogdanm | 0:9b334a45a8ff | 653 | * @brief Set the selected regular channel rank for rank between 1 and 6. |
| bogdanm | 0:9b334a45a8ff | 654 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 655 | * @param _RANKNB_: Rank number. |
| bogdanm | 0:9b334a45a8ff | 656 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 657 | */ |
| bogdanm | 0:9b334a45a8ff | 658 | #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ |
| bogdanm | 0:9b334a45a8ff | 659 | ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR3_SQ2) * ((_RANKNB_) - 1))) |
| bogdanm | 0:9b334a45a8ff | 660 | |
| bogdanm | 0:9b334a45a8ff | 661 | /** |
| bogdanm | 0:9b334a45a8ff | 662 | * @brief Set the selected regular channel rank for rank between 7 and 12. |
| bogdanm | 0:9b334a45a8ff | 663 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 664 | * @param _RANKNB_: Rank number. |
| bogdanm | 0:9b334a45a8ff | 665 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 666 | */ |
| bogdanm | 0:9b334a45a8ff | 667 | #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ |
| bogdanm | 0:9b334a45a8ff | 668 | ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR2_SQ8) * ((_RANKNB_) - 7))) |
| bogdanm | 0:9b334a45a8ff | 669 | |
| bogdanm | 0:9b334a45a8ff | 670 | /** |
| bogdanm | 0:9b334a45a8ff | 671 | * @brief Set the selected regular channel rank for rank between 13 and 16. |
| bogdanm | 0:9b334a45a8ff | 672 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 673 | * @param _RANKNB_: Rank number. |
| bogdanm | 0:9b334a45a8ff | 674 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 675 | */ |
| bogdanm | 0:9b334a45a8ff | 676 | #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ |
| bogdanm | 0:9b334a45a8ff | 677 | ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR1_SQ14) * ((_RANKNB_) - 13))) |
| bogdanm | 0:9b334a45a8ff | 678 | |
| bogdanm | 0:9b334a45a8ff | 679 | /** |
| bogdanm | 0:9b334a45a8ff | 680 | * @brief Set the injected sequence length. |
| bogdanm | 0:9b334a45a8ff | 681 | * @param _JSQR_JL_: Sequence length. |
| bogdanm | 0:9b334a45a8ff | 682 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 683 | */ |
| bogdanm | 0:9b334a45a8ff | 684 | #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ |
| bogdanm | 0:9b334a45a8ff | 685 | (((_JSQR_JL_) -1) << POSITION_VAL(ADC_JSQR_JL)) |
| bogdanm | 0:9b334a45a8ff | 686 | |
| bogdanm | 0:9b334a45a8ff | 687 | /** |
| bogdanm | 0:9b334a45a8ff | 688 | * @brief Set the selected injected channel rank |
| bogdanm | 0:9b334a45a8ff | 689 | * Note: on STM32F1 devices, channel rank position in JSQR register |
| bogdanm | 0:9b334a45a8ff | 690 | * is depending on total number of ranks selected into |
| bogdanm | 0:9b334a45a8ff | 691 | * injected sequencer (ranks sequence starting from 4-JL) |
| bogdanm | 0:9b334a45a8ff | 692 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 693 | * @param _RANKNB_: Rank number. |
| bogdanm | 0:9b334a45a8ff | 694 | * @param _JSQR_JL_: Sequence length. |
| bogdanm | 0:9b334a45a8ff | 695 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 696 | */ |
| bogdanm | 0:9b334a45a8ff | 697 | #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ |
| bogdanm | 0:9b334a45a8ff | 698 | ((_CHANNELNB_) << (POSITION_VAL(ADC_JSQR_JSQ2) * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) |
| bogdanm | 0:9b334a45a8ff | 699 | |
| bogdanm | 0:9b334a45a8ff | 700 | /** |
| bogdanm | 0:9b334a45a8ff | 701 | * @brief Enable ADC continuous conversion mode. |
| bogdanm | 0:9b334a45a8ff | 702 | * @param _CONTINUOUS_MODE_: Continuous mode. |
| bogdanm | 0:9b334a45a8ff | 703 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 704 | */ |
| bogdanm | 0:9b334a45a8ff | 705 | #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ |
| bogdanm | 0:9b334a45a8ff | 706 | ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) |
| bogdanm | 0:9b334a45a8ff | 707 | |
| bogdanm | 0:9b334a45a8ff | 708 | /** |
| bogdanm | 0:9b334a45a8ff | 709 | * @brief Configures the number of discontinuous conversions for the regular group channels. |
| bogdanm | 0:9b334a45a8ff | 710 | * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. |
| bogdanm | 0:9b334a45a8ff | 711 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 712 | */ |
| bogdanm | 0:9b334a45a8ff | 713 | #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ |
| bogdanm | 0:9b334a45a8ff | 714 | (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) |
| bogdanm | 0:9b334a45a8ff | 715 | |
| bogdanm | 0:9b334a45a8ff | 716 | /** |
| bogdanm | 0:9b334a45a8ff | 717 | * @brief Enable ADC scan mode to convert multiple ranks with sequencer. |
| bogdanm | 0:9b334a45a8ff | 718 | * @param _SCAN_MODE_: Scan conversion mode. |
| bogdanm | 0:9b334a45a8ff | 719 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 720 | */ |
| bogdanm | 0:9b334a45a8ff | 721 | /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ |
| bogdanm | 0:9b334a45a8ff | 722 | /* is equivalent to ADC_SCAN_ENABLE. */ |
| bogdanm | 0:9b334a45a8ff | 723 | #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ |
| bogdanm | 0:9b334a45a8ff | 724 | (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ |
| bogdanm | 0:9b334a45a8ff | 725 | )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ |
| bogdanm | 0:9b334a45a8ff | 726 | ) |
| bogdanm | 0:9b334a45a8ff | 727 | |
| bogdanm | 0:9b334a45a8ff | 728 | /** |
| bogdanm | 0:9b334a45a8ff | 729 | * @brief Get the maximum ADC conversion cycles on all channels. |
| bogdanm | 0:9b334a45a8ff | 730 | * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) |
| bogdanm | 0:9b334a45a8ff | 731 | * Approximation of sampling time within 4 ranges, returns the highest value: |
| bogdanm | 0:9b334a45a8ff | 732 | * below 7.5 cycles {1.5 cycle; 7.5 cycles}, |
| bogdanm | 0:9b334a45a8ff | 733 | * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} |
| bogdanm | 0:9b334a45a8ff | 734 | * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} |
| bogdanm | 0:9b334a45a8ff | 735 | * equal to 239.5 cycles |
| bogdanm | 0:9b334a45a8ff | 736 | * Unit: ADC clock cycles |
| bogdanm | 0:9b334a45a8ff | 737 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 738 | * @retval ADC conversion cycles on all channels |
| bogdanm | 0:9b334a45a8ff | 739 | */ |
| bogdanm | 0:9b334a45a8ff | 740 | #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 741 | (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ |
| bogdanm | 0:9b334a45a8ff | 742 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ |
| bogdanm | 0:9b334a45a8ff | 743 | \ |
| bogdanm | 0:9b334a45a8ff | 744 | (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ |
| bogdanm | 0:9b334a45a8ff | 745 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ |
| bogdanm | 0:9b334a45a8ff | 746 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ |
| bogdanm | 0:9b334a45a8ff | 747 | : \ |
| bogdanm | 0:9b334a45a8ff | 748 | ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ |
| bogdanm | 0:9b334a45a8ff | 749 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ |
| bogdanm | 0:9b334a45a8ff | 750 | ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ |
| bogdanm | 0:9b334a45a8ff | 751 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ |
| bogdanm | 0:9b334a45a8ff | 752 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ |
| bogdanm | 0:9b334a45a8ff | 753 | ) |
| bogdanm | 0:9b334a45a8ff | 754 | |
| bogdanm | 0:9b334a45a8ff | 755 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
| bogdanm | 0:9b334a45a8ff | 756 | ((ALIGN) == ADC_DATAALIGN_LEFT) ) |
| bogdanm | 0:9b334a45a8ff | 757 | |
| bogdanm | 0:9b334a45a8ff | 758 | #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 759 | ((SCAN_MODE) == ADC_SCAN_ENABLE) ) |
| bogdanm | 0:9b334a45a8ff | 760 | |
| bogdanm | 0:9b334a45a8ff | 761 | #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 762 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) |
| bogdanm | 0:9b334a45a8ff | 763 | |
| bogdanm | 0:9b334a45a8ff | 764 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
| bogdanm | 0:9b334a45a8ff | 765 | ((CHANNEL) == ADC_CHANNEL_1) || \ |
| bogdanm | 0:9b334a45a8ff | 766 | ((CHANNEL) == ADC_CHANNEL_2) || \ |
| bogdanm | 0:9b334a45a8ff | 767 | ((CHANNEL) == ADC_CHANNEL_3) || \ |
| bogdanm | 0:9b334a45a8ff | 768 | ((CHANNEL) == ADC_CHANNEL_4) || \ |
| bogdanm | 0:9b334a45a8ff | 769 | ((CHANNEL) == ADC_CHANNEL_5) || \ |
| bogdanm | 0:9b334a45a8ff | 770 | ((CHANNEL) == ADC_CHANNEL_6) || \ |
| bogdanm | 0:9b334a45a8ff | 771 | ((CHANNEL) == ADC_CHANNEL_7) || \ |
| bogdanm | 0:9b334a45a8ff | 772 | ((CHANNEL) == ADC_CHANNEL_8) || \ |
| bogdanm | 0:9b334a45a8ff | 773 | ((CHANNEL) == ADC_CHANNEL_9) || \ |
| bogdanm | 0:9b334a45a8ff | 774 | ((CHANNEL) == ADC_CHANNEL_10) || \ |
| bogdanm | 0:9b334a45a8ff | 775 | ((CHANNEL) == ADC_CHANNEL_11) || \ |
| bogdanm | 0:9b334a45a8ff | 776 | ((CHANNEL) == ADC_CHANNEL_12) || \ |
| bogdanm | 0:9b334a45a8ff | 777 | ((CHANNEL) == ADC_CHANNEL_13) || \ |
| bogdanm | 0:9b334a45a8ff | 778 | ((CHANNEL) == ADC_CHANNEL_14) || \ |
| bogdanm | 0:9b334a45a8ff | 779 | ((CHANNEL) == ADC_CHANNEL_15) || \ |
| bogdanm | 0:9b334a45a8ff | 780 | ((CHANNEL) == ADC_CHANNEL_16) || \ |
| bogdanm | 0:9b334a45a8ff | 781 | ((CHANNEL) == ADC_CHANNEL_17) ) |
| bogdanm | 0:9b334a45a8ff | 782 | |
| bogdanm | 0:9b334a45a8ff | 783 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ |
| bogdanm | 0:9b334a45a8ff | 784 | ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ |
| bogdanm | 0:9b334a45a8ff | 785 | ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ |
| bogdanm | 0:9b334a45a8ff | 786 | ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ |
| bogdanm | 0:9b334a45a8ff | 787 | ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ |
| bogdanm | 0:9b334a45a8ff | 788 | ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ |
| bogdanm | 0:9b334a45a8ff | 789 | ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ |
| bogdanm | 0:9b334a45a8ff | 790 | ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) |
| bogdanm | 0:9b334a45a8ff | 791 | |
| bogdanm | 0:9b334a45a8ff | 792 | #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ |
| bogdanm | 0:9b334a45a8ff | 793 | ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ |
| bogdanm | 0:9b334a45a8ff | 794 | ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ |
| bogdanm | 0:9b334a45a8ff | 795 | ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ |
| bogdanm | 0:9b334a45a8ff | 796 | ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ |
| bogdanm | 0:9b334a45a8ff | 797 | ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ |
| bogdanm | 0:9b334a45a8ff | 798 | ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ |
| bogdanm | 0:9b334a45a8ff | 799 | ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ |
| bogdanm | 0:9b334a45a8ff | 800 | ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ |
| bogdanm | 0:9b334a45a8ff | 801 | ((CHANNEL) == ADC_REGULAR_RANK_10) || \ |
| bogdanm | 0:9b334a45a8ff | 802 | ((CHANNEL) == ADC_REGULAR_RANK_11) || \ |
| bogdanm | 0:9b334a45a8ff | 803 | ((CHANNEL) == ADC_REGULAR_RANK_12) || \ |
| bogdanm | 0:9b334a45a8ff | 804 | ((CHANNEL) == ADC_REGULAR_RANK_13) || \ |
| bogdanm | 0:9b334a45a8ff | 805 | ((CHANNEL) == ADC_REGULAR_RANK_14) || \ |
| bogdanm | 0:9b334a45a8ff | 806 | ((CHANNEL) == ADC_REGULAR_RANK_15) || \ |
| bogdanm | 0:9b334a45a8ff | 807 | ((CHANNEL) == ADC_REGULAR_RANK_16) ) |
| bogdanm | 0:9b334a45a8ff | 808 | |
| bogdanm | 0:9b334a45a8ff | 809 | #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 810 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
| bogdanm | 0:9b334a45a8ff | 811 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ |
| bogdanm | 0:9b334a45a8ff | 812 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ |
| bogdanm | 0:9b334a45a8ff | 813 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ |
| bogdanm | 0:9b334a45a8ff | 814 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ |
| bogdanm | 0:9b334a45a8ff | 815 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) |
| bogdanm | 0:9b334a45a8ff | 816 | |
| bogdanm | 0:9b334a45a8ff | 817 | #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ |
| bogdanm | 0:9b334a45a8ff | 818 | ((CONVERSION) == ADC_INJECTED_GROUP) || \ |
| bogdanm | 0:9b334a45a8ff | 819 | ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) |
| bogdanm | 0:9b334a45a8ff | 820 | |
| bogdanm | 0:9b334a45a8ff | 821 | #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) |
| bogdanm | 0:9b334a45a8ff | 822 | |
| bogdanm | 0:9b334a45a8ff | 823 | |
| bogdanm | 0:9b334a45a8ff | 824 | /** @defgroup ADC_range_verification ADC range verification |
| bogdanm | 0:9b334a45a8ff | 825 | * For a unique ADC resolution: 12 bits |
| bogdanm | 0:9b334a45a8ff | 826 | * @{ |
| bogdanm | 0:9b334a45a8ff | 827 | */ |
| bogdanm | 0:9b334a45a8ff | 828 | #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF)) |
| bogdanm | 0:9b334a45a8ff | 829 | /** |
| bogdanm | 0:9b334a45a8ff | 830 | * @} |
| bogdanm | 0:9b334a45a8ff | 831 | */ |
| bogdanm | 0:9b334a45a8ff | 832 | |
| bogdanm | 0:9b334a45a8ff | 833 | /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification |
| bogdanm | 0:9b334a45a8ff | 834 | * @{ |
| bogdanm | 0:9b334a45a8ff | 835 | */ |
| bogdanm | 0:9b334a45a8ff | 836 | #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) |
| bogdanm | 0:9b334a45a8ff | 837 | /** |
| bogdanm | 0:9b334a45a8ff | 838 | * @} |
| bogdanm | 0:9b334a45a8ff | 839 | */ |
| bogdanm | 0:9b334a45a8ff | 840 | |
| bogdanm | 0:9b334a45a8ff | 841 | /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification |
| bogdanm | 0:9b334a45a8ff | 842 | * @{ |
| bogdanm | 0:9b334a45a8ff | 843 | */ |
| bogdanm | 0:9b334a45a8ff | 844 | #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) |
| bogdanm | 0:9b334a45a8ff | 845 | /** |
| bogdanm | 0:9b334a45a8ff | 846 | * @} |
| mbed_official | 124:6a4a5b7d7324 | 847 | */ |
| bogdanm | 0:9b334a45a8ff | 848 | |
| bogdanm | 0:9b334a45a8ff | 849 | /** |
| bogdanm | 0:9b334a45a8ff | 850 | * @} |
| bogdanm | 0:9b334a45a8ff | 851 | */ |
| bogdanm | 0:9b334a45a8ff | 852 | |
| bogdanm | 0:9b334a45a8ff | 853 | /* Include ADC HAL Extension module */ |
| bogdanm | 0:9b334a45a8ff | 854 | #include "stm32f1xx_hal_adc_ex.h" |
| bogdanm | 0:9b334a45a8ff | 855 | |
| bogdanm | 0:9b334a45a8ff | 856 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 857 | /** @addtogroup ADC_Exported_Functions |
| bogdanm | 0:9b334a45a8ff | 858 | * @{ |
| bogdanm | 0:9b334a45a8ff | 859 | */ |
| bogdanm | 0:9b334a45a8ff | 860 | |
| bogdanm | 0:9b334a45a8ff | 861 | /** @addtogroup ADC_Exported_Functions_Group1 |
| bogdanm | 0:9b334a45a8ff | 862 | * @{ |
| bogdanm | 0:9b334a45a8ff | 863 | */ |
| bogdanm | 0:9b334a45a8ff | 864 | |
| bogdanm | 0:9b334a45a8ff | 865 | |
| bogdanm | 0:9b334a45a8ff | 866 | /* Initialization and de-initialization functions **********************************/ |
| bogdanm | 0:9b334a45a8ff | 867 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 868 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
| bogdanm | 0:9b334a45a8ff | 869 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 870 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 871 | /** |
| bogdanm | 0:9b334a45a8ff | 872 | * @} |
| bogdanm | 0:9b334a45a8ff | 873 | */ |
| bogdanm | 0:9b334a45a8ff | 874 | |
| bogdanm | 0:9b334a45a8ff | 875 | /* IO operation functions *****************************************************/ |
| bogdanm | 0:9b334a45a8ff | 876 | |
| bogdanm | 0:9b334a45a8ff | 877 | /** @addtogroup ADC_Exported_Functions_Group2 |
| bogdanm | 0:9b334a45a8ff | 878 | * @{ |
| bogdanm | 0:9b334a45a8ff | 879 | */ |
| bogdanm | 0:9b334a45a8ff | 880 | |
| bogdanm | 0:9b334a45a8ff | 881 | |
| bogdanm | 0:9b334a45a8ff | 882 | /* Blocking mode: Polling */ |
| bogdanm | 0:9b334a45a8ff | 883 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 884 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 885 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 886 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 887 | |
| bogdanm | 0:9b334a45a8ff | 888 | /* Non-blocking mode: Interruption */ |
| bogdanm | 0:9b334a45a8ff | 889 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 890 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 891 | |
| bogdanm | 0:9b334a45a8ff | 892 | /* Non-blocking mode: DMA */ |
| bogdanm | 0:9b334a45a8ff | 893 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
| bogdanm | 0:9b334a45a8ff | 894 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 895 | |
| bogdanm | 0:9b334a45a8ff | 896 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
| bogdanm | 0:9b334a45a8ff | 897 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 898 | |
| bogdanm | 0:9b334a45a8ff | 899 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ |
| bogdanm | 0:9b334a45a8ff | 900 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 901 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 902 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 903 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 904 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
| bogdanm | 0:9b334a45a8ff | 905 | /** |
| bogdanm | 0:9b334a45a8ff | 906 | * @} |
| bogdanm | 0:9b334a45a8ff | 907 | */ |
| bogdanm | 0:9b334a45a8ff | 908 | |
| bogdanm | 0:9b334a45a8ff | 909 | |
| bogdanm | 0:9b334a45a8ff | 910 | /* Peripheral Control functions ***********************************************/ |
| bogdanm | 0:9b334a45a8ff | 911 | /** @addtogroup ADC_Exported_Functions_Group3 |
| bogdanm | 0:9b334a45a8ff | 912 | * @{ |
| bogdanm | 0:9b334a45a8ff | 913 | */ |
| bogdanm | 0:9b334a45a8ff | 914 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
| bogdanm | 0:9b334a45a8ff | 915 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
| bogdanm | 0:9b334a45a8ff | 916 | /** |
| bogdanm | 0:9b334a45a8ff | 917 | * @} |
| bogdanm | 0:9b334a45a8ff | 918 | */ |
| bogdanm | 0:9b334a45a8ff | 919 | |
| bogdanm | 0:9b334a45a8ff | 920 | |
| bogdanm | 0:9b334a45a8ff | 921 | /* Peripheral State functions *************************************************/ |
| bogdanm | 0:9b334a45a8ff | 922 | /** @addtogroup ADC_Exported_Functions_Group4 |
| bogdanm | 0:9b334a45a8ff | 923 | * @{ |
| bogdanm | 0:9b334a45a8ff | 924 | */ |
| mbed_official | 124:6a4a5b7d7324 | 925 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 926 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
| bogdanm | 0:9b334a45a8ff | 927 | /** |
| bogdanm | 0:9b334a45a8ff | 928 | * @} |
| bogdanm | 0:9b334a45a8ff | 929 | */ |
| bogdanm | 0:9b334a45a8ff | 930 | |
| bogdanm | 0:9b334a45a8ff | 931 | |
| bogdanm | 0:9b334a45a8ff | 932 | /** |
| bogdanm | 0:9b334a45a8ff | 933 | * @} |
| bogdanm | 0:9b334a45a8ff | 934 | */ |
| bogdanm | 0:9b334a45a8ff | 935 | |
| bogdanm | 0:9b334a45a8ff | 936 | |
| bogdanm | 0:9b334a45a8ff | 937 | /* Internal HAL driver functions **********************************************/ |
| bogdanm | 0:9b334a45a8ff | 938 | /** @addtogroup ADC_Private_Functions |
| bogdanm | 0:9b334a45a8ff | 939 | * @{ |
| bogdanm | 0:9b334a45a8ff | 940 | */ |
| bogdanm | 0:9b334a45a8ff | 941 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 942 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 943 | void ADC_StabilizationTime(uint32_t DelayUs); |
| bogdanm | 0:9b334a45a8ff | 944 | void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 945 | void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 946 | void ADC_DMAError(DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 947 | /** |
| bogdanm | 0:9b334a45a8ff | 948 | * @} |
| bogdanm | 0:9b334a45a8ff | 949 | */ |
| bogdanm | 0:9b334a45a8ff | 950 | |
| bogdanm | 0:9b334a45a8ff | 951 | |
| bogdanm | 0:9b334a45a8ff | 952 | /** |
| bogdanm | 0:9b334a45a8ff | 953 | * @} |
| bogdanm | 0:9b334a45a8ff | 954 | */ |
| bogdanm | 0:9b334a45a8ff | 955 | |
| bogdanm | 0:9b334a45a8ff | 956 | /** |
| bogdanm | 0:9b334a45a8ff | 957 | * @} |
| bogdanm | 0:9b334a45a8ff | 958 | */ |
| bogdanm | 0:9b334a45a8ff | 959 | |
| bogdanm | 0:9b334a45a8ff | 960 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 961 | } |
| bogdanm | 0:9b334a45a8ff | 962 | #endif |
| bogdanm | 0:9b334a45a8ff | 963 | |
| bogdanm | 0:9b334a45a8ff | 964 | |
| bogdanm | 0:9b334a45a8ff | 965 | #endif /* __STM32F1xx_HAL_ADC_H */ |
| bogdanm | 0:9b334a45a8ff | 966 | |
| bogdanm | 0:9b334a45a8ff | 967 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |