mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f0xx_hal_rcc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.3.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F0xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F0xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f0xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup RCC
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/** @addtogroup RCC_Private_Constants
bogdanm	0:9b334a45a8ff	58	* @{
bogdanm	0:9b334a45a8ff	59	*/
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	/** @defgroup RCC_Timeout RCC Timeout
bogdanm	0:9b334a45a8ff	62	* @{
bogdanm	0:9b334a45a8ff	63	*/
bogdanm	0:9b334a45a8ff	64
bogdanm	0:9b334a45a8ff	65	/* Disable Backup domain write protection state change timeout */
bogdanm	0:9b334a45a8ff	66	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	67	/* LSE state change timeout */
bogdanm	0:9b334a45a8ff	68	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
bogdanm	0:9b334a45a8ff	69	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm	0:9b334a45a8ff	70	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
bogdanm	0:9b334a45a8ff	71	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	72	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	73	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	74	#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	75	#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	/**
bogdanm	0:9b334a45a8ff	78	* @}
bogdanm	0:9b334a45a8ff	79	*/
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81	/** @defgroup RCC_Register_Offset Register offsets
bogdanm	0:9b334a45a8ff	82	* @{
bogdanm	0:9b334a45a8ff	83	*/
bogdanm	0:9b334a45a8ff	84	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	0:9b334a45a8ff	85	#define RCC_CR_OFFSET 0x00
bogdanm	0:9b334a45a8ff	86	#define RCC_CFGR_OFFSET 0x04
bogdanm	0:9b334a45a8ff	87	#define RCC_CIR_OFFSET 0x08
bogdanm	0:9b334a45a8ff	88	#define RCC_BDCR_OFFSET 0x20
bogdanm	0:9b334a45a8ff	89	#define RCC_CSR_OFFSET 0x24
bogdanm	0:9b334a45a8ff	90
bogdanm	0:9b334a45a8ff	91	/**
bogdanm	0:9b334a45a8ff	92	* @}
bogdanm	0:9b334a45a8ff	93	*/
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	/* CR register byte 2 (Bits[23:16]) base address */
bogdanm	0:9b334a45a8ff	97	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	/* CIR register byte 1 (Bits[15:8]) base address */
bogdanm	0:9b334a45a8ff	100	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102	/* CIR register byte 2 (Bits[23:16]) base address */
bogdanm	0:9b334a45a8ff	103	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105	/* Defines used for Flags */
bogdanm	0:9b334a45a8ff	106	#define CR_REG_INDEX ((uint8_t)1)
bogdanm	0:9b334a45a8ff	107	#define CR2_REG_INDEX 2
bogdanm	0:9b334a45a8ff	108	#define BDCR_REG_INDEX 3
bogdanm	0:9b334a45a8ff	109	#define CSR_REG_INDEX 4
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	/* Flags in the CFGR register */
bogdanm	0:9b334a45a8ff	112	#define RCC_CFGR_PLLMUL_BITNUMBER 18
bogdanm	0:9b334a45a8ff	113	#define RCC_CFGR_HPRE_BITNUMBER 4
bogdanm	0:9b334a45a8ff	114	#define RCC_CFGR_PPRE_BITNUMBER 8
bogdanm	0:9b334a45a8ff	115	/* Flags in the CFGR2 register */
bogdanm	0:9b334a45a8ff	116	#define RCC_CFGR2_PREDIV_BITNUMBER 0
bogdanm	0:9b334a45a8ff	117	/* Flags in the CR register */
bogdanm	0:9b334a45a8ff	118	#define RCC_CR_HSIRDY_BitNumber 1
bogdanm	0:9b334a45a8ff	119	#define RCC_CR_HSERDY_BitNumber 17
bogdanm	0:9b334a45a8ff	120	#define RCC_CR_PLLRDY_BitNumber 25
bogdanm	0:9b334a45a8ff	121	/* Flags in the CR2 register */
bogdanm	0:9b334a45a8ff	122	#define RCC_CR2_HSI14RDY_BitNumber 1
bogdanm	0:9b334a45a8ff	123	#define RCC_CR2_HSI48RDY_BitNumber 16
bogdanm	0:9b334a45a8ff	124	/* Flags in the BDCR register */
bogdanm	0:9b334a45a8ff	125	#define RCC_BDCR_LSERDY_BitNumber 1
bogdanm	0:9b334a45a8ff	126	/* Flags in the CSR register */
bogdanm	0:9b334a45a8ff	127	#define RCC_CSR_LSIRDY_BitNumber 1
bogdanm	0:9b334a45a8ff	128	#define RCC_CSR_V18PWRRSTF_BitNumber 23
bogdanm	0:9b334a45a8ff	129	#define RCC_CSR_RMVF_BitNumber 24
bogdanm	0:9b334a45a8ff	130	#define RCC_CSR_OBLRSTF_BitNumber 25
bogdanm	0:9b334a45a8ff	131	#define RCC_CSR_PINRSTF_BitNumber 26
bogdanm	0:9b334a45a8ff	132	#define RCC_CSR_PORRSTF_BitNumber 27
bogdanm	0:9b334a45a8ff	133	#define RCC_CSR_SFTRSTF_BitNumber 28
bogdanm	0:9b334a45a8ff	134	#define RCC_CSR_IWDGRSTF_BitNumber 29
bogdanm	0:9b334a45a8ff	135	#define RCC_CSR_WWDGRSTF_BitNumber 30
bogdanm	0:9b334a45a8ff	136	#define RCC_CSR_LPWRRSTF_BitNumber 31
bogdanm	0:9b334a45a8ff	137	/* Flags in the HSITRIM register */
bogdanm	0:9b334a45a8ff	138	#define RCC_CR_HSITRIM_BitNumber 3
bogdanm	0:9b334a45a8ff	139	#define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm	0:9b334a45a8ff	140
bogdanm	0:9b334a45a8ff	141	/**
bogdanm	0:9b334a45a8ff	142	* @}
bogdanm	0:9b334a45a8ff	143	*/
bogdanm	0:9b334a45a8ff	144
bogdanm	0:9b334a45a8ff	145	/** @addtogroup RCC_Private_Macros
bogdanm	0:9b334a45a8ff	146	* @{
bogdanm	0:9b334a45a8ff	147	*/
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
bogdanm	0:9b334a45a8ff	150	((__HSE__) == RCC_HSE_BYPASS))
bogdanm	0:9b334a45a8ff	151	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
bogdanm	0:9b334a45a8ff	152	((__LSE__) == RCC_LSE_BYPASS))
bogdanm	0:9b334a45a8ff	153	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
bogdanm	0:9b334a45a8ff	154	#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) \|\| ((__HSI14__) == RCC_HSI14_ON) \|\| ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
bogdanm	0:9b334a45a8ff	155	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
bogdanm	0:9b334a45a8ff	156	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
bogdanm	0:9b334a45a8ff	157	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	158	((__PLL__) == RCC_PLL_ON))
bogdanm	0:9b334a45a8ff	159	#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) \|\| ((__PREDIV__) == RCC_PREDIV_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	160	((__PREDIV__) == RCC_PREDIV_DIV3) \|\| ((__PREDIV__) == RCC_PREDIV_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	161	((__PREDIV__) == RCC_PREDIV_DIV5) \|\| ((__PREDIV__) == RCC_PREDIV_DIV6) \|\| \
bogdanm	0:9b334a45a8ff	162	((__PREDIV__) == RCC_PREDIV_DIV7) \|\| ((__PREDIV__) == RCC_PREDIV_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	163	((__PREDIV__) == RCC_PREDIV_DIV9) \|\| ((__PREDIV__) == RCC_PREDIV_DIV10) \|\| \
bogdanm	0:9b334a45a8ff	164	((__PREDIV__) == RCC_PREDIV_DIV11) \|\| ((__PREDIV__) == RCC_PREDIV_DIV12) \|\| \
bogdanm	0:9b334a45a8ff	165	((__PREDIV__) == RCC_PREDIV_DIV13) \|\| ((__PREDIV__) == RCC_PREDIV_DIV14) \|\| \
bogdanm	0:9b334a45a8ff	166	((__PREDIV__) == RCC_PREDIV_DIV15) \|\| ((__PREDIV__) == RCC_PREDIV_DIV16))
bogdanm	0:9b334a45a8ff	167	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
bogdanm	0:9b334a45a8ff	168	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
bogdanm	0:9b334a45a8ff	169	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
bogdanm	0:9b334a45a8ff	170	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
bogdanm	0:9b334a45a8ff	171	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
bogdanm	0:9b334a45a8ff	172	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
bogdanm	0:9b334a45a8ff	173	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
bogdanm	0:9b334a45a8ff	174	((__MUL__) == RCC_PLL_MUL16))
bogdanm	0:9b334a45a8ff	175	#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	176	(((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
bogdanm	0:9b334a45a8ff	177	(((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
bogdanm	0:9b334a45a8ff	178	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	179	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	180	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	0:9b334a45a8ff	181	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	0:9b334a45a8ff	182	((__HCLK__) == RCC_SYSCLK_DIV512))
bogdanm	0:9b334a45a8ff	183	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	184	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	185	((__PCLK__) == RCC_HCLK_DIV16))
bogdanm	0:9b334a45a8ff	186	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
bogdanm	0:9b334a45a8ff	187	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
bogdanm	0:9b334a45a8ff	188	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	189	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	190	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
bogdanm	0:9b334a45a8ff	191	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	192	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	193	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	194	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	195	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	196	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	/**
bogdanm	0:9b334a45a8ff	199	* @}
bogdanm	0:9b334a45a8ff	200	*/
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	/** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm	0:9b334a45a8ff	205	* @{
bogdanm	0:9b334a45a8ff	206	*/
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	/**
bogdanm	0:9b334a45a8ff	209	* @brief RCC PLL configuration structure definition
bogdanm	0:9b334a45a8ff	210	*/
bogdanm	0:9b334a45a8ff	211	typedef struct
bogdanm	0:9b334a45a8ff	212	{
bogdanm	0:9b334a45a8ff	213	uint32_t PLLState; /*!< The new state of the PLL.
bogdanm	0:9b334a45a8ff	214	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
bogdanm	0:9b334a45a8ff	217	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
bogdanm	0:9b334a45a8ff	220	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
bogdanm	0:9b334a45a8ff	223	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	} RCC_PLLInitTypeDef;
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	/**
bogdanm	0:9b334a45a8ff	228	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	0:9b334a45a8ff	229	*/
bogdanm	0:9b334a45a8ff	230	typedef struct
bogdanm	0:9b334a45a8ff	231	{
bogdanm	0:9b334a45a8ff	232	uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm	0:9b334a45a8ff	233	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	0:9b334a45a8ff	236	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	0:9b334a45a8ff	237
bogdanm	0:9b334a45a8ff	238	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	0:9b334a45a8ff	239	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	0:9b334a45a8ff	240
bogdanm	0:9b334a45a8ff	241	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	0:9b334a45a8ff	242	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	245	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	uint32_t HSI14State; /*!< The new state of the HSI14.
bogdanm	0:9b334a45a8ff	248	This parameter can be a value of @ref RCC_HSI14_Config */
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	251	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	0:9b334a45a8ff	252
bogdanm	0:9b334a45a8ff	253	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
bogdanm	0:9b334a45a8ff	254	This parameter can be a value of @ref RCCEx_HSI48_Config */
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	0:9b334a45a8ff	257	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	} RCC_OscInitTypeDef;
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	/**
bogdanm	0:9b334a45a8ff	265	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	0:9b334a45a8ff	266	*/
bogdanm	0:9b334a45a8ff	267	typedef struct
bogdanm	0:9b334a45a8ff	268	{
bogdanm	0:9b334a45a8ff	269	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	0:9b334a45a8ff	270	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	0:9b334a45a8ff	273	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	0:9b334a45a8ff	276	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	279	This parameter can be a value of @ref RCC_APB1_Clock_Source */
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	} RCC_ClkInitTypeDef;
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283	/**
bogdanm	0:9b334a45a8ff	284	* @}
bogdanm	0:9b334a45a8ff	285	*/
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	288	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	0:9b334a45a8ff	289	* @{
bogdanm	0:9b334a45a8ff	290	*/
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm	0:9b334a45a8ff	293	* @{
bogdanm	0:9b334a45a8ff	294	*/
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /!< HSE clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/**
bogdanm	0:9b334a45a8ff	299	* @}
bogdanm	0:9b334a45a8ff	300	*/
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm	0:9b334a45a8ff	303	* @{
bogdanm	0:9b334a45a8ff	304	*/
bogdanm	0:9b334a45a8ff	305	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	306	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	307	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	308	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	309	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	310	#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	311	/**
bogdanm	0:9b334a45a8ff	312	* @}
bogdanm	0:9b334a45a8ff	313	*/
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/** @defgroup RCC_HSE_Config HSE Config
bogdanm	0:9b334a45a8ff	316	* @{
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
bogdanm	0:9b334a45a8ff	319	#define RCC_HSE_ON ((uint32_t)0x00000001) /!< HSE clock activation /
bogdanm	0:9b334a45a8ff	320	#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for HSE clock /
bogdanm	0:9b334a45a8ff	321	/**
bogdanm	0:9b334a45a8ff	322	* @}
bogdanm	0:9b334a45a8ff	323	*/
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	/** @defgroup RCC_LSE_Config LSE Config
bogdanm	0:9b334a45a8ff	326	* @{
bogdanm	0:9b334a45a8ff	327	*/
bogdanm	0:9b334a45a8ff	328	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
bogdanm	0:9b334a45a8ff	329	#define RCC_LSE_ON ((uint32_t)0x00000001) /!< LSE clock activation /
bogdanm	0:9b334a45a8ff	330	#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for LSE clock /
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/**
bogdanm	0:9b334a45a8ff	333	* @}
bogdanm	0:9b334a45a8ff	334	*/
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/** @defgroup RCC_HSI_Config HSI Config
bogdanm	0:9b334a45a8ff	337	* @{
bogdanm	0:9b334a45a8ff	338	*/
bogdanm	0:9b334a45a8ff	339	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
bogdanm	0:9b334a45a8ff	340	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/**
bogdanm	0:9b334a45a8ff	345	* @}
bogdanm	0:9b334a45a8ff	346	*/
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/** @defgroup RCC_HSI14_Config RCC HSI14 Config
bogdanm	0:9b334a45a8ff	349	* @{
bogdanm	0:9b334a45a8ff	350	*/
bogdanm	0:9b334a45a8ff	351	#define RCC_HSI14_OFF ((uint32_t)0x00)
bogdanm	0:9b334a45a8ff	352	#define RCC_HSI14_ON RCC_CR2_HSI14ON
bogdanm	0:9b334a45a8ff	353	#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
bogdanm	0:9b334a45a8ff	356	/**
bogdanm	0:9b334a45a8ff	357	* @}
bogdanm	0:9b334a45a8ff	358	*/
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360
bogdanm	0:9b334a45a8ff	361	/** @defgroup RCC_LSI_Config LSI Config
bogdanm	0:9b334a45a8ff	362	* @{
bogdanm	0:9b334a45a8ff	363	*/
bogdanm	0:9b334a45a8ff	364	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
bogdanm	0:9b334a45a8ff	365	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367	/**
bogdanm	0:9b334a45a8ff	368	* @}
bogdanm	0:9b334a45a8ff	369	*/
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	/** @defgroup RCC_PLL_Config PLL Config
bogdanm	0:9b334a45a8ff	372	* @{
bogdanm	0:9b334a45a8ff	373	*/
bogdanm	0:9b334a45a8ff	374	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
bogdanm	0:9b334a45a8ff	375	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
bogdanm	0:9b334a45a8ff	376	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
bogdanm	0:9b334a45a8ff	377
bogdanm	0:9b334a45a8ff	378	/**
bogdanm	0:9b334a45a8ff	379	* @}
bogdanm	0:9b334a45a8ff	380	*/
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/** @defgroup RCC_System_Clock_Type System Clock Type
bogdanm	0:9b334a45a8ff	383	* @{
bogdanm	0:9b334a45a8ff	384	*/
bogdanm	0:9b334a45a8ff	385	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
bogdanm	0:9b334a45a8ff	386	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
bogdanm	0:9b334a45a8ff	387	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	/**
bogdanm	0:9b334a45a8ff	390	* @}
bogdanm	0:9b334a45a8ff	391	*/
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	/** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm	0:9b334a45a8ff	394	* @{
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396	#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) /!< HSI selected as system clock /
bogdanm	0:9b334a45a8ff	397	#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) /!< HSE selected as system clock /
bogdanm	0:9b334a45a8ff	398	#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) /!< PLL selected as system clock /
bogdanm	0:9b334a45a8ff	399
bogdanm	0:9b334a45a8ff	400	/**
bogdanm	0:9b334a45a8ff	401	* @}
bogdanm	0:9b334a45a8ff	402	*/
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
bogdanm	0:9b334a45a8ff	405	* @{
bogdanm	0:9b334a45a8ff	406	*/
bogdanm	0:9b334a45a8ff	407	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
bogdanm	0:9b334a45a8ff	408	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
bogdanm	0:9b334a45a8ff	409	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	/**
bogdanm	0:9b334a45a8ff	412	* @}
bogdanm	0:9b334a45a8ff	413	*/
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
bogdanm	0:9b334a45a8ff	416	* @{
bogdanm	0:9b334a45a8ff	417	*/
bogdanm	0:9b334a45a8ff	418	#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
bogdanm	0:9b334a45a8ff	419	#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
bogdanm	0:9b334a45a8ff	420	#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
bogdanm	0:9b334a45a8ff	421	#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
bogdanm	0:9b334a45a8ff	422	#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
bogdanm	0:9b334a45a8ff	423	#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
bogdanm	0:9b334a45a8ff	424	#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
bogdanm	0:9b334a45a8ff	425	#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
bogdanm	0:9b334a45a8ff	426	#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	/**
bogdanm	0:9b334a45a8ff	429	* @}
bogdanm	0:9b334a45a8ff	430	*/
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
bogdanm	0:9b334a45a8ff	433	* @{
bogdanm	0:9b334a45a8ff	434	*/
bogdanm	0:9b334a45a8ff	435	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
bogdanm	0:9b334a45a8ff	436	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
bogdanm	0:9b334a45a8ff	437	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
bogdanm	0:9b334a45a8ff	438	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
bogdanm	0:9b334a45a8ff	439	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	/**
bogdanm	0:9b334a45a8ff	442	* @}
bogdanm	0:9b334a45a8ff	443	*/
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
bogdanm	0:9b334a45a8ff	446	* @{
bogdanm	0:9b334a45a8ff	447	*/
bogdanm	0:9b334a45a8ff	448	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /!< No clock /
bogdanm	0:9b334a45a8ff	449	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_BDCR_RTCSEL_LSE) /!< LSE oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	450	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_BDCR_RTCSEL_LSI) /!< LSI oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	451	#define RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)RCC_BDCR_RTCSEL_HSE) /!< HSE oscillator clock divided by 32 used as RTC clock /
bogdanm	0:9b334a45a8ff	452	/**
bogdanm	0:9b334a45a8ff	453	* @}
bogdanm	0:9b334a45a8ff	454	*/
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
bogdanm	0:9b334a45a8ff	457	* @{
bogdanm	0:9b334a45a8ff	458	*/
bogdanm	0:9b334a45a8ff	459	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
bogdanm	0:9b334a45a8ff	460	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
bogdanm	0:9b334a45a8ff	461	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
bogdanm	0:9b334a45a8ff	462	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
bogdanm	0:9b334a45a8ff	463	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
bogdanm	0:9b334a45a8ff	464	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
bogdanm	0:9b334a45a8ff	465	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
bogdanm	0:9b334a45a8ff	466	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
bogdanm	0:9b334a45a8ff	467	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
bogdanm	0:9b334a45a8ff	468	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
bogdanm	0:9b334a45a8ff	469	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
bogdanm	0:9b334a45a8ff	470	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
bogdanm	0:9b334a45a8ff	471	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
bogdanm	0:9b334a45a8ff	472	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
bogdanm	0:9b334a45a8ff	473	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
bogdanm	0:9b334a45a8ff	474	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
bogdanm	0:9b334a45a8ff	475
bogdanm	0:9b334a45a8ff	476	/**
bogdanm	0:9b334a45a8ff	477	* @}
bogdanm	0:9b334a45a8ff	478	*/
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
bogdanm	0:9b334a45a8ff	481	* @{
bogdanm	0:9b334a45a8ff	482	*/
bogdanm	0:9b334a45a8ff	483	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
bogdanm	0:9b334a45a8ff	484	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
bogdanm	0:9b334a45a8ff	485	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
bogdanm	0:9b334a45a8ff	486	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
bogdanm	0:9b334a45a8ff	487	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
bogdanm	0:9b334a45a8ff	488	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
bogdanm	0:9b334a45a8ff	489	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
bogdanm	0:9b334a45a8ff	490	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
bogdanm	0:9b334a45a8ff	491	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
bogdanm	0:9b334a45a8ff	492	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
bogdanm	0:9b334a45a8ff	493	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
bogdanm	0:9b334a45a8ff	494	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
bogdanm	0:9b334a45a8ff	495	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
bogdanm	0:9b334a45a8ff	496	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
bogdanm	0:9b334a45a8ff	497	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/**
bogdanm	0:9b334a45a8ff	500	* @}
bogdanm	0:9b334a45a8ff	501	*/
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
bogdanm	0:9b334a45a8ff	504	* @{
bogdanm	0:9b334a45a8ff	505	*/
bogdanm	0:9b334a45a8ff	506	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
bogdanm	0:9b334a45a8ff	507	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm	0:9b334a45a8ff	508	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm	0:9b334a45a8ff	509	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/**
bogdanm	0:9b334a45a8ff	512	* @}
bogdanm	0:9b334a45a8ff	513	*/
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
bogdanm	0:9b334a45a8ff	516	* @{
bogdanm	0:9b334a45a8ff	517	*/
bogdanm	0:9b334a45a8ff	518	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
bogdanm	0:9b334a45a8ff	519	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/**
bogdanm	0:9b334a45a8ff	522	* @}
bogdanm	0:9b334a45a8ff	523	*/
bogdanm	0:9b334a45a8ff	524	/** @defgroup RCC_MCO_Index MCO Index
bogdanm	0:9b334a45a8ff	525	* @{
bogdanm	0:9b334a45a8ff	526	*/
bogdanm	0:9b334a45a8ff	527	#define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	528	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/**
bogdanm	0:9b334a45a8ff	531	* @}
bogdanm	0:9b334a45a8ff	532	*/
bogdanm	0:9b334a45a8ff	533
bogdanm	0:9b334a45a8ff	534	/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
bogdanm	0:9b334a45a8ff	535	* @{
bogdanm	0:9b334a45a8ff	536	*/
bogdanm	0:9b334a45a8ff	537	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
bogdanm	0:9b334a45a8ff	538	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
bogdanm	0:9b334a45a8ff	539	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
bogdanm	0:9b334a45a8ff	540	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
bogdanm	0:9b334a45a8ff	541	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
bogdanm	0:9b334a45a8ff	542	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
bogdanm	0:9b334a45a8ff	543	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
bogdanm	0:9b334a45a8ff	544	#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	/**
bogdanm	0:9b334a45a8ff	547	* @}
bogdanm	0:9b334a45a8ff	548	*/
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	/** @defgroup RCC_Interrupt Interrupts
bogdanm	0:9b334a45a8ff	551	* @{
bogdanm	0:9b334a45a8ff	552	*/
bogdanm	0:9b334a45a8ff	553	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	554	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	555	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	556	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	557	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	558	#define RCC_IT_HSI14 ((uint8_t)RCC_CIR_HSI14RDYF) /!< HSI14 Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	559	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	560	/**
bogdanm	0:9b334a45a8ff	561	* @}
bogdanm	0:9b334a45a8ff	562	*/
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564	/** @defgroup RCC_Flag Flags
bogdanm	0:9b334a45a8ff	565	* Elements values convention: XXXYYYYYb
bogdanm	0:9b334a45a8ff	566	* - YYYYY : Flag position in the register
bogdanm	0:9b334a45a8ff	567	* - XXX : Register index
bogdanm	0:9b334a45a8ff	568	* - 001: CR register
bogdanm	0:9b334a45a8ff	569	* - 010: CR2 register
bogdanm	0:9b334a45a8ff	570	* - 011: BDCR register
bogdanm	0:9b334a45a8ff	571	* - 0100: CSR register
bogdanm	0:9b334a45a8ff	572	* @{
bogdanm	0:9b334a45a8ff	573	*/
bogdanm	0:9b334a45a8ff	574	/* Flags in the CR register */
bogdanm	0:9b334a45a8ff	575	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSIRDY_BitNumber))
bogdanm	0:9b334a45a8ff	576	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSERDY_BitNumber))
bogdanm	0:9b334a45a8ff	577	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_PLLRDY_BitNumber))
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	/* Flags in the CR2 register */
bogdanm	0:9b334a45a8ff	580	#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI14RDY_BitNumber))
bogdanm	0:9b334a45a8ff	581
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	/* Flags in the CSR register */
bogdanm	0:9b334a45a8ff	584	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
bogdanm	0:9b334a45a8ff	585	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
bogdanm	0:9b334a45a8ff	586	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_RMVF_BitNumber))
bogdanm	0:9b334a45a8ff	587	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_OBLRSTF_BitNumber))
bogdanm	0:9b334a45a8ff	588	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PINRSTF_BitNumber))
bogdanm	0:9b334a45a8ff	589	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PORRSTF_BitNumber))
bogdanm	0:9b334a45a8ff	590	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_SFTRSTF_BitNumber))
bogdanm	0:9b334a45a8ff	591	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_IWDGRSTF_BitNumber))
bogdanm	0:9b334a45a8ff	592	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_WWDGRSTF_BitNumber))
bogdanm	0:9b334a45a8ff	593	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LPWRRSTF_BitNumber))
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	/* Flags in the BDCR register */
bogdanm	0:9b334a45a8ff	596	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| RCC_BDCR_LSERDY_BitNumber))
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	/**
bogdanm	0:9b334a45a8ff	599	* @}
bogdanm	0:9b334a45a8ff	600	*/
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/**
bogdanm	0:9b334a45a8ff	603	* @}
bogdanm	0:9b334a45a8ff	604	*/
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	607
bogdanm	0:9b334a45a8ff	608	/** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm	0:9b334a45a8ff	609	* @{
bogdanm	0:9b334a45a8ff	610	*/
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
bogdanm	0:9b334a45a8ff	613	* @brief Enable or disable the AHB peripheral clock.
bogdanm	0:9b334a45a8ff	614	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	615	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	616	* using it.
bogdanm	0:9b334a45a8ff	617	* @{
bogdanm	0:9b334a45a8ff	618	*/
bogdanm	0:9b334a45a8ff	619	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	620	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	621	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
bogdanm	0:9b334a45a8ff	622	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	623	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
bogdanm	0:9b334a45a8ff	624	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	625	} while(0)
bogdanm	0:9b334a45a8ff	626	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	627	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	628	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
bogdanm	0:9b334a45a8ff	629	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	630	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
bogdanm	0:9b334a45a8ff	631	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	632	} while(0)
bogdanm	0:9b334a45a8ff	633	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	634	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	635	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
bogdanm	0:9b334a45a8ff	636	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	637	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
bogdanm	0:9b334a45a8ff	638	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	639	} while(0)
bogdanm	0:9b334a45a8ff	640	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	641	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	642	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	643	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	644	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	645	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	646	} while(0)
bogdanm	0:9b334a45a8ff	647	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	648	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	649	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	650	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	651	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	652	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	653	} while(0)
bogdanm	0:9b334a45a8ff	654	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	655	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	656	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	657	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	658	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	659	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	660	} while(0)
bogdanm	0:9b334a45a8ff	661	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	662	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	663	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
bogdanm	0:9b334a45a8ff	664	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	665	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
bogdanm	0:9b334a45a8ff	666	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	667	} while(0)
bogdanm	0:9b334a45a8ff	668	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	669	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	670	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
bogdanm	0:9b334a45a8ff	671	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	672	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
bogdanm	0:9b334a45a8ff	673	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	674	} while(0)
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
bogdanm	0:9b334a45a8ff	677	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
bogdanm	0:9b334a45a8ff	678	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
bogdanm	0:9b334a45a8ff	679	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
bogdanm	0:9b334a45a8ff	680	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
bogdanm	0:9b334a45a8ff	681	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
bogdanm	0:9b334a45a8ff	682	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
bogdanm	0:9b334a45a8ff	683	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm	0:9b334a45a8ff	684	/**
bogdanm	0:9b334a45a8ff	685	* @}
bogdanm	0:9b334a45a8ff	686	*/
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	689	* @brief Get the enable or disable status of the AHB peripheral clock.
bogdanm	0:9b334a45a8ff	690	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	691	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	692	* using it.
bogdanm	0:9b334a45a8ff	693	* @{
bogdanm	0:9b334a45a8ff	694	*/
bogdanm	0:9b334a45a8ff	695	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
bogdanm	0:9b334a45a8ff	696	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
bogdanm	0:9b334a45a8ff	697	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
bogdanm	0:9b334a45a8ff	698	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
bogdanm	0:9b334a45a8ff	699	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
bogdanm	0:9b334a45a8ff	700	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
bogdanm	0:9b334a45a8ff	701	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
bogdanm	0:9b334a45a8ff	702	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
bogdanm	0:9b334a45a8ff	703	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
bogdanm	0:9b334a45a8ff	704	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
bogdanm	0:9b334a45a8ff	705	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
bogdanm	0:9b334a45a8ff	706	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
bogdanm	0:9b334a45a8ff	707	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
bogdanm	0:9b334a45a8ff	708	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
bogdanm	0:9b334a45a8ff	709	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
bogdanm	0:9b334a45a8ff	710	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
bogdanm	0:9b334a45a8ff	711	/**
bogdanm	0:9b334a45a8ff	712	* @}
bogdanm	0:9b334a45a8ff	713	*/
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
bogdanm	0:9b334a45a8ff	716	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	717	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	718	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	719	* using it.
bogdanm	0:9b334a45a8ff	720	* @{
bogdanm	0:9b334a45a8ff	721	*/
bogdanm	0:9b334a45a8ff	722	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	723	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	724	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm	0:9b334a45a8ff	725	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	726	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm	0:9b334a45a8ff	727	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	728	} while(0)
bogdanm	0:9b334a45a8ff	729	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	730	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	731	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	732	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	733	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	734	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	735	} while(0)
bogdanm	0:9b334a45a8ff	736	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	737	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	738	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm	0:9b334a45a8ff	739	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	740	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm	0:9b334a45a8ff	741	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	742	} while(0)
bogdanm	0:9b334a45a8ff	743	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	744	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	745	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm	0:9b334a45a8ff	746	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	747	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm	0:9b334a45a8ff	748	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	749	} while(0)
bogdanm	0:9b334a45a8ff	750	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	751	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	752	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm	0:9b334a45a8ff	753	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	754	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm	0:9b334a45a8ff	755	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	756	} while(0)
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	0:9b334a45a8ff	759	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	0:9b334a45a8ff	760	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	0:9b334a45a8ff	761	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	762	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm	0:9b334a45a8ff	763	/**
bogdanm	0:9b334a45a8ff	764	* @}
bogdanm	0:9b334a45a8ff	765	*/
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	768	* @brief Get the enable or disable status of the APB1 peripheral clock.
bogdanm	0:9b334a45a8ff	769	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	770	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	771	* using it.
bogdanm	0:9b334a45a8ff	772	* @{
bogdanm	0:9b334a45a8ff	773	*/
bogdanm	0:9b334a45a8ff	774	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
bogdanm	0:9b334a45a8ff	775	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
bogdanm	0:9b334a45a8ff	776	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
bogdanm	0:9b334a45a8ff	777	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
bogdanm	0:9b334a45a8ff	778	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
bogdanm	0:9b334a45a8ff	779	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
bogdanm	0:9b334a45a8ff	780	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
bogdanm	0:9b334a45a8ff	781	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
bogdanm	0:9b334a45a8ff	782	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
bogdanm	0:9b334a45a8ff	783	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
bogdanm	0:9b334a45a8ff	784	/**
bogdanm	0:9b334a45a8ff	785	* @}
bogdanm	0:9b334a45a8ff	786	*/
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788
bogdanm	0:9b334a45a8ff	789	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
bogdanm	0:9b334a45a8ff	790	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	791	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	792	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	793	* using it.
bogdanm	0:9b334a45a8ff	794	* @{
bogdanm	0:9b334a45a8ff	795	*/
bogdanm	0:9b334a45a8ff	796	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	797	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	798	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
bogdanm	0:9b334a45a8ff	799	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	800	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
bogdanm	0:9b334a45a8ff	801	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	802	} while(0)
bogdanm	0:9b334a45a8ff	803	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	804	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	805	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm	0:9b334a45a8ff	806	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	807	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm	0:9b334a45a8ff	808	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	809	} while(0)
bogdanm	0:9b334a45a8ff	810	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	811	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	812	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm	0:9b334a45a8ff	813	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	814	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm	0:9b334a45a8ff	815	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	816	} while(0)
bogdanm	0:9b334a45a8ff	817	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	818	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	819	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm	0:9b334a45a8ff	820	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	821	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm	0:9b334a45a8ff	822	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	823	} while(0)
bogdanm	0:9b334a45a8ff	824	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	825	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	826	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
bogdanm	0:9b334a45a8ff	827	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	828	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
bogdanm	0:9b334a45a8ff	829	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	830	} while(0)
bogdanm	0:9b334a45a8ff	831	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	832	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	833	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
bogdanm	0:9b334a45a8ff	834	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	835	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
bogdanm	0:9b334a45a8ff	836	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	837	} while(0)
bogdanm	0:9b334a45a8ff	838	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	839	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	840	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm	0:9b334a45a8ff	841	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	842	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm	0:9b334a45a8ff	843	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	844	} while(0)
bogdanm	0:9b334a45a8ff	845	#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	846	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	847	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
bogdanm	0:9b334a45a8ff	848	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	849	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
bogdanm	0:9b334a45a8ff	850	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	851	} while(0)
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm	0:9b334a45a8ff	854	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm	0:9b334a45a8ff	855	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm	0:9b334a45a8ff	856	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	0:9b334a45a8ff	857	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
bogdanm	0:9b334a45a8ff	858	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
bogdanm	0:9b334a45a8ff	859	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm	0:9b334a45a8ff	860	#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
bogdanm	0:9b334a45a8ff	861	/**
bogdanm	0:9b334a45a8ff	862	* @}
bogdanm	0:9b334a45a8ff	863	*/
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	866	* @brief Get the enable or disable status of the APB2 peripheral clock.
bogdanm	0:9b334a45a8ff	867	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	868	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	869	* using it.
bogdanm	0:9b334a45a8ff	870	* @{
bogdanm	0:9b334a45a8ff	871	*/
bogdanm	0:9b334a45a8ff	872	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
bogdanm	0:9b334a45a8ff	873	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
bogdanm	0:9b334a45a8ff	874	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
bogdanm	0:9b334a45a8ff	875	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
bogdanm	0:9b334a45a8ff	876	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
bogdanm	0:9b334a45a8ff	877	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
bogdanm	0:9b334a45a8ff	878	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
bogdanm	0:9b334a45a8ff	879	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
bogdanm	0:9b334a45a8ff	880	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
bogdanm	0:9b334a45a8ff	881	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
bogdanm	0:9b334a45a8ff	882	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
bogdanm	0:9b334a45a8ff	883	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
bogdanm	0:9b334a45a8ff	884	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
bogdanm	0:9b334a45a8ff	885	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
bogdanm	0:9b334a45a8ff	886	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
bogdanm	0:9b334a45a8ff	887	#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
bogdanm	0:9b334a45a8ff	888	/**
bogdanm	0:9b334a45a8ff	889	* @}
bogdanm	0:9b334a45a8ff	890	*/
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
bogdanm	0:9b334a45a8ff	893	* @brief Force or release AHB peripheral reset.
bogdanm	0:9b334a45a8ff	894	* @{
bogdanm	0:9b334a45a8ff	895	*/
bogdanm	0:9b334a45a8ff	896	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	897	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
bogdanm	0:9b334a45a8ff	898	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
bogdanm	0:9b334a45a8ff	899	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
bogdanm	0:9b334a45a8ff	900	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
bogdanm	0:9b334a45a8ff	903	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
bogdanm	0:9b334a45a8ff	904	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
bogdanm	0:9b334a45a8ff	905	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
bogdanm	0:9b334a45a8ff	906	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	907	/**
bogdanm	0:9b334a45a8ff	908	* @}
bogdanm	0:9b334a45a8ff	909	*/
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
bogdanm	0:9b334a45a8ff	912	* @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	913	* @{
bogdanm	0:9b334a45a8ff	914	*/
bogdanm	0:9b334a45a8ff	915	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	916	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	917	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	918	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
bogdanm	0:9b334a45a8ff	919	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	920	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	921
bogdanm	0:9b334a45a8ff	922	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm	0:9b334a45a8ff	923	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	924	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	925	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm	0:9b334a45a8ff	926	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	927	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	928	/**
bogdanm	0:9b334a45a8ff	929	* @}
bogdanm	0:9b334a45a8ff	930	*/
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
bogdanm	0:9b334a45a8ff	933	* @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	934	* @{
bogdanm	0:9b334a45a8ff	935	*/
bogdanm	0:9b334a45a8ff	936	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	937	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
bogdanm	0:9b334a45a8ff	938	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
bogdanm	0:9b334a45a8ff	939	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
bogdanm	0:9b334a45a8ff	940	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	941	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	942	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
bogdanm	0:9b334a45a8ff	943	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
bogdanm	0:9b334a45a8ff	944	#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm	0:9b334a45a8ff	947	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm	0:9b334a45a8ff	948	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
bogdanm	0:9b334a45a8ff	949	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm	0:9b334a45a8ff	950	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	951	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	952	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
bogdanm	0:9b334a45a8ff	953	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
bogdanm	0:9b334a45a8ff	954	#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
bogdanm	0:9b334a45a8ff	955	/**
bogdanm	0:9b334a45a8ff	956	* @}
bogdanm	0:9b334a45a8ff	957	*/
bogdanm	0:9b334a45a8ff	958	/** @defgroup RCC_HSI_Configuration HSI Configuration
bogdanm	0:9b334a45a8ff	959	* @{
bogdanm	0:9b334a45a8ff	960	*/
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	0:9b334a45a8ff	963	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	964	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	0:9b334a45a8ff	965	* you have to select another source of the system clock then stop the HSI.
bogdanm	0:9b334a45a8ff	966	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	0:9b334a45a8ff	967	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	0:9b334a45a8ff	968	* system clock source.
bogdanm	0:9b334a45a8ff	969	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	0:9b334a45a8ff	970	* clock cycles.
bogdanm	0:9b334a45a8ff	971	*/
bogdanm	0:9b334a45a8ff	972	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	973	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	0:9b334a45a8ff	976	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	977	* and temperature that influence the frequency of the internal HSI RC.
bogdanm	0:9b334a45a8ff	978	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
bogdanm	0:9b334a45a8ff	979	* (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	980	* This parameter must be a number between 0 and 0x1F.
bogdanm	0:9b334a45a8ff	981	*/
bogdanm	0:9b334a45a8ff	982	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
bogdanm	0:9b334a45a8ff	983	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	/**
bogdanm	0:9b334a45a8ff	986	* @}
bogdanm	0:9b334a45a8ff	987	*/
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	/** @defgroup RCC_LSI_Configuration LSI Configuration
bogdanm	0:9b334a45a8ff	990	* @{
bogdanm	0:9b334a45a8ff	991	*/
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	0:9b334a45a8ff	994	* @note After enabling the LSI, the application software should wait on
bogdanm	0:9b334a45a8ff	995	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	0:9b334a45a8ff	996	* be used to clock the IWDG and/or the RTC.
bogdanm	0:9b334a45a8ff	997	* @note LSI can not be disabled if the IWDG is running.
bogdanm	0:9b334a45a8ff	998	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	0:9b334a45a8ff	999	* clock cycles.
bogdanm	0:9b334a45a8ff	1000	*/
bogdanm	0:9b334a45a8ff	1001	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	1002	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	/**
bogdanm	0:9b334a45a8ff	1005	* @}
bogdanm	0:9b334a45a8ff	1006	*/
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/** @defgroup RCC_HSE_Configuration HSE Configuration
bogdanm	0:9b334a45a8ff	1009	* @{
bogdanm	0:9b334a45a8ff	1010	*/
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/**
bogdanm	0:9b334a45a8ff	1013	* @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm	0:9b334a45a8ff	1014	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
bogdanm	0:9b334a45a8ff	1015	* supported by this macro. User should request a transition to HSE Off
bogdanm	0:9b334a45a8ff	1016	* first and then HSE On or HSE Bypass.
bogdanm	0:9b334a45a8ff	1017	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	0:9b334a45a8ff	1018	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	0:9b334a45a8ff	1019	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	0:9b334a45a8ff	1020	* @note HSE state can not be changed if it is used directly or through the
bogdanm	0:9b334a45a8ff	1021	* PLL as system clock. In this case, you have to select another source
bogdanm	0:9b334a45a8ff	1022	* of the system clock then change the HSE state (ex. disable it).
bogdanm	0:9b334a45a8ff	1023	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1024	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
bogdanm	0:9b334a45a8ff	1025	* was previously enabled you have to enable it again after calling this
bogdanm	0:9b334a45a8ff	1026	* function.
bogdanm	0:9b334a45a8ff	1027	* @param __STATE__: specifies the new state of the HSE.
bogdanm	0:9b334a45a8ff	1028	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1029	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	0:9b334a45a8ff	1030	* 6 HSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	1031	* @arg RCC_HSE_ON: turn ON the HSE oscillator
bogdanm	0:9b334a45a8ff	1032	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
bogdanm	0:9b334a45a8ff	1033	*/
bogdanm	0:9b334a45a8ff	1034	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	1035	do{ \
bogdanm	0:9b334a45a8ff	1036	if ((__STATE__) == RCC_HSE_ON) \
bogdanm	0:9b334a45a8ff	1037	{ \
bogdanm	0:9b334a45a8ff	1038	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	1039	} \
bogdanm	0:9b334a45a8ff	1040	else if ((__STATE__) == RCC_HSE_OFF) \
bogdanm	0:9b334a45a8ff	1041	{ \
bogdanm	0:9b334a45a8ff	1042	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	1043	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	1044	} \
bogdanm	0:9b334a45a8ff	1045	else if ((__STATE__) == RCC_HSE_BYPASS) \
bogdanm	0:9b334a45a8ff	1046	{ \
bogdanm	0:9b334a45a8ff	1047	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	1048	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	1049	} \
bogdanm	0:9b334a45a8ff	1050	else \
bogdanm	0:9b334a45a8ff	1051	{ \
bogdanm	0:9b334a45a8ff	1052	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	1053	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	1054	} \
bogdanm	0:9b334a45a8ff	1055	}while(0)
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/**
bogdanm	0:9b334a45a8ff	1058	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
bogdanm	0:9b334a45a8ff	1059	* @note Predivision factor can not be changed if PLL is used as system clock
bogdanm	0:9b334a45a8ff	1060	* In this case, you have to select another source of the system clock, disable the PLL and
bogdanm	0:9b334a45a8ff	1061	* then change the HSE predivision factor.
bogdanm	0:9b334a45a8ff	1062	* @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
bogdanm	0:9b334a45a8ff	1063	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
bogdanm	0:9b334a45a8ff	1064	*/
bogdanm	0:9b334a45a8ff	1065	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
bogdanm	0:9b334a45a8ff	1066	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
bogdanm	0:9b334a45a8ff	1067
bogdanm	0:9b334a45a8ff	1068	/**
bogdanm	0:9b334a45a8ff	1069	* @}
bogdanm	0:9b334a45a8ff	1070	*/
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	/** @defgroup RCC_LSE_Configuration LSE Configuration
bogdanm	0:9b334a45a8ff	1073	* @{
bogdanm	0:9b334a45a8ff	1074	*/
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/**
bogdanm	0:9b334a45a8ff	1077	* @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm	0:9b334a45a8ff	1078	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
bogdanm	0:9b334a45a8ff	1079	* @note As the LSE is in the Backup domain and write access is denied to
bogdanm	0:9b334a45a8ff	1080	* this domain after reset, you have to enable write access using
bogdanm	0:9b334a45a8ff	1081	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm	0:9b334a45a8ff	1082	* (to be done once after reset).
bogdanm	0:9b334a45a8ff	1083	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	0:9b334a45a8ff	1084	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	0:9b334a45a8ff	1085	* is stable and can be used to clock the RTC.
bogdanm	0:9b334a45a8ff	1086	* @param __STATE__: specifies the new state of the LSE.
bogdanm	0:9b334a45a8ff	1087	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1088	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	0:9b334a45a8ff	1089	* 6 LSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	1090	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm	0:9b334a45a8ff	1091	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm	0:9b334a45a8ff	1092	*/
bogdanm	0:9b334a45a8ff	1093	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	1094	do{ \
bogdanm	0:9b334a45a8ff	1095	if ((__STATE__) == RCC_LSE_ON) \
bogdanm	0:9b334a45a8ff	1096	{ \
bogdanm	0:9b334a45a8ff	1097	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	1098	} \
bogdanm	0:9b334a45a8ff	1099	else if ((__STATE__) == RCC_LSE_OFF) \
bogdanm	0:9b334a45a8ff	1100	{ \
bogdanm	0:9b334a45a8ff	1101	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	1102	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm	0:9b334a45a8ff	1103	} \
bogdanm	0:9b334a45a8ff	1104	else if ((__STATE__) == RCC_LSE_BYPASS) \
bogdanm	0:9b334a45a8ff	1105	{ \
bogdanm	0:9b334a45a8ff	1106	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm	0:9b334a45a8ff	1107	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	1108	} \
bogdanm	0:9b334a45a8ff	1109	else \
bogdanm	0:9b334a45a8ff	1110	{ \
bogdanm	0:9b334a45a8ff	1111	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm	0:9b334a45a8ff	1112	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm	0:9b334a45a8ff	1113	} \
bogdanm	0:9b334a45a8ff	1114	}while(0)
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	/**
bogdanm	0:9b334a45a8ff	1117	* @}
bogdanm	0:9b334a45a8ff	1118	*/
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
bogdanm	0:9b334a45a8ff	1121	* @{
bogdanm	0:9b334a45a8ff	1122	*/
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	/** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
bogdanm	0:9b334a45a8ff	1125	* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1126	* @note HSI14 can not be stopped if it is used as system clock source. In this case,
bogdanm	0:9b334a45a8ff	1127	* you have to select another source of the system clock then stop the HSI14.
bogdanm	0:9b334a45a8ff	1128	* @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
bogdanm	0:9b334a45a8ff	1129	* should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
bogdanm	0:9b334a45a8ff	1130	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm	0:9b334a45a8ff	1131	* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
bogdanm	0:9b334a45a8ff	1132	* clock cycles.
bogdanm	0:9b334a45a8ff	1133	*/
bogdanm	0:9b334a45a8ff	1134	#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
bogdanm	0:9b334a45a8ff	1135	#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
bogdanm	0:9b334a45a8ff	1138	*/
bogdanm	0:9b334a45a8ff	1139	#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
bogdanm	0:9b334a45a8ff	1140	#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
bogdanm	0:9b334a45a8ff	1141
bogdanm	0:9b334a45a8ff	1142	/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
bogdanm	0:9b334a45a8ff	1143	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	1144	* and temperature that influence the frequency of the internal HSI14 RC.
bogdanm	0:9b334a45a8ff	1145	* @param __HSI14CalibrationValue__: specifies the calibration trimming value
bogdanm	0:9b334a45a8ff	1146	* (default is RCC_HSI14CALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	1147	* This parameter must be a number between 0 and 0x1F.
bogdanm	0:9b334a45a8ff	1148	*/
bogdanm	0:9b334a45a8ff	1149	#define RCC_CR2_HSI14TRIM_BitNumber 3
bogdanm	0:9b334a45a8ff	1150	#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
bogdanm	0:9b334a45a8ff	1151	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
bogdanm	0:9b334a45a8ff	1152	/**
bogdanm	0:9b334a45a8ff	1153	* @}
bogdanm	0:9b334a45a8ff	1154	*/
bogdanm	0:9b334a45a8ff	1155
bogdanm	0:9b334a45a8ff	1156	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
bogdanm	0:9b334a45a8ff	1157	* @{
bogdanm	0:9b334a45a8ff	1158	*/
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	/** @brief Macro to configure the USART1 clock (USART1CLK).
bogdanm	0:9b334a45a8ff	1161	* @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm	0:9b334a45a8ff	1162	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1163	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
bogdanm	0:9b334a45a8ff	1164	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	0:9b334a45a8ff	1165	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	0:9b334a45a8ff	1166	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	0:9b334a45a8ff	1167	*/
bogdanm	0:9b334a45a8ff	1168	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm	0:9b334a45a8ff	1169	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/** @brief Macro to get the USART1 clock source.
bogdanm	0:9b334a45a8ff	1172	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1173	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
bogdanm	0:9b334a45a8ff	1174	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	0:9b334a45a8ff	1175	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	0:9b334a45a8ff	1176	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	0:9b334a45a8ff	1177	*/
bogdanm	0:9b334a45a8ff	1178	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
bogdanm	0:9b334a45a8ff	1179	/**
bogdanm	0:9b334a45a8ff	1180	* @}
bogdanm	0:9b334a45a8ff	1181	*/
bogdanm	0:9b334a45a8ff	1182
bogdanm	0:9b334a45a8ff	1183	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
bogdanm	0:9b334a45a8ff	1184	* @{
bogdanm	0:9b334a45a8ff	1185	*/
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
bogdanm	0:9b334a45a8ff	1188	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm	0:9b334a45a8ff	1189	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1190	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1191	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1192	*/
bogdanm	0:9b334a45a8ff	1193	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm	0:9b334a45a8ff	1194	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/** @brief Macro to get the I2C1 clock source.
bogdanm	0:9b334a45a8ff	1197	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1198	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1199	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1200	*/
bogdanm	0:9b334a45a8ff	1201	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
bogdanm	0:9b334a45a8ff	1202	/**
bogdanm	0:9b334a45a8ff	1203	* @}
bogdanm	0:9b334a45a8ff	1204	*/
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/** @defgroup RCC_PLL_Configuration PLL Configuration
bogdanm	0:9b334a45a8ff	1208	* @{
bogdanm	0:9b334a45a8ff	1209	*/
bogdanm	0:9b334a45a8ff	1210
bogdanm	0:9b334a45a8ff	1211	/** @brief Macros to enable the main PLL.
bogdanm	0:9b334a45a8ff	1212	* @note After enabling the main PLL, the application software should wait on
bogdanm	0:9b334a45a8ff	1213	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	0:9b334a45a8ff	1214	* be used as system clock source.
bogdanm	0:9b334a45a8ff	1215	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1216	*/
bogdanm	0:9b334a45a8ff	1217	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	/** @brief Macros to disable the main PLL.
bogdanm	0:9b334a45a8ff	1220	* @note The main PLL can not be disabled if it is used as system clock source
bogdanm	0:9b334a45a8ff	1221	*/
bogdanm	0:9b334a45a8ff	1222	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
bogdanm	0:9b334a45a8ff	1225	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	1226	*
bogdanm	0:9b334a45a8ff	1227	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	1228	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1229	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	1230	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	1231	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
bogdanm	0:9b334a45a8ff	1232	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1233	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
bogdanm	0:9b334a45a8ff	1234	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
bogdanm	0:9b334a45a8ff	1235	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
bogdanm	0:9b334a45a8ff	1236	*
bogdanm	0:9b334a45a8ff	1237	*/
bogdanm	0:9b334a45a8ff	1238	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
bogdanm	0:9b334a45a8ff	1239	do { \
bogdanm	0:9b334a45a8ff	1240	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
bogdanm	0:9b334a45a8ff	1241	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSOURCE__))); \
bogdanm	0:9b334a45a8ff	1242	} while(0)
bogdanm	0:9b334a45a8ff	1243
bogdanm	0:9b334a45a8ff	1244	/** @brief Get oscillator clock selected as PLL input clock
bogdanm	0:9b334a45a8ff	1245	* @retval The clock source used for PLL entry. The returned value can be one
bogdanm	0:9b334a45a8ff	1246	* of the following:
bogdanm	0:9b334a45a8ff	1247	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
bogdanm	0:9b334a45a8ff	1248	*/
bogdanm	0:9b334a45a8ff	1249	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	/**
bogdanm	0:9b334a45a8ff	1252	* @}
bogdanm	0:9b334a45a8ff	1253	*/
bogdanm	0:9b334a45a8ff	1254
bogdanm	0:9b334a45a8ff	1255	/** @defgroup RCC_Get_Clock_source Get Clock source
bogdanm	0:9b334a45a8ff	1256	* @{
bogdanm	0:9b334a45a8ff	1257	*/
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	/**
bogdanm	0:9b334a45a8ff	1260	* @brief Macro to configure the system clock source.
bogdanm	0:9b334a45a8ff	1261	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
bogdanm	0:9b334a45a8ff	1262	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1263	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
bogdanm	0:9b334a45a8ff	1264	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
bogdanm	0:9b334a45a8ff	1265	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
bogdanm	0:9b334a45a8ff	1266	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
bogdanm	0:9b334a45a8ff	1267	*/
bogdanm	0:9b334a45a8ff	1268	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
bogdanm	0:9b334a45a8ff	1269	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	/** @brief Macro to get the clock source used as system clock.
bogdanm	0:9b334a45a8ff	1272	* @retval The clock source used as system clock. The returned value can be one
bogdanm	0:9b334a45a8ff	1273	* of the following:
bogdanm	0:9b334a45a8ff	1274	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
bogdanm	0:9b334a45a8ff	1275	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
bogdanm	0:9b334a45a8ff	1276	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
bogdanm	0:9b334a45a8ff	1277	*/
bogdanm	0:9b334a45a8ff	1278	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/**
bogdanm	0:9b334a45a8ff	1281	* @}
bogdanm	0:9b334a45a8ff	1282	*/
bogdanm	0:9b334a45a8ff	1283
bogdanm	0:9b334a45a8ff	1284	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
bogdanm	0:9b334a45a8ff	1285	* @{
bogdanm	0:9b334a45a8ff	1286	*/
bogdanm	0:9b334a45a8ff	1287
bogdanm	0:9b334a45a8ff	1288	/** @brief Macro to configures the RTC clock (RTCCLK).
bogdanm	0:9b334a45a8ff	1289	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	0:9b334a45a8ff	1290	* access is denied to this domain after reset, you have to enable write
bogdanm	0:9b334a45a8ff	1291	* access using the Power Backup Access macro before to configure
bogdanm	0:9b334a45a8ff	1292	* the RTC clock source (to be done once after reset).
bogdanm	0:9b334a45a8ff	1293	* @note Once the RTC clock is configured it can't be changed unless the
bogdanm	0:9b334a45a8ff	1294	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
bogdanm	0:9b334a45a8ff	1295	* a Power On Reset (POR).
bogdanm	0:9b334a45a8ff	1296	*
bogdanm	0:9b334a45a8ff	1297	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
bogdanm	0:9b334a45a8ff	1298	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1299	* @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
bogdanm	0:9b334a45a8ff	1300	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	0:9b334a45a8ff	1301	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	0:9b334a45a8ff	1302	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
bogdanm	0:9b334a45a8ff	1303	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	0:9b334a45a8ff	1304	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	0:9b334a45a8ff	1305	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
bogdanm	0:9b334a45a8ff	1306	* the RTC cannot be used in STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1307	* @note The system must always be configured so as to get a PCLK frequency greater than or
bogdanm	0:9b334a45a8ff	1308	* equal to the RTCCLK frequency for a proper operation of the RTC.
bogdanm	0:9b334a45a8ff	1309	*/
bogdanm	0:9b334a45a8ff	1310	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/** @brief macros to get the RTC clock source.
bogdanm	0:9b334a45a8ff	1313	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1314	* @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
bogdanm	0:9b334a45a8ff	1315	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	0:9b334a45a8ff	1316	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	0:9b334a45a8ff	1317	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
bogdanm	0:9b334a45a8ff	1318	*/
bogdanm	0:9b334a45a8ff	1319	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/** @brief Macros to enable the the RTC clock.
bogdanm	0:9b334a45a8ff	1322	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	0:9b334a45a8ff	1323	*/
bogdanm	0:9b334a45a8ff	1324	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
bogdanm	0:9b334a45a8ff	1325
bogdanm	0:9b334a45a8ff	1326	/** @brief Macros to disable the the RTC clock.
bogdanm	0:9b334a45a8ff	1327	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	0:9b334a45a8ff	1328	*/
bogdanm	0:9b334a45a8ff	1329	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	/** @brief Macros to force the Backup domain reset.
bogdanm	0:9b334a45a8ff	1332	* @note This function resets the RTC peripheral (including the backup registers)
bogdanm	0:9b334a45a8ff	1333	* and the RTC clock source selection in RCC_BDCR register.
bogdanm	0:9b334a45a8ff	1334	*/
bogdanm	0:9b334a45a8ff	1335	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	/** @brief Macros to release the Backup domain reset.
bogdanm	0:9b334a45a8ff	1338	*/
bogdanm	0:9b334a45a8ff	1339	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	/**
bogdanm	0:9b334a45a8ff	1342	* @}
bogdanm	0:9b334a45a8ff	1343	*/
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm	0:9b334a45a8ff	1346	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	0:9b334a45a8ff	1347	* @{
bogdanm	0:9b334a45a8ff	1348	*/
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	/** @brief Enable RCC interrupt.
bogdanm	0:9b334a45a8ff	1351	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	1352	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1353	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1354	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1355	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1356	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1357	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	0:9b334a45a8ff	1358	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
bogdanm	0:9b334a45a8ff	1359	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
bogdanm	0:9b334a45a8ff	1360	*/
bogdanm	0:9b334a45a8ff	1361	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	/** @brief Disable RCC interrupt.
bogdanm	0:9b334a45a8ff	1364	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	1365	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1366	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1367	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1368	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1369	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1370	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	0:9b334a45a8ff	1371	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
bogdanm	0:9b334a45a8ff	1372	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
bogdanm	0:9b334a45a8ff	1373	*/
bogdanm	0:9b334a45a8ff	1374	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1375
bogdanm	0:9b334a45a8ff	1376	/** @brief Clear the RCC's interrupt pending bits.
bogdanm	0:9b334a45a8ff	1377	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1378	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1379	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	0:9b334a45a8ff	1380	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	0:9b334a45a8ff	1381	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	0:9b334a45a8ff	1382	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	0:9b334a45a8ff	1383	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	0:9b334a45a8ff	1384	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1385	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
bogdanm	0:9b334a45a8ff	1386	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
bogdanm	0:9b334a45a8ff	1387	*/
bogdanm	0:9b334a45a8ff	1388	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	/** @brief Check the RCC's interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	1391	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm	0:9b334a45a8ff	1392	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1393	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	0:9b334a45a8ff	1394	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	0:9b334a45a8ff	1395	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	0:9b334a45a8ff	1396	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	0:9b334a45a8ff	1397	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	0:9b334a45a8ff	1398	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1399	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
bogdanm	0:9b334a45a8ff	1400	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
bogdanm	0:9b334a45a8ff	1401	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1402	*/
bogdanm	0:9b334a45a8ff	1403	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	/** @brief Set RMVF bit to clear the reset flags.
bogdanm	0:9b334a45a8ff	1406	* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
bogdanm	0:9b334a45a8ff	1407	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm	0:9b334a45a8ff	1408	*/
bogdanm	0:9b334a45a8ff	1409	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
bogdanm	0:9b334a45a8ff	1410
bogdanm	0:9b334a45a8ff	1411	/** @brief Check RCC flag is set or not.
bogdanm	0:9b334a45a8ff	1412	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	1413	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1414	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm	0:9b334a45a8ff	1415	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm	0:9b334a45a8ff	1416	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm	0:9b334a45a8ff	1417	* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
bogdanm	0:9b334a45a8ff	1418	* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
bogdanm	0:9b334a45a8ff	1419	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm	0:9b334a45a8ff	1420	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm	0:9b334a45a8ff	1421	* @arg RCC_FLAG_OBLRST: Option Byte Load reset
bogdanm	0:9b334a45a8ff	1422	* @arg RCC_FLAG_PINRST: Pin reset.
bogdanm	0:9b334a45a8ff	1423	* @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm	0:9b334a45a8ff	1424	* @arg RCC_FLAG_SFTRST: Software reset.
bogdanm	0:9b334a45a8ff	1425	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm	0:9b334a45a8ff	1426	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm	0:9b334a45a8ff	1427	* @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm	0:9b334a45a8ff	1428	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1429	*/
bogdanm	0:9b334a45a8ff	1430	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
bogdanm	0:9b334a45a8ff	1431	(((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
bogdanm	0:9b334a45a8ff	1432	(((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
bogdanm	0:9b334a45a8ff	1433	RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/**
bogdanm	0:9b334a45a8ff	1436	* @}
bogdanm	0:9b334a45a8ff	1437	*/
bogdanm	0:9b334a45a8ff	1438
bogdanm	0:9b334a45a8ff	1439	/**
bogdanm	0:9b334a45a8ff	1440	* @}
bogdanm	0:9b334a45a8ff	1441	*/
bogdanm	0:9b334a45a8ff	1442
bogdanm	0:9b334a45a8ff	1443	/* Include RCC HAL Extension module */
bogdanm	0:9b334a45a8ff	1444	#include "stm32f0xx_hal_rcc_ex.h"
bogdanm	0:9b334a45a8ff	1445
bogdanm	0:9b334a45a8ff	1446	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1447	/** @addtogroup RCC_Exported_Functions
bogdanm	0:9b334a45a8ff	1448	* @{
bogdanm	0:9b334a45a8ff	1449	*/
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	/** @addtogroup RCC_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	1452	* @{
bogdanm	0:9b334a45a8ff	1453	*/
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	/* Initialization and de-initialization functions ******************************/
bogdanm	0:9b334a45a8ff	1456	void HAL_RCC_DeInit(void);
bogdanm	0:9b334a45a8ff	1457	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1458	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460	/**
bogdanm	0:9b334a45a8ff	1461	* @}
bogdanm	0:9b334a45a8ff	1462	*/
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/** @addtogroup RCC_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	1465	* @{
bogdanm	0:9b334a45a8ff	1466	*/
bogdanm	0:9b334a45a8ff	1467
bogdanm	0:9b334a45a8ff	1468	/* Peripheral Control functions ************************************************/
bogdanm	0:9b334a45a8ff	1469	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	0:9b334a45a8ff	1470	void HAL_RCC_EnableCSS(void);
bogdanm	0:9b334a45a8ff	1471	void HAL_RCC_DisableCSS(void);
bogdanm	0:9b334a45a8ff	1472	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	0:9b334a45a8ff	1473	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	0:9b334a45a8ff	1474	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	0:9b334a45a8ff	1475	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1476	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	0:9b334a45a8ff	1477
bogdanm	0:9b334a45a8ff	1478	/* CSS NMI IRQ handler */
bogdanm	0:9b334a45a8ff	1479	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	0:9b334a45a8ff	1482	void HAL_RCC_CSSCallback(void);
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	/**
bogdanm	0:9b334a45a8ff	1485	* @}
bogdanm	0:9b334a45a8ff	1486	*/
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	/**
bogdanm	0:9b334a45a8ff	1489	* @}
bogdanm	0:9b334a45a8ff	1490	*/
bogdanm	0:9b334a45a8ff	1491
bogdanm	0:9b334a45a8ff	1492	/**
bogdanm	0:9b334a45a8ff	1493	* @}
bogdanm	0:9b334a45a8ff	1494	*/
bogdanm	0:9b334a45a8ff	1495
bogdanm	0:9b334a45a8ff	1496	/**
bogdanm	0:9b334a45a8ff	1497	* @}
bogdanm	0:9b334a45a8ff	1498	*/
bogdanm	0:9b334a45a8ff	1499
bogdanm	0:9b334a45a8ff	1500	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1501	}
bogdanm	0:9b334a45a8ff	1502	#endif
bogdanm	0:9b334a45a8ff	1503
bogdanm	0:9b334a45a8ff	1504	#endif /* __STM32F0xx_HAL_RCC_H */
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1507

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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