en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
56:05912f50f004 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 5:ac9f6c2c45e8 1 /**
mbed_official 5:ac9f6c2c45e8 2 ******************************************************************************
mbed_official 5:ac9f6c2c45e8 3 * @file system_stm32f0xx.c
mbed_official 5:ac9f6c2c45e8 4 * @author MCD Application Team
mbed_official 5:ac9f6c2c45e8 5 * @version V2.2.2
mbed_official 5:ac9f6c2c45e8 6 * @date 26-June-2015
mbed_official 5:ac9f6c2c45e8 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
mbed_official 5:ac9f6c2c45e8 8 *
mbed_official 5:ac9f6c2c45e8 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 5:ac9f6c2c45e8 10 * user application:
mbed_official 5:ac9f6c2c45e8 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 5:ac9f6c2c45e8 12 * before branch to main program. This call is made inside
mbed_official 5:ac9f6c2c45e8 13 * the "startup_stm32f0xx.s" file.
mbed_official 5:ac9f6c2c45e8 14 *
mbed_official 5:ac9f6c2c45e8 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 5:ac9f6c2c45e8 16 * by the user application to setup the SysTick
mbed_official 5:ac9f6c2c45e8 17 * timer or configure other parameters.
mbed_official 5:ac9f6c2c45e8 18 *
mbed_official 5:ac9f6c2c45e8 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 5:ac9f6c2c45e8 20 * be called whenever the core clock is changed
mbed_official 5:ac9f6c2c45e8 21 * during program execution.
mbed_official 5:ac9f6c2c45e8 22 *
mbed_official 5:ac9f6c2c45e8 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 5:ac9f6c2c45e8 24 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
mbed_official 5:ac9f6c2c45e8 25 * configure the system clock before to branch to main program.
mbed_official 5:ac9f6c2c45e8 26 *
mbed_official 5:ac9f6c2c45e8 27 * 3. This file configures the system clock as follows:
mbed_official 5:ac9f6c2c45e8 28 *=============================================================================
mbed_official 5:ac9f6c2c45e8 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 5:ac9f6c2c45e8 30 * | (external 8 MHz clock) | (internal 48 MHz)
mbed_official 5:ac9f6c2c45e8 31 * | 2- PLL_HSE_XTAL |
mbed_official 5:ac9f6c2c45e8 32 * | (external 8 MHz xtal) |
mbed_official 5:ac9f6c2c45e8 33 *-----------------------------------------------------------------------------
mbed_official 5:ac9f6c2c45e8 34 * SYSCLK(MHz) | 48 | 48
mbed_official 5:ac9f6c2c45e8 35 *-----------------------------------------------------------------------------
mbed_official 5:ac9f6c2c45e8 36 * AHBCLK (MHz) | 48 | 48
mbed_official 5:ac9f6c2c45e8 37 *-----------------------------------------------------------------------------
mbed_official 5:ac9f6c2c45e8 38 * APB1CLK (MHz) | 48 | 48
mbed_official 5:ac9f6c2c45e8 39 *-----------------------------------------------------------------------------
mbed_official 5:ac9f6c2c45e8 40 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 5:ac9f6c2c45e8 41 *=============================================================================
mbed_official 5:ac9f6c2c45e8 42 ******************************************************************************
mbed_official 5:ac9f6c2c45e8 43 * @attention
mbed_official 5:ac9f6c2c45e8 44 *
mbed_official 5:ac9f6c2c45e8 45 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 5:ac9f6c2c45e8 46 *
mbed_official 5:ac9f6c2c45e8 47 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 5:ac9f6c2c45e8 48 * are permitted provided that the following conditions are met:
mbed_official 5:ac9f6c2c45e8 49 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 5:ac9f6c2c45e8 50 * this list of conditions and the following disclaimer.
mbed_official 5:ac9f6c2c45e8 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 5:ac9f6c2c45e8 52 * this list of conditions and the following disclaimer in the documentation
mbed_official 5:ac9f6c2c45e8 53 * and/or other materials provided with the distribution.
mbed_official 5:ac9f6c2c45e8 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 5:ac9f6c2c45e8 55 * may be used to endorse or promote products derived from this software
mbed_official 5:ac9f6c2c45e8 56 * without specific prior written permission.
mbed_official 5:ac9f6c2c45e8 57 *
mbed_official 5:ac9f6c2c45e8 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 5:ac9f6c2c45e8 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 5:ac9f6c2c45e8 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 5:ac9f6c2c45e8 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 5:ac9f6c2c45e8 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 5:ac9f6c2c45e8 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 5:ac9f6c2c45e8 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 5:ac9f6c2c45e8 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 5:ac9f6c2c45e8 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 5:ac9f6c2c45e8 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 5:ac9f6c2c45e8 68 *
mbed_official 5:ac9f6c2c45e8 69 ******************************************************************************
mbed_official 5:ac9f6c2c45e8 70 */
mbed_official 5:ac9f6c2c45e8 71
mbed_official 5:ac9f6c2c45e8 72 /** @addtogroup CMSIS
mbed_official 5:ac9f6c2c45e8 73 * @{
mbed_official 5:ac9f6c2c45e8 74 */
mbed_official 5:ac9f6c2c45e8 75
mbed_official 5:ac9f6c2c45e8 76 /** @addtogroup stm32f0xx_system
mbed_official 5:ac9f6c2c45e8 77 * @{
mbed_official 5:ac9f6c2c45e8 78 */
mbed_official 5:ac9f6c2c45e8 79
mbed_official 5:ac9f6c2c45e8 80 /** @addtogroup STM32F0xx_System_Private_Includes
mbed_official 5:ac9f6c2c45e8 81 * @{
mbed_official 5:ac9f6c2c45e8 82 */
mbed_official 5:ac9f6c2c45e8 83
mbed_official 5:ac9f6c2c45e8 84 #include "stm32f0xx.h"
mbed_official 43:e3d4af315dd8 85 #include "hal_tick.h"
mbed_official 5:ac9f6c2c45e8 86 /**
mbed_official 5:ac9f6c2c45e8 87 * @}
mbed_official 5:ac9f6c2c45e8 88 */
mbed_official 5:ac9f6c2c45e8 89
mbed_official 5:ac9f6c2c45e8 90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
mbed_official 5:ac9f6c2c45e8 91 * @{
mbed_official 5:ac9f6c2c45e8 92 */
mbed_official 5:ac9f6c2c45e8 93
mbed_official 5:ac9f6c2c45e8 94 /**
mbed_official 5:ac9f6c2c45e8 95 * @}
mbed_official 5:ac9f6c2c45e8 96 */
mbed_official 5:ac9f6c2c45e8 97
mbed_official 5:ac9f6c2c45e8 98 /** @addtogroup STM32F0xx_System_Private_Defines
mbed_official 5:ac9f6c2c45e8 99 * @{
mbed_official 5:ac9f6c2c45e8 100 */
mbed_official 5:ac9f6c2c45e8 101 #if !defined (HSE_VALUE)
mbed_official 5:ac9f6c2c45e8 102 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 5:ac9f6c2c45e8 103 This value can be provided and adapted by the user application. */
mbed_official 5:ac9f6c2c45e8 104 #endif /* HSE_VALUE */
mbed_official 5:ac9f6c2c45e8 105
mbed_official 5:ac9f6c2c45e8 106 #if !defined (HSI_VALUE)
mbed_official 5:ac9f6c2c45e8 107 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 5:ac9f6c2c45e8 108 This value can be provided and adapted by the user application. */
mbed_official 5:ac9f6c2c45e8 109 #endif /* HSI_VALUE */
mbed_official 5:ac9f6c2c45e8 110
mbed_official 5:ac9f6c2c45e8 111 /**
mbed_official 5:ac9f6c2c45e8 112 * @}
mbed_official 5:ac9f6c2c45e8 113 */
mbed_official 5:ac9f6c2c45e8 114
mbed_official 5:ac9f6c2c45e8 115 /** @addtogroup STM32F0xx_System_Private_Macros
mbed_official 5:ac9f6c2c45e8 116 * @{
mbed_official 5:ac9f6c2c45e8 117 */
mbed_official 5:ac9f6c2c45e8 118
mbed_official 5:ac9f6c2c45e8 119 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 34:bb6061527455 120 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
mbed_official 9:673ec039aeb3 121 #define USE_PLL_HSE_XTAL (0) /* Use external xtal */
mbed_official 5:ac9f6c2c45e8 122
mbed_official 5:ac9f6c2c45e8 123 /**
mbed_official 5:ac9f6c2c45e8 124 * @}
mbed_official 5:ac9f6c2c45e8 125 */
mbed_official 5:ac9f6c2c45e8 126
mbed_official 5:ac9f6c2c45e8 127 /** @addtogroup STM32F0xx_System_Private_Variables
mbed_official 5:ac9f6c2c45e8 128 * @{
mbed_official 5:ac9f6c2c45e8 129 */
mbed_official 5:ac9f6c2c45e8 130 /* This variable is updated in three ways:
mbed_official 5:ac9f6c2c45e8 131 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 5:ac9f6c2c45e8 132 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 5:ac9f6c2c45e8 133 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 5:ac9f6c2c45e8 134 Note: If you use this function to configure the system clock there is no need to
mbed_official 5:ac9f6c2c45e8 135 call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official 5:ac9f6c2c45e8 136 updated automatically.
mbed_official 5:ac9f6c2c45e8 137 */
mbed_official 5:ac9f6c2c45e8 138 uint32_t SystemCoreClock = 48000000;
mbed_official 5:ac9f6c2c45e8 139
mbed_official 5:ac9f6c2c45e8 140 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 5:ac9f6c2c45e8 141
mbed_official 5:ac9f6c2c45e8 142 /**
mbed_official 5:ac9f6c2c45e8 143 * @}
mbed_official 5:ac9f6c2c45e8 144 */
mbed_official 5:ac9f6c2c45e8 145
mbed_official 5:ac9f6c2c45e8 146 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
mbed_official 5:ac9f6c2c45e8 147 * @{
mbed_official 5:ac9f6c2c45e8 148 */
mbed_official 5:ac9f6c2c45e8 149
mbed_official 5:ac9f6c2c45e8 150 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 5:ac9f6c2c45e8 151 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 5:ac9f6c2c45e8 152 #endif
mbed_official 5:ac9f6c2c45e8 153
mbed_official 5:ac9f6c2c45e8 154 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 5:ac9f6c2c45e8 155
mbed_official 5:ac9f6c2c45e8 156 /**
mbed_official 5:ac9f6c2c45e8 157 * @}
mbed_official 5:ac9f6c2c45e8 158 */
mbed_official 5:ac9f6c2c45e8 159
mbed_official 5:ac9f6c2c45e8 160 /** @addtogroup STM32F0xx_System_Private_Functions
mbed_official 5:ac9f6c2c45e8 161 * @{
mbed_official 5:ac9f6c2c45e8 162 */
mbed_official 5:ac9f6c2c45e8 163
mbed_official 43:e3d4af315dd8 164
mbed_official 5:ac9f6c2c45e8 165 /**
mbed_official 5:ac9f6c2c45e8 166 * @brief Setup the microcontroller system.
mbed_official 5:ac9f6c2c45e8 167 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
mbed_official 5:ac9f6c2c45e8 168 * @param None
mbed_official 5:ac9f6c2c45e8 169 * @retval None
mbed_official 5:ac9f6c2c45e8 170 */
mbed_official 5:ac9f6c2c45e8 171 void SystemInit(void)
mbed_official 5:ac9f6c2c45e8 172 {
mbed_official 5:ac9f6c2c45e8 173 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 5:ac9f6c2c45e8 174 /* Set HSION bit */
mbed_official 5:ac9f6c2c45e8 175 RCC->CR |= (uint32_t)0x00000001;
mbed_official 5:ac9f6c2c45e8 176
mbed_official 5:ac9f6c2c45e8 177 #if defined (STM32F051x8) || defined (STM32F058x8)
mbed_official 5:ac9f6c2c45e8 178 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
mbed_official 5:ac9f6c2c45e8 179 RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official 5:ac9f6c2c45e8 180 #else
mbed_official 5:ac9f6c2c45e8 181 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
mbed_official 5:ac9f6c2c45e8 182 RCC->CFGR &= (uint32_t)0x08FFB80C;
mbed_official 5:ac9f6c2c45e8 183 #endif /* STM32F051x8 or STM32F058x8 */
mbed_official 5:ac9f6c2c45e8 184
mbed_official 5:ac9f6c2c45e8 185 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 5:ac9f6c2c45e8 186 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 5:ac9f6c2c45e8 187
mbed_official 5:ac9f6c2c45e8 188 /* Reset HSEBYP bit */
mbed_official 5:ac9f6c2c45e8 189 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 5:ac9f6c2c45e8 190
mbed_official 5:ac9f6c2c45e8 191 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official 5:ac9f6c2c45e8 192 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official 5:ac9f6c2c45e8 193
mbed_official 5:ac9f6c2c45e8 194 /* Reset PREDIV[3:0] bits */
mbed_official 5:ac9f6c2c45e8 195 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 5:ac9f6c2c45e8 196
mbed_official 5:ac9f6c2c45e8 197 #if defined (STM32F072xB) || defined (STM32F078xx)
mbed_official 5:ac9f6c2c45e8 198 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 5:ac9f6c2c45e8 199 RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
mbed_official 5:ac9f6c2c45e8 200 #elif defined (STM32F071xB)
mbed_official 5:ac9f6c2c45e8 201 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
mbed_official 5:ac9f6c2c45e8 202 RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
mbed_official 5:ac9f6c2c45e8 203 #elif defined (STM32F091xC) || defined (STM32F098xx)
mbed_official 5:ac9f6c2c45e8 204 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
mbed_official 5:ac9f6c2c45e8 205 RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
mbed_official 5:ac9f6c2c45e8 206 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
mbed_official 5:ac9f6c2c45e8 207 /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
mbed_official 5:ac9f6c2c45e8 208 RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
mbed_official 5:ac9f6c2c45e8 209 #elif defined (STM32F051x8) || defined (STM32F058xx)
mbed_official 5:ac9f6c2c45e8 210 /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
mbed_official 5:ac9f6c2c45e8 211 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
mbed_official 5:ac9f6c2c45e8 212 #elif defined (STM32F042x6) || defined (STM32F048xx)
mbed_official 5:ac9f6c2c45e8 213 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 5:ac9f6c2c45e8 214 RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
mbed_official 5:ac9f6c2c45e8 215 #elif defined (STM32F070x6) || defined (STM32F070xB)
mbed_official 5:ac9f6c2c45e8 216 /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
mbed_official 5:ac9f6c2c45e8 217 RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
mbed_official 5:ac9f6c2c45e8 218 /* Set default USB clock to PLLCLK, since there is no HSI48 */
mbed_official 5:ac9f6c2c45e8 219 RCC->CFGR3 |= (uint32_t)0x00000080;
mbed_official 5:ac9f6c2c45e8 220 #else
mbed_official 5:ac9f6c2c45e8 221 #warning "No target selected"
mbed_official 5:ac9f6c2c45e8 222 #endif
mbed_official 5:ac9f6c2c45e8 223
mbed_official 5:ac9f6c2c45e8 224 /* Reset HSI14 bit */
mbed_official 5:ac9f6c2c45e8 225 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official 5:ac9f6c2c45e8 226
mbed_official 5:ac9f6c2c45e8 227 /* Disable all interrupts */
mbed_official 5:ac9f6c2c45e8 228 RCC->CIR = 0x00000000;
mbed_official 43:e3d4af315dd8 229
mbed_official 46:cb4f85f96d35 230 /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
mbed_official 46:cb4f85f96d35 231 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
mbed_official 46:cb4f85f96d35 232
mbed_official 43:e3d4af315dd8 233 /* Configure the Cube driver */
mbed_official 43:e3d4af315dd8 234 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official 43:e3d4af315dd8 235 HAL_Init();
mbed_official 43:e3d4af315dd8 236
mbed_official 43:e3d4af315dd8 237 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 43:e3d4af315dd8 238 AHB/APBx prescalers and Flash settings */
mbed_official 43:e3d4af315dd8 239 SetSysClock();
mbed_official 43:e3d4af315dd8 240
mbed_official 43:e3d4af315dd8 241 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 43:e3d4af315dd8 242 TIM_MST_RESET_ON;
mbed_official 43:e3d4af315dd8 243 TIM_MST_RESET_OFF;
mbed_official 5:ac9f6c2c45e8 244 }
mbed_official 5:ac9f6c2c45e8 245
mbed_official 5:ac9f6c2c45e8 246 /**
mbed_official 5:ac9f6c2c45e8 247 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 5:ac9f6c2c45e8 248 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 5:ac9f6c2c45e8 249 * be used by the user application to setup the SysTick timer or configure
mbed_official 5:ac9f6c2c45e8 250 * other parameters.
mbed_official 5:ac9f6c2c45e8 251 *
mbed_official 5:ac9f6c2c45e8 252 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 5:ac9f6c2c45e8 253 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 5:ac9f6c2c45e8 254 * based on this variable will be incorrect.
mbed_official 5:ac9f6c2c45e8 255 *
mbed_official 5:ac9f6c2c45e8 256 * @note - The system frequency computed by this function is not the real
mbed_official 5:ac9f6c2c45e8 257 * frequency in the chip. It is calculated based on the predefined
mbed_official 5:ac9f6c2c45e8 258 * constant and the selected clock source:
mbed_official 5:ac9f6c2c45e8 259 *
mbed_official 5:ac9f6c2c45e8 260 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 5:ac9f6c2c45e8 261 *
mbed_official 5:ac9f6c2c45e8 262 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 5:ac9f6c2c45e8 263 *
mbed_official 5:ac9f6c2c45e8 264 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 5:ac9f6c2c45e8 265 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 5:ac9f6c2c45e8 266 *
mbed_official 5:ac9f6c2c45e8 267 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 5:ac9f6c2c45e8 268 * 8 MHz) but the real value may vary depending on the variations
mbed_official 5:ac9f6c2c45e8 269 * in voltage and temperature.
mbed_official 5:ac9f6c2c45e8 270 *
mbed_official 5:ac9f6c2c45e8 271 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 5:ac9f6c2c45e8 272 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 5:ac9f6c2c45e8 273 * frequency of the crystal used. Otherwise, this function may
mbed_official 5:ac9f6c2c45e8 274 * have wrong result.
mbed_official 5:ac9f6c2c45e8 275 *
mbed_official 5:ac9f6c2c45e8 276 * - The result of this function could be not correct when using fractional
mbed_official 5:ac9f6c2c45e8 277 * value for HSE crystal.
mbed_official 5:ac9f6c2c45e8 278 *
mbed_official 5:ac9f6c2c45e8 279 * @param None
mbed_official 5:ac9f6c2c45e8 280 * @retval None
mbed_official 5:ac9f6c2c45e8 281 */
mbed_official 5:ac9f6c2c45e8 282 void SystemCoreClockUpdate (void)
mbed_official 5:ac9f6c2c45e8 283 {
mbed_official 5:ac9f6c2c45e8 284 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 5:ac9f6c2c45e8 285
mbed_official 5:ac9f6c2c45e8 286 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 5:ac9f6c2c45e8 287 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 5:ac9f6c2c45e8 288
mbed_official 5:ac9f6c2c45e8 289 switch (tmp)
mbed_official 5:ac9f6c2c45e8 290 {
mbed_official 5:ac9f6c2c45e8 291 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 5:ac9f6c2c45e8 292 SystemCoreClock = HSI_VALUE;
mbed_official 5:ac9f6c2c45e8 293 break;
mbed_official 5:ac9f6c2c45e8 294 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 5:ac9f6c2c45e8 295 SystemCoreClock = HSE_VALUE;
mbed_official 5:ac9f6c2c45e8 296 break;
mbed_official 5:ac9f6c2c45e8 297 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 5:ac9f6c2c45e8 298 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 5:ac9f6c2c45e8 299 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 5:ac9f6c2c45e8 300 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 5:ac9f6c2c45e8 301 pllmull = ( pllmull >> 18) + 2;
mbed_official 5:ac9f6c2c45e8 302 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 5:ac9f6c2c45e8 303
mbed_official 5:ac9f6c2c45e8 304 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
mbed_official 5:ac9f6c2c45e8 305 {
mbed_official 5:ac9f6c2c45e8 306 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
mbed_official 5:ac9f6c2c45e8 307 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
mbed_official 5:ac9f6c2c45e8 308 }
mbed_official 5:ac9f6c2c45e8 309 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
mbed_official 5:ac9f6c2c45e8 310 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
mbed_official 5:ac9f6c2c45e8 311 {
mbed_official 5:ac9f6c2c45e8 312 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
mbed_official 5:ac9f6c2c45e8 313 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
mbed_official 5:ac9f6c2c45e8 314 }
mbed_official 5:ac9f6c2c45e8 315 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
mbed_official 5:ac9f6c2c45e8 316 else
mbed_official 5:ac9f6c2c45e8 317 {
mbed_official 5:ac9f6c2c45e8 318 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
mbed_official 5:ac9f6c2c45e8 319 || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
mbed_official 5:ac9f6c2c45e8 320 || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
mbed_official 5:ac9f6c2c45e8 321 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
mbed_official 5:ac9f6c2c45e8 322 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
mbed_official 5:ac9f6c2c45e8 323 #else
mbed_official 5:ac9f6c2c45e8 324 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
mbed_official 5:ac9f6c2c45e8 325 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 5:ac9f6c2c45e8 326 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
mbed_official 5:ac9f6c2c45e8 327 STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
mbed_official 5:ac9f6c2c45e8 328 STM32F091xC || STM32F098xx || STM32F030xC */
mbed_official 5:ac9f6c2c45e8 329 }
mbed_official 5:ac9f6c2c45e8 330 break;
mbed_official 5:ac9f6c2c45e8 331 default: /* HSI used as system clock */
mbed_official 5:ac9f6c2c45e8 332 SystemCoreClock = HSI_VALUE;
mbed_official 5:ac9f6c2c45e8 333 break;
mbed_official 5:ac9f6c2c45e8 334 }
mbed_official 5:ac9f6c2c45e8 335 /* Compute HCLK clock frequency ----------------*/
mbed_official 5:ac9f6c2c45e8 336 /* Get HCLK prescaler */
mbed_official 5:ac9f6c2c45e8 337 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 5:ac9f6c2c45e8 338 /* HCLK clock frequency */
mbed_official 5:ac9f6c2c45e8 339 SystemCoreClock >>= tmp;
mbed_official 5:ac9f6c2c45e8 340 }
mbed_official 5:ac9f6c2c45e8 341
mbed_official 5:ac9f6c2c45e8 342 /**
mbed_official 5:ac9f6c2c45e8 343 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 5:ac9f6c2c45e8 344 * AHB/APBx prescalers and Flash settings
mbed_official 5:ac9f6c2c45e8 345 * @note This function should be called only once the RCC clock configuration
mbed_official 5:ac9f6c2c45e8 346 * is reset to the default reset state (done in SystemInit() function).
mbed_official 5:ac9f6c2c45e8 347 * @param None
mbed_official 5:ac9f6c2c45e8 348 * @retval None
mbed_official 5:ac9f6c2c45e8 349 */
mbed_official 5:ac9f6c2c45e8 350 void SetSysClock(void)
mbed_official 5:ac9f6c2c45e8 351 {
mbed_official 5:ac9f6c2c45e8 352 /* 1- Try to start with HSE and external clock */
mbed_official 5:ac9f6c2c45e8 353 #if USE_PLL_HSE_EXTC != 0
mbed_official 5:ac9f6c2c45e8 354 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 5:ac9f6c2c45e8 355 #endif
mbed_official 5:ac9f6c2c45e8 356 {
mbed_official 5:ac9f6c2c45e8 357 /* 2- If fail try to start with HSE and external xtal */
mbed_official 5:ac9f6c2c45e8 358 #if USE_PLL_HSE_XTAL != 0
mbed_official 5:ac9f6c2c45e8 359 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 5:ac9f6c2c45e8 360 #endif
mbed_official 5:ac9f6c2c45e8 361 {
mbed_official 5:ac9f6c2c45e8 362 /* 3- If fail start with HSI clock */
mbed_official 5:ac9f6c2c45e8 363 if (SetSysClock_PLL_HSI() == 0)
mbed_official 5:ac9f6c2c45e8 364 {
mbed_official 5:ac9f6c2c45e8 365 while(1)
mbed_official 5:ac9f6c2c45e8 366 {
mbed_official 5:ac9f6c2c45e8 367 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 5:ac9f6c2c45e8 368 }
mbed_official 5:ac9f6c2c45e8 369 }
mbed_official 5:ac9f6c2c45e8 370 }
mbed_official 5:ac9f6c2c45e8 371 }
mbed_official 5:ac9f6c2c45e8 372
mbed_official 5:ac9f6c2c45e8 373 // Output clock on MCO pin(PA8) for debugging purpose
mbed_official 5:ac9f6c2c45e8 374 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
mbed_official 5:ac9f6c2c45e8 375 }
mbed_official 5:ac9f6c2c45e8 376
mbed_official 5:ac9f6c2c45e8 377 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 5:ac9f6c2c45e8 378 /******************************************************************************/
mbed_official 5:ac9f6c2c45e8 379 /* PLL (clocked by HSE) used as System clock source */
mbed_official 5:ac9f6c2c45e8 380 /******************************************************************************/
mbed_official 5:ac9f6c2c45e8 381 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 5:ac9f6c2c45e8 382 {
mbed_official 5:ac9f6c2c45e8 383 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
mbed_official 5:ac9f6c2c45e8 384 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
mbed_official 5:ac9f6c2c45e8 385 //Select HSI as system clock source to allow modification of the PLL configuration
mbed_official 5:ac9f6c2c45e8 386 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
mbed_official 5:ac9f6c2c45e8 387 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
mbed_official 5:ac9f6c2c45e8 388 if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 5:ac9f6c2c45e8 389 {
mbed_official 5:ac9f6c2c45e8 390 return 0; // FAIL
mbed_official 5:ac9f6c2c45e8 391 }
mbed_official 5:ac9f6c2c45e8 392
mbed_official 5:ac9f6c2c45e8 393
mbed_official 5:ac9f6c2c45e8 394 // Select HSE oscillator as PLL source
mbed_official 5:ac9f6c2c45e8 395 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 5:ac9f6c2c45e8 396 if (bypass == 0) {
mbed_official 5:ac9f6c2c45e8 397 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
mbed_official 5:ac9f6c2c45e8 398 } else {
mbed_official 5:ac9f6c2c45e8 399 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
mbed_official 5:ac9f6c2c45e8 400 }
mbed_official 5:ac9f6c2c45e8 401 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 5:ac9f6c2c45e8 402 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 5:ac9f6c2c45e8 403 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
mbed_official 5:ac9f6c2c45e8 404 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official 5:ac9f6c2c45e8 405 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 5:ac9f6c2c45e8 406 return 0; // FAIL
mbed_official 5:ac9f6c2c45e8 407 }
mbed_official 5:ac9f6c2c45e8 408
mbed_official 5:ac9f6c2c45e8 409 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 5:ac9f6c2c45e8 410 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 5:ac9f6c2c45e8 411 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 5:ac9f6c2c45e8 412 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 5:ac9f6c2c45e8 413 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 5:ac9f6c2c45e8 414 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 5:ac9f6c2c45e8 415 return 0; // FAIL
mbed_official 5:ac9f6c2c45e8 416 }
mbed_official 5:ac9f6c2c45e8 417
mbed_official 5:ac9f6c2c45e8 418 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
mbed_official 5:ac9f6c2c45e8 419
mbed_official 5:ac9f6c2c45e8 420 return 1; // OK
mbed_official 5:ac9f6c2c45e8 421 }
mbed_official 5:ac9f6c2c45e8 422 #endif
mbed_official 5:ac9f6c2c45e8 423
mbed_official 5:ac9f6c2c45e8 424 /******************************************************************************/
mbed_official 5:ac9f6c2c45e8 425 /* PLL (clocked by HSI) used as System clock source */
mbed_official 5:ac9f6c2c45e8 426 /******************************************************************************/
mbed_official 5:ac9f6c2c45e8 427 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 5:ac9f6c2c45e8 428 {
mbed_official 5:ac9f6c2c45e8 429 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 5:ac9f6c2c45e8 430 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 5:ac9f6c2c45e8 431
mbed_official 56:05912f50f004 432 // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
mbed_official 56:05912f50f004 433 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
mbed_official 56:05912f50f004 434 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 56:05912f50f004 435 RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
mbed_official 56:05912f50f004 436 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 56:05912f50f004 437 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
mbed_official 56:05912f50f004 438 RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
mbed_official 56:05912f50f004 439 RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
mbed_official 56:05912f50f004 440 RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
mbed_official 56:05912f50f004 441 RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
mbed_official 56:05912f50f004 442 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 56:05912f50f004 443 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
mbed_official 56:05912f50f004 444 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
mbed_official 56:05912f50f004 445 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
mbed_official 5:ac9f6c2c45e8 446 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 5:ac9f6c2c45e8 447 return 0; // FAIL
mbed_official 5:ac9f6c2c45e8 448 }
mbed_official 5:ac9f6c2c45e8 449
mbed_official 5:ac9f6c2c45e8 450 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 5:ac9f6c2c45e8 451 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 5:ac9f6c2c45e8 452 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 5:ac9f6c2c45e8 453 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 5:ac9f6c2c45e8 454 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 5:ac9f6c2c45e8 455 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 5:ac9f6c2c45e8 456 return 0; // FAIL
mbed_official 5:ac9f6c2c45e8 457 }
mbed_official 5:ac9f6c2c45e8 458
mbed_official 5:ac9f6c2c45e8 459 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
mbed_official 5:ac9f6c2c45e8 460
mbed_official 5:ac9f6c2c45e8 461 return 1; // OK
mbed_official 5:ac9f6c2c45e8 462 }
mbed_official 5:ac9f6c2c45e8 463
mbed_official 5:ac9f6c2c45e8 464 /**
mbed_official 5:ac9f6c2c45e8 465 * @}
mbed_official 5:ac9f6c2c45e8 466 */
mbed_official 5:ac9f6c2c45e8 467
mbed_official 5:ac9f6c2c45e8 468 /**
mbed_official 5:ac9f6c2c45e8 469 * @}
mbed_official 5:ac9f6c2c45e8 470 */
mbed_official 5:ac9f6c2c45e8 471
mbed_official 5:ac9f6c2c45e8 472 /**
mbed_official 5:ac9f6c2c45e8 473 * @}
mbed_official 5:ac9f6c2c45e8 474 */
mbed_official 5:ac9f6c2c45e8 475
mbed_official 5:ac9f6c2c45e8 476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 5:ac9f6c2c45e8 477