en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
56:05912f50f004 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32f0xx.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V2.2.2
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * 1. This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 10 * user application:
bogdanm 0:9b334a45a8ff 11 * - SystemInit(): This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 12 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 13 * the "startup_stm32f0xx.s" file.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 16 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 17 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 20 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 21 * during program execution.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
bogdanm 0:9b334a45a8ff 24 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
bogdanm 0:9b334a45a8ff 25 * configure the system clock before to branch to main program.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * 3. This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 28 *=============================================================================
bogdanm 0:9b334a45a8ff 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
bogdanm 0:9b334a45a8ff 30 * | (external 8 MHz clock) | (internal 48 MHz)
bogdanm 0:9b334a45a8ff 31 * | 2- PLL_HSE_XTAL |
bogdanm 0:9b334a45a8ff 32 * | (external 8 MHz xtal) |
bogdanm 0:9b334a45a8ff 33 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 34 * SYSCLK(MHz) | 48 | 48
bogdanm 0:9b334a45a8ff 35 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 36 * AHBCLK (MHz) | 48 | 48
bogdanm 0:9b334a45a8ff 37 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 38 * APB1CLK (MHz) | 48 | 48
bogdanm 0:9b334a45a8ff 39 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 40 * USB capable (48 MHz precise clock) | YES | YES
bogdanm 0:9b334a45a8ff 41 *=============================================================================
bogdanm 0:9b334a45a8ff 42 ******************************************************************************
bogdanm 0:9b334a45a8ff 43 * @attention
bogdanm 0:9b334a45a8ff 44 *
bogdanm 0:9b334a45a8ff 45 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 46 *
bogdanm 0:9b334a45a8ff 47 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 48 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 49 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 50 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 52 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 53 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 55 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 56 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 57 *
bogdanm 0:9b334a45a8ff 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 68 *
bogdanm 0:9b334a45a8ff 69 ******************************************************************************
bogdanm 0:9b334a45a8ff 70 */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 73 * @{
bogdanm 0:9b334a45a8ff 74 */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 /** @addtogroup stm32f0xx_system
bogdanm 0:9b334a45a8ff 77 * @{
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 /** @addtogroup STM32F0xx_System_Private_Includes
bogdanm 0:9b334a45a8ff 81 * @{
bogdanm 0:9b334a45a8ff 82 */
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 #include "stm32f0xx.h"
mbed_official 43:e3d4af315dd8 85 #include "hal_tick.h"
bogdanm 0:9b334a45a8ff 86 /**
bogdanm 0:9b334a45a8ff 87 * @}
bogdanm 0:9b334a45a8ff 88 */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 91 * @{
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /**
bogdanm 0:9b334a45a8ff 95 * @}
bogdanm 0:9b334a45a8ff 96 */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /** @addtogroup STM32F0xx_System_Private_Defines
bogdanm 0:9b334a45a8ff 99 * @{
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 102 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
bogdanm 0:9b334a45a8ff 103 This value can be provided and adapted by the user application. */
bogdanm 0:9b334a45a8ff 104 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 107 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
bogdanm 0:9b334a45a8ff 108 This value can be provided and adapted by the user application. */
bogdanm 0:9b334a45a8ff 109 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /**
bogdanm 0:9b334a45a8ff 112 * @}
bogdanm 0:9b334a45a8ff 113 */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /** @addtogroup STM32F0xx_System_Private_Macros
bogdanm 0:9b334a45a8ff 116 * @{
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 34:bb6061527455 120 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
mbed_official 11:f10b285e3846 121 #define USE_PLL_HSE_XTAL (0) /* Use external xtal */
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /**
bogdanm 0:9b334a45a8ff 124 * @}
bogdanm 0:9b334a45a8ff 125 */
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /** @addtogroup STM32F0xx_System_Private_Variables
bogdanm 0:9b334a45a8ff 128 * @{
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130 /* This variable is updated in three ways:
bogdanm 0:9b334a45a8ff 131 1) by calling CMSIS function SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 132 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
bogdanm 0:9b334a45a8ff 133 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
bogdanm 0:9b334a45a8ff 134 Note: If you use this function to configure the system clock there is no need to
bogdanm 0:9b334a45a8ff 135 call the 2 first functions listed above, since SystemCoreClock variable is
bogdanm 0:9b334a45a8ff 136 updated automatically.
bogdanm 0:9b334a45a8ff 137 */
bogdanm 0:9b334a45a8ff 138 uint32_t SystemCoreClock = 48000000;
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /**
bogdanm 0:9b334a45a8ff 143 * @}
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 147 * @{
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 151 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
bogdanm 0:9b334a45a8ff 152 #endif
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 uint8_t SetSysClock_PLL_HSI(void);
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /**
bogdanm 0:9b334a45a8ff 157 * @}
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 /** @addtogroup STM32F0xx_System_Private_Functions
bogdanm 0:9b334a45a8ff 161 * @{
bogdanm 0:9b334a45a8ff 162 */
bogdanm 0:9b334a45a8ff 163
mbed_official 43:e3d4af315dd8 164
bogdanm 0:9b334a45a8ff 165 /**
bogdanm 0:9b334a45a8ff 166 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 167 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
bogdanm 0:9b334a45a8ff 168 * @param None
bogdanm 0:9b334a45a8ff 169 * @retval None
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171 void SystemInit(void)
bogdanm 0:9b334a45a8ff 172 {
bogdanm 0:9b334a45a8ff 173 /* Reset the RCC clock configuration to the default reset state ------------*/
bogdanm 0:9b334a45a8ff 174 /* Set HSION bit */
bogdanm 0:9b334a45a8ff 175 RCC->CR |= (uint32_t)0x00000001;
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 #if defined (STM32F051x8) || defined (STM32F058x8)
bogdanm 0:9b334a45a8ff 178 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
bogdanm 0:9b334a45a8ff 179 RCC->CFGR &= (uint32_t)0xF8FFB80C;
bogdanm 0:9b334a45a8ff 180 #else
bogdanm 0:9b334a45a8ff 181 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
bogdanm 0:9b334a45a8ff 182 RCC->CFGR &= (uint32_t)0x08FFB80C;
bogdanm 0:9b334a45a8ff 183 #endif /* STM32F051x8 or STM32F058x8 */
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Reset HSEON, CSSON and PLLON bits */
bogdanm 0:9b334a45a8ff 186 RCC->CR &= (uint32_t)0xFEF6FFFF;
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 189 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
bogdanm 0:9b334a45a8ff 192 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* Reset PREDIV[3:0] bits */
bogdanm 0:9b334a45a8ff 195 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 #if defined (STM32F072xB) || defined (STM32F078xx)
bogdanm 0:9b334a45a8ff 198 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
bogdanm 0:9b334a45a8ff 199 RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
bogdanm 0:9b334a45a8ff 200 #elif defined (STM32F071xB)
bogdanm 0:9b334a45a8ff 201 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
bogdanm 0:9b334a45a8ff 202 RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
bogdanm 0:9b334a45a8ff 203 #elif defined (STM32F091xC) || defined (STM32F098xx)
bogdanm 0:9b334a45a8ff 204 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
bogdanm 0:9b334a45a8ff 205 RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
bogdanm 0:9b334a45a8ff 206 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
bogdanm 0:9b334a45a8ff 207 /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
bogdanm 0:9b334a45a8ff 208 RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
bogdanm 0:9b334a45a8ff 209 #elif defined (STM32F051x8) || defined (STM32F058xx)
bogdanm 0:9b334a45a8ff 210 /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
bogdanm 0:9b334a45a8ff 211 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
bogdanm 0:9b334a45a8ff 212 #elif defined (STM32F042x6) || defined (STM32F048xx)
bogdanm 0:9b334a45a8ff 213 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
bogdanm 0:9b334a45a8ff 214 RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
bogdanm 0:9b334a45a8ff 215 #elif defined (STM32F070x6) || defined (STM32F070xB)
bogdanm 0:9b334a45a8ff 216 /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
bogdanm 0:9b334a45a8ff 217 RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
bogdanm 0:9b334a45a8ff 218 /* Set default USB clock to PLLCLK, since there is no HSI48 */
bogdanm 0:9b334a45a8ff 219 RCC->CFGR3 |= (uint32_t)0x00000080;
bogdanm 0:9b334a45a8ff 220 #else
bogdanm 0:9b334a45a8ff 221 #warning "No target selected"
bogdanm 0:9b334a45a8ff 222 #endif
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /* Reset HSI14 bit */
bogdanm 0:9b334a45a8ff 225 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 228 RCC->CIR = 0x00000000;
mbed_official 43:e3d4af315dd8 229
mbed_official 46:cb4f85f96d35 230 /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
mbed_official 46:cb4f85f96d35 231 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
mbed_official 46:cb4f85f96d35 232
mbed_official 43:e3d4af315dd8 233 /* Configure the Cube driver */
mbed_official 43:e3d4af315dd8 234 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official 43:e3d4af315dd8 235 HAL_Init();
mbed_official 43:e3d4af315dd8 236
mbed_official 43:e3d4af315dd8 237 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 43:e3d4af315dd8 238 AHB/APBx prescalers and Flash settings */
mbed_official 43:e3d4af315dd8 239 SetSysClock();
mbed_official 43:e3d4af315dd8 240
mbed_official 43:e3d4af315dd8 241 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 43:e3d4af315dd8 242 TIM_MST_RESET_ON;
mbed_official 43:e3d4af315dd8 243 TIM_MST_RESET_OFF;
bogdanm 0:9b334a45a8ff 244 }
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /**
bogdanm 0:9b334a45a8ff 247 * @brief Update SystemCoreClock variable according to Clock Register Values.
bogdanm 0:9b334a45a8ff 248 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 249 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 250 * other parameters.
bogdanm 0:9b334a45a8ff 251 *
bogdanm 0:9b334a45a8ff 252 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 253 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 254 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 255 *
bogdanm 0:9b334a45a8ff 256 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 257 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 258 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 259 *
bogdanm 0:9b334a45a8ff 260 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 261 *
bogdanm 0:9b334a45a8ff 262 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 263 *
bogdanm 0:9b334a45a8ff 264 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 265 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 266 *
bogdanm 0:9b334a45a8ff 267 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
bogdanm 0:9b334a45a8ff 268 * 8 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 269 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 270 *
bogdanm 0:9b334a45a8ff 271 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
bogdanm 0:9b334a45a8ff 272 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 273 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 274 * have wrong result.
bogdanm 0:9b334a45a8ff 275 *
bogdanm 0:9b334a45a8ff 276 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 277 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 278 *
bogdanm 0:9b334a45a8ff 279 * @param None
bogdanm 0:9b334a45a8ff 280 * @retval None
bogdanm 0:9b334a45a8ff 281 */
bogdanm 0:9b334a45a8ff 282 void SystemCoreClockUpdate (void)
bogdanm 0:9b334a45a8ff 283 {
bogdanm 0:9b334a45a8ff 284 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 287 tmp = RCC->CFGR & RCC_CFGR_SWS;
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 switch (tmp)
bogdanm 0:9b334a45a8ff 290 {
bogdanm 0:9b334a45a8ff 291 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 292 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 293 break;
bogdanm 0:9b334a45a8ff 294 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
bogdanm 0:9b334a45a8ff 295 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 296 break;
bogdanm 0:9b334a45a8ff 297 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
bogdanm 0:9b334a45a8ff 298 /* Get PLL clock source and multiplication factor ----------------------*/
bogdanm 0:9b334a45a8ff 299 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
bogdanm 0:9b334a45a8ff 300 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
bogdanm 0:9b334a45a8ff 301 pllmull = ( pllmull >> 18) + 2;
bogdanm 0:9b334a45a8ff 302 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
bogdanm 0:9b334a45a8ff 305 {
bogdanm 0:9b334a45a8ff 306 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 307 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 310 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 313 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
bogdanm 0:9b334a45a8ff 316 else
bogdanm 0:9b334a45a8ff 317 {
bogdanm 0:9b334a45a8ff 318 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
bogdanm 0:9b334a45a8ff 319 || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
bogdanm 0:9b334a45a8ff 320 || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
bogdanm 0:9b334a45a8ff 321 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 322 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
bogdanm 0:9b334a45a8ff 323 #else
bogdanm 0:9b334a45a8ff 324 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
bogdanm 0:9b334a45a8ff 325 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
bogdanm 0:9b334a45a8ff 326 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
bogdanm 0:9b334a45a8ff 327 STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
bogdanm 0:9b334a45a8ff 328 STM32F091xC || STM32F098xx || STM32F030xC */
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330 break;
bogdanm 0:9b334a45a8ff 331 default: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 332 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 333 break;
bogdanm 0:9b334a45a8ff 334 }
bogdanm 0:9b334a45a8ff 335 /* Compute HCLK clock frequency ----------------*/
bogdanm 0:9b334a45a8ff 336 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 337 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 338 /* HCLK clock frequency */
bogdanm 0:9b334a45a8ff 339 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 340 }
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /**
bogdanm 0:9b334a45a8ff 343 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 344 * AHB/APBx prescalers and Flash settings
bogdanm 0:9b334a45a8ff 345 * @note This function should be called only once the RCC clock configuration
bogdanm 0:9b334a45a8ff 346 * is reset to the default reset state (done in SystemInit() function).
bogdanm 0:9b334a45a8ff 347 * @param None
bogdanm 0:9b334a45a8ff 348 * @retval None
bogdanm 0:9b334a45a8ff 349 */
bogdanm 0:9b334a45a8ff 350 void SetSysClock(void)
bogdanm 0:9b334a45a8ff 351 {
bogdanm 0:9b334a45a8ff 352 /* 1- Try to start with HSE and external clock */
bogdanm 0:9b334a45a8ff 353 #if USE_PLL_HSE_EXTC != 0
bogdanm 0:9b334a45a8ff 354 if (SetSysClock_PLL_HSE(1) == 0)
bogdanm 0:9b334a45a8ff 355 #endif
bogdanm 0:9b334a45a8ff 356 {
bogdanm 0:9b334a45a8ff 357 /* 2- If fail try to start with HSE and external xtal */
bogdanm 0:9b334a45a8ff 358 #if USE_PLL_HSE_XTAL != 0
bogdanm 0:9b334a45a8ff 359 if (SetSysClock_PLL_HSE(0) == 0)
bogdanm 0:9b334a45a8ff 360 #endif
bogdanm 0:9b334a45a8ff 361 {
bogdanm 0:9b334a45a8ff 362 /* 3- If fail start with HSI clock */
bogdanm 0:9b334a45a8ff 363 if (SetSysClock_PLL_HSI() == 0)
bogdanm 0:9b334a45a8ff 364 {
bogdanm 0:9b334a45a8ff 365 while(1)
bogdanm 0:9b334a45a8ff 366 {
bogdanm 0:9b334a45a8ff 367 // [TODO] Put something here to tell the user that a problem occured...
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369 }
bogdanm 0:9b334a45a8ff 370 }
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 // Output clock on MCO pin(PA8) for debugging purpose
bogdanm 0:9b334a45a8ff 374 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
bogdanm 0:9b334a45a8ff 375 }
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 378 /******************************************************************************/
bogdanm 0:9b334a45a8ff 379 /* PLL (clocked by HSE) used as System clock source */
bogdanm 0:9b334a45a8ff 380 /******************************************************************************/
bogdanm 0:9b334a45a8ff 381 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
bogdanm 0:9b334a45a8ff 382 {
bogdanm 0:9b334a45a8ff 383 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
bogdanm 0:9b334a45a8ff 384 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
bogdanm 0:9b334a45a8ff 385 //Select HSI as system clock source to allow modification of the PLL configuration
bogdanm 0:9b334a45a8ff 386 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
bogdanm 0:9b334a45a8ff 387 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
bogdanm 0:9b334a45a8ff 388 if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
bogdanm 0:9b334a45a8ff 389 {
bogdanm 0:9b334a45a8ff 390 return 0; // FAIL
bogdanm 0:9b334a45a8ff 391 }
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 // Select HSE oscillator as PLL source
bogdanm 0:9b334a45a8ff 395 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 396 if (bypass == 0) {
bogdanm 0:9b334a45a8ff 397 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
bogdanm 0:9b334a45a8ff 398 } else {
bogdanm 0:9b334a45a8ff 399 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
bogdanm 0:9b334a45a8ff 400 }
bogdanm 0:9b334a45a8ff 401 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 402 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
bogdanm 0:9b334a45a8ff 403 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
bogdanm 0:9b334a45a8ff 404 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
bogdanm 0:9b334a45a8ff 405 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
bogdanm 0:9b334a45a8ff 406 return 0; // FAIL
bogdanm 0:9b334a45a8ff 407 }
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
bogdanm 0:9b334a45a8ff 410 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
bogdanm 0:9b334a45a8ff 411 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
bogdanm 0:9b334a45a8ff 412 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
bogdanm 0:9b334a45a8ff 413 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
bogdanm 0:9b334a45a8ff 414 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
bogdanm 0:9b334a45a8ff 415 return 0; // FAIL
bogdanm 0:9b334a45a8ff 416 }
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 return 1; // OK
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422 #endif
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /******************************************************************************/
bogdanm 0:9b334a45a8ff 425 /* PLL (clocked by HSI) used as System clock source */
bogdanm 0:9b334a45a8ff 426 /******************************************************************************/
bogdanm 0:9b334a45a8ff 427 uint8_t SetSysClock_PLL_HSI(void)
bogdanm 0:9b334a45a8ff 428 {
bogdanm 0:9b334a45a8ff 429 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 430 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
mbed_official 56:05912f50f004 433 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
mbed_official 56:05912f50f004 434 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 56:05912f50f004 435 RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
mbed_official 56:05912f50f004 436 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 56:05912f50f004 437 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
mbed_official 56:05912f50f004 438 RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
mbed_official 56:05912f50f004 439 RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
mbed_official 56:05912f50f004 440 RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
mbed_official 56:05912f50f004 441 RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
mbed_official 56:05912f50f004 442 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 56:05912f50f004 443 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
mbed_official 56:05912f50f004 444 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
mbed_official 56:05912f50f004 445 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
bogdanm 0:9b334a45a8ff 446 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
bogdanm 0:9b334a45a8ff 447 return 0; // FAIL
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
bogdanm 0:9b334a45a8ff 451 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
bogdanm 0:9b334a45a8ff 452 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
bogdanm 0:9b334a45a8ff 453 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
bogdanm 0:9b334a45a8ff 454 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
bogdanm 0:9b334a45a8ff 455 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
bogdanm 0:9b334a45a8ff 456 return 0; // FAIL
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 return 1; // OK
bogdanm 0:9b334a45a8ff 462 }
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /**
bogdanm 0:9b334a45a8ff 465 * @}
bogdanm 0:9b334a45a8ff 466 */
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /**
bogdanm 0:9b334a45a8ff 469 * @}
bogdanm 0:9b334a45a8ff 470 */
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 /**
bogdanm 0:9b334a45a8ff 473 * @}
bogdanm 0:9b334a45a8ff 474 */
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 0:9b334a45a8ff 477