mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f031x6.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V2.2.2
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief CMSIS STM32F031x4/STM32F031x6 devices Peripheral Access Layer Header File.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file contains:
bogdanm	0:9b334a45a8ff	10	* - Data structures and the address mapping for all peripherals
bogdanm	0:9b334a45a8ff	11	* - Peripheral's registers declarations and bits definition
bogdanm	0:9b334a45a8ff	12	* - Macros to access peripherals registers hardware
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	******************************************************************************
bogdanm	0:9b334a45a8ff	15	* @attention
bogdanm	0:9b334a45a8ff	16	*
bogdanm	0:9b334a45a8ff	17	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	18	*
bogdanm	0:9b334a45a8ff	19	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	20	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	21	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	22	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	24	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	25	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	27	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	28	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	29	*
bogdanm	0:9b334a45a8ff	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	40	*
bogdanm	0:9b334a45a8ff	41	******************************************************************************
bogdanm	0:9b334a45a8ff	42	*/
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	/** @addtogroup CMSIS_Device
bogdanm	0:9b334a45a8ff	45	* @{
bogdanm	0:9b334a45a8ff	46	*/
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	/** @addtogroup stm32f031x6
bogdanm	0:9b334a45a8ff	49	* @{
bogdanm	0:9b334a45a8ff	50	*/
bogdanm	0:9b334a45a8ff	51
bogdanm	0:9b334a45a8ff	52	#ifndef __STM32F031x6_H
bogdanm	0:9b334a45a8ff	53	#define __STM32F031x6_H
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	56	extern "C" {
bogdanm	0:9b334a45a8ff	57	#endif /* __cplusplus */
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	/** @addtogroup Configuration_section_for_CMSIS
bogdanm	0:9b334a45a8ff	60	* @{
bogdanm	0:9b334a45a8ff	61	*/
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	#define __CM0_REV 0 /!< Core Revision r0p0 /
bogdanm	0:9b334a45a8ff	66	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
bogdanm	0:9b334a45a8ff	67	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
bogdanm	0:9b334a45a8ff	68	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	/**
bogdanm	0:9b334a45a8ff	71	* @}
bogdanm	0:9b334a45a8ff	72	*/
bogdanm	0:9b334a45a8ff	73
bogdanm	0:9b334a45a8ff	74	/** @addtogroup Peripheral_interrupt_number_definition
bogdanm	0:9b334a45a8ff	75	* @{
bogdanm	0:9b334a45a8ff	76	*/
bogdanm	0:9b334a45a8ff	77
bogdanm	0:9b334a45a8ff	78	/**
bogdanm	0:9b334a45a8ff	79	* @brief STM32F031x4/STM32F031x6 device Interrupt Number Definition
bogdanm	0:9b334a45a8ff	80	*/
bogdanm	0:9b334a45a8ff	81	typedef enum
bogdanm	0:9b334a45a8ff	82	{
bogdanm	0:9b334a45a8ff	83	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
bogdanm	0:9b334a45a8ff	84	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
bogdanm	0:9b334a45a8ff	85	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
bogdanm	0:9b334a45a8ff	86	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
bogdanm	0:9b334a45a8ff	87	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
bogdanm	0:9b334a45a8ff	88	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
bogdanm	0:9b334a45a8ff	89
bogdanm	0:9b334a45a8ff	90	/**** STM32F031x4/STM32F031x6 specific Interrupt Numbers ************************************************/
bogdanm	0:9b334a45a8ff	91	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
bogdanm	0:9b334a45a8ff	92	PVD_IRQn = 1, /!< PVD Interrupts through EXTI Lines 16 /
bogdanm	0:9b334a45a8ff	93	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
bogdanm	0:9b334a45a8ff	94	FLASH_IRQn = 3, /!< FLASH global Interrupt /
bogdanm	0:9b334a45a8ff	95	RCC_IRQn = 4, /!< RCC global Interrupt /
bogdanm	0:9b334a45a8ff	96	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
bogdanm	0:9b334a45a8ff	97	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
bogdanm	0:9b334a45a8ff	98	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
bogdanm	0:9b334a45a8ff	99	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
bogdanm	0:9b334a45a8ff	100	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
bogdanm	0:9b334a45a8ff	101	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
bogdanm	0:9b334a45a8ff	102	ADC1_IRQn = 12, /!< ADC1 global Interrupt /
bogdanm	0:9b334a45a8ff	103	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
bogdanm	0:9b334a45a8ff	104	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
bogdanm	0:9b334a45a8ff	105	TIM2_IRQn = 15, /!< TIM2 global Interrupt /
bogdanm	0:9b334a45a8ff	106	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
bogdanm	0:9b334a45a8ff	107	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
bogdanm	0:9b334a45a8ff	108	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
bogdanm	0:9b334a45a8ff	109	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
bogdanm	0:9b334a45a8ff	110	I2C1_IRQn = 23, /!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) /
bogdanm	0:9b334a45a8ff	111	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
bogdanm	0:9b334a45a8ff	112	USART1_IRQn = 27 /!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) /
bogdanm	0:9b334a45a8ff	113	} IRQn_Type;
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	/**
bogdanm	0:9b334a45a8ff	116	* @}
bogdanm	0:9b334a45a8ff	117	*/
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
bogdanm	0:9b334a45a8ff	120	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
bogdanm	0:9b334a45a8ff	121	#include <stdint.h>
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	/** @addtogroup Peripheral_registers_structures
bogdanm	0:9b334a45a8ff	124	* @{
bogdanm	0:9b334a45a8ff	125	*/
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	/**
bogdanm	0:9b334a45a8ff	128	* @brief Analog to Digital Converter
bogdanm	0:9b334a45a8ff	129	*/
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	typedef struct
bogdanm	0:9b334a45a8ff	132	{
bogdanm	0:9b334a45a8ff	133	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
bogdanm	0:9b334a45a8ff	134	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
bogdanm	0:9b334a45a8ff	135	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
bogdanm	0:9b334a45a8ff	136	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
bogdanm	0:9b334a45a8ff	137	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
bogdanm	0:9b334a45a8ff	138	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
bogdanm	0:9b334a45a8ff	139	uint32_t RESERVED1; /!< Reserved, 0x18 /
bogdanm	0:9b334a45a8ff	140	uint32_t RESERVED2; /!< Reserved, 0x1C /
bogdanm	0:9b334a45a8ff	141	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
bogdanm	0:9b334a45a8ff	142	uint32_t RESERVED3; /!< Reserved, 0x24 /
bogdanm	0:9b334a45a8ff	143	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
bogdanm	0:9b334a45a8ff	144	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
bogdanm	0:9b334a45a8ff	145	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
bogdanm	0:9b334a45a8ff	146	}ADC_TypeDef;
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	typedef struct
bogdanm	0:9b334a45a8ff	149	{
bogdanm	0:9b334a45a8ff	150	__IO uint32_t CCR;
bogdanm	0:9b334a45a8ff	151	}ADC_Common_TypeDef;
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/**
bogdanm	0:9b334a45a8ff	154	* @brief CRC calculation unit
bogdanm	0:9b334a45a8ff	155	*/
bogdanm	0:9b334a45a8ff	156
bogdanm	0:9b334a45a8ff	157	typedef struct
bogdanm	0:9b334a45a8ff	158	{
bogdanm	0:9b334a45a8ff	159	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	160	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	161	uint8_t RESERVED0; /!< Reserved, 0x05 /
bogdanm	0:9b334a45a8ff	162	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	0:9b334a45a8ff	163	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	164	uint32_t RESERVED2; /!< Reserved, 0x0C /
bogdanm	0:9b334a45a8ff	165	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	166	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	167	}CRC_TypeDef;
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/**
bogdanm	0:9b334a45a8ff	170	* @brief Debug MCU
bogdanm	0:9b334a45a8ff	171	*/
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	typedef struct
bogdanm	0:9b334a45a8ff	174	{
bogdanm	0:9b334a45a8ff	175	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	176	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	177	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	178	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	179	}DBGMCU_TypeDef;
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	/**
bogdanm	0:9b334a45a8ff	182	* @brief DMA Controller
bogdanm	0:9b334a45a8ff	183	*/
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	typedef struct
bogdanm	0:9b334a45a8ff	186	{
bogdanm	0:9b334a45a8ff	187	__IO uint32_t CCR; /!< DMA channel x configuration register /
bogdanm	0:9b334a45a8ff	188	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
bogdanm	0:9b334a45a8ff	189	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
bogdanm	0:9b334a45a8ff	190	__IO uint32_t CMAR; /!< DMA channel x memory address register /
bogdanm	0:9b334a45a8ff	191	}DMA_Channel_TypeDef;
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	typedef struct
bogdanm	0:9b334a45a8ff	194	{
bogdanm	0:9b334a45a8ff	195	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	196	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	197	}DMA_TypeDef;
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	/**
bogdanm	0:9b334a45a8ff	200	* @brief External Interrupt/Event Controller
bogdanm	0:9b334a45a8ff	201	*/
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	typedef struct
bogdanm	0:9b334a45a8ff	204	{
bogdanm	0:9b334a45a8ff	205	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	206	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	207	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	208	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	209	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	210	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	211	}EXTI_TypeDef;
bogdanm	0:9b334a45a8ff	212
bogdanm	0:9b334a45a8ff	213	/**
bogdanm	0:9b334a45a8ff	214	* @brief FLASH Registers
bogdanm	0:9b334a45a8ff	215	*/
bogdanm	0:9b334a45a8ff	216	typedef struct
bogdanm	0:9b334a45a8ff	217	{
bogdanm	0:9b334a45a8ff	218	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	219	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	220	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	221	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	222	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	223	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	224	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
bogdanm	0:9b334a45a8ff	225	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	226	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	227	}FLASH_TypeDef;
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230	/**
bogdanm	0:9b334a45a8ff	231	* @brief Option Bytes Registers
bogdanm	0:9b334a45a8ff	232	*/
bogdanm	0:9b334a45a8ff	233	typedef struct
bogdanm	0:9b334a45a8ff	234	{
bogdanm	0:9b334a45a8ff	235	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	236	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
bogdanm	0:9b334a45a8ff	237	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	238	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
bogdanm	0:9b334a45a8ff	239	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	240	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
bogdanm	0:9b334a45a8ff	241	}OB_TypeDef;
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/**
bogdanm	0:9b334a45a8ff	244	* @brief General Purpose I/O
bogdanm	0:9b334a45a8ff	245	*/
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	typedef struct
bogdanm	0:9b334a45a8ff	248	{
bogdanm	0:9b334a45a8ff	249	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	250	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	251	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	252	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	253	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	254	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	255	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
bogdanm	0:9b334a45a8ff	256	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	257	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
bogdanm	0:9b334a45a8ff	258	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	259	}GPIO_TypeDef;
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/**
bogdanm	0:9b334a45a8ff	262	* @brief SysTem Configuration
bogdanm	0:9b334a45a8ff	263	*/
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	typedef struct
bogdanm	0:9b334a45a8ff	266	{
bogdanm	0:9b334a45a8ff	267	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	268	uint32_t RESERVED; /!< Reserved, 0x04 /
bogdanm	0:9b334a45a8ff	269	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
bogdanm	0:9b334a45a8ff	270	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	271	}SYSCFG_TypeDef;
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/**
bogdanm	0:9b334a45a8ff	274	* @brief Inter-integrated Circuit Interface
bogdanm	0:9b334a45a8ff	275	*/
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	typedef struct
bogdanm	0:9b334a45a8ff	278	{
bogdanm	0:9b334a45a8ff	279	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	280	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	281	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	282	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	283	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	284	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	285	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	286	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	287	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	288	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	289	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	290	}I2C_TypeDef;
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/**
bogdanm	0:9b334a45a8ff	293	* @brief Independent WATCHDOG
bogdanm	0:9b334a45a8ff	294	*/
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	typedef struct
bogdanm	0:9b334a45a8ff	297	{
bogdanm	0:9b334a45a8ff	298	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	299	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	300	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	301	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	302	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	303	}IWDG_TypeDef;
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/**
bogdanm	0:9b334a45a8ff	306	* @brief Power Control
bogdanm	0:9b334a45a8ff	307	*/
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	typedef struct
bogdanm	0:9b334a45a8ff	310	{
bogdanm	0:9b334a45a8ff	311	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	312	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	313	}PWR_TypeDef;
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/**
bogdanm	0:9b334a45a8ff	316	* @brief Reset and Clock Control
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	typedef struct
bogdanm	0:9b334a45a8ff	320	{
bogdanm	0:9b334a45a8ff	321	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	322	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	323	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	324	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	325	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	326	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	327	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	328	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	329	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	330	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	331	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	332	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	333	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	334	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	335	}RCC_TypeDef;
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/**
bogdanm	0:9b334a45a8ff	338	* @brief Real-Time Clock
bogdanm	0:9b334a45a8ff	339	*/
bogdanm	0:9b334a45a8ff	340	typedef struct
bogdanm	0:9b334a45a8ff	341	{
bogdanm	0:9b334a45a8ff	342	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	343	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	344	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	345	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	346	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	347	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	348	uint32_t RESERVED2; /!< Reserved, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	349	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	350	uint32_t RESERVED3; /!< Reserved, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	351	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	352	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	353	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	354	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	355	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	356	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	357	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	358	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	359	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	360	uint32_t RESERVED4; /!< Reserved, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	361	uint32_t RESERVED5; /!< Reserved, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	362	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	363	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	364	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	365	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	366	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	367	}RTC_TypeDef;
bogdanm	0:9b334a45a8ff	368
bogdanm	0:9b334a45a8ff	369	/**
bogdanm	0:9b334a45a8ff	370	* @brief Serial Peripheral Interface
bogdanm	0:9b334a45a8ff	371	*/
bogdanm	0:9b334a45a8ff	372
bogdanm	0:9b334a45a8ff	373	typedef struct
bogdanm	0:9b334a45a8ff	374	{
bogdanm	0:9b334a45a8ff	375	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	376	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	377	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	378	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	379	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	380	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	381	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	382	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	383	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	384	}SPI_TypeDef;
bogdanm	0:9b334a45a8ff	385
bogdanm	0:9b334a45a8ff	386	/**
bogdanm	0:9b334a45a8ff	387	* @brief TIM
bogdanm	0:9b334a45a8ff	388	*/
bogdanm	0:9b334a45a8ff	389	typedef struct
bogdanm	0:9b334a45a8ff	390	{
bogdanm	0:9b334a45a8ff	391	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	392	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	393	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	394	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	395	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	396	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	397	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	398	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	399	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	400	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	401	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	402	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	403	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	404	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	405	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	406	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	407	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	408	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	409	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	410	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	411	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	412	}TIM_TypeDef;
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	/**
bogdanm	0:9b334a45a8ff	415	* @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm	0:9b334a45a8ff	416	*/
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	typedef struct
bogdanm	0:9b334a45a8ff	419	{
bogdanm	0:9b334a45a8ff	420	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	421	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	422	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	423	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	424	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	425	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	426	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	427	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	428	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	429	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	430	uint16_t RESERVED1; /!< Reserved, 0x26 /
bogdanm	0:9b334a45a8ff	431	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	432	uint16_t RESERVED2; /!< Reserved, 0x2A /
bogdanm	0:9b334a45a8ff	433	}USART_TypeDef;
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	/**
bogdanm	0:9b334a45a8ff	436	* @brief Window WATCHDOG
bogdanm	0:9b334a45a8ff	437	*/
bogdanm	0:9b334a45a8ff	438	typedef struct
bogdanm	0:9b334a45a8ff	439	{
bogdanm	0:9b334a45a8ff	440	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	441	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	442	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	443	}WWDG_TypeDef;
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/**
bogdanm	0:9b334a45a8ff	446	* @}
bogdanm	0:9b334a45a8ff	447	*/
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	/** @addtogroup Peripheral_memory_map
bogdanm	0:9b334a45a8ff	450	* @{
bogdanm	0:9b334a45a8ff	451	*/
bogdanm	0:9b334a45a8ff	452
bogdanm	0:9b334a45a8ff	453	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
bogdanm	0:9b334a45a8ff	454	#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /!< FLASH END address of bank1 /
bogdanm	0:9b334a45a8ff	455	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
bogdanm	0:9b334a45a8ff	456	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/!< Peripheral memory map /
bogdanm	0:9b334a45a8ff	459	#define APBPERIPH_BASE PERIPH_BASE
bogdanm	0:9b334a45a8ff	460	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm	0:9b334a45a8ff	461	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
bogdanm	0:9b334a45a8ff	464	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
bogdanm	0:9b334a45a8ff	465	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
bogdanm	0:9b334a45a8ff	466	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
bogdanm	0:9b334a45a8ff	467	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
bogdanm	0:9b334a45a8ff	468	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
bogdanm	0:9b334a45a8ff	469	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
bogdanm	0:9b334a45a8ff	470	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
bogdanm	0:9b334a45a8ff	471	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
bogdanm	0:9b334a45a8ff	472	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
bogdanm	0:9b334a45a8ff	473	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
bogdanm	0:9b334a45a8ff	474	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
bogdanm	0:9b334a45a8ff	475	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
bogdanm	0:9b334a45a8ff	476	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
bogdanm	0:9b334a45a8ff	477	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
bogdanm	0:9b334a45a8ff	478	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
bogdanm	0:9b334a45a8ff	479	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
bogdanm	0:9b334a45a8ff	480	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
bogdanm	0:9b334a45a8ff	481
bogdanm	0:9b334a45a8ff	482	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
bogdanm	0:9b334a45a8ff	483	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
bogdanm	0:9b334a45a8ff	484	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
bogdanm	0:9b334a45a8ff	485	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
bogdanm	0:9b334a45a8ff	486	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
bogdanm	0:9b334a45a8ff	487	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
bogdanm	0:9b334a45a8ff	490	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
bogdanm	0:9b334a45a8ff	491	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
bogdanm	0:9b334a45a8ff	492	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
bogdanm	0:9b334a45a8ff	495	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
bogdanm	0:9b334a45a8ff	496	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
bogdanm	0:9b334a45a8ff	497	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/**
bogdanm	0:9b334a45a8ff	500	* @}
bogdanm	0:9b334a45a8ff	501	*/
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/** @addtogroup Peripheral_declaration
bogdanm	0:9b334a45a8ff	504	* @{
bogdanm	0:9b334a45a8ff	505	*/
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm	0:9b334a45a8ff	508	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm	0:9b334a45a8ff	509	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm	0:9b334a45a8ff	510	#define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm	0:9b334a45a8ff	511	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm	0:9b334a45a8ff	512	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm	0:9b334a45a8ff	513	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm	0:9b334a45a8ff	514	#define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm	0:9b334a45a8ff	515	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm	0:9b334a45a8ff	516	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm	0:9b334a45a8ff	517	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm	0:9b334a45a8ff	518	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm	0:9b334a45a8ff	519	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm	0:9b334a45a8ff	520	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm	0:9b334a45a8ff	521	#define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm	0:9b334a45a8ff	522	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm	0:9b334a45a8ff	523	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm	0:9b334a45a8ff	524	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm	0:9b334a45a8ff	525	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm	0:9b334a45a8ff	526	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm	0:9b334a45a8ff	527	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm	0:9b334a45a8ff	528	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm	0:9b334a45a8ff	529	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm	0:9b334a45a8ff	530	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm	0:9b334a45a8ff	531	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm	0:9b334a45a8ff	532	#define OB ((OB_TypeDef *) OB_BASE)
bogdanm	0:9b334a45a8ff	533	#define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm	0:9b334a45a8ff	534	#define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm	0:9b334a45a8ff	535	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm	0:9b334a45a8ff	536	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm	0:9b334a45a8ff	537	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm	0:9b334a45a8ff	538	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm	0:9b334a45a8ff	539	/**
bogdanm	0:9b334a45a8ff	540	* @}
bogdanm	0:9b334a45a8ff	541	*/
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	/** @addtogroup Exported_constants
bogdanm	0:9b334a45a8ff	544	* @{
bogdanm	0:9b334a45a8ff	545	*/
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	/** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm	0:9b334a45a8ff	548	* @{
bogdanm	0:9b334a45a8ff	549	*/
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/******************************************************************************/
bogdanm	0:9b334a45a8ff	552	/* Peripheral Registers Bits Definition */
bogdanm	0:9b334a45a8ff	553	/******************************************************************************/
bogdanm	0:9b334a45a8ff	554	/******************************************************************************/
bogdanm	0:9b334a45a8ff	555	/* */
bogdanm	0:9b334a45a8ff	556	/* Analog to Digital Converter (ADC) */
bogdanm	0:9b334a45a8ff	557	/* */
bogdanm	0:9b334a45a8ff	558	/******************************************************************************/
bogdanm	0:9b334a45a8ff	559	/****************** Bits definition for ADC_ISR register ****************/
bogdanm	0:9b334a45a8ff	560	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
bogdanm	0:9b334a45a8ff	561	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
bogdanm	0:9b334a45a8ff	562	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
bogdanm	0:9b334a45a8ff	563	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
bogdanm	0:9b334a45a8ff	564	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
bogdanm	0:9b334a45a8ff	565	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/* Old EOSEQ bit definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	568	#define ADC_ISR_EOS ADC_ISR_EOSEQ
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	/****************** Bits definition for ADC_IER register ****************/
bogdanm	0:9b334a45a8ff	571	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
bogdanm	0:9b334a45a8ff	572	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
bogdanm	0:9b334a45a8ff	573	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
bogdanm	0:9b334a45a8ff	574	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
bogdanm	0:9b334a45a8ff	575	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
bogdanm	0:9b334a45a8ff	576	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/* Old EOSEQIE bit definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	579	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/****************** Bits definition for ADC_CR register *****************/
bogdanm	0:9b334a45a8ff	582	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
bogdanm	0:9b334a45a8ff	583	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
bogdanm	0:9b334a45a8ff	584	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
bogdanm	0:9b334a45a8ff	585	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
bogdanm	0:9b334a45a8ff	586	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
bogdanm	0:9b334a45a8ff	587
bogdanm	0:9b334a45a8ff	588	/***************** Bits definition for ADC_CFGR1 register ***************/
bogdanm	0:9b334a45a8ff	589	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
bogdanm	0:9b334a45a8ff	590	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	591	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	592	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	593	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	594	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	595	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
bogdanm	0:9b334a45a8ff	596	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
bogdanm	0:9b334a45a8ff	597	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
bogdanm	0:9b334a45a8ff	598	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
bogdanm	0:9b334a45a8ff	599	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
bogdanm	0:9b334a45a8ff	600	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
bogdanm	0:9b334a45a8ff	601	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
bogdanm	0:9b334a45a8ff	602	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
bogdanm	0:9b334a45a8ff	603	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	604	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	605	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
bogdanm	0:9b334a45a8ff	606	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	607	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	608	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	609	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
bogdanm	0:9b334a45a8ff	610	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
bogdanm	0:9b334a45a8ff	611	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	612	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	613	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
bogdanm	0:9b334a45a8ff	614	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
bogdanm	0:9b334a45a8ff	615	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	/* Old WAIT bit definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	618	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	/***************** Bits definition for ADC_CFGR2 register ***************/
bogdanm	0:9b334a45a8ff	621	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
bogdanm	0:9b334a45a8ff	622	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
bogdanm	0:9b334a45a8ff	623	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	/* Old bit definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	626	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
bogdanm	0:9b334a45a8ff	627	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	/**************** Bit definition for ADC_SMPR register ******************/
bogdanm	0:9b334a45a8ff	630	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
bogdanm	0:9b334a45a8ff	631	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	632	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	633	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635	/* Old bit definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	636	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
bogdanm	0:9b334a45a8ff	637	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
bogdanm	0:9b334a45a8ff	638	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
bogdanm	0:9b334a45a8ff	639	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
bogdanm	0:9b334a45a8ff	640
bogdanm	0:9b334a45a8ff	641	/***************** Bit definition for ADC_TR register ******************/
bogdanm	0:9b334a45a8ff	642	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
bogdanm	0:9b334a45a8ff	643	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
bogdanm	0:9b334a45a8ff	644
bogdanm	0:9b334a45a8ff	645	/* Old bit definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	646	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
bogdanm	0:9b334a45a8ff	647	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	/**************** Bit definition for ADC_CHSELR register ****************/
bogdanm	0:9b334a45a8ff	650	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
bogdanm	0:9b334a45a8ff	651	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
bogdanm	0:9b334a45a8ff	652	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
bogdanm	0:9b334a45a8ff	653	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
bogdanm	0:9b334a45a8ff	654	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
bogdanm	0:9b334a45a8ff	655	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
bogdanm	0:9b334a45a8ff	656	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
bogdanm	0:9b334a45a8ff	657	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
bogdanm	0:9b334a45a8ff	658	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
bogdanm	0:9b334a45a8ff	659	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
bogdanm	0:9b334a45a8ff	660	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
bogdanm	0:9b334a45a8ff	661	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
bogdanm	0:9b334a45a8ff	662	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
bogdanm	0:9b334a45a8ff	663	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
bogdanm	0:9b334a45a8ff	664	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
bogdanm	0:9b334a45a8ff	665	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
bogdanm	0:9b334a45a8ff	666	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
bogdanm	0:9b334a45a8ff	667	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
bogdanm	0:9b334a45a8ff	668	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	/****************** Bit definition for ADC_DR register ******************/
bogdanm	0:9b334a45a8ff	671	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	/***************** Bit definition for ADC_CCR register ******************/
bogdanm	0:9b334a45a8ff	674	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< Voltage battery enable /
bogdanm	0:9b334a45a8ff	675	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
bogdanm	0:9b334a45a8ff	676	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	/******************************************************************************/
bogdanm	0:9b334a45a8ff	679	/* */
bogdanm	0:9b334a45a8ff	680	/* CRC calculation unit (CRC) */
bogdanm	0:9b334a45a8ff	681	/* */
bogdanm	0:9b334a45a8ff	682	/******************************************************************************/
bogdanm	0:9b334a45a8ff	683	/***************** Bit definition for CRC_DR register *******************/
bogdanm	0:9b334a45a8ff	684	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	/***************** Bit definition for CRC_IDR register ******************/
bogdanm	0:9b334a45a8ff	687	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
bogdanm	0:9b334a45a8ff	688
bogdanm	0:9b334a45a8ff	689	/****************** Bit definition for CRC_CR register ******************/
bogdanm	0:9b334a45a8ff	690	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
bogdanm	0:9b334a45a8ff	691	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
bogdanm	0:9b334a45a8ff	692	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
bogdanm	0:9b334a45a8ff	693	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
bogdanm	0:9b334a45a8ff	694	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/***************** Bit definition for CRC_INIT register *****************/
bogdanm	0:9b334a45a8ff	697	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
bogdanm	0:9b334a45a8ff	698
bogdanm	0:9b334a45a8ff	699	/******************************************************************************/
bogdanm	0:9b334a45a8ff	700	/* */
bogdanm	0:9b334a45a8ff	701	/* Debug MCU (DBGMCU) */
bogdanm	0:9b334a45a8ff	702	/* */
bogdanm	0:9b334a45a8ff	703	/******************************************************************************/
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	/************** Bit definition for DBGMCU_IDCODE register ***************/
bogdanm	0:9b334a45a8ff	706	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
bogdanm	0:9b334a45a8ff	709	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	710	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	711	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	712	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	713	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	714	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	715	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
bogdanm	0:9b334a45a8ff	716	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
bogdanm	0:9b334a45a8ff	717	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
bogdanm	0:9b334a45a8ff	718	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
bogdanm	0:9b334a45a8ff	719	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
bogdanm	0:9b334a45a8ff	720	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
bogdanm	0:9b334a45a8ff	721	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
bogdanm	0:9b334a45a8ff	722	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
bogdanm	0:9b334a45a8ff	723	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
bogdanm	0:9b334a45a8ff	724	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	/**************** Bit definition for DBGMCU_CR register *****************/
bogdanm	0:9b334a45a8ff	727	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
bogdanm	0:9b334a45a8ff	728	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
bogdanm	0:9b334a45a8ff	731	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	732	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	733	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	734	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
bogdanm	0:9b334a45a8ff	735	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
bogdanm	0:9b334a45a8ff	736	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
bogdanm	0:9b334a45a8ff	737	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
bogdanm	0:9b334a45a8ff	740	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	741	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	742	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/******************************************************************************/
bogdanm	0:9b334a45a8ff	745	/* */
bogdanm	0:9b334a45a8ff	746	/* DMA Controller (DMA) */
bogdanm	0:9b334a45a8ff	747	/* */
bogdanm	0:9b334a45a8ff	748	/******************************************************************************/
bogdanm	0:9b334a45a8ff	749	/***************** Bit definition for DMA_ISR register ******************/
bogdanm	0:9b334a45a8ff	750	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
bogdanm	0:9b334a45a8ff	751	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	752	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
bogdanm	0:9b334a45a8ff	753	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
bogdanm	0:9b334a45a8ff	754	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
bogdanm	0:9b334a45a8ff	755	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	756	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
bogdanm	0:9b334a45a8ff	757	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
bogdanm	0:9b334a45a8ff	758	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
bogdanm	0:9b334a45a8ff	759	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	760	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
bogdanm	0:9b334a45a8ff	761	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
bogdanm	0:9b334a45a8ff	762	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
bogdanm	0:9b334a45a8ff	763	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	764	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
bogdanm	0:9b334a45a8ff	765	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
bogdanm	0:9b334a45a8ff	766	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
bogdanm	0:9b334a45a8ff	767	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	768	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
bogdanm	0:9b334a45a8ff	769	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	/***************** Bit definition for DMA_IFCR register *****************/
bogdanm	0:9b334a45a8ff	772	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
bogdanm	0:9b334a45a8ff	773	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	774	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
bogdanm	0:9b334a45a8ff	775	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
bogdanm	0:9b334a45a8ff	776	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
bogdanm	0:9b334a45a8ff	777	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	778	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
bogdanm	0:9b334a45a8ff	779	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
bogdanm	0:9b334a45a8ff	780	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
bogdanm	0:9b334a45a8ff	781	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	782	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
bogdanm	0:9b334a45a8ff	783	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
bogdanm	0:9b334a45a8ff	784	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
bogdanm	0:9b334a45a8ff	785	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	786	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
bogdanm	0:9b334a45a8ff	787	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
bogdanm	0:9b334a45a8ff	788	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
bogdanm	0:9b334a45a8ff	789	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	790	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
bogdanm	0:9b334a45a8ff	791	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793	/***************** Bit definition for DMA_CCR register ******************/
bogdanm	0:9b334a45a8ff	794	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
bogdanm	0:9b334a45a8ff	795	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
bogdanm	0:9b334a45a8ff	796	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
bogdanm	0:9b334a45a8ff	797	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
bogdanm	0:9b334a45a8ff	798	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
bogdanm	0:9b334a45a8ff	799	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
bogdanm	0:9b334a45a8ff	800	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
bogdanm	0:9b334a45a8ff	801	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
bogdanm	0:9b334a45a8ff	802
bogdanm	0:9b334a45a8ff	803	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
bogdanm	0:9b334a45a8ff	804	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	805	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	806
bogdanm	0:9b334a45a8ff	807	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
bogdanm	0:9b334a45a8ff	808	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	809	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
bogdanm	0:9b334a45a8ff	812	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	813	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	814
bogdanm	0:9b334a45a8ff	815	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/**************** Bit definition for DMA_CNDTR register *****************/
bogdanm	0:9b334a45a8ff	818	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	/**************** Bit definition for DMA_CPAR register ******************/
bogdanm	0:9b334a45a8ff	821	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/**************** Bit definition for DMA_CMAR register ******************/
bogdanm	0:9b334a45a8ff	824	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
bogdanm	0:9b334a45a8ff	825
bogdanm	0:9b334a45a8ff	826	/******************************************************************************/
bogdanm	0:9b334a45a8ff	827	/* */
bogdanm	0:9b334a45a8ff	828	/* External Interrupt/Event Controller (EXTI) */
bogdanm	0:9b334a45a8ff	829	/* */
bogdanm	0:9b334a45a8ff	830	/******************************************************************************/
bogdanm	0:9b334a45a8ff	831	/***************** Bit definition for EXTI_IMR register *****************/
bogdanm	0:9b334a45a8ff	832	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
bogdanm	0:9b334a45a8ff	833	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
bogdanm	0:9b334a45a8ff	834	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
bogdanm	0:9b334a45a8ff	835	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
bogdanm	0:9b334a45a8ff	836	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
bogdanm	0:9b334a45a8ff	837	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
bogdanm	0:9b334a45a8ff	838	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
bogdanm	0:9b334a45a8ff	839	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
bogdanm	0:9b334a45a8ff	840	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
bogdanm	0:9b334a45a8ff	841	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
bogdanm	0:9b334a45a8ff	842	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
bogdanm	0:9b334a45a8ff	843	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
bogdanm	0:9b334a45a8ff	844	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
bogdanm	0:9b334a45a8ff	845	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
bogdanm	0:9b334a45a8ff	846	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
bogdanm	0:9b334a45a8ff	847	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
bogdanm	0:9b334a45a8ff	848	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
bogdanm	0:9b334a45a8ff	849	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
bogdanm	0:9b334a45a8ff	850	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
bogdanm	0:9b334a45a8ff	851	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
bogdanm	0:9b334a45a8ff	852	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
bogdanm	0:9b334a45a8ff	853	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
bogdanm	0:9b334a45a8ff	854	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
bogdanm	0:9b334a45a8ff	855	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/**************** Bit definition for EXTI_EMR register ******************/
bogdanm	0:9b334a45a8ff	858	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
bogdanm	0:9b334a45a8ff	859	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
bogdanm	0:9b334a45a8ff	860	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
bogdanm	0:9b334a45a8ff	861	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
bogdanm	0:9b334a45a8ff	862	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
bogdanm	0:9b334a45a8ff	863	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
bogdanm	0:9b334a45a8ff	864	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
bogdanm	0:9b334a45a8ff	865	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
bogdanm	0:9b334a45a8ff	866	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
bogdanm	0:9b334a45a8ff	867	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
bogdanm	0:9b334a45a8ff	868	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
bogdanm	0:9b334a45a8ff	869	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
bogdanm	0:9b334a45a8ff	870	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
bogdanm	0:9b334a45a8ff	871	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
bogdanm	0:9b334a45a8ff	872	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
bogdanm	0:9b334a45a8ff	873	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
bogdanm	0:9b334a45a8ff	874	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
bogdanm	0:9b334a45a8ff	875	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
bogdanm	0:9b334a45a8ff	876	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
bogdanm	0:9b334a45a8ff	877	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
bogdanm	0:9b334a45a8ff	878	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
bogdanm	0:9b334a45a8ff	879	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
bogdanm	0:9b334a45a8ff	880	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
bogdanm	0:9b334a45a8ff	881	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	/***************** Bit definition for EXTI_RTSR register ****************/
bogdanm	0:9b334a45a8ff	884	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
bogdanm	0:9b334a45a8ff	885	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
bogdanm	0:9b334a45a8ff	886	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
bogdanm	0:9b334a45a8ff	887	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
bogdanm	0:9b334a45a8ff	888	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
bogdanm	0:9b334a45a8ff	889	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
bogdanm	0:9b334a45a8ff	890	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
bogdanm	0:9b334a45a8ff	891	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
bogdanm	0:9b334a45a8ff	892	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
bogdanm	0:9b334a45a8ff	893	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
bogdanm	0:9b334a45a8ff	894	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
bogdanm	0:9b334a45a8ff	895	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
bogdanm	0:9b334a45a8ff	896	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
bogdanm	0:9b334a45a8ff	897	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
bogdanm	0:9b334a45a8ff	898	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
bogdanm	0:9b334a45a8ff	899	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
bogdanm	0:9b334a45a8ff	900	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
bogdanm	0:9b334a45a8ff	901	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
bogdanm	0:9b334a45a8ff	902	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/***************** Bit definition for EXTI_FTSR register *****************/
bogdanm	0:9b334a45a8ff	905	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
bogdanm	0:9b334a45a8ff	906	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
bogdanm	0:9b334a45a8ff	907	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
bogdanm	0:9b334a45a8ff	908	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
bogdanm	0:9b334a45a8ff	909	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
bogdanm	0:9b334a45a8ff	910	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
bogdanm	0:9b334a45a8ff	911	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
bogdanm	0:9b334a45a8ff	912	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
bogdanm	0:9b334a45a8ff	913	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
bogdanm	0:9b334a45a8ff	914	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
bogdanm	0:9b334a45a8ff	915	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
bogdanm	0:9b334a45a8ff	916	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
bogdanm	0:9b334a45a8ff	917	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
bogdanm	0:9b334a45a8ff	918	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
bogdanm	0:9b334a45a8ff	919	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
bogdanm	0:9b334a45a8ff	920	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
bogdanm	0:9b334a45a8ff	921	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
bogdanm	0:9b334a45a8ff	922	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
bogdanm	0:9b334a45a8ff	923	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
bogdanm	0:9b334a45a8ff	924
bogdanm	0:9b334a45a8ff	925	/***************** Bit definition for EXTI_SWIER register *****************/
bogdanm	0:9b334a45a8ff	926	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
bogdanm	0:9b334a45a8ff	927	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
bogdanm	0:9b334a45a8ff	928	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
bogdanm	0:9b334a45a8ff	929	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
bogdanm	0:9b334a45a8ff	930	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
bogdanm	0:9b334a45a8ff	931	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
bogdanm	0:9b334a45a8ff	932	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
bogdanm	0:9b334a45a8ff	933	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
bogdanm	0:9b334a45a8ff	934	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
bogdanm	0:9b334a45a8ff	935	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
bogdanm	0:9b334a45a8ff	936	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
bogdanm	0:9b334a45a8ff	937	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
bogdanm	0:9b334a45a8ff	938	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
bogdanm	0:9b334a45a8ff	939	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
bogdanm	0:9b334a45a8ff	940	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
bogdanm	0:9b334a45a8ff	941	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
bogdanm	0:9b334a45a8ff	942	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
bogdanm	0:9b334a45a8ff	943	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
bogdanm	0:9b334a45a8ff	944	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	/**************** Bit definition for EXTI_PR register *******************/
bogdanm	0:9b334a45a8ff	947	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
bogdanm	0:9b334a45a8ff	948	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
bogdanm	0:9b334a45a8ff	949	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
bogdanm	0:9b334a45a8ff	950	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
bogdanm	0:9b334a45a8ff	951	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
bogdanm	0:9b334a45a8ff	952	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
bogdanm	0:9b334a45a8ff	953	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
bogdanm	0:9b334a45a8ff	954	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
bogdanm	0:9b334a45a8ff	955	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
bogdanm	0:9b334a45a8ff	956	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
bogdanm	0:9b334a45a8ff	957	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
bogdanm	0:9b334a45a8ff	958	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
bogdanm	0:9b334a45a8ff	959	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
bogdanm	0:9b334a45a8ff	960	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
bogdanm	0:9b334a45a8ff	961	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
bogdanm	0:9b334a45a8ff	962	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
bogdanm	0:9b334a45a8ff	963	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
bogdanm	0:9b334a45a8ff	964	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
bogdanm	0:9b334a45a8ff	965	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
bogdanm	0:9b334a45a8ff	966
bogdanm	0:9b334a45a8ff	967	/******************************************************************************/
bogdanm	0:9b334a45a8ff	968	/* */
bogdanm	0:9b334a45a8ff	969	/* FLASH and Option Bytes Registers */
bogdanm	0:9b334a45a8ff	970	/* */
bogdanm	0:9b334a45a8ff	971	/******************************************************************************/
bogdanm	0:9b334a45a8ff	972
bogdanm	0:9b334a45a8ff	973	/***************** Bit definition for FLASH_ACR register ****************/
bogdanm	0:9b334a45a8ff	974	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
bogdanm	0:9b334a45a8ff	977	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	/**************** Bit definition for FLASH_KEYR register ****************/
bogdanm	0:9b334a45a8ff	980	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982	/*************** Bit definition for FLASH_OPTKEYR register **************/
bogdanm	0:9b334a45a8ff	983	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	/**************** FLASH Keys ********************************************/
bogdanm	0:9b334a45a8ff	986	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
bogdanm	0:9b334a45a8ff	987	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
bogdanm	0:9b334a45a8ff	988	to unlock the write access to the FPEC. */
bogdanm	0:9b334a45a8ff	989
bogdanm	0:9b334a45a8ff	990	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
bogdanm	0:9b334a45a8ff	991	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
bogdanm	0:9b334a45a8ff	992	unlock the write access to the option byte block */
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/**************** Bit definition for FLASH_SR register *****************/
bogdanm	0:9b334a45a8ff	995	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
bogdanm	0:9b334a45a8ff	996	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
bogdanm	0:9b334a45a8ff	997	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
bogdanm	0:9b334a45a8ff	998	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
bogdanm	0:9b334a45a8ff	999	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	/***************** Bit definition for FLASH_CR register *****************/
bogdanm	0:9b334a45a8ff	1002	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
bogdanm	0:9b334a45a8ff	1003	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
bogdanm	0:9b334a45a8ff	1004	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
bogdanm	0:9b334a45a8ff	1005	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
bogdanm	0:9b334a45a8ff	1006	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
bogdanm	0:9b334a45a8ff	1007	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
bogdanm	0:9b334a45a8ff	1008	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
bogdanm	0:9b334a45a8ff	1009	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
bogdanm	0:9b334a45a8ff	1010	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	1011	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
bogdanm	0:9b334a45a8ff	1012	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/***************** Bit definition for FLASH_AR register *****************/
bogdanm	0:9b334a45a8ff	1015	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	/**************** Bit definition for FLASH_OBR register *****************/
bogdanm	0:9b334a45a8ff	1018	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
bogdanm	0:9b334a45a8ff	1019	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
bogdanm	0:9b334a45a8ff	1020	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	#define FLASH_OBR_USER ((uint32_t)0x00007700) /!< User Option Bytes /
bogdanm	0:9b334a45a8ff	1023	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
bogdanm	0:9b334a45a8ff	1024	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
bogdanm	0:9b334a45a8ff	1025	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
bogdanm	0:9b334a45a8ff	1026	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
bogdanm	0:9b334a45a8ff	1027	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
bogdanm	0:9b334a45a8ff	1028	#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /!< RAM parity check /
bogdanm	0:9b334a45a8ff	1029
bogdanm	0:9b334a45a8ff	1030	/* Old BOOT1 bit definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	1031	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	1034	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	/**************** Bit definition for FLASH_WRPR register ****************/
bogdanm	0:9b334a45a8ff	1037	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /!< Write Protect /
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/----------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	1040
bogdanm	0:9b334a45a8ff	1041	/**************** Bit definition for OB_RDP register ********************/
bogdanm	0:9b334a45a8ff	1042	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
bogdanm	0:9b334a45a8ff	1043	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	/**************** Bit definition for OB_USER register *******************/
bogdanm	0:9b334a45a8ff	1046	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
bogdanm	0:9b334a45a8ff	1047	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/**************** Bit definition for OB_WRP0 register *******************/
bogdanm	0:9b334a45a8ff	1050	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	1051	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	1052
bogdanm	0:9b334a45a8ff	1053	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1054	/* */
bogdanm	0:9b334a45a8ff	1055	/* General Purpose IOs (GPIO) */
bogdanm	0:9b334a45a8ff	1056	/* */
bogdanm	0:9b334a45a8ff	1057	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1058	/***************** Bit definition for GPIO_MODER register ***************/
bogdanm	0:9b334a45a8ff	1059	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	1060	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1061	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1062	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	1063	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1064	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1065	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	1066	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1067	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1068	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	1069	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1070	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1071	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	1072	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1073	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1074	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	1075	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1076	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1077	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	1078	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1079	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1080	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	1081	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1082	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1083	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	1084	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1085	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	1086	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	1087	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	1088	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	1089	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	1090	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	1091	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	1092	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	1093	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	1094	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	1095	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	1096	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	1097	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	1098	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	1099	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	1100	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	1101	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	1102	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	1103	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	1104	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	1105	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	1106	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	1107
bogdanm	0:9b334a45a8ff	1108	/**************** Bit definition for GPIO_OTYPER register ***************/
bogdanm	0:9b334a45a8ff	1109	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1110	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1111	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1112	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1113	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1114	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1115	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1116	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1117	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1118	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1119	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1120	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1121	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1122	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1123	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1124	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	/************** Bit definition for GPIO_OSPEEDR register ****************/
bogdanm	0:9b334a45a8ff	1127	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	1128	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1129	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1130	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	1131	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1132	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1133	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	1134	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1135	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1136	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	1137	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1138	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1139	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	1140	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1141	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1142	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	1143	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1144	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1145	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	1146	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1147	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1148	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	1149	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1150	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1151	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	1152	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1153	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	1154	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	1155	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	1156	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	1157	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	1158	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	1159	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	1160	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	1161	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	1162	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	1163	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	1164	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	1165	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	1166	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	1167	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	1168	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	1169	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	1170	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	1171	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	1172	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	1173	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	1174	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	1177	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
bogdanm	0:9b334a45a8ff	1178	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
bogdanm	0:9b334a45a8ff	1179	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
bogdanm	0:9b334a45a8ff	1180	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
bogdanm	0:9b334a45a8ff	1181	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
bogdanm	0:9b334a45a8ff	1182	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
bogdanm	0:9b334a45a8ff	1183	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
bogdanm	0:9b334a45a8ff	1184	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
bogdanm	0:9b334a45a8ff	1185	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
bogdanm	0:9b334a45a8ff	1186	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
bogdanm	0:9b334a45a8ff	1187	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
bogdanm	0:9b334a45a8ff	1188	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
bogdanm	0:9b334a45a8ff	1189	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
bogdanm	0:9b334a45a8ff	1190	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
bogdanm	0:9b334a45a8ff	1191	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
bogdanm	0:9b334a45a8ff	1192	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
bogdanm	0:9b334a45a8ff	1193	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
bogdanm	0:9b334a45a8ff	1194	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
bogdanm	0:9b334a45a8ff	1195	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
bogdanm	0:9b334a45a8ff	1196	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
bogdanm	0:9b334a45a8ff	1197	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
bogdanm	0:9b334a45a8ff	1198	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
bogdanm	0:9b334a45a8ff	1199	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
bogdanm	0:9b334a45a8ff	1200	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
bogdanm	0:9b334a45a8ff	1201	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
bogdanm	0:9b334a45a8ff	1202	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
bogdanm	0:9b334a45a8ff	1203	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
bogdanm	0:9b334a45a8ff	1204	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
bogdanm	0:9b334a45a8ff	1205	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
bogdanm	0:9b334a45a8ff	1206	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
bogdanm	0:9b334a45a8ff	1207	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
bogdanm	0:9b334a45a8ff	1208	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
bogdanm	0:9b334a45a8ff	1209	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
bogdanm	0:9b334a45a8ff	1210	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
bogdanm	0:9b334a45a8ff	1211	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
bogdanm	0:9b334a45a8ff	1212	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
bogdanm	0:9b334a45a8ff	1213	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
bogdanm	0:9b334a45a8ff	1214	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
bogdanm	0:9b334a45a8ff	1215	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
bogdanm	0:9b334a45a8ff	1216	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
bogdanm	0:9b334a45a8ff	1217	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
bogdanm	0:9b334a45a8ff	1218	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
bogdanm	0:9b334a45a8ff	1219	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
bogdanm	0:9b334a45a8ff	1220	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
bogdanm	0:9b334a45a8ff	1221	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
bogdanm	0:9b334a45a8ff	1222	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
bogdanm	0:9b334a45a8ff	1223	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
bogdanm	0:9b334a45a8ff	1224	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	/***************** Bit definition for GPIO_PUPDR register ****************/
bogdanm	0:9b334a45a8ff	1227	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	1228	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1229	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1230	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	1231	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1232	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1233	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	1234	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1235	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1236	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	1237	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1238	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1239	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	1240	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1241	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1242	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	1243	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1244	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1245	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	1246	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1247	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1248	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	1249	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1250	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1251	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	1252	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1253	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	1254	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	1255	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	1256	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	1257	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	1258	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	1259	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	1260	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	1261	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	1262	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	1263	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	1264	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	1265	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	1266	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	1267	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	1268	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	1269	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	1270	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	1271	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	1272	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	1273	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	1274	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/***************** Bit definition for GPIO_IDR register *****************/
bogdanm	0:9b334a45a8ff	1277	#define GPIO_IDR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1278	#define GPIO_IDR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1279	#define GPIO_IDR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1280	#define GPIO_IDR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1281	#define GPIO_IDR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1282	#define GPIO_IDR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1283	#define GPIO_IDR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1284	#define GPIO_IDR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1285	#define GPIO_IDR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1286	#define GPIO_IDR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1287	#define GPIO_IDR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1288	#define GPIO_IDR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1289	#define GPIO_IDR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1290	#define GPIO_IDR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1291	#define GPIO_IDR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1292	#define GPIO_IDR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1293
bogdanm	0:9b334a45a8ff	1294	/**************** Bit definition for GPIO_ODR register ******************/
bogdanm	0:9b334a45a8ff	1295	#define GPIO_ODR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1296	#define GPIO_ODR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1297	#define GPIO_ODR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1298	#define GPIO_ODR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1299	#define GPIO_ODR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1300	#define GPIO_ODR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1301	#define GPIO_ODR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1302	#define GPIO_ODR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1303	#define GPIO_ODR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1304	#define GPIO_ODR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1305	#define GPIO_ODR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1306	#define GPIO_ODR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1307	#define GPIO_ODR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1308	#define GPIO_ODR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1309	#define GPIO_ODR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1310	#define GPIO_ODR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/**************** Bit definition for GPIO_BSRR register ******************/
bogdanm	0:9b334a45a8ff	1313	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1314	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1315	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1316	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1317	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1318	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1319	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1320	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1321	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1322	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1323	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1324	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1325	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1326	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1327	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1328	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1329	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1330	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	1331	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	1332	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	1333	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	1334	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	1335	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	1336	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	1337	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	1338	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	1339	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	1340	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	1341	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	1342	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	1343	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	1344	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	1345
bogdanm	0:9b334a45a8ff	1346	/**************** Bit definition for GPIO_LCKR register ******************/
bogdanm	0:9b334a45a8ff	1347	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1348	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1349	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1350	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1351	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1352	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1353	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1354	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1355	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1356	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1357	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1358	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1359	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1360	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1361	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1362	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1363	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	/**************** Bit definition for GPIO_AFRL register ******************/
bogdanm	0:9b334a45a8ff	1366	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	1367	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
bogdanm	0:9b334a45a8ff	1368	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	1369	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
bogdanm	0:9b334a45a8ff	1370	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	1371	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	1372	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	1373	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	/**************** Bit definition for GPIO_AFRH register ******************/
bogdanm	0:9b334a45a8ff	1376	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	1377	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
bogdanm	0:9b334a45a8ff	1378	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	1379	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
bogdanm	0:9b334a45a8ff	1380	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	1381	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	1382	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	1383	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385	/**************** Bit definition for GPIO_BRR register *******************/
bogdanm	0:9b334a45a8ff	1386	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1387	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1388	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1389	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1390	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1391	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1392	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1393	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1394	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1395	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1396	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1397	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1398	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1399	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1400	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1401	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1404	/* */
bogdanm	0:9b334a45a8ff	1405	/* Inter-integrated Circuit Interface (I2C) */
bogdanm	0:9b334a45a8ff	1406	/* */
bogdanm	0:9b334a45a8ff	1407	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	/***************** Bit definition for I2C_CR1 register *****************/
bogdanm	0:9b334a45a8ff	1410	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
bogdanm	0:9b334a45a8ff	1411	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
bogdanm	0:9b334a45a8ff	1412	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
bogdanm	0:9b334a45a8ff	1413	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
bogdanm	0:9b334a45a8ff	1414	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
bogdanm	0:9b334a45a8ff	1415	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
bogdanm	0:9b334a45a8ff	1416	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
bogdanm	0:9b334a45a8ff	1417	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
bogdanm	0:9b334a45a8ff	1418	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
bogdanm	0:9b334a45a8ff	1419	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
bogdanm	0:9b334a45a8ff	1420	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
bogdanm	0:9b334a45a8ff	1421	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
bogdanm	0:9b334a45a8ff	1422	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
bogdanm	0:9b334a45a8ff	1423	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
bogdanm	0:9b334a45a8ff	1424	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
bogdanm	0:9b334a45a8ff	1425	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
bogdanm	0:9b334a45a8ff	1426	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
bogdanm	0:9b334a45a8ff	1427	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
bogdanm	0:9b334a45a8ff	1428	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
bogdanm	0:9b334a45a8ff	1429	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
bogdanm	0:9b334a45a8ff	1430	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	/**************** Bit definition for I2C_CR2 register ******************/
bogdanm	0:9b334a45a8ff	1433	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
bogdanm	0:9b334a45a8ff	1434	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
bogdanm	0:9b334a45a8ff	1435	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
bogdanm	0:9b334a45a8ff	1436	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
bogdanm	0:9b334a45a8ff	1437	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
bogdanm	0:9b334a45a8ff	1438	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
bogdanm	0:9b334a45a8ff	1439	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
bogdanm	0:9b334a45a8ff	1440	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
bogdanm	0:9b334a45a8ff	1441	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
bogdanm	0:9b334a45a8ff	1442	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
bogdanm	0:9b334a45a8ff	1443	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	/***************** Bit definition for I2C_OAR1 register ****************/
bogdanm	0:9b334a45a8ff	1446	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
bogdanm	0:9b334a45a8ff	1447	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
bogdanm	0:9b334a45a8ff	1448	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
bogdanm	0:9b334a45a8ff	1449
bogdanm	0:9b334a45a8ff	1450	/***************** Bit definition for I2C_OAR2 register ****************/
bogdanm	0:9b334a45a8ff	1451	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
bogdanm	0:9b334a45a8ff	1452	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
bogdanm	0:9b334a45a8ff	1453	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	/***************** Bit definition for I2C_TIMINGR register **************/
bogdanm	0:9b334a45a8ff	1456	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
bogdanm	0:9b334a45a8ff	1457	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
bogdanm	0:9b334a45a8ff	1458	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
bogdanm	0:9b334a45a8ff	1459	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
bogdanm	0:9b334a45a8ff	1460	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
bogdanm	0:9b334a45a8ff	1461
bogdanm	0:9b334a45a8ff	1462	/***************** Bit definition for I2C_TIMEOUTR register **************/
bogdanm	0:9b334a45a8ff	1463	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
bogdanm	0:9b334a45a8ff	1464	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
bogdanm	0:9b334a45a8ff	1465	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
bogdanm	0:9b334a45a8ff	1466	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
bogdanm	0:9b334a45a8ff	1467	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	/**************** Bit definition for I2C_ISR register ******************/
bogdanm	0:9b334a45a8ff	1470	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
bogdanm	0:9b334a45a8ff	1471	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
bogdanm	0:9b334a45a8ff	1472	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
bogdanm	0:9b334a45a8ff	1473	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
bogdanm	0:9b334a45a8ff	1474	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
bogdanm	0:9b334a45a8ff	1475	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
bogdanm	0:9b334a45a8ff	1476	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
bogdanm	0:9b334a45a8ff	1477	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
bogdanm	0:9b334a45a8ff	1478	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
bogdanm	0:9b334a45a8ff	1479	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
bogdanm	0:9b334a45a8ff	1480	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
bogdanm	0:9b334a45a8ff	1481	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
bogdanm	0:9b334a45a8ff	1482	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
bogdanm	0:9b334a45a8ff	1483	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
bogdanm	0:9b334a45a8ff	1484	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
bogdanm	0:9b334a45a8ff	1485	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
bogdanm	0:9b334a45a8ff	1486	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	/**************** Bit definition for I2C_ICR register ******************/
bogdanm	0:9b334a45a8ff	1489	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
bogdanm	0:9b334a45a8ff	1490	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
bogdanm	0:9b334a45a8ff	1491	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
bogdanm	0:9b334a45a8ff	1492	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
bogdanm	0:9b334a45a8ff	1493	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
bogdanm	0:9b334a45a8ff	1494	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
bogdanm	0:9b334a45a8ff	1495	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
bogdanm	0:9b334a45a8ff	1496	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
bogdanm	0:9b334a45a8ff	1497	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
bogdanm	0:9b334a45a8ff	1498
bogdanm	0:9b334a45a8ff	1499	/**************** Bit definition for I2C_PECR register *****************/
bogdanm	0:9b334a45a8ff	1500	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	/**************** Bit definition for I2C_RXDR register *******************/
bogdanm	0:9b334a45a8ff	1503	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/**************** Bit definition for I2C_TXDR register *****************/
bogdanm	0:9b334a45a8ff	1506	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
bogdanm	0:9b334a45a8ff	1507
bogdanm	0:9b334a45a8ff	1508	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	1509	/* */
bogdanm	0:9b334a45a8ff	1510	/* Independent WATCHDOG (IWDG) */
bogdanm	0:9b334a45a8ff	1511	/* */
bogdanm	0:9b334a45a8ff	1512	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	1513	/***************** Bit definition for IWDG_KR register *****************/
bogdanm	0:9b334a45a8ff	1514	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!< Key value (write only, read 0000h) /
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516	/***************** Bit definition for IWDG_PR register *****************/
bogdanm	0:9b334a45a8ff	1517	#define IWDG_PR_PR ((uint32_t)0x07) /!< PR[2:0] (Prescaler divider) /
bogdanm	0:9b334a45a8ff	1518	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1519	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1520	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	/***************** Bit definition for IWDG_RLR register ****************/
bogdanm	0:9b334a45a8ff	1523	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!< Watchdog counter reload value /
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525	/***************** Bit definition for IWDG_SR register *****************/
bogdanm	0:9b334a45a8ff	1526	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
bogdanm	0:9b334a45a8ff	1527	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
bogdanm	0:9b334a45a8ff	1528	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	/***************** Bit definition for IWDG_KR register *****************/
bogdanm	0:9b334a45a8ff	1531	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	1534	/* */
bogdanm	0:9b334a45a8ff	1535	/* Power Control (PWR) */
bogdanm	0:9b334a45a8ff	1536	/* */
bogdanm	0:9b334a45a8ff	1537	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	1538
bogdanm	0:9b334a45a8ff	1539	/****************** Bit definition for PWR_CR register *****************/
bogdanm	0:9b334a45a8ff	1540	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-power Deepsleep /
bogdanm	0:9b334a45a8ff	1541	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
bogdanm	0:9b334a45a8ff	1542	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
bogdanm	0:9b334a45a8ff	1543	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
bogdanm	0:9b334a45a8ff	1544	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
bogdanm	0:9b334a45a8ff	1547	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1548	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1549	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1550
bogdanm	0:9b334a45a8ff	1551	/!< PVD level configuration /
bogdanm	0:9b334a45a8ff	1552	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
bogdanm	0:9b334a45a8ff	1553	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
bogdanm	0:9b334a45a8ff	1554	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
bogdanm	0:9b334a45a8ff	1555	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
bogdanm	0:9b334a45a8ff	1556	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
bogdanm	0:9b334a45a8ff	1557	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
bogdanm	0:9b334a45a8ff	1558	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
bogdanm	0:9b334a45a8ff	1559	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	/***************** Bit definition for PWR_CSR register *****************/
bogdanm	0:9b334a45a8ff	1564	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
bogdanm	0:9b334a45a8ff	1565	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
bogdanm	0:9b334a45a8ff	1566	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
bogdanm	0:9b334a45a8ff	1567	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /!< Internal voltage reference (VREFINT) ready flag /
bogdanm	0:9b334a45a8ff	1568
bogdanm	0:9b334a45a8ff	1569	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
bogdanm	0:9b334a45a8ff	1570	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
bogdanm	0:9b334a45a8ff	1571
bogdanm	0:9b334a45a8ff	1572	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	1573	/* */
bogdanm	0:9b334a45a8ff	1574	/* Reset and Clock Control */
bogdanm	0:9b334a45a8ff	1575	/* */
bogdanm	0:9b334a45a8ff	1576	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	1577
bogdanm	0:9b334a45a8ff	1578	/****************** Bit definition for RCC_CR register *****************/
bogdanm	0:9b334a45a8ff	1579	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
bogdanm	0:9b334a45a8ff	1580	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
bogdanm	0:9b334a45a8ff	1583	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	1584	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	1585	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	1586	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	1587	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
bogdanm	0:9b334a45a8ff	1590	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	1591	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	1592	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	1593	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	1594	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	1595	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	1596	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	1597	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	1598
bogdanm	0:9b334a45a8ff	1599	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
bogdanm	0:9b334a45a8ff	1600	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	1601	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
bogdanm	0:9b334a45a8ff	1602	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
bogdanm	0:9b334a45a8ff	1603	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
bogdanm	0:9b334a45a8ff	1604	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	/****************** Bit definition for RCC_CFGR register ***************/
bogdanm	0:9b334a45a8ff	1607	/!< SW configuration /
bogdanm	0:9b334a45a8ff	1608	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
bogdanm	0:9b334a45a8ff	1609	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1610	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1611
bogdanm	0:9b334a45a8ff	1612	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
bogdanm	0:9b334a45a8ff	1613	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
bogdanm	0:9b334a45a8ff	1614	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	/!< SWS configuration /
bogdanm	0:9b334a45a8ff	1617	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
bogdanm	0:9b334a45a8ff	1618	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1619	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1620
bogdanm	0:9b334a45a8ff	1621	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
bogdanm	0:9b334a45a8ff	1622	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
bogdanm	0:9b334a45a8ff	1623	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
bogdanm	0:9b334a45a8ff	1624
bogdanm	0:9b334a45a8ff	1625	/!< HPRE configuration /
bogdanm	0:9b334a45a8ff	1626	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
bogdanm	0:9b334a45a8ff	1627	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1628	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1629	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1630	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	1631
bogdanm	0:9b334a45a8ff	1632	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
bogdanm	0:9b334a45a8ff	1633	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
bogdanm	0:9b334a45a8ff	1634	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
bogdanm	0:9b334a45a8ff	1635	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
bogdanm	0:9b334a45a8ff	1636	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
bogdanm	0:9b334a45a8ff	1637	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
bogdanm	0:9b334a45a8ff	1638	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
bogdanm	0:9b334a45a8ff	1639	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
bogdanm	0:9b334a45a8ff	1640	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
bogdanm	0:9b334a45a8ff	1641
bogdanm	0:9b334a45a8ff	1642	/!< PPRE configuration /
bogdanm	0:9b334a45a8ff	1643	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
bogdanm	0:9b334a45a8ff	1644	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1645	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1646	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1647
bogdanm	0:9b334a45a8ff	1648	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	1649	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	1650	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	1651	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	1652	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/!< ADCPPRE configuration /
bogdanm	0:9b334a45a8ff	1655	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /!< ADCPRE bit (ADC prescaler) /
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK divided by 2 /
bogdanm	0:9b334a45a8ff	1658	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK divided by 4 /
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
bogdanm	0:9b334a45a8ff	1661	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	1662	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE/PREDIV clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
bogdanm	0:9b334a45a8ff	1665	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /!< HSE/PREDIV clock not divided for PLL entry /
bogdanm	0:9b334a45a8ff	1666	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /!< HSE/PREDIV clock divided by 2 for PLL entry /
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	/!< PLLMUL configuration /
bogdanm	0:9b334a45a8ff	1669	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
bogdanm	0:9b334a45a8ff	1670	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1671	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1672	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1673	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	1674
bogdanm	0:9b334a45a8ff	1675	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
bogdanm	0:9b334a45a8ff	1676	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
bogdanm	0:9b334a45a8ff	1677	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
bogdanm	0:9b334a45a8ff	1678	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
bogdanm	0:9b334a45a8ff	1679	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
bogdanm	0:9b334a45a8ff	1680	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
bogdanm	0:9b334a45a8ff	1681	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
bogdanm	0:9b334a45a8ff	1682	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
bogdanm	0:9b334a45a8ff	1683	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
bogdanm	0:9b334a45a8ff	1684	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
bogdanm	0:9b334a45a8ff	1685	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
bogdanm	0:9b334a45a8ff	1686	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
bogdanm	0:9b334a45a8ff	1687	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
bogdanm	0:9b334a45a8ff	1688	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
bogdanm	0:9b334a45a8ff	1689	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
bogdanm	0:9b334a45a8ff	1690
bogdanm	0:9b334a45a8ff	1691	/!< MCO configuration /
bogdanm	0:9b334a45a8ff	1692	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
bogdanm	0:9b334a45a8ff	1693	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1694	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1695	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1696	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	1697
bogdanm	0:9b334a45a8ff	1698	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
bogdanm	0:9b334a45a8ff	1699	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
bogdanm	0:9b334a45a8ff	1700	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
bogdanm	0:9b334a45a8ff	1701	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
bogdanm	0:9b334a45a8ff	1702	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
bogdanm	0:9b334a45a8ff	1703	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
bogdanm	0:9b334a45a8ff	1704	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
bogdanm	0:9b334a45a8ff	1705	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
bogdanm	0:9b334a45a8ff	1706
bogdanm	0:9b334a45a8ff	1707	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /!< MCO prescaler /
bogdanm	0:9b334a45a8ff	1708	#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
bogdanm	0:9b334a45a8ff	1709	#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
bogdanm	0:9b334a45a8ff	1710	#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
bogdanm	0:9b334a45a8ff	1711	#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
bogdanm	0:9b334a45a8ff	1712	#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
bogdanm	0:9b334a45a8ff	1713	#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /!< MCO is divided by 32 /
bogdanm	0:9b334a45a8ff	1714	#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /!< MCO is divided by 64 /
bogdanm	0:9b334a45a8ff	1715	#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /!< MCO is divided by 128 /
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /!< PLL is not divided to MCO /
bogdanm	0:9b334a45a8ff	1718
bogdanm	0:9b334a45a8ff	1719	/!<*************** Bit definition for RCC_CIR register ***************/
bogdanm	0:9b334a45a8ff	1720	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	1721	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	1722	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	1723	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	1724	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	1725	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	1726	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	1727	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	1728	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	1729	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	1730	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	1731	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	1732	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	1733	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	1734	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	1735	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	1736	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	1737	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	1738	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	1739	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
bogdanm	0:9b334a45a8ff	1740
bogdanm	0:9b334a45a8ff	1741	/*************** Bit definition for RCC_APB2RSTR register **************/
bogdanm	0:9b334a45a8ff	1742	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
bogdanm	0:9b334a45a8ff	1743	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
bogdanm	0:9b334a45a8ff	1744	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
bogdanm	0:9b334a45a8ff	1745	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
bogdanm	0:9b334a45a8ff	1746	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
bogdanm	0:9b334a45a8ff	1747	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
bogdanm	0:9b334a45a8ff	1748	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
bogdanm	0:9b334a45a8ff	1749	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
bogdanm	0:9b334a45a8ff	1750
bogdanm	0:9b334a45a8ff	1751	/!< Old ADC1 clock reset bit definition maintained for legacy purpose /
bogdanm	0:9b334a45a8ff	1752	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
bogdanm	0:9b334a45a8ff	1753
bogdanm	0:9b334a45a8ff	1754	/*************** Bit definition for RCC_APB1RSTR register **************/
bogdanm	0:9b334a45a8ff	1755	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 clock reset /
bogdanm	0:9b334a45a8ff	1756	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
bogdanm	0:9b334a45a8ff	1757	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
bogdanm	0:9b334a45a8ff	1758	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
bogdanm	0:9b334a45a8ff	1759	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
bogdanm	0:9b334a45a8ff	1760	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
bogdanm	0:9b334a45a8ff	1761
bogdanm	0:9b334a45a8ff	1762	/**************** Bit definition for RCC_AHBENR register ***************/
bogdanm	0:9b334a45a8ff	1763	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA1 clock enable /
bogdanm	0:9b334a45a8ff	1764	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
bogdanm	0:9b334a45a8ff	1765	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
bogdanm	0:9b334a45a8ff	1766	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
bogdanm	0:9b334a45a8ff	1767	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
bogdanm	0:9b334a45a8ff	1768	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
bogdanm	0:9b334a45a8ff	1769	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
bogdanm	0:9b334a45a8ff	1770	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
bogdanm	0:9b334a45a8ff	1771	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
bogdanm	0:9b334a45a8ff	1772
bogdanm	0:9b334a45a8ff	1773	/* Old Bit definition maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	1774	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
bogdanm	0:9b334a45a8ff	1775	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
bogdanm	0:9b334a45a8ff	1776
bogdanm	0:9b334a45a8ff	1777	/*************** Bit definition for RCC_APB2ENR register ***************/
bogdanm	0:9b334a45a8ff	1778	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
bogdanm	0:9b334a45a8ff	1779	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
bogdanm	0:9b334a45a8ff	1780	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
bogdanm	0:9b334a45a8ff	1781	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
bogdanm	0:9b334a45a8ff	1782	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
bogdanm	0:9b334a45a8ff	1783	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
bogdanm	0:9b334a45a8ff	1784	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
bogdanm	0:9b334a45a8ff	1785	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
bogdanm	0:9b334a45a8ff	1786
bogdanm	0:9b334a45a8ff	1787	/* Old Bit definition maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	1788	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
bogdanm	0:9b334a45a8ff	1789	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	/*************** Bit definition for RCC_APB1ENR register ***************/
bogdanm	0:9b334a45a8ff	1792	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enable /
bogdanm	0:9b334a45a8ff	1793	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
bogdanm	0:9b334a45a8ff	1794	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
bogdanm	0:9b334a45a8ff	1795	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
bogdanm	0:9b334a45a8ff	1796	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
bogdanm	0:9b334a45a8ff	1797	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
bogdanm	0:9b334a45a8ff	1798
bogdanm	0:9b334a45a8ff	1799	/***************** Bit definition for RCC_BDCR register ****************/
bogdanm	0:9b334a45a8ff	1800	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
bogdanm	0:9b334a45a8ff	1801	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	1802	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
bogdanm	0:9b334a45a8ff	1803
bogdanm	0:9b334a45a8ff	1804	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
bogdanm	0:9b334a45a8ff	1805	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1806	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1807
bogdanm	0:9b334a45a8ff	1808	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
bogdanm	0:9b334a45a8ff	1809	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1810	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1811
bogdanm	0:9b334a45a8ff	1812	/!< RTC configuration /
bogdanm	0:9b334a45a8ff	1813	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
bogdanm	0:9b334a45a8ff	1814	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	1815	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	1816	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
bogdanm	0:9b334a45a8ff	1817
bogdanm	0:9b334a45a8ff	1818	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
bogdanm	0:9b334a45a8ff	1819	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
bogdanm	0:9b334a45a8ff	1820
bogdanm	0:9b334a45a8ff	1821	/***************** Bit definition for RCC_CSR register *****************/
bogdanm	0:9b334a45a8ff	1822	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
bogdanm	0:9b334a45a8ff	1823	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	1824	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
bogdanm	0:9b334a45a8ff	1825	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
bogdanm	0:9b334a45a8ff	1826	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
bogdanm	0:9b334a45a8ff	1827	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
bogdanm	0:9b334a45a8ff	1828	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
bogdanm	0:9b334a45a8ff	1829	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
bogdanm	0:9b334a45a8ff	1830	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
bogdanm	0:9b334a45a8ff	1831	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
bogdanm	0:9b334a45a8ff	1832	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	/* Old Bit definition maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	1835	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
bogdanm	0:9b334a45a8ff	1836
bogdanm	0:9b334a45a8ff	1837	/***************** Bit definition for RCC_AHBRSTR register *************/
bogdanm	0:9b334a45a8ff	1838	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
bogdanm	0:9b334a45a8ff	1839	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
bogdanm	0:9b334a45a8ff	1840	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
bogdanm	0:9b334a45a8ff	1841	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /!< GPIOD clock reset /
bogdanm	0:9b334a45a8ff	1842	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /!< GPIOF clock reset /
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	/***************** Bit definition for RCC_CFGR2 register ***************/
bogdanm	0:9b334a45a8ff	1845	/!< PREDIV configuration /
bogdanm	0:9b334a45a8ff	1846	#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /!< PREDIV[3:0] bits /
bogdanm	0:9b334a45a8ff	1847	#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1848	#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1849	#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1850	#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	1851
bogdanm	0:9b334a45a8ff	1852	#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /!< PREDIV input clock not divided /
bogdanm	0:9b334a45a8ff	1853	#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /!< PREDIV input clock divided by 2 /
bogdanm	0:9b334a45a8ff	1854	#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /!< PREDIV input clock divided by 3 /
bogdanm	0:9b334a45a8ff	1855	#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /!< PREDIV input clock divided by 4 /
bogdanm	0:9b334a45a8ff	1856	#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /!< PREDIV input clock divided by 5 /
bogdanm	0:9b334a45a8ff	1857	#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /!< PREDIV input clock divided by 6 /
bogdanm	0:9b334a45a8ff	1858	#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /!< PREDIV input clock divided by 7 /
bogdanm	0:9b334a45a8ff	1859	#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /!< PREDIV input clock divided by 8 /
bogdanm	0:9b334a45a8ff	1860	#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /!< PREDIV input clock divided by 9 /
bogdanm	0:9b334a45a8ff	1861	#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /!< PREDIV input clock divided by 10 /
bogdanm	0:9b334a45a8ff	1862	#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /!< PREDIV input clock divided by 11 /
bogdanm	0:9b334a45a8ff	1863	#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /!< PREDIV input clock divided by 12 /
bogdanm	0:9b334a45a8ff	1864	#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /!< PREDIV input clock divided by 13 /
bogdanm	0:9b334a45a8ff	1865	#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /!< PREDIV input clock divided by 14 /
bogdanm	0:9b334a45a8ff	1866	#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /!< PREDIV input clock divided by 15 /
bogdanm	0:9b334a45a8ff	1867	#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /!< PREDIV input clock divided by 16 /
bogdanm	0:9b334a45a8ff	1868
bogdanm	0:9b334a45a8ff	1869	/***************** Bit definition for RCC_CFGR3 register ***************/
bogdanm	0:9b334a45a8ff	1870	/!< USART1 Clock source selection /
bogdanm	0:9b334a45a8ff	1871	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
bogdanm	0:9b334a45a8ff	1872	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1873	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1874
bogdanm	0:9b334a45a8ff	1875	#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART1 clock source /
bogdanm	0:9b334a45a8ff	1876	#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /!< System clock selected as USART1 clock source /
bogdanm	0:9b334a45a8ff	1877	#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /!< LSE oscillator clock used as USART1 clock source /
bogdanm	0:9b334a45a8ff	1878	#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /!< HSI oscillator clock used as USART1 clock source /
bogdanm	0:9b334a45a8ff	1879
bogdanm	0:9b334a45a8ff	1880	/!< I2C1 Clock source selection /
bogdanm	0:9b334a45a8ff	1881	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
bogdanm	0:9b334a45a8ff	1882
bogdanm	0:9b334a45a8ff	1883	#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /!< HSI oscillator clock used as I2C1 clock source /
bogdanm	0:9b334a45a8ff	1884	#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /!< System clock selected as I2C1 clock source /
bogdanm	0:9b334a45a8ff	1885
bogdanm	0:9b334a45a8ff	1886	/***************** Bit definition for RCC_CR2 register *****************/
bogdanm	0:9b334a45a8ff	1887	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
bogdanm	0:9b334a45a8ff	1888	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
bogdanm	0:9b334a45a8ff	1889	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
bogdanm	0:9b334a45a8ff	1890	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
bogdanm	0:9b334a45a8ff	1891	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
bogdanm	0:9b334a45a8ff	1892
bogdanm	0:9b334a45a8ff	1893	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	1894	/* */
bogdanm	0:9b334a45a8ff	1895	/* Real-Time Clock (RTC) */
bogdanm	0:9b334a45a8ff	1896	/* */
bogdanm	0:9b334a45a8ff	1897	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	1898	/****************** Bits definition for RTC_TR register ****************/
bogdanm	0:9b334a45a8ff	1899	#define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	1900	#define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	1901	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	1902	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	1903	#define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	1904	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1905	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	1906	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	1907	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	1908	#define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	1909	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1910	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1911	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1912	#define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	1913	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1914	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1915	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1916	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1917	#define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	1918	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1919	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1920	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1921	#define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	1922	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1923	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1924	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1925	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1926
bogdanm	0:9b334a45a8ff	1927	/****************** Bits definition for RTC_DR register ****************/
bogdanm	0:9b334a45a8ff	1928	#define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	1929	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	1930	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	1931	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	1932	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	1933	#define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	1934	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1935	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	1936	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	1937	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	1938	#define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm	0:9b334a45a8ff	1939	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1940	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1941	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1942	#define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1943	#define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	1944	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1945	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1946	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1947	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1948	#define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	1949	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1950	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1951	#define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	1952	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1953	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1954	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1955	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1956
bogdanm	0:9b334a45a8ff	1957	/****************** Bits definition for RTC_CR register ****************/
bogdanm	0:9b334a45a8ff	1958	#define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	1959	#define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm	0:9b334a45a8ff	1960	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	1961	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	1962	#define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	1963	#define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	1964	#define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	1965	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	1966	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1967	#define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1968	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1969	#define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1970	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1971	#define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1972	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1973	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1974	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1975
bogdanm	0:9b334a45a8ff	1976	/****************** Bits definition for RTC_ISR register ***************/
bogdanm	0:9b334a45a8ff	1977	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1978	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1979	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1980	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1981	#define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	1982	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	1983	#define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1984	#define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1985	#define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1986	#define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1987	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1988	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1989
bogdanm	0:9b334a45a8ff	1990	/****************** Bits definition for RTC_PRER register **************/
bogdanm	0:9b334a45a8ff	1991	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm	0:9b334a45a8ff	1992	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	/****************** Bits definition for RTC_ALRMAR register ************/
bogdanm	0:9b334a45a8ff	1995	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	1996	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	1997	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	1998	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	1999	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	2000	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	2001	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	2002	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	2003	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	2004	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	2005	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	2006	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	2007	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	2008	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	2009	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	2010	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	2011	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	2012	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	2013	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	2014	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	2015	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	2016	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	2017	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	2018	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	2019	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	2020	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	2021	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	2022	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	2023	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	2024	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	2025	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	2026	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	2027	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	2028	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	2029	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	2030	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	2031	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	2032	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	2033	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	2034	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	2035
bogdanm	0:9b334a45a8ff	2036	/****************** Bits definition for RTC_WPR register ***************/
bogdanm	0:9b334a45a8ff	2037	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm	0:9b334a45a8ff	2038
bogdanm	0:9b334a45a8ff	2039	/****************** Bits definition for RTC_SSR register ***************/
bogdanm	0:9b334a45a8ff	2040	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	2041
bogdanm	0:9b334a45a8ff	2042	/****************** Bits definition for RTC_SHIFTR register ************/
bogdanm	0:9b334a45a8ff	2043	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	2044	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	2045
bogdanm	0:9b334a45a8ff	2046	/****************** Bits definition for RTC_TSTR register **************/
bogdanm	0:9b334a45a8ff	2047	#define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	2048	#define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	2049	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	2050	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	2051	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	2052	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	2053	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	2054	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	2055	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	2056	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	2057	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	2058	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	2059	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	2060	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	2061	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	2062	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	2063	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	2064	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	2065	#define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	2066	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	2067	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	2068	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	2069	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	2070	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	2071	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	2072	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	2073	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	2074
bogdanm	0:9b334a45a8ff	2075	/****************** Bits definition for RTC_TSDR register **************/
bogdanm	0:9b334a45a8ff	2076	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm	0:9b334a45a8ff	2077	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	2078	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	2079	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	2080	#define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	2081	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	2082	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	2083	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	2084	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	2085	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	2086	#define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	2087	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	2088	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	2089	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	2090	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	2091	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	2092	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	2093	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	2094
bogdanm	0:9b334a45a8ff	2095	/****************** Bits definition for RTC_TSSSR register *************/
bogdanm	0:9b334a45a8ff	2096	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	2097
bogdanm	0:9b334a45a8ff	2098	/****************** Bits definition for RTC_CALR register **************/
bogdanm	0:9b334a45a8ff	2099	#define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	2100	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	2101	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	2102	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm	0:9b334a45a8ff	2103	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	2104	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	2105	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	2106	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	2107	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	2108	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	2109	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	2110	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	2111	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	2112
bogdanm	0:9b334a45a8ff	2113	/****************** Bits definition for RTC_TAFCR register *************/
bogdanm	0:9b334a45a8ff	2114	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	2115	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	2116	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm	0:9b334a45a8ff	2117	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	2118	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	2119	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm	0:9b334a45a8ff	2120	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	2121	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	2122	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm	0:9b334a45a8ff	2123	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	2124	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	2125	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	2126	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	2127	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	2128	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	2129	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	2130	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	2131	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	2132
bogdanm	0:9b334a45a8ff	2133	/****************** Bits definition for RTC_ALRMASSR register **********/
bogdanm	0:9b334a45a8ff	2134	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	2135	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	2136	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	2137	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	2138	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	2139	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	2140
bogdanm	0:9b334a45a8ff	2141	/****************** Bits definition for RTC_BKP0R register *************/
bogdanm	0:9b334a45a8ff	2142	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	2143
bogdanm	0:9b334a45a8ff	2144	/****************** Bits definition for RTC_BKP1R register *************/
bogdanm	0:9b334a45a8ff	2145	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	2146
bogdanm	0:9b334a45a8ff	2147	/****************** Bits definition for RTC_BKP2R register *************/
bogdanm	0:9b334a45a8ff	2148	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	2149
bogdanm	0:9b334a45a8ff	2150	/****************** Bits definition for RTC_BKP3R register *************/
bogdanm	0:9b334a45a8ff	2151	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	2152
bogdanm	0:9b334a45a8ff	2153	/****************** Bits definition for RTC_BKP4R register *************/
bogdanm	0:9b334a45a8ff	2154	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	2155
bogdanm	0:9b334a45a8ff	2156	/****************** Number of backup registers ****************************/
bogdanm	0:9b334a45a8ff	2157	#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
bogdanm	0:9b334a45a8ff	2158
bogdanm	0:9b334a45a8ff	2159	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	2160	/* */
bogdanm	0:9b334a45a8ff	2161	/* Serial Peripheral Interface (SPI) */
bogdanm	0:9b334a45a8ff	2162	/* */
bogdanm	0:9b334a45a8ff	2163	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	2164	/***************** Bit definition for SPI_CR1 register *****************/
bogdanm	0:9b334a45a8ff	2165	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
bogdanm	0:9b334a45a8ff	2166	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
bogdanm	0:9b334a45a8ff	2167	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
bogdanm	0:9b334a45a8ff	2168	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
bogdanm	0:9b334a45a8ff	2169	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2170	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2171	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2172	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
bogdanm	0:9b334a45a8ff	2173	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
bogdanm	0:9b334a45a8ff	2174	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
bogdanm	0:9b334a45a8ff	2175	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
bogdanm	0:9b334a45a8ff	2176	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
bogdanm	0:9b334a45a8ff	2177	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
bogdanm	0:9b334a45a8ff	2178	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
bogdanm	0:9b334a45a8ff	2179	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
bogdanm	0:9b334a45a8ff	2180	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
bogdanm	0:9b334a45a8ff	2181	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
bogdanm	0:9b334a45a8ff	2182
bogdanm	0:9b334a45a8ff	2183	/***************** Bit definition for SPI_CR2 register *****************/
bogdanm	0:9b334a45a8ff	2184	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
bogdanm	0:9b334a45a8ff	2185	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
bogdanm	0:9b334a45a8ff	2186	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
bogdanm	0:9b334a45a8ff	2187	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
bogdanm	0:9b334a45a8ff	2188	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
bogdanm	0:9b334a45a8ff	2189	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	2190	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	2191	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	2192	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
bogdanm	0:9b334a45a8ff	2193	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2194	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2195	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2196	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2197	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
bogdanm	0:9b334a45a8ff	2198	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
bogdanm	0:9b334a45a8ff	2199	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
bogdanm	0:9b334a45a8ff	2200
bogdanm	0:9b334a45a8ff	2201	/****************** Bit definition for SPI_SR register *****************/
bogdanm	0:9b334a45a8ff	2202	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
bogdanm	0:9b334a45a8ff	2203	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
bogdanm	0:9b334a45a8ff	2204	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
bogdanm	0:9b334a45a8ff	2205	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
bogdanm	0:9b334a45a8ff	2206	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
bogdanm	0:9b334a45a8ff	2207	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
bogdanm	0:9b334a45a8ff	2208	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
bogdanm	0:9b334a45a8ff	2209	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
bogdanm	0:9b334a45a8ff	2210	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
bogdanm	0:9b334a45a8ff	2211	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
bogdanm	0:9b334a45a8ff	2212	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2213	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2214	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
bogdanm	0:9b334a45a8ff	2215	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2216	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2217
bogdanm	0:9b334a45a8ff	2218	/****************** Bit definition for SPI_DR register *****************/
bogdanm	0:9b334a45a8ff	2219	#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data Register /
bogdanm	0:9b334a45a8ff	2220
bogdanm	0:9b334a45a8ff	2221	/***************** Bit definition for SPI_CRCPR register ***************/
bogdanm	0:9b334a45a8ff	2222	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /!< CRC polynomial register /
bogdanm	0:9b334a45a8ff	2223
bogdanm	0:9b334a45a8ff	2224	/**************** Bit definition for SPI_RXCRCR register ***************/
bogdanm	0:9b334a45a8ff	2225	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /!< Rx CRC Register /
bogdanm	0:9b334a45a8ff	2226
bogdanm	0:9b334a45a8ff	2227	/**************** Bit definition for SPI_TXCRCR register ***************/
bogdanm	0:9b334a45a8ff	2228	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /!< Tx CRC Register /
bogdanm	0:9b334a45a8ff	2229
bogdanm	0:9b334a45a8ff	2230	/**************** Bit definition for SPI_I2SCFGR register **************/
bogdanm	0:9b334a45a8ff	2231	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
bogdanm	0:9b334a45a8ff	2232	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
bogdanm	0:9b334a45a8ff	2233	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2234	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2235	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
bogdanm	0:9b334a45a8ff	2236	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
bogdanm	0:9b334a45a8ff	2237	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2238	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2239	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
bogdanm	0:9b334a45a8ff	2240	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
bogdanm	0:9b334a45a8ff	2241	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2242	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2243	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
bogdanm	0:9b334a45a8ff	2244	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
bogdanm	0:9b334a45a8ff	2245
bogdanm	0:9b334a45a8ff	2246	/**************** Bit definition for SPI_I2SPR register ****************/
bogdanm	0:9b334a45a8ff	2247	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
bogdanm	0:9b334a45a8ff	2248	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
bogdanm	0:9b334a45a8ff	2249	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
bogdanm	0:9b334a45a8ff	2250
bogdanm	0:9b334a45a8ff	2251	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	2252	/* */
bogdanm	0:9b334a45a8ff	2253	/* System Configuration (SYSCFG) */
bogdanm	0:9b334a45a8ff	2254	/* */
bogdanm	0:9b334a45a8ff	2255	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	2256	/*************** Bit definition for SYSCFG_CFGR1 register **************/
bogdanm	0:9b334a45a8ff	2257	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
bogdanm	0:9b334a45a8ff	2258	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
bogdanm	0:9b334a45a8ff	2259	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
bogdanm	0:9b334a45a8ff	2260
bogdanm	0:9b334a45a8ff	2261
bogdanm	0:9b334a45a8ff	2262	#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /!< DMA remap mask /
bogdanm	0:9b334a45a8ff	2263	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
bogdanm	0:9b334a45a8ff	2264	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
bogdanm	0:9b334a45a8ff	2265	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
bogdanm	0:9b334a45a8ff	2266	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
bogdanm	0:9b334a45a8ff	2267	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
bogdanm	0:9b334a45a8ff	2268
bogdanm	0:9b334a45a8ff	2269	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
bogdanm	0:9b334a45a8ff	2270	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
bogdanm	0:9b334a45a8ff	2271	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
bogdanm	0:9b334a45a8ff	2272	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
bogdanm	0:9b334a45a8ff	2273	#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
bogdanm	0:9b334a45a8ff	2274	#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /!< Enable Fast Mode Plus on PA9 /
bogdanm	0:9b334a45a8ff	2275	#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /!< Enable Fast Mode Plus on PA10 /
bogdanm	0:9b334a45a8ff	2276
bogdanm	0:9b334a45a8ff	2277
bogdanm	0:9b334a45a8ff	2278	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
bogdanm	0:9b334a45a8ff	2279	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
bogdanm	0:9b334a45a8ff	2280	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
bogdanm	0:9b334a45a8ff	2281	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
bogdanm	0:9b334a45a8ff	2282	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
bogdanm	0:9b334a45a8ff	2283
bogdanm	0:9b334a45a8ff	2284	/**
bogdanm	0:9b334a45a8ff	2285	* @brief EXTI0 configuration
bogdanm	0:9b334a45a8ff	2286	*/
bogdanm	0:9b334a45a8ff	2287	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
bogdanm	0:9b334a45a8ff	2288	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
bogdanm	0:9b334a45a8ff	2289	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
bogdanm	0:9b334a45a8ff	2290	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
bogdanm	0:9b334a45a8ff	2291	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
bogdanm	0:9b334a45a8ff	2292
bogdanm	0:9b334a45a8ff	2293	/**
bogdanm	0:9b334a45a8ff	2294	* @brief EXTI1 configuration
bogdanm	0:9b334a45a8ff	2295	*/
bogdanm	0:9b334a45a8ff	2296	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
bogdanm	0:9b334a45a8ff	2297	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
bogdanm	0:9b334a45a8ff	2298	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
bogdanm	0:9b334a45a8ff	2299	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
bogdanm	0:9b334a45a8ff	2300	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
bogdanm	0:9b334a45a8ff	2301
bogdanm	0:9b334a45a8ff	2302	/**
bogdanm	0:9b334a45a8ff	2303	* @brief EXTI2 configuration
bogdanm	0:9b334a45a8ff	2304	*/
bogdanm	0:9b334a45a8ff	2305	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
bogdanm	0:9b334a45a8ff	2306	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
bogdanm	0:9b334a45a8ff	2307	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
bogdanm	0:9b334a45a8ff	2308	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
bogdanm	0:9b334a45a8ff	2309	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
bogdanm	0:9b334a45a8ff	2310
bogdanm	0:9b334a45a8ff	2311	/**
bogdanm	0:9b334a45a8ff	2312	* @brief EXTI3 configuration
bogdanm	0:9b334a45a8ff	2313	*/
bogdanm	0:9b334a45a8ff	2314	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
bogdanm	0:9b334a45a8ff	2315	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
bogdanm	0:9b334a45a8ff	2316	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
bogdanm	0:9b334a45a8ff	2317	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
bogdanm	0:9b334a45a8ff	2318	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
bogdanm	0:9b334a45a8ff	2319
bogdanm	0:9b334a45a8ff	2320	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
bogdanm	0:9b334a45a8ff	2321	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
bogdanm	0:9b334a45a8ff	2322	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
bogdanm	0:9b334a45a8ff	2323	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
bogdanm	0:9b334a45a8ff	2324	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
bogdanm	0:9b334a45a8ff	2325
bogdanm	0:9b334a45a8ff	2326	/**
bogdanm	0:9b334a45a8ff	2327	* @brief EXTI4 configuration
bogdanm	0:9b334a45a8ff	2328	*/
bogdanm	0:9b334a45a8ff	2329	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
bogdanm	0:9b334a45a8ff	2330	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
bogdanm	0:9b334a45a8ff	2331	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
bogdanm	0:9b334a45a8ff	2332	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
bogdanm	0:9b334a45a8ff	2333	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
bogdanm	0:9b334a45a8ff	2334
bogdanm	0:9b334a45a8ff	2335	/**
bogdanm	0:9b334a45a8ff	2336	* @brief EXTI5 configuration
bogdanm	0:9b334a45a8ff	2337	*/
bogdanm	0:9b334a45a8ff	2338	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
bogdanm	0:9b334a45a8ff	2339	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
bogdanm	0:9b334a45a8ff	2340	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
bogdanm	0:9b334a45a8ff	2341	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
bogdanm	0:9b334a45a8ff	2342	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
bogdanm	0:9b334a45a8ff	2343
bogdanm	0:9b334a45a8ff	2344	/**
bogdanm	0:9b334a45a8ff	2345	* @brief EXTI6 configuration
bogdanm	0:9b334a45a8ff	2346	*/
bogdanm	0:9b334a45a8ff	2347	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
bogdanm	0:9b334a45a8ff	2348	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
bogdanm	0:9b334a45a8ff	2349	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
bogdanm	0:9b334a45a8ff	2350	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
bogdanm	0:9b334a45a8ff	2351	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
bogdanm	0:9b334a45a8ff	2352
bogdanm	0:9b334a45a8ff	2353	/**
bogdanm	0:9b334a45a8ff	2354	* @brief EXTI7 configuration
bogdanm	0:9b334a45a8ff	2355	*/
bogdanm	0:9b334a45a8ff	2356	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
bogdanm	0:9b334a45a8ff	2357	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
bogdanm	0:9b334a45a8ff	2358	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
bogdanm	0:9b334a45a8ff	2359	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
bogdanm	0:9b334a45a8ff	2360	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
bogdanm	0:9b334a45a8ff	2361
bogdanm	0:9b334a45a8ff	2362	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
bogdanm	0:9b334a45a8ff	2363	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
bogdanm	0:9b334a45a8ff	2364	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
bogdanm	0:9b334a45a8ff	2365	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
bogdanm	0:9b334a45a8ff	2366	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
bogdanm	0:9b334a45a8ff	2367
bogdanm	0:9b334a45a8ff	2368	/**
bogdanm	0:9b334a45a8ff	2369	* @brief EXTI8 configuration
bogdanm	0:9b334a45a8ff	2370	*/
bogdanm	0:9b334a45a8ff	2371	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
bogdanm	0:9b334a45a8ff	2372	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
bogdanm	0:9b334a45a8ff	2373	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
bogdanm	0:9b334a45a8ff	2374	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
bogdanm	0:9b334a45a8ff	2375	#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
bogdanm	0:9b334a45a8ff	2376
bogdanm	0:9b334a45a8ff	2377	/**
bogdanm	0:9b334a45a8ff	2378	* @brief EXTI9 configuration
bogdanm	0:9b334a45a8ff	2379	*/
bogdanm	0:9b334a45a8ff	2380	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
bogdanm	0:9b334a45a8ff	2381	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
bogdanm	0:9b334a45a8ff	2382	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
bogdanm	0:9b334a45a8ff	2383	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
bogdanm	0:9b334a45a8ff	2384	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
bogdanm	0:9b334a45a8ff	2385
bogdanm	0:9b334a45a8ff	2386	/**
bogdanm	0:9b334a45a8ff	2387	* @brief EXTI10 configuration
bogdanm	0:9b334a45a8ff	2388	*/
bogdanm	0:9b334a45a8ff	2389	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
bogdanm	0:9b334a45a8ff	2390	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
bogdanm	0:9b334a45a8ff	2391	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
bogdanm	0:9b334a45a8ff	2392	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
bogdanm	0:9b334a45a8ff	2393	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
bogdanm	0:9b334a45a8ff	2394
bogdanm	0:9b334a45a8ff	2395	/**
bogdanm	0:9b334a45a8ff	2396	* @brief EXTI11 configuration
bogdanm	0:9b334a45a8ff	2397	*/
bogdanm	0:9b334a45a8ff	2398	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
bogdanm	0:9b334a45a8ff	2399	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
bogdanm	0:9b334a45a8ff	2400	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
bogdanm	0:9b334a45a8ff	2401	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
bogdanm	0:9b334a45a8ff	2402	#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
bogdanm	0:9b334a45a8ff	2403
bogdanm	0:9b334a45a8ff	2404	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
bogdanm	0:9b334a45a8ff	2405	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
bogdanm	0:9b334a45a8ff	2406	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
bogdanm	0:9b334a45a8ff	2407	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
bogdanm	0:9b334a45a8ff	2408	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
bogdanm	0:9b334a45a8ff	2409
bogdanm	0:9b334a45a8ff	2410	/**
bogdanm	0:9b334a45a8ff	2411	* @brief EXTI12 configuration
bogdanm	0:9b334a45a8ff	2412	*/
bogdanm	0:9b334a45a8ff	2413	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
bogdanm	0:9b334a45a8ff	2414	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
bogdanm	0:9b334a45a8ff	2415	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
bogdanm	0:9b334a45a8ff	2416	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
bogdanm	0:9b334a45a8ff	2417	#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
bogdanm	0:9b334a45a8ff	2418
bogdanm	0:9b334a45a8ff	2419	/**
bogdanm	0:9b334a45a8ff	2420	* @brief EXTI13 configuration
bogdanm	0:9b334a45a8ff	2421	*/
bogdanm	0:9b334a45a8ff	2422	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
bogdanm	0:9b334a45a8ff	2423	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
bogdanm	0:9b334a45a8ff	2424	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
bogdanm	0:9b334a45a8ff	2425	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
bogdanm	0:9b334a45a8ff	2426	#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
bogdanm	0:9b334a45a8ff	2427
bogdanm	0:9b334a45a8ff	2428	/**
bogdanm	0:9b334a45a8ff	2429	* @brief EXTI14 configuration
bogdanm	0:9b334a45a8ff	2430	*/
bogdanm	0:9b334a45a8ff	2431	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
bogdanm	0:9b334a45a8ff	2432	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
bogdanm	0:9b334a45a8ff	2433	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
bogdanm	0:9b334a45a8ff	2434	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
bogdanm	0:9b334a45a8ff	2435	#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
bogdanm	0:9b334a45a8ff	2436
bogdanm	0:9b334a45a8ff	2437	/**
bogdanm	0:9b334a45a8ff	2438	* @brief EXTI15 configuration
bogdanm	0:9b334a45a8ff	2439	*/
bogdanm	0:9b334a45a8ff	2440	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
bogdanm	0:9b334a45a8ff	2441	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
bogdanm	0:9b334a45a8ff	2442	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
bogdanm	0:9b334a45a8ff	2443	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
bogdanm	0:9b334a45a8ff	2444	#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
bogdanm	0:9b334a45a8ff	2445
bogdanm	0:9b334a45a8ff	2446	/*************** Bit definition for SYSCFG_CFGR2 register **************/
bogdanm	0:9b334a45a8ff	2447	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
bogdanm	0:9b334a45a8ff	2448	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
bogdanm	0:9b334a45a8ff	2449	#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
bogdanm	0:9b334a45a8ff	2450	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
bogdanm	0:9b334a45a8ff	2451	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
bogdanm	0:9b334a45a8ff	2452
bogdanm	0:9b334a45a8ff	2453	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	2454	/* */
bogdanm	0:9b334a45a8ff	2455	/* Timers (TIM) */
bogdanm	0:9b334a45a8ff	2456	/* */
bogdanm	0:9b334a45a8ff	2457	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	2458	/***************** Bit definition for TIM_CR1 register *****************/
bogdanm	0:9b334a45a8ff	2459	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
bogdanm	0:9b334a45a8ff	2460	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
bogdanm	0:9b334a45a8ff	2461	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
bogdanm	0:9b334a45a8ff	2462	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
bogdanm	0:9b334a45a8ff	2463	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
bogdanm	0:9b334a45a8ff	2464
bogdanm	0:9b334a45a8ff	2465	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
bogdanm	0:9b334a45a8ff	2466	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2467	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2468
bogdanm	0:9b334a45a8ff	2469	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
bogdanm	0:9b334a45a8ff	2470
bogdanm	0:9b334a45a8ff	2471	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
bogdanm	0:9b334a45a8ff	2472	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2473	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2474
bogdanm	0:9b334a45a8ff	2475	/***************** Bit definition for TIM_CR2 register *****************/
bogdanm	0:9b334a45a8ff	2476	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
bogdanm	0:9b334a45a8ff	2477	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
bogdanm	0:9b334a45a8ff	2478	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
bogdanm	0:9b334a45a8ff	2479
bogdanm	0:9b334a45a8ff	2480	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
bogdanm	0:9b334a45a8ff	2481	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2482	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2483	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2484
bogdanm	0:9b334a45a8ff	2485	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
bogdanm	0:9b334a45a8ff	2486	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
bogdanm	0:9b334a45a8ff	2487	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
bogdanm	0:9b334a45a8ff	2488	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
bogdanm	0:9b334a45a8ff	2489	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
bogdanm	0:9b334a45a8ff	2490	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
bogdanm	0:9b334a45a8ff	2491	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
bogdanm	0:9b334a45a8ff	2492	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
bogdanm	0:9b334a45a8ff	2493
bogdanm	0:9b334a45a8ff	2494	/***************** Bit definition for TIM_SMCR register ****************/
bogdanm	0:9b334a45a8ff	2495	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
bogdanm	0:9b334a45a8ff	2496	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2497	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2498	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2499
bogdanm	0:9b334a45a8ff	2500	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
bogdanm	0:9b334a45a8ff	2501
bogdanm	0:9b334a45a8ff	2502	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
bogdanm	0:9b334a45a8ff	2503	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2504	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2505	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2506
bogdanm	0:9b334a45a8ff	2507	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
bogdanm	0:9b334a45a8ff	2508
bogdanm	0:9b334a45a8ff	2509	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
bogdanm	0:9b334a45a8ff	2510	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2511	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2512	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2513	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2514
bogdanm	0:9b334a45a8ff	2515	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
bogdanm	0:9b334a45a8ff	2516	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2517	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2518
bogdanm	0:9b334a45a8ff	2519	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
bogdanm	0:9b334a45a8ff	2520	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
bogdanm	0:9b334a45a8ff	2521
bogdanm	0:9b334a45a8ff	2522	/***************** Bit definition for TIM_DIER register ****************/
bogdanm	0:9b334a45a8ff	2523	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
bogdanm	0:9b334a45a8ff	2524	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
bogdanm	0:9b334a45a8ff	2525	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
bogdanm	0:9b334a45a8ff	2526	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
bogdanm	0:9b334a45a8ff	2527	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
bogdanm	0:9b334a45a8ff	2528	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
bogdanm	0:9b334a45a8ff	2529	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
bogdanm	0:9b334a45a8ff	2530	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
bogdanm	0:9b334a45a8ff	2531	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
bogdanm	0:9b334a45a8ff	2532	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
bogdanm	0:9b334a45a8ff	2533	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
bogdanm	0:9b334a45a8ff	2534	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
bogdanm	0:9b334a45a8ff	2535	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
bogdanm	0:9b334a45a8ff	2536	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
bogdanm	0:9b334a45a8ff	2537	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
bogdanm	0:9b334a45a8ff	2538
bogdanm	0:9b334a45a8ff	2539	/****************** Bit definition for TIM_SR register *****************/
bogdanm	0:9b334a45a8ff	2540	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
bogdanm	0:9b334a45a8ff	2541	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
bogdanm	0:9b334a45a8ff	2542	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
bogdanm	0:9b334a45a8ff	2543	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
bogdanm	0:9b334a45a8ff	2544	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
bogdanm	0:9b334a45a8ff	2545	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
bogdanm	0:9b334a45a8ff	2546	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
bogdanm	0:9b334a45a8ff	2547	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
bogdanm	0:9b334a45a8ff	2548	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
bogdanm	0:9b334a45a8ff	2549	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
bogdanm	0:9b334a45a8ff	2550	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
bogdanm	0:9b334a45a8ff	2551	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
bogdanm	0:9b334a45a8ff	2552
bogdanm	0:9b334a45a8ff	2553	/***************** Bit definition for TIM_EGR register *****************/
bogdanm	0:9b334a45a8ff	2554	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
bogdanm	0:9b334a45a8ff	2555	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
bogdanm	0:9b334a45a8ff	2556	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
bogdanm	0:9b334a45a8ff	2557	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
bogdanm	0:9b334a45a8ff	2558	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
bogdanm	0:9b334a45a8ff	2559	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
bogdanm	0:9b334a45a8ff	2560	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
bogdanm	0:9b334a45a8ff	2561	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
bogdanm	0:9b334a45a8ff	2562
bogdanm	0:9b334a45a8ff	2563	/**************** Bit definition for TIM_CCMR1 register ****************/
bogdanm	0:9b334a45a8ff	2564	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
bogdanm	0:9b334a45a8ff	2565	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2566	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2567
bogdanm	0:9b334a45a8ff	2568	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
bogdanm	0:9b334a45a8ff	2569	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
bogdanm	0:9b334a45a8ff	2570
bogdanm	0:9b334a45a8ff	2571	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
bogdanm	0:9b334a45a8ff	2572	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2573	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2574	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2575
bogdanm	0:9b334a45a8ff	2576	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
bogdanm	0:9b334a45a8ff	2577
bogdanm	0:9b334a45a8ff	2578	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
bogdanm	0:9b334a45a8ff	2579	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2580	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2581
bogdanm	0:9b334a45a8ff	2582	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
bogdanm	0:9b334a45a8ff	2583	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
bogdanm	0:9b334a45a8ff	2584
bogdanm	0:9b334a45a8ff	2585	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
bogdanm	0:9b334a45a8ff	2586	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2587	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2588	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2589
bogdanm	0:9b334a45a8ff	2590	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
bogdanm	0:9b334a45a8ff	2591
bogdanm	0:9b334a45a8ff	2592	/---------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2593
bogdanm	0:9b334a45a8ff	2594	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
bogdanm	0:9b334a45a8ff	2595	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2596	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2597
bogdanm	0:9b334a45a8ff	2598	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
bogdanm	0:9b334a45a8ff	2599	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2600	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2601	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2602	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2603
bogdanm	0:9b334a45a8ff	2604	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
bogdanm	0:9b334a45a8ff	2605	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2606	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2607
bogdanm	0:9b334a45a8ff	2608	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
bogdanm	0:9b334a45a8ff	2609	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2610	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2611	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2612	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2613
bogdanm	0:9b334a45a8ff	2614	/**************** Bit definition for TIM_CCMR2 register ****************/
bogdanm	0:9b334a45a8ff	2615	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
bogdanm	0:9b334a45a8ff	2616	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2617	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2618
bogdanm	0:9b334a45a8ff	2619	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
bogdanm	0:9b334a45a8ff	2620	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
bogdanm	0:9b334a45a8ff	2621
bogdanm	0:9b334a45a8ff	2622	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
bogdanm	0:9b334a45a8ff	2623	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2624	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2625	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2626
bogdanm	0:9b334a45a8ff	2627	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
bogdanm	0:9b334a45a8ff	2628
bogdanm	0:9b334a45a8ff	2629	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
bogdanm	0:9b334a45a8ff	2630	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2631	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2632
bogdanm	0:9b334a45a8ff	2633	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
bogdanm	0:9b334a45a8ff	2634	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
bogdanm	0:9b334a45a8ff	2635
bogdanm	0:9b334a45a8ff	2636	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
bogdanm	0:9b334a45a8ff	2637	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2638	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2639	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2640
bogdanm	0:9b334a45a8ff	2641	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
bogdanm	0:9b334a45a8ff	2642
bogdanm	0:9b334a45a8ff	2643	/---------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2644
bogdanm	0:9b334a45a8ff	2645	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
bogdanm	0:9b334a45a8ff	2646	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2647	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2648
bogdanm	0:9b334a45a8ff	2649	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
bogdanm	0:9b334a45a8ff	2650	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2651	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2652	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2653	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2654
bogdanm	0:9b334a45a8ff	2655	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
bogdanm	0:9b334a45a8ff	2656	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2657	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2658
bogdanm	0:9b334a45a8ff	2659	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
bogdanm	0:9b334a45a8ff	2660	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2661	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2662	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2663	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2664
bogdanm	0:9b334a45a8ff	2665	/***************** Bit definition for TIM_CCER register ****************/
bogdanm	0:9b334a45a8ff	2666	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
bogdanm	0:9b334a45a8ff	2667	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
bogdanm	0:9b334a45a8ff	2668	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
bogdanm	0:9b334a45a8ff	2669	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	2670	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
bogdanm	0:9b334a45a8ff	2671	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
bogdanm	0:9b334a45a8ff	2672	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
bogdanm	0:9b334a45a8ff	2673	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	2674	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
bogdanm	0:9b334a45a8ff	2675	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
bogdanm	0:9b334a45a8ff	2676	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
bogdanm	0:9b334a45a8ff	2677	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	2678	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
bogdanm	0:9b334a45a8ff	2679	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
bogdanm	0:9b334a45a8ff	2680	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	2681
bogdanm	0:9b334a45a8ff	2682	/***************** Bit definition for TIM_CNT register *****************/
bogdanm	0:9b334a45a8ff	2683	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
bogdanm	0:9b334a45a8ff	2684
bogdanm	0:9b334a45a8ff	2685	/***************** Bit definition for TIM_PSC register *****************/
bogdanm	0:9b334a45a8ff	2686	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
bogdanm	0:9b334a45a8ff	2687
bogdanm	0:9b334a45a8ff	2688	/***************** Bit definition for TIM_ARR register *****************/
bogdanm	0:9b334a45a8ff	2689	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
bogdanm	0:9b334a45a8ff	2690
bogdanm	0:9b334a45a8ff	2691	/***************** Bit definition for TIM_RCR register *****************/
bogdanm	0:9b334a45a8ff	2692	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
bogdanm	0:9b334a45a8ff	2693
bogdanm	0:9b334a45a8ff	2694	/***************** Bit definition for TIM_CCR1 register ****************/
bogdanm	0:9b334a45a8ff	2695	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
bogdanm	0:9b334a45a8ff	2696
bogdanm	0:9b334a45a8ff	2697	/***************** Bit definition for TIM_CCR2 register ****************/
bogdanm	0:9b334a45a8ff	2698	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
bogdanm	0:9b334a45a8ff	2699
bogdanm	0:9b334a45a8ff	2700	/***************** Bit definition for TIM_CCR3 register ****************/
bogdanm	0:9b334a45a8ff	2701	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
bogdanm	0:9b334a45a8ff	2702
bogdanm	0:9b334a45a8ff	2703	/***************** Bit definition for TIM_CCR4 register ****************/
bogdanm	0:9b334a45a8ff	2704	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
bogdanm	0:9b334a45a8ff	2705
bogdanm	0:9b334a45a8ff	2706	/***************** Bit definition for TIM_BDTR register ****************/
bogdanm	0:9b334a45a8ff	2707	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
bogdanm	0:9b334a45a8ff	2708	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2709	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2710	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2711	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2712	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	2713	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	2714	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	2715	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	2716
bogdanm	0:9b334a45a8ff	2717	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
bogdanm	0:9b334a45a8ff	2718	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2719	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2720
bogdanm	0:9b334a45a8ff	2721	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
bogdanm	0:9b334a45a8ff	2722	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
bogdanm	0:9b334a45a8ff	2723	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
bogdanm	0:9b334a45a8ff	2724	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
bogdanm	0:9b334a45a8ff	2725	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
bogdanm	0:9b334a45a8ff	2726	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
bogdanm	0:9b334a45a8ff	2727
bogdanm	0:9b334a45a8ff	2728	/***************** Bit definition for TIM_DCR register *****************/
bogdanm	0:9b334a45a8ff	2729	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
bogdanm	0:9b334a45a8ff	2730	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2731	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2732	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2733	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2734	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	2735
bogdanm	0:9b334a45a8ff	2736	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
bogdanm	0:9b334a45a8ff	2737	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2738	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2739	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2740	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2741	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	2742
bogdanm	0:9b334a45a8ff	2743	/***************** Bit definition for TIM_DMAR register ****************/
bogdanm	0:9b334a45a8ff	2744	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
bogdanm	0:9b334a45a8ff	2745
bogdanm	0:9b334a45a8ff	2746	/***************** Bit definition for TIM14_OR register ******************/
bogdanm	0:9b334a45a8ff	2747	#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
bogdanm	0:9b334a45a8ff	2748	#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2749	#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2750
bogdanm	0:9b334a45a8ff	2751	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2752	/* */
bogdanm	0:9b334a45a8ff	2753	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm	0:9b334a45a8ff	2754	/* */
bogdanm	0:9b334a45a8ff	2755	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2756	/**************** Bit definition for USART_CR1 register *****************/
bogdanm	0:9b334a45a8ff	2757	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
bogdanm	0:9b334a45a8ff	2758	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
bogdanm	0:9b334a45a8ff	2759	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
bogdanm	0:9b334a45a8ff	2760	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
bogdanm	0:9b334a45a8ff	2761	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
bogdanm	0:9b334a45a8ff	2762	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
bogdanm	0:9b334a45a8ff	2763	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
bogdanm	0:9b334a45a8ff	2764	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
bogdanm	0:9b334a45a8ff	2765	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
bogdanm	0:9b334a45a8ff	2766	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
bogdanm	0:9b334a45a8ff	2767	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
bogdanm	0:9b334a45a8ff	2768	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
bogdanm	0:9b334a45a8ff	2769	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length bit 0 /
bogdanm	0:9b334a45a8ff	2770	#define USART_CR1_M ((uint32_t)0x00001000) /!< SmartCard Length /
bogdanm	0:9b334a45a8ff	2771	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
bogdanm	0:9b334a45a8ff	2772	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
bogdanm	0:9b334a45a8ff	2773	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
bogdanm	0:9b334a45a8ff	2774	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
bogdanm	0:9b334a45a8ff	2775	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2776	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2777	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2778	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2779	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2780	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
bogdanm	0:9b334a45a8ff	2781	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2782	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2783	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2784	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2785	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2786	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
bogdanm	0:9b334a45a8ff	2787	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
bogdanm	0:9b334a45a8ff	2788
bogdanm	0:9b334a45a8ff	2789	/**************** Bit definition for USART_CR2 register *****************/
bogdanm	0:9b334a45a8ff	2790	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
bogdanm	0:9b334a45a8ff	2791	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
bogdanm	0:9b334a45a8ff	2792	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
bogdanm	0:9b334a45a8ff	2793	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
bogdanm	0:9b334a45a8ff	2794	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
bogdanm	0:9b334a45a8ff	2795	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
bogdanm	0:9b334a45a8ff	2796	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
bogdanm	0:9b334a45a8ff	2797	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
bogdanm	0:9b334a45a8ff	2798	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2799	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2800	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
bogdanm	0:9b334a45a8ff	2801	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
bogdanm	0:9b334a45a8ff	2802	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
bogdanm	0:9b334a45a8ff	2803	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
bogdanm	0:9b334a45a8ff	2804	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
bogdanm	0:9b334a45a8ff	2805	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
bogdanm	0:9b334a45a8ff	2806	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
bogdanm	0:9b334a45a8ff	2807	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
bogdanm	0:9b334a45a8ff	2808	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2809	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2810	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
bogdanm	0:9b334a45a8ff	2811	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
bogdanm	0:9b334a45a8ff	2812
bogdanm	0:9b334a45a8ff	2813	/**************** Bit definition for USART_CR3 register *****************/
bogdanm	0:9b334a45a8ff	2814	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	2815	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
bogdanm	0:9b334a45a8ff	2816	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
bogdanm	0:9b334a45a8ff	2817	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
bogdanm	0:9b334a45a8ff	2818	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
bogdanm	0:9b334a45a8ff	2819	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
bogdanm	0:9b334a45a8ff	2820	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
bogdanm	0:9b334a45a8ff	2821	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
bogdanm	0:9b334a45a8ff	2822	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
bogdanm	0:9b334a45a8ff	2823	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
bogdanm	0:9b334a45a8ff	2824	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
bogdanm	0:9b334a45a8ff	2825	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
bogdanm	0:9b334a45a8ff	2826	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
bogdanm	0:9b334a45a8ff	2827	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
bogdanm	0:9b334a45a8ff	2828	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
bogdanm	0:9b334a45a8ff	2829	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
bogdanm	0:9b334a45a8ff	2830	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
bogdanm	0:9b334a45a8ff	2831	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2832	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2833	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2834	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
bogdanm	0:9b334a45a8ff	2835	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2836	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2837	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
bogdanm	0:9b334a45a8ff	2838
bogdanm	0:9b334a45a8ff	2839	/**************** Bit definition for USART_BRR register *****************/
bogdanm	0:9b334a45a8ff	2840	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
bogdanm	0:9b334a45a8ff	2841	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
bogdanm	0:9b334a45a8ff	2842
bogdanm	0:9b334a45a8ff	2843	/**************** Bit definition for USART_GTPR register ****************/
bogdanm	0:9b334a45a8ff	2844	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
bogdanm	0:9b334a45a8ff	2845	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
bogdanm	0:9b334a45a8ff	2846
bogdanm	0:9b334a45a8ff	2847
bogdanm	0:9b334a45a8ff	2848	/***************** Bit definition for USART_RTOR register ***************/
bogdanm	0:9b334a45a8ff	2849	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
bogdanm	0:9b334a45a8ff	2850	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
bogdanm	0:9b334a45a8ff	2851
bogdanm	0:9b334a45a8ff	2852	/***************** Bit definition for USART_RQR register ****************/
bogdanm	0:9b334a45a8ff	2853	#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /!< Auto-Baud Rate Request /
bogdanm	0:9b334a45a8ff	2854	#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /!< Send Break Request /
bogdanm	0:9b334a45a8ff	2855	#define USART_RQR_MMRQ ((uint32_t)0x00000004) /!< Mute Mode Request /
bogdanm	0:9b334a45a8ff	2856	#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /!< Receive Data flush Request /
bogdanm	0:9b334a45a8ff	2857	#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /!< Transmit data flush Request /
bogdanm	0:9b334a45a8ff	2858
bogdanm	0:9b334a45a8ff	2859	/***************** Bit definition for USART_ISR register ****************/
bogdanm	0:9b334a45a8ff	2860	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
bogdanm	0:9b334a45a8ff	2861	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
bogdanm	0:9b334a45a8ff	2862	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
bogdanm	0:9b334a45a8ff	2863	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
bogdanm	0:9b334a45a8ff	2864	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
bogdanm	0:9b334a45a8ff	2865	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
bogdanm	0:9b334a45a8ff	2866	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
bogdanm	0:9b334a45a8ff	2867	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
bogdanm	0:9b334a45a8ff	2868	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
bogdanm	0:9b334a45a8ff	2869	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
bogdanm	0:9b334a45a8ff	2870	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
bogdanm	0:9b334a45a8ff	2871	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
bogdanm	0:9b334a45a8ff	2872	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
bogdanm	0:9b334a45a8ff	2873	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
bogdanm	0:9b334a45a8ff	2874	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
bogdanm	0:9b334a45a8ff	2875	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
bogdanm	0:9b334a45a8ff	2876	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
bogdanm	0:9b334a45a8ff	2877	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
bogdanm	0:9b334a45a8ff	2878	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
bogdanm	0:9b334a45a8ff	2879	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
bogdanm	0:9b334a45a8ff	2880	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
bogdanm	0:9b334a45a8ff	2881	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
bogdanm	0:9b334a45a8ff	2882
bogdanm	0:9b334a45a8ff	2883	/***************** Bit definition for USART_ICR register ****************/
bogdanm	0:9b334a45a8ff	2884	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
bogdanm	0:9b334a45a8ff	2885	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
bogdanm	0:9b334a45a8ff	2886	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
bogdanm	0:9b334a45a8ff	2887	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
bogdanm	0:9b334a45a8ff	2888	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
bogdanm	0:9b334a45a8ff	2889	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
bogdanm	0:9b334a45a8ff	2890	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
bogdanm	0:9b334a45a8ff	2891	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
bogdanm	0:9b334a45a8ff	2892	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
bogdanm	0:9b334a45a8ff	2893	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
bogdanm	0:9b334a45a8ff	2894	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
bogdanm	0:9b334a45a8ff	2895	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
bogdanm	0:9b334a45a8ff	2896
bogdanm	0:9b334a45a8ff	2897	/***************** Bit definition for USART_RDR register ****************/
bogdanm	0:9b334a45a8ff	2898	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
bogdanm	0:9b334a45a8ff	2899
bogdanm	0:9b334a45a8ff	2900	/***************** Bit definition for USART_TDR register ****************/
bogdanm	0:9b334a45a8ff	2901	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
bogdanm	0:9b334a45a8ff	2902
bogdanm	0:9b334a45a8ff	2903	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2904	/* */
bogdanm	0:9b334a45a8ff	2905	/* Window WATCHDOG (WWDG) */
bogdanm	0:9b334a45a8ff	2906	/* */
bogdanm	0:9b334a45a8ff	2907	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2908	/***************** Bit definition for WWDG_CR register ******************/
bogdanm	0:9b334a45a8ff	2909	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
bogdanm	0:9b334a45a8ff	2910	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2911	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2912	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2913	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2914	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	2915	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	2916	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	2917
bogdanm	0:9b334a45a8ff	2918	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
bogdanm	0:9b334a45a8ff	2919
bogdanm	0:9b334a45a8ff	2920	/***************** Bit definition for WWDG_CFR register *****************/
bogdanm	0:9b334a45a8ff	2921	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
bogdanm	0:9b334a45a8ff	2922	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2923	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2924	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2925	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2926	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	2927	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	2928	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	2929
bogdanm	0:9b334a45a8ff	2930	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
bogdanm	0:9b334a45a8ff	2931	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2932	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2933
bogdanm	0:9b334a45a8ff	2934	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
bogdanm	0:9b334a45a8ff	2935
bogdanm	0:9b334a45a8ff	2936	/***************** Bit definition for WWDG_SR register ******************/
bogdanm	0:9b334a45a8ff	2937	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
bogdanm	0:9b334a45a8ff	2938
bogdanm	0:9b334a45a8ff	2939	/**
bogdanm	0:9b334a45a8ff	2940	* @}
bogdanm	0:9b334a45a8ff	2941	*/
bogdanm	0:9b334a45a8ff	2942
bogdanm	0:9b334a45a8ff	2943	/**
bogdanm	0:9b334a45a8ff	2944	* @}
bogdanm	0:9b334a45a8ff	2945	*/
bogdanm	0:9b334a45a8ff	2946
bogdanm	0:9b334a45a8ff	2947
bogdanm	0:9b334a45a8ff	2948	/** @addtogroup Exported_macro
bogdanm	0:9b334a45a8ff	2949	* @{
bogdanm	0:9b334a45a8ff	2950	*/
bogdanm	0:9b334a45a8ff	2951
bogdanm	0:9b334a45a8ff	2952	/**************************** ADC Instances *******************************/
bogdanm	0:9b334a45a8ff	2953	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
bogdanm	0:9b334a45a8ff	2954
bogdanm	0:9b334a45a8ff	2955	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
bogdanm	0:9b334a45a8ff	2956
bogdanm	0:9b334a45a8ff	2957	/**************************** CRC Instances *******************************/
bogdanm	0:9b334a45a8ff	2958	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm	0:9b334a45a8ff	2959
bogdanm	0:9b334a45a8ff	2960	/***************************** DMA Instances ****************************/
bogdanm	0:9b334a45a8ff	2961	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
bogdanm	0:9b334a45a8ff	2962	((INSTANCE) == DMA1_Channel2) \|\| \
bogdanm	0:9b334a45a8ff	2963	((INSTANCE) == DMA1_Channel3) \|\| \
bogdanm	0:9b334a45a8ff	2964	((INSTANCE) == DMA1_Channel4) \|\| \
bogdanm	0:9b334a45a8ff	2965	((INSTANCE) == DMA1_Channel5))
bogdanm	0:9b334a45a8ff	2966
bogdanm	0:9b334a45a8ff	2967	/**************************** GPIO Instances ******************************/
bogdanm	0:9b334a45a8ff	2968	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
bogdanm	0:9b334a45a8ff	2969	((INSTANCE) == GPIOB) \|\| \
bogdanm	0:9b334a45a8ff	2970	((INSTANCE) == GPIOC) \|\| \
bogdanm	0:9b334a45a8ff	2971	((INSTANCE) == GPIOF))
bogdanm	0:9b334a45a8ff	2972
bogdanm	0:9b334a45a8ff	2973	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
bogdanm	0:9b334a45a8ff	2974	((INSTANCE) == GPIOB))
bogdanm	0:9b334a45a8ff	2975
bogdanm	0:9b334a45a8ff	2976	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
bogdanm	0:9b334a45a8ff	2977	((INSTANCE) == GPIOB))
bogdanm	0:9b334a45a8ff	2978
bogdanm	0:9b334a45a8ff	2979	/**************************** I2C Instances *******************************/
bogdanm	0:9b334a45a8ff	2980	#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
bogdanm	0:9b334a45a8ff	2981
bogdanm	0:9b334a45a8ff	2982	/**************************** I2S Instances *******************************/
bogdanm	0:9b334a45a8ff	2983	#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
bogdanm	0:9b334a45a8ff	2984
bogdanm	0:9b334a45a8ff	2985	/**************************** IWDG Instances ******************************/
bogdanm	0:9b334a45a8ff	2986	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm	0:9b334a45a8ff	2987
bogdanm	0:9b334a45a8ff	2988	/**************************** RTC Instances *******************************/
bogdanm	0:9b334a45a8ff	2989	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm	0:9b334a45a8ff	2990
bogdanm	0:9b334a45a8ff	2991	/**************************** SMBUS Instances *******************************/
bogdanm	0:9b334a45a8ff	2992	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
bogdanm	0:9b334a45a8ff	2993
bogdanm	0:9b334a45a8ff	2994	/**************************** SPI Instances *******************************/
bogdanm	0:9b334a45a8ff	2995	#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
bogdanm	0:9b334a45a8ff	2996
bogdanm	0:9b334a45a8ff	2997	/**************************** TIM Instances *******************************/
bogdanm	0:9b334a45a8ff	2998	#define IS_TIM_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	2999	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3000	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3001	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3002	((INSTANCE) == TIM14) \|\| \
bogdanm	0:9b334a45a8ff	3003	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3004	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3005
bogdanm	0:9b334a45a8ff	3006	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3007	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3008	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3009	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3010	((INSTANCE) == TIM14) \|\| \
bogdanm	0:9b334a45a8ff	3011	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3012	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3013
bogdanm	0:9b334a45a8ff	3014	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3015	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3016	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3017	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3018
bogdanm	0:9b334a45a8ff	3019	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3020	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3021	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3022	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3023
bogdanm	0:9b334a45a8ff	3024	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3025	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3026	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3027	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3028
bogdanm	0:9b334a45a8ff	3029
bogdanm	0:9b334a45a8ff	3030	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3031	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3032	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3033	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3034
bogdanm	0:9b334a45a8ff	3035	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3036	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3037	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3038	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3039
bogdanm	0:9b334a45a8ff	3040	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3041	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3042	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3043	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3044
bogdanm	0:9b334a45a8ff	3045	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3046	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3047	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3048	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3049
bogdanm	0:9b334a45a8ff	3050	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3051	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3052	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3053	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3054
bogdanm	0:9b334a45a8ff	3055	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3056	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3057	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3058	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3059
bogdanm	0:9b334a45a8ff	3060	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3061	(((INSTANCE) == TIM1))
bogdanm	0:9b334a45a8ff	3062
bogdanm	0:9b334a45a8ff	3063	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3064	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3065	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3066	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3067
bogdanm	0:9b334a45a8ff	3068	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3069	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3070	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3071	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3072
bogdanm	0:9b334a45a8ff	3073	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3074	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3075	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3076	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3077
bogdanm	0:9b334a45a8ff	3078	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3079	((INSTANCE) == TIM2)
bogdanm	0:9b334a45a8ff	3080
bogdanm	0:9b334a45a8ff	3081	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3082	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3083	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3084	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3085	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3086	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3087
bogdanm	0:9b334a45a8ff	3088	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3089	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3090	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3091	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3092
bogdanm	0:9b334a45a8ff	3093	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm	0:9b334a45a8ff	3094	((((INSTANCE) == TIM1) && \
bogdanm	0:9b334a45a8ff	3095	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3096	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3097	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	3098	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	3099	\|\| \
bogdanm	0:9b334a45a8ff	3100	(((INSTANCE) == TIM2) && \
bogdanm	0:9b334a45a8ff	3101	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3102	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3103	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	3104	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	3105	\|\| \
bogdanm	0:9b334a45a8ff	3106	(((INSTANCE) == TIM3) && \
bogdanm	0:9b334a45a8ff	3107	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3108	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3109	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	3110	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	3111	\|\| \
bogdanm	0:9b334a45a8ff	3112	(((INSTANCE) == TIM14) && \
bogdanm	0:9b334a45a8ff	3113	(((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm	0:9b334a45a8ff	3114	\|\| \
bogdanm	0:9b334a45a8ff	3115	(((INSTANCE) == TIM16) && \
bogdanm	0:9b334a45a8ff	3116	(((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm	0:9b334a45a8ff	3117	\|\| \
bogdanm	0:9b334a45a8ff	3118	(((INSTANCE) == TIM17) && \
bogdanm	0:9b334a45a8ff	3119	(((CHANNEL) == TIM_CHANNEL_1))))
bogdanm	0:9b334a45a8ff	3120
bogdanm	0:9b334a45a8ff	3121	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm	0:9b334a45a8ff	3122	((((INSTANCE) == TIM1) && \
bogdanm	0:9b334a45a8ff	3123	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3124	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3125	((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm	0:9b334a45a8ff	3126	\|\| \
bogdanm	0:9b334a45a8ff	3127	(((INSTANCE) == TIM16) && \
bogdanm	0:9b334a45a8ff	3128	((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm	0:9b334a45a8ff	3129	\|\| \
bogdanm	0:9b334a45a8ff	3130	(((INSTANCE) == TIM17) && \
bogdanm	0:9b334a45a8ff	3131	((CHANNEL) == TIM_CHANNEL_1)))
bogdanm	0:9b334a45a8ff	3132
bogdanm	0:9b334a45a8ff	3133	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3134	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3135	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3136	((INSTANCE) == TIM3))
bogdanm	0:9b334a45a8ff	3137
bogdanm	0:9b334a45a8ff	3138	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3139	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3140	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3141	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3142
bogdanm	0:9b334a45a8ff	3143	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3144	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3145	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3146	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3147	((INSTANCE) == TIM14) \|\| \
bogdanm	0:9b334a45a8ff	3148	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3149	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3150
bogdanm	0:9b334a45a8ff	3151	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3152	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3153	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3154	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3155	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3156	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3157
bogdanm	0:9b334a45a8ff	3158	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3159	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3160	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3161	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3162	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3163	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3164
bogdanm	0:9b334a45a8ff	3165	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3166	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3167	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3168	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3169
bogdanm	0:9b334a45a8ff	3170	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3171	((INSTANCE) == TIM14)
bogdanm	0:9b334a45a8ff	3172
bogdanm	0:9b334a45a8ff	3173	/********************* UART Instances : IRDA mode *************************/
bogdanm	0:9b334a45a8ff	3174	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
bogdanm	0:9b334a45a8ff	3175
bogdanm	0:9b334a45a8ff	3176	/******************* UART Instances : Smard card mode *********************/
bogdanm	0:9b334a45a8ff	3177	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
bogdanm	0:9b334a45a8ff	3178
bogdanm	0:9b334a45a8ff	3179	/****************** USART Instances : Synchronous mode ********************/
bogdanm	0:9b334a45a8ff	3180	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
bogdanm	0:9b334a45a8ff	3181
bogdanm	0:9b334a45a8ff	3182	/****************** USART Instances : auto Baud rate detection ************/
bogdanm	0:9b334a45a8ff	3183	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
bogdanm	0:9b334a45a8ff	3184
bogdanm	0:9b334a45a8ff	3185	/****************** UART Instances : Asynchronous mode ********************/
bogdanm	0:9b334a45a8ff	3186	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
bogdanm	0:9b334a45a8ff	3187
bogdanm	0:9b334a45a8ff	3188	/****************** UART Instances : Half-Duplex mode ********************/
bogdanm	0:9b334a45a8ff	3189	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm	0:9b334a45a8ff	3190
bogdanm	0:9b334a45a8ff	3191	/**************** UART Instances : Hardware Flow control ******************/
bogdanm	0:9b334a45a8ff	3192	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
bogdanm	0:9b334a45a8ff	3193
bogdanm	0:9b334a45a8ff	3194	/**************** UART Instances : LIN mode ******************/
bogdanm	0:9b334a45a8ff	3195	#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm	0:9b334a45a8ff	3196
bogdanm	0:9b334a45a8ff	3197	/**************** UART Instances : wakeup from stop mode ******************/
bogdanm	0:9b334a45a8ff	3198	#define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm	0:9b334a45a8ff	3199
bogdanm	0:9b334a45a8ff	3200	/**************** UART Instances : Auto Baud Rate detection ******************/
bogdanm	0:9b334a45a8ff	3201	#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
bogdanm	0:9b334a45a8ff	3202
bogdanm	0:9b334a45a8ff	3203	/**************** UART Instances : Driver enable detection ******************/
bogdanm	0:9b334a45a8ff	3204	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
bogdanm	0:9b334a45a8ff	3205
bogdanm	0:9b334a45a8ff	3206	/**************************** WWDG Instances ******************************/
bogdanm	0:9b334a45a8ff	3207	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm	0:9b334a45a8ff	3208
bogdanm	0:9b334a45a8ff	3209	/**
bogdanm	0:9b334a45a8ff	3210	* @}
bogdanm	0:9b334a45a8ff	3211	*/
bogdanm	0:9b334a45a8ff	3212
bogdanm	0:9b334a45a8ff	3213
bogdanm	0:9b334a45a8ff	3214	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3215	/* For a painless codes migration between the STM32F0xx device product */
bogdanm	0:9b334a45a8ff	3216	/* lines, the aliases defined below are put in place to overcome the */
bogdanm	0:9b334a45a8ff	3217	/* differences in the interrupt handlers and IRQn definitions. */
bogdanm	0:9b334a45a8ff	3218	/* No need to update developed interrupt code when moving across */
bogdanm	0:9b334a45a8ff	3219	/* product lines within the same STM32F0 Family */
bogdanm	0:9b334a45a8ff	3220	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3221
bogdanm	0:9b334a45a8ff	3222	/* Aliases for __IRQn */
bogdanm	0:9b334a45a8ff	3223	#define PVD_VDDIO2_IRQn PVD_IRQn
bogdanm	0:9b334a45a8ff	3224	#define RCC_CRS_IRQn RCC_IRQn
bogdanm	0:9b334a45a8ff	3225	#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
bogdanm	0:9b334a45a8ff	3226	#define ADC1_COMP_IRQn ADC1_IRQn
bogdanm	0:9b334a45a8ff	3227
bogdanm	0:9b334a45a8ff	3228	/* Aliases for __IRQHandler */
bogdanm	0:9b334a45a8ff	3229	#define PVD_VDDIO2_IRQHandler PVD_IRQHandler
bogdanm	0:9b334a45a8ff	3230	#define RCC_CRS_IRQHandler RCC_IRQHandler
bogdanm	0:9b334a45a8ff	3231	#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
bogdanm	0:9b334a45a8ff	3232	#define ADC1_COMP_IRQHandler ADC1_IRQHandler
bogdanm	0:9b334a45a8ff	3233
bogdanm	0:9b334a45a8ff	3234	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	3235	}
bogdanm	0:9b334a45a8ff	3236	#endif /* __cplusplus */
bogdanm	0:9b334a45a8ff	3237
bogdanm	0:9b334a45a8ff	3238	#endif /* __STM32F031x6_H */
bogdanm	0:9b334a45a8ff	3239
bogdanm	0:9b334a45a8ff	3240	/**
bogdanm	0:9b334a45a8ff	3241	* @}
bogdanm	0:9b334a45a8ff	3242	*/
bogdanm	0:9b334a45a8ff	3243
bogdanm	0:9b334a45a8ff	3244	/**
bogdanm	0:9b334a45a8ff	3245	* @}
bogdanm	0:9b334a45a8ff	3246	*/
bogdanm	0:9b334a45a8ff	3247
bogdanm	0:9b334a45a8ff	3248	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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