en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 * @brief LPC43xx/LPC18xx mcu header
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Copyright(C) NXP Semiconductors, 2012
bogdanm 0:9b334a45a8ff 5 * All rights reserved.
bogdanm 0:9b334a45a8ff 6 *
bogdanm 0:9b334a45a8ff 7 * Software that is described herein is for illustrative purposes only
bogdanm 0:9b334a45a8ff 8 * which provides customers with programming information regarding the
bogdanm 0:9b334a45a8ff 9 * LPC products. This software is supplied "AS IS" without any warranties of
bogdanm 0:9b334a45a8ff 10 * any kind, and NXP Semiconductors and its licensor disclaim any and
bogdanm 0:9b334a45a8ff 11 * all warranties, express or implied, including all implied warranties of
bogdanm 0:9b334a45a8ff 12 * merchantability, fitness for a particular purpose and non-infringement of
bogdanm 0:9b334a45a8ff 13 * intellectual property rights. NXP Semiconductors assumes no responsibility
bogdanm 0:9b334a45a8ff 14 * or liability for the use of the software, conveys no license or rights under any
bogdanm 0:9b334a45a8ff 15 * patent, copyright, mask work right, or any other intellectual property rights in
bogdanm 0:9b334a45a8ff 16 * or to any products. NXP Semiconductors reserves the right to make changes
bogdanm 0:9b334a45a8ff 17 * in the software without notification. NXP Semiconductors also makes no
bogdanm 0:9b334a45a8ff 18 * representation or warranty that such application will be suitable for the
bogdanm 0:9b334a45a8ff 19 * specified use without further testing or modification.
bogdanm 0:9b334a45a8ff 20 *
bogdanm 0:9b334a45a8ff 21 * Permission to use, copy, modify, and distribute this software and its
bogdanm 0:9b334a45a8ff 22 * documentation is hereby granted, under NXP Semiconductors' and its
bogdanm 0:9b334a45a8ff 23 * licensor's relevant copyrights in the software, without fee, provided that it
bogdanm 0:9b334a45a8ff 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 0:9b334a45a8ff 25 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 0:9b334a45a8ff 26 * this code.
bogdanm 0:9b334a45a8ff 27 */
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 #ifndef __SYSTEM_LPC43XX_H
bogdanm 0:9b334a45a8ff 30 #define __SYSTEM_LPC43XX_H
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 33 extern "C" {
bogdanm 0:9b334a45a8ff 34 #endif
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 /* System initialization options */
bogdanm 0:9b334a45a8ff 37 #define PIN_SETUP 1 /* Configure pins during initialization */
bogdanm 0:9b334a45a8ff 38 #define CLOCK_SETUP 1 /* Configure clocks during initialization */
bogdanm 0:9b334a45a8ff 39 #define MEMORY_SETUP 0 /* Configure external memory during init */
bogdanm 0:9b334a45a8ff 40 #define SPIFI_INIT 1 /* Initialize SPIFI */
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 /* Crystal frequency into device */
bogdanm 0:9b334a45a8ff 43 #define CRYSTAL_MAIN_FREQ_IN 12000000
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 /* Crystal frequency into device for RTC/32K input */
bogdanm 0:9b334a45a8ff 46 #define CRYSTAL_32K_FREQ_IN 32768
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 /* Default CPU clock frequency */
bogdanm 0:9b334a45a8ff 49 #if defined(CHIP_LPC43XX)
bogdanm 0:9b334a45a8ff 50 #define MAX_CLOCK_FREQ (204000000)
bogdanm 0:9b334a45a8ff 51 #else
bogdanm 0:9b334a45a8ff 52 #define MAX_CLOCK_FREQ (180000000)
bogdanm 0:9b334a45a8ff 53 #endif
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
bogdanm 0:9b334a45a8ff 56 /* FPU declarations */
bogdanm 0:9b334a45a8ff 57 #define LPC_CPACR 0xE000ED88
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 #define SCB_MVFR0 0xE000EF40
bogdanm 0:9b334a45a8ff 60 #define SCB_MVFR0_RESET 0x10110021
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 #define SCB_MVFR1 0xE000EF44
bogdanm 0:9b334a45a8ff 63 #define SCB_MVFR1_RESET 0x11000011
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 #if defined(__ARMCC_VERSION)
bogdanm 0:9b334a45a8ff 66 void fpuInit(void) __attribute__ ((section("BOOTSTRAP_CODE")));
bogdanm 0:9b334a45a8ff 67 #else
bogdanm 0:9b334a45a8ff 68 extern void fpuInit(void);
bogdanm 0:9b334a45a8ff 69 #endif
bogdanm 0:9b334a45a8ff 70 #endif
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /**
bogdanm 0:9b334a45a8ff 75 * Initialize the system
bogdanm 0:9b334a45a8ff 76 *
bogdanm 0:9b334a45a8ff 77 * @param none
bogdanm 0:9b334a45a8ff 78 * @return none
bogdanm 0:9b334a45a8ff 79 *
bogdanm 0:9b334a45a8ff 80 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 81 * Initialize the System and update the SystemCoreClock variable.
bogdanm 0:9b334a45a8ff 82 */
bogdanm 0:9b334a45a8ff 83 extern void SystemInit (void);
bogdanm 0:9b334a45a8ff 84 extern void SystemCoreClockUpdate(void);
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 87 }
bogdanm 0:9b334a45a8ff 88 #endif
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 #endif /* __SYSTEM_LPC43XX_H */