en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /******************************************************************************
bogdanm 0:9b334a45a8ff 2 * @file system_LPC13Uxx.c
bogdanm 0:9b334a45a8ff 3 * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
bogdanm 0:9b334a45a8ff 4 * for the NXP LPC13xx Device Series
bogdanm 0:9b334a45a8ff 5 * @version V1.10
bogdanm 0:9b334a45a8ff 6 * @date 24. November 2010
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * @note
bogdanm 0:9b334a45a8ff 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * @par
bogdanm 0:9b334a45a8ff 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 0:9b334a45a8ff 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 14 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * @par
bogdanm 0:9b334a45a8ff 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 ******************************************************************************/
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 #include <stdint.h>
bogdanm 0:9b334a45a8ff 27 #include "LPC13Uxx.h"
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 /*
bogdanm 0:9b334a45a8ff 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 0:9b334a45a8ff 31 */
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 /*--------------------- Clock Configuration ----------------------------------
bogdanm 0:9b334a45a8ff 34 //
bogdanm 0:9b334a45a8ff 35 // <e> Clock Configuration
bogdanm 0:9b334a45a8ff 36 // <h> System Oscillator Control Register (SYSOSCCTRL)
bogdanm 0:9b334a45a8ff 37 // <o1.0> BYPASS: System Oscillator Bypass Enable
bogdanm 0:9b334a45a8ff 38 // <i> If enabled then PLL input (sys_osc_clk) is fed
bogdanm 0:9b334a45a8ff 39 // <i> directly from XTALIN and XTALOUT pins.
bogdanm 0:9b334a45a8ff 40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
bogdanm 0:9b334a45a8ff 41 // <i> Determines frequency range for Low-power oscillator.
bogdanm 0:9b334a45a8ff 42 // <0=> 1 - 20 MHz
bogdanm 0:9b334a45a8ff 43 // <1=> 15 - 25 MHz
bogdanm 0:9b334a45a8ff 44 // </h>
bogdanm 0:9b334a45a8ff 45 //
bogdanm 0:9b334a45a8ff 46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
bogdanm 0:9b334a45a8ff 47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
bogdanm 0:9b334a45a8ff 48 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
bogdanm 0:9b334a45a8ff 49 // <0-31>
bogdanm 0:9b334a45a8ff 50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
bogdanm 0:9b334a45a8ff 51 // <0=> Undefined
bogdanm 0:9b334a45a8ff 52 // <1=> 0.5 MHz
bogdanm 0:9b334a45a8ff 53 // <2=> 0.8 MHz
bogdanm 0:9b334a45a8ff 54 // <3=> 1.1 MHz
bogdanm 0:9b334a45a8ff 55 // <4=> 1.4 MHz
bogdanm 0:9b334a45a8ff 56 // <5=> 1.6 MHz
bogdanm 0:9b334a45a8ff 57 // <6=> 1.8 MHz
bogdanm 0:9b334a45a8ff 58 // <7=> 2.0 MHz
bogdanm 0:9b334a45a8ff 59 // <8=> 2.2 MHz
bogdanm 0:9b334a45a8ff 60 // <9=> 2.4 MHz
bogdanm 0:9b334a45a8ff 61 // <10=> 2.6 MHz
bogdanm 0:9b334a45a8ff 62 // <11=> 2.7 MHz
bogdanm 0:9b334a45a8ff 63 // <12=> 2.9 MHz
bogdanm 0:9b334a45a8ff 64 // <13=> 3.1 MHz
bogdanm 0:9b334a45a8ff 65 // <14=> 3.2 MHz
bogdanm 0:9b334a45a8ff 66 // <15=> 3.4 MHz
bogdanm 0:9b334a45a8ff 67 // </h>
bogdanm 0:9b334a45a8ff 68 //
bogdanm 0:9b334a45a8ff 69 // <h> System PLL Control Register (SYSPLLCTRL)
bogdanm 0:9b334a45a8ff 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 73 // <o3.0..4> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 74 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 75 // <0-31>
bogdanm 0:9b334a45a8ff 76 // <o3.5..6> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 77 // <0=> P = 1
bogdanm 0:9b334a45a8ff 78 // <1=> P = 2
bogdanm 0:9b334a45a8ff 79 // <2=> P = 4
bogdanm 0:9b334a45a8ff 80 // <3=> P = 8
bogdanm 0:9b334a45a8ff 81 // </h>
bogdanm 0:9b334a45a8ff 82 //
bogdanm 0:9b334a45a8ff 83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
bogdanm 0:9b334a45a8ff 84 // <o4.0..1> SEL: System PLL Clock Source
bogdanm 0:9b334a45a8ff 85 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 86 // <1=> System Oscillator
bogdanm 0:9b334a45a8ff 87 // <2=> Reserved
bogdanm 0:9b334a45a8ff 88 // <3=> Reserved
bogdanm 0:9b334a45a8ff 89 // </h>
bogdanm 0:9b334a45a8ff 90 //
bogdanm 0:9b334a45a8ff 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
bogdanm 0:9b334a45a8ff 92 // <o5.0..1> SEL: Clock Source for Main Clock
bogdanm 0:9b334a45a8ff 93 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 94 // <1=> Input Clock to System PLL
bogdanm 0:9b334a45a8ff 95 // <2=> WDT Oscillator
bogdanm 0:9b334a45a8ff 96 // <3=> System PLL Clock Out
bogdanm 0:9b334a45a8ff 97 // </h>
bogdanm 0:9b334a45a8ff 98 //
bogdanm 0:9b334a45a8ff 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
bogdanm 0:9b334a45a8ff 100 // <o6.0..7> DIV: System AHB Clock Divider
bogdanm 0:9b334a45a8ff 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
bogdanm 0:9b334a45a8ff 102 // <i> 0 = is disabled
bogdanm 0:9b334a45a8ff 103 // <0-255>
bogdanm 0:9b334a45a8ff 104 // </h>
bogdanm 0:9b334a45a8ff 105 //
bogdanm 0:9b334a45a8ff 106 // <h> USB PLL Control Register (USBPLLCTRL)
bogdanm 0:9b334a45a8ff 107 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 108 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 109 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 110 // <o7.0..4> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 111 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 112 // <0-31>
bogdanm 0:9b334a45a8ff 113 // <o7.5..6> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 114 // <0=> P = 1
bogdanm 0:9b334a45a8ff 115 // <1=> P = 2
bogdanm 0:9b334a45a8ff 116 // <2=> P = 4
bogdanm 0:9b334a45a8ff 117 // <3=> P = 8
bogdanm 0:9b334a45a8ff 118 // </h>
bogdanm 0:9b334a45a8ff 119 //
bogdanm 0:9b334a45a8ff 120 // <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
bogdanm 0:9b334a45a8ff 121 // <o8.0..1> SEL: USB PLL Clock Source
bogdanm 0:9b334a45a8ff 122 // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
bogdanm 0:9b334a45a8ff 123 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 124 // <1=> System Oscillator
bogdanm 0:9b334a45a8ff 125 // <2=> Reserved
bogdanm 0:9b334a45a8ff 126 // <3=> Reserved
bogdanm 0:9b334a45a8ff 127 // </h>
bogdanm 0:9b334a45a8ff 128 //
bogdanm 0:9b334a45a8ff 129 // <h> USB Clock Source Select Register (USBCLKSEL)
bogdanm 0:9b334a45a8ff 130 // <o9.0..1> SEL: System PLL Clock Source
bogdanm 0:9b334a45a8ff 131 // <0=> USB PLL out
bogdanm 0:9b334a45a8ff 132 // <1=> Main clock
bogdanm 0:9b334a45a8ff 133 // <2=> Reserved
bogdanm 0:9b334a45a8ff 134 // <3=> Reserved
bogdanm 0:9b334a45a8ff 135 // </h>
bogdanm 0:9b334a45a8ff 136 //
bogdanm 0:9b334a45a8ff 137 // <h> USB Clock Divider Register (USBCLKDIV)
bogdanm 0:9b334a45a8ff 138 // <o10.0..7> DIV: USB Clock Divider
bogdanm 0:9b334a45a8ff 139 // <i> Divides USB clock to 48 MHz.
bogdanm 0:9b334a45a8ff 140 // <i> 0 = is disabled
bogdanm 0:9b334a45a8ff 141 // <0-255>
bogdanm 0:9b334a45a8ff 142 // </h>
bogdanm 0:9b334a45a8ff 143 // </e>
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 146 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 147 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 148 #define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
bogdanm 0:9b334a45a8ff 149 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
bogdanm 0:9b334a45a8ff 150 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
bogdanm 0:9b334a45a8ff 151 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 0:9b334a45a8ff 152 #define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
bogdanm 0:9b334a45a8ff 153 #define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
bogdanm 0:9b334a45a8ff 154 #define USBCLKSEL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 155 #define USBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 /*
bogdanm 0:9b334a45a8ff 158 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 0:9b334a45a8ff 159 */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 162 Check the register settings
bogdanm 0:9b334a45a8ff 163 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 164 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 0:9b334a45a8ff 165 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 /* Clock Configuration -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 168 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 169 #error "SYSOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 170 #endif
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 173 #error "WDTOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 174 #endif
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
bogdanm 0:9b334a45a8ff 177 #error "SYSPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 178 #endif
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 181 #error "SYSPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 182 #endif
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 185 #error "MAINCLKSEL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 186 #endif
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
bogdanm 0:9b334a45a8ff 189 #error "SYSAHBCLKDIV: Value out of range!"
bogdanm 0:9b334a45a8ff 190 #endif
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
bogdanm 0:9b334a45a8ff 193 #error "USBPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 194 #endif
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 197 #error "USBPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 198 #endif
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
bogdanm 0:9b334a45a8ff 201 #error "USBCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 202 #endif
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
bogdanm 0:9b334a45a8ff 205 #error "USBCLKDIV: Value out of range!"
bogdanm 0:9b334a45a8ff 206 #endif
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 210 DEFINES
bogdanm 0:9b334a45a8ff 211 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 214 Define clocks
bogdanm 0:9b334a45a8ff 215 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 216 #define __XTAL (12000000UL) /* Oscillator frequency */
bogdanm 0:9b334a45a8ff 217 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
bogdanm 0:9b334a45a8ff 218 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
bogdanm 0:9b334a45a8ff 222 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 225 #if (__FREQSEL == 0)
bogdanm 0:9b334a45a8ff 226 #define __WDT_OSC_CLK ( 0) /* undefined */
bogdanm 0:9b334a45a8ff 227 #elif (__FREQSEL == 1)
bogdanm 0:9b334a45a8ff 228 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 229 #elif (__FREQSEL == 2)
bogdanm 0:9b334a45a8ff 230 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 231 #elif (__FREQSEL == 3)
bogdanm 0:9b334a45a8ff 232 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 233 #elif (__FREQSEL == 4)
bogdanm 0:9b334a45a8ff 234 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 235 #elif (__FREQSEL == 5)
bogdanm 0:9b334a45a8ff 236 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 237 #elif (__FREQSEL == 6)
bogdanm 0:9b334a45a8ff 238 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 239 #elif (__FREQSEL == 7)
bogdanm 0:9b334a45a8ff 240 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 241 #elif (__FREQSEL == 8)
bogdanm 0:9b334a45a8ff 242 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 243 #elif (__FREQSEL == 9)
bogdanm 0:9b334a45a8ff 244 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 245 #elif (__FREQSEL == 10)
bogdanm 0:9b334a45a8ff 246 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 247 #elif (__FREQSEL == 11)
bogdanm 0:9b334a45a8ff 248 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 249 #elif (__FREQSEL == 12)
bogdanm 0:9b334a45a8ff 250 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 251 #elif (__FREQSEL == 13)
bogdanm 0:9b334a45a8ff 252 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 253 #elif (__FREQSEL == 14)
bogdanm 0:9b334a45a8ff 254 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 255 #else
bogdanm 0:9b334a45a8ff 256 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 257 #endif
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /* sys_pllclkin calculation */
bogdanm 0:9b334a45a8ff 260 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 261 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 262 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 263 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
bogdanm 0:9b334a45a8ff 264 #else
bogdanm 0:9b334a45a8ff 265 #define __SYS_PLLCLKIN (0)
bogdanm 0:9b334a45a8ff 266 #endif
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /* main clock calculation */
bogdanm 0:9b334a45a8ff 271 #if ((MAINCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 272 #define __MAIN_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 273 #elif ((MAINCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 274 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
bogdanm 0:9b334a45a8ff 275 #elif ((MAINCLKSEL_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 276 #if (__FREQSEL == 0)
bogdanm 0:9b334a45a8ff 277 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
bogdanm 0:9b334a45a8ff 278 #else
bogdanm 0:9b334a45a8ff 279 #define __MAIN_CLOCK (__WDT_OSC_CLK)
bogdanm 0:9b334a45a8ff 280 #endif
bogdanm 0:9b334a45a8ff 281 #elif ((MAINCLKSEL_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 282 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
bogdanm 0:9b334a45a8ff 283 #else
bogdanm 0:9b334a45a8ff 284 #define __MAIN_CLOCK (0)
bogdanm 0:9b334a45a8ff 285 #endif
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 #else
bogdanm 0:9b334a45a8ff 290 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 291 #endif // CLOCK_SETUP
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 295 Clock Variable definitions
bogdanm 0:9b334a45a8ff 296 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 297 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 301 Clock functions
bogdanm 0:9b334a45a8ff 302 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 303 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 0:9b334a45a8ff 304 {
bogdanm 0:9b334a45a8ff 305 uint32_t wdt_osc = 0;
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 308 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
bogdanm 0:9b334a45a8ff 309 case 0: wdt_osc = 0; break;
bogdanm 0:9b334a45a8ff 310 case 1: wdt_osc = 500000; break;
bogdanm 0:9b334a45a8ff 311 case 2: wdt_osc = 800000; break;
bogdanm 0:9b334a45a8ff 312 case 3: wdt_osc = 1100000; break;
bogdanm 0:9b334a45a8ff 313 case 4: wdt_osc = 1400000; break;
bogdanm 0:9b334a45a8ff 314 case 5: wdt_osc = 1600000; break;
bogdanm 0:9b334a45a8ff 315 case 6: wdt_osc = 1800000; break;
bogdanm 0:9b334a45a8ff 316 case 7: wdt_osc = 2000000; break;
bogdanm 0:9b334a45a8ff 317 case 8: wdt_osc = 2200000; break;
bogdanm 0:9b334a45a8ff 318 case 9: wdt_osc = 2400000; break;
bogdanm 0:9b334a45a8ff 319 case 10: wdt_osc = 2600000; break;
bogdanm 0:9b334a45a8ff 320 case 11: wdt_osc = 2700000; break;
bogdanm 0:9b334a45a8ff 321 case 12: wdt_osc = 2900000; break;
bogdanm 0:9b334a45a8ff 322 case 13: wdt_osc = 3100000; break;
bogdanm 0:9b334a45a8ff 323 case 14: wdt_osc = 3200000; break;
bogdanm 0:9b334a45a8ff 324 case 15: wdt_osc = 3400000; break;
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 329 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 330 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 331 break;
bogdanm 0:9b334a45a8ff 332 case 1: /* Input Clock to System PLL */
bogdanm 0:9b334a45a8ff 333 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 334 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 335 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 336 break;
bogdanm 0:9b334a45a8ff 337 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 338 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 0:9b334a45a8ff 339 break;
bogdanm 0:9b334a45a8ff 340 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 341 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 342 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 343 break;
bogdanm 0:9b334a45a8ff 344 }
bogdanm 0:9b334a45a8ff 345 break;
bogdanm 0:9b334a45a8ff 346 case 2: /* WDT Oscillator */
bogdanm 0:9b334a45a8ff 347 SystemCoreClock = wdt_osc;
bogdanm 0:9b334a45a8ff 348 break;
bogdanm 0:9b334a45a8ff 349 case 3: /* System PLL Clock Out */
bogdanm 0:9b334a45a8ff 350 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 351 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 352 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 0:9b334a45a8ff 353 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 354 } else {
bogdanm 0:9b334a45a8ff 355 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 356 }
bogdanm 0:9b334a45a8ff 357 break;
bogdanm 0:9b334a45a8ff 358 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 359 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 0:9b334a45a8ff 360 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 0:9b334a45a8ff 361 } else {
bogdanm 0:9b334a45a8ff 362 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364 break;
bogdanm 0:9b334a45a8ff 365 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 366 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 367 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 368 break;
bogdanm 0:9b334a45a8ff 369 }
bogdanm 0:9b334a45a8ff 370 break;
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
bogdanm 0:9b334a45a8ff 374
bogdanm 0:9b334a45a8ff 375 }
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /**
bogdanm 0:9b334a45a8ff 378 * Initialize the system
bogdanm 0:9b334a45a8ff 379 *
bogdanm 0:9b334a45a8ff 380 * @param none
bogdanm 0:9b334a45a8ff 381 * @return none
bogdanm 0:9b334a45a8ff 382 *
bogdanm 0:9b334a45a8ff 383 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 384 * Initialize the System.
bogdanm 0:9b334a45a8ff 385 */
bogdanm 0:9b334a45a8ff 386 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 387 volatile uint32_t i;
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 392 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
bogdanm 0:9b334a45a8ff 393 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 394 for (i = 0; i < 200; i++) __NOP();
bogdanm 0:9b334a45a8ff 395 #endif
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 398 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
bogdanm 0:9b334a45a8ff 399 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 400 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
bogdanm 0:9b334a45a8ff 401 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 402 #endif
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 #if (((MAINCLKSEL_Val & 0x03) == 2) )
bogdanm 0:9b334a45a8ff 405 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 406 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
bogdanm 0:9b334a45a8ff 407 for (i = 0; i < 200; i++) __NOP();
bogdanm 0:9b334a45a8ff 408 #endif
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
bogdanm 0:9b334a45a8ff 411
bogdanm 0:9b334a45a8ff 412 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 #if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
bogdanm 0:9b334a45a8ff 415 LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
bogdanm 0:9b334a45a8ff 418 LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
bogdanm 0:9b334a45a8ff 419 LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 420 LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 421 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423 LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
bogdanm 0:9b334a45a8ff 424 LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 #else /* USB clock is not used */
bogdanm 0:9b334a45a8ff 427 LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
bogdanm 0:9b334a45a8ff 428 LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
bogdanm 0:9b334a45a8ff 429 #endif
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 #endif
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 /* System clock to the IOCON needs to be enabled or
bogdanm 0:9b334a45a8ff 434 most of the I/O related peripherals won't work. */
bogdanm 0:9b334a45a8ff 435 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 }