en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K64F/MK64F12.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
121:7f86b4238bec 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 121:7f86b4238bec 1 /*
mbed_official 121:7f86b4238bec 2 ** ###################################################################
mbed_official 121:7f86b4238bec 3 ** Processors: MK64FN1M0VDC12
mbed_official 121:7f86b4238bec 4 ** MK64FN1M0VLL12
mbed_official 121:7f86b4238bec 5 ** MK64FN1M0VLQ12
mbed_official 121:7f86b4238bec 6 ** MK64FN1M0VMD12
mbed_official 121:7f86b4238bec 7 ** MK64FX512VDC12
mbed_official 121:7f86b4238bec 8 ** MK64FX512VLL12
mbed_official 121:7f86b4238bec 9 ** MK64FX512VLQ12
mbed_official 121:7f86b4238bec 10 ** MK64FX512VMD12
mbed_official 121:7f86b4238bec 11 **
mbed_official 121:7f86b4238bec 12 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 121:7f86b4238bec 13 ** Freescale C/C++ for Embedded ARM
mbed_official 121:7f86b4238bec 14 ** GNU C Compiler
mbed_official 121:7f86b4238bec 15 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 121:7f86b4238bec 16 **
mbed_official 121:7f86b4238bec 17 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 121:7f86b4238bec 18 ** Version: rev. 2.8, 2015-02-19
mbed_official 121:7f86b4238bec 19 ** Build: b151218
mbed_official 121:7f86b4238bec 20 **
mbed_official 121:7f86b4238bec 21 ** Abstract:
mbed_official 121:7f86b4238bec 22 ** CMSIS Peripheral Access Layer for MK64F12
mbed_official 121:7f86b4238bec 23 **
mbed_official 121:7f86b4238bec 24 ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
mbed_official 121:7f86b4238bec 25 ** All rights reserved.
mbed_official 121:7f86b4238bec 26 **
mbed_official 121:7f86b4238bec 27 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 121:7f86b4238bec 28 ** are permitted provided that the following conditions are met:
mbed_official 121:7f86b4238bec 29 **
mbed_official 121:7f86b4238bec 30 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 121:7f86b4238bec 31 ** of conditions and the following disclaimer.
mbed_official 121:7f86b4238bec 32 **
mbed_official 121:7f86b4238bec 33 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 121:7f86b4238bec 34 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 121:7f86b4238bec 35 ** other materials provided with the distribution.
mbed_official 121:7f86b4238bec 36 **
mbed_official 121:7f86b4238bec 37 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 121:7f86b4238bec 38 ** contributors may be used to endorse or promote products derived from this
mbed_official 121:7f86b4238bec 39 ** software without specific prior written permission.
mbed_official 121:7f86b4238bec 40 **
mbed_official 121:7f86b4238bec 41 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 121:7f86b4238bec 42 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 121:7f86b4238bec 43 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 121:7f86b4238bec 44 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 121:7f86b4238bec 45 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 121:7f86b4238bec 46 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 121:7f86b4238bec 47 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 121:7f86b4238bec 48 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 121:7f86b4238bec 49 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 121:7f86b4238bec 50 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 121:7f86b4238bec 51 **
mbed_official 121:7f86b4238bec 52 ** http: www.freescale.com
mbed_official 121:7f86b4238bec 53 ** mail: support@freescale.com
mbed_official 121:7f86b4238bec 54 **
mbed_official 121:7f86b4238bec 55 ** Revisions:
mbed_official 121:7f86b4238bec 56 ** - rev. 1.0 (2013-08-12)
mbed_official 121:7f86b4238bec 57 ** Initial version.
mbed_official 121:7f86b4238bec 58 ** - rev. 2.0 (2013-10-29)
mbed_official 121:7f86b4238bec 59 ** Register accessor macros added to the memory map.
mbed_official 121:7f86b4238bec 60 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 121:7f86b4238bec 61 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 121:7f86b4238bec 62 ** System initialization updated.
mbed_official 121:7f86b4238bec 63 ** MCG - registers updated.
mbed_official 121:7f86b4238bec 64 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 121:7f86b4238bec 65 ** - rev. 2.1 (2013-10-30)
mbed_official 121:7f86b4238bec 66 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 121:7f86b4238bec 67 ** - rev. 2.2 (2013-12-09)
mbed_official 121:7f86b4238bec 68 ** DMA - EARS register removed.
mbed_official 121:7f86b4238bec 69 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 121:7f86b4238bec 70 ** - rev. 2.3 (2014-01-24)
mbed_official 121:7f86b4238bec 71 ** Update according to reference manual rev. 2
mbed_official 121:7f86b4238bec 72 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 121:7f86b4238bec 73 ** - rev. 2.4 (2014-02-10)
mbed_official 121:7f86b4238bec 74 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 121:7f86b4238bec 75 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 121:7f86b4238bec 76 ** - rev. 2.5 (2014-02-10)
mbed_official 121:7f86b4238bec 77 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 121:7f86b4238bec 78 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 121:7f86b4238bec 79 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 121:7f86b4238bec 80 ** - rev. 2.6 (2014-08-28)
mbed_official 121:7f86b4238bec 81 ** Update of system files - default clock configuration changed.
mbed_official 121:7f86b4238bec 82 ** Update of startup files - possibility to override DefaultISR added.
mbed_official 121:7f86b4238bec 83 ** - rev. 2.7 (2014-10-14)
mbed_official 121:7f86b4238bec 84 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
mbed_official 121:7f86b4238bec 85 ** - rev. 2.8 (2015-02-19)
mbed_official 121:7f86b4238bec 86 ** Renamed interrupt vector LLW to LLWU.
mbed_official 121:7f86b4238bec 87 **
mbed_official 121:7f86b4238bec 88 ** ###################################################################
mbed_official 121:7f86b4238bec 89 */
mbed_official 121:7f86b4238bec 90
mbed_official 121:7f86b4238bec 91 /*!
mbed_official 121:7f86b4238bec 92 * @file MK64F12.h
mbed_official 121:7f86b4238bec 93 * @version 2.8
mbed_official 121:7f86b4238bec 94 * @date 2015-02-19
mbed_official 121:7f86b4238bec 95 * @brief CMSIS Peripheral Access Layer for MK64F12
mbed_official 121:7f86b4238bec 96 *
mbed_official 121:7f86b4238bec 97 * CMSIS Peripheral Access Layer for MK64F12
mbed_official 121:7f86b4238bec 98 */
mbed_official 121:7f86b4238bec 99
mbed_official 121:7f86b4238bec 100 #ifndef _MK64F12_H_
mbed_official 121:7f86b4238bec 101 #define _MK64F12_H_ /**< Symbol preventing repeated inclusion */
mbed_official 121:7f86b4238bec 102
mbed_official 121:7f86b4238bec 103 /** Memory map major version (memory maps with equal major version number are
mbed_official 121:7f86b4238bec 104 * compatible) */
mbed_official 121:7f86b4238bec 105 #define MCU_MEM_MAP_VERSION 0x0200U
mbed_official 121:7f86b4238bec 106 /** Memory map minor version */
mbed_official 121:7f86b4238bec 107 #define MCU_MEM_MAP_VERSION_MINOR 0x0008U
mbed_official 121:7f86b4238bec 108
mbed_official 121:7f86b4238bec 109 /**
mbed_official 121:7f86b4238bec 110 * @brief Macro to calculate address of an aliased word in the peripheral
mbed_official 121:7f86b4238bec 111 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
mbed_official 121:7f86b4238bec 112 * 0x400FFFFF).
mbed_official 121:7f86b4238bec 113 * @param Reg Register to access.
mbed_official 121:7f86b4238bec 114 * @param Bit Bit number to access.
mbed_official 121:7f86b4238bec 115 * @return Address of the aliased word in the peripheral bitband area.
mbed_official 121:7f86b4238bec 116 */
mbed_official 121:7f86b4238bec 117 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
mbed_official 121:7f86b4238bec 118 /**
mbed_official 121:7f86b4238bec 119 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 121:7f86b4238bec 120 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 121:7f86b4238bec 121 * be used for peripherals with 32bit access allowed.
mbed_official 121:7f86b4238bec 122 * @param Reg Register to access.
mbed_official 121:7f86b4238bec 123 * @param Bit Bit number to access.
mbed_official 121:7f86b4238bec 124 * @return Value of the targeted bit in the bit band region.
mbed_official 121:7f86b4238bec 125 */
mbed_official 121:7f86b4238bec 126 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
mbed_official 121:7f86b4238bec 127 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
mbed_official 121:7f86b4238bec 128 /**
mbed_official 121:7f86b4238bec 129 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 121:7f86b4238bec 130 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 121:7f86b4238bec 131 * be used for peripherals with 16bit access allowed.
mbed_official 121:7f86b4238bec 132 * @param Reg Register to access.
mbed_official 121:7f86b4238bec 133 * @param Bit Bit number to access.
mbed_official 121:7f86b4238bec 134 * @return Value of the targeted bit in the bit band region.
mbed_official 121:7f86b4238bec 135 */
mbed_official 121:7f86b4238bec 136 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
mbed_official 121:7f86b4238bec 137 /**
mbed_official 121:7f86b4238bec 138 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 121:7f86b4238bec 139 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 121:7f86b4238bec 140 * be used for peripherals with 8bit access allowed.
mbed_official 121:7f86b4238bec 141 * @param Reg Register to access.
mbed_official 121:7f86b4238bec 142 * @param Bit Bit number to access.
mbed_official 121:7f86b4238bec 143 * @return Value of the targeted bit in the bit band region.
mbed_official 121:7f86b4238bec 144 */
mbed_official 121:7f86b4238bec 145 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
mbed_official 121:7f86b4238bec 146
mbed_official 121:7f86b4238bec 147 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 148 -- Interrupt vector numbers
mbed_official 121:7f86b4238bec 149 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 150
mbed_official 121:7f86b4238bec 151 /*!
mbed_official 121:7f86b4238bec 152 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mbed_official 121:7f86b4238bec 153 * @{
mbed_official 121:7f86b4238bec 154 */
mbed_official 121:7f86b4238bec 155
mbed_official 121:7f86b4238bec 156 /** Interrupt Number Definitions */
mbed_official 121:7f86b4238bec 157 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
mbed_official 121:7f86b4238bec 158
mbed_official 121:7f86b4238bec 159 typedef enum IRQn {
mbed_official 121:7f86b4238bec 160 /* Auxiliary constants */
mbed_official 121:7f86b4238bec 161 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
mbed_official 121:7f86b4238bec 162
mbed_official 121:7f86b4238bec 163 /* Core interrupts */
mbed_official 121:7f86b4238bec 164 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mbed_official 121:7f86b4238bec 165 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
mbed_official 121:7f86b4238bec 166 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
mbed_official 121:7f86b4238bec 167 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
mbed_official 121:7f86b4238bec 168 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
mbed_official 121:7f86b4238bec 169 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
mbed_official 121:7f86b4238bec 170 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
mbed_official 121:7f86b4238bec 171 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
mbed_official 121:7f86b4238bec 172 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
mbed_official 121:7f86b4238bec 173
mbed_official 121:7f86b4238bec 174 /* Device specific interrupts */
mbed_official 121:7f86b4238bec 175 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
mbed_official 121:7f86b4238bec 176 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
mbed_official 121:7f86b4238bec 177 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
mbed_official 121:7f86b4238bec 178 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
mbed_official 121:7f86b4238bec 179 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
mbed_official 121:7f86b4238bec 180 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
mbed_official 121:7f86b4238bec 181 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
mbed_official 121:7f86b4238bec 182 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
mbed_official 121:7f86b4238bec 183 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
mbed_official 121:7f86b4238bec 184 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
mbed_official 121:7f86b4238bec 185 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
mbed_official 121:7f86b4238bec 186 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
mbed_official 121:7f86b4238bec 187 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
mbed_official 121:7f86b4238bec 188 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
mbed_official 121:7f86b4238bec 189 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
mbed_official 121:7f86b4238bec 190 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
mbed_official 121:7f86b4238bec 191 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
mbed_official 121:7f86b4238bec 192 MCM_IRQn = 17, /**< Normal Interrupt */
mbed_official 121:7f86b4238bec 193 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
mbed_official 121:7f86b4238bec 194 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
mbed_official 121:7f86b4238bec 195 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
mbed_official 121:7f86b4238bec 196 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
mbed_official 121:7f86b4238bec 197 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
mbed_official 121:7f86b4238bec 198 RNG_IRQn = 23, /**< RNG Interrupt */
mbed_official 121:7f86b4238bec 199 I2C0_IRQn = 24, /**< I2C0 interrupt */
mbed_official 121:7f86b4238bec 200 I2C1_IRQn = 25, /**< I2C1 interrupt */
mbed_official 121:7f86b4238bec 201 SPI0_IRQn = 26, /**< SPI0 Interrupt */
mbed_official 121:7f86b4238bec 202 SPI1_IRQn = 27, /**< SPI1 Interrupt */
mbed_official 121:7f86b4238bec 203 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
mbed_official 121:7f86b4238bec 204 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
mbed_official 121:7f86b4238bec 205 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
mbed_official 121:7f86b4238bec 206 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
mbed_official 121:7f86b4238bec 207 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
mbed_official 121:7f86b4238bec 208 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
mbed_official 121:7f86b4238bec 209 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
mbed_official 121:7f86b4238bec 210 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
mbed_official 121:7f86b4238bec 211 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
mbed_official 121:7f86b4238bec 212 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
mbed_official 121:7f86b4238bec 213 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
mbed_official 121:7f86b4238bec 214 ADC0_IRQn = 39, /**< ADC0 interrupt */
mbed_official 121:7f86b4238bec 215 CMP0_IRQn = 40, /**< CMP0 interrupt */
mbed_official 121:7f86b4238bec 216 CMP1_IRQn = 41, /**< CMP1 interrupt */
mbed_official 121:7f86b4238bec 217 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
mbed_official 121:7f86b4238bec 218 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
mbed_official 121:7f86b4238bec 219 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
mbed_official 121:7f86b4238bec 220 CMT_IRQn = 45, /**< CMT interrupt */
mbed_official 121:7f86b4238bec 221 RTC_IRQn = 46, /**< RTC interrupt */
mbed_official 121:7f86b4238bec 222 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
mbed_official 121:7f86b4238bec 223 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
mbed_official 121:7f86b4238bec 224 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
mbed_official 121:7f86b4238bec 225 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
mbed_official 121:7f86b4238bec 226 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
mbed_official 121:7f86b4238bec 227 PDB0_IRQn = 52, /**< PDB0 Interrupt */
mbed_official 121:7f86b4238bec 228 USB0_IRQn = 53, /**< USB0 interrupt */
mbed_official 121:7f86b4238bec 229 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
mbed_official 121:7f86b4238bec 230 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
mbed_official 121:7f86b4238bec 231 DAC0_IRQn = 56, /**< DAC0 interrupt */
mbed_official 121:7f86b4238bec 232 MCG_IRQn = 57, /**< MCG Interrupt */
mbed_official 121:7f86b4238bec 233 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
mbed_official 121:7f86b4238bec 234 PORTA_IRQn = 59, /**< Port A interrupt */
mbed_official 121:7f86b4238bec 235 PORTB_IRQn = 60, /**< Port B interrupt */
mbed_official 121:7f86b4238bec 236 PORTC_IRQn = 61, /**< Port C interrupt */
mbed_official 121:7f86b4238bec 237 PORTD_IRQn = 62, /**< Port D interrupt */
mbed_official 121:7f86b4238bec 238 PORTE_IRQn = 63, /**< Port E interrupt */
mbed_official 121:7f86b4238bec 239 SWI_IRQn = 64, /**< Software interrupt */
mbed_official 121:7f86b4238bec 240 SPI2_IRQn = 65, /**< SPI2 Interrupt */
mbed_official 121:7f86b4238bec 241 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
mbed_official 121:7f86b4238bec 242 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
mbed_official 121:7f86b4238bec 243 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
mbed_official 121:7f86b4238bec 244 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
mbed_official 121:7f86b4238bec 245 CMP2_IRQn = 70, /**< CMP2 interrupt */
mbed_official 121:7f86b4238bec 246 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
mbed_official 121:7f86b4238bec 247 DAC1_IRQn = 72, /**< DAC1 interrupt */
mbed_official 121:7f86b4238bec 248 ADC1_IRQn = 73, /**< ADC1 interrupt */
mbed_official 121:7f86b4238bec 249 I2C2_IRQn = 74, /**< I2C2 interrupt */
mbed_official 121:7f86b4238bec 250 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
mbed_official 121:7f86b4238bec 251 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
mbed_official 121:7f86b4238bec 252 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
mbed_official 121:7f86b4238bec 253 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
mbed_official 121:7f86b4238bec 254 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
mbed_official 121:7f86b4238bec 255 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
mbed_official 121:7f86b4238bec 256 SDHC_IRQn = 81, /**< SDHC interrupt */
mbed_official 121:7f86b4238bec 257 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
mbed_official 121:7f86b4238bec 258 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
mbed_official 121:7f86b4238bec 259 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
mbed_official 121:7f86b4238bec 260 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
mbed_official 121:7f86b4238bec 261 } IRQn_Type;
mbed_official 121:7f86b4238bec 262
mbed_official 121:7f86b4238bec 263 /*!
mbed_official 121:7f86b4238bec 264 * @}
mbed_official 121:7f86b4238bec 265 */ /* end of group Interrupt_vector_numbers */
mbed_official 121:7f86b4238bec 266
mbed_official 121:7f86b4238bec 267
mbed_official 121:7f86b4238bec 268 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 269 -- Cortex M4 Core Configuration
mbed_official 121:7f86b4238bec 270 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 271
mbed_official 121:7f86b4238bec 272 /*!
mbed_official 121:7f86b4238bec 273 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
mbed_official 121:7f86b4238bec 274 * @{
mbed_official 121:7f86b4238bec 275 */
mbed_official 121:7f86b4238bec 276
mbed_official 121:7f86b4238bec 277 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mbed_official 121:7f86b4238bec 278 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
mbed_official 121:7f86b4238bec 279 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mbed_official 121:7f86b4238bec 280 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
mbed_official 121:7f86b4238bec 281
mbed_official 121:7f86b4238bec 282 #include "core_cm4.h" /* Core Peripheral Access Layer */
mbed_official 121:7f86b4238bec 283 #include "system_MK64F12.h" /* Device specific configuration file */
mbed_official 121:7f86b4238bec 284
mbed_official 121:7f86b4238bec 285 /*!
mbed_official 121:7f86b4238bec 286 * @}
mbed_official 121:7f86b4238bec 287 */ /* end of group Cortex_Core_Configuration */
mbed_official 121:7f86b4238bec 288
mbed_official 121:7f86b4238bec 289
mbed_official 121:7f86b4238bec 290 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 291 -- Mapping Information
mbed_official 121:7f86b4238bec 292 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 293
mbed_official 121:7f86b4238bec 294 /*!
mbed_official 121:7f86b4238bec 295 * @addtogroup Mapping_Information Mapping Information
mbed_official 121:7f86b4238bec 296 * @{
mbed_official 121:7f86b4238bec 297 */
mbed_official 121:7f86b4238bec 298
mbed_official 121:7f86b4238bec 299 /** Mapping Information */
mbed_official 121:7f86b4238bec 300 /*!
mbed_official 121:7f86b4238bec 301 * @addtogroup edma_request
mbed_official 121:7f86b4238bec 302 * @{
mbed_official 121:7f86b4238bec 303 */
mbed_official 121:7f86b4238bec 304
mbed_official 121:7f86b4238bec 305 /*******************************************************************************
mbed_official 121:7f86b4238bec 306 * Definitions
mbed_official 121:7f86b4238bec 307 ******************************************************************************/
mbed_official 121:7f86b4238bec 308
mbed_official 121:7f86b4238bec 309 /*!
mbed_official 121:7f86b4238bec 310 * @brief Structure for the DMA hardware request
mbed_official 121:7f86b4238bec 311 *
mbed_official 121:7f86b4238bec 312 * Defines the structure for the DMA hardware request collections. The user can configure the
mbed_official 121:7f86b4238bec 313 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
mbed_official 121:7f86b4238bec 314 * of the hardware request varies according to the to SoC.
mbed_official 121:7f86b4238bec 315 */
mbed_official 121:7f86b4238bec 316 typedef enum _dma_request_source
mbed_official 121:7f86b4238bec 317 {
mbed_official 121:7f86b4238bec 318 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
mbed_official 121:7f86b4238bec 319 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
mbed_official 121:7f86b4238bec 320 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
mbed_official 121:7f86b4238bec 321 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
mbed_official 121:7f86b4238bec 322 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
mbed_official 121:7f86b4238bec 323 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
mbed_official 121:7f86b4238bec 324 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
mbed_official 121:7f86b4238bec 325 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
mbed_official 121:7f86b4238bec 326 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
mbed_official 121:7f86b4238bec 327 kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
mbed_official 121:7f86b4238bec 328 kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
mbed_official 121:7f86b4238bec 329 kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */
mbed_official 121:7f86b4238bec 330 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
mbed_official 121:7f86b4238bec 331 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
mbed_official 121:7f86b4238bec 332 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
mbed_official 121:7f86b4238bec 333 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
mbed_official 121:7f86b4238bec 334 kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
mbed_official 121:7f86b4238bec 335 kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */
mbed_official 121:7f86b4238bec 336 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
mbed_official 121:7f86b4238bec 337 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
mbed_official 121:7f86b4238bec 338 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
mbed_official 121:7f86b4238bec 339 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
mbed_official 121:7f86b4238bec 340 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
mbed_official 121:7f86b4238bec 341 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
mbed_official 121:7f86b4238bec 342 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
mbed_official 121:7f86b4238bec 343 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
mbed_official 121:7f86b4238bec 344 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
mbed_official 121:7f86b4238bec 345 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
mbed_official 121:7f86b4238bec 346 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
mbed_official 121:7f86b4238bec 347 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
mbed_official 121:7f86b4238bec 348 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
mbed_official 121:7f86b4238bec 349 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
mbed_official 121:7f86b4238bec 350 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
mbed_official 121:7f86b4238bec 351 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
mbed_official 121:7f86b4238bec 352 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
mbed_official 121:7f86b4238bec 353 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
mbed_official 121:7f86b4238bec 354 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
mbed_official 121:7f86b4238bec 355 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
mbed_official 121:7f86b4238bec 356 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
mbed_official 121:7f86b4238bec 357 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
mbed_official 121:7f86b4238bec 358 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
mbed_official 121:7f86b4238bec 359 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
mbed_official 121:7f86b4238bec 360 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
mbed_official 121:7f86b4238bec 361 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
mbed_official 121:7f86b4238bec 362 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
mbed_official 121:7f86b4238bec 363 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
mbed_official 121:7f86b4238bec 364 kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */
mbed_official 121:7f86b4238bec 365 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
mbed_official 121:7f86b4238bec 366 kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
mbed_official 121:7f86b4238bec 367 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
mbed_official 121:7f86b4238bec 368 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
mbed_official 121:7f86b4238bec 369 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
mbed_official 121:7f86b4238bec 370 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
mbed_official 121:7f86b4238bec 371 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
mbed_official 121:7f86b4238bec 372 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
mbed_official 121:7f86b4238bec 373 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
mbed_official 121:7f86b4238bec 374 kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */
mbed_official 121:7f86b4238bec 375 kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1. */
mbed_official 121:7f86b4238bec 376 kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2. */
mbed_official 121:7f86b4238bec 377 kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */
mbed_official 121:7f86b4238bec 378 kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */
mbed_official 121:7f86b4238bec 379 kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */
mbed_official 121:7f86b4238bec 380 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
mbed_official 121:7f86b4238bec 381 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
mbed_official 121:7f86b4238bec 382 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
mbed_official 121:7f86b4238bec 383 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
mbed_official 121:7f86b4238bec 384 } dma_request_source_t;
mbed_official 121:7f86b4238bec 385
mbed_official 121:7f86b4238bec 386 /* @} */
mbed_official 121:7f86b4238bec 387
mbed_official 121:7f86b4238bec 388
mbed_official 121:7f86b4238bec 389 /*!
mbed_official 121:7f86b4238bec 390 * @}
mbed_official 121:7f86b4238bec 391 */ /* end of group Mapping_Information */
mbed_official 121:7f86b4238bec 392
mbed_official 121:7f86b4238bec 393
mbed_official 121:7f86b4238bec 394 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 395 -- Device Peripheral Access Layer
mbed_official 121:7f86b4238bec 396 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 397
mbed_official 121:7f86b4238bec 398 /*!
mbed_official 121:7f86b4238bec 399 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mbed_official 121:7f86b4238bec 400 * @{
mbed_official 121:7f86b4238bec 401 */
mbed_official 121:7f86b4238bec 402
mbed_official 121:7f86b4238bec 403
mbed_official 121:7f86b4238bec 404 /*
mbed_official 121:7f86b4238bec 405 ** Start of section using anonymous unions
mbed_official 121:7f86b4238bec 406 */
mbed_official 121:7f86b4238bec 407
mbed_official 121:7f86b4238bec 408 #if defined(__ARMCC_VERSION)
mbed_official 121:7f86b4238bec 409 #pragma push
mbed_official 121:7f86b4238bec 410 #pragma anon_unions
mbed_official 121:7f86b4238bec 411 #elif defined(__CWCC__)
mbed_official 121:7f86b4238bec 412 #pragma push
mbed_official 121:7f86b4238bec 413 #pragma cpp_extensions on
mbed_official 121:7f86b4238bec 414 #elif defined(__GNUC__)
mbed_official 121:7f86b4238bec 415 /* anonymous unions are enabled by default */
mbed_official 121:7f86b4238bec 416 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 121:7f86b4238bec 417 #pragma language=extended
mbed_official 121:7f86b4238bec 418 #else
mbed_official 121:7f86b4238bec 419 #error Not supported compiler type
mbed_official 121:7f86b4238bec 420 #endif
mbed_official 121:7f86b4238bec 421
mbed_official 121:7f86b4238bec 422 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 423 -- ADC Peripheral Access Layer
mbed_official 121:7f86b4238bec 424 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 425
mbed_official 121:7f86b4238bec 426 /*!
mbed_official 121:7f86b4238bec 427 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mbed_official 121:7f86b4238bec 428 * @{
mbed_official 121:7f86b4238bec 429 */
mbed_official 121:7f86b4238bec 430
mbed_official 121:7f86b4238bec 431 /** ADC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 432 typedef struct {
mbed_official 121:7f86b4238bec 433 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
mbed_official 121:7f86b4238bec 434 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
mbed_official 121:7f86b4238bec 435 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
mbed_official 121:7f86b4238bec 436 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
mbed_official 121:7f86b4238bec 437 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
mbed_official 121:7f86b4238bec 438 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
mbed_official 121:7f86b4238bec 439 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
mbed_official 121:7f86b4238bec 440 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
mbed_official 121:7f86b4238bec 441 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
mbed_official 121:7f86b4238bec 442 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
mbed_official 121:7f86b4238bec 443 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
mbed_official 121:7f86b4238bec 444 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
mbed_official 121:7f86b4238bec 445 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
mbed_official 121:7f86b4238bec 446 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
mbed_official 121:7f86b4238bec 447 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
mbed_official 121:7f86b4238bec 448 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
mbed_official 121:7f86b4238bec 449 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
mbed_official 121:7f86b4238bec 450 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
mbed_official 121:7f86b4238bec 451 uint8_t RESERVED_0[4];
mbed_official 121:7f86b4238bec 452 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
mbed_official 121:7f86b4238bec 453 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
mbed_official 121:7f86b4238bec 454 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
mbed_official 121:7f86b4238bec 455 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
mbed_official 121:7f86b4238bec 456 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
mbed_official 121:7f86b4238bec 457 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
mbed_official 121:7f86b4238bec 458 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
mbed_official 121:7f86b4238bec 459 } ADC_Type;
mbed_official 121:7f86b4238bec 460
mbed_official 121:7f86b4238bec 461 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 462 -- ADC Register Masks
mbed_official 121:7f86b4238bec 463 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 464
mbed_official 121:7f86b4238bec 465 /*!
mbed_official 121:7f86b4238bec 466 * @addtogroup ADC_Register_Masks ADC Register Masks
mbed_official 121:7f86b4238bec 467 * @{
mbed_official 121:7f86b4238bec 468 */
mbed_official 121:7f86b4238bec 469
mbed_official 121:7f86b4238bec 470 /*! @name SC1 - ADC Status and Control Registers 1 */
mbed_official 121:7f86b4238bec 471 #define ADC_SC1_ADCH_MASK (0x1FU)
mbed_official 121:7f86b4238bec 472 #define ADC_SC1_ADCH_SHIFT (0U)
mbed_official 121:7f86b4238bec 473 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
mbed_official 121:7f86b4238bec 474 #define ADC_SC1_DIFF_MASK (0x20U)
mbed_official 121:7f86b4238bec 475 #define ADC_SC1_DIFF_SHIFT (5U)
mbed_official 121:7f86b4238bec 476 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
mbed_official 121:7f86b4238bec 477 #define ADC_SC1_AIEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 478 #define ADC_SC1_AIEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 479 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
mbed_official 121:7f86b4238bec 480 #define ADC_SC1_COCO_MASK (0x80U)
mbed_official 121:7f86b4238bec 481 #define ADC_SC1_COCO_SHIFT (7U)
mbed_official 121:7f86b4238bec 482 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
mbed_official 121:7f86b4238bec 483
mbed_official 121:7f86b4238bec 484 /* The count of ADC_SC1 */
mbed_official 121:7f86b4238bec 485 #define ADC_SC1_COUNT (2U)
mbed_official 121:7f86b4238bec 486
mbed_official 121:7f86b4238bec 487 /*! @name CFG1 - ADC Configuration Register 1 */
mbed_official 121:7f86b4238bec 488 #define ADC_CFG1_ADICLK_MASK (0x3U)
mbed_official 121:7f86b4238bec 489 #define ADC_CFG1_ADICLK_SHIFT (0U)
mbed_official 121:7f86b4238bec 490 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
mbed_official 121:7f86b4238bec 491 #define ADC_CFG1_MODE_MASK (0xCU)
mbed_official 121:7f86b4238bec 492 #define ADC_CFG1_MODE_SHIFT (2U)
mbed_official 121:7f86b4238bec 493 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
mbed_official 121:7f86b4238bec 494 #define ADC_CFG1_ADLSMP_MASK (0x10U)
mbed_official 121:7f86b4238bec 495 #define ADC_CFG1_ADLSMP_SHIFT (4U)
mbed_official 121:7f86b4238bec 496 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
mbed_official 121:7f86b4238bec 497 #define ADC_CFG1_ADIV_MASK (0x60U)
mbed_official 121:7f86b4238bec 498 #define ADC_CFG1_ADIV_SHIFT (5U)
mbed_official 121:7f86b4238bec 499 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
mbed_official 121:7f86b4238bec 500 #define ADC_CFG1_ADLPC_MASK (0x80U)
mbed_official 121:7f86b4238bec 501 #define ADC_CFG1_ADLPC_SHIFT (7U)
mbed_official 121:7f86b4238bec 502 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
mbed_official 121:7f86b4238bec 503
mbed_official 121:7f86b4238bec 504 /*! @name CFG2 - ADC Configuration Register 2 */
mbed_official 121:7f86b4238bec 505 #define ADC_CFG2_ADLSTS_MASK (0x3U)
mbed_official 121:7f86b4238bec 506 #define ADC_CFG2_ADLSTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 507 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
mbed_official 121:7f86b4238bec 508 #define ADC_CFG2_ADHSC_MASK (0x4U)
mbed_official 121:7f86b4238bec 509 #define ADC_CFG2_ADHSC_SHIFT (2U)
mbed_official 121:7f86b4238bec 510 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
mbed_official 121:7f86b4238bec 511 #define ADC_CFG2_ADACKEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 512 #define ADC_CFG2_ADACKEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 513 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
mbed_official 121:7f86b4238bec 514 #define ADC_CFG2_MUXSEL_MASK (0x10U)
mbed_official 121:7f86b4238bec 515 #define ADC_CFG2_MUXSEL_SHIFT (4U)
mbed_official 121:7f86b4238bec 516 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
mbed_official 121:7f86b4238bec 517
mbed_official 121:7f86b4238bec 518 /*! @name R - ADC Data Result Register */
mbed_official 121:7f86b4238bec 519 #define ADC_R_D_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 520 #define ADC_R_D_SHIFT (0U)
mbed_official 121:7f86b4238bec 521 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
mbed_official 121:7f86b4238bec 522
mbed_official 121:7f86b4238bec 523 /* The count of ADC_R */
mbed_official 121:7f86b4238bec 524 #define ADC_R_COUNT (2U)
mbed_official 121:7f86b4238bec 525
mbed_official 121:7f86b4238bec 526 /*! @name CV1 - Compare Value Registers */
mbed_official 121:7f86b4238bec 527 #define ADC_CV1_CV_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 528 #define ADC_CV1_CV_SHIFT (0U)
mbed_official 121:7f86b4238bec 529 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
mbed_official 121:7f86b4238bec 530
mbed_official 121:7f86b4238bec 531 /*! @name CV2 - Compare Value Registers */
mbed_official 121:7f86b4238bec 532 #define ADC_CV2_CV_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 533 #define ADC_CV2_CV_SHIFT (0U)
mbed_official 121:7f86b4238bec 534 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
mbed_official 121:7f86b4238bec 535
mbed_official 121:7f86b4238bec 536 /*! @name SC2 - Status and Control Register 2 */
mbed_official 121:7f86b4238bec 537 #define ADC_SC2_REFSEL_MASK (0x3U)
mbed_official 121:7f86b4238bec 538 #define ADC_SC2_REFSEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 539 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
mbed_official 121:7f86b4238bec 540 #define ADC_SC2_DMAEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 541 #define ADC_SC2_DMAEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 542 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
mbed_official 121:7f86b4238bec 543 #define ADC_SC2_ACREN_MASK (0x8U)
mbed_official 121:7f86b4238bec 544 #define ADC_SC2_ACREN_SHIFT (3U)
mbed_official 121:7f86b4238bec 545 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
mbed_official 121:7f86b4238bec 546 #define ADC_SC2_ACFGT_MASK (0x10U)
mbed_official 121:7f86b4238bec 547 #define ADC_SC2_ACFGT_SHIFT (4U)
mbed_official 121:7f86b4238bec 548 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
mbed_official 121:7f86b4238bec 549 #define ADC_SC2_ACFE_MASK (0x20U)
mbed_official 121:7f86b4238bec 550 #define ADC_SC2_ACFE_SHIFT (5U)
mbed_official 121:7f86b4238bec 551 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
mbed_official 121:7f86b4238bec 552 #define ADC_SC2_ADTRG_MASK (0x40U)
mbed_official 121:7f86b4238bec 553 #define ADC_SC2_ADTRG_SHIFT (6U)
mbed_official 121:7f86b4238bec 554 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
mbed_official 121:7f86b4238bec 555 #define ADC_SC2_ADACT_MASK (0x80U)
mbed_official 121:7f86b4238bec 556 #define ADC_SC2_ADACT_SHIFT (7U)
mbed_official 121:7f86b4238bec 557 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
mbed_official 121:7f86b4238bec 558
mbed_official 121:7f86b4238bec 559 /*! @name SC3 - Status and Control Register 3 */
mbed_official 121:7f86b4238bec 560 #define ADC_SC3_AVGS_MASK (0x3U)
mbed_official 121:7f86b4238bec 561 #define ADC_SC3_AVGS_SHIFT (0U)
mbed_official 121:7f86b4238bec 562 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
mbed_official 121:7f86b4238bec 563 #define ADC_SC3_AVGE_MASK (0x4U)
mbed_official 121:7f86b4238bec 564 #define ADC_SC3_AVGE_SHIFT (2U)
mbed_official 121:7f86b4238bec 565 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
mbed_official 121:7f86b4238bec 566 #define ADC_SC3_ADCO_MASK (0x8U)
mbed_official 121:7f86b4238bec 567 #define ADC_SC3_ADCO_SHIFT (3U)
mbed_official 121:7f86b4238bec 568 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
mbed_official 121:7f86b4238bec 569 #define ADC_SC3_CALF_MASK (0x40U)
mbed_official 121:7f86b4238bec 570 #define ADC_SC3_CALF_SHIFT (6U)
mbed_official 121:7f86b4238bec 571 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
mbed_official 121:7f86b4238bec 572 #define ADC_SC3_CAL_MASK (0x80U)
mbed_official 121:7f86b4238bec 573 #define ADC_SC3_CAL_SHIFT (7U)
mbed_official 121:7f86b4238bec 574 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
mbed_official 121:7f86b4238bec 575
mbed_official 121:7f86b4238bec 576 /*! @name OFS - ADC Offset Correction Register */
mbed_official 121:7f86b4238bec 577 #define ADC_OFS_OFS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 578 #define ADC_OFS_OFS_SHIFT (0U)
mbed_official 121:7f86b4238bec 579 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
mbed_official 121:7f86b4238bec 580
mbed_official 121:7f86b4238bec 581 /*! @name PG - ADC Plus-Side Gain Register */
mbed_official 121:7f86b4238bec 582 #define ADC_PG_PG_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 583 #define ADC_PG_PG_SHIFT (0U)
mbed_official 121:7f86b4238bec 584 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
mbed_official 121:7f86b4238bec 585
mbed_official 121:7f86b4238bec 586 /*! @name MG - ADC Minus-Side Gain Register */
mbed_official 121:7f86b4238bec 587 #define ADC_MG_MG_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 588 #define ADC_MG_MG_SHIFT (0U)
mbed_official 121:7f86b4238bec 589 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
mbed_official 121:7f86b4238bec 590
mbed_official 121:7f86b4238bec 591 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 592 #define ADC_CLPD_CLPD_MASK (0x3FU)
mbed_official 121:7f86b4238bec 593 #define ADC_CLPD_CLPD_SHIFT (0U)
mbed_official 121:7f86b4238bec 594 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
mbed_official 121:7f86b4238bec 595
mbed_official 121:7f86b4238bec 596 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 597 #define ADC_CLPS_CLPS_MASK (0x3FU)
mbed_official 121:7f86b4238bec 598 #define ADC_CLPS_CLPS_SHIFT (0U)
mbed_official 121:7f86b4238bec 599 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
mbed_official 121:7f86b4238bec 600
mbed_official 121:7f86b4238bec 601 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 602 #define ADC_CLP4_CLP4_MASK (0x3FFU)
mbed_official 121:7f86b4238bec 603 #define ADC_CLP4_CLP4_SHIFT (0U)
mbed_official 121:7f86b4238bec 604 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
mbed_official 121:7f86b4238bec 605
mbed_official 121:7f86b4238bec 606 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 607 #define ADC_CLP3_CLP3_MASK (0x1FFU)
mbed_official 121:7f86b4238bec 608 #define ADC_CLP3_CLP3_SHIFT (0U)
mbed_official 121:7f86b4238bec 609 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
mbed_official 121:7f86b4238bec 610
mbed_official 121:7f86b4238bec 611 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 612 #define ADC_CLP2_CLP2_MASK (0xFFU)
mbed_official 121:7f86b4238bec 613 #define ADC_CLP2_CLP2_SHIFT (0U)
mbed_official 121:7f86b4238bec 614 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
mbed_official 121:7f86b4238bec 615
mbed_official 121:7f86b4238bec 616 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 617 #define ADC_CLP1_CLP1_MASK (0x7FU)
mbed_official 121:7f86b4238bec 618 #define ADC_CLP1_CLP1_SHIFT (0U)
mbed_official 121:7f86b4238bec 619 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
mbed_official 121:7f86b4238bec 620
mbed_official 121:7f86b4238bec 621 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 622 #define ADC_CLP0_CLP0_MASK (0x3FU)
mbed_official 121:7f86b4238bec 623 #define ADC_CLP0_CLP0_SHIFT (0U)
mbed_official 121:7f86b4238bec 624 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
mbed_official 121:7f86b4238bec 625
mbed_official 121:7f86b4238bec 626 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 627 #define ADC_CLMD_CLMD_MASK (0x3FU)
mbed_official 121:7f86b4238bec 628 #define ADC_CLMD_CLMD_SHIFT (0U)
mbed_official 121:7f86b4238bec 629 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
mbed_official 121:7f86b4238bec 630
mbed_official 121:7f86b4238bec 631 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 632 #define ADC_CLMS_CLMS_MASK (0x3FU)
mbed_official 121:7f86b4238bec 633 #define ADC_CLMS_CLMS_SHIFT (0U)
mbed_official 121:7f86b4238bec 634 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
mbed_official 121:7f86b4238bec 635
mbed_official 121:7f86b4238bec 636 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 637 #define ADC_CLM4_CLM4_MASK (0x3FFU)
mbed_official 121:7f86b4238bec 638 #define ADC_CLM4_CLM4_SHIFT (0U)
mbed_official 121:7f86b4238bec 639 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
mbed_official 121:7f86b4238bec 640
mbed_official 121:7f86b4238bec 641 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 642 #define ADC_CLM3_CLM3_MASK (0x1FFU)
mbed_official 121:7f86b4238bec 643 #define ADC_CLM3_CLM3_SHIFT (0U)
mbed_official 121:7f86b4238bec 644 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
mbed_official 121:7f86b4238bec 645
mbed_official 121:7f86b4238bec 646 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 647 #define ADC_CLM2_CLM2_MASK (0xFFU)
mbed_official 121:7f86b4238bec 648 #define ADC_CLM2_CLM2_SHIFT (0U)
mbed_official 121:7f86b4238bec 649 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
mbed_official 121:7f86b4238bec 650
mbed_official 121:7f86b4238bec 651 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 652 #define ADC_CLM1_CLM1_MASK (0x7FU)
mbed_official 121:7f86b4238bec 653 #define ADC_CLM1_CLM1_SHIFT (0U)
mbed_official 121:7f86b4238bec 654 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
mbed_official 121:7f86b4238bec 655
mbed_official 121:7f86b4238bec 656 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
mbed_official 121:7f86b4238bec 657 #define ADC_CLM0_CLM0_MASK (0x3FU)
mbed_official 121:7f86b4238bec 658 #define ADC_CLM0_CLM0_SHIFT (0U)
mbed_official 121:7f86b4238bec 659 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
mbed_official 121:7f86b4238bec 660
mbed_official 121:7f86b4238bec 661
mbed_official 121:7f86b4238bec 662 /*!
mbed_official 121:7f86b4238bec 663 * @}
mbed_official 121:7f86b4238bec 664 */ /* end of group ADC_Register_Masks */
mbed_official 121:7f86b4238bec 665
mbed_official 121:7f86b4238bec 666
mbed_official 121:7f86b4238bec 667 /* ADC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 668 /** Peripheral ADC0 base address */
mbed_official 121:7f86b4238bec 669 #define ADC0_BASE (0x4003B000u)
mbed_official 121:7f86b4238bec 670 /** Peripheral ADC0 base pointer */
mbed_official 121:7f86b4238bec 671 #define ADC0 ((ADC_Type *)ADC0_BASE)
mbed_official 121:7f86b4238bec 672 /** Peripheral ADC1 base address */
mbed_official 121:7f86b4238bec 673 #define ADC1_BASE (0x400BB000u)
mbed_official 121:7f86b4238bec 674 /** Peripheral ADC1 base pointer */
mbed_official 121:7f86b4238bec 675 #define ADC1 ((ADC_Type *)ADC1_BASE)
mbed_official 121:7f86b4238bec 676 /** Array initializer of ADC peripheral base addresses */
mbed_official 121:7f86b4238bec 677 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
mbed_official 121:7f86b4238bec 678 /** Array initializer of ADC peripheral base pointers */
mbed_official 121:7f86b4238bec 679 #define ADC_BASE_PTRS { ADC0, ADC1 }
mbed_official 121:7f86b4238bec 680 /** Interrupt vectors for the ADC peripheral type */
mbed_official 121:7f86b4238bec 681 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
mbed_official 121:7f86b4238bec 682
mbed_official 121:7f86b4238bec 683 /*!
mbed_official 121:7f86b4238bec 684 * @}
mbed_official 121:7f86b4238bec 685 */ /* end of group ADC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 686
mbed_official 121:7f86b4238bec 687
mbed_official 121:7f86b4238bec 688 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 689 -- AIPS Peripheral Access Layer
mbed_official 121:7f86b4238bec 690 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 691
mbed_official 121:7f86b4238bec 692 /*!
mbed_official 121:7f86b4238bec 693 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
mbed_official 121:7f86b4238bec 694 * @{
mbed_official 121:7f86b4238bec 695 */
mbed_official 121:7f86b4238bec 696
mbed_official 121:7f86b4238bec 697 /** AIPS - Register Layout Typedef */
mbed_official 121:7f86b4238bec 698 typedef struct {
mbed_official 121:7f86b4238bec 699 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
mbed_official 121:7f86b4238bec 700 uint8_t RESERVED_0[28];
mbed_official 121:7f86b4238bec 701 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
mbed_official 121:7f86b4238bec 702 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
mbed_official 121:7f86b4238bec 703 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
mbed_official 121:7f86b4238bec 704 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
mbed_official 121:7f86b4238bec 705 uint8_t RESERVED_1[16];
mbed_official 121:7f86b4238bec 706 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
mbed_official 121:7f86b4238bec 707 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
mbed_official 121:7f86b4238bec 708 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
mbed_official 121:7f86b4238bec 709 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
mbed_official 121:7f86b4238bec 710 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
mbed_official 121:7f86b4238bec 711 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
mbed_official 121:7f86b4238bec 712 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
mbed_official 121:7f86b4238bec 713 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
mbed_official 121:7f86b4238bec 714 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
mbed_official 121:7f86b4238bec 715 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
mbed_official 121:7f86b4238bec 716 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
mbed_official 121:7f86b4238bec 717 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
mbed_official 121:7f86b4238bec 718 uint8_t RESERVED_2[16];
mbed_official 121:7f86b4238bec 719 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
mbed_official 121:7f86b4238bec 720 } AIPS_Type;
mbed_official 121:7f86b4238bec 721
mbed_official 121:7f86b4238bec 722 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 723 -- AIPS Register Masks
mbed_official 121:7f86b4238bec 724 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 725
mbed_official 121:7f86b4238bec 726 /*!
mbed_official 121:7f86b4238bec 727 * @addtogroup AIPS_Register_Masks AIPS Register Masks
mbed_official 121:7f86b4238bec 728 * @{
mbed_official 121:7f86b4238bec 729 */
mbed_official 121:7f86b4238bec 730
mbed_official 121:7f86b4238bec 731 /*! @name MPRA - Master Privilege Register A */
mbed_official 121:7f86b4238bec 732 #define AIPS_MPRA_MPL5_MASK (0x100U)
mbed_official 121:7f86b4238bec 733 #define AIPS_MPRA_MPL5_SHIFT (8U)
mbed_official 121:7f86b4238bec 734 #define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
mbed_official 121:7f86b4238bec 735 #define AIPS_MPRA_MTW5_MASK (0x200U)
mbed_official 121:7f86b4238bec 736 #define AIPS_MPRA_MTW5_SHIFT (9U)
mbed_official 121:7f86b4238bec 737 #define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
mbed_official 121:7f86b4238bec 738 #define AIPS_MPRA_MTR5_MASK (0x400U)
mbed_official 121:7f86b4238bec 739 #define AIPS_MPRA_MTR5_SHIFT (10U)
mbed_official 121:7f86b4238bec 740 #define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
mbed_official 121:7f86b4238bec 741 #define AIPS_MPRA_MPL4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 742 #define AIPS_MPRA_MPL4_SHIFT (12U)
mbed_official 121:7f86b4238bec 743 #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
mbed_official 121:7f86b4238bec 744 #define AIPS_MPRA_MTW4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 745 #define AIPS_MPRA_MTW4_SHIFT (13U)
mbed_official 121:7f86b4238bec 746 #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
mbed_official 121:7f86b4238bec 747 #define AIPS_MPRA_MTR4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 748 #define AIPS_MPRA_MTR4_SHIFT (14U)
mbed_official 121:7f86b4238bec 749 #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
mbed_official 121:7f86b4238bec 750 #define AIPS_MPRA_MPL3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 751 #define AIPS_MPRA_MPL3_SHIFT (16U)
mbed_official 121:7f86b4238bec 752 #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
mbed_official 121:7f86b4238bec 753 #define AIPS_MPRA_MTW3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 754 #define AIPS_MPRA_MTW3_SHIFT (17U)
mbed_official 121:7f86b4238bec 755 #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
mbed_official 121:7f86b4238bec 756 #define AIPS_MPRA_MTR3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 757 #define AIPS_MPRA_MTR3_SHIFT (18U)
mbed_official 121:7f86b4238bec 758 #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
mbed_official 121:7f86b4238bec 759 #define AIPS_MPRA_MPL2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 760 #define AIPS_MPRA_MPL2_SHIFT (20U)
mbed_official 121:7f86b4238bec 761 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
mbed_official 121:7f86b4238bec 762 #define AIPS_MPRA_MTW2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 763 #define AIPS_MPRA_MTW2_SHIFT (21U)
mbed_official 121:7f86b4238bec 764 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
mbed_official 121:7f86b4238bec 765 #define AIPS_MPRA_MTR2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 766 #define AIPS_MPRA_MTR2_SHIFT (22U)
mbed_official 121:7f86b4238bec 767 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
mbed_official 121:7f86b4238bec 768 #define AIPS_MPRA_MPL1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 769 #define AIPS_MPRA_MPL1_SHIFT (24U)
mbed_official 121:7f86b4238bec 770 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
mbed_official 121:7f86b4238bec 771 #define AIPS_MPRA_MTW1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 772 #define AIPS_MPRA_MTW1_SHIFT (25U)
mbed_official 121:7f86b4238bec 773 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
mbed_official 121:7f86b4238bec 774 #define AIPS_MPRA_MTR1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 775 #define AIPS_MPRA_MTR1_SHIFT (26U)
mbed_official 121:7f86b4238bec 776 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
mbed_official 121:7f86b4238bec 777 #define AIPS_MPRA_MPL0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 778 #define AIPS_MPRA_MPL0_SHIFT (28U)
mbed_official 121:7f86b4238bec 779 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
mbed_official 121:7f86b4238bec 780 #define AIPS_MPRA_MTW0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 781 #define AIPS_MPRA_MTW0_SHIFT (29U)
mbed_official 121:7f86b4238bec 782 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
mbed_official 121:7f86b4238bec 783 #define AIPS_MPRA_MTR0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 784 #define AIPS_MPRA_MTR0_SHIFT (30U)
mbed_official 121:7f86b4238bec 785 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
mbed_official 121:7f86b4238bec 786
mbed_official 121:7f86b4238bec 787 /*! @name PACRA - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 788 #define AIPS_PACRA_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 789 #define AIPS_PACRA_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 790 #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
mbed_official 121:7f86b4238bec 791 #define AIPS_PACRA_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 792 #define AIPS_PACRA_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 793 #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
mbed_official 121:7f86b4238bec 794 #define AIPS_PACRA_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 795 #define AIPS_PACRA_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 796 #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
mbed_official 121:7f86b4238bec 797 #define AIPS_PACRA_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 798 #define AIPS_PACRA_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 799 #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
mbed_official 121:7f86b4238bec 800 #define AIPS_PACRA_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 801 #define AIPS_PACRA_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 802 #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
mbed_official 121:7f86b4238bec 803 #define AIPS_PACRA_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 804 #define AIPS_PACRA_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 805 #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
mbed_official 121:7f86b4238bec 806 #define AIPS_PACRA_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 807 #define AIPS_PACRA_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 808 #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
mbed_official 121:7f86b4238bec 809 #define AIPS_PACRA_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 810 #define AIPS_PACRA_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 811 #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
mbed_official 121:7f86b4238bec 812 #define AIPS_PACRA_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 813 #define AIPS_PACRA_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 814 #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
mbed_official 121:7f86b4238bec 815 #define AIPS_PACRA_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 816 #define AIPS_PACRA_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 817 #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
mbed_official 121:7f86b4238bec 818 #define AIPS_PACRA_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 819 #define AIPS_PACRA_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 820 #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
mbed_official 121:7f86b4238bec 821 #define AIPS_PACRA_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 822 #define AIPS_PACRA_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 823 #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
mbed_official 121:7f86b4238bec 824 #define AIPS_PACRA_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 825 #define AIPS_PACRA_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 826 #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
mbed_official 121:7f86b4238bec 827 #define AIPS_PACRA_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 828 #define AIPS_PACRA_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 829 #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
mbed_official 121:7f86b4238bec 830 #define AIPS_PACRA_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 831 #define AIPS_PACRA_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 832 #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
mbed_official 121:7f86b4238bec 833 #define AIPS_PACRA_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 834 #define AIPS_PACRA_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 835 #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
mbed_official 121:7f86b4238bec 836 #define AIPS_PACRA_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 837 #define AIPS_PACRA_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 838 #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
mbed_official 121:7f86b4238bec 839 #define AIPS_PACRA_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 840 #define AIPS_PACRA_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 841 #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
mbed_official 121:7f86b4238bec 842 #define AIPS_PACRA_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 843 #define AIPS_PACRA_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 844 #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
mbed_official 121:7f86b4238bec 845 #define AIPS_PACRA_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 846 #define AIPS_PACRA_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 847 #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
mbed_official 121:7f86b4238bec 848 #define AIPS_PACRA_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 849 #define AIPS_PACRA_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 850 #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
mbed_official 121:7f86b4238bec 851 #define AIPS_PACRA_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 852 #define AIPS_PACRA_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 853 #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
mbed_official 121:7f86b4238bec 854 #define AIPS_PACRA_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 855 #define AIPS_PACRA_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 856 #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
mbed_official 121:7f86b4238bec 857 #define AIPS_PACRA_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 858 #define AIPS_PACRA_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 859 #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
mbed_official 121:7f86b4238bec 860
mbed_official 121:7f86b4238bec 861 /*! @name PACRB - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 862 #define AIPS_PACRB_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 863 #define AIPS_PACRB_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 864 #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
mbed_official 121:7f86b4238bec 865 #define AIPS_PACRB_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 866 #define AIPS_PACRB_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 867 #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
mbed_official 121:7f86b4238bec 868 #define AIPS_PACRB_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 869 #define AIPS_PACRB_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 870 #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
mbed_official 121:7f86b4238bec 871 #define AIPS_PACRB_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 872 #define AIPS_PACRB_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 873 #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
mbed_official 121:7f86b4238bec 874 #define AIPS_PACRB_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 875 #define AIPS_PACRB_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 876 #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
mbed_official 121:7f86b4238bec 877 #define AIPS_PACRB_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 878 #define AIPS_PACRB_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 879 #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
mbed_official 121:7f86b4238bec 880 #define AIPS_PACRB_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 881 #define AIPS_PACRB_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 882 #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
mbed_official 121:7f86b4238bec 883 #define AIPS_PACRB_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 884 #define AIPS_PACRB_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 885 #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
mbed_official 121:7f86b4238bec 886 #define AIPS_PACRB_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 887 #define AIPS_PACRB_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 888 #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
mbed_official 121:7f86b4238bec 889 #define AIPS_PACRB_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 890 #define AIPS_PACRB_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 891 #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
mbed_official 121:7f86b4238bec 892 #define AIPS_PACRB_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 893 #define AIPS_PACRB_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 894 #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
mbed_official 121:7f86b4238bec 895 #define AIPS_PACRB_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 896 #define AIPS_PACRB_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 897 #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
mbed_official 121:7f86b4238bec 898 #define AIPS_PACRB_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 899 #define AIPS_PACRB_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 900 #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
mbed_official 121:7f86b4238bec 901 #define AIPS_PACRB_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 902 #define AIPS_PACRB_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 903 #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
mbed_official 121:7f86b4238bec 904 #define AIPS_PACRB_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 905 #define AIPS_PACRB_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 906 #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
mbed_official 121:7f86b4238bec 907 #define AIPS_PACRB_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 908 #define AIPS_PACRB_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 909 #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
mbed_official 121:7f86b4238bec 910 #define AIPS_PACRB_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 911 #define AIPS_PACRB_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 912 #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
mbed_official 121:7f86b4238bec 913 #define AIPS_PACRB_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 914 #define AIPS_PACRB_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 915 #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
mbed_official 121:7f86b4238bec 916 #define AIPS_PACRB_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 917 #define AIPS_PACRB_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 918 #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
mbed_official 121:7f86b4238bec 919 #define AIPS_PACRB_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 920 #define AIPS_PACRB_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 921 #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
mbed_official 121:7f86b4238bec 922 #define AIPS_PACRB_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 923 #define AIPS_PACRB_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 924 #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
mbed_official 121:7f86b4238bec 925 #define AIPS_PACRB_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 926 #define AIPS_PACRB_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 927 #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
mbed_official 121:7f86b4238bec 928 #define AIPS_PACRB_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 929 #define AIPS_PACRB_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 930 #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
mbed_official 121:7f86b4238bec 931 #define AIPS_PACRB_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 932 #define AIPS_PACRB_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 933 #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
mbed_official 121:7f86b4238bec 934
mbed_official 121:7f86b4238bec 935 /*! @name PACRC - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 936 #define AIPS_PACRC_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 937 #define AIPS_PACRC_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 938 #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
mbed_official 121:7f86b4238bec 939 #define AIPS_PACRC_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 940 #define AIPS_PACRC_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 941 #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
mbed_official 121:7f86b4238bec 942 #define AIPS_PACRC_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 943 #define AIPS_PACRC_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 944 #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
mbed_official 121:7f86b4238bec 945 #define AIPS_PACRC_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 946 #define AIPS_PACRC_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 947 #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
mbed_official 121:7f86b4238bec 948 #define AIPS_PACRC_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 949 #define AIPS_PACRC_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 950 #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
mbed_official 121:7f86b4238bec 951 #define AIPS_PACRC_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 952 #define AIPS_PACRC_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 953 #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
mbed_official 121:7f86b4238bec 954 #define AIPS_PACRC_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 955 #define AIPS_PACRC_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 956 #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
mbed_official 121:7f86b4238bec 957 #define AIPS_PACRC_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 958 #define AIPS_PACRC_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 959 #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
mbed_official 121:7f86b4238bec 960 #define AIPS_PACRC_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 961 #define AIPS_PACRC_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 962 #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
mbed_official 121:7f86b4238bec 963 #define AIPS_PACRC_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 964 #define AIPS_PACRC_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 965 #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
mbed_official 121:7f86b4238bec 966 #define AIPS_PACRC_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 967 #define AIPS_PACRC_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 968 #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
mbed_official 121:7f86b4238bec 969 #define AIPS_PACRC_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 970 #define AIPS_PACRC_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 971 #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
mbed_official 121:7f86b4238bec 972 #define AIPS_PACRC_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 973 #define AIPS_PACRC_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 974 #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
mbed_official 121:7f86b4238bec 975 #define AIPS_PACRC_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 976 #define AIPS_PACRC_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 977 #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
mbed_official 121:7f86b4238bec 978 #define AIPS_PACRC_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 979 #define AIPS_PACRC_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 980 #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
mbed_official 121:7f86b4238bec 981 #define AIPS_PACRC_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 982 #define AIPS_PACRC_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 983 #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
mbed_official 121:7f86b4238bec 984 #define AIPS_PACRC_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 985 #define AIPS_PACRC_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 986 #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
mbed_official 121:7f86b4238bec 987 #define AIPS_PACRC_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 988 #define AIPS_PACRC_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 989 #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
mbed_official 121:7f86b4238bec 990 #define AIPS_PACRC_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 991 #define AIPS_PACRC_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 992 #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
mbed_official 121:7f86b4238bec 993 #define AIPS_PACRC_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 994 #define AIPS_PACRC_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 995 #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
mbed_official 121:7f86b4238bec 996 #define AIPS_PACRC_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 997 #define AIPS_PACRC_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 998 #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
mbed_official 121:7f86b4238bec 999 #define AIPS_PACRC_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1000 #define AIPS_PACRC_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1001 #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
mbed_official 121:7f86b4238bec 1002 #define AIPS_PACRC_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1003 #define AIPS_PACRC_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1004 #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
mbed_official 121:7f86b4238bec 1005 #define AIPS_PACRC_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1006 #define AIPS_PACRC_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1007 #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
mbed_official 121:7f86b4238bec 1008
mbed_official 121:7f86b4238bec 1009 /*! @name PACRD - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1010 #define AIPS_PACRD_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1011 #define AIPS_PACRD_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1012 #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
mbed_official 121:7f86b4238bec 1013 #define AIPS_PACRD_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1014 #define AIPS_PACRD_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1015 #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
mbed_official 121:7f86b4238bec 1016 #define AIPS_PACRD_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1017 #define AIPS_PACRD_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1018 #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
mbed_official 121:7f86b4238bec 1019 #define AIPS_PACRD_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1020 #define AIPS_PACRD_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1021 #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
mbed_official 121:7f86b4238bec 1022 #define AIPS_PACRD_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1023 #define AIPS_PACRD_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1024 #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
mbed_official 121:7f86b4238bec 1025 #define AIPS_PACRD_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1026 #define AIPS_PACRD_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1027 #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
mbed_official 121:7f86b4238bec 1028 #define AIPS_PACRD_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1029 #define AIPS_PACRD_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1030 #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
mbed_official 121:7f86b4238bec 1031 #define AIPS_PACRD_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1032 #define AIPS_PACRD_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1033 #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
mbed_official 121:7f86b4238bec 1034 #define AIPS_PACRD_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1035 #define AIPS_PACRD_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1036 #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
mbed_official 121:7f86b4238bec 1037 #define AIPS_PACRD_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1038 #define AIPS_PACRD_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1039 #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
mbed_official 121:7f86b4238bec 1040 #define AIPS_PACRD_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1041 #define AIPS_PACRD_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1042 #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
mbed_official 121:7f86b4238bec 1043 #define AIPS_PACRD_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1044 #define AIPS_PACRD_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1045 #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
mbed_official 121:7f86b4238bec 1046 #define AIPS_PACRD_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1047 #define AIPS_PACRD_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1048 #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
mbed_official 121:7f86b4238bec 1049 #define AIPS_PACRD_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1050 #define AIPS_PACRD_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1051 #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
mbed_official 121:7f86b4238bec 1052 #define AIPS_PACRD_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1053 #define AIPS_PACRD_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1054 #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
mbed_official 121:7f86b4238bec 1055 #define AIPS_PACRD_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1056 #define AIPS_PACRD_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1057 #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
mbed_official 121:7f86b4238bec 1058 #define AIPS_PACRD_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1059 #define AIPS_PACRD_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1060 #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
mbed_official 121:7f86b4238bec 1061 #define AIPS_PACRD_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1062 #define AIPS_PACRD_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1063 #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
mbed_official 121:7f86b4238bec 1064 #define AIPS_PACRD_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1065 #define AIPS_PACRD_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1066 #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
mbed_official 121:7f86b4238bec 1067 #define AIPS_PACRD_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1068 #define AIPS_PACRD_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1069 #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
mbed_official 121:7f86b4238bec 1070 #define AIPS_PACRD_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1071 #define AIPS_PACRD_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1072 #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
mbed_official 121:7f86b4238bec 1073 #define AIPS_PACRD_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1074 #define AIPS_PACRD_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1075 #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
mbed_official 121:7f86b4238bec 1076 #define AIPS_PACRD_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1077 #define AIPS_PACRD_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1078 #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
mbed_official 121:7f86b4238bec 1079 #define AIPS_PACRD_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1080 #define AIPS_PACRD_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1081 #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
mbed_official 121:7f86b4238bec 1082
mbed_official 121:7f86b4238bec 1083 /*! @name PACRE - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1084 #define AIPS_PACRE_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1085 #define AIPS_PACRE_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1086 #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
mbed_official 121:7f86b4238bec 1087 #define AIPS_PACRE_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1088 #define AIPS_PACRE_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1089 #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
mbed_official 121:7f86b4238bec 1090 #define AIPS_PACRE_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1091 #define AIPS_PACRE_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1092 #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
mbed_official 121:7f86b4238bec 1093 #define AIPS_PACRE_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1094 #define AIPS_PACRE_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1095 #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
mbed_official 121:7f86b4238bec 1096 #define AIPS_PACRE_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1097 #define AIPS_PACRE_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1098 #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
mbed_official 121:7f86b4238bec 1099 #define AIPS_PACRE_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1100 #define AIPS_PACRE_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1101 #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
mbed_official 121:7f86b4238bec 1102 #define AIPS_PACRE_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1103 #define AIPS_PACRE_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1104 #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
mbed_official 121:7f86b4238bec 1105 #define AIPS_PACRE_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1106 #define AIPS_PACRE_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1107 #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
mbed_official 121:7f86b4238bec 1108 #define AIPS_PACRE_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1109 #define AIPS_PACRE_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1110 #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
mbed_official 121:7f86b4238bec 1111 #define AIPS_PACRE_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1112 #define AIPS_PACRE_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1113 #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
mbed_official 121:7f86b4238bec 1114 #define AIPS_PACRE_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1115 #define AIPS_PACRE_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1116 #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
mbed_official 121:7f86b4238bec 1117 #define AIPS_PACRE_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1118 #define AIPS_PACRE_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1119 #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
mbed_official 121:7f86b4238bec 1120 #define AIPS_PACRE_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1121 #define AIPS_PACRE_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1122 #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
mbed_official 121:7f86b4238bec 1123 #define AIPS_PACRE_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1124 #define AIPS_PACRE_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1125 #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
mbed_official 121:7f86b4238bec 1126 #define AIPS_PACRE_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1127 #define AIPS_PACRE_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1128 #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
mbed_official 121:7f86b4238bec 1129 #define AIPS_PACRE_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1130 #define AIPS_PACRE_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1131 #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
mbed_official 121:7f86b4238bec 1132 #define AIPS_PACRE_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1133 #define AIPS_PACRE_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1134 #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
mbed_official 121:7f86b4238bec 1135 #define AIPS_PACRE_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1136 #define AIPS_PACRE_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1137 #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
mbed_official 121:7f86b4238bec 1138 #define AIPS_PACRE_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1139 #define AIPS_PACRE_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1140 #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
mbed_official 121:7f86b4238bec 1141 #define AIPS_PACRE_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1142 #define AIPS_PACRE_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1143 #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
mbed_official 121:7f86b4238bec 1144 #define AIPS_PACRE_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1145 #define AIPS_PACRE_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1146 #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
mbed_official 121:7f86b4238bec 1147 #define AIPS_PACRE_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1148 #define AIPS_PACRE_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1149 #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
mbed_official 121:7f86b4238bec 1150 #define AIPS_PACRE_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1151 #define AIPS_PACRE_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1152 #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
mbed_official 121:7f86b4238bec 1153 #define AIPS_PACRE_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1154 #define AIPS_PACRE_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1155 #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
mbed_official 121:7f86b4238bec 1156
mbed_official 121:7f86b4238bec 1157 /*! @name PACRF - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1158 #define AIPS_PACRF_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1159 #define AIPS_PACRF_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1160 #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
mbed_official 121:7f86b4238bec 1161 #define AIPS_PACRF_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1162 #define AIPS_PACRF_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1163 #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
mbed_official 121:7f86b4238bec 1164 #define AIPS_PACRF_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1165 #define AIPS_PACRF_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1166 #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
mbed_official 121:7f86b4238bec 1167 #define AIPS_PACRF_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1168 #define AIPS_PACRF_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1169 #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
mbed_official 121:7f86b4238bec 1170 #define AIPS_PACRF_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1171 #define AIPS_PACRF_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1172 #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
mbed_official 121:7f86b4238bec 1173 #define AIPS_PACRF_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1174 #define AIPS_PACRF_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1175 #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
mbed_official 121:7f86b4238bec 1176 #define AIPS_PACRF_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1177 #define AIPS_PACRF_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1178 #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
mbed_official 121:7f86b4238bec 1179 #define AIPS_PACRF_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1180 #define AIPS_PACRF_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1181 #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
mbed_official 121:7f86b4238bec 1182 #define AIPS_PACRF_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1183 #define AIPS_PACRF_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1184 #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
mbed_official 121:7f86b4238bec 1185 #define AIPS_PACRF_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1186 #define AIPS_PACRF_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1187 #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
mbed_official 121:7f86b4238bec 1188 #define AIPS_PACRF_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1189 #define AIPS_PACRF_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1190 #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
mbed_official 121:7f86b4238bec 1191 #define AIPS_PACRF_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1192 #define AIPS_PACRF_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1193 #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
mbed_official 121:7f86b4238bec 1194 #define AIPS_PACRF_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1195 #define AIPS_PACRF_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1196 #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
mbed_official 121:7f86b4238bec 1197 #define AIPS_PACRF_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1198 #define AIPS_PACRF_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1199 #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
mbed_official 121:7f86b4238bec 1200 #define AIPS_PACRF_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1201 #define AIPS_PACRF_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1202 #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
mbed_official 121:7f86b4238bec 1203 #define AIPS_PACRF_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1204 #define AIPS_PACRF_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1205 #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
mbed_official 121:7f86b4238bec 1206 #define AIPS_PACRF_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1207 #define AIPS_PACRF_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1208 #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
mbed_official 121:7f86b4238bec 1209 #define AIPS_PACRF_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1210 #define AIPS_PACRF_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1211 #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
mbed_official 121:7f86b4238bec 1212 #define AIPS_PACRF_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1213 #define AIPS_PACRF_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1214 #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
mbed_official 121:7f86b4238bec 1215 #define AIPS_PACRF_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1216 #define AIPS_PACRF_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1217 #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
mbed_official 121:7f86b4238bec 1218 #define AIPS_PACRF_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1219 #define AIPS_PACRF_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1220 #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
mbed_official 121:7f86b4238bec 1221 #define AIPS_PACRF_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1222 #define AIPS_PACRF_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1223 #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
mbed_official 121:7f86b4238bec 1224 #define AIPS_PACRF_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1225 #define AIPS_PACRF_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1226 #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
mbed_official 121:7f86b4238bec 1227 #define AIPS_PACRF_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1228 #define AIPS_PACRF_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1229 #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
mbed_official 121:7f86b4238bec 1230
mbed_official 121:7f86b4238bec 1231 /*! @name PACRG - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1232 #define AIPS_PACRG_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1233 #define AIPS_PACRG_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1234 #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
mbed_official 121:7f86b4238bec 1235 #define AIPS_PACRG_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1236 #define AIPS_PACRG_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1237 #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
mbed_official 121:7f86b4238bec 1238 #define AIPS_PACRG_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1239 #define AIPS_PACRG_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1240 #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
mbed_official 121:7f86b4238bec 1241 #define AIPS_PACRG_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1242 #define AIPS_PACRG_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1243 #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
mbed_official 121:7f86b4238bec 1244 #define AIPS_PACRG_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1245 #define AIPS_PACRG_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1246 #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
mbed_official 121:7f86b4238bec 1247 #define AIPS_PACRG_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1248 #define AIPS_PACRG_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1249 #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
mbed_official 121:7f86b4238bec 1250 #define AIPS_PACRG_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1251 #define AIPS_PACRG_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1252 #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
mbed_official 121:7f86b4238bec 1253 #define AIPS_PACRG_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1254 #define AIPS_PACRG_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1255 #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
mbed_official 121:7f86b4238bec 1256 #define AIPS_PACRG_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1257 #define AIPS_PACRG_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1258 #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
mbed_official 121:7f86b4238bec 1259 #define AIPS_PACRG_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1260 #define AIPS_PACRG_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1261 #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
mbed_official 121:7f86b4238bec 1262 #define AIPS_PACRG_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1263 #define AIPS_PACRG_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1264 #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
mbed_official 121:7f86b4238bec 1265 #define AIPS_PACRG_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1266 #define AIPS_PACRG_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1267 #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
mbed_official 121:7f86b4238bec 1268 #define AIPS_PACRG_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1269 #define AIPS_PACRG_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1270 #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
mbed_official 121:7f86b4238bec 1271 #define AIPS_PACRG_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1272 #define AIPS_PACRG_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1273 #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
mbed_official 121:7f86b4238bec 1274 #define AIPS_PACRG_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1275 #define AIPS_PACRG_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1276 #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
mbed_official 121:7f86b4238bec 1277 #define AIPS_PACRG_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1278 #define AIPS_PACRG_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1279 #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
mbed_official 121:7f86b4238bec 1280 #define AIPS_PACRG_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1281 #define AIPS_PACRG_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1282 #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
mbed_official 121:7f86b4238bec 1283 #define AIPS_PACRG_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1284 #define AIPS_PACRG_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1285 #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
mbed_official 121:7f86b4238bec 1286 #define AIPS_PACRG_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1287 #define AIPS_PACRG_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1288 #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
mbed_official 121:7f86b4238bec 1289 #define AIPS_PACRG_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1290 #define AIPS_PACRG_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1291 #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
mbed_official 121:7f86b4238bec 1292 #define AIPS_PACRG_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1293 #define AIPS_PACRG_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1294 #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
mbed_official 121:7f86b4238bec 1295 #define AIPS_PACRG_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1296 #define AIPS_PACRG_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1297 #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
mbed_official 121:7f86b4238bec 1298 #define AIPS_PACRG_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1299 #define AIPS_PACRG_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1300 #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
mbed_official 121:7f86b4238bec 1301 #define AIPS_PACRG_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1302 #define AIPS_PACRG_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1303 #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
mbed_official 121:7f86b4238bec 1304
mbed_official 121:7f86b4238bec 1305 /*! @name PACRH - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1306 #define AIPS_PACRH_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1307 #define AIPS_PACRH_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1308 #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
mbed_official 121:7f86b4238bec 1309 #define AIPS_PACRH_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1310 #define AIPS_PACRH_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1311 #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
mbed_official 121:7f86b4238bec 1312 #define AIPS_PACRH_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1313 #define AIPS_PACRH_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1314 #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
mbed_official 121:7f86b4238bec 1315 #define AIPS_PACRH_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1316 #define AIPS_PACRH_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1317 #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
mbed_official 121:7f86b4238bec 1318 #define AIPS_PACRH_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1319 #define AIPS_PACRH_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1320 #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
mbed_official 121:7f86b4238bec 1321 #define AIPS_PACRH_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1322 #define AIPS_PACRH_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1323 #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
mbed_official 121:7f86b4238bec 1324 #define AIPS_PACRH_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1325 #define AIPS_PACRH_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1326 #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
mbed_official 121:7f86b4238bec 1327 #define AIPS_PACRH_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1328 #define AIPS_PACRH_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1329 #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
mbed_official 121:7f86b4238bec 1330 #define AIPS_PACRH_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1331 #define AIPS_PACRH_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1332 #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
mbed_official 121:7f86b4238bec 1333 #define AIPS_PACRH_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1334 #define AIPS_PACRH_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1335 #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
mbed_official 121:7f86b4238bec 1336 #define AIPS_PACRH_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1337 #define AIPS_PACRH_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1338 #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
mbed_official 121:7f86b4238bec 1339 #define AIPS_PACRH_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1340 #define AIPS_PACRH_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1341 #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
mbed_official 121:7f86b4238bec 1342 #define AIPS_PACRH_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1343 #define AIPS_PACRH_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1344 #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
mbed_official 121:7f86b4238bec 1345 #define AIPS_PACRH_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1346 #define AIPS_PACRH_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1347 #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
mbed_official 121:7f86b4238bec 1348 #define AIPS_PACRH_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1349 #define AIPS_PACRH_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1350 #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
mbed_official 121:7f86b4238bec 1351 #define AIPS_PACRH_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1352 #define AIPS_PACRH_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1353 #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
mbed_official 121:7f86b4238bec 1354 #define AIPS_PACRH_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1355 #define AIPS_PACRH_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1356 #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
mbed_official 121:7f86b4238bec 1357 #define AIPS_PACRH_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1358 #define AIPS_PACRH_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1359 #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
mbed_official 121:7f86b4238bec 1360 #define AIPS_PACRH_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1361 #define AIPS_PACRH_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1362 #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
mbed_official 121:7f86b4238bec 1363 #define AIPS_PACRH_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1364 #define AIPS_PACRH_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1365 #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
mbed_official 121:7f86b4238bec 1366 #define AIPS_PACRH_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1367 #define AIPS_PACRH_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1368 #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
mbed_official 121:7f86b4238bec 1369 #define AIPS_PACRH_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1370 #define AIPS_PACRH_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1371 #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
mbed_official 121:7f86b4238bec 1372 #define AIPS_PACRH_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1373 #define AIPS_PACRH_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1374 #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
mbed_official 121:7f86b4238bec 1375 #define AIPS_PACRH_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1376 #define AIPS_PACRH_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1377 #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
mbed_official 121:7f86b4238bec 1378
mbed_official 121:7f86b4238bec 1379 /*! @name PACRI - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1380 #define AIPS_PACRI_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1381 #define AIPS_PACRI_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1382 #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
mbed_official 121:7f86b4238bec 1383 #define AIPS_PACRI_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1384 #define AIPS_PACRI_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1385 #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
mbed_official 121:7f86b4238bec 1386 #define AIPS_PACRI_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1387 #define AIPS_PACRI_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1388 #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
mbed_official 121:7f86b4238bec 1389 #define AIPS_PACRI_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1390 #define AIPS_PACRI_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1391 #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
mbed_official 121:7f86b4238bec 1392 #define AIPS_PACRI_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1393 #define AIPS_PACRI_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1394 #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
mbed_official 121:7f86b4238bec 1395 #define AIPS_PACRI_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1396 #define AIPS_PACRI_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1397 #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
mbed_official 121:7f86b4238bec 1398 #define AIPS_PACRI_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1399 #define AIPS_PACRI_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1400 #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
mbed_official 121:7f86b4238bec 1401 #define AIPS_PACRI_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1402 #define AIPS_PACRI_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1403 #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
mbed_official 121:7f86b4238bec 1404 #define AIPS_PACRI_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1405 #define AIPS_PACRI_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1406 #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
mbed_official 121:7f86b4238bec 1407 #define AIPS_PACRI_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1408 #define AIPS_PACRI_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1409 #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
mbed_official 121:7f86b4238bec 1410 #define AIPS_PACRI_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1411 #define AIPS_PACRI_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1412 #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
mbed_official 121:7f86b4238bec 1413 #define AIPS_PACRI_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1414 #define AIPS_PACRI_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1415 #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
mbed_official 121:7f86b4238bec 1416 #define AIPS_PACRI_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1417 #define AIPS_PACRI_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1418 #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
mbed_official 121:7f86b4238bec 1419 #define AIPS_PACRI_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1420 #define AIPS_PACRI_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1421 #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
mbed_official 121:7f86b4238bec 1422 #define AIPS_PACRI_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1423 #define AIPS_PACRI_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1424 #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
mbed_official 121:7f86b4238bec 1425 #define AIPS_PACRI_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1426 #define AIPS_PACRI_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1427 #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
mbed_official 121:7f86b4238bec 1428 #define AIPS_PACRI_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1429 #define AIPS_PACRI_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1430 #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
mbed_official 121:7f86b4238bec 1431 #define AIPS_PACRI_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1432 #define AIPS_PACRI_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1433 #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
mbed_official 121:7f86b4238bec 1434 #define AIPS_PACRI_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1435 #define AIPS_PACRI_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1436 #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
mbed_official 121:7f86b4238bec 1437 #define AIPS_PACRI_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1438 #define AIPS_PACRI_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1439 #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
mbed_official 121:7f86b4238bec 1440 #define AIPS_PACRI_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1441 #define AIPS_PACRI_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1442 #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
mbed_official 121:7f86b4238bec 1443 #define AIPS_PACRI_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1444 #define AIPS_PACRI_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1445 #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
mbed_official 121:7f86b4238bec 1446 #define AIPS_PACRI_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1447 #define AIPS_PACRI_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1448 #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
mbed_official 121:7f86b4238bec 1449 #define AIPS_PACRI_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1450 #define AIPS_PACRI_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1451 #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
mbed_official 121:7f86b4238bec 1452
mbed_official 121:7f86b4238bec 1453 /*! @name PACRJ - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1454 #define AIPS_PACRJ_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1455 #define AIPS_PACRJ_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1456 #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
mbed_official 121:7f86b4238bec 1457 #define AIPS_PACRJ_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1458 #define AIPS_PACRJ_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1459 #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
mbed_official 121:7f86b4238bec 1460 #define AIPS_PACRJ_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1461 #define AIPS_PACRJ_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1462 #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
mbed_official 121:7f86b4238bec 1463 #define AIPS_PACRJ_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1464 #define AIPS_PACRJ_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1465 #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
mbed_official 121:7f86b4238bec 1466 #define AIPS_PACRJ_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1467 #define AIPS_PACRJ_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1468 #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
mbed_official 121:7f86b4238bec 1469 #define AIPS_PACRJ_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1470 #define AIPS_PACRJ_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1471 #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
mbed_official 121:7f86b4238bec 1472 #define AIPS_PACRJ_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1473 #define AIPS_PACRJ_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1474 #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
mbed_official 121:7f86b4238bec 1475 #define AIPS_PACRJ_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1476 #define AIPS_PACRJ_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1477 #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
mbed_official 121:7f86b4238bec 1478 #define AIPS_PACRJ_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1479 #define AIPS_PACRJ_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1480 #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
mbed_official 121:7f86b4238bec 1481 #define AIPS_PACRJ_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1482 #define AIPS_PACRJ_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1483 #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
mbed_official 121:7f86b4238bec 1484 #define AIPS_PACRJ_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1485 #define AIPS_PACRJ_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1486 #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
mbed_official 121:7f86b4238bec 1487 #define AIPS_PACRJ_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1488 #define AIPS_PACRJ_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1489 #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
mbed_official 121:7f86b4238bec 1490 #define AIPS_PACRJ_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1491 #define AIPS_PACRJ_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1492 #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
mbed_official 121:7f86b4238bec 1493 #define AIPS_PACRJ_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1494 #define AIPS_PACRJ_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1495 #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
mbed_official 121:7f86b4238bec 1496 #define AIPS_PACRJ_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1497 #define AIPS_PACRJ_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1498 #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
mbed_official 121:7f86b4238bec 1499 #define AIPS_PACRJ_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1500 #define AIPS_PACRJ_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1501 #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
mbed_official 121:7f86b4238bec 1502 #define AIPS_PACRJ_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1503 #define AIPS_PACRJ_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1504 #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
mbed_official 121:7f86b4238bec 1505 #define AIPS_PACRJ_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1506 #define AIPS_PACRJ_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1507 #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
mbed_official 121:7f86b4238bec 1508 #define AIPS_PACRJ_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1509 #define AIPS_PACRJ_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1510 #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
mbed_official 121:7f86b4238bec 1511 #define AIPS_PACRJ_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1512 #define AIPS_PACRJ_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1513 #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
mbed_official 121:7f86b4238bec 1514 #define AIPS_PACRJ_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1515 #define AIPS_PACRJ_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1516 #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
mbed_official 121:7f86b4238bec 1517 #define AIPS_PACRJ_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1518 #define AIPS_PACRJ_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1519 #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
mbed_official 121:7f86b4238bec 1520 #define AIPS_PACRJ_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1521 #define AIPS_PACRJ_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1522 #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
mbed_official 121:7f86b4238bec 1523 #define AIPS_PACRJ_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1524 #define AIPS_PACRJ_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1525 #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
mbed_official 121:7f86b4238bec 1526
mbed_official 121:7f86b4238bec 1527 /*! @name PACRK - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1528 #define AIPS_PACRK_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1529 #define AIPS_PACRK_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1530 #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
mbed_official 121:7f86b4238bec 1531 #define AIPS_PACRK_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1532 #define AIPS_PACRK_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1533 #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
mbed_official 121:7f86b4238bec 1534 #define AIPS_PACRK_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1535 #define AIPS_PACRK_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1536 #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
mbed_official 121:7f86b4238bec 1537 #define AIPS_PACRK_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1538 #define AIPS_PACRK_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1539 #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
mbed_official 121:7f86b4238bec 1540 #define AIPS_PACRK_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1541 #define AIPS_PACRK_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1542 #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
mbed_official 121:7f86b4238bec 1543 #define AIPS_PACRK_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1544 #define AIPS_PACRK_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1545 #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
mbed_official 121:7f86b4238bec 1546 #define AIPS_PACRK_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1547 #define AIPS_PACRK_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1548 #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
mbed_official 121:7f86b4238bec 1549 #define AIPS_PACRK_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1550 #define AIPS_PACRK_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1551 #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
mbed_official 121:7f86b4238bec 1552 #define AIPS_PACRK_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1553 #define AIPS_PACRK_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1554 #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
mbed_official 121:7f86b4238bec 1555 #define AIPS_PACRK_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1556 #define AIPS_PACRK_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1557 #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
mbed_official 121:7f86b4238bec 1558 #define AIPS_PACRK_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1559 #define AIPS_PACRK_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1560 #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
mbed_official 121:7f86b4238bec 1561 #define AIPS_PACRK_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1562 #define AIPS_PACRK_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1563 #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
mbed_official 121:7f86b4238bec 1564 #define AIPS_PACRK_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1565 #define AIPS_PACRK_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1566 #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
mbed_official 121:7f86b4238bec 1567 #define AIPS_PACRK_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1568 #define AIPS_PACRK_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1569 #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
mbed_official 121:7f86b4238bec 1570 #define AIPS_PACRK_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1571 #define AIPS_PACRK_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1572 #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
mbed_official 121:7f86b4238bec 1573 #define AIPS_PACRK_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1574 #define AIPS_PACRK_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1575 #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
mbed_official 121:7f86b4238bec 1576 #define AIPS_PACRK_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1577 #define AIPS_PACRK_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1578 #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
mbed_official 121:7f86b4238bec 1579 #define AIPS_PACRK_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1580 #define AIPS_PACRK_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1581 #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
mbed_official 121:7f86b4238bec 1582 #define AIPS_PACRK_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1583 #define AIPS_PACRK_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1584 #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
mbed_official 121:7f86b4238bec 1585 #define AIPS_PACRK_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1586 #define AIPS_PACRK_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1587 #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
mbed_official 121:7f86b4238bec 1588 #define AIPS_PACRK_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1589 #define AIPS_PACRK_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1590 #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
mbed_official 121:7f86b4238bec 1591 #define AIPS_PACRK_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1592 #define AIPS_PACRK_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1593 #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
mbed_official 121:7f86b4238bec 1594 #define AIPS_PACRK_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1595 #define AIPS_PACRK_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1596 #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
mbed_official 121:7f86b4238bec 1597 #define AIPS_PACRK_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1598 #define AIPS_PACRK_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1599 #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
mbed_official 121:7f86b4238bec 1600
mbed_official 121:7f86b4238bec 1601 /*! @name PACRL - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1602 #define AIPS_PACRL_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1603 #define AIPS_PACRL_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1604 #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
mbed_official 121:7f86b4238bec 1605 #define AIPS_PACRL_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1606 #define AIPS_PACRL_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1607 #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
mbed_official 121:7f86b4238bec 1608 #define AIPS_PACRL_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1609 #define AIPS_PACRL_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1610 #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
mbed_official 121:7f86b4238bec 1611 #define AIPS_PACRL_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1612 #define AIPS_PACRL_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1613 #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
mbed_official 121:7f86b4238bec 1614 #define AIPS_PACRL_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1615 #define AIPS_PACRL_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1616 #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
mbed_official 121:7f86b4238bec 1617 #define AIPS_PACRL_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1618 #define AIPS_PACRL_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1619 #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
mbed_official 121:7f86b4238bec 1620 #define AIPS_PACRL_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1621 #define AIPS_PACRL_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1622 #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
mbed_official 121:7f86b4238bec 1623 #define AIPS_PACRL_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1624 #define AIPS_PACRL_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1625 #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
mbed_official 121:7f86b4238bec 1626 #define AIPS_PACRL_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1627 #define AIPS_PACRL_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1628 #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
mbed_official 121:7f86b4238bec 1629 #define AIPS_PACRL_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1630 #define AIPS_PACRL_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1631 #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
mbed_official 121:7f86b4238bec 1632 #define AIPS_PACRL_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1633 #define AIPS_PACRL_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1634 #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
mbed_official 121:7f86b4238bec 1635 #define AIPS_PACRL_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1636 #define AIPS_PACRL_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1637 #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
mbed_official 121:7f86b4238bec 1638 #define AIPS_PACRL_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1639 #define AIPS_PACRL_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1640 #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
mbed_official 121:7f86b4238bec 1641 #define AIPS_PACRL_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1642 #define AIPS_PACRL_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1643 #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
mbed_official 121:7f86b4238bec 1644 #define AIPS_PACRL_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1645 #define AIPS_PACRL_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1646 #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
mbed_official 121:7f86b4238bec 1647 #define AIPS_PACRL_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1648 #define AIPS_PACRL_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1649 #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
mbed_official 121:7f86b4238bec 1650 #define AIPS_PACRL_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1651 #define AIPS_PACRL_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1652 #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
mbed_official 121:7f86b4238bec 1653 #define AIPS_PACRL_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1654 #define AIPS_PACRL_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1655 #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
mbed_official 121:7f86b4238bec 1656 #define AIPS_PACRL_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1657 #define AIPS_PACRL_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1658 #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
mbed_official 121:7f86b4238bec 1659 #define AIPS_PACRL_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1660 #define AIPS_PACRL_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1661 #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
mbed_official 121:7f86b4238bec 1662 #define AIPS_PACRL_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1663 #define AIPS_PACRL_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1664 #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
mbed_official 121:7f86b4238bec 1665 #define AIPS_PACRL_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1666 #define AIPS_PACRL_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1667 #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
mbed_official 121:7f86b4238bec 1668 #define AIPS_PACRL_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1669 #define AIPS_PACRL_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1670 #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
mbed_official 121:7f86b4238bec 1671 #define AIPS_PACRL_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1672 #define AIPS_PACRL_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1673 #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
mbed_official 121:7f86b4238bec 1674
mbed_official 121:7f86b4238bec 1675 /*! @name PACRM - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1676 #define AIPS_PACRM_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1677 #define AIPS_PACRM_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1678 #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
mbed_official 121:7f86b4238bec 1679 #define AIPS_PACRM_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1680 #define AIPS_PACRM_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1681 #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
mbed_official 121:7f86b4238bec 1682 #define AIPS_PACRM_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1683 #define AIPS_PACRM_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1684 #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
mbed_official 121:7f86b4238bec 1685 #define AIPS_PACRM_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1686 #define AIPS_PACRM_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1687 #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
mbed_official 121:7f86b4238bec 1688 #define AIPS_PACRM_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1689 #define AIPS_PACRM_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1690 #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
mbed_official 121:7f86b4238bec 1691 #define AIPS_PACRM_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1692 #define AIPS_PACRM_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1693 #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
mbed_official 121:7f86b4238bec 1694 #define AIPS_PACRM_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1695 #define AIPS_PACRM_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1696 #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
mbed_official 121:7f86b4238bec 1697 #define AIPS_PACRM_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1698 #define AIPS_PACRM_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1699 #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
mbed_official 121:7f86b4238bec 1700 #define AIPS_PACRM_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1701 #define AIPS_PACRM_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1702 #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
mbed_official 121:7f86b4238bec 1703 #define AIPS_PACRM_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1704 #define AIPS_PACRM_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1705 #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
mbed_official 121:7f86b4238bec 1706 #define AIPS_PACRM_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1707 #define AIPS_PACRM_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1708 #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
mbed_official 121:7f86b4238bec 1709 #define AIPS_PACRM_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1710 #define AIPS_PACRM_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1711 #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
mbed_official 121:7f86b4238bec 1712 #define AIPS_PACRM_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1713 #define AIPS_PACRM_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1714 #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
mbed_official 121:7f86b4238bec 1715 #define AIPS_PACRM_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1716 #define AIPS_PACRM_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1717 #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
mbed_official 121:7f86b4238bec 1718 #define AIPS_PACRM_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1719 #define AIPS_PACRM_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1720 #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
mbed_official 121:7f86b4238bec 1721 #define AIPS_PACRM_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1722 #define AIPS_PACRM_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1723 #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
mbed_official 121:7f86b4238bec 1724 #define AIPS_PACRM_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1725 #define AIPS_PACRM_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1726 #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
mbed_official 121:7f86b4238bec 1727 #define AIPS_PACRM_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1728 #define AIPS_PACRM_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1729 #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
mbed_official 121:7f86b4238bec 1730 #define AIPS_PACRM_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1731 #define AIPS_PACRM_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1732 #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
mbed_official 121:7f86b4238bec 1733 #define AIPS_PACRM_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1734 #define AIPS_PACRM_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1735 #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
mbed_official 121:7f86b4238bec 1736 #define AIPS_PACRM_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1737 #define AIPS_PACRM_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1738 #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
mbed_official 121:7f86b4238bec 1739 #define AIPS_PACRM_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1740 #define AIPS_PACRM_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1741 #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
mbed_official 121:7f86b4238bec 1742 #define AIPS_PACRM_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1743 #define AIPS_PACRM_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1744 #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
mbed_official 121:7f86b4238bec 1745 #define AIPS_PACRM_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1746 #define AIPS_PACRM_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1747 #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
mbed_official 121:7f86b4238bec 1748
mbed_official 121:7f86b4238bec 1749 /*! @name PACRN - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1750 #define AIPS_PACRN_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1751 #define AIPS_PACRN_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1752 #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
mbed_official 121:7f86b4238bec 1753 #define AIPS_PACRN_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1754 #define AIPS_PACRN_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1755 #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
mbed_official 121:7f86b4238bec 1756 #define AIPS_PACRN_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1757 #define AIPS_PACRN_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1758 #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
mbed_official 121:7f86b4238bec 1759 #define AIPS_PACRN_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1760 #define AIPS_PACRN_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1761 #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
mbed_official 121:7f86b4238bec 1762 #define AIPS_PACRN_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1763 #define AIPS_PACRN_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1764 #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
mbed_official 121:7f86b4238bec 1765 #define AIPS_PACRN_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1766 #define AIPS_PACRN_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1767 #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
mbed_official 121:7f86b4238bec 1768 #define AIPS_PACRN_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1769 #define AIPS_PACRN_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1770 #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
mbed_official 121:7f86b4238bec 1771 #define AIPS_PACRN_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1772 #define AIPS_PACRN_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1773 #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
mbed_official 121:7f86b4238bec 1774 #define AIPS_PACRN_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1775 #define AIPS_PACRN_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1776 #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
mbed_official 121:7f86b4238bec 1777 #define AIPS_PACRN_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1778 #define AIPS_PACRN_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1779 #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
mbed_official 121:7f86b4238bec 1780 #define AIPS_PACRN_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1781 #define AIPS_PACRN_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1782 #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
mbed_official 121:7f86b4238bec 1783 #define AIPS_PACRN_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1784 #define AIPS_PACRN_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1785 #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
mbed_official 121:7f86b4238bec 1786 #define AIPS_PACRN_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1787 #define AIPS_PACRN_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1788 #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
mbed_official 121:7f86b4238bec 1789 #define AIPS_PACRN_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1790 #define AIPS_PACRN_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1791 #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
mbed_official 121:7f86b4238bec 1792 #define AIPS_PACRN_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1793 #define AIPS_PACRN_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1794 #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
mbed_official 121:7f86b4238bec 1795 #define AIPS_PACRN_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1796 #define AIPS_PACRN_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1797 #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
mbed_official 121:7f86b4238bec 1798 #define AIPS_PACRN_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1799 #define AIPS_PACRN_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1800 #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
mbed_official 121:7f86b4238bec 1801 #define AIPS_PACRN_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1802 #define AIPS_PACRN_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1803 #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
mbed_official 121:7f86b4238bec 1804 #define AIPS_PACRN_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1805 #define AIPS_PACRN_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1806 #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
mbed_official 121:7f86b4238bec 1807 #define AIPS_PACRN_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1808 #define AIPS_PACRN_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1809 #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
mbed_official 121:7f86b4238bec 1810 #define AIPS_PACRN_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1811 #define AIPS_PACRN_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1812 #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
mbed_official 121:7f86b4238bec 1813 #define AIPS_PACRN_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1814 #define AIPS_PACRN_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1815 #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
mbed_official 121:7f86b4238bec 1816 #define AIPS_PACRN_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1817 #define AIPS_PACRN_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1818 #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
mbed_official 121:7f86b4238bec 1819 #define AIPS_PACRN_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1820 #define AIPS_PACRN_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1821 #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
mbed_official 121:7f86b4238bec 1822
mbed_official 121:7f86b4238bec 1823 /*! @name PACRO - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1824 #define AIPS_PACRO_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1825 #define AIPS_PACRO_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1826 #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
mbed_official 121:7f86b4238bec 1827 #define AIPS_PACRO_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1828 #define AIPS_PACRO_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1829 #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
mbed_official 121:7f86b4238bec 1830 #define AIPS_PACRO_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1831 #define AIPS_PACRO_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1832 #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
mbed_official 121:7f86b4238bec 1833 #define AIPS_PACRO_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1834 #define AIPS_PACRO_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1835 #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
mbed_official 121:7f86b4238bec 1836 #define AIPS_PACRO_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1837 #define AIPS_PACRO_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1838 #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
mbed_official 121:7f86b4238bec 1839 #define AIPS_PACRO_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1840 #define AIPS_PACRO_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1841 #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
mbed_official 121:7f86b4238bec 1842 #define AIPS_PACRO_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1843 #define AIPS_PACRO_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1844 #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
mbed_official 121:7f86b4238bec 1845 #define AIPS_PACRO_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1846 #define AIPS_PACRO_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1847 #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
mbed_official 121:7f86b4238bec 1848 #define AIPS_PACRO_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1849 #define AIPS_PACRO_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1850 #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
mbed_official 121:7f86b4238bec 1851 #define AIPS_PACRO_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1852 #define AIPS_PACRO_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1853 #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
mbed_official 121:7f86b4238bec 1854 #define AIPS_PACRO_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1855 #define AIPS_PACRO_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1856 #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
mbed_official 121:7f86b4238bec 1857 #define AIPS_PACRO_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1858 #define AIPS_PACRO_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1859 #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
mbed_official 121:7f86b4238bec 1860 #define AIPS_PACRO_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1861 #define AIPS_PACRO_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1862 #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
mbed_official 121:7f86b4238bec 1863 #define AIPS_PACRO_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1864 #define AIPS_PACRO_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1865 #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
mbed_official 121:7f86b4238bec 1866 #define AIPS_PACRO_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1867 #define AIPS_PACRO_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1868 #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
mbed_official 121:7f86b4238bec 1869 #define AIPS_PACRO_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1870 #define AIPS_PACRO_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1871 #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
mbed_official 121:7f86b4238bec 1872 #define AIPS_PACRO_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1873 #define AIPS_PACRO_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1874 #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
mbed_official 121:7f86b4238bec 1875 #define AIPS_PACRO_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1876 #define AIPS_PACRO_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1877 #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
mbed_official 121:7f86b4238bec 1878 #define AIPS_PACRO_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1879 #define AIPS_PACRO_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1880 #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
mbed_official 121:7f86b4238bec 1881 #define AIPS_PACRO_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1882 #define AIPS_PACRO_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1883 #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
mbed_official 121:7f86b4238bec 1884 #define AIPS_PACRO_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1885 #define AIPS_PACRO_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1886 #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
mbed_official 121:7f86b4238bec 1887 #define AIPS_PACRO_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1888 #define AIPS_PACRO_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1889 #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
mbed_official 121:7f86b4238bec 1890 #define AIPS_PACRO_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1891 #define AIPS_PACRO_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1892 #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
mbed_official 121:7f86b4238bec 1893 #define AIPS_PACRO_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1894 #define AIPS_PACRO_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1895 #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
mbed_official 121:7f86b4238bec 1896
mbed_official 121:7f86b4238bec 1897 /*! @name PACRP - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1898 #define AIPS_PACRP_TP7_MASK (0x1U)
mbed_official 121:7f86b4238bec 1899 #define AIPS_PACRP_TP7_SHIFT (0U)
mbed_official 121:7f86b4238bec 1900 #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
mbed_official 121:7f86b4238bec 1901 #define AIPS_PACRP_WP7_MASK (0x2U)
mbed_official 121:7f86b4238bec 1902 #define AIPS_PACRP_WP7_SHIFT (1U)
mbed_official 121:7f86b4238bec 1903 #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
mbed_official 121:7f86b4238bec 1904 #define AIPS_PACRP_SP7_MASK (0x4U)
mbed_official 121:7f86b4238bec 1905 #define AIPS_PACRP_SP7_SHIFT (2U)
mbed_official 121:7f86b4238bec 1906 #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
mbed_official 121:7f86b4238bec 1907 #define AIPS_PACRP_TP6_MASK (0x10U)
mbed_official 121:7f86b4238bec 1908 #define AIPS_PACRP_TP6_SHIFT (4U)
mbed_official 121:7f86b4238bec 1909 #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
mbed_official 121:7f86b4238bec 1910 #define AIPS_PACRP_WP6_MASK (0x20U)
mbed_official 121:7f86b4238bec 1911 #define AIPS_PACRP_WP6_SHIFT (5U)
mbed_official 121:7f86b4238bec 1912 #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
mbed_official 121:7f86b4238bec 1913 #define AIPS_PACRP_SP6_MASK (0x40U)
mbed_official 121:7f86b4238bec 1914 #define AIPS_PACRP_SP6_SHIFT (6U)
mbed_official 121:7f86b4238bec 1915 #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
mbed_official 121:7f86b4238bec 1916 #define AIPS_PACRP_TP5_MASK (0x100U)
mbed_official 121:7f86b4238bec 1917 #define AIPS_PACRP_TP5_SHIFT (8U)
mbed_official 121:7f86b4238bec 1918 #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
mbed_official 121:7f86b4238bec 1919 #define AIPS_PACRP_WP5_MASK (0x200U)
mbed_official 121:7f86b4238bec 1920 #define AIPS_PACRP_WP5_SHIFT (9U)
mbed_official 121:7f86b4238bec 1921 #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
mbed_official 121:7f86b4238bec 1922 #define AIPS_PACRP_SP5_MASK (0x400U)
mbed_official 121:7f86b4238bec 1923 #define AIPS_PACRP_SP5_SHIFT (10U)
mbed_official 121:7f86b4238bec 1924 #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
mbed_official 121:7f86b4238bec 1925 #define AIPS_PACRP_TP4_MASK (0x1000U)
mbed_official 121:7f86b4238bec 1926 #define AIPS_PACRP_TP4_SHIFT (12U)
mbed_official 121:7f86b4238bec 1927 #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
mbed_official 121:7f86b4238bec 1928 #define AIPS_PACRP_WP4_MASK (0x2000U)
mbed_official 121:7f86b4238bec 1929 #define AIPS_PACRP_WP4_SHIFT (13U)
mbed_official 121:7f86b4238bec 1930 #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
mbed_official 121:7f86b4238bec 1931 #define AIPS_PACRP_SP4_MASK (0x4000U)
mbed_official 121:7f86b4238bec 1932 #define AIPS_PACRP_SP4_SHIFT (14U)
mbed_official 121:7f86b4238bec 1933 #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
mbed_official 121:7f86b4238bec 1934 #define AIPS_PACRP_TP3_MASK (0x10000U)
mbed_official 121:7f86b4238bec 1935 #define AIPS_PACRP_TP3_SHIFT (16U)
mbed_official 121:7f86b4238bec 1936 #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
mbed_official 121:7f86b4238bec 1937 #define AIPS_PACRP_WP3_MASK (0x20000U)
mbed_official 121:7f86b4238bec 1938 #define AIPS_PACRP_WP3_SHIFT (17U)
mbed_official 121:7f86b4238bec 1939 #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
mbed_official 121:7f86b4238bec 1940 #define AIPS_PACRP_SP3_MASK (0x40000U)
mbed_official 121:7f86b4238bec 1941 #define AIPS_PACRP_SP3_SHIFT (18U)
mbed_official 121:7f86b4238bec 1942 #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
mbed_official 121:7f86b4238bec 1943 #define AIPS_PACRP_TP2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 1944 #define AIPS_PACRP_TP2_SHIFT (20U)
mbed_official 121:7f86b4238bec 1945 #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
mbed_official 121:7f86b4238bec 1946 #define AIPS_PACRP_WP2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 1947 #define AIPS_PACRP_WP2_SHIFT (21U)
mbed_official 121:7f86b4238bec 1948 #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
mbed_official 121:7f86b4238bec 1949 #define AIPS_PACRP_SP2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 1950 #define AIPS_PACRP_SP2_SHIFT (22U)
mbed_official 121:7f86b4238bec 1951 #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
mbed_official 121:7f86b4238bec 1952 #define AIPS_PACRP_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1953 #define AIPS_PACRP_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1954 #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
mbed_official 121:7f86b4238bec 1955 #define AIPS_PACRP_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1956 #define AIPS_PACRP_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1957 #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
mbed_official 121:7f86b4238bec 1958 #define AIPS_PACRP_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1959 #define AIPS_PACRP_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1960 #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
mbed_official 121:7f86b4238bec 1961 #define AIPS_PACRP_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1962 #define AIPS_PACRP_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1963 #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
mbed_official 121:7f86b4238bec 1964 #define AIPS_PACRP_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1965 #define AIPS_PACRP_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1966 #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
mbed_official 121:7f86b4238bec 1967 #define AIPS_PACRP_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1968 #define AIPS_PACRP_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1969 #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
mbed_official 121:7f86b4238bec 1970
mbed_official 121:7f86b4238bec 1971 /*! @name PACRU - Peripheral Access Control Register */
mbed_official 121:7f86b4238bec 1972 #define AIPS_PACRU_TP1_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 1973 #define AIPS_PACRU_TP1_SHIFT (24U)
mbed_official 121:7f86b4238bec 1974 #define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK)
mbed_official 121:7f86b4238bec 1975 #define AIPS_PACRU_WP1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 1976 #define AIPS_PACRU_WP1_SHIFT (25U)
mbed_official 121:7f86b4238bec 1977 #define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK)
mbed_official 121:7f86b4238bec 1978 #define AIPS_PACRU_SP1_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 1979 #define AIPS_PACRU_SP1_SHIFT (26U)
mbed_official 121:7f86b4238bec 1980 #define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK)
mbed_official 121:7f86b4238bec 1981 #define AIPS_PACRU_TP0_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 1982 #define AIPS_PACRU_TP0_SHIFT (28U)
mbed_official 121:7f86b4238bec 1983 #define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK)
mbed_official 121:7f86b4238bec 1984 #define AIPS_PACRU_WP0_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 1985 #define AIPS_PACRU_WP0_SHIFT (29U)
mbed_official 121:7f86b4238bec 1986 #define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK)
mbed_official 121:7f86b4238bec 1987 #define AIPS_PACRU_SP0_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 1988 #define AIPS_PACRU_SP0_SHIFT (30U)
mbed_official 121:7f86b4238bec 1989 #define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK)
mbed_official 121:7f86b4238bec 1990
mbed_official 121:7f86b4238bec 1991
mbed_official 121:7f86b4238bec 1992 /*!
mbed_official 121:7f86b4238bec 1993 * @}
mbed_official 121:7f86b4238bec 1994 */ /* end of group AIPS_Register_Masks */
mbed_official 121:7f86b4238bec 1995
mbed_official 121:7f86b4238bec 1996
mbed_official 121:7f86b4238bec 1997 /* AIPS - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 1998 /** Peripheral AIPS0 base address */
mbed_official 121:7f86b4238bec 1999 #define AIPS0_BASE (0x40000000u)
mbed_official 121:7f86b4238bec 2000 /** Peripheral AIPS0 base pointer */
mbed_official 121:7f86b4238bec 2001 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
mbed_official 121:7f86b4238bec 2002 /** Peripheral AIPS1 base address */
mbed_official 121:7f86b4238bec 2003 #define AIPS1_BASE (0x40080000u)
mbed_official 121:7f86b4238bec 2004 /** Peripheral AIPS1 base pointer */
mbed_official 121:7f86b4238bec 2005 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
mbed_official 121:7f86b4238bec 2006 /** Array initializer of AIPS peripheral base addresses */
mbed_official 121:7f86b4238bec 2007 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
mbed_official 121:7f86b4238bec 2008 /** Array initializer of AIPS peripheral base pointers */
mbed_official 121:7f86b4238bec 2009 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
mbed_official 121:7f86b4238bec 2010
mbed_official 121:7f86b4238bec 2011 /*!
mbed_official 121:7f86b4238bec 2012 * @}
mbed_official 121:7f86b4238bec 2013 */ /* end of group AIPS_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 2014
mbed_official 121:7f86b4238bec 2015
mbed_official 121:7f86b4238bec 2016 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 2017 -- AXBS Peripheral Access Layer
mbed_official 121:7f86b4238bec 2018 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 2019
mbed_official 121:7f86b4238bec 2020 /*!
mbed_official 121:7f86b4238bec 2021 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
mbed_official 121:7f86b4238bec 2022 * @{
mbed_official 121:7f86b4238bec 2023 */
mbed_official 121:7f86b4238bec 2024
mbed_official 121:7f86b4238bec 2025 /** AXBS - Register Layout Typedef */
mbed_official 121:7f86b4238bec 2026 typedef struct {
mbed_official 121:7f86b4238bec 2027 struct { /* offset: 0x0, array step: 0x100 */
mbed_official 121:7f86b4238bec 2028 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
mbed_official 121:7f86b4238bec 2029 uint8_t RESERVED_0[12];
mbed_official 121:7f86b4238bec 2030 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
mbed_official 121:7f86b4238bec 2031 uint8_t RESERVED_1[236];
mbed_official 121:7f86b4238bec 2032 } SLAVE[5];
mbed_official 121:7f86b4238bec 2033 uint8_t RESERVED_0[768];
mbed_official 121:7f86b4238bec 2034 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
mbed_official 121:7f86b4238bec 2035 uint8_t RESERVED_1[252];
mbed_official 121:7f86b4238bec 2036 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
mbed_official 121:7f86b4238bec 2037 uint8_t RESERVED_2[252];
mbed_official 121:7f86b4238bec 2038 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
mbed_official 121:7f86b4238bec 2039 uint8_t RESERVED_3[252];
mbed_official 121:7f86b4238bec 2040 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
mbed_official 121:7f86b4238bec 2041 uint8_t RESERVED_4[252];
mbed_official 121:7f86b4238bec 2042 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
mbed_official 121:7f86b4238bec 2043 uint8_t RESERVED_5[252];
mbed_official 121:7f86b4238bec 2044 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
mbed_official 121:7f86b4238bec 2045 } AXBS_Type;
mbed_official 121:7f86b4238bec 2046
mbed_official 121:7f86b4238bec 2047 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 2048 -- AXBS Register Masks
mbed_official 121:7f86b4238bec 2049 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 2050
mbed_official 121:7f86b4238bec 2051 /*!
mbed_official 121:7f86b4238bec 2052 * @addtogroup AXBS_Register_Masks AXBS Register Masks
mbed_official 121:7f86b4238bec 2053 * @{
mbed_official 121:7f86b4238bec 2054 */
mbed_official 121:7f86b4238bec 2055
mbed_official 121:7f86b4238bec 2056 /*! @name PRS - Priority Registers Slave */
mbed_official 121:7f86b4238bec 2057 #define AXBS_PRS_M0_MASK (0x7U)
mbed_official 121:7f86b4238bec 2058 #define AXBS_PRS_M0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2059 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
mbed_official 121:7f86b4238bec 2060 #define AXBS_PRS_M1_MASK (0x70U)
mbed_official 121:7f86b4238bec 2061 #define AXBS_PRS_M1_SHIFT (4U)
mbed_official 121:7f86b4238bec 2062 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
mbed_official 121:7f86b4238bec 2063 #define AXBS_PRS_M2_MASK (0x700U)
mbed_official 121:7f86b4238bec 2064 #define AXBS_PRS_M2_SHIFT (8U)
mbed_official 121:7f86b4238bec 2065 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
mbed_official 121:7f86b4238bec 2066 #define AXBS_PRS_M3_MASK (0x7000U)
mbed_official 121:7f86b4238bec 2067 #define AXBS_PRS_M3_SHIFT (12U)
mbed_official 121:7f86b4238bec 2068 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
mbed_official 121:7f86b4238bec 2069 #define AXBS_PRS_M4_MASK (0x70000U)
mbed_official 121:7f86b4238bec 2070 #define AXBS_PRS_M4_SHIFT (16U)
mbed_official 121:7f86b4238bec 2071 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
mbed_official 121:7f86b4238bec 2072 #define AXBS_PRS_M5_MASK (0x700000U)
mbed_official 121:7f86b4238bec 2073 #define AXBS_PRS_M5_SHIFT (20U)
mbed_official 121:7f86b4238bec 2074 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
mbed_official 121:7f86b4238bec 2075
mbed_official 121:7f86b4238bec 2076 /* The count of AXBS_PRS */
mbed_official 121:7f86b4238bec 2077 #define AXBS_PRS_COUNT (5U)
mbed_official 121:7f86b4238bec 2078
mbed_official 121:7f86b4238bec 2079 /*! @name CRS - Control Register */
mbed_official 121:7f86b4238bec 2080 #define AXBS_CRS_PARK_MASK (0x7U)
mbed_official 121:7f86b4238bec 2081 #define AXBS_CRS_PARK_SHIFT (0U)
mbed_official 121:7f86b4238bec 2082 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
mbed_official 121:7f86b4238bec 2083 #define AXBS_CRS_PCTL_MASK (0x30U)
mbed_official 121:7f86b4238bec 2084 #define AXBS_CRS_PCTL_SHIFT (4U)
mbed_official 121:7f86b4238bec 2085 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
mbed_official 121:7f86b4238bec 2086 #define AXBS_CRS_ARB_MASK (0x300U)
mbed_official 121:7f86b4238bec 2087 #define AXBS_CRS_ARB_SHIFT (8U)
mbed_official 121:7f86b4238bec 2088 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
mbed_official 121:7f86b4238bec 2089 #define AXBS_CRS_HLP_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 2090 #define AXBS_CRS_HLP_SHIFT (30U)
mbed_official 121:7f86b4238bec 2091 #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
mbed_official 121:7f86b4238bec 2092 #define AXBS_CRS_RO_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 2093 #define AXBS_CRS_RO_SHIFT (31U)
mbed_official 121:7f86b4238bec 2094 #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
mbed_official 121:7f86b4238bec 2095
mbed_official 121:7f86b4238bec 2096 /* The count of AXBS_CRS */
mbed_official 121:7f86b4238bec 2097 #define AXBS_CRS_COUNT (5U)
mbed_official 121:7f86b4238bec 2098
mbed_official 121:7f86b4238bec 2099 /*! @name MGPCR0 - Master General Purpose Control Register */
mbed_official 121:7f86b4238bec 2100 #define AXBS_MGPCR0_AULB_MASK (0x7U)
mbed_official 121:7f86b4238bec 2101 #define AXBS_MGPCR0_AULB_SHIFT (0U)
mbed_official 121:7f86b4238bec 2102 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
mbed_official 121:7f86b4238bec 2103
mbed_official 121:7f86b4238bec 2104 /*! @name MGPCR1 - Master General Purpose Control Register */
mbed_official 121:7f86b4238bec 2105 #define AXBS_MGPCR1_AULB_MASK (0x7U)
mbed_official 121:7f86b4238bec 2106 #define AXBS_MGPCR1_AULB_SHIFT (0U)
mbed_official 121:7f86b4238bec 2107 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
mbed_official 121:7f86b4238bec 2108
mbed_official 121:7f86b4238bec 2109 /*! @name MGPCR2 - Master General Purpose Control Register */
mbed_official 121:7f86b4238bec 2110 #define AXBS_MGPCR2_AULB_MASK (0x7U)
mbed_official 121:7f86b4238bec 2111 #define AXBS_MGPCR2_AULB_SHIFT (0U)
mbed_official 121:7f86b4238bec 2112 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
mbed_official 121:7f86b4238bec 2113
mbed_official 121:7f86b4238bec 2114 /*! @name MGPCR3 - Master General Purpose Control Register */
mbed_official 121:7f86b4238bec 2115 #define AXBS_MGPCR3_AULB_MASK (0x7U)
mbed_official 121:7f86b4238bec 2116 #define AXBS_MGPCR3_AULB_SHIFT (0U)
mbed_official 121:7f86b4238bec 2117 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
mbed_official 121:7f86b4238bec 2118
mbed_official 121:7f86b4238bec 2119 /*! @name MGPCR4 - Master General Purpose Control Register */
mbed_official 121:7f86b4238bec 2120 #define AXBS_MGPCR4_AULB_MASK (0x7U)
mbed_official 121:7f86b4238bec 2121 #define AXBS_MGPCR4_AULB_SHIFT (0U)
mbed_official 121:7f86b4238bec 2122 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
mbed_official 121:7f86b4238bec 2123
mbed_official 121:7f86b4238bec 2124 /*! @name MGPCR5 - Master General Purpose Control Register */
mbed_official 121:7f86b4238bec 2125 #define AXBS_MGPCR5_AULB_MASK (0x7U)
mbed_official 121:7f86b4238bec 2126 #define AXBS_MGPCR5_AULB_SHIFT (0U)
mbed_official 121:7f86b4238bec 2127 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
mbed_official 121:7f86b4238bec 2128
mbed_official 121:7f86b4238bec 2129
mbed_official 121:7f86b4238bec 2130 /*!
mbed_official 121:7f86b4238bec 2131 * @}
mbed_official 121:7f86b4238bec 2132 */ /* end of group AXBS_Register_Masks */
mbed_official 121:7f86b4238bec 2133
mbed_official 121:7f86b4238bec 2134
mbed_official 121:7f86b4238bec 2135 /* AXBS - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 2136 /** Peripheral AXBS base address */
mbed_official 121:7f86b4238bec 2137 #define AXBS_BASE (0x40004000u)
mbed_official 121:7f86b4238bec 2138 /** Peripheral AXBS base pointer */
mbed_official 121:7f86b4238bec 2139 #define AXBS ((AXBS_Type *)AXBS_BASE)
mbed_official 121:7f86b4238bec 2140 /** Array initializer of AXBS peripheral base addresses */
mbed_official 121:7f86b4238bec 2141 #define AXBS_BASE_ADDRS { AXBS_BASE }
mbed_official 121:7f86b4238bec 2142 /** Array initializer of AXBS peripheral base pointers */
mbed_official 121:7f86b4238bec 2143 #define AXBS_BASE_PTRS { AXBS }
mbed_official 121:7f86b4238bec 2144
mbed_official 121:7f86b4238bec 2145 /*!
mbed_official 121:7f86b4238bec 2146 * @}
mbed_official 121:7f86b4238bec 2147 */ /* end of group AXBS_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 2148
mbed_official 121:7f86b4238bec 2149
mbed_official 121:7f86b4238bec 2150 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 2151 -- CAN Peripheral Access Layer
mbed_official 121:7f86b4238bec 2152 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 2153
mbed_official 121:7f86b4238bec 2154 /*!
mbed_official 121:7f86b4238bec 2155 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
mbed_official 121:7f86b4238bec 2156 * @{
mbed_official 121:7f86b4238bec 2157 */
mbed_official 121:7f86b4238bec 2158
mbed_official 121:7f86b4238bec 2159 /** CAN - Register Layout Typedef */
mbed_official 121:7f86b4238bec 2160 typedef struct {
mbed_official 121:7f86b4238bec 2161 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 2162 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
mbed_official 121:7f86b4238bec 2163 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
mbed_official 121:7f86b4238bec 2164 uint8_t RESERVED_0[4];
mbed_official 121:7f86b4238bec 2165 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
mbed_official 121:7f86b4238bec 2166 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
mbed_official 121:7f86b4238bec 2167 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
mbed_official 121:7f86b4238bec 2168 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
mbed_official 121:7f86b4238bec 2169 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
mbed_official 121:7f86b4238bec 2170 uint8_t RESERVED_1[4];
mbed_official 121:7f86b4238bec 2171 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
mbed_official 121:7f86b4238bec 2172 uint8_t RESERVED_2[4];
mbed_official 121:7f86b4238bec 2173 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
mbed_official 121:7f86b4238bec 2174 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
mbed_official 121:7f86b4238bec 2175 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
mbed_official 121:7f86b4238bec 2176 uint8_t RESERVED_3[8];
mbed_official 121:7f86b4238bec 2177 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
mbed_official 121:7f86b4238bec 2178 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
mbed_official 121:7f86b4238bec 2179 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
mbed_official 121:7f86b4238bec 2180 uint8_t RESERVED_4[48];
mbed_official 121:7f86b4238bec 2181 struct { /* offset: 0x80, array step: 0x10 */
mbed_official 121:7f86b4238bec 2182 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
mbed_official 121:7f86b4238bec 2183 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
mbed_official 121:7f86b4238bec 2184 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
mbed_official 121:7f86b4238bec 2185 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
mbed_official 121:7f86b4238bec 2186 } MB[16];
mbed_official 121:7f86b4238bec 2187 uint8_t RESERVED_5[1792];
mbed_official 121:7f86b4238bec 2188 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
mbed_official 121:7f86b4238bec 2189 } CAN_Type;
mbed_official 121:7f86b4238bec 2190
mbed_official 121:7f86b4238bec 2191 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 2192 -- CAN Register Masks
mbed_official 121:7f86b4238bec 2193 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 2194
mbed_official 121:7f86b4238bec 2195 /*!
mbed_official 121:7f86b4238bec 2196 * @addtogroup CAN_Register_Masks CAN Register Masks
mbed_official 121:7f86b4238bec 2197 * @{
mbed_official 121:7f86b4238bec 2198 */
mbed_official 121:7f86b4238bec 2199
mbed_official 121:7f86b4238bec 2200 /*! @name MCR - Module Configuration Register */
mbed_official 121:7f86b4238bec 2201 #define CAN_MCR_MAXMB_MASK (0x7FU)
mbed_official 121:7f86b4238bec 2202 #define CAN_MCR_MAXMB_SHIFT (0U)
mbed_official 121:7f86b4238bec 2203 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
mbed_official 121:7f86b4238bec 2204 #define CAN_MCR_IDAM_MASK (0x300U)
mbed_official 121:7f86b4238bec 2205 #define CAN_MCR_IDAM_SHIFT (8U)
mbed_official 121:7f86b4238bec 2206 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
mbed_official 121:7f86b4238bec 2207 #define CAN_MCR_AEN_MASK (0x1000U)
mbed_official 121:7f86b4238bec 2208 #define CAN_MCR_AEN_SHIFT (12U)
mbed_official 121:7f86b4238bec 2209 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
mbed_official 121:7f86b4238bec 2210 #define CAN_MCR_LPRIOEN_MASK (0x2000U)
mbed_official 121:7f86b4238bec 2211 #define CAN_MCR_LPRIOEN_SHIFT (13U)
mbed_official 121:7f86b4238bec 2212 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
mbed_official 121:7f86b4238bec 2213 #define CAN_MCR_IRMQ_MASK (0x10000U)
mbed_official 121:7f86b4238bec 2214 #define CAN_MCR_IRMQ_SHIFT (16U)
mbed_official 121:7f86b4238bec 2215 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
mbed_official 121:7f86b4238bec 2216 #define CAN_MCR_SRXDIS_MASK (0x20000U)
mbed_official 121:7f86b4238bec 2217 #define CAN_MCR_SRXDIS_SHIFT (17U)
mbed_official 121:7f86b4238bec 2218 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
mbed_official 121:7f86b4238bec 2219 #define CAN_MCR_WAKSRC_MASK (0x80000U)
mbed_official 121:7f86b4238bec 2220 #define CAN_MCR_WAKSRC_SHIFT (19U)
mbed_official 121:7f86b4238bec 2221 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
mbed_official 121:7f86b4238bec 2222 #define CAN_MCR_LPMACK_MASK (0x100000U)
mbed_official 121:7f86b4238bec 2223 #define CAN_MCR_LPMACK_SHIFT (20U)
mbed_official 121:7f86b4238bec 2224 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
mbed_official 121:7f86b4238bec 2225 #define CAN_MCR_WRNEN_MASK (0x200000U)
mbed_official 121:7f86b4238bec 2226 #define CAN_MCR_WRNEN_SHIFT (21U)
mbed_official 121:7f86b4238bec 2227 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
mbed_official 121:7f86b4238bec 2228 #define CAN_MCR_SLFWAK_MASK (0x400000U)
mbed_official 121:7f86b4238bec 2229 #define CAN_MCR_SLFWAK_SHIFT (22U)
mbed_official 121:7f86b4238bec 2230 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
mbed_official 121:7f86b4238bec 2231 #define CAN_MCR_SUPV_MASK (0x800000U)
mbed_official 121:7f86b4238bec 2232 #define CAN_MCR_SUPV_SHIFT (23U)
mbed_official 121:7f86b4238bec 2233 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
mbed_official 121:7f86b4238bec 2234 #define CAN_MCR_FRZACK_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 2235 #define CAN_MCR_FRZACK_SHIFT (24U)
mbed_official 121:7f86b4238bec 2236 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
mbed_official 121:7f86b4238bec 2237 #define CAN_MCR_SOFTRST_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 2238 #define CAN_MCR_SOFTRST_SHIFT (25U)
mbed_official 121:7f86b4238bec 2239 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
mbed_official 121:7f86b4238bec 2240 #define CAN_MCR_WAKMSK_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 2241 #define CAN_MCR_WAKMSK_SHIFT (26U)
mbed_official 121:7f86b4238bec 2242 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
mbed_official 121:7f86b4238bec 2243 #define CAN_MCR_NOTRDY_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 2244 #define CAN_MCR_NOTRDY_SHIFT (27U)
mbed_official 121:7f86b4238bec 2245 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
mbed_official 121:7f86b4238bec 2246 #define CAN_MCR_HALT_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 2247 #define CAN_MCR_HALT_SHIFT (28U)
mbed_official 121:7f86b4238bec 2248 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
mbed_official 121:7f86b4238bec 2249 #define CAN_MCR_RFEN_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 2250 #define CAN_MCR_RFEN_SHIFT (29U)
mbed_official 121:7f86b4238bec 2251 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
mbed_official 121:7f86b4238bec 2252 #define CAN_MCR_FRZ_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 2253 #define CAN_MCR_FRZ_SHIFT (30U)
mbed_official 121:7f86b4238bec 2254 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
mbed_official 121:7f86b4238bec 2255 #define CAN_MCR_MDIS_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 2256 #define CAN_MCR_MDIS_SHIFT (31U)
mbed_official 121:7f86b4238bec 2257 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
mbed_official 121:7f86b4238bec 2258
mbed_official 121:7f86b4238bec 2259 /*! @name CTRL1 - Control 1 register */
mbed_official 121:7f86b4238bec 2260 #define CAN_CTRL1_PROPSEG_MASK (0x7U)
mbed_official 121:7f86b4238bec 2261 #define CAN_CTRL1_PROPSEG_SHIFT (0U)
mbed_official 121:7f86b4238bec 2262 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
mbed_official 121:7f86b4238bec 2263 #define CAN_CTRL1_LOM_MASK (0x8U)
mbed_official 121:7f86b4238bec 2264 #define CAN_CTRL1_LOM_SHIFT (3U)
mbed_official 121:7f86b4238bec 2265 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
mbed_official 121:7f86b4238bec 2266 #define CAN_CTRL1_LBUF_MASK (0x10U)
mbed_official 121:7f86b4238bec 2267 #define CAN_CTRL1_LBUF_SHIFT (4U)
mbed_official 121:7f86b4238bec 2268 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
mbed_official 121:7f86b4238bec 2269 #define CAN_CTRL1_TSYN_MASK (0x20U)
mbed_official 121:7f86b4238bec 2270 #define CAN_CTRL1_TSYN_SHIFT (5U)
mbed_official 121:7f86b4238bec 2271 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
mbed_official 121:7f86b4238bec 2272 #define CAN_CTRL1_BOFFREC_MASK (0x40U)
mbed_official 121:7f86b4238bec 2273 #define CAN_CTRL1_BOFFREC_SHIFT (6U)
mbed_official 121:7f86b4238bec 2274 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
mbed_official 121:7f86b4238bec 2275 #define CAN_CTRL1_SMP_MASK (0x80U)
mbed_official 121:7f86b4238bec 2276 #define CAN_CTRL1_SMP_SHIFT (7U)
mbed_official 121:7f86b4238bec 2277 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
mbed_official 121:7f86b4238bec 2278 #define CAN_CTRL1_RWRNMSK_MASK (0x400U)
mbed_official 121:7f86b4238bec 2279 #define CAN_CTRL1_RWRNMSK_SHIFT (10U)
mbed_official 121:7f86b4238bec 2280 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
mbed_official 121:7f86b4238bec 2281 #define CAN_CTRL1_TWRNMSK_MASK (0x800U)
mbed_official 121:7f86b4238bec 2282 #define CAN_CTRL1_TWRNMSK_SHIFT (11U)
mbed_official 121:7f86b4238bec 2283 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
mbed_official 121:7f86b4238bec 2284 #define CAN_CTRL1_LPB_MASK (0x1000U)
mbed_official 121:7f86b4238bec 2285 #define CAN_CTRL1_LPB_SHIFT (12U)
mbed_official 121:7f86b4238bec 2286 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
mbed_official 121:7f86b4238bec 2287 #define CAN_CTRL1_CLKSRC_MASK (0x2000U)
mbed_official 121:7f86b4238bec 2288 #define CAN_CTRL1_CLKSRC_SHIFT (13U)
mbed_official 121:7f86b4238bec 2289 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
mbed_official 121:7f86b4238bec 2290 #define CAN_CTRL1_ERRMSK_MASK (0x4000U)
mbed_official 121:7f86b4238bec 2291 #define CAN_CTRL1_ERRMSK_SHIFT (14U)
mbed_official 121:7f86b4238bec 2292 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
mbed_official 121:7f86b4238bec 2293 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
mbed_official 121:7f86b4238bec 2294 #define CAN_CTRL1_BOFFMSK_SHIFT (15U)
mbed_official 121:7f86b4238bec 2295 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
mbed_official 121:7f86b4238bec 2296 #define CAN_CTRL1_PSEG2_MASK (0x70000U)
mbed_official 121:7f86b4238bec 2297 #define CAN_CTRL1_PSEG2_SHIFT (16U)
mbed_official 121:7f86b4238bec 2298 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
mbed_official 121:7f86b4238bec 2299 #define CAN_CTRL1_PSEG1_MASK (0x380000U)
mbed_official 121:7f86b4238bec 2300 #define CAN_CTRL1_PSEG1_SHIFT (19U)
mbed_official 121:7f86b4238bec 2301 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
mbed_official 121:7f86b4238bec 2302 #define CAN_CTRL1_RJW_MASK (0xC00000U)
mbed_official 121:7f86b4238bec 2303 #define CAN_CTRL1_RJW_SHIFT (22U)
mbed_official 121:7f86b4238bec 2304 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
mbed_official 121:7f86b4238bec 2305 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 2306 #define CAN_CTRL1_PRESDIV_SHIFT (24U)
mbed_official 121:7f86b4238bec 2307 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
mbed_official 121:7f86b4238bec 2308
mbed_official 121:7f86b4238bec 2309 /*! @name TIMER - Free Running Timer */
mbed_official 121:7f86b4238bec 2310 #define CAN_TIMER_TIMER_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 2311 #define CAN_TIMER_TIMER_SHIFT (0U)
mbed_official 121:7f86b4238bec 2312 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
mbed_official 121:7f86b4238bec 2313
mbed_official 121:7f86b4238bec 2314 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
mbed_official 121:7f86b4238bec 2315 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2316 #define CAN_RXMGMASK_MG_SHIFT (0U)
mbed_official 121:7f86b4238bec 2317 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
mbed_official 121:7f86b4238bec 2318
mbed_official 121:7f86b4238bec 2319 /*! @name RX14MASK - Rx 14 Mask register */
mbed_official 121:7f86b4238bec 2320 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2321 #define CAN_RX14MASK_RX14M_SHIFT (0U)
mbed_official 121:7f86b4238bec 2322 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
mbed_official 121:7f86b4238bec 2323
mbed_official 121:7f86b4238bec 2324 /*! @name RX15MASK - Rx 15 Mask register */
mbed_official 121:7f86b4238bec 2325 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2326 #define CAN_RX15MASK_RX15M_SHIFT (0U)
mbed_official 121:7f86b4238bec 2327 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
mbed_official 121:7f86b4238bec 2328
mbed_official 121:7f86b4238bec 2329 /*! @name ECR - Error Counter */
mbed_official 121:7f86b4238bec 2330 #define CAN_ECR_TXERRCNT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 2331 #define CAN_ECR_TXERRCNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 2332 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
mbed_official 121:7f86b4238bec 2333 #define CAN_ECR_RXERRCNT_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 2334 #define CAN_ECR_RXERRCNT_SHIFT (8U)
mbed_official 121:7f86b4238bec 2335 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
mbed_official 121:7f86b4238bec 2336
mbed_official 121:7f86b4238bec 2337 /*! @name ESR1 - Error and Status 1 register */
mbed_official 121:7f86b4238bec 2338 #define CAN_ESR1_WAKINT_MASK (0x1U)
mbed_official 121:7f86b4238bec 2339 #define CAN_ESR1_WAKINT_SHIFT (0U)
mbed_official 121:7f86b4238bec 2340 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
mbed_official 121:7f86b4238bec 2341 #define CAN_ESR1_ERRINT_MASK (0x2U)
mbed_official 121:7f86b4238bec 2342 #define CAN_ESR1_ERRINT_SHIFT (1U)
mbed_official 121:7f86b4238bec 2343 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
mbed_official 121:7f86b4238bec 2344 #define CAN_ESR1_BOFFINT_MASK (0x4U)
mbed_official 121:7f86b4238bec 2345 #define CAN_ESR1_BOFFINT_SHIFT (2U)
mbed_official 121:7f86b4238bec 2346 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
mbed_official 121:7f86b4238bec 2347 #define CAN_ESR1_RX_MASK (0x8U)
mbed_official 121:7f86b4238bec 2348 #define CAN_ESR1_RX_SHIFT (3U)
mbed_official 121:7f86b4238bec 2349 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
mbed_official 121:7f86b4238bec 2350 #define CAN_ESR1_FLTCONF_MASK (0x30U)
mbed_official 121:7f86b4238bec 2351 #define CAN_ESR1_FLTCONF_SHIFT (4U)
mbed_official 121:7f86b4238bec 2352 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
mbed_official 121:7f86b4238bec 2353 #define CAN_ESR1_TX_MASK (0x40U)
mbed_official 121:7f86b4238bec 2354 #define CAN_ESR1_TX_SHIFT (6U)
mbed_official 121:7f86b4238bec 2355 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
mbed_official 121:7f86b4238bec 2356 #define CAN_ESR1_IDLE_MASK (0x80U)
mbed_official 121:7f86b4238bec 2357 #define CAN_ESR1_IDLE_SHIFT (7U)
mbed_official 121:7f86b4238bec 2358 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
mbed_official 121:7f86b4238bec 2359 #define CAN_ESR1_RXWRN_MASK (0x100U)
mbed_official 121:7f86b4238bec 2360 #define CAN_ESR1_RXWRN_SHIFT (8U)
mbed_official 121:7f86b4238bec 2361 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
mbed_official 121:7f86b4238bec 2362 #define CAN_ESR1_TXWRN_MASK (0x200U)
mbed_official 121:7f86b4238bec 2363 #define CAN_ESR1_TXWRN_SHIFT (9U)
mbed_official 121:7f86b4238bec 2364 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
mbed_official 121:7f86b4238bec 2365 #define CAN_ESR1_STFERR_MASK (0x400U)
mbed_official 121:7f86b4238bec 2366 #define CAN_ESR1_STFERR_SHIFT (10U)
mbed_official 121:7f86b4238bec 2367 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
mbed_official 121:7f86b4238bec 2368 #define CAN_ESR1_FRMERR_MASK (0x800U)
mbed_official 121:7f86b4238bec 2369 #define CAN_ESR1_FRMERR_SHIFT (11U)
mbed_official 121:7f86b4238bec 2370 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
mbed_official 121:7f86b4238bec 2371 #define CAN_ESR1_CRCERR_MASK (0x1000U)
mbed_official 121:7f86b4238bec 2372 #define CAN_ESR1_CRCERR_SHIFT (12U)
mbed_official 121:7f86b4238bec 2373 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
mbed_official 121:7f86b4238bec 2374 #define CAN_ESR1_ACKERR_MASK (0x2000U)
mbed_official 121:7f86b4238bec 2375 #define CAN_ESR1_ACKERR_SHIFT (13U)
mbed_official 121:7f86b4238bec 2376 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
mbed_official 121:7f86b4238bec 2377 #define CAN_ESR1_BIT0ERR_MASK (0x4000U)
mbed_official 121:7f86b4238bec 2378 #define CAN_ESR1_BIT0ERR_SHIFT (14U)
mbed_official 121:7f86b4238bec 2379 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
mbed_official 121:7f86b4238bec 2380 #define CAN_ESR1_BIT1ERR_MASK (0x8000U)
mbed_official 121:7f86b4238bec 2381 #define CAN_ESR1_BIT1ERR_SHIFT (15U)
mbed_official 121:7f86b4238bec 2382 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
mbed_official 121:7f86b4238bec 2383 #define CAN_ESR1_RWRNINT_MASK (0x10000U)
mbed_official 121:7f86b4238bec 2384 #define CAN_ESR1_RWRNINT_SHIFT (16U)
mbed_official 121:7f86b4238bec 2385 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
mbed_official 121:7f86b4238bec 2386 #define CAN_ESR1_TWRNINT_MASK (0x20000U)
mbed_official 121:7f86b4238bec 2387 #define CAN_ESR1_TWRNINT_SHIFT (17U)
mbed_official 121:7f86b4238bec 2388 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
mbed_official 121:7f86b4238bec 2389 #define CAN_ESR1_SYNCH_MASK (0x40000U)
mbed_official 121:7f86b4238bec 2390 #define CAN_ESR1_SYNCH_SHIFT (18U)
mbed_official 121:7f86b4238bec 2391 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
mbed_official 121:7f86b4238bec 2392
mbed_official 121:7f86b4238bec 2393 /*! @name IMASK1 - Interrupt Masks 1 register */
mbed_official 121:7f86b4238bec 2394 #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2395 #define CAN_IMASK1_BUFLM_SHIFT (0U)
mbed_official 121:7f86b4238bec 2396 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
mbed_official 121:7f86b4238bec 2397
mbed_official 121:7f86b4238bec 2398 /*! @name IFLAG1 - Interrupt Flags 1 register */
mbed_official 121:7f86b4238bec 2399 #define CAN_IFLAG1_BUF0I_MASK (0x1U)
mbed_official 121:7f86b4238bec 2400 #define CAN_IFLAG1_BUF0I_SHIFT (0U)
mbed_official 121:7f86b4238bec 2401 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
mbed_official 121:7f86b4238bec 2402 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
mbed_official 121:7f86b4238bec 2403 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
mbed_official 121:7f86b4238bec 2404 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
mbed_official 121:7f86b4238bec 2405 #define CAN_IFLAG1_BUF5I_MASK (0x20U)
mbed_official 121:7f86b4238bec 2406 #define CAN_IFLAG1_BUF5I_SHIFT (5U)
mbed_official 121:7f86b4238bec 2407 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
mbed_official 121:7f86b4238bec 2408 #define CAN_IFLAG1_BUF6I_MASK (0x40U)
mbed_official 121:7f86b4238bec 2409 #define CAN_IFLAG1_BUF6I_SHIFT (6U)
mbed_official 121:7f86b4238bec 2410 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
mbed_official 121:7f86b4238bec 2411 #define CAN_IFLAG1_BUF7I_MASK (0x80U)
mbed_official 121:7f86b4238bec 2412 #define CAN_IFLAG1_BUF7I_SHIFT (7U)
mbed_official 121:7f86b4238bec 2413 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
mbed_official 121:7f86b4238bec 2414 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
mbed_official 121:7f86b4238bec 2415 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
mbed_official 121:7f86b4238bec 2416 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
mbed_official 121:7f86b4238bec 2417
mbed_official 121:7f86b4238bec 2418 /*! @name CTRL2 - Control 2 register */
mbed_official 121:7f86b4238bec 2419 #define CAN_CTRL2_EACEN_MASK (0x10000U)
mbed_official 121:7f86b4238bec 2420 #define CAN_CTRL2_EACEN_SHIFT (16U)
mbed_official 121:7f86b4238bec 2421 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
mbed_official 121:7f86b4238bec 2422 #define CAN_CTRL2_RRS_MASK (0x20000U)
mbed_official 121:7f86b4238bec 2423 #define CAN_CTRL2_RRS_SHIFT (17U)
mbed_official 121:7f86b4238bec 2424 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
mbed_official 121:7f86b4238bec 2425 #define CAN_CTRL2_MRP_MASK (0x40000U)
mbed_official 121:7f86b4238bec 2426 #define CAN_CTRL2_MRP_SHIFT (18U)
mbed_official 121:7f86b4238bec 2427 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
mbed_official 121:7f86b4238bec 2428 #define CAN_CTRL2_TASD_MASK (0xF80000U)
mbed_official 121:7f86b4238bec 2429 #define CAN_CTRL2_TASD_SHIFT (19U)
mbed_official 121:7f86b4238bec 2430 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
mbed_official 121:7f86b4238bec 2431 #define CAN_CTRL2_RFFN_MASK (0xF000000U)
mbed_official 121:7f86b4238bec 2432 #define CAN_CTRL2_RFFN_SHIFT (24U)
mbed_official 121:7f86b4238bec 2433 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
mbed_official 121:7f86b4238bec 2434 #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 2435 #define CAN_CTRL2_WRMFRZ_SHIFT (28U)
mbed_official 121:7f86b4238bec 2436 #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
mbed_official 121:7f86b4238bec 2437
mbed_official 121:7f86b4238bec 2438 /*! @name ESR2 - Error and Status 2 register */
mbed_official 121:7f86b4238bec 2439 #define CAN_ESR2_IMB_MASK (0x2000U)
mbed_official 121:7f86b4238bec 2440 #define CAN_ESR2_IMB_SHIFT (13U)
mbed_official 121:7f86b4238bec 2441 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
mbed_official 121:7f86b4238bec 2442 #define CAN_ESR2_VPS_MASK (0x4000U)
mbed_official 121:7f86b4238bec 2443 #define CAN_ESR2_VPS_SHIFT (14U)
mbed_official 121:7f86b4238bec 2444 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
mbed_official 121:7f86b4238bec 2445 #define CAN_ESR2_LPTM_MASK (0x7F0000U)
mbed_official 121:7f86b4238bec 2446 #define CAN_ESR2_LPTM_SHIFT (16U)
mbed_official 121:7f86b4238bec 2447 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
mbed_official 121:7f86b4238bec 2448
mbed_official 121:7f86b4238bec 2449 /*! @name CRCR - CRC Register */
mbed_official 121:7f86b4238bec 2450 #define CAN_CRCR_TXCRC_MASK (0x7FFFU)
mbed_official 121:7f86b4238bec 2451 #define CAN_CRCR_TXCRC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2452 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
mbed_official 121:7f86b4238bec 2453 #define CAN_CRCR_MBCRC_MASK (0x7F0000U)
mbed_official 121:7f86b4238bec 2454 #define CAN_CRCR_MBCRC_SHIFT (16U)
mbed_official 121:7f86b4238bec 2455 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
mbed_official 121:7f86b4238bec 2456
mbed_official 121:7f86b4238bec 2457 /*! @name RXFGMASK - Rx FIFO Global Mask register */
mbed_official 121:7f86b4238bec 2458 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2459 #define CAN_RXFGMASK_FGM_SHIFT (0U)
mbed_official 121:7f86b4238bec 2460 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
mbed_official 121:7f86b4238bec 2461
mbed_official 121:7f86b4238bec 2462 /*! @name RXFIR - Rx FIFO Information Register */
mbed_official 121:7f86b4238bec 2463 #define CAN_RXFIR_IDHIT_MASK (0x1FFU)
mbed_official 121:7f86b4238bec 2464 #define CAN_RXFIR_IDHIT_SHIFT (0U)
mbed_official 121:7f86b4238bec 2465 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
mbed_official 121:7f86b4238bec 2466
mbed_official 121:7f86b4238bec 2467 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
mbed_official 121:7f86b4238bec 2468 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 2469 #define CAN_CS_TIME_STAMP_SHIFT (0U)
mbed_official 121:7f86b4238bec 2470 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
mbed_official 121:7f86b4238bec 2471 #define CAN_CS_DLC_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 2472 #define CAN_CS_DLC_SHIFT (16U)
mbed_official 121:7f86b4238bec 2473 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
mbed_official 121:7f86b4238bec 2474 #define CAN_CS_RTR_MASK (0x100000U)
mbed_official 121:7f86b4238bec 2475 #define CAN_CS_RTR_SHIFT (20U)
mbed_official 121:7f86b4238bec 2476 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
mbed_official 121:7f86b4238bec 2477 #define CAN_CS_IDE_MASK (0x200000U)
mbed_official 121:7f86b4238bec 2478 #define CAN_CS_IDE_SHIFT (21U)
mbed_official 121:7f86b4238bec 2479 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
mbed_official 121:7f86b4238bec 2480 #define CAN_CS_SRR_MASK (0x400000U)
mbed_official 121:7f86b4238bec 2481 #define CAN_CS_SRR_SHIFT (22U)
mbed_official 121:7f86b4238bec 2482 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
mbed_official 121:7f86b4238bec 2483 #define CAN_CS_CODE_MASK (0xF000000U)
mbed_official 121:7f86b4238bec 2484 #define CAN_CS_CODE_SHIFT (24U)
mbed_official 121:7f86b4238bec 2485 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
mbed_official 121:7f86b4238bec 2486
mbed_official 121:7f86b4238bec 2487 /* The count of CAN_CS */
mbed_official 121:7f86b4238bec 2488 #define CAN_CS_COUNT (16U)
mbed_official 121:7f86b4238bec 2489
mbed_official 121:7f86b4238bec 2490 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
mbed_official 121:7f86b4238bec 2491 #define CAN_ID_EXT_MASK (0x3FFFFU)
mbed_official 121:7f86b4238bec 2492 #define CAN_ID_EXT_SHIFT (0U)
mbed_official 121:7f86b4238bec 2493 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
mbed_official 121:7f86b4238bec 2494 #define CAN_ID_STD_MASK (0x1FFC0000U)
mbed_official 121:7f86b4238bec 2495 #define CAN_ID_STD_SHIFT (18U)
mbed_official 121:7f86b4238bec 2496 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
mbed_official 121:7f86b4238bec 2497 #define CAN_ID_PRIO_MASK (0xE0000000U)
mbed_official 121:7f86b4238bec 2498 #define CAN_ID_PRIO_SHIFT (29U)
mbed_official 121:7f86b4238bec 2499 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
mbed_official 121:7f86b4238bec 2500
mbed_official 121:7f86b4238bec 2501 /* The count of CAN_ID */
mbed_official 121:7f86b4238bec 2502 #define CAN_ID_COUNT (16U)
mbed_official 121:7f86b4238bec 2503
mbed_official 121:7f86b4238bec 2504 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
mbed_official 121:7f86b4238bec 2505 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
mbed_official 121:7f86b4238bec 2506 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2507 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
mbed_official 121:7f86b4238bec 2508 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 2509 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
mbed_official 121:7f86b4238bec 2510 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
mbed_official 121:7f86b4238bec 2511 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 2512 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
mbed_official 121:7f86b4238bec 2513 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
mbed_official 121:7f86b4238bec 2514 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 2515 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
mbed_official 121:7f86b4238bec 2516 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
mbed_official 121:7f86b4238bec 2517
mbed_official 121:7f86b4238bec 2518 /* The count of CAN_WORD0 */
mbed_official 121:7f86b4238bec 2519 #define CAN_WORD0_COUNT (16U)
mbed_official 121:7f86b4238bec 2520
mbed_official 121:7f86b4238bec 2521 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
mbed_official 121:7f86b4238bec 2522 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
mbed_official 121:7f86b4238bec 2523 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
mbed_official 121:7f86b4238bec 2524 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
mbed_official 121:7f86b4238bec 2525 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 2526 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
mbed_official 121:7f86b4238bec 2527 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
mbed_official 121:7f86b4238bec 2528 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 2529 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
mbed_official 121:7f86b4238bec 2530 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
mbed_official 121:7f86b4238bec 2531 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 2532 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
mbed_official 121:7f86b4238bec 2533 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
mbed_official 121:7f86b4238bec 2534
mbed_official 121:7f86b4238bec 2535 /* The count of CAN_WORD1 */
mbed_official 121:7f86b4238bec 2536 #define CAN_WORD1_COUNT (16U)
mbed_official 121:7f86b4238bec 2537
mbed_official 121:7f86b4238bec 2538 /*! @name RXIMR - Rx Individual Mask Registers */
mbed_official 121:7f86b4238bec 2539 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2540 #define CAN_RXIMR_MI_SHIFT (0U)
mbed_official 121:7f86b4238bec 2541 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
mbed_official 121:7f86b4238bec 2542
mbed_official 121:7f86b4238bec 2543 /* The count of CAN_RXIMR */
mbed_official 121:7f86b4238bec 2544 #define CAN_RXIMR_COUNT (16U)
mbed_official 121:7f86b4238bec 2545
mbed_official 121:7f86b4238bec 2546
mbed_official 121:7f86b4238bec 2547 /*!
mbed_official 121:7f86b4238bec 2548 * @}
mbed_official 121:7f86b4238bec 2549 */ /* end of group CAN_Register_Masks */
mbed_official 121:7f86b4238bec 2550
mbed_official 121:7f86b4238bec 2551
mbed_official 121:7f86b4238bec 2552 /* CAN - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 2553 /** Peripheral CAN0 base address */
mbed_official 121:7f86b4238bec 2554 #define CAN0_BASE (0x40024000u)
mbed_official 121:7f86b4238bec 2555 /** Peripheral CAN0 base pointer */
mbed_official 121:7f86b4238bec 2556 #define CAN0 ((CAN_Type *)CAN0_BASE)
mbed_official 121:7f86b4238bec 2557 /** Array initializer of CAN peripheral base addresses */
mbed_official 121:7f86b4238bec 2558 #define CAN_BASE_ADDRS { CAN0_BASE }
mbed_official 121:7f86b4238bec 2559 /** Array initializer of CAN peripheral base pointers */
mbed_official 121:7f86b4238bec 2560 #define CAN_BASE_PTRS { CAN0 }
mbed_official 121:7f86b4238bec 2561 /** Interrupt vectors for the CAN peripheral type */
mbed_official 121:7f86b4238bec 2562 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
mbed_official 121:7f86b4238bec 2563 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
mbed_official 121:7f86b4238bec 2564 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
mbed_official 121:7f86b4238bec 2565 #define CAN_Error_IRQS { CAN0_Error_IRQn }
mbed_official 121:7f86b4238bec 2566 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
mbed_official 121:7f86b4238bec 2567 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
mbed_official 121:7f86b4238bec 2568
mbed_official 121:7f86b4238bec 2569 /*!
mbed_official 121:7f86b4238bec 2570 * @}
mbed_official 121:7f86b4238bec 2571 */ /* end of group CAN_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 2572
mbed_official 121:7f86b4238bec 2573
mbed_official 121:7f86b4238bec 2574 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 2575 -- CAU Peripheral Access Layer
mbed_official 121:7f86b4238bec 2576 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 2577
mbed_official 121:7f86b4238bec 2578 /*!
mbed_official 121:7f86b4238bec 2579 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
mbed_official 121:7f86b4238bec 2580 * @{
mbed_official 121:7f86b4238bec 2581 */
mbed_official 121:7f86b4238bec 2582
mbed_official 121:7f86b4238bec 2583 /** CAU - Register Layout Typedef */
mbed_official 121:7f86b4238bec 2584 typedef struct {
mbed_official 121:7f86b4238bec 2585 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
mbed_official 121:7f86b4238bec 2586 uint8_t RESERVED_0[2048];
mbed_official 121:7f86b4238bec 2587 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
mbed_official 121:7f86b4238bec 2588 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
mbed_official 121:7f86b4238bec 2589 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
mbed_official 121:7f86b4238bec 2590 uint8_t RESERVED_1[20];
mbed_official 121:7f86b4238bec 2591 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
mbed_official 121:7f86b4238bec 2592 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
mbed_official 121:7f86b4238bec 2593 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
mbed_official 121:7f86b4238bec 2594 uint8_t RESERVED_2[20];
mbed_official 121:7f86b4238bec 2595 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
mbed_official 121:7f86b4238bec 2596 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
mbed_official 121:7f86b4238bec 2597 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
mbed_official 121:7f86b4238bec 2598 uint8_t RESERVED_3[20];
mbed_official 121:7f86b4238bec 2599 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
mbed_official 121:7f86b4238bec 2600 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
mbed_official 121:7f86b4238bec 2601 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
mbed_official 121:7f86b4238bec 2602 uint8_t RESERVED_4[84];
mbed_official 121:7f86b4238bec 2603 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
mbed_official 121:7f86b4238bec 2604 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
mbed_official 121:7f86b4238bec 2605 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
mbed_official 121:7f86b4238bec 2606 uint8_t RESERVED_5[20];
mbed_official 121:7f86b4238bec 2607 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
mbed_official 121:7f86b4238bec 2608 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
mbed_official 121:7f86b4238bec 2609 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
mbed_official 121:7f86b4238bec 2610 uint8_t RESERVED_6[276];
mbed_official 121:7f86b4238bec 2611 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
mbed_official 121:7f86b4238bec 2612 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
mbed_official 121:7f86b4238bec 2613 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
mbed_official 121:7f86b4238bec 2614 uint8_t RESERVED_7[20];
mbed_official 121:7f86b4238bec 2615 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
mbed_official 121:7f86b4238bec 2616 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
mbed_official 121:7f86b4238bec 2617 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
mbed_official 121:7f86b4238bec 2618 } CAU_Type;
mbed_official 121:7f86b4238bec 2619
mbed_official 121:7f86b4238bec 2620 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 2621 -- CAU Register Masks
mbed_official 121:7f86b4238bec 2622 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 2623
mbed_official 121:7f86b4238bec 2624 /*!
mbed_official 121:7f86b4238bec 2625 * @addtogroup CAU_Register_Masks CAU Register Masks
mbed_official 121:7f86b4238bec 2626 * @{
mbed_official 121:7f86b4238bec 2627 */
mbed_official 121:7f86b4238bec 2628
mbed_official 121:7f86b4238bec 2629 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
mbed_official 121:7f86b4238bec 2630 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2631 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2632 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
mbed_official 121:7f86b4238bec 2633 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2634 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
mbed_official 121:7f86b4238bec 2635 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
mbed_official 121:7f86b4238bec 2636 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2637 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
mbed_official 121:7f86b4238bec 2638 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
mbed_official 121:7f86b4238bec 2639 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2640 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2641 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
mbed_official 121:7f86b4238bec 2642 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2643 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
mbed_official 121:7f86b4238bec 2644 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
mbed_official 121:7f86b4238bec 2645 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2646 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
mbed_official 121:7f86b4238bec 2647 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
mbed_official 121:7f86b4238bec 2648 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2649 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
mbed_official 121:7f86b4238bec 2650 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
mbed_official 121:7f86b4238bec 2651 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2652 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
mbed_official 121:7f86b4238bec 2653 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
mbed_official 121:7f86b4238bec 2654 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2655 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
mbed_official 121:7f86b4238bec 2656 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
mbed_official 121:7f86b4238bec 2657 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2658 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
mbed_official 121:7f86b4238bec 2659 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
mbed_official 121:7f86b4238bec 2660 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2661 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
mbed_official 121:7f86b4238bec 2662 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
mbed_official 121:7f86b4238bec 2663 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2664 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
mbed_official 121:7f86b4238bec 2665 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
mbed_official 121:7f86b4238bec 2666 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2667 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
mbed_official 121:7f86b4238bec 2668 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
mbed_official 121:7f86b4238bec 2669 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2670 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
mbed_official 121:7f86b4238bec 2671 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
mbed_official 121:7f86b4238bec 2672 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2673 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
mbed_official 121:7f86b4238bec 2674 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
mbed_official 121:7f86b4238bec 2675 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2676 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
mbed_official 121:7f86b4238bec 2677 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
mbed_official 121:7f86b4238bec 2678
mbed_official 121:7f86b4238bec 2679 /* The count of CAU_DIRECT */
mbed_official 121:7f86b4238bec 2680 #define CAU_DIRECT_COUNT (16U)
mbed_official 121:7f86b4238bec 2681
mbed_official 121:7f86b4238bec 2682 /*! @name LDR_CASR - Status register - Load Register command */
mbed_official 121:7f86b4238bec 2683 #define CAU_LDR_CASR_IC_MASK (0x1U)
mbed_official 121:7f86b4238bec 2684 #define CAU_LDR_CASR_IC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2685 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
mbed_official 121:7f86b4238bec 2686 #define CAU_LDR_CASR_DPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 2687 #define CAU_LDR_CASR_DPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 2688 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
mbed_official 121:7f86b4238bec 2689 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 2690 #define CAU_LDR_CASR_VER_SHIFT (28U)
mbed_official 121:7f86b4238bec 2691 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
mbed_official 121:7f86b4238bec 2692
mbed_official 121:7f86b4238bec 2693 /*! @name LDR_CAA - Accumulator register - Load Register command */
mbed_official 121:7f86b4238bec 2694 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2695 #define CAU_LDR_CAA_ACC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2696 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
mbed_official 121:7f86b4238bec 2697
mbed_official 121:7f86b4238bec 2698 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
mbed_official 121:7f86b4238bec 2699 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2700 #define CAU_LDR_CA_CA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2701 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
mbed_official 121:7f86b4238bec 2702 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2703 #define CAU_LDR_CA_CA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 2704 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
mbed_official 121:7f86b4238bec 2705 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2706 #define CAU_LDR_CA_CA2_SHIFT (0U)
mbed_official 121:7f86b4238bec 2707 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
mbed_official 121:7f86b4238bec 2708 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2709 #define CAU_LDR_CA_CA3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2710 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
mbed_official 121:7f86b4238bec 2711 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2712 #define CAU_LDR_CA_CA4_SHIFT (0U)
mbed_official 121:7f86b4238bec 2713 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
mbed_official 121:7f86b4238bec 2714 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2715 #define CAU_LDR_CA_CA5_SHIFT (0U)
mbed_official 121:7f86b4238bec 2716 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
mbed_official 121:7f86b4238bec 2717 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2718 #define CAU_LDR_CA_CA6_SHIFT (0U)
mbed_official 121:7f86b4238bec 2719 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
mbed_official 121:7f86b4238bec 2720 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2721 #define CAU_LDR_CA_CA7_SHIFT (0U)
mbed_official 121:7f86b4238bec 2722 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
mbed_official 121:7f86b4238bec 2723 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2724 #define CAU_LDR_CA_CA8_SHIFT (0U)
mbed_official 121:7f86b4238bec 2725 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
mbed_official 121:7f86b4238bec 2726
mbed_official 121:7f86b4238bec 2727 /* The count of CAU_LDR_CA */
mbed_official 121:7f86b4238bec 2728 #define CAU_LDR_CA_COUNT (9U)
mbed_official 121:7f86b4238bec 2729
mbed_official 121:7f86b4238bec 2730 /*! @name STR_CASR - Status register - Store Register command */
mbed_official 121:7f86b4238bec 2731 #define CAU_STR_CASR_IC_MASK (0x1U)
mbed_official 121:7f86b4238bec 2732 #define CAU_STR_CASR_IC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2733 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
mbed_official 121:7f86b4238bec 2734 #define CAU_STR_CASR_DPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 2735 #define CAU_STR_CASR_DPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 2736 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
mbed_official 121:7f86b4238bec 2737 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 2738 #define CAU_STR_CASR_VER_SHIFT (28U)
mbed_official 121:7f86b4238bec 2739 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
mbed_official 121:7f86b4238bec 2740
mbed_official 121:7f86b4238bec 2741 /*! @name STR_CAA - Accumulator register - Store Register command */
mbed_official 121:7f86b4238bec 2742 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2743 #define CAU_STR_CAA_ACC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2744 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
mbed_official 121:7f86b4238bec 2745
mbed_official 121:7f86b4238bec 2746 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
mbed_official 121:7f86b4238bec 2747 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2748 #define CAU_STR_CA_CA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2749 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
mbed_official 121:7f86b4238bec 2750 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2751 #define CAU_STR_CA_CA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 2752 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
mbed_official 121:7f86b4238bec 2753 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2754 #define CAU_STR_CA_CA2_SHIFT (0U)
mbed_official 121:7f86b4238bec 2755 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
mbed_official 121:7f86b4238bec 2756 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2757 #define CAU_STR_CA_CA3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2758 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
mbed_official 121:7f86b4238bec 2759 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2760 #define CAU_STR_CA_CA4_SHIFT (0U)
mbed_official 121:7f86b4238bec 2761 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
mbed_official 121:7f86b4238bec 2762 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2763 #define CAU_STR_CA_CA5_SHIFT (0U)
mbed_official 121:7f86b4238bec 2764 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
mbed_official 121:7f86b4238bec 2765 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2766 #define CAU_STR_CA_CA6_SHIFT (0U)
mbed_official 121:7f86b4238bec 2767 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
mbed_official 121:7f86b4238bec 2768 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2769 #define CAU_STR_CA_CA7_SHIFT (0U)
mbed_official 121:7f86b4238bec 2770 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
mbed_official 121:7f86b4238bec 2771 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2772 #define CAU_STR_CA_CA8_SHIFT (0U)
mbed_official 121:7f86b4238bec 2773 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
mbed_official 121:7f86b4238bec 2774
mbed_official 121:7f86b4238bec 2775 /* The count of CAU_STR_CA */
mbed_official 121:7f86b4238bec 2776 #define CAU_STR_CA_COUNT (9U)
mbed_official 121:7f86b4238bec 2777
mbed_official 121:7f86b4238bec 2778 /*! @name ADR_CASR - Status register - Add Register command */
mbed_official 121:7f86b4238bec 2779 #define CAU_ADR_CASR_IC_MASK (0x1U)
mbed_official 121:7f86b4238bec 2780 #define CAU_ADR_CASR_IC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2781 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
mbed_official 121:7f86b4238bec 2782 #define CAU_ADR_CASR_DPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 2783 #define CAU_ADR_CASR_DPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 2784 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
mbed_official 121:7f86b4238bec 2785 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 2786 #define CAU_ADR_CASR_VER_SHIFT (28U)
mbed_official 121:7f86b4238bec 2787 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
mbed_official 121:7f86b4238bec 2788
mbed_official 121:7f86b4238bec 2789 /*! @name ADR_CAA - Accumulator register - Add to register command */
mbed_official 121:7f86b4238bec 2790 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2791 #define CAU_ADR_CAA_ACC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2792 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
mbed_official 121:7f86b4238bec 2793
mbed_official 121:7f86b4238bec 2794 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
mbed_official 121:7f86b4238bec 2795 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2796 #define CAU_ADR_CA_CA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2797 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
mbed_official 121:7f86b4238bec 2798 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2799 #define CAU_ADR_CA_CA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 2800 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
mbed_official 121:7f86b4238bec 2801 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2802 #define CAU_ADR_CA_CA2_SHIFT (0U)
mbed_official 121:7f86b4238bec 2803 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
mbed_official 121:7f86b4238bec 2804 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2805 #define CAU_ADR_CA_CA3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2806 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
mbed_official 121:7f86b4238bec 2807 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2808 #define CAU_ADR_CA_CA4_SHIFT (0U)
mbed_official 121:7f86b4238bec 2809 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
mbed_official 121:7f86b4238bec 2810 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2811 #define CAU_ADR_CA_CA5_SHIFT (0U)
mbed_official 121:7f86b4238bec 2812 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
mbed_official 121:7f86b4238bec 2813 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2814 #define CAU_ADR_CA_CA6_SHIFT (0U)
mbed_official 121:7f86b4238bec 2815 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
mbed_official 121:7f86b4238bec 2816 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2817 #define CAU_ADR_CA_CA7_SHIFT (0U)
mbed_official 121:7f86b4238bec 2818 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
mbed_official 121:7f86b4238bec 2819 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2820 #define CAU_ADR_CA_CA8_SHIFT (0U)
mbed_official 121:7f86b4238bec 2821 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
mbed_official 121:7f86b4238bec 2822
mbed_official 121:7f86b4238bec 2823 /* The count of CAU_ADR_CA */
mbed_official 121:7f86b4238bec 2824 #define CAU_ADR_CA_COUNT (9U)
mbed_official 121:7f86b4238bec 2825
mbed_official 121:7f86b4238bec 2826 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
mbed_official 121:7f86b4238bec 2827 #define CAU_RADR_CASR_IC_MASK (0x1U)
mbed_official 121:7f86b4238bec 2828 #define CAU_RADR_CASR_IC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2829 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
mbed_official 121:7f86b4238bec 2830 #define CAU_RADR_CASR_DPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 2831 #define CAU_RADR_CASR_DPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 2832 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
mbed_official 121:7f86b4238bec 2833 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 2834 #define CAU_RADR_CASR_VER_SHIFT (28U)
mbed_official 121:7f86b4238bec 2835 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
mbed_official 121:7f86b4238bec 2836
mbed_official 121:7f86b4238bec 2837 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
mbed_official 121:7f86b4238bec 2838 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2839 #define CAU_RADR_CAA_ACC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2840 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
mbed_official 121:7f86b4238bec 2841
mbed_official 121:7f86b4238bec 2842 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
mbed_official 121:7f86b4238bec 2843 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2844 #define CAU_RADR_CA_CA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2845 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
mbed_official 121:7f86b4238bec 2846 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2847 #define CAU_RADR_CA_CA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 2848 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
mbed_official 121:7f86b4238bec 2849 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2850 #define CAU_RADR_CA_CA2_SHIFT (0U)
mbed_official 121:7f86b4238bec 2851 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
mbed_official 121:7f86b4238bec 2852 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2853 #define CAU_RADR_CA_CA3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2854 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
mbed_official 121:7f86b4238bec 2855 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2856 #define CAU_RADR_CA_CA4_SHIFT (0U)
mbed_official 121:7f86b4238bec 2857 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
mbed_official 121:7f86b4238bec 2858 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2859 #define CAU_RADR_CA_CA5_SHIFT (0U)
mbed_official 121:7f86b4238bec 2860 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
mbed_official 121:7f86b4238bec 2861 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2862 #define CAU_RADR_CA_CA6_SHIFT (0U)
mbed_official 121:7f86b4238bec 2863 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
mbed_official 121:7f86b4238bec 2864 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2865 #define CAU_RADR_CA_CA7_SHIFT (0U)
mbed_official 121:7f86b4238bec 2866 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
mbed_official 121:7f86b4238bec 2867 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2868 #define CAU_RADR_CA_CA8_SHIFT (0U)
mbed_official 121:7f86b4238bec 2869 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
mbed_official 121:7f86b4238bec 2870
mbed_official 121:7f86b4238bec 2871 /* The count of CAU_RADR_CA */
mbed_official 121:7f86b4238bec 2872 #define CAU_RADR_CA_COUNT (9U)
mbed_official 121:7f86b4238bec 2873
mbed_official 121:7f86b4238bec 2874 /*! @name XOR_CASR - Status register - Exclusive Or command */
mbed_official 121:7f86b4238bec 2875 #define CAU_XOR_CASR_IC_MASK (0x1U)
mbed_official 121:7f86b4238bec 2876 #define CAU_XOR_CASR_IC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2877 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
mbed_official 121:7f86b4238bec 2878 #define CAU_XOR_CASR_DPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 2879 #define CAU_XOR_CASR_DPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 2880 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
mbed_official 121:7f86b4238bec 2881 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 2882 #define CAU_XOR_CASR_VER_SHIFT (28U)
mbed_official 121:7f86b4238bec 2883 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
mbed_official 121:7f86b4238bec 2884
mbed_official 121:7f86b4238bec 2885 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
mbed_official 121:7f86b4238bec 2886 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2887 #define CAU_XOR_CAA_ACC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2888 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
mbed_official 121:7f86b4238bec 2889
mbed_official 121:7f86b4238bec 2890 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
mbed_official 121:7f86b4238bec 2891 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2892 #define CAU_XOR_CA_CA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2893 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
mbed_official 121:7f86b4238bec 2894 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2895 #define CAU_XOR_CA_CA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 2896 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
mbed_official 121:7f86b4238bec 2897 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2898 #define CAU_XOR_CA_CA2_SHIFT (0U)
mbed_official 121:7f86b4238bec 2899 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
mbed_official 121:7f86b4238bec 2900 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2901 #define CAU_XOR_CA_CA3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2902 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
mbed_official 121:7f86b4238bec 2903 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2904 #define CAU_XOR_CA_CA4_SHIFT (0U)
mbed_official 121:7f86b4238bec 2905 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
mbed_official 121:7f86b4238bec 2906 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2907 #define CAU_XOR_CA_CA5_SHIFT (0U)
mbed_official 121:7f86b4238bec 2908 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
mbed_official 121:7f86b4238bec 2909 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2910 #define CAU_XOR_CA_CA6_SHIFT (0U)
mbed_official 121:7f86b4238bec 2911 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
mbed_official 121:7f86b4238bec 2912 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2913 #define CAU_XOR_CA_CA7_SHIFT (0U)
mbed_official 121:7f86b4238bec 2914 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
mbed_official 121:7f86b4238bec 2915 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2916 #define CAU_XOR_CA_CA8_SHIFT (0U)
mbed_official 121:7f86b4238bec 2917 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
mbed_official 121:7f86b4238bec 2918
mbed_official 121:7f86b4238bec 2919 /* The count of CAU_XOR_CA */
mbed_official 121:7f86b4238bec 2920 #define CAU_XOR_CA_COUNT (9U)
mbed_official 121:7f86b4238bec 2921
mbed_official 121:7f86b4238bec 2922 /*! @name ROTL_CASR - Status register - Rotate Left command */
mbed_official 121:7f86b4238bec 2923 #define CAU_ROTL_CASR_IC_MASK (0x1U)
mbed_official 121:7f86b4238bec 2924 #define CAU_ROTL_CASR_IC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2925 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
mbed_official 121:7f86b4238bec 2926 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 2927 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 2928 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
mbed_official 121:7f86b4238bec 2929 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 2930 #define CAU_ROTL_CASR_VER_SHIFT (28U)
mbed_official 121:7f86b4238bec 2931 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
mbed_official 121:7f86b4238bec 2932
mbed_official 121:7f86b4238bec 2933 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
mbed_official 121:7f86b4238bec 2934 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2935 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2936 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
mbed_official 121:7f86b4238bec 2937
mbed_official 121:7f86b4238bec 2938 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
mbed_official 121:7f86b4238bec 2939 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2940 #define CAU_ROTL_CA_CA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2941 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
mbed_official 121:7f86b4238bec 2942 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2943 #define CAU_ROTL_CA_CA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 2944 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
mbed_official 121:7f86b4238bec 2945 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2946 #define CAU_ROTL_CA_CA2_SHIFT (0U)
mbed_official 121:7f86b4238bec 2947 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
mbed_official 121:7f86b4238bec 2948 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2949 #define CAU_ROTL_CA_CA3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2950 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
mbed_official 121:7f86b4238bec 2951 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2952 #define CAU_ROTL_CA_CA4_SHIFT (0U)
mbed_official 121:7f86b4238bec 2953 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
mbed_official 121:7f86b4238bec 2954 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2955 #define CAU_ROTL_CA_CA5_SHIFT (0U)
mbed_official 121:7f86b4238bec 2956 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
mbed_official 121:7f86b4238bec 2957 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2958 #define CAU_ROTL_CA_CA6_SHIFT (0U)
mbed_official 121:7f86b4238bec 2959 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
mbed_official 121:7f86b4238bec 2960 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2961 #define CAU_ROTL_CA_CA7_SHIFT (0U)
mbed_official 121:7f86b4238bec 2962 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
mbed_official 121:7f86b4238bec 2963 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2964 #define CAU_ROTL_CA_CA8_SHIFT (0U)
mbed_official 121:7f86b4238bec 2965 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
mbed_official 121:7f86b4238bec 2966
mbed_official 121:7f86b4238bec 2967 /* The count of CAU_ROTL_CA */
mbed_official 121:7f86b4238bec 2968 #define CAU_ROTL_CA_COUNT (9U)
mbed_official 121:7f86b4238bec 2969
mbed_official 121:7f86b4238bec 2970 /*! @name AESC_CASR - Status register - AES Column Operation command */
mbed_official 121:7f86b4238bec 2971 #define CAU_AESC_CASR_IC_MASK (0x1U)
mbed_official 121:7f86b4238bec 2972 #define CAU_AESC_CASR_IC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2973 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
mbed_official 121:7f86b4238bec 2974 #define CAU_AESC_CASR_DPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 2975 #define CAU_AESC_CASR_DPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 2976 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
mbed_official 121:7f86b4238bec 2977 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 2978 #define CAU_AESC_CASR_VER_SHIFT (28U)
mbed_official 121:7f86b4238bec 2979 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
mbed_official 121:7f86b4238bec 2980
mbed_official 121:7f86b4238bec 2981 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
mbed_official 121:7f86b4238bec 2982 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2983 #define CAU_AESC_CAA_ACC_SHIFT (0U)
mbed_official 121:7f86b4238bec 2984 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
mbed_official 121:7f86b4238bec 2985
mbed_official 121:7f86b4238bec 2986 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
mbed_official 121:7f86b4238bec 2987 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2988 #define CAU_AESC_CA_CA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 2989 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
mbed_official 121:7f86b4238bec 2990 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2991 #define CAU_AESC_CA_CA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 2992 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
mbed_official 121:7f86b4238bec 2993 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2994 #define CAU_AESC_CA_CA2_SHIFT (0U)
mbed_official 121:7f86b4238bec 2995 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
mbed_official 121:7f86b4238bec 2996 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 2997 #define CAU_AESC_CA_CA3_SHIFT (0U)
mbed_official 121:7f86b4238bec 2998 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
mbed_official 121:7f86b4238bec 2999 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3000 #define CAU_AESC_CA_CA4_SHIFT (0U)
mbed_official 121:7f86b4238bec 3001 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
mbed_official 121:7f86b4238bec 3002 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3003 #define CAU_AESC_CA_CA5_SHIFT (0U)
mbed_official 121:7f86b4238bec 3004 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
mbed_official 121:7f86b4238bec 3005 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3006 #define CAU_AESC_CA_CA6_SHIFT (0U)
mbed_official 121:7f86b4238bec 3007 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
mbed_official 121:7f86b4238bec 3008 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3009 #define CAU_AESC_CA_CA7_SHIFT (0U)
mbed_official 121:7f86b4238bec 3010 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
mbed_official 121:7f86b4238bec 3011 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3012 #define CAU_AESC_CA_CA8_SHIFT (0U)
mbed_official 121:7f86b4238bec 3013 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
mbed_official 121:7f86b4238bec 3014
mbed_official 121:7f86b4238bec 3015 /* The count of CAU_AESC_CA */
mbed_official 121:7f86b4238bec 3016 #define CAU_AESC_CA_COUNT (9U)
mbed_official 121:7f86b4238bec 3017
mbed_official 121:7f86b4238bec 3018 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
mbed_official 121:7f86b4238bec 3019 #define CAU_AESIC_CASR_IC_MASK (0x1U)
mbed_official 121:7f86b4238bec 3020 #define CAU_AESIC_CASR_IC_SHIFT (0U)
mbed_official 121:7f86b4238bec 3021 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
mbed_official 121:7f86b4238bec 3022 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 3023 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 3024 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
mbed_official 121:7f86b4238bec 3025 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 3026 #define CAU_AESIC_CASR_VER_SHIFT (28U)
mbed_official 121:7f86b4238bec 3027 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
mbed_official 121:7f86b4238bec 3028
mbed_official 121:7f86b4238bec 3029 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
mbed_official 121:7f86b4238bec 3030 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3031 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
mbed_official 121:7f86b4238bec 3032 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
mbed_official 121:7f86b4238bec 3033
mbed_official 121:7f86b4238bec 3034 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
mbed_official 121:7f86b4238bec 3035 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3036 #define CAU_AESIC_CA_CA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 3037 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
mbed_official 121:7f86b4238bec 3038 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3039 #define CAU_AESIC_CA_CA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 3040 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
mbed_official 121:7f86b4238bec 3041 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3042 #define CAU_AESIC_CA_CA2_SHIFT (0U)
mbed_official 121:7f86b4238bec 3043 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
mbed_official 121:7f86b4238bec 3044 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3045 #define CAU_AESIC_CA_CA3_SHIFT (0U)
mbed_official 121:7f86b4238bec 3046 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
mbed_official 121:7f86b4238bec 3047 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3048 #define CAU_AESIC_CA_CA4_SHIFT (0U)
mbed_official 121:7f86b4238bec 3049 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
mbed_official 121:7f86b4238bec 3050 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3051 #define CAU_AESIC_CA_CA5_SHIFT (0U)
mbed_official 121:7f86b4238bec 3052 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
mbed_official 121:7f86b4238bec 3053 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3054 #define CAU_AESIC_CA_CA6_SHIFT (0U)
mbed_official 121:7f86b4238bec 3055 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
mbed_official 121:7f86b4238bec 3056 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3057 #define CAU_AESIC_CA_CA7_SHIFT (0U)
mbed_official 121:7f86b4238bec 3058 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
mbed_official 121:7f86b4238bec 3059 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 3060 #define CAU_AESIC_CA_CA8_SHIFT (0U)
mbed_official 121:7f86b4238bec 3061 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
mbed_official 121:7f86b4238bec 3062
mbed_official 121:7f86b4238bec 3063 /* The count of CAU_AESIC_CA */
mbed_official 121:7f86b4238bec 3064 #define CAU_AESIC_CA_COUNT (9U)
mbed_official 121:7f86b4238bec 3065
mbed_official 121:7f86b4238bec 3066
mbed_official 121:7f86b4238bec 3067 /*!
mbed_official 121:7f86b4238bec 3068 * @}
mbed_official 121:7f86b4238bec 3069 */ /* end of group CAU_Register_Masks */
mbed_official 121:7f86b4238bec 3070
mbed_official 121:7f86b4238bec 3071
mbed_official 121:7f86b4238bec 3072 /* CAU - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 3073 /** Peripheral CAU base address */
mbed_official 121:7f86b4238bec 3074 #define CAU_BASE (0xE0081000u)
mbed_official 121:7f86b4238bec 3075 /** Peripheral CAU base pointer */
mbed_official 121:7f86b4238bec 3076 #define CAU ((CAU_Type *)CAU_BASE)
mbed_official 121:7f86b4238bec 3077 /** Array initializer of CAU peripheral base addresses */
mbed_official 121:7f86b4238bec 3078 #define CAU_BASE_ADDRS { CAU_BASE }
mbed_official 121:7f86b4238bec 3079 /** Array initializer of CAU peripheral base pointers */
mbed_official 121:7f86b4238bec 3080 #define CAU_BASE_PTRS { CAU }
mbed_official 121:7f86b4238bec 3081
mbed_official 121:7f86b4238bec 3082 /*!
mbed_official 121:7f86b4238bec 3083 * @}
mbed_official 121:7f86b4238bec 3084 */ /* end of group CAU_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 3085
mbed_official 121:7f86b4238bec 3086
mbed_official 121:7f86b4238bec 3087 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3088 -- CMP Peripheral Access Layer
mbed_official 121:7f86b4238bec 3089 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3090
mbed_official 121:7f86b4238bec 3091 /*!
mbed_official 121:7f86b4238bec 3092 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mbed_official 121:7f86b4238bec 3093 * @{
mbed_official 121:7f86b4238bec 3094 */
mbed_official 121:7f86b4238bec 3095
mbed_official 121:7f86b4238bec 3096 /** CMP - Register Layout Typedef */
mbed_official 121:7f86b4238bec 3097 typedef struct {
mbed_official 121:7f86b4238bec 3098 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mbed_official 121:7f86b4238bec 3099 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mbed_official 121:7f86b4238bec 3100 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mbed_official 121:7f86b4238bec 3101 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mbed_official 121:7f86b4238bec 3102 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 3103 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mbed_official 121:7f86b4238bec 3104 } CMP_Type;
mbed_official 121:7f86b4238bec 3105
mbed_official 121:7f86b4238bec 3106 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3107 -- CMP Register Masks
mbed_official 121:7f86b4238bec 3108 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3109
mbed_official 121:7f86b4238bec 3110 /*!
mbed_official 121:7f86b4238bec 3111 * @addtogroup CMP_Register_Masks CMP Register Masks
mbed_official 121:7f86b4238bec 3112 * @{
mbed_official 121:7f86b4238bec 3113 */
mbed_official 121:7f86b4238bec 3114
mbed_official 121:7f86b4238bec 3115 /*! @name CR0 - CMP Control Register 0 */
mbed_official 121:7f86b4238bec 3116 #define CMP_CR0_HYSTCTR_MASK (0x3U)
mbed_official 121:7f86b4238bec 3117 #define CMP_CR0_HYSTCTR_SHIFT (0U)
mbed_official 121:7f86b4238bec 3118 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
mbed_official 121:7f86b4238bec 3119 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
mbed_official 121:7f86b4238bec 3120 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
mbed_official 121:7f86b4238bec 3121 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
mbed_official 121:7f86b4238bec 3122
mbed_official 121:7f86b4238bec 3123 /*! @name CR1 - CMP Control Register 1 */
mbed_official 121:7f86b4238bec 3124 #define CMP_CR1_EN_MASK (0x1U)
mbed_official 121:7f86b4238bec 3125 #define CMP_CR1_EN_SHIFT (0U)
mbed_official 121:7f86b4238bec 3126 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
mbed_official 121:7f86b4238bec 3127 #define CMP_CR1_OPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 3128 #define CMP_CR1_OPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 3129 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
mbed_official 121:7f86b4238bec 3130 #define CMP_CR1_COS_MASK (0x4U)
mbed_official 121:7f86b4238bec 3131 #define CMP_CR1_COS_SHIFT (2U)
mbed_official 121:7f86b4238bec 3132 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
mbed_official 121:7f86b4238bec 3133 #define CMP_CR1_INV_MASK (0x8U)
mbed_official 121:7f86b4238bec 3134 #define CMP_CR1_INV_SHIFT (3U)
mbed_official 121:7f86b4238bec 3135 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
mbed_official 121:7f86b4238bec 3136 #define CMP_CR1_PMODE_MASK (0x10U)
mbed_official 121:7f86b4238bec 3137 #define CMP_CR1_PMODE_SHIFT (4U)
mbed_official 121:7f86b4238bec 3138 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
mbed_official 121:7f86b4238bec 3139 #define CMP_CR1_WE_MASK (0x40U)
mbed_official 121:7f86b4238bec 3140 #define CMP_CR1_WE_SHIFT (6U)
mbed_official 121:7f86b4238bec 3141 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
mbed_official 121:7f86b4238bec 3142 #define CMP_CR1_SE_MASK (0x80U)
mbed_official 121:7f86b4238bec 3143 #define CMP_CR1_SE_SHIFT (7U)
mbed_official 121:7f86b4238bec 3144 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
mbed_official 121:7f86b4238bec 3145
mbed_official 121:7f86b4238bec 3146 /*! @name FPR - CMP Filter Period Register */
mbed_official 121:7f86b4238bec 3147 #define CMP_FPR_FILT_PER_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3148 #define CMP_FPR_FILT_PER_SHIFT (0U)
mbed_official 121:7f86b4238bec 3149 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
mbed_official 121:7f86b4238bec 3150
mbed_official 121:7f86b4238bec 3151 /*! @name SCR - CMP Status and Control Register */
mbed_official 121:7f86b4238bec 3152 #define CMP_SCR_COUT_MASK (0x1U)
mbed_official 121:7f86b4238bec 3153 #define CMP_SCR_COUT_SHIFT (0U)
mbed_official 121:7f86b4238bec 3154 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
mbed_official 121:7f86b4238bec 3155 #define CMP_SCR_CFF_MASK (0x2U)
mbed_official 121:7f86b4238bec 3156 #define CMP_SCR_CFF_SHIFT (1U)
mbed_official 121:7f86b4238bec 3157 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
mbed_official 121:7f86b4238bec 3158 #define CMP_SCR_CFR_MASK (0x4U)
mbed_official 121:7f86b4238bec 3159 #define CMP_SCR_CFR_SHIFT (2U)
mbed_official 121:7f86b4238bec 3160 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
mbed_official 121:7f86b4238bec 3161 #define CMP_SCR_IEF_MASK (0x8U)
mbed_official 121:7f86b4238bec 3162 #define CMP_SCR_IEF_SHIFT (3U)
mbed_official 121:7f86b4238bec 3163 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
mbed_official 121:7f86b4238bec 3164 #define CMP_SCR_IER_MASK (0x10U)
mbed_official 121:7f86b4238bec 3165 #define CMP_SCR_IER_SHIFT (4U)
mbed_official 121:7f86b4238bec 3166 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
mbed_official 121:7f86b4238bec 3167 #define CMP_SCR_DMAEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 3168 #define CMP_SCR_DMAEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 3169 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
mbed_official 121:7f86b4238bec 3170
mbed_official 121:7f86b4238bec 3171 /*! @name DACCR - DAC Control Register */
mbed_official 121:7f86b4238bec 3172 #define CMP_DACCR_VOSEL_MASK (0x3FU)
mbed_official 121:7f86b4238bec 3173 #define CMP_DACCR_VOSEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3174 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
mbed_official 121:7f86b4238bec 3175 #define CMP_DACCR_VRSEL_MASK (0x40U)
mbed_official 121:7f86b4238bec 3176 #define CMP_DACCR_VRSEL_SHIFT (6U)
mbed_official 121:7f86b4238bec 3177 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
mbed_official 121:7f86b4238bec 3178 #define CMP_DACCR_DACEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 3179 #define CMP_DACCR_DACEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 3180 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
mbed_official 121:7f86b4238bec 3181
mbed_official 121:7f86b4238bec 3182 /*! @name MUXCR - MUX Control Register */
mbed_official 121:7f86b4238bec 3183 #define CMP_MUXCR_MSEL_MASK (0x7U)
mbed_official 121:7f86b4238bec 3184 #define CMP_MUXCR_MSEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3185 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
mbed_official 121:7f86b4238bec 3186 #define CMP_MUXCR_PSEL_MASK (0x38U)
mbed_official 121:7f86b4238bec 3187 #define CMP_MUXCR_PSEL_SHIFT (3U)
mbed_official 121:7f86b4238bec 3188 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
mbed_official 121:7f86b4238bec 3189 #define CMP_MUXCR_PSTM_MASK (0x80U)
mbed_official 121:7f86b4238bec 3190 #define CMP_MUXCR_PSTM_SHIFT (7U)
mbed_official 121:7f86b4238bec 3191 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
mbed_official 121:7f86b4238bec 3192
mbed_official 121:7f86b4238bec 3193
mbed_official 121:7f86b4238bec 3194 /*!
mbed_official 121:7f86b4238bec 3195 * @}
mbed_official 121:7f86b4238bec 3196 */ /* end of group CMP_Register_Masks */
mbed_official 121:7f86b4238bec 3197
mbed_official 121:7f86b4238bec 3198
mbed_official 121:7f86b4238bec 3199 /* CMP - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 3200 /** Peripheral CMP0 base address */
mbed_official 121:7f86b4238bec 3201 #define CMP0_BASE (0x40073000u)
mbed_official 121:7f86b4238bec 3202 /** Peripheral CMP0 base pointer */
mbed_official 121:7f86b4238bec 3203 #define CMP0 ((CMP_Type *)CMP0_BASE)
mbed_official 121:7f86b4238bec 3204 /** Peripheral CMP1 base address */
mbed_official 121:7f86b4238bec 3205 #define CMP1_BASE (0x40073008u)
mbed_official 121:7f86b4238bec 3206 /** Peripheral CMP1 base pointer */
mbed_official 121:7f86b4238bec 3207 #define CMP1 ((CMP_Type *)CMP1_BASE)
mbed_official 121:7f86b4238bec 3208 /** Peripheral CMP2 base address */
mbed_official 121:7f86b4238bec 3209 #define CMP2_BASE (0x40073010u)
mbed_official 121:7f86b4238bec 3210 /** Peripheral CMP2 base pointer */
mbed_official 121:7f86b4238bec 3211 #define CMP2 ((CMP_Type *)CMP2_BASE)
mbed_official 121:7f86b4238bec 3212 /** Array initializer of CMP peripheral base addresses */
mbed_official 121:7f86b4238bec 3213 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
mbed_official 121:7f86b4238bec 3214 /** Array initializer of CMP peripheral base pointers */
mbed_official 121:7f86b4238bec 3215 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
mbed_official 121:7f86b4238bec 3216 /** Interrupt vectors for the CMP peripheral type */
mbed_official 121:7f86b4238bec 3217 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
mbed_official 121:7f86b4238bec 3218
mbed_official 121:7f86b4238bec 3219 /*!
mbed_official 121:7f86b4238bec 3220 * @}
mbed_official 121:7f86b4238bec 3221 */ /* end of group CMP_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 3222
mbed_official 121:7f86b4238bec 3223
mbed_official 121:7f86b4238bec 3224 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3225 -- CMT Peripheral Access Layer
mbed_official 121:7f86b4238bec 3226 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3227
mbed_official 121:7f86b4238bec 3228 /*!
mbed_official 121:7f86b4238bec 3229 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
mbed_official 121:7f86b4238bec 3230 * @{
mbed_official 121:7f86b4238bec 3231 */
mbed_official 121:7f86b4238bec 3232
mbed_official 121:7f86b4238bec 3233 /** CMT - Register Layout Typedef */
mbed_official 121:7f86b4238bec 3234 typedef struct {
mbed_official 121:7f86b4238bec 3235 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
mbed_official 121:7f86b4238bec 3236 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
mbed_official 121:7f86b4238bec 3237 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
mbed_official 121:7f86b4238bec 3238 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
mbed_official 121:7f86b4238bec 3239 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 3240 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
mbed_official 121:7f86b4238bec 3241 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
mbed_official 121:7f86b4238bec 3242 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
mbed_official 121:7f86b4238bec 3243 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
mbed_official 121:7f86b4238bec 3244 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
mbed_official 121:7f86b4238bec 3245 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
mbed_official 121:7f86b4238bec 3246 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
mbed_official 121:7f86b4238bec 3247 } CMT_Type;
mbed_official 121:7f86b4238bec 3248
mbed_official 121:7f86b4238bec 3249 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3250 -- CMT Register Masks
mbed_official 121:7f86b4238bec 3251 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3252
mbed_official 121:7f86b4238bec 3253 /*!
mbed_official 121:7f86b4238bec 3254 * @addtogroup CMT_Register_Masks CMT Register Masks
mbed_official 121:7f86b4238bec 3255 * @{
mbed_official 121:7f86b4238bec 3256 */
mbed_official 121:7f86b4238bec 3257
mbed_official 121:7f86b4238bec 3258 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
mbed_official 121:7f86b4238bec 3259 #define CMT_CGH1_PH_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3260 #define CMT_CGH1_PH_SHIFT (0U)
mbed_official 121:7f86b4238bec 3261 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
mbed_official 121:7f86b4238bec 3262
mbed_official 121:7f86b4238bec 3263 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
mbed_official 121:7f86b4238bec 3264 #define CMT_CGL1_PL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3265 #define CMT_CGL1_PL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3266 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
mbed_official 121:7f86b4238bec 3267
mbed_official 121:7f86b4238bec 3268 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
mbed_official 121:7f86b4238bec 3269 #define CMT_CGH2_SH_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3270 #define CMT_CGH2_SH_SHIFT (0U)
mbed_official 121:7f86b4238bec 3271 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
mbed_official 121:7f86b4238bec 3272
mbed_official 121:7f86b4238bec 3273 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
mbed_official 121:7f86b4238bec 3274 #define CMT_CGL2_SL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3275 #define CMT_CGL2_SL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3276 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
mbed_official 121:7f86b4238bec 3277
mbed_official 121:7f86b4238bec 3278 /*! @name OC - CMT Output Control Register */
mbed_official 121:7f86b4238bec 3279 #define CMT_OC_IROPEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 3280 #define CMT_OC_IROPEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 3281 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
mbed_official 121:7f86b4238bec 3282 #define CMT_OC_CMTPOL_MASK (0x40U)
mbed_official 121:7f86b4238bec 3283 #define CMT_OC_CMTPOL_SHIFT (6U)
mbed_official 121:7f86b4238bec 3284 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
mbed_official 121:7f86b4238bec 3285 #define CMT_OC_IROL_MASK (0x80U)
mbed_official 121:7f86b4238bec 3286 #define CMT_OC_IROL_SHIFT (7U)
mbed_official 121:7f86b4238bec 3287 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
mbed_official 121:7f86b4238bec 3288
mbed_official 121:7f86b4238bec 3289 /*! @name MSC - CMT Modulator Status and Control Register */
mbed_official 121:7f86b4238bec 3290 #define CMT_MSC_MCGEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 3291 #define CMT_MSC_MCGEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 3292 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
mbed_official 121:7f86b4238bec 3293 #define CMT_MSC_EOCIE_MASK (0x2U)
mbed_official 121:7f86b4238bec 3294 #define CMT_MSC_EOCIE_SHIFT (1U)
mbed_official 121:7f86b4238bec 3295 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
mbed_official 121:7f86b4238bec 3296 #define CMT_MSC_FSK_MASK (0x4U)
mbed_official 121:7f86b4238bec 3297 #define CMT_MSC_FSK_SHIFT (2U)
mbed_official 121:7f86b4238bec 3298 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
mbed_official 121:7f86b4238bec 3299 #define CMT_MSC_BASE_MASK (0x8U)
mbed_official 121:7f86b4238bec 3300 #define CMT_MSC_BASE_SHIFT (3U)
mbed_official 121:7f86b4238bec 3301 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
mbed_official 121:7f86b4238bec 3302 #define CMT_MSC_EXSPC_MASK (0x10U)
mbed_official 121:7f86b4238bec 3303 #define CMT_MSC_EXSPC_SHIFT (4U)
mbed_official 121:7f86b4238bec 3304 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
mbed_official 121:7f86b4238bec 3305 #define CMT_MSC_CMTDIV_MASK (0x60U)
mbed_official 121:7f86b4238bec 3306 #define CMT_MSC_CMTDIV_SHIFT (5U)
mbed_official 121:7f86b4238bec 3307 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
mbed_official 121:7f86b4238bec 3308 #define CMT_MSC_EOCF_MASK (0x80U)
mbed_official 121:7f86b4238bec 3309 #define CMT_MSC_EOCF_SHIFT (7U)
mbed_official 121:7f86b4238bec 3310 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
mbed_official 121:7f86b4238bec 3311
mbed_official 121:7f86b4238bec 3312 /*! @name CMD1 - CMT Modulator Data Register Mark High */
mbed_official 121:7f86b4238bec 3313 #define CMT_CMD1_MB_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3314 #define CMT_CMD1_MB_SHIFT (0U)
mbed_official 121:7f86b4238bec 3315 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
mbed_official 121:7f86b4238bec 3316
mbed_official 121:7f86b4238bec 3317 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
mbed_official 121:7f86b4238bec 3318 #define CMT_CMD2_MB_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3319 #define CMT_CMD2_MB_SHIFT (0U)
mbed_official 121:7f86b4238bec 3320 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
mbed_official 121:7f86b4238bec 3321
mbed_official 121:7f86b4238bec 3322 /*! @name CMD3 - CMT Modulator Data Register Space High */
mbed_official 121:7f86b4238bec 3323 #define CMT_CMD3_SB_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3324 #define CMT_CMD3_SB_SHIFT (0U)
mbed_official 121:7f86b4238bec 3325 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
mbed_official 121:7f86b4238bec 3326
mbed_official 121:7f86b4238bec 3327 /*! @name CMD4 - CMT Modulator Data Register Space Low */
mbed_official 121:7f86b4238bec 3328 #define CMT_CMD4_SB_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3329 #define CMT_CMD4_SB_SHIFT (0U)
mbed_official 121:7f86b4238bec 3330 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
mbed_official 121:7f86b4238bec 3331
mbed_official 121:7f86b4238bec 3332 /*! @name PPS - CMT Primary Prescaler Register */
mbed_official 121:7f86b4238bec 3333 #define CMT_PPS_PPSDIV_MASK (0xFU)
mbed_official 121:7f86b4238bec 3334 #define CMT_PPS_PPSDIV_SHIFT (0U)
mbed_official 121:7f86b4238bec 3335 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
mbed_official 121:7f86b4238bec 3336
mbed_official 121:7f86b4238bec 3337 /*! @name DMA - CMT Direct Memory Access Register */
mbed_official 121:7f86b4238bec 3338 #define CMT_DMA_DMA_MASK (0x1U)
mbed_official 121:7f86b4238bec 3339 #define CMT_DMA_DMA_SHIFT (0U)
mbed_official 121:7f86b4238bec 3340 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
mbed_official 121:7f86b4238bec 3341
mbed_official 121:7f86b4238bec 3342
mbed_official 121:7f86b4238bec 3343 /*!
mbed_official 121:7f86b4238bec 3344 * @}
mbed_official 121:7f86b4238bec 3345 */ /* end of group CMT_Register_Masks */
mbed_official 121:7f86b4238bec 3346
mbed_official 121:7f86b4238bec 3347
mbed_official 121:7f86b4238bec 3348 /* CMT - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 3349 /** Peripheral CMT base address */
mbed_official 121:7f86b4238bec 3350 #define CMT_BASE (0x40062000u)
mbed_official 121:7f86b4238bec 3351 /** Peripheral CMT base pointer */
mbed_official 121:7f86b4238bec 3352 #define CMT ((CMT_Type *)CMT_BASE)
mbed_official 121:7f86b4238bec 3353 /** Array initializer of CMT peripheral base addresses */
mbed_official 121:7f86b4238bec 3354 #define CMT_BASE_ADDRS { CMT_BASE }
mbed_official 121:7f86b4238bec 3355 /** Array initializer of CMT peripheral base pointers */
mbed_official 121:7f86b4238bec 3356 #define CMT_BASE_PTRS { CMT }
mbed_official 121:7f86b4238bec 3357 /** Interrupt vectors for the CMT peripheral type */
mbed_official 121:7f86b4238bec 3358 #define CMT_IRQS { CMT_IRQn }
mbed_official 121:7f86b4238bec 3359
mbed_official 121:7f86b4238bec 3360 /*!
mbed_official 121:7f86b4238bec 3361 * @}
mbed_official 121:7f86b4238bec 3362 */ /* end of group CMT_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 3363
mbed_official 121:7f86b4238bec 3364
mbed_official 121:7f86b4238bec 3365 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3366 -- CRC Peripheral Access Layer
mbed_official 121:7f86b4238bec 3367 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3368
mbed_official 121:7f86b4238bec 3369 /*!
mbed_official 121:7f86b4238bec 3370 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
mbed_official 121:7f86b4238bec 3371 * @{
mbed_official 121:7f86b4238bec 3372 */
mbed_official 121:7f86b4238bec 3373
mbed_official 121:7f86b4238bec 3374 /** CRC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 3375 typedef struct {
mbed_official 121:7f86b4238bec 3376 union { /* offset: 0x0 */
mbed_official 121:7f86b4238bec 3377 struct { /* offset: 0x0 */
mbed_official 121:7f86b4238bec 3378 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
mbed_official 121:7f86b4238bec 3379 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
mbed_official 121:7f86b4238bec 3380 } ACCESS16BIT;
mbed_official 121:7f86b4238bec 3381 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
mbed_official 121:7f86b4238bec 3382 struct { /* offset: 0x0 */
mbed_official 121:7f86b4238bec 3383 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
mbed_official 121:7f86b4238bec 3384 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
mbed_official 121:7f86b4238bec 3385 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
mbed_official 121:7f86b4238bec 3386 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
mbed_official 121:7f86b4238bec 3387 } ACCESS8BIT;
mbed_official 121:7f86b4238bec 3388 };
mbed_official 121:7f86b4238bec 3389 union { /* offset: 0x4 */
mbed_official 121:7f86b4238bec 3390 struct { /* offset: 0x4 */
mbed_official 121:7f86b4238bec 3391 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
mbed_official 121:7f86b4238bec 3392 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
mbed_official 121:7f86b4238bec 3393 } GPOLY_ACCESS16BIT;
mbed_official 121:7f86b4238bec 3394 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
mbed_official 121:7f86b4238bec 3395 struct { /* offset: 0x4 */
mbed_official 121:7f86b4238bec 3396 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
mbed_official 121:7f86b4238bec 3397 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
mbed_official 121:7f86b4238bec 3398 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
mbed_official 121:7f86b4238bec 3399 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
mbed_official 121:7f86b4238bec 3400 } GPOLY_ACCESS8BIT;
mbed_official 121:7f86b4238bec 3401 };
mbed_official 121:7f86b4238bec 3402 union { /* offset: 0x8 */
mbed_official 121:7f86b4238bec 3403 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
mbed_official 121:7f86b4238bec 3404 struct { /* offset: 0x8 */
mbed_official 121:7f86b4238bec 3405 uint8_t RESERVED_0[3];
mbed_official 121:7f86b4238bec 3406 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
mbed_official 121:7f86b4238bec 3407 } CTRL_ACCESS8BIT;
mbed_official 121:7f86b4238bec 3408 };
mbed_official 121:7f86b4238bec 3409 } CRC_Type;
mbed_official 121:7f86b4238bec 3410
mbed_official 121:7f86b4238bec 3411 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3412 -- CRC Register Masks
mbed_official 121:7f86b4238bec 3413 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3414
mbed_official 121:7f86b4238bec 3415 /*!
mbed_official 121:7f86b4238bec 3416 * @addtogroup CRC_Register_Masks CRC Register Masks
mbed_official 121:7f86b4238bec 3417 * @{
mbed_official 121:7f86b4238bec 3418 */
mbed_official 121:7f86b4238bec 3419
mbed_official 121:7f86b4238bec 3420 /*! @name DATAL - CRC_DATAL register. */
mbed_official 121:7f86b4238bec 3421 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 3422 #define CRC_DATAL_DATAL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3423 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
mbed_official 121:7f86b4238bec 3424
mbed_official 121:7f86b4238bec 3425 /*! @name DATAH - CRC_DATAH register. */
mbed_official 121:7f86b4238bec 3426 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 3427 #define CRC_DATAH_DATAH_SHIFT (0U)
mbed_official 121:7f86b4238bec 3428 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
mbed_official 121:7f86b4238bec 3429
mbed_official 121:7f86b4238bec 3430 /*! @name DATA - CRC Data register */
mbed_official 121:7f86b4238bec 3431 #define CRC_DATA_LL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3432 #define CRC_DATA_LL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3433 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
mbed_official 121:7f86b4238bec 3434 #define CRC_DATA_LU_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 3435 #define CRC_DATA_LU_SHIFT (8U)
mbed_official 121:7f86b4238bec 3436 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
mbed_official 121:7f86b4238bec 3437 #define CRC_DATA_HL_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 3438 #define CRC_DATA_HL_SHIFT (16U)
mbed_official 121:7f86b4238bec 3439 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
mbed_official 121:7f86b4238bec 3440 #define CRC_DATA_HU_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 3441 #define CRC_DATA_HU_SHIFT (24U)
mbed_official 121:7f86b4238bec 3442 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
mbed_official 121:7f86b4238bec 3443
mbed_official 121:7f86b4238bec 3444 /*! @name DATALL - CRC_DATALL register. */
mbed_official 121:7f86b4238bec 3445 #define CRC_DATALL_DATALL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3446 #define CRC_DATALL_DATALL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3447 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
mbed_official 121:7f86b4238bec 3448
mbed_official 121:7f86b4238bec 3449 /*! @name DATALU - CRC_DATALU register. */
mbed_official 121:7f86b4238bec 3450 #define CRC_DATALU_DATALU_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3451 #define CRC_DATALU_DATALU_SHIFT (0U)
mbed_official 121:7f86b4238bec 3452 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
mbed_official 121:7f86b4238bec 3453
mbed_official 121:7f86b4238bec 3454 /*! @name DATAHL - CRC_DATAHL register. */
mbed_official 121:7f86b4238bec 3455 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3456 #define CRC_DATAHL_DATAHL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3457 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
mbed_official 121:7f86b4238bec 3458
mbed_official 121:7f86b4238bec 3459 /*! @name DATAHU - CRC_DATAHU register. */
mbed_official 121:7f86b4238bec 3460 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3461 #define CRC_DATAHU_DATAHU_SHIFT (0U)
mbed_official 121:7f86b4238bec 3462 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
mbed_official 121:7f86b4238bec 3463
mbed_official 121:7f86b4238bec 3464 /*! @name GPOLYL - CRC_GPOLYL register. */
mbed_official 121:7f86b4238bec 3465 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 3466 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3467 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
mbed_official 121:7f86b4238bec 3468
mbed_official 121:7f86b4238bec 3469 /*! @name GPOLYH - CRC_GPOLYH register. */
mbed_official 121:7f86b4238bec 3470 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 3471 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
mbed_official 121:7f86b4238bec 3472 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
mbed_official 121:7f86b4238bec 3473
mbed_official 121:7f86b4238bec 3474 /*! @name GPOLY - CRC Polynomial register */
mbed_official 121:7f86b4238bec 3475 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 3476 #define CRC_GPOLY_LOW_SHIFT (0U)
mbed_official 121:7f86b4238bec 3477 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
mbed_official 121:7f86b4238bec 3478 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 3479 #define CRC_GPOLY_HIGH_SHIFT (16U)
mbed_official 121:7f86b4238bec 3480 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
mbed_official 121:7f86b4238bec 3481
mbed_official 121:7f86b4238bec 3482 /*! @name GPOLYLL - CRC_GPOLYLL register. */
mbed_official 121:7f86b4238bec 3483 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3484 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3485 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
mbed_official 121:7f86b4238bec 3486
mbed_official 121:7f86b4238bec 3487 /*! @name GPOLYLU - CRC_GPOLYLU register. */
mbed_official 121:7f86b4238bec 3488 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3489 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
mbed_official 121:7f86b4238bec 3490 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
mbed_official 121:7f86b4238bec 3491
mbed_official 121:7f86b4238bec 3492 /*! @name GPOLYHL - CRC_GPOLYHL register. */
mbed_official 121:7f86b4238bec 3493 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3494 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
mbed_official 121:7f86b4238bec 3495 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
mbed_official 121:7f86b4238bec 3496
mbed_official 121:7f86b4238bec 3497 /*! @name GPOLYHU - CRC_GPOLYHU register. */
mbed_official 121:7f86b4238bec 3498 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3499 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
mbed_official 121:7f86b4238bec 3500 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
mbed_official 121:7f86b4238bec 3501
mbed_official 121:7f86b4238bec 3502 /*! @name CTRL - CRC Control register */
mbed_official 121:7f86b4238bec 3503 #define CRC_CTRL_TCRC_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 3504 #define CRC_CTRL_TCRC_SHIFT (24U)
mbed_official 121:7f86b4238bec 3505 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
mbed_official 121:7f86b4238bec 3506 #define CRC_CTRL_WAS_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 3507 #define CRC_CTRL_WAS_SHIFT (25U)
mbed_official 121:7f86b4238bec 3508 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
mbed_official 121:7f86b4238bec 3509 #define CRC_CTRL_FXOR_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 3510 #define CRC_CTRL_FXOR_SHIFT (26U)
mbed_official 121:7f86b4238bec 3511 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
mbed_official 121:7f86b4238bec 3512 #define CRC_CTRL_TOTR_MASK (0x30000000U)
mbed_official 121:7f86b4238bec 3513 #define CRC_CTRL_TOTR_SHIFT (28U)
mbed_official 121:7f86b4238bec 3514 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
mbed_official 121:7f86b4238bec 3515 #define CRC_CTRL_TOT_MASK (0xC0000000U)
mbed_official 121:7f86b4238bec 3516 #define CRC_CTRL_TOT_SHIFT (30U)
mbed_official 121:7f86b4238bec 3517 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
mbed_official 121:7f86b4238bec 3518
mbed_official 121:7f86b4238bec 3519 /*! @name CTRLHU - CRC_CTRLHU register. */
mbed_official 121:7f86b4238bec 3520 #define CRC_CTRLHU_TCRC_MASK (0x1U)
mbed_official 121:7f86b4238bec 3521 #define CRC_CTRLHU_TCRC_SHIFT (0U)
mbed_official 121:7f86b4238bec 3522 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
mbed_official 121:7f86b4238bec 3523 #define CRC_CTRLHU_WAS_MASK (0x2U)
mbed_official 121:7f86b4238bec 3524 #define CRC_CTRLHU_WAS_SHIFT (1U)
mbed_official 121:7f86b4238bec 3525 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
mbed_official 121:7f86b4238bec 3526 #define CRC_CTRLHU_FXOR_MASK (0x4U)
mbed_official 121:7f86b4238bec 3527 #define CRC_CTRLHU_FXOR_SHIFT (2U)
mbed_official 121:7f86b4238bec 3528 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
mbed_official 121:7f86b4238bec 3529 #define CRC_CTRLHU_TOTR_MASK (0x30U)
mbed_official 121:7f86b4238bec 3530 #define CRC_CTRLHU_TOTR_SHIFT (4U)
mbed_official 121:7f86b4238bec 3531 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
mbed_official 121:7f86b4238bec 3532 #define CRC_CTRLHU_TOT_MASK (0xC0U)
mbed_official 121:7f86b4238bec 3533 #define CRC_CTRLHU_TOT_SHIFT (6U)
mbed_official 121:7f86b4238bec 3534 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
mbed_official 121:7f86b4238bec 3535
mbed_official 121:7f86b4238bec 3536
mbed_official 121:7f86b4238bec 3537 /*!
mbed_official 121:7f86b4238bec 3538 * @}
mbed_official 121:7f86b4238bec 3539 */ /* end of group CRC_Register_Masks */
mbed_official 121:7f86b4238bec 3540
mbed_official 121:7f86b4238bec 3541
mbed_official 121:7f86b4238bec 3542 /* CRC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 3543 /** Peripheral CRC base address */
mbed_official 121:7f86b4238bec 3544 #define CRC_BASE (0x40032000u)
mbed_official 121:7f86b4238bec 3545 /** Peripheral CRC base pointer */
mbed_official 121:7f86b4238bec 3546 #define CRC0 ((CRC_Type *)CRC_BASE)
mbed_official 121:7f86b4238bec 3547 /** Array initializer of CRC peripheral base addresses */
mbed_official 121:7f86b4238bec 3548 #define CRC_BASE_ADDRS { CRC_BASE }
mbed_official 121:7f86b4238bec 3549 /** Array initializer of CRC peripheral base pointers */
mbed_official 121:7f86b4238bec 3550 #define CRC_BASE_PTRS { CRC0 }
mbed_official 121:7f86b4238bec 3551
mbed_official 121:7f86b4238bec 3552 /*!
mbed_official 121:7f86b4238bec 3553 * @}
mbed_official 121:7f86b4238bec 3554 */ /* end of group CRC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 3555
mbed_official 121:7f86b4238bec 3556
mbed_official 121:7f86b4238bec 3557 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3558 -- DAC Peripheral Access Layer
mbed_official 121:7f86b4238bec 3559 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3560
mbed_official 121:7f86b4238bec 3561 /*!
mbed_official 121:7f86b4238bec 3562 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
mbed_official 121:7f86b4238bec 3563 * @{
mbed_official 121:7f86b4238bec 3564 */
mbed_official 121:7f86b4238bec 3565
mbed_official 121:7f86b4238bec 3566 /** DAC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 3567 typedef struct {
mbed_official 121:7f86b4238bec 3568 struct { /* offset: 0x0, array step: 0x2 */
mbed_official 121:7f86b4238bec 3569 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
mbed_official 121:7f86b4238bec 3570 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
mbed_official 121:7f86b4238bec 3571 } DAT[16];
mbed_official 121:7f86b4238bec 3572 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
mbed_official 121:7f86b4238bec 3573 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
mbed_official 121:7f86b4238bec 3574 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
mbed_official 121:7f86b4238bec 3575 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
mbed_official 121:7f86b4238bec 3576 } DAC_Type;
mbed_official 121:7f86b4238bec 3577
mbed_official 121:7f86b4238bec 3578 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3579 -- DAC Register Masks
mbed_official 121:7f86b4238bec 3580 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3581
mbed_official 121:7f86b4238bec 3582 /*!
mbed_official 121:7f86b4238bec 3583 * @addtogroup DAC_Register_Masks DAC Register Masks
mbed_official 121:7f86b4238bec 3584 * @{
mbed_official 121:7f86b4238bec 3585 */
mbed_official 121:7f86b4238bec 3586
mbed_official 121:7f86b4238bec 3587 /*! @name DATL - DAC Data Low Register */
mbed_official 121:7f86b4238bec 3588 #define DAC_DATL_DATA0_MASK (0xFFU)
mbed_official 121:7f86b4238bec 3589 #define DAC_DATL_DATA0_SHIFT (0U)
mbed_official 121:7f86b4238bec 3590 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
mbed_official 121:7f86b4238bec 3591
mbed_official 121:7f86b4238bec 3592 /* The count of DAC_DATL */
mbed_official 121:7f86b4238bec 3593 #define DAC_DATL_COUNT (16U)
mbed_official 121:7f86b4238bec 3594
mbed_official 121:7f86b4238bec 3595 /*! @name DATH - DAC Data High Register */
mbed_official 121:7f86b4238bec 3596 #define DAC_DATH_DATA1_MASK (0xFU)
mbed_official 121:7f86b4238bec 3597 #define DAC_DATH_DATA1_SHIFT (0U)
mbed_official 121:7f86b4238bec 3598 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
mbed_official 121:7f86b4238bec 3599
mbed_official 121:7f86b4238bec 3600 /* The count of DAC_DATH */
mbed_official 121:7f86b4238bec 3601 #define DAC_DATH_COUNT (16U)
mbed_official 121:7f86b4238bec 3602
mbed_official 121:7f86b4238bec 3603 /*! @name SR - DAC Status Register */
mbed_official 121:7f86b4238bec 3604 #define DAC_SR_DACBFRPBF_MASK (0x1U)
mbed_official 121:7f86b4238bec 3605 #define DAC_SR_DACBFRPBF_SHIFT (0U)
mbed_official 121:7f86b4238bec 3606 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
mbed_official 121:7f86b4238bec 3607 #define DAC_SR_DACBFRPTF_MASK (0x2U)
mbed_official 121:7f86b4238bec 3608 #define DAC_SR_DACBFRPTF_SHIFT (1U)
mbed_official 121:7f86b4238bec 3609 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
mbed_official 121:7f86b4238bec 3610 #define DAC_SR_DACBFWMF_MASK (0x4U)
mbed_official 121:7f86b4238bec 3611 #define DAC_SR_DACBFWMF_SHIFT (2U)
mbed_official 121:7f86b4238bec 3612 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
mbed_official 121:7f86b4238bec 3613
mbed_official 121:7f86b4238bec 3614 /*! @name C0 - DAC Control Register */
mbed_official 121:7f86b4238bec 3615 #define DAC_C0_DACBBIEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 3616 #define DAC_C0_DACBBIEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 3617 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
mbed_official 121:7f86b4238bec 3618 #define DAC_C0_DACBTIEN_MASK (0x2U)
mbed_official 121:7f86b4238bec 3619 #define DAC_C0_DACBTIEN_SHIFT (1U)
mbed_official 121:7f86b4238bec 3620 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
mbed_official 121:7f86b4238bec 3621 #define DAC_C0_DACBWIEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 3622 #define DAC_C0_DACBWIEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 3623 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
mbed_official 121:7f86b4238bec 3624 #define DAC_C0_LPEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 3625 #define DAC_C0_LPEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 3626 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
mbed_official 121:7f86b4238bec 3627 #define DAC_C0_DACSWTRG_MASK (0x10U)
mbed_official 121:7f86b4238bec 3628 #define DAC_C0_DACSWTRG_SHIFT (4U)
mbed_official 121:7f86b4238bec 3629 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
mbed_official 121:7f86b4238bec 3630 #define DAC_C0_DACTRGSEL_MASK (0x20U)
mbed_official 121:7f86b4238bec 3631 #define DAC_C0_DACTRGSEL_SHIFT (5U)
mbed_official 121:7f86b4238bec 3632 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
mbed_official 121:7f86b4238bec 3633 #define DAC_C0_DACRFS_MASK (0x40U)
mbed_official 121:7f86b4238bec 3634 #define DAC_C0_DACRFS_SHIFT (6U)
mbed_official 121:7f86b4238bec 3635 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
mbed_official 121:7f86b4238bec 3636 #define DAC_C0_DACEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 3637 #define DAC_C0_DACEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 3638 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
mbed_official 121:7f86b4238bec 3639
mbed_official 121:7f86b4238bec 3640 /*! @name C1 - DAC Control Register 1 */
mbed_official 121:7f86b4238bec 3641 #define DAC_C1_DACBFEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 3642 #define DAC_C1_DACBFEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 3643 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
mbed_official 121:7f86b4238bec 3644 #define DAC_C1_DACBFMD_MASK (0x6U)
mbed_official 121:7f86b4238bec 3645 #define DAC_C1_DACBFMD_SHIFT (1U)
mbed_official 121:7f86b4238bec 3646 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
mbed_official 121:7f86b4238bec 3647 #define DAC_C1_DACBFWM_MASK (0x18U)
mbed_official 121:7f86b4238bec 3648 #define DAC_C1_DACBFWM_SHIFT (3U)
mbed_official 121:7f86b4238bec 3649 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
mbed_official 121:7f86b4238bec 3650 #define DAC_C1_DMAEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 3651 #define DAC_C1_DMAEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 3652 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
mbed_official 121:7f86b4238bec 3653
mbed_official 121:7f86b4238bec 3654 /*! @name C2 - DAC Control Register 2 */
mbed_official 121:7f86b4238bec 3655 #define DAC_C2_DACBFUP_MASK (0xFU)
mbed_official 121:7f86b4238bec 3656 #define DAC_C2_DACBFUP_SHIFT (0U)
mbed_official 121:7f86b4238bec 3657 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
mbed_official 121:7f86b4238bec 3658 #define DAC_C2_DACBFRP_MASK (0xF0U)
mbed_official 121:7f86b4238bec 3659 #define DAC_C2_DACBFRP_SHIFT (4U)
mbed_official 121:7f86b4238bec 3660 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
mbed_official 121:7f86b4238bec 3661
mbed_official 121:7f86b4238bec 3662
mbed_official 121:7f86b4238bec 3663 /*!
mbed_official 121:7f86b4238bec 3664 * @}
mbed_official 121:7f86b4238bec 3665 */ /* end of group DAC_Register_Masks */
mbed_official 121:7f86b4238bec 3666
mbed_official 121:7f86b4238bec 3667
mbed_official 121:7f86b4238bec 3668 /* DAC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 3669 /** Peripheral DAC0 base address */
mbed_official 121:7f86b4238bec 3670 #define DAC0_BASE (0x400CC000u)
mbed_official 121:7f86b4238bec 3671 /** Peripheral DAC0 base pointer */
mbed_official 121:7f86b4238bec 3672 #define DAC0 ((DAC_Type *)DAC0_BASE)
mbed_official 121:7f86b4238bec 3673 /** Peripheral DAC1 base address */
mbed_official 121:7f86b4238bec 3674 #define DAC1_BASE (0x400CD000u)
mbed_official 121:7f86b4238bec 3675 /** Peripheral DAC1 base pointer */
mbed_official 121:7f86b4238bec 3676 #define DAC1 ((DAC_Type *)DAC1_BASE)
mbed_official 121:7f86b4238bec 3677 /** Array initializer of DAC peripheral base addresses */
mbed_official 121:7f86b4238bec 3678 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
mbed_official 121:7f86b4238bec 3679 /** Array initializer of DAC peripheral base pointers */
mbed_official 121:7f86b4238bec 3680 #define DAC_BASE_PTRS { DAC0, DAC1 }
mbed_official 121:7f86b4238bec 3681 /** Interrupt vectors for the DAC peripheral type */
mbed_official 121:7f86b4238bec 3682 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
mbed_official 121:7f86b4238bec 3683
mbed_official 121:7f86b4238bec 3684 /*!
mbed_official 121:7f86b4238bec 3685 * @}
mbed_official 121:7f86b4238bec 3686 */ /* end of group DAC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 3687
mbed_official 121:7f86b4238bec 3688
mbed_official 121:7f86b4238bec 3689 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3690 -- DMA Peripheral Access Layer
mbed_official 121:7f86b4238bec 3691 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3692
mbed_official 121:7f86b4238bec 3693 /*!
mbed_official 121:7f86b4238bec 3694 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mbed_official 121:7f86b4238bec 3695 * @{
mbed_official 121:7f86b4238bec 3696 */
mbed_official 121:7f86b4238bec 3697
mbed_official 121:7f86b4238bec 3698 /** DMA - Register Layout Typedef */
mbed_official 121:7f86b4238bec 3699 typedef struct {
mbed_official 121:7f86b4238bec 3700 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 3701 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 3702 uint8_t RESERVED_0[4];
mbed_official 121:7f86b4238bec 3703 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
mbed_official 121:7f86b4238bec 3704 uint8_t RESERVED_1[4];
mbed_official 121:7f86b4238bec 3705 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
mbed_official 121:7f86b4238bec 3706 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
mbed_official 121:7f86b4238bec 3707 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
mbed_official 121:7f86b4238bec 3708 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
mbed_official 121:7f86b4238bec 3709 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
mbed_official 121:7f86b4238bec 3710 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
mbed_official 121:7f86b4238bec 3711 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
mbed_official 121:7f86b4238bec 3712 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
mbed_official 121:7f86b4238bec 3713 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
mbed_official 121:7f86b4238bec 3714 uint8_t RESERVED_2[4];
mbed_official 121:7f86b4238bec 3715 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
mbed_official 121:7f86b4238bec 3716 uint8_t RESERVED_3[4];
mbed_official 121:7f86b4238bec 3717 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
mbed_official 121:7f86b4238bec 3718 uint8_t RESERVED_4[4];
mbed_official 121:7f86b4238bec 3719 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
mbed_official 121:7f86b4238bec 3720 uint8_t RESERVED_5[200];
mbed_official 121:7f86b4238bec 3721 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
mbed_official 121:7f86b4238bec 3722 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
mbed_official 121:7f86b4238bec 3723 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
mbed_official 121:7f86b4238bec 3724 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
mbed_official 121:7f86b4238bec 3725 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
mbed_official 121:7f86b4238bec 3726 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
mbed_official 121:7f86b4238bec 3727 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
mbed_official 121:7f86b4238bec 3728 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
mbed_official 121:7f86b4238bec 3729 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
mbed_official 121:7f86b4238bec 3730 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
mbed_official 121:7f86b4238bec 3731 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
mbed_official 121:7f86b4238bec 3732 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
mbed_official 121:7f86b4238bec 3733 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
mbed_official 121:7f86b4238bec 3734 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
mbed_official 121:7f86b4238bec 3735 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
mbed_official 121:7f86b4238bec 3736 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
mbed_official 121:7f86b4238bec 3737 uint8_t RESERVED_6[3824];
mbed_official 121:7f86b4238bec 3738 struct { /* offset: 0x1000, array step: 0x20 */
mbed_official 121:7f86b4238bec 3739 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
mbed_official 121:7f86b4238bec 3740 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
mbed_official 121:7f86b4238bec 3741 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
mbed_official 121:7f86b4238bec 3742 union { /* offset: 0x1008, array step: 0x20 */
mbed_official 121:7f86b4238bec 3743 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
mbed_official 121:7f86b4238bec 3744 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
mbed_official 121:7f86b4238bec 3745 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
mbed_official 121:7f86b4238bec 3746 };
mbed_official 121:7f86b4238bec 3747 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
mbed_official 121:7f86b4238bec 3748 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
mbed_official 121:7f86b4238bec 3749 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
mbed_official 121:7f86b4238bec 3750 union { /* offset: 0x1016, array step: 0x20 */
mbed_official 121:7f86b4238bec 3751 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
mbed_official 121:7f86b4238bec 3752 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
mbed_official 121:7f86b4238bec 3753 };
mbed_official 121:7f86b4238bec 3754 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
mbed_official 121:7f86b4238bec 3755 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
mbed_official 121:7f86b4238bec 3756 union { /* offset: 0x101E, array step: 0x20 */
mbed_official 121:7f86b4238bec 3757 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
mbed_official 121:7f86b4238bec 3758 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
mbed_official 121:7f86b4238bec 3759 };
mbed_official 121:7f86b4238bec 3760 } TCD[16];
mbed_official 121:7f86b4238bec 3761 } DMA_Type;
mbed_official 121:7f86b4238bec 3762
mbed_official 121:7f86b4238bec 3763 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 3764 -- DMA Register Masks
mbed_official 121:7f86b4238bec 3765 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 3766
mbed_official 121:7f86b4238bec 3767 /*!
mbed_official 121:7f86b4238bec 3768 * @addtogroup DMA_Register_Masks DMA Register Masks
mbed_official 121:7f86b4238bec 3769 * @{
mbed_official 121:7f86b4238bec 3770 */
mbed_official 121:7f86b4238bec 3771
mbed_official 121:7f86b4238bec 3772 /*! @name CR - Control Register */
mbed_official 121:7f86b4238bec 3773 #define DMA_CR_EDBG_MASK (0x2U)
mbed_official 121:7f86b4238bec 3774 #define DMA_CR_EDBG_SHIFT (1U)
mbed_official 121:7f86b4238bec 3775 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
mbed_official 121:7f86b4238bec 3776 #define DMA_CR_ERCA_MASK (0x4U)
mbed_official 121:7f86b4238bec 3777 #define DMA_CR_ERCA_SHIFT (2U)
mbed_official 121:7f86b4238bec 3778 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
mbed_official 121:7f86b4238bec 3779 #define DMA_CR_HOE_MASK (0x10U)
mbed_official 121:7f86b4238bec 3780 #define DMA_CR_HOE_SHIFT (4U)
mbed_official 121:7f86b4238bec 3781 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
mbed_official 121:7f86b4238bec 3782 #define DMA_CR_HALT_MASK (0x20U)
mbed_official 121:7f86b4238bec 3783 #define DMA_CR_HALT_SHIFT (5U)
mbed_official 121:7f86b4238bec 3784 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
mbed_official 121:7f86b4238bec 3785 #define DMA_CR_CLM_MASK (0x40U)
mbed_official 121:7f86b4238bec 3786 #define DMA_CR_CLM_SHIFT (6U)
mbed_official 121:7f86b4238bec 3787 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
mbed_official 121:7f86b4238bec 3788 #define DMA_CR_EMLM_MASK (0x80U)
mbed_official 121:7f86b4238bec 3789 #define DMA_CR_EMLM_SHIFT (7U)
mbed_official 121:7f86b4238bec 3790 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
mbed_official 121:7f86b4238bec 3791 #define DMA_CR_ECX_MASK (0x10000U)
mbed_official 121:7f86b4238bec 3792 #define DMA_CR_ECX_SHIFT (16U)
mbed_official 121:7f86b4238bec 3793 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
mbed_official 121:7f86b4238bec 3794 #define DMA_CR_CX_MASK (0x20000U)
mbed_official 121:7f86b4238bec 3795 #define DMA_CR_CX_SHIFT (17U)
mbed_official 121:7f86b4238bec 3796 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
mbed_official 121:7f86b4238bec 3797
mbed_official 121:7f86b4238bec 3798 /*! @name ES - Error Status Register */
mbed_official 121:7f86b4238bec 3799 #define DMA_ES_DBE_MASK (0x1U)
mbed_official 121:7f86b4238bec 3800 #define DMA_ES_DBE_SHIFT (0U)
mbed_official 121:7f86b4238bec 3801 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
mbed_official 121:7f86b4238bec 3802 #define DMA_ES_SBE_MASK (0x2U)
mbed_official 121:7f86b4238bec 3803 #define DMA_ES_SBE_SHIFT (1U)
mbed_official 121:7f86b4238bec 3804 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
mbed_official 121:7f86b4238bec 3805 #define DMA_ES_SGE_MASK (0x4U)
mbed_official 121:7f86b4238bec 3806 #define DMA_ES_SGE_SHIFT (2U)
mbed_official 121:7f86b4238bec 3807 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
mbed_official 121:7f86b4238bec 3808 #define DMA_ES_NCE_MASK (0x8U)
mbed_official 121:7f86b4238bec 3809 #define DMA_ES_NCE_SHIFT (3U)
mbed_official 121:7f86b4238bec 3810 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
mbed_official 121:7f86b4238bec 3811 #define DMA_ES_DOE_MASK (0x10U)
mbed_official 121:7f86b4238bec 3812 #define DMA_ES_DOE_SHIFT (4U)
mbed_official 121:7f86b4238bec 3813 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
mbed_official 121:7f86b4238bec 3814 #define DMA_ES_DAE_MASK (0x20U)
mbed_official 121:7f86b4238bec 3815 #define DMA_ES_DAE_SHIFT (5U)
mbed_official 121:7f86b4238bec 3816 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
mbed_official 121:7f86b4238bec 3817 #define DMA_ES_SOE_MASK (0x40U)
mbed_official 121:7f86b4238bec 3818 #define DMA_ES_SOE_SHIFT (6U)
mbed_official 121:7f86b4238bec 3819 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
mbed_official 121:7f86b4238bec 3820 #define DMA_ES_SAE_MASK (0x80U)
mbed_official 121:7f86b4238bec 3821 #define DMA_ES_SAE_SHIFT (7U)
mbed_official 121:7f86b4238bec 3822 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
mbed_official 121:7f86b4238bec 3823 #define DMA_ES_ERRCHN_MASK (0xF00U)
mbed_official 121:7f86b4238bec 3824 #define DMA_ES_ERRCHN_SHIFT (8U)
mbed_official 121:7f86b4238bec 3825 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
mbed_official 121:7f86b4238bec 3826 #define DMA_ES_CPE_MASK (0x4000U)
mbed_official 121:7f86b4238bec 3827 #define DMA_ES_CPE_SHIFT (14U)
mbed_official 121:7f86b4238bec 3828 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
mbed_official 121:7f86b4238bec 3829 #define DMA_ES_ECX_MASK (0x10000U)
mbed_official 121:7f86b4238bec 3830 #define DMA_ES_ECX_SHIFT (16U)
mbed_official 121:7f86b4238bec 3831 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
mbed_official 121:7f86b4238bec 3832 #define DMA_ES_VLD_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 3833 #define DMA_ES_VLD_SHIFT (31U)
mbed_official 121:7f86b4238bec 3834 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
mbed_official 121:7f86b4238bec 3835
mbed_official 121:7f86b4238bec 3836 /*! @name ERQ - Enable Request Register */
mbed_official 121:7f86b4238bec 3837 #define DMA_ERQ_ERQ0_MASK (0x1U)
mbed_official 121:7f86b4238bec 3838 #define DMA_ERQ_ERQ0_SHIFT (0U)
mbed_official 121:7f86b4238bec 3839 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
mbed_official 121:7f86b4238bec 3840 #define DMA_ERQ_ERQ1_MASK (0x2U)
mbed_official 121:7f86b4238bec 3841 #define DMA_ERQ_ERQ1_SHIFT (1U)
mbed_official 121:7f86b4238bec 3842 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
mbed_official 121:7f86b4238bec 3843 #define DMA_ERQ_ERQ2_MASK (0x4U)
mbed_official 121:7f86b4238bec 3844 #define DMA_ERQ_ERQ2_SHIFT (2U)
mbed_official 121:7f86b4238bec 3845 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
mbed_official 121:7f86b4238bec 3846 #define DMA_ERQ_ERQ3_MASK (0x8U)
mbed_official 121:7f86b4238bec 3847 #define DMA_ERQ_ERQ3_SHIFT (3U)
mbed_official 121:7f86b4238bec 3848 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
mbed_official 121:7f86b4238bec 3849 #define DMA_ERQ_ERQ4_MASK (0x10U)
mbed_official 121:7f86b4238bec 3850 #define DMA_ERQ_ERQ4_SHIFT (4U)
mbed_official 121:7f86b4238bec 3851 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
mbed_official 121:7f86b4238bec 3852 #define DMA_ERQ_ERQ5_MASK (0x20U)
mbed_official 121:7f86b4238bec 3853 #define DMA_ERQ_ERQ5_SHIFT (5U)
mbed_official 121:7f86b4238bec 3854 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
mbed_official 121:7f86b4238bec 3855 #define DMA_ERQ_ERQ6_MASK (0x40U)
mbed_official 121:7f86b4238bec 3856 #define DMA_ERQ_ERQ6_SHIFT (6U)
mbed_official 121:7f86b4238bec 3857 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
mbed_official 121:7f86b4238bec 3858 #define DMA_ERQ_ERQ7_MASK (0x80U)
mbed_official 121:7f86b4238bec 3859 #define DMA_ERQ_ERQ7_SHIFT (7U)
mbed_official 121:7f86b4238bec 3860 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
mbed_official 121:7f86b4238bec 3861 #define DMA_ERQ_ERQ8_MASK (0x100U)
mbed_official 121:7f86b4238bec 3862 #define DMA_ERQ_ERQ8_SHIFT (8U)
mbed_official 121:7f86b4238bec 3863 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
mbed_official 121:7f86b4238bec 3864 #define DMA_ERQ_ERQ9_MASK (0x200U)
mbed_official 121:7f86b4238bec 3865 #define DMA_ERQ_ERQ9_SHIFT (9U)
mbed_official 121:7f86b4238bec 3866 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
mbed_official 121:7f86b4238bec 3867 #define DMA_ERQ_ERQ10_MASK (0x400U)
mbed_official 121:7f86b4238bec 3868 #define DMA_ERQ_ERQ10_SHIFT (10U)
mbed_official 121:7f86b4238bec 3869 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
mbed_official 121:7f86b4238bec 3870 #define DMA_ERQ_ERQ11_MASK (0x800U)
mbed_official 121:7f86b4238bec 3871 #define DMA_ERQ_ERQ11_SHIFT (11U)
mbed_official 121:7f86b4238bec 3872 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
mbed_official 121:7f86b4238bec 3873 #define DMA_ERQ_ERQ12_MASK (0x1000U)
mbed_official 121:7f86b4238bec 3874 #define DMA_ERQ_ERQ12_SHIFT (12U)
mbed_official 121:7f86b4238bec 3875 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
mbed_official 121:7f86b4238bec 3876 #define DMA_ERQ_ERQ13_MASK (0x2000U)
mbed_official 121:7f86b4238bec 3877 #define DMA_ERQ_ERQ13_SHIFT (13U)
mbed_official 121:7f86b4238bec 3878 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
mbed_official 121:7f86b4238bec 3879 #define DMA_ERQ_ERQ14_MASK (0x4000U)
mbed_official 121:7f86b4238bec 3880 #define DMA_ERQ_ERQ14_SHIFT (14U)
mbed_official 121:7f86b4238bec 3881 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
mbed_official 121:7f86b4238bec 3882 #define DMA_ERQ_ERQ15_MASK (0x8000U)
mbed_official 121:7f86b4238bec 3883 #define DMA_ERQ_ERQ15_SHIFT (15U)
mbed_official 121:7f86b4238bec 3884 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
mbed_official 121:7f86b4238bec 3885
mbed_official 121:7f86b4238bec 3886 /*! @name EEI - Enable Error Interrupt Register */
mbed_official 121:7f86b4238bec 3887 #define DMA_EEI_EEI0_MASK (0x1U)
mbed_official 121:7f86b4238bec 3888 #define DMA_EEI_EEI0_SHIFT (0U)
mbed_official 121:7f86b4238bec 3889 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
mbed_official 121:7f86b4238bec 3890 #define DMA_EEI_EEI1_MASK (0x2U)
mbed_official 121:7f86b4238bec 3891 #define DMA_EEI_EEI1_SHIFT (1U)
mbed_official 121:7f86b4238bec 3892 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
mbed_official 121:7f86b4238bec 3893 #define DMA_EEI_EEI2_MASK (0x4U)
mbed_official 121:7f86b4238bec 3894 #define DMA_EEI_EEI2_SHIFT (2U)
mbed_official 121:7f86b4238bec 3895 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
mbed_official 121:7f86b4238bec 3896 #define DMA_EEI_EEI3_MASK (0x8U)
mbed_official 121:7f86b4238bec 3897 #define DMA_EEI_EEI3_SHIFT (3U)
mbed_official 121:7f86b4238bec 3898 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
mbed_official 121:7f86b4238bec 3899 #define DMA_EEI_EEI4_MASK (0x10U)
mbed_official 121:7f86b4238bec 3900 #define DMA_EEI_EEI4_SHIFT (4U)
mbed_official 121:7f86b4238bec 3901 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
mbed_official 121:7f86b4238bec 3902 #define DMA_EEI_EEI5_MASK (0x20U)
mbed_official 121:7f86b4238bec 3903 #define DMA_EEI_EEI5_SHIFT (5U)
mbed_official 121:7f86b4238bec 3904 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
mbed_official 121:7f86b4238bec 3905 #define DMA_EEI_EEI6_MASK (0x40U)
mbed_official 121:7f86b4238bec 3906 #define DMA_EEI_EEI6_SHIFT (6U)
mbed_official 121:7f86b4238bec 3907 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
mbed_official 121:7f86b4238bec 3908 #define DMA_EEI_EEI7_MASK (0x80U)
mbed_official 121:7f86b4238bec 3909 #define DMA_EEI_EEI7_SHIFT (7U)
mbed_official 121:7f86b4238bec 3910 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
mbed_official 121:7f86b4238bec 3911 #define DMA_EEI_EEI8_MASK (0x100U)
mbed_official 121:7f86b4238bec 3912 #define DMA_EEI_EEI8_SHIFT (8U)
mbed_official 121:7f86b4238bec 3913 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
mbed_official 121:7f86b4238bec 3914 #define DMA_EEI_EEI9_MASK (0x200U)
mbed_official 121:7f86b4238bec 3915 #define DMA_EEI_EEI9_SHIFT (9U)
mbed_official 121:7f86b4238bec 3916 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
mbed_official 121:7f86b4238bec 3917 #define DMA_EEI_EEI10_MASK (0x400U)
mbed_official 121:7f86b4238bec 3918 #define DMA_EEI_EEI10_SHIFT (10U)
mbed_official 121:7f86b4238bec 3919 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
mbed_official 121:7f86b4238bec 3920 #define DMA_EEI_EEI11_MASK (0x800U)
mbed_official 121:7f86b4238bec 3921 #define DMA_EEI_EEI11_SHIFT (11U)
mbed_official 121:7f86b4238bec 3922 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
mbed_official 121:7f86b4238bec 3923 #define DMA_EEI_EEI12_MASK (0x1000U)
mbed_official 121:7f86b4238bec 3924 #define DMA_EEI_EEI12_SHIFT (12U)
mbed_official 121:7f86b4238bec 3925 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
mbed_official 121:7f86b4238bec 3926 #define DMA_EEI_EEI13_MASK (0x2000U)
mbed_official 121:7f86b4238bec 3927 #define DMA_EEI_EEI13_SHIFT (13U)
mbed_official 121:7f86b4238bec 3928 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
mbed_official 121:7f86b4238bec 3929 #define DMA_EEI_EEI14_MASK (0x4000U)
mbed_official 121:7f86b4238bec 3930 #define DMA_EEI_EEI14_SHIFT (14U)
mbed_official 121:7f86b4238bec 3931 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
mbed_official 121:7f86b4238bec 3932 #define DMA_EEI_EEI15_MASK (0x8000U)
mbed_official 121:7f86b4238bec 3933 #define DMA_EEI_EEI15_SHIFT (15U)
mbed_official 121:7f86b4238bec 3934 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
mbed_official 121:7f86b4238bec 3935
mbed_official 121:7f86b4238bec 3936 /*! @name CEEI - Clear Enable Error Interrupt Register */
mbed_official 121:7f86b4238bec 3937 #define DMA_CEEI_CEEI_MASK (0xFU)
mbed_official 121:7f86b4238bec 3938 #define DMA_CEEI_CEEI_SHIFT (0U)
mbed_official 121:7f86b4238bec 3939 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
mbed_official 121:7f86b4238bec 3940 #define DMA_CEEI_CAEE_MASK (0x40U)
mbed_official 121:7f86b4238bec 3941 #define DMA_CEEI_CAEE_SHIFT (6U)
mbed_official 121:7f86b4238bec 3942 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
mbed_official 121:7f86b4238bec 3943 #define DMA_CEEI_NOP_MASK (0x80U)
mbed_official 121:7f86b4238bec 3944 #define DMA_CEEI_NOP_SHIFT (7U)
mbed_official 121:7f86b4238bec 3945 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
mbed_official 121:7f86b4238bec 3946
mbed_official 121:7f86b4238bec 3947 /*! @name SEEI - Set Enable Error Interrupt Register */
mbed_official 121:7f86b4238bec 3948 #define DMA_SEEI_SEEI_MASK (0xFU)
mbed_official 121:7f86b4238bec 3949 #define DMA_SEEI_SEEI_SHIFT (0U)
mbed_official 121:7f86b4238bec 3950 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
mbed_official 121:7f86b4238bec 3951 #define DMA_SEEI_SAEE_MASK (0x40U)
mbed_official 121:7f86b4238bec 3952 #define DMA_SEEI_SAEE_SHIFT (6U)
mbed_official 121:7f86b4238bec 3953 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
mbed_official 121:7f86b4238bec 3954 #define DMA_SEEI_NOP_MASK (0x80U)
mbed_official 121:7f86b4238bec 3955 #define DMA_SEEI_NOP_SHIFT (7U)
mbed_official 121:7f86b4238bec 3956 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
mbed_official 121:7f86b4238bec 3957
mbed_official 121:7f86b4238bec 3958 /*! @name CERQ - Clear Enable Request Register */
mbed_official 121:7f86b4238bec 3959 #define DMA_CERQ_CERQ_MASK (0xFU)
mbed_official 121:7f86b4238bec 3960 #define DMA_CERQ_CERQ_SHIFT (0U)
mbed_official 121:7f86b4238bec 3961 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
mbed_official 121:7f86b4238bec 3962 #define DMA_CERQ_CAER_MASK (0x40U)
mbed_official 121:7f86b4238bec 3963 #define DMA_CERQ_CAER_SHIFT (6U)
mbed_official 121:7f86b4238bec 3964 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
mbed_official 121:7f86b4238bec 3965 #define DMA_CERQ_NOP_MASK (0x80U)
mbed_official 121:7f86b4238bec 3966 #define DMA_CERQ_NOP_SHIFT (7U)
mbed_official 121:7f86b4238bec 3967 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
mbed_official 121:7f86b4238bec 3968
mbed_official 121:7f86b4238bec 3969 /*! @name SERQ - Set Enable Request Register */
mbed_official 121:7f86b4238bec 3970 #define DMA_SERQ_SERQ_MASK (0xFU)
mbed_official 121:7f86b4238bec 3971 #define DMA_SERQ_SERQ_SHIFT (0U)
mbed_official 121:7f86b4238bec 3972 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
mbed_official 121:7f86b4238bec 3973 #define DMA_SERQ_SAER_MASK (0x40U)
mbed_official 121:7f86b4238bec 3974 #define DMA_SERQ_SAER_SHIFT (6U)
mbed_official 121:7f86b4238bec 3975 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
mbed_official 121:7f86b4238bec 3976 #define DMA_SERQ_NOP_MASK (0x80U)
mbed_official 121:7f86b4238bec 3977 #define DMA_SERQ_NOP_SHIFT (7U)
mbed_official 121:7f86b4238bec 3978 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
mbed_official 121:7f86b4238bec 3979
mbed_official 121:7f86b4238bec 3980 /*! @name CDNE - Clear DONE Status Bit Register */
mbed_official 121:7f86b4238bec 3981 #define DMA_CDNE_CDNE_MASK (0xFU)
mbed_official 121:7f86b4238bec 3982 #define DMA_CDNE_CDNE_SHIFT (0U)
mbed_official 121:7f86b4238bec 3983 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
mbed_official 121:7f86b4238bec 3984 #define DMA_CDNE_CADN_MASK (0x40U)
mbed_official 121:7f86b4238bec 3985 #define DMA_CDNE_CADN_SHIFT (6U)
mbed_official 121:7f86b4238bec 3986 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
mbed_official 121:7f86b4238bec 3987 #define DMA_CDNE_NOP_MASK (0x80U)
mbed_official 121:7f86b4238bec 3988 #define DMA_CDNE_NOP_SHIFT (7U)
mbed_official 121:7f86b4238bec 3989 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
mbed_official 121:7f86b4238bec 3990
mbed_official 121:7f86b4238bec 3991 /*! @name SSRT - Set START Bit Register */
mbed_official 121:7f86b4238bec 3992 #define DMA_SSRT_SSRT_MASK (0xFU)
mbed_official 121:7f86b4238bec 3993 #define DMA_SSRT_SSRT_SHIFT (0U)
mbed_official 121:7f86b4238bec 3994 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
mbed_official 121:7f86b4238bec 3995 #define DMA_SSRT_SAST_MASK (0x40U)
mbed_official 121:7f86b4238bec 3996 #define DMA_SSRT_SAST_SHIFT (6U)
mbed_official 121:7f86b4238bec 3997 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
mbed_official 121:7f86b4238bec 3998 #define DMA_SSRT_NOP_MASK (0x80U)
mbed_official 121:7f86b4238bec 3999 #define DMA_SSRT_NOP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4000 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
mbed_official 121:7f86b4238bec 4001
mbed_official 121:7f86b4238bec 4002 /*! @name CERR - Clear Error Register */
mbed_official 121:7f86b4238bec 4003 #define DMA_CERR_CERR_MASK (0xFU)
mbed_official 121:7f86b4238bec 4004 #define DMA_CERR_CERR_SHIFT (0U)
mbed_official 121:7f86b4238bec 4005 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
mbed_official 121:7f86b4238bec 4006 #define DMA_CERR_CAEI_MASK (0x40U)
mbed_official 121:7f86b4238bec 4007 #define DMA_CERR_CAEI_SHIFT (6U)
mbed_official 121:7f86b4238bec 4008 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
mbed_official 121:7f86b4238bec 4009 #define DMA_CERR_NOP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4010 #define DMA_CERR_NOP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4011 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
mbed_official 121:7f86b4238bec 4012
mbed_official 121:7f86b4238bec 4013 /*! @name CINT - Clear Interrupt Request Register */
mbed_official 121:7f86b4238bec 4014 #define DMA_CINT_CINT_MASK (0xFU)
mbed_official 121:7f86b4238bec 4015 #define DMA_CINT_CINT_SHIFT (0U)
mbed_official 121:7f86b4238bec 4016 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
mbed_official 121:7f86b4238bec 4017 #define DMA_CINT_CAIR_MASK (0x40U)
mbed_official 121:7f86b4238bec 4018 #define DMA_CINT_CAIR_SHIFT (6U)
mbed_official 121:7f86b4238bec 4019 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
mbed_official 121:7f86b4238bec 4020 #define DMA_CINT_NOP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4021 #define DMA_CINT_NOP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4022 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
mbed_official 121:7f86b4238bec 4023
mbed_official 121:7f86b4238bec 4024 /*! @name INT - Interrupt Request Register */
mbed_official 121:7f86b4238bec 4025 #define DMA_INT_INT0_MASK (0x1U)
mbed_official 121:7f86b4238bec 4026 #define DMA_INT_INT0_SHIFT (0U)
mbed_official 121:7f86b4238bec 4027 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
mbed_official 121:7f86b4238bec 4028 #define DMA_INT_INT1_MASK (0x2U)
mbed_official 121:7f86b4238bec 4029 #define DMA_INT_INT1_SHIFT (1U)
mbed_official 121:7f86b4238bec 4030 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
mbed_official 121:7f86b4238bec 4031 #define DMA_INT_INT2_MASK (0x4U)
mbed_official 121:7f86b4238bec 4032 #define DMA_INT_INT2_SHIFT (2U)
mbed_official 121:7f86b4238bec 4033 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
mbed_official 121:7f86b4238bec 4034 #define DMA_INT_INT3_MASK (0x8U)
mbed_official 121:7f86b4238bec 4035 #define DMA_INT_INT3_SHIFT (3U)
mbed_official 121:7f86b4238bec 4036 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
mbed_official 121:7f86b4238bec 4037 #define DMA_INT_INT4_MASK (0x10U)
mbed_official 121:7f86b4238bec 4038 #define DMA_INT_INT4_SHIFT (4U)
mbed_official 121:7f86b4238bec 4039 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
mbed_official 121:7f86b4238bec 4040 #define DMA_INT_INT5_MASK (0x20U)
mbed_official 121:7f86b4238bec 4041 #define DMA_INT_INT5_SHIFT (5U)
mbed_official 121:7f86b4238bec 4042 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
mbed_official 121:7f86b4238bec 4043 #define DMA_INT_INT6_MASK (0x40U)
mbed_official 121:7f86b4238bec 4044 #define DMA_INT_INT6_SHIFT (6U)
mbed_official 121:7f86b4238bec 4045 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
mbed_official 121:7f86b4238bec 4046 #define DMA_INT_INT7_MASK (0x80U)
mbed_official 121:7f86b4238bec 4047 #define DMA_INT_INT7_SHIFT (7U)
mbed_official 121:7f86b4238bec 4048 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
mbed_official 121:7f86b4238bec 4049 #define DMA_INT_INT8_MASK (0x100U)
mbed_official 121:7f86b4238bec 4050 #define DMA_INT_INT8_SHIFT (8U)
mbed_official 121:7f86b4238bec 4051 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
mbed_official 121:7f86b4238bec 4052 #define DMA_INT_INT9_MASK (0x200U)
mbed_official 121:7f86b4238bec 4053 #define DMA_INT_INT9_SHIFT (9U)
mbed_official 121:7f86b4238bec 4054 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
mbed_official 121:7f86b4238bec 4055 #define DMA_INT_INT10_MASK (0x400U)
mbed_official 121:7f86b4238bec 4056 #define DMA_INT_INT10_SHIFT (10U)
mbed_official 121:7f86b4238bec 4057 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
mbed_official 121:7f86b4238bec 4058 #define DMA_INT_INT11_MASK (0x800U)
mbed_official 121:7f86b4238bec 4059 #define DMA_INT_INT11_SHIFT (11U)
mbed_official 121:7f86b4238bec 4060 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
mbed_official 121:7f86b4238bec 4061 #define DMA_INT_INT12_MASK (0x1000U)
mbed_official 121:7f86b4238bec 4062 #define DMA_INT_INT12_SHIFT (12U)
mbed_official 121:7f86b4238bec 4063 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
mbed_official 121:7f86b4238bec 4064 #define DMA_INT_INT13_MASK (0x2000U)
mbed_official 121:7f86b4238bec 4065 #define DMA_INT_INT13_SHIFT (13U)
mbed_official 121:7f86b4238bec 4066 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
mbed_official 121:7f86b4238bec 4067 #define DMA_INT_INT14_MASK (0x4000U)
mbed_official 121:7f86b4238bec 4068 #define DMA_INT_INT14_SHIFT (14U)
mbed_official 121:7f86b4238bec 4069 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
mbed_official 121:7f86b4238bec 4070 #define DMA_INT_INT15_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4071 #define DMA_INT_INT15_SHIFT (15U)
mbed_official 121:7f86b4238bec 4072 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
mbed_official 121:7f86b4238bec 4073
mbed_official 121:7f86b4238bec 4074 /*! @name ERR - Error Register */
mbed_official 121:7f86b4238bec 4075 #define DMA_ERR_ERR0_MASK (0x1U)
mbed_official 121:7f86b4238bec 4076 #define DMA_ERR_ERR0_SHIFT (0U)
mbed_official 121:7f86b4238bec 4077 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
mbed_official 121:7f86b4238bec 4078 #define DMA_ERR_ERR1_MASK (0x2U)
mbed_official 121:7f86b4238bec 4079 #define DMA_ERR_ERR1_SHIFT (1U)
mbed_official 121:7f86b4238bec 4080 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
mbed_official 121:7f86b4238bec 4081 #define DMA_ERR_ERR2_MASK (0x4U)
mbed_official 121:7f86b4238bec 4082 #define DMA_ERR_ERR2_SHIFT (2U)
mbed_official 121:7f86b4238bec 4083 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
mbed_official 121:7f86b4238bec 4084 #define DMA_ERR_ERR3_MASK (0x8U)
mbed_official 121:7f86b4238bec 4085 #define DMA_ERR_ERR3_SHIFT (3U)
mbed_official 121:7f86b4238bec 4086 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
mbed_official 121:7f86b4238bec 4087 #define DMA_ERR_ERR4_MASK (0x10U)
mbed_official 121:7f86b4238bec 4088 #define DMA_ERR_ERR4_SHIFT (4U)
mbed_official 121:7f86b4238bec 4089 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
mbed_official 121:7f86b4238bec 4090 #define DMA_ERR_ERR5_MASK (0x20U)
mbed_official 121:7f86b4238bec 4091 #define DMA_ERR_ERR5_SHIFT (5U)
mbed_official 121:7f86b4238bec 4092 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
mbed_official 121:7f86b4238bec 4093 #define DMA_ERR_ERR6_MASK (0x40U)
mbed_official 121:7f86b4238bec 4094 #define DMA_ERR_ERR6_SHIFT (6U)
mbed_official 121:7f86b4238bec 4095 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
mbed_official 121:7f86b4238bec 4096 #define DMA_ERR_ERR7_MASK (0x80U)
mbed_official 121:7f86b4238bec 4097 #define DMA_ERR_ERR7_SHIFT (7U)
mbed_official 121:7f86b4238bec 4098 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
mbed_official 121:7f86b4238bec 4099 #define DMA_ERR_ERR8_MASK (0x100U)
mbed_official 121:7f86b4238bec 4100 #define DMA_ERR_ERR8_SHIFT (8U)
mbed_official 121:7f86b4238bec 4101 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
mbed_official 121:7f86b4238bec 4102 #define DMA_ERR_ERR9_MASK (0x200U)
mbed_official 121:7f86b4238bec 4103 #define DMA_ERR_ERR9_SHIFT (9U)
mbed_official 121:7f86b4238bec 4104 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
mbed_official 121:7f86b4238bec 4105 #define DMA_ERR_ERR10_MASK (0x400U)
mbed_official 121:7f86b4238bec 4106 #define DMA_ERR_ERR10_SHIFT (10U)
mbed_official 121:7f86b4238bec 4107 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
mbed_official 121:7f86b4238bec 4108 #define DMA_ERR_ERR11_MASK (0x800U)
mbed_official 121:7f86b4238bec 4109 #define DMA_ERR_ERR11_SHIFT (11U)
mbed_official 121:7f86b4238bec 4110 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
mbed_official 121:7f86b4238bec 4111 #define DMA_ERR_ERR12_MASK (0x1000U)
mbed_official 121:7f86b4238bec 4112 #define DMA_ERR_ERR12_SHIFT (12U)
mbed_official 121:7f86b4238bec 4113 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
mbed_official 121:7f86b4238bec 4114 #define DMA_ERR_ERR13_MASK (0x2000U)
mbed_official 121:7f86b4238bec 4115 #define DMA_ERR_ERR13_SHIFT (13U)
mbed_official 121:7f86b4238bec 4116 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
mbed_official 121:7f86b4238bec 4117 #define DMA_ERR_ERR14_MASK (0x4000U)
mbed_official 121:7f86b4238bec 4118 #define DMA_ERR_ERR14_SHIFT (14U)
mbed_official 121:7f86b4238bec 4119 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
mbed_official 121:7f86b4238bec 4120 #define DMA_ERR_ERR15_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4121 #define DMA_ERR_ERR15_SHIFT (15U)
mbed_official 121:7f86b4238bec 4122 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
mbed_official 121:7f86b4238bec 4123
mbed_official 121:7f86b4238bec 4124 /*! @name HRS - Hardware Request Status Register */
mbed_official 121:7f86b4238bec 4125 #define DMA_HRS_HRS0_MASK (0x1U)
mbed_official 121:7f86b4238bec 4126 #define DMA_HRS_HRS0_SHIFT (0U)
mbed_official 121:7f86b4238bec 4127 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
mbed_official 121:7f86b4238bec 4128 #define DMA_HRS_HRS1_MASK (0x2U)
mbed_official 121:7f86b4238bec 4129 #define DMA_HRS_HRS1_SHIFT (1U)
mbed_official 121:7f86b4238bec 4130 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
mbed_official 121:7f86b4238bec 4131 #define DMA_HRS_HRS2_MASK (0x4U)
mbed_official 121:7f86b4238bec 4132 #define DMA_HRS_HRS2_SHIFT (2U)
mbed_official 121:7f86b4238bec 4133 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
mbed_official 121:7f86b4238bec 4134 #define DMA_HRS_HRS3_MASK (0x8U)
mbed_official 121:7f86b4238bec 4135 #define DMA_HRS_HRS3_SHIFT (3U)
mbed_official 121:7f86b4238bec 4136 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
mbed_official 121:7f86b4238bec 4137 #define DMA_HRS_HRS4_MASK (0x10U)
mbed_official 121:7f86b4238bec 4138 #define DMA_HRS_HRS4_SHIFT (4U)
mbed_official 121:7f86b4238bec 4139 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
mbed_official 121:7f86b4238bec 4140 #define DMA_HRS_HRS5_MASK (0x20U)
mbed_official 121:7f86b4238bec 4141 #define DMA_HRS_HRS5_SHIFT (5U)
mbed_official 121:7f86b4238bec 4142 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
mbed_official 121:7f86b4238bec 4143 #define DMA_HRS_HRS6_MASK (0x40U)
mbed_official 121:7f86b4238bec 4144 #define DMA_HRS_HRS6_SHIFT (6U)
mbed_official 121:7f86b4238bec 4145 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
mbed_official 121:7f86b4238bec 4146 #define DMA_HRS_HRS7_MASK (0x80U)
mbed_official 121:7f86b4238bec 4147 #define DMA_HRS_HRS7_SHIFT (7U)
mbed_official 121:7f86b4238bec 4148 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
mbed_official 121:7f86b4238bec 4149 #define DMA_HRS_HRS8_MASK (0x100U)
mbed_official 121:7f86b4238bec 4150 #define DMA_HRS_HRS8_SHIFT (8U)
mbed_official 121:7f86b4238bec 4151 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
mbed_official 121:7f86b4238bec 4152 #define DMA_HRS_HRS9_MASK (0x200U)
mbed_official 121:7f86b4238bec 4153 #define DMA_HRS_HRS9_SHIFT (9U)
mbed_official 121:7f86b4238bec 4154 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
mbed_official 121:7f86b4238bec 4155 #define DMA_HRS_HRS10_MASK (0x400U)
mbed_official 121:7f86b4238bec 4156 #define DMA_HRS_HRS10_SHIFT (10U)
mbed_official 121:7f86b4238bec 4157 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
mbed_official 121:7f86b4238bec 4158 #define DMA_HRS_HRS11_MASK (0x800U)
mbed_official 121:7f86b4238bec 4159 #define DMA_HRS_HRS11_SHIFT (11U)
mbed_official 121:7f86b4238bec 4160 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
mbed_official 121:7f86b4238bec 4161 #define DMA_HRS_HRS12_MASK (0x1000U)
mbed_official 121:7f86b4238bec 4162 #define DMA_HRS_HRS12_SHIFT (12U)
mbed_official 121:7f86b4238bec 4163 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
mbed_official 121:7f86b4238bec 4164 #define DMA_HRS_HRS13_MASK (0x2000U)
mbed_official 121:7f86b4238bec 4165 #define DMA_HRS_HRS13_SHIFT (13U)
mbed_official 121:7f86b4238bec 4166 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
mbed_official 121:7f86b4238bec 4167 #define DMA_HRS_HRS14_MASK (0x4000U)
mbed_official 121:7f86b4238bec 4168 #define DMA_HRS_HRS14_SHIFT (14U)
mbed_official 121:7f86b4238bec 4169 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
mbed_official 121:7f86b4238bec 4170 #define DMA_HRS_HRS15_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4171 #define DMA_HRS_HRS15_SHIFT (15U)
mbed_official 121:7f86b4238bec 4172 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
mbed_official 121:7f86b4238bec 4173
mbed_official 121:7f86b4238bec 4174 /*! @name DCHPRI3 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4175 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4176 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4177 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4178 #define DMA_DCHPRI3_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4179 #define DMA_DCHPRI3_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4180 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
mbed_official 121:7f86b4238bec 4181 #define DMA_DCHPRI3_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4182 #define DMA_DCHPRI3_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4183 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
mbed_official 121:7f86b4238bec 4184
mbed_official 121:7f86b4238bec 4185 /*! @name DCHPRI2 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4186 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4187 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4188 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4189 #define DMA_DCHPRI2_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4190 #define DMA_DCHPRI2_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4191 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
mbed_official 121:7f86b4238bec 4192 #define DMA_DCHPRI2_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4193 #define DMA_DCHPRI2_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4194 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
mbed_official 121:7f86b4238bec 4195
mbed_official 121:7f86b4238bec 4196 /*! @name DCHPRI1 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4197 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4198 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4199 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4200 #define DMA_DCHPRI1_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4201 #define DMA_DCHPRI1_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4202 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
mbed_official 121:7f86b4238bec 4203 #define DMA_DCHPRI1_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4204 #define DMA_DCHPRI1_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4205 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
mbed_official 121:7f86b4238bec 4206
mbed_official 121:7f86b4238bec 4207 /*! @name DCHPRI0 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4208 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4209 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4210 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4211 #define DMA_DCHPRI0_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4212 #define DMA_DCHPRI0_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4213 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
mbed_official 121:7f86b4238bec 4214 #define DMA_DCHPRI0_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4215 #define DMA_DCHPRI0_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4216 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
mbed_official 121:7f86b4238bec 4217
mbed_official 121:7f86b4238bec 4218 /*! @name DCHPRI7 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4219 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4220 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4221 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4222 #define DMA_DCHPRI7_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4223 #define DMA_DCHPRI7_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4224 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
mbed_official 121:7f86b4238bec 4225 #define DMA_DCHPRI7_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4226 #define DMA_DCHPRI7_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4227 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
mbed_official 121:7f86b4238bec 4228
mbed_official 121:7f86b4238bec 4229 /*! @name DCHPRI6 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4230 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4231 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4232 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4233 #define DMA_DCHPRI6_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4234 #define DMA_DCHPRI6_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4235 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
mbed_official 121:7f86b4238bec 4236 #define DMA_DCHPRI6_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4237 #define DMA_DCHPRI6_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4238 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
mbed_official 121:7f86b4238bec 4239
mbed_official 121:7f86b4238bec 4240 /*! @name DCHPRI5 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4241 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4242 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4243 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4244 #define DMA_DCHPRI5_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4245 #define DMA_DCHPRI5_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4246 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
mbed_official 121:7f86b4238bec 4247 #define DMA_DCHPRI5_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4248 #define DMA_DCHPRI5_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4249 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
mbed_official 121:7f86b4238bec 4250
mbed_official 121:7f86b4238bec 4251 /*! @name DCHPRI4 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4252 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4253 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4254 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4255 #define DMA_DCHPRI4_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4256 #define DMA_DCHPRI4_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4257 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
mbed_official 121:7f86b4238bec 4258 #define DMA_DCHPRI4_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4259 #define DMA_DCHPRI4_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4260 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
mbed_official 121:7f86b4238bec 4261
mbed_official 121:7f86b4238bec 4262 /*! @name DCHPRI11 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4263 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4264 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4265 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4266 #define DMA_DCHPRI11_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4267 #define DMA_DCHPRI11_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4268 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
mbed_official 121:7f86b4238bec 4269 #define DMA_DCHPRI11_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4270 #define DMA_DCHPRI11_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4271 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
mbed_official 121:7f86b4238bec 4272
mbed_official 121:7f86b4238bec 4273 /*! @name DCHPRI10 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4274 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4275 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4276 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4277 #define DMA_DCHPRI10_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4278 #define DMA_DCHPRI10_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4279 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
mbed_official 121:7f86b4238bec 4280 #define DMA_DCHPRI10_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4281 #define DMA_DCHPRI10_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4282 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
mbed_official 121:7f86b4238bec 4283
mbed_official 121:7f86b4238bec 4284 /*! @name DCHPRI9 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4285 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4286 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4287 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4288 #define DMA_DCHPRI9_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4289 #define DMA_DCHPRI9_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4290 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
mbed_official 121:7f86b4238bec 4291 #define DMA_DCHPRI9_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4292 #define DMA_DCHPRI9_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4293 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
mbed_official 121:7f86b4238bec 4294
mbed_official 121:7f86b4238bec 4295 /*! @name DCHPRI8 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4296 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4297 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4298 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4299 #define DMA_DCHPRI8_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4300 #define DMA_DCHPRI8_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4301 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
mbed_official 121:7f86b4238bec 4302 #define DMA_DCHPRI8_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4303 #define DMA_DCHPRI8_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4304 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
mbed_official 121:7f86b4238bec 4305
mbed_official 121:7f86b4238bec 4306 /*! @name DCHPRI15 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4307 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4308 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4309 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4310 #define DMA_DCHPRI15_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4311 #define DMA_DCHPRI15_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4312 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
mbed_official 121:7f86b4238bec 4313 #define DMA_DCHPRI15_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4314 #define DMA_DCHPRI15_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4315 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
mbed_official 121:7f86b4238bec 4316
mbed_official 121:7f86b4238bec 4317 /*! @name DCHPRI14 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4318 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4319 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4320 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4321 #define DMA_DCHPRI14_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4322 #define DMA_DCHPRI14_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4323 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
mbed_official 121:7f86b4238bec 4324 #define DMA_DCHPRI14_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4325 #define DMA_DCHPRI14_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4326 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
mbed_official 121:7f86b4238bec 4327
mbed_official 121:7f86b4238bec 4328 /*! @name DCHPRI13 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4329 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4330 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4331 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4332 #define DMA_DCHPRI13_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4333 #define DMA_DCHPRI13_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4334 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
mbed_official 121:7f86b4238bec 4335 #define DMA_DCHPRI13_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4336 #define DMA_DCHPRI13_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4337 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
mbed_official 121:7f86b4238bec 4338
mbed_official 121:7f86b4238bec 4339 /*! @name DCHPRI12 - Channel n Priority Register */
mbed_official 121:7f86b4238bec 4340 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
mbed_official 121:7f86b4238bec 4341 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
mbed_official 121:7f86b4238bec 4342 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
mbed_official 121:7f86b4238bec 4343 #define DMA_DCHPRI12_DPA_MASK (0x40U)
mbed_official 121:7f86b4238bec 4344 #define DMA_DCHPRI12_DPA_SHIFT (6U)
mbed_official 121:7f86b4238bec 4345 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
mbed_official 121:7f86b4238bec 4346 #define DMA_DCHPRI12_ECP_MASK (0x80U)
mbed_official 121:7f86b4238bec 4347 #define DMA_DCHPRI12_ECP_SHIFT (7U)
mbed_official 121:7f86b4238bec 4348 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
mbed_official 121:7f86b4238bec 4349
mbed_official 121:7f86b4238bec 4350 /*! @name SADDR - TCD Source Address */
mbed_official 121:7f86b4238bec 4351 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 4352 #define DMA_SADDR_SADDR_SHIFT (0U)
mbed_official 121:7f86b4238bec 4353 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
mbed_official 121:7f86b4238bec 4354
mbed_official 121:7f86b4238bec 4355 /* The count of DMA_SADDR */
mbed_official 121:7f86b4238bec 4356 #define DMA_SADDR_COUNT (16U)
mbed_official 121:7f86b4238bec 4357
mbed_official 121:7f86b4238bec 4358 /*! @name SOFF - TCD Signed Source Address Offset */
mbed_official 121:7f86b4238bec 4359 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 4360 #define DMA_SOFF_SOFF_SHIFT (0U)
mbed_official 121:7f86b4238bec 4361 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
mbed_official 121:7f86b4238bec 4362
mbed_official 121:7f86b4238bec 4363 /* The count of DMA_SOFF */
mbed_official 121:7f86b4238bec 4364 #define DMA_SOFF_COUNT (16U)
mbed_official 121:7f86b4238bec 4365
mbed_official 121:7f86b4238bec 4366 /*! @name ATTR - TCD Transfer Attributes */
mbed_official 121:7f86b4238bec 4367 #define DMA_ATTR_DSIZE_MASK (0x7U)
mbed_official 121:7f86b4238bec 4368 #define DMA_ATTR_DSIZE_SHIFT (0U)
mbed_official 121:7f86b4238bec 4369 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
mbed_official 121:7f86b4238bec 4370 #define DMA_ATTR_DMOD_MASK (0xF8U)
mbed_official 121:7f86b4238bec 4371 #define DMA_ATTR_DMOD_SHIFT (3U)
mbed_official 121:7f86b4238bec 4372 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
mbed_official 121:7f86b4238bec 4373 #define DMA_ATTR_SSIZE_MASK (0x700U)
mbed_official 121:7f86b4238bec 4374 #define DMA_ATTR_SSIZE_SHIFT (8U)
mbed_official 121:7f86b4238bec 4375 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
mbed_official 121:7f86b4238bec 4376 #define DMA_ATTR_SMOD_MASK (0xF800U)
mbed_official 121:7f86b4238bec 4377 #define DMA_ATTR_SMOD_SHIFT (11U)
mbed_official 121:7f86b4238bec 4378 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
mbed_official 121:7f86b4238bec 4379
mbed_official 121:7f86b4238bec 4380 /* The count of DMA_ATTR */
mbed_official 121:7f86b4238bec 4381 #define DMA_ATTR_COUNT (16U)
mbed_official 121:7f86b4238bec 4382
mbed_official 121:7f86b4238bec 4383 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
mbed_official 121:7f86b4238bec 4384 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 4385 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
mbed_official 121:7f86b4238bec 4386 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
mbed_official 121:7f86b4238bec 4387
mbed_official 121:7f86b4238bec 4388 /* The count of DMA_NBYTES_MLNO */
mbed_official 121:7f86b4238bec 4389 #define DMA_NBYTES_MLNO_COUNT (16U)
mbed_official 121:7f86b4238bec 4390
mbed_official 121:7f86b4238bec 4391 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
mbed_official 121:7f86b4238bec 4392 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
mbed_official 121:7f86b4238bec 4393 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
mbed_official 121:7f86b4238bec 4394 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
mbed_official 121:7f86b4238bec 4395 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 4396 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
mbed_official 121:7f86b4238bec 4397 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
mbed_official 121:7f86b4238bec 4398 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 4399 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
mbed_official 121:7f86b4238bec 4400 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
mbed_official 121:7f86b4238bec 4401
mbed_official 121:7f86b4238bec 4402 /* The count of DMA_NBYTES_MLOFFNO */
mbed_official 121:7f86b4238bec 4403 #define DMA_NBYTES_MLOFFNO_COUNT (16U)
mbed_official 121:7f86b4238bec 4404
mbed_official 121:7f86b4238bec 4405 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
mbed_official 121:7f86b4238bec 4406 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
mbed_official 121:7f86b4238bec 4407 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
mbed_official 121:7f86b4238bec 4408 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
mbed_official 121:7f86b4238bec 4409 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
mbed_official 121:7f86b4238bec 4410 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
mbed_official 121:7f86b4238bec 4411 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
mbed_official 121:7f86b4238bec 4412 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 4413 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
mbed_official 121:7f86b4238bec 4414 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
mbed_official 121:7f86b4238bec 4415 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 4416 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
mbed_official 121:7f86b4238bec 4417 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
mbed_official 121:7f86b4238bec 4418
mbed_official 121:7f86b4238bec 4419 /* The count of DMA_NBYTES_MLOFFYES */
mbed_official 121:7f86b4238bec 4420 #define DMA_NBYTES_MLOFFYES_COUNT (16U)
mbed_official 121:7f86b4238bec 4421
mbed_official 121:7f86b4238bec 4422 /*! @name SLAST - TCD Last Source Address Adjustment */
mbed_official 121:7f86b4238bec 4423 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 4424 #define DMA_SLAST_SLAST_SHIFT (0U)
mbed_official 121:7f86b4238bec 4425 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
mbed_official 121:7f86b4238bec 4426
mbed_official 121:7f86b4238bec 4427 /* The count of DMA_SLAST */
mbed_official 121:7f86b4238bec 4428 #define DMA_SLAST_COUNT (16U)
mbed_official 121:7f86b4238bec 4429
mbed_official 121:7f86b4238bec 4430 /*! @name DADDR - TCD Destination Address */
mbed_official 121:7f86b4238bec 4431 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 4432 #define DMA_DADDR_DADDR_SHIFT (0U)
mbed_official 121:7f86b4238bec 4433 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
mbed_official 121:7f86b4238bec 4434
mbed_official 121:7f86b4238bec 4435 /* The count of DMA_DADDR */
mbed_official 121:7f86b4238bec 4436 #define DMA_DADDR_COUNT (16U)
mbed_official 121:7f86b4238bec 4437
mbed_official 121:7f86b4238bec 4438 /*! @name DOFF - TCD Signed Destination Address Offset */
mbed_official 121:7f86b4238bec 4439 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 4440 #define DMA_DOFF_DOFF_SHIFT (0U)
mbed_official 121:7f86b4238bec 4441 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
mbed_official 121:7f86b4238bec 4442
mbed_official 121:7f86b4238bec 4443 /* The count of DMA_DOFF */
mbed_official 121:7f86b4238bec 4444 #define DMA_DOFF_COUNT (16U)
mbed_official 121:7f86b4238bec 4445
mbed_official 121:7f86b4238bec 4446 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
mbed_official 121:7f86b4238bec 4447 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
mbed_official 121:7f86b4238bec 4448 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
mbed_official 121:7f86b4238bec 4449 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
mbed_official 121:7f86b4238bec 4450 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4451 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
mbed_official 121:7f86b4238bec 4452 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
mbed_official 121:7f86b4238bec 4453
mbed_official 121:7f86b4238bec 4454 /* The count of DMA_CITER_ELINKNO */
mbed_official 121:7f86b4238bec 4455 #define DMA_CITER_ELINKNO_COUNT (16U)
mbed_official 121:7f86b4238bec 4456
mbed_official 121:7f86b4238bec 4457 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
mbed_official 121:7f86b4238bec 4458 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
mbed_official 121:7f86b4238bec 4459 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
mbed_official 121:7f86b4238bec 4460 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
mbed_official 121:7f86b4238bec 4461 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
mbed_official 121:7f86b4238bec 4462 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
mbed_official 121:7f86b4238bec 4463 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
mbed_official 121:7f86b4238bec 4464 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4465 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
mbed_official 121:7f86b4238bec 4466 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
mbed_official 121:7f86b4238bec 4467
mbed_official 121:7f86b4238bec 4468 /* The count of DMA_CITER_ELINKYES */
mbed_official 121:7f86b4238bec 4469 #define DMA_CITER_ELINKYES_COUNT (16U)
mbed_official 121:7f86b4238bec 4470
mbed_official 121:7f86b4238bec 4471 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
mbed_official 121:7f86b4238bec 4472 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 4473 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
mbed_official 121:7f86b4238bec 4474 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
mbed_official 121:7f86b4238bec 4475
mbed_official 121:7f86b4238bec 4476 /* The count of DMA_DLAST_SGA */
mbed_official 121:7f86b4238bec 4477 #define DMA_DLAST_SGA_COUNT (16U)
mbed_official 121:7f86b4238bec 4478
mbed_official 121:7f86b4238bec 4479 /*! @name CSR - TCD Control and Status */
mbed_official 121:7f86b4238bec 4480 #define DMA_CSR_START_MASK (0x1U)
mbed_official 121:7f86b4238bec 4481 #define DMA_CSR_START_SHIFT (0U)
mbed_official 121:7f86b4238bec 4482 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
mbed_official 121:7f86b4238bec 4483 #define DMA_CSR_INTMAJOR_MASK (0x2U)
mbed_official 121:7f86b4238bec 4484 #define DMA_CSR_INTMAJOR_SHIFT (1U)
mbed_official 121:7f86b4238bec 4485 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
mbed_official 121:7f86b4238bec 4486 #define DMA_CSR_INTHALF_MASK (0x4U)
mbed_official 121:7f86b4238bec 4487 #define DMA_CSR_INTHALF_SHIFT (2U)
mbed_official 121:7f86b4238bec 4488 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
mbed_official 121:7f86b4238bec 4489 #define DMA_CSR_DREQ_MASK (0x8U)
mbed_official 121:7f86b4238bec 4490 #define DMA_CSR_DREQ_SHIFT (3U)
mbed_official 121:7f86b4238bec 4491 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
mbed_official 121:7f86b4238bec 4492 #define DMA_CSR_ESG_MASK (0x10U)
mbed_official 121:7f86b4238bec 4493 #define DMA_CSR_ESG_SHIFT (4U)
mbed_official 121:7f86b4238bec 4494 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
mbed_official 121:7f86b4238bec 4495 #define DMA_CSR_MAJORELINK_MASK (0x20U)
mbed_official 121:7f86b4238bec 4496 #define DMA_CSR_MAJORELINK_SHIFT (5U)
mbed_official 121:7f86b4238bec 4497 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
mbed_official 121:7f86b4238bec 4498 #define DMA_CSR_ACTIVE_MASK (0x40U)
mbed_official 121:7f86b4238bec 4499 #define DMA_CSR_ACTIVE_SHIFT (6U)
mbed_official 121:7f86b4238bec 4500 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
mbed_official 121:7f86b4238bec 4501 #define DMA_CSR_DONE_MASK (0x80U)
mbed_official 121:7f86b4238bec 4502 #define DMA_CSR_DONE_SHIFT (7U)
mbed_official 121:7f86b4238bec 4503 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
mbed_official 121:7f86b4238bec 4504 #define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
mbed_official 121:7f86b4238bec 4505 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
mbed_official 121:7f86b4238bec 4506 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
mbed_official 121:7f86b4238bec 4507 #define DMA_CSR_BWC_MASK (0xC000U)
mbed_official 121:7f86b4238bec 4508 #define DMA_CSR_BWC_SHIFT (14U)
mbed_official 121:7f86b4238bec 4509 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
mbed_official 121:7f86b4238bec 4510
mbed_official 121:7f86b4238bec 4511 /* The count of DMA_CSR */
mbed_official 121:7f86b4238bec 4512 #define DMA_CSR_COUNT (16U)
mbed_official 121:7f86b4238bec 4513
mbed_official 121:7f86b4238bec 4514 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
mbed_official 121:7f86b4238bec 4515 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
mbed_official 121:7f86b4238bec 4516 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
mbed_official 121:7f86b4238bec 4517 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
mbed_official 121:7f86b4238bec 4518 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4519 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
mbed_official 121:7f86b4238bec 4520 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
mbed_official 121:7f86b4238bec 4521
mbed_official 121:7f86b4238bec 4522 /* The count of DMA_BITER_ELINKNO */
mbed_official 121:7f86b4238bec 4523 #define DMA_BITER_ELINKNO_COUNT (16U)
mbed_official 121:7f86b4238bec 4524
mbed_official 121:7f86b4238bec 4525 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
mbed_official 121:7f86b4238bec 4526 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
mbed_official 121:7f86b4238bec 4527 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
mbed_official 121:7f86b4238bec 4528 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
mbed_official 121:7f86b4238bec 4529 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
mbed_official 121:7f86b4238bec 4530 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
mbed_official 121:7f86b4238bec 4531 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
mbed_official 121:7f86b4238bec 4532 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4533 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
mbed_official 121:7f86b4238bec 4534 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
mbed_official 121:7f86b4238bec 4535
mbed_official 121:7f86b4238bec 4536 /* The count of DMA_BITER_ELINKYES */
mbed_official 121:7f86b4238bec 4537 #define DMA_BITER_ELINKYES_COUNT (16U)
mbed_official 121:7f86b4238bec 4538
mbed_official 121:7f86b4238bec 4539
mbed_official 121:7f86b4238bec 4540 /*!
mbed_official 121:7f86b4238bec 4541 * @}
mbed_official 121:7f86b4238bec 4542 */ /* end of group DMA_Register_Masks */
mbed_official 121:7f86b4238bec 4543
mbed_official 121:7f86b4238bec 4544
mbed_official 121:7f86b4238bec 4545 /* DMA - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 4546 /** Peripheral DMA base address */
mbed_official 121:7f86b4238bec 4547 #define DMA_BASE (0x40008000u)
mbed_official 121:7f86b4238bec 4548 /** Peripheral DMA base pointer */
mbed_official 121:7f86b4238bec 4549 #define DMA0 ((DMA_Type *)DMA_BASE)
mbed_official 121:7f86b4238bec 4550 /** Array initializer of DMA peripheral base addresses */
mbed_official 121:7f86b4238bec 4551 #define DMA_BASE_ADDRS { DMA_BASE }
mbed_official 121:7f86b4238bec 4552 /** Array initializer of DMA peripheral base pointers */
mbed_official 121:7f86b4238bec 4553 #define DMA_BASE_PTRS { DMA0 }
mbed_official 121:7f86b4238bec 4554 /** Interrupt vectors for the DMA peripheral type */
mbed_official 121:7f86b4238bec 4555 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
mbed_official 121:7f86b4238bec 4556 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
mbed_official 121:7f86b4238bec 4557
mbed_official 121:7f86b4238bec 4558 /*!
mbed_official 121:7f86b4238bec 4559 * @}
mbed_official 121:7f86b4238bec 4560 */ /* end of group DMA_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 4561
mbed_official 121:7f86b4238bec 4562
mbed_official 121:7f86b4238bec 4563 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 4564 -- DMAMUX Peripheral Access Layer
mbed_official 121:7f86b4238bec 4565 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 4566
mbed_official 121:7f86b4238bec 4567 /*!
mbed_official 121:7f86b4238bec 4568 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mbed_official 121:7f86b4238bec 4569 * @{
mbed_official 121:7f86b4238bec 4570 */
mbed_official 121:7f86b4238bec 4571
mbed_official 121:7f86b4238bec 4572 /** DMAMUX - Register Layout Typedef */
mbed_official 121:7f86b4238bec 4573 typedef struct {
mbed_official 121:7f86b4238bec 4574 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
mbed_official 121:7f86b4238bec 4575 } DMAMUX_Type;
mbed_official 121:7f86b4238bec 4576
mbed_official 121:7f86b4238bec 4577 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 4578 -- DMAMUX Register Masks
mbed_official 121:7f86b4238bec 4579 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 4580
mbed_official 121:7f86b4238bec 4581 /*!
mbed_official 121:7f86b4238bec 4582 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mbed_official 121:7f86b4238bec 4583 * @{
mbed_official 121:7f86b4238bec 4584 */
mbed_official 121:7f86b4238bec 4585
mbed_official 121:7f86b4238bec 4586 /*! @name CHCFG - Channel Configuration register */
mbed_official 121:7f86b4238bec 4587 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
mbed_official 121:7f86b4238bec 4588 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
mbed_official 121:7f86b4238bec 4589 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
mbed_official 121:7f86b4238bec 4590 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
mbed_official 121:7f86b4238bec 4591 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
mbed_official 121:7f86b4238bec 4592 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
mbed_official 121:7f86b4238bec 4593 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
mbed_official 121:7f86b4238bec 4594 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
mbed_official 121:7f86b4238bec 4595 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
mbed_official 121:7f86b4238bec 4596
mbed_official 121:7f86b4238bec 4597 /* The count of DMAMUX_CHCFG */
mbed_official 121:7f86b4238bec 4598 #define DMAMUX_CHCFG_COUNT (16U)
mbed_official 121:7f86b4238bec 4599
mbed_official 121:7f86b4238bec 4600
mbed_official 121:7f86b4238bec 4601 /*!
mbed_official 121:7f86b4238bec 4602 * @}
mbed_official 121:7f86b4238bec 4603 */ /* end of group DMAMUX_Register_Masks */
mbed_official 121:7f86b4238bec 4604
mbed_official 121:7f86b4238bec 4605
mbed_official 121:7f86b4238bec 4606 /* DMAMUX - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 4607 /** Peripheral DMAMUX base address */
mbed_official 121:7f86b4238bec 4608 #define DMAMUX_BASE (0x40021000u)
mbed_official 121:7f86b4238bec 4609 /** Peripheral DMAMUX base pointer */
mbed_official 121:7f86b4238bec 4610 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
mbed_official 121:7f86b4238bec 4611 /** Array initializer of DMAMUX peripheral base addresses */
mbed_official 121:7f86b4238bec 4612 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
mbed_official 121:7f86b4238bec 4613 /** Array initializer of DMAMUX peripheral base pointers */
mbed_official 121:7f86b4238bec 4614 #define DMAMUX_BASE_PTRS { DMAMUX }
mbed_official 121:7f86b4238bec 4615
mbed_official 121:7f86b4238bec 4616 /*!
mbed_official 121:7f86b4238bec 4617 * @}
mbed_official 121:7f86b4238bec 4618 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 4619
mbed_official 121:7f86b4238bec 4620
mbed_official 121:7f86b4238bec 4621 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 4622 -- ENET Peripheral Access Layer
mbed_official 121:7f86b4238bec 4623 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 4624
mbed_official 121:7f86b4238bec 4625 /*!
mbed_official 121:7f86b4238bec 4626 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
mbed_official 121:7f86b4238bec 4627 * @{
mbed_official 121:7f86b4238bec 4628 */
mbed_official 121:7f86b4238bec 4629
mbed_official 121:7f86b4238bec 4630 /** ENET - Register Layout Typedef */
mbed_official 121:7f86b4238bec 4631 typedef struct {
mbed_official 121:7f86b4238bec 4632 uint8_t RESERVED_0[4];
mbed_official 121:7f86b4238bec 4633 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 4634 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 4635 uint8_t RESERVED_1[4];
mbed_official 121:7f86b4238bec 4636 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
mbed_official 121:7f86b4238bec 4637 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
mbed_official 121:7f86b4238bec 4638 uint8_t RESERVED_2[12];
mbed_official 121:7f86b4238bec 4639 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
mbed_official 121:7f86b4238bec 4640 uint8_t RESERVED_3[24];
mbed_official 121:7f86b4238bec 4641 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
mbed_official 121:7f86b4238bec 4642 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
mbed_official 121:7f86b4238bec 4643 uint8_t RESERVED_4[28];
mbed_official 121:7f86b4238bec 4644 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
mbed_official 121:7f86b4238bec 4645 uint8_t RESERVED_5[28];
mbed_official 121:7f86b4238bec 4646 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
mbed_official 121:7f86b4238bec 4647 uint8_t RESERVED_6[60];
mbed_official 121:7f86b4238bec 4648 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
mbed_official 121:7f86b4238bec 4649 uint8_t RESERVED_7[28];
mbed_official 121:7f86b4238bec 4650 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
mbed_official 121:7f86b4238bec 4651 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
mbed_official 121:7f86b4238bec 4652 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
mbed_official 121:7f86b4238bec 4653 uint8_t RESERVED_8[40];
mbed_official 121:7f86b4238bec 4654 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
mbed_official 121:7f86b4238bec 4655 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
mbed_official 121:7f86b4238bec 4656 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
mbed_official 121:7f86b4238bec 4657 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
mbed_official 121:7f86b4238bec 4658 uint8_t RESERVED_9[28];
mbed_official 121:7f86b4238bec 4659 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
mbed_official 121:7f86b4238bec 4660 uint8_t RESERVED_10[56];
mbed_official 121:7f86b4238bec 4661 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
mbed_official 121:7f86b4238bec 4662 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
mbed_official 121:7f86b4238bec 4663 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
mbed_official 121:7f86b4238bec 4664 uint8_t RESERVED_11[4];
mbed_official 121:7f86b4238bec 4665 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
mbed_official 121:7f86b4238bec 4666 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
mbed_official 121:7f86b4238bec 4667 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
mbed_official 121:7f86b4238bec 4668 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
mbed_official 121:7f86b4238bec 4669 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
mbed_official 121:7f86b4238bec 4670 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
mbed_official 121:7f86b4238bec 4671 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
mbed_official 121:7f86b4238bec 4672 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
mbed_official 121:7f86b4238bec 4673 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
mbed_official 121:7f86b4238bec 4674 uint8_t RESERVED_12[12];
mbed_official 121:7f86b4238bec 4675 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
mbed_official 121:7f86b4238bec 4676 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
mbed_official 121:7f86b4238bec 4677 uint8_t RESERVED_13[60];
mbed_official 121:7f86b4238bec 4678 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
mbed_official 121:7f86b4238bec 4679 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
mbed_official 121:7f86b4238bec 4680 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
mbed_official 121:7f86b4238bec 4681 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
mbed_official 121:7f86b4238bec 4682 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
mbed_official 121:7f86b4238bec 4683 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
mbed_official 121:7f86b4238bec 4684 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
mbed_official 121:7f86b4238bec 4685 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
mbed_official 121:7f86b4238bec 4686 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
mbed_official 121:7f86b4238bec 4687 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
mbed_official 121:7f86b4238bec 4688 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
mbed_official 121:7f86b4238bec 4689 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
mbed_official 121:7f86b4238bec 4690 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
mbed_official 121:7f86b4238bec 4691 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
mbed_official 121:7f86b4238bec 4692 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
mbed_official 121:7f86b4238bec 4693 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
mbed_official 121:7f86b4238bec 4694 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
mbed_official 121:7f86b4238bec 4695 uint8_t RESERVED_14[4];
mbed_official 121:7f86b4238bec 4696 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
mbed_official 121:7f86b4238bec 4697 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
mbed_official 121:7f86b4238bec 4698 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
mbed_official 121:7f86b4238bec 4699 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
mbed_official 121:7f86b4238bec 4700 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
mbed_official 121:7f86b4238bec 4701 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
mbed_official 121:7f86b4238bec 4702 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
mbed_official 121:7f86b4238bec 4703 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
mbed_official 121:7f86b4238bec 4704 uint8_t RESERVED_15[4];
mbed_official 121:7f86b4238bec 4705 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
mbed_official 121:7f86b4238bec 4706 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
mbed_official 121:7f86b4238bec 4707 uint8_t RESERVED_16[12];
mbed_official 121:7f86b4238bec 4708 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
mbed_official 121:7f86b4238bec 4709 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
mbed_official 121:7f86b4238bec 4710 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
mbed_official 121:7f86b4238bec 4711 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
mbed_official 121:7f86b4238bec 4712 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
mbed_official 121:7f86b4238bec 4713 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
mbed_official 121:7f86b4238bec 4714 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
mbed_official 121:7f86b4238bec 4715 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
mbed_official 121:7f86b4238bec 4716 uint8_t RESERVED_17[4];
mbed_official 121:7f86b4238bec 4717 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
mbed_official 121:7f86b4238bec 4718 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
mbed_official 121:7f86b4238bec 4719 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
mbed_official 121:7f86b4238bec 4720 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
mbed_official 121:7f86b4238bec 4721 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
mbed_official 121:7f86b4238bec 4722 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
mbed_official 121:7f86b4238bec 4723 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
mbed_official 121:7f86b4238bec 4724 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
mbed_official 121:7f86b4238bec 4725 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
mbed_official 121:7f86b4238bec 4726 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
mbed_official 121:7f86b4238bec 4727 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
mbed_official 121:7f86b4238bec 4728 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
mbed_official 121:7f86b4238bec 4729 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
mbed_official 121:7f86b4238bec 4730 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
mbed_official 121:7f86b4238bec 4731 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
mbed_official 121:7f86b4238bec 4732 uint8_t RESERVED_18[284];
mbed_official 121:7f86b4238bec 4733 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
mbed_official 121:7f86b4238bec 4734 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
mbed_official 121:7f86b4238bec 4735 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
mbed_official 121:7f86b4238bec 4736 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
mbed_official 121:7f86b4238bec 4737 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
mbed_official 121:7f86b4238bec 4738 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
mbed_official 121:7f86b4238bec 4739 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
mbed_official 121:7f86b4238bec 4740 uint8_t RESERVED_19[488];
mbed_official 121:7f86b4238bec 4741 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
mbed_official 121:7f86b4238bec 4742 struct { /* offset: 0x608, array step: 0x8 */
mbed_official 121:7f86b4238bec 4743 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
mbed_official 121:7f86b4238bec 4744 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
mbed_official 121:7f86b4238bec 4745 } CHANNEL[4];
mbed_official 121:7f86b4238bec 4746 } ENET_Type;
mbed_official 121:7f86b4238bec 4747
mbed_official 121:7f86b4238bec 4748 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 4749 -- ENET Register Masks
mbed_official 121:7f86b4238bec 4750 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 4751
mbed_official 121:7f86b4238bec 4752 /*!
mbed_official 121:7f86b4238bec 4753 * @addtogroup ENET_Register_Masks ENET Register Masks
mbed_official 121:7f86b4238bec 4754 * @{
mbed_official 121:7f86b4238bec 4755 */
mbed_official 121:7f86b4238bec 4756
mbed_official 121:7f86b4238bec 4757 /*! @name EIR - Interrupt Event Register */
mbed_official 121:7f86b4238bec 4758 #define ENET_EIR_TS_TIMER_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4759 #define ENET_EIR_TS_TIMER_SHIFT (15U)
mbed_official 121:7f86b4238bec 4760 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
mbed_official 121:7f86b4238bec 4761 #define ENET_EIR_TS_AVAIL_MASK (0x10000U)
mbed_official 121:7f86b4238bec 4762 #define ENET_EIR_TS_AVAIL_SHIFT (16U)
mbed_official 121:7f86b4238bec 4763 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
mbed_official 121:7f86b4238bec 4764 #define ENET_EIR_WAKEUP_MASK (0x20000U)
mbed_official 121:7f86b4238bec 4765 #define ENET_EIR_WAKEUP_SHIFT (17U)
mbed_official 121:7f86b4238bec 4766 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
mbed_official 121:7f86b4238bec 4767 #define ENET_EIR_PLR_MASK (0x40000U)
mbed_official 121:7f86b4238bec 4768 #define ENET_EIR_PLR_SHIFT (18U)
mbed_official 121:7f86b4238bec 4769 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
mbed_official 121:7f86b4238bec 4770 #define ENET_EIR_UN_MASK (0x80000U)
mbed_official 121:7f86b4238bec 4771 #define ENET_EIR_UN_SHIFT (19U)
mbed_official 121:7f86b4238bec 4772 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
mbed_official 121:7f86b4238bec 4773 #define ENET_EIR_RL_MASK (0x100000U)
mbed_official 121:7f86b4238bec 4774 #define ENET_EIR_RL_SHIFT (20U)
mbed_official 121:7f86b4238bec 4775 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
mbed_official 121:7f86b4238bec 4776 #define ENET_EIR_LC_MASK (0x200000U)
mbed_official 121:7f86b4238bec 4777 #define ENET_EIR_LC_SHIFT (21U)
mbed_official 121:7f86b4238bec 4778 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
mbed_official 121:7f86b4238bec 4779 #define ENET_EIR_EBERR_MASK (0x400000U)
mbed_official 121:7f86b4238bec 4780 #define ENET_EIR_EBERR_SHIFT (22U)
mbed_official 121:7f86b4238bec 4781 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
mbed_official 121:7f86b4238bec 4782 #define ENET_EIR_MII_MASK (0x800000U)
mbed_official 121:7f86b4238bec 4783 #define ENET_EIR_MII_SHIFT (23U)
mbed_official 121:7f86b4238bec 4784 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
mbed_official 121:7f86b4238bec 4785 #define ENET_EIR_RXB_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 4786 #define ENET_EIR_RXB_SHIFT (24U)
mbed_official 121:7f86b4238bec 4787 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
mbed_official 121:7f86b4238bec 4788 #define ENET_EIR_RXF_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 4789 #define ENET_EIR_RXF_SHIFT (25U)
mbed_official 121:7f86b4238bec 4790 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
mbed_official 121:7f86b4238bec 4791 #define ENET_EIR_TXB_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 4792 #define ENET_EIR_TXB_SHIFT (26U)
mbed_official 121:7f86b4238bec 4793 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
mbed_official 121:7f86b4238bec 4794 #define ENET_EIR_TXF_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 4795 #define ENET_EIR_TXF_SHIFT (27U)
mbed_official 121:7f86b4238bec 4796 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
mbed_official 121:7f86b4238bec 4797 #define ENET_EIR_GRA_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 4798 #define ENET_EIR_GRA_SHIFT (28U)
mbed_official 121:7f86b4238bec 4799 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
mbed_official 121:7f86b4238bec 4800 #define ENET_EIR_BABT_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 4801 #define ENET_EIR_BABT_SHIFT (29U)
mbed_official 121:7f86b4238bec 4802 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
mbed_official 121:7f86b4238bec 4803 #define ENET_EIR_BABR_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 4804 #define ENET_EIR_BABR_SHIFT (30U)
mbed_official 121:7f86b4238bec 4805 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
mbed_official 121:7f86b4238bec 4806
mbed_official 121:7f86b4238bec 4807 /*! @name EIMR - Interrupt Mask Register */
mbed_official 121:7f86b4238bec 4808 #define ENET_EIMR_TS_TIMER_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4809 #define ENET_EIMR_TS_TIMER_SHIFT (15U)
mbed_official 121:7f86b4238bec 4810 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
mbed_official 121:7f86b4238bec 4811 #define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
mbed_official 121:7f86b4238bec 4812 #define ENET_EIMR_TS_AVAIL_SHIFT (16U)
mbed_official 121:7f86b4238bec 4813 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
mbed_official 121:7f86b4238bec 4814 #define ENET_EIMR_WAKEUP_MASK (0x20000U)
mbed_official 121:7f86b4238bec 4815 #define ENET_EIMR_WAKEUP_SHIFT (17U)
mbed_official 121:7f86b4238bec 4816 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
mbed_official 121:7f86b4238bec 4817 #define ENET_EIMR_PLR_MASK (0x40000U)
mbed_official 121:7f86b4238bec 4818 #define ENET_EIMR_PLR_SHIFT (18U)
mbed_official 121:7f86b4238bec 4819 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
mbed_official 121:7f86b4238bec 4820 #define ENET_EIMR_UN_MASK (0x80000U)
mbed_official 121:7f86b4238bec 4821 #define ENET_EIMR_UN_SHIFT (19U)
mbed_official 121:7f86b4238bec 4822 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
mbed_official 121:7f86b4238bec 4823 #define ENET_EIMR_RL_MASK (0x100000U)
mbed_official 121:7f86b4238bec 4824 #define ENET_EIMR_RL_SHIFT (20U)
mbed_official 121:7f86b4238bec 4825 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
mbed_official 121:7f86b4238bec 4826 #define ENET_EIMR_LC_MASK (0x200000U)
mbed_official 121:7f86b4238bec 4827 #define ENET_EIMR_LC_SHIFT (21U)
mbed_official 121:7f86b4238bec 4828 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
mbed_official 121:7f86b4238bec 4829 #define ENET_EIMR_EBERR_MASK (0x400000U)
mbed_official 121:7f86b4238bec 4830 #define ENET_EIMR_EBERR_SHIFT (22U)
mbed_official 121:7f86b4238bec 4831 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
mbed_official 121:7f86b4238bec 4832 #define ENET_EIMR_MII_MASK (0x800000U)
mbed_official 121:7f86b4238bec 4833 #define ENET_EIMR_MII_SHIFT (23U)
mbed_official 121:7f86b4238bec 4834 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
mbed_official 121:7f86b4238bec 4835 #define ENET_EIMR_RXB_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 4836 #define ENET_EIMR_RXB_SHIFT (24U)
mbed_official 121:7f86b4238bec 4837 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
mbed_official 121:7f86b4238bec 4838 #define ENET_EIMR_RXF_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 4839 #define ENET_EIMR_RXF_SHIFT (25U)
mbed_official 121:7f86b4238bec 4840 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
mbed_official 121:7f86b4238bec 4841 #define ENET_EIMR_TXB_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 4842 #define ENET_EIMR_TXB_SHIFT (26U)
mbed_official 121:7f86b4238bec 4843 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
mbed_official 121:7f86b4238bec 4844 #define ENET_EIMR_TXF_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 4845 #define ENET_EIMR_TXF_SHIFT (27U)
mbed_official 121:7f86b4238bec 4846 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
mbed_official 121:7f86b4238bec 4847 #define ENET_EIMR_GRA_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 4848 #define ENET_EIMR_GRA_SHIFT (28U)
mbed_official 121:7f86b4238bec 4849 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
mbed_official 121:7f86b4238bec 4850 #define ENET_EIMR_BABT_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 4851 #define ENET_EIMR_BABT_SHIFT (29U)
mbed_official 121:7f86b4238bec 4852 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
mbed_official 121:7f86b4238bec 4853 #define ENET_EIMR_BABR_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 4854 #define ENET_EIMR_BABR_SHIFT (30U)
mbed_official 121:7f86b4238bec 4855 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
mbed_official 121:7f86b4238bec 4856
mbed_official 121:7f86b4238bec 4857 /*! @name RDAR - Receive Descriptor Active Register */
mbed_official 121:7f86b4238bec 4858 #define ENET_RDAR_RDAR_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 4859 #define ENET_RDAR_RDAR_SHIFT (24U)
mbed_official 121:7f86b4238bec 4860 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
mbed_official 121:7f86b4238bec 4861
mbed_official 121:7f86b4238bec 4862 /*! @name TDAR - Transmit Descriptor Active Register */
mbed_official 121:7f86b4238bec 4863 #define ENET_TDAR_TDAR_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 4864 #define ENET_TDAR_TDAR_SHIFT (24U)
mbed_official 121:7f86b4238bec 4865 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
mbed_official 121:7f86b4238bec 4866
mbed_official 121:7f86b4238bec 4867 /*! @name ECR - Ethernet Control Register */
mbed_official 121:7f86b4238bec 4868 #define ENET_ECR_RESET_MASK (0x1U)
mbed_official 121:7f86b4238bec 4869 #define ENET_ECR_RESET_SHIFT (0U)
mbed_official 121:7f86b4238bec 4870 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
mbed_official 121:7f86b4238bec 4871 #define ENET_ECR_ETHEREN_MASK (0x2U)
mbed_official 121:7f86b4238bec 4872 #define ENET_ECR_ETHEREN_SHIFT (1U)
mbed_official 121:7f86b4238bec 4873 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
mbed_official 121:7f86b4238bec 4874 #define ENET_ECR_MAGICEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 4875 #define ENET_ECR_MAGICEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 4876 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
mbed_official 121:7f86b4238bec 4877 #define ENET_ECR_SLEEP_MASK (0x8U)
mbed_official 121:7f86b4238bec 4878 #define ENET_ECR_SLEEP_SHIFT (3U)
mbed_official 121:7f86b4238bec 4879 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
mbed_official 121:7f86b4238bec 4880 #define ENET_ECR_EN1588_MASK (0x10U)
mbed_official 121:7f86b4238bec 4881 #define ENET_ECR_EN1588_SHIFT (4U)
mbed_official 121:7f86b4238bec 4882 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
mbed_official 121:7f86b4238bec 4883 #define ENET_ECR_DBGEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 4884 #define ENET_ECR_DBGEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 4885 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
mbed_official 121:7f86b4238bec 4886 #define ENET_ECR_STOPEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 4887 #define ENET_ECR_STOPEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 4888 #define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
mbed_official 121:7f86b4238bec 4889 #define ENET_ECR_DBSWP_MASK (0x100U)
mbed_official 121:7f86b4238bec 4890 #define ENET_ECR_DBSWP_SHIFT (8U)
mbed_official 121:7f86b4238bec 4891 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
mbed_official 121:7f86b4238bec 4892
mbed_official 121:7f86b4238bec 4893 /*! @name MMFR - MII Management Frame Register */
mbed_official 121:7f86b4238bec 4894 #define ENET_MMFR_DATA_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 4895 #define ENET_MMFR_DATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 4896 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
mbed_official 121:7f86b4238bec 4897 #define ENET_MMFR_TA_MASK (0x30000U)
mbed_official 121:7f86b4238bec 4898 #define ENET_MMFR_TA_SHIFT (16U)
mbed_official 121:7f86b4238bec 4899 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
mbed_official 121:7f86b4238bec 4900 #define ENET_MMFR_RA_MASK (0x7C0000U)
mbed_official 121:7f86b4238bec 4901 #define ENET_MMFR_RA_SHIFT (18U)
mbed_official 121:7f86b4238bec 4902 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
mbed_official 121:7f86b4238bec 4903 #define ENET_MMFR_PA_MASK (0xF800000U)
mbed_official 121:7f86b4238bec 4904 #define ENET_MMFR_PA_SHIFT (23U)
mbed_official 121:7f86b4238bec 4905 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
mbed_official 121:7f86b4238bec 4906 #define ENET_MMFR_OP_MASK (0x30000000U)
mbed_official 121:7f86b4238bec 4907 #define ENET_MMFR_OP_SHIFT (28U)
mbed_official 121:7f86b4238bec 4908 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
mbed_official 121:7f86b4238bec 4909 #define ENET_MMFR_ST_MASK (0xC0000000U)
mbed_official 121:7f86b4238bec 4910 #define ENET_MMFR_ST_SHIFT (30U)
mbed_official 121:7f86b4238bec 4911 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
mbed_official 121:7f86b4238bec 4912
mbed_official 121:7f86b4238bec 4913 /*! @name MSCR - MII Speed Control Register */
mbed_official 121:7f86b4238bec 4914 #define ENET_MSCR_MII_SPEED_MASK (0x7EU)
mbed_official 121:7f86b4238bec 4915 #define ENET_MSCR_MII_SPEED_SHIFT (1U)
mbed_official 121:7f86b4238bec 4916 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
mbed_official 121:7f86b4238bec 4917 #define ENET_MSCR_DIS_PRE_MASK (0x80U)
mbed_official 121:7f86b4238bec 4918 #define ENET_MSCR_DIS_PRE_SHIFT (7U)
mbed_official 121:7f86b4238bec 4919 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
mbed_official 121:7f86b4238bec 4920 #define ENET_MSCR_HOLDTIME_MASK (0x700U)
mbed_official 121:7f86b4238bec 4921 #define ENET_MSCR_HOLDTIME_SHIFT (8U)
mbed_official 121:7f86b4238bec 4922 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
mbed_official 121:7f86b4238bec 4923
mbed_official 121:7f86b4238bec 4924 /*! @name MIBC - MIB Control Register */
mbed_official 121:7f86b4238bec 4925 #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 4926 #define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
mbed_official 121:7f86b4238bec 4927 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
mbed_official 121:7f86b4238bec 4928 #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 4929 #define ENET_MIBC_MIB_IDLE_SHIFT (30U)
mbed_official 121:7f86b4238bec 4930 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
mbed_official 121:7f86b4238bec 4931 #define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 4932 #define ENET_MIBC_MIB_DIS_SHIFT (31U)
mbed_official 121:7f86b4238bec 4933 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
mbed_official 121:7f86b4238bec 4934
mbed_official 121:7f86b4238bec 4935 /*! @name RCR - Receive Control Register */
mbed_official 121:7f86b4238bec 4936 #define ENET_RCR_LOOP_MASK (0x1U)
mbed_official 121:7f86b4238bec 4937 #define ENET_RCR_LOOP_SHIFT (0U)
mbed_official 121:7f86b4238bec 4938 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
mbed_official 121:7f86b4238bec 4939 #define ENET_RCR_DRT_MASK (0x2U)
mbed_official 121:7f86b4238bec 4940 #define ENET_RCR_DRT_SHIFT (1U)
mbed_official 121:7f86b4238bec 4941 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
mbed_official 121:7f86b4238bec 4942 #define ENET_RCR_MII_MODE_MASK (0x4U)
mbed_official 121:7f86b4238bec 4943 #define ENET_RCR_MII_MODE_SHIFT (2U)
mbed_official 121:7f86b4238bec 4944 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
mbed_official 121:7f86b4238bec 4945 #define ENET_RCR_PROM_MASK (0x8U)
mbed_official 121:7f86b4238bec 4946 #define ENET_RCR_PROM_SHIFT (3U)
mbed_official 121:7f86b4238bec 4947 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
mbed_official 121:7f86b4238bec 4948 #define ENET_RCR_BC_REJ_MASK (0x10U)
mbed_official 121:7f86b4238bec 4949 #define ENET_RCR_BC_REJ_SHIFT (4U)
mbed_official 121:7f86b4238bec 4950 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
mbed_official 121:7f86b4238bec 4951 #define ENET_RCR_FCE_MASK (0x20U)
mbed_official 121:7f86b4238bec 4952 #define ENET_RCR_FCE_SHIFT (5U)
mbed_official 121:7f86b4238bec 4953 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
mbed_official 121:7f86b4238bec 4954 #define ENET_RCR_RMII_MODE_MASK (0x100U)
mbed_official 121:7f86b4238bec 4955 #define ENET_RCR_RMII_MODE_SHIFT (8U)
mbed_official 121:7f86b4238bec 4956 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
mbed_official 121:7f86b4238bec 4957 #define ENET_RCR_RMII_10T_MASK (0x200U)
mbed_official 121:7f86b4238bec 4958 #define ENET_RCR_RMII_10T_SHIFT (9U)
mbed_official 121:7f86b4238bec 4959 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
mbed_official 121:7f86b4238bec 4960 #define ENET_RCR_PADEN_MASK (0x1000U)
mbed_official 121:7f86b4238bec 4961 #define ENET_RCR_PADEN_SHIFT (12U)
mbed_official 121:7f86b4238bec 4962 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
mbed_official 121:7f86b4238bec 4963 #define ENET_RCR_PAUFWD_MASK (0x2000U)
mbed_official 121:7f86b4238bec 4964 #define ENET_RCR_PAUFWD_SHIFT (13U)
mbed_official 121:7f86b4238bec 4965 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
mbed_official 121:7f86b4238bec 4966 #define ENET_RCR_CRCFWD_MASK (0x4000U)
mbed_official 121:7f86b4238bec 4967 #define ENET_RCR_CRCFWD_SHIFT (14U)
mbed_official 121:7f86b4238bec 4968 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
mbed_official 121:7f86b4238bec 4969 #define ENET_RCR_CFEN_MASK (0x8000U)
mbed_official 121:7f86b4238bec 4970 #define ENET_RCR_CFEN_SHIFT (15U)
mbed_official 121:7f86b4238bec 4971 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
mbed_official 121:7f86b4238bec 4972 #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
mbed_official 121:7f86b4238bec 4973 #define ENET_RCR_MAX_FL_SHIFT (16U)
mbed_official 121:7f86b4238bec 4974 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
mbed_official 121:7f86b4238bec 4975 #define ENET_RCR_NLC_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 4976 #define ENET_RCR_NLC_SHIFT (30U)
mbed_official 121:7f86b4238bec 4977 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
mbed_official 121:7f86b4238bec 4978 #define ENET_RCR_GRS_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 4979 #define ENET_RCR_GRS_SHIFT (31U)
mbed_official 121:7f86b4238bec 4980 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
mbed_official 121:7f86b4238bec 4981
mbed_official 121:7f86b4238bec 4982 /*! @name TCR - Transmit Control Register */
mbed_official 121:7f86b4238bec 4983 #define ENET_TCR_GTS_MASK (0x1U)
mbed_official 121:7f86b4238bec 4984 #define ENET_TCR_GTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 4985 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
mbed_official 121:7f86b4238bec 4986 #define ENET_TCR_FDEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 4987 #define ENET_TCR_FDEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 4988 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
mbed_official 121:7f86b4238bec 4989 #define ENET_TCR_TFC_PAUSE_MASK (0x8U)
mbed_official 121:7f86b4238bec 4990 #define ENET_TCR_TFC_PAUSE_SHIFT (3U)
mbed_official 121:7f86b4238bec 4991 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
mbed_official 121:7f86b4238bec 4992 #define ENET_TCR_RFC_PAUSE_MASK (0x10U)
mbed_official 121:7f86b4238bec 4993 #define ENET_TCR_RFC_PAUSE_SHIFT (4U)
mbed_official 121:7f86b4238bec 4994 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
mbed_official 121:7f86b4238bec 4995 #define ENET_TCR_ADDSEL_MASK (0xE0U)
mbed_official 121:7f86b4238bec 4996 #define ENET_TCR_ADDSEL_SHIFT (5U)
mbed_official 121:7f86b4238bec 4997 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
mbed_official 121:7f86b4238bec 4998 #define ENET_TCR_ADDINS_MASK (0x100U)
mbed_official 121:7f86b4238bec 4999 #define ENET_TCR_ADDINS_SHIFT (8U)
mbed_official 121:7f86b4238bec 5000 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
mbed_official 121:7f86b4238bec 5001 #define ENET_TCR_CRCFWD_MASK (0x200U)
mbed_official 121:7f86b4238bec 5002 #define ENET_TCR_CRCFWD_SHIFT (9U)
mbed_official 121:7f86b4238bec 5003 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
mbed_official 121:7f86b4238bec 5004
mbed_official 121:7f86b4238bec 5005 /*! @name PALR - Physical Address Lower Register */
mbed_official 121:7f86b4238bec 5006 #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5007 #define ENET_PALR_PADDR1_SHIFT (0U)
mbed_official 121:7f86b4238bec 5008 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
mbed_official 121:7f86b4238bec 5009
mbed_official 121:7f86b4238bec 5010 /*! @name PAUR - Physical Address Upper Register */
mbed_official 121:7f86b4238bec 5011 #define ENET_PAUR_TYPE_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5012 #define ENET_PAUR_TYPE_SHIFT (0U)
mbed_official 121:7f86b4238bec 5013 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
mbed_official 121:7f86b4238bec 5014 #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 5015 #define ENET_PAUR_PADDR2_SHIFT (16U)
mbed_official 121:7f86b4238bec 5016 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
mbed_official 121:7f86b4238bec 5017
mbed_official 121:7f86b4238bec 5018 /*! @name OPD - Opcode/Pause Duration Register */
mbed_official 121:7f86b4238bec 5019 #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5020 #define ENET_OPD_PAUSE_DUR_SHIFT (0U)
mbed_official 121:7f86b4238bec 5021 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
mbed_official 121:7f86b4238bec 5022 #define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 5023 #define ENET_OPD_OPCODE_SHIFT (16U)
mbed_official 121:7f86b4238bec 5024 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
mbed_official 121:7f86b4238bec 5025
mbed_official 121:7f86b4238bec 5026 /*! @name IAUR - Descriptor Individual Upper Address Register */
mbed_official 121:7f86b4238bec 5027 #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5028 #define ENET_IAUR_IADDR1_SHIFT (0U)
mbed_official 121:7f86b4238bec 5029 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
mbed_official 121:7f86b4238bec 5030
mbed_official 121:7f86b4238bec 5031 /*! @name IALR - Descriptor Individual Lower Address Register */
mbed_official 121:7f86b4238bec 5032 #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5033 #define ENET_IALR_IADDR2_SHIFT (0U)
mbed_official 121:7f86b4238bec 5034 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
mbed_official 121:7f86b4238bec 5035
mbed_official 121:7f86b4238bec 5036 /*! @name GAUR - Descriptor Group Upper Address Register */
mbed_official 121:7f86b4238bec 5037 #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5038 #define ENET_GAUR_GADDR1_SHIFT (0U)
mbed_official 121:7f86b4238bec 5039 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
mbed_official 121:7f86b4238bec 5040
mbed_official 121:7f86b4238bec 5041 /*! @name GALR - Descriptor Group Lower Address Register */
mbed_official 121:7f86b4238bec 5042 #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5043 #define ENET_GALR_GADDR2_SHIFT (0U)
mbed_official 121:7f86b4238bec 5044 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
mbed_official 121:7f86b4238bec 5045
mbed_official 121:7f86b4238bec 5046 /*! @name TFWR - Transmit FIFO Watermark Register */
mbed_official 121:7f86b4238bec 5047 #define ENET_TFWR_TFWR_MASK (0x3FU)
mbed_official 121:7f86b4238bec 5048 #define ENET_TFWR_TFWR_SHIFT (0U)
mbed_official 121:7f86b4238bec 5049 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
mbed_official 121:7f86b4238bec 5050 #define ENET_TFWR_STRFWD_MASK (0x100U)
mbed_official 121:7f86b4238bec 5051 #define ENET_TFWR_STRFWD_SHIFT (8U)
mbed_official 121:7f86b4238bec 5052 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
mbed_official 121:7f86b4238bec 5053
mbed_official 121:7f86b4238bec 5054 /*! @name RDSR - Receive Descriptor Ring Start Register */
mbed_official 121:7f86b4238bec 5055 #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
mbed_official 121:7f86b4238bec 5056 #define ENET_RDSR_R_DES_START_SHIFT (3U)
mbed_official 121:7f86b4238bec 5057 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
mbed_official 121:7f86b4238bec 5058
mbed_official 121:7f86b4238bec 5059 /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
mbed_official 121:7f86b4238bec 5060 #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
mbed_official 121:7f86b4238bec 5061 #define ENET_TDSR_X_DES_START_SHIFT (3U)
mbed_official 121:7f86b4238bec 5062 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
mbed_official 121:7f86b4238bec 5063
mbed_official 121:7f86b4238bec 5064 /*! @name MRBR - Maximum Receive Buffer Size Register */
mbed_official 121:7f86b4238bec 5065 #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
mbed_official 121:7f86b4238bec 5066 #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
mbed_official 121:7f86b4238bec 5067 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
mbed_official 121:7f86b4238bec 5068
mbed_official 121:7f86b4238bec 5069 /*! @name RSFL - Receive FIFO Section Full Threshold */
mbed_official 121:7f86b4238bec 5070 #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5071 #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
mbed_official 121:7f86b4238bec 5072 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
mbed_official 121:7f86b4238bec 5073
mbed_official 121:7f86b4238bec 5074 /*! @name RSEM - Receive FIFO Section Empty Threshold */
mbed_official 121:7f86b4238bec 5075 #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5076 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
mbed_official 121:7f86b4238bec 5077 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
mbed_official 121:7f86b4238bec 5078 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
mbed_official 121:7f86b4238bec 5079 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
mbed_official 121:7f86b4238bec 5080 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
mbed_official 121:7f86b4238bec 5081
mbed_official 121:7f86b4238bec 5082 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
mbed_official 121:7f86b4238bec 5083 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5084 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
mbed_official 121:7f86b4238bec 5085 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
mbed_official 121:7f86b4238bec 5086
mbed_official 121:7f86b4238bec 5087 /*! @name RAFL - Receive FIFO Almost Full Threshold */
mbed_official 121:7f86b4238bec 5088 #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5089 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
mbed_official 121:7f86b4238bec 5090 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
mbed_official 121:7f86b4238bec 5091
mbed_official 121:7f86b4238bec 5092 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
mbed_official 121:7f86b4238bec 5093 #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5094 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
mbed_official 121:7f86b4238bec 5095 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
mbed_official 121:7f86b4238bec 5096
mbed_official 121:7f86b4238bec 5097 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
mbed_official 121:7f86b4238bec 5098 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5099 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
mbed_official 121:7f86b4238bec 5100 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
mbed_official 121:7f86b4238bec 5101
mbed_official 121:7f86b4238bec 5102 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
mbed_official 121:7f86b4238bec 5103 #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5104 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
mbed_official 121:7f86b4238bec 5105 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
mbed_official 121:7f86b4238bec 5106
mbed_official 121:7f86b4238bec 5107 /*! @name TIPG - Transmit Inter-Packet Gap */
mbed_official 121:7f86b4238bec 5108 #define ENET_TIPG_IPG_MASK (0x1FU)
mbed_official 121:7f86b4238bec 5109 #define ENET_TIPG_IPG_SHIFT (0U)
mbed_official 121:7f86b4238bec 5110 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
mbed_official 121:7f86b4238bec 5111
mbed_official 121:7f86b4238bec 5112 /*! @name FTRL - Frame Truncation Length */
mbed_official 121:7f86b4238bec 5113 #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
mbed_official 121:7f86b4238bec 5114 #define ENET_FTRL_TRUNC_FL_SHIFT (0U)
mbed_official 121:7f86b4238bec 5115 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
mbed_official 121:7f86b4238bec 5116
mbed_official 121:7f86b4238bec 5117 /*! @name TACC - Transmit Accelerator Function Configuration */
mbed_official 121:7f86b4238bec 5118 #define ENET_TACC_SHIFT16_MASK (0x1U)
mbed_official 121:7f86b4238bec 5119 #define ENET_TACC_SHIFT16_SHIFT (0U)
mbed_official 121:7f86b4238bec 5120 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
mbed_official 121:7f86b4238bec 5121 #define ENET_TACC_IPCHK_MASK (0x8U)
mbed_official 121:7f86b4238bec 5122 #define ENET_TACC_IPCHK_SHIFT (3U)
mbed_official 121:7f86b4238bec 5123 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
mbed_official 121:7f86b4238bec 5124 #define ENET_TACC_PROCHK_MASK (0x10U)
mbed_official 121:7f86b4238bec 5125 #define ENET_TACC_PROCHK_SHIFT (4U)
mbed_official 121:7f86b4238bec 5126 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
mbed_official 121:7f86b4238bec 5127
mbed_official 121:7f86b4238bec 5128 /*! @name RACC - Receive Accelerator Function Configuration */
mbed_official 121:7f86b4238bec 5129 #define ENET_RACC_PADREM_MASK (0x1U)
mbed_official 121:7f86b4238bec 5130 #define ENET_RACC_PADREM_SHIFT (0U)
mbed_official 121:7f86b4238bec 5131 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
mbed_official 121:7f86b4238bec 5132 #define ENET_RACC_IPDIS_MASK (0x2U)
mbed_official 121:7f86b4238bec 5133 #define ENET_RACC_IPDIS_SHIFT (1U)
mbed_official 121:7f86b4238bec 5134 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
mbed_official 121:7f86b4238bec 5135 #define ENET_RACC_PRODIS_MASK (0x4U)
mbed_official 121:7f86b4238bec 5136 #define ENET_RACC_PRODIS_SHIFT (2U)
mbed_official 121:7f86b4238bec 5137 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
mbed_official 121:7f86b4238bec 5138 #define ENET_RACC_LINEDIS_MASK (0x40U)
mbed_official 121:7f86b4238bec 5139 #define ENET_RACC_LINEDIS_SHIFT (6U)
mbed_official 121:7f86b4238bec 5140 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
mbed_official 121:7f86b4238bec 5141 #define ENET_RACC_SHIFT16_MASK (0x80U)
mbed_official 121:7f86b4238bec 5142 #define ENET_RACC_SHIFT16_SHIFT (7U)
mbed_official 121:7f86b4238bec 5143 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
mbed_official 121:7f86b4238bec 5144
mbed_official 121:7f86b4238bec 5145 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
mbed_official 121:7f86b4238bec 5146 #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5147 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5148 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5149
mbed_official 121:7f86b4238bec 5150 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
mbed_official 121:7f86b4238bec 5151 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5152 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5153 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5154
mbed_official 121:7f86b4238bec 5155 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
mbed_official 121:7f86b4238bec 5156 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5157 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5158 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5159
mbed_official 121:7f86b4238bec 5160 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
mbed_official 121:7f86b4238bec 5161 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5162 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5163 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5164
mbed_official 121:7f86b4238bec 5165 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
mbed_official 121:7f86b4238bec 5166 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5167 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5168 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5169
mbed_official 121:7f86b4238bec 5170 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
mbed_official 121:7f86b4238bec 5171 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5172 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5173 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5174
mbed_official 121:7f86b4238bec 5175 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
mbed_official 121:7f86b4238bec 5176 #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5177 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5178 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5179
mbed_official 121:7f86b4238bec 5180 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
mbed_official 121:7f86b4238bec 5181 #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5182 #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5183 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5184
mbed_official 121:7f86b4238bec 5185 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
mbed_official 121:7f86b4238bec 5186 #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5187 #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5188 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5189
mbed_official 121:7f86b4238bec 5190 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5191 #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5192 #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5193 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5194
mbed_official 121:7f86b4238bec 5195 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5196 #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5197 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5198 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5199
mbed_official 121:7f86b4238bec 5200 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5201 #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5202 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5203 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5204
mbed_official 121:7f86b4238bec 5205 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5206 #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5207 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5208 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5209
mbed_official 121:7f86b4238bec 5210 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5211 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5212 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5213 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5214
mbed_official 121:7f86b4238bec 5215 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5216 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5217 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5218 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5219
mbed_official 121:7f86b4238bec 5220 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
mbed_official 121:7f86b4238bec 5221 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5222 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5223 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
mbed_official 121:7f86b4238bec 5224
mbed_official 121:7f86b4238bec 5225 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
mbed_official 121:7f86b4238bec 5226 #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5227 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
mbed_official 121:7f86b4238bec 5228 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
mbed_official 121:7f86b4238bec 5229
mbed_official 121:7f86b4238bec 5230 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
mbed_official 121:7f86b4238bec 5231 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5232 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5233 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
mbed_official 121:7f86b4238bec 5234
mbed_official 121:7f86b4238bec 5235 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
mbed_official 121:7f86b4238bec 5236 #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5237 #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5238 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
mbed_official 121:7f86b4238bec 5239
mbed_official 121:7f86b4238bec 5240 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
mbed_official 121:7f86b4238bec 5241 #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5242 #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5243 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
mbed_official 121:7f86b4238bec 5244
mbed_official 121:7f86b4238bec 5245 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
mbed_official 121:7f86b4238bec 5246 #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5247 #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5248 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
mbed_official 121:7f86b4238bec 5249
mbed_official 121:7f86b4238bec 5250 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
mbed_official 121:7f86b4238bec 5251 #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5252 #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5253 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
mbed_official 121:7f86b4238bec 5254
mbed_official 121:7f86b4238bec 5255 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
mbed_official 121:7f86b4238bec 5256 #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5257 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5258 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
mbed_official 121:7f86b4238bec 5259
mbed_official 121:7f86b4238bec 5260 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
mbed_official 121:7f86b4238bec 5261 #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5262 #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5263 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
mbed_official 121:7f86b4238bec 5264
mbed_official 121:7f86b4238bec 5265 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
mbed_official 121:7f86b4238bec 5266 #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5267 #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5268 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
mbed_official 121:7f86b4238bec 5269
mbed_official 121:7f86b4238bec 5270 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
mbed_official 121:7f86b4238bec 5271 #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5272 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5273 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
mbed_official 121:7f86b4238bec 5274
mbed_official 121:7f86b4238bec 5275 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
mbed_official 121:7f86b4238bec 5276 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5277 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5278 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
mbed_official 121:7f86b4238bec 5279
mbed_official 121:7f86b4238bec 5280 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
mbed_official 121:7f86b4238bec 5281 #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5282 #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5283 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
mbed_official 121:7f86b4238bec 5284
mbed_official 121:7f86b4238bec 5285 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
mbed_official 121:7f86b4238bec 5286 #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5287 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5288 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
mbed_official 121:7f86b4238bec 5289
mbed_official 121:7f86b4238bec 5290 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
mbed_official 121:7f86b4238bec 5291 #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5292 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5293 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
mbed_official 121:7f86b4238bec 5294
mbed_official 121:7f86b4238bec 5295 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
mbed_official 121:7f86b4238bec 5296 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5297 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5298 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
mbed_official 121:7f86b4238bec 5299
mbed_official 121:7f86b4238bec 5300 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
mbed_official 121:7f86b4238bec 5301 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5302 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5303 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
mbed_official 121:7f86b4238bec 5304
mbed_official 121:7f86b4238bec 5305 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
mbed_official 121:7f86b4238bec 5306 #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5307 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5308 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
mbed_official 121:7f86b4238bec 5309
mbed_official 121:7f86b4238bec 5310 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
mbed_official 121:7f86b4238bec 5311 #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5312 #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5313 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
mbed_official 121:7f86b4238bec 5314
mbed_official 121:7f86b4238bec 5315 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
mbed_official 121:7f86b4238bec 5316 #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5317 #define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5318 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
mbed_official 121:7f86b4238bec 5319
mbed_official 121:7f86b4238bec 5320 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5321 #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5322 #define ENET_RMON_R_P64_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5323 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
mbed_official 121:7f86b4238bec 5324
mbed_official 121:7f86b4238bec 5325 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5326 #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5327 #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5328 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
mbed_official 121:7f86b4238bec 5329
mbed_official 121:7f86b4238bec 5330 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5331 #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5332 #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5333 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
mbed_official 121:7f86b4238bec 5334
mbed_official 121:7f86b4238bec 5335 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5336 #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5337 #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5338 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
mbed_official 121:7f86b4238bec 5339
mbed_official 121:7f86b4238bec 5340 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5341 #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5342 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5343 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
mbed_official 121:7f86b4238bec 5344
mbed_official 121:7f86b4238bec 5345 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
mbed_official 121:7f86b4238bec 5346 #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5347 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5348 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
mbed_official 121:7f86b4238bec 5349
mbed_official 121:7f86b4238bec 5350 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
mbed_official 121:7f86b4238bec 5351 #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5352 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5353 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
mbed_official 121:7f86b4238bec 5354
mbed_official 121:7f86b4238bec 5355 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
mbed_official 121:7f86b4238bec 5356 #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5357 #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5358 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
mbed_official 121:7f86b4238bec 5359
mbed_official 121:7f86b4238bec 5360 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
mbed_official 121:7f86b4238bec 5361 #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5362 #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5363 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
mbed_official 121:7f86b4238bec 5364
mbed_official 121:7f86b4238bec 5365 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
mbed_official 121:7f86b4238bec 5366 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5367 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5368 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
mbed_official 121:7f86b4238bec 5369
mbed_official 121:7f86b4238bec 5370 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
mbed_official 121:7f86b4238bec 5371 #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5372 #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5373 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
mbed_official 121:7f86b4238bec 5374
mbed_official 121:7f86b4238bec 5375 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
mbed_official 121:7f86b4238bec 5376 #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5377 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5378 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
mbed_official 121:7f86b4238bec 5379
mbed_official 121:7f86b4238bec 5380 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
mbed_official 121:7f86b4238bec 5381 #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5382 #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5383 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
mbed_official 121:7f86b4238bec 5384
mbed_official 121:7f86b4238bec 5385 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
mbed_official 121:7f86b4238bec 5386 #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 5387 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5388 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
mbed_official 121:7f86b4238bec 5389
mbed_official 121:7f86b4238bec 5390 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
mbed_official 121:7f86b4238bec 5391 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5392 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 5393 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
mbed_official 121:7f86b4238bec 5394
mbed_official 121:7f86b4238bec 5395 /*! @name ATCR - Adjustable Timer Control Register */
mbed_official 121:7f86b4238bec 5396 #define ENET_ATCR_EN_MASK (0x1U)
mbed_official 121:7f86b4238bec 5397 #define ENET_ATCR_EN_SHIFT (0U)
mbed_official 121:7f86b4238bec 5398 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
mbed_official 121:7f86b4238bec 5399 #define ENET_ATCR_OFFEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 5400 #define ENET_ATCR_OFFEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 5401 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
mbed_official 121:7f86b4238bec 5402 #define ENET_ATCR_OFFRST_MASK (0x8U)
mbed_official 121:7f86b4238bec 5403 #define ENET_ATCR_OFFRST_SHIFT (3U)
mbed_official 121:7f86b4238bec 5404 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
mbed_official 121:7f86b4238bec 5405 #define ENET_ATCR_PEREN_MASK (0x10U)
mbed_official 121:7f86b4238bec 5406 #define ENET_ATCR_PEREN_SHIFT (4U)
mbed_official 121:7f86b4238bec 5407 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
mbed_official 121:7f86b4238bec 5408 #define ENET_ATCR_PINPER_MASK (0x80U)
mbed_official 121:7f86b4238bec 5409 #define ENET_ATCR_PINPER_SHIFT (7U)
mbed_official 121:7f86b4238bec 5410 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
mbed_official 121:7f86b4238bec 5411 #define ENET_ATCR_RESTART_MASK (0x200U)
mbed_official 121:7f86b4238bec 5412 #define ENET_ATCR_RESTART_SHIFT (9U)
mbed_official 121:7f86b4238bec 5413 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
mbed_official 121:7f86b4238bec 5414 #define ENET_ATCR_CAPTURE_MASK (0x800U)
mbed_official 121:7f86b4238bec 5415 #define ENET_ATCR_CAPTURE_SHIFT (11U)
mbed_official 121:7f86b4238bec 5416 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
mbed_official 121:7f86b4238bec 5417 #define ENET_ATCR_SLAVE_MASK (0x2000U)
mbed_official 121:7f86b4238bec 5418 #define ENET_ATCR_SLAVE_SHIFT (13U)
mbed_official 121:7f86b4238bec 5419 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
mbed_official 121:7f86b4238bec 5420
mbed_official 121:7f86b4238bec 5421 /*! @name ATVR - Timer Value Register */
mbed_official 121:7f86b4238bec 5422 #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5423 #define ENET_ATVR_ATIME_SHIFT (0U)
mbed_official 121:7f86b4238bec 5424 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
mbed_official 121:7f86b4238bec 5425
mbed_official 121:7f86b4238bec 5426 /*! @name ATOFF - Timer Offset Register */
mbed_official 121:7f86b4238bec 5427 #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5428 #define ENET_ATOFF_OFFSET_SHIFT (0U)
mbed_official 121:7f86b4238bec 5429 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
mbed_official 121:7f86b4238bec 5430
mbed_official 121:7f86b4238bec 5431 /*! @name ATPER - Timer Period Register */
mbed_official 121:7f86b4238bec 5432 #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5433 #define ENET_ATPER_PERIOD_SHIFT (0U)
mbed_official 121:7f86b4238bec 5434 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
mbed_official 121:7f86b4238bec 5435
mbed_official 121:7f86b4238bec 5436 /*! @name ATCOR - Timer Correction Register */
mbed_official 121:7f86b4238bec 5437 #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
mbed_official 121:7f86b4238bec 5438 #define ENET_ATCOR_COR_SHIFT (0U)
mbed_official 121:7f86b4238bec 5439 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
mbed_official 121:7f86b4238bec 5440
mbed_official 121:7f86b4238bec 5441 /*! @name ATINC - Time-Stamping Clock Period Register */
mbed_official 121:7f86b4238bec 5442 #define ENET_ATINC_INC_MASK (0x7FU)
mbed_official 121:7f86b4238bec 5443 #define ENET_ATINC_INC_SHIFT (0U)
mbed_official 121:7f86b4238bec 5444 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
mbed_official 121:7f86b4238bec 5445 #define ENET_ATINC_INC_CORR_MASK (0x7F00U)
mbed_official 121:7f86b4238bec 5446 #define ENET_ATINC_INC_CORR_SHIFT (8U)
mbed_official 121:7f86b4238bec 5447 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
mbed_official 121:7f86b4238bec 5448
mbed_official 121:7f86b4238bec 5449 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
mbed_official 121:7f86b4238bec 5450 #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5451 #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
mbed_official 121:7f86b4238bec 5452 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
mbed_official 121:7f86b4238bec 5453
mbed_official 121:7f86b4238bec 5454 /*! @name TGSR - Timer Global Status Register */
mbed_official 121:7f86b4238bec 5455 #define ENET_TGSR_TF0_MASK (0x1U)
mbed_official 121:7f86b4238bec 5456 #define ENET_TGSR_TF0_SHIFT (0U)
mbed_official 121:7f86b4238bec 5457 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
mbed_official 121:7f86b4238bec 5458 #define ENET_TGSR_TF1_MASK (0x2U)
mbed_official 121:7f86b4238bec 5459 #define ENET_TGSR_TF1_SHIFT (1U)
mbed_official 121:7f86b4238bec 5460 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
mbed_official 121:7f86b4238bec 5461 #define ENET_TGSR_TF2_MASK (0x4U)
mbed_official 121:7f86b4238bec 5462 #define ENET_TGSR_TF2_SHIFT (2U)
mbed_official 121:7f86b4238bec 5463 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
mbed_official 121:7f86b4238bec 5464 #define ENET_TGSR_TF3_MASK (0x8U)
mbed_official 121:7f86b4238bec 5465 #define ENET_TGSR_TF3_SHIFT (3U)
mbed_official 121:7f86b4238bec 5466 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
mbed_official 121:7f86b4238bec 5467
mbed_official 121:7f86b4238bec 5468 /*! @name TCSR - Timer Control Status Register */
mbed_official 121:7f86b4238bec 5469 #define ENET_TCSR_TDRE_MASK (0x1U)
mbed_official 121:7f86b4238bec 5470 #define ENET_TCSR_TDRE_SHIFT (0U)
mbed_official 121:7f86b4238bec 5471 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
mbed_official 121:7f86b4238bec 5472 #define ENET_TCSR_TMODE_MASK (0x3CU)
mbed_official 121:7f86b4238bec 5473 #define ENET_TCSR_TMODE_SHIFT (2U)
mbed_official 121:7f86b4238bec 5474 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
mbed_official 121:7f86b4238bec 5475 #define ENET_TCSR_TIE_MASK (0x40U)
mbed_official 121:7f86b4238bec 5476 #define ENET_TCSR_TIE_SHIFT (6U)
mbed_official 121:7f86b4238bec 5477 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
mbed_official 121:7f86b4238bec 5478 #define ENET_TCSR_TF_MASK (0x80U)
mbed_official 121:7f86b4238bec 5479 #define ENET_TCSR_TF_SHIFT (7U)
mbed_official 121:7f86b4238bec 5480 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
mbed_official 121:7f86b4238bec 5481
mbed_official 121:7f86b4238bec 5482 /* The count of ENET_TCSR */
mbed_official 121:7f86b4238bec 5483 #define ENET_TCSR_COUNT (4U)
mbed_official 121:7f86b4238bec 5484
mbed_official 121:7f86b4238bec 5485 /*! @name TCCR - Timer Compare Capture Register */
mbed_official 121:7f86b4238bec 5486 #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5487 #define ENET_TCCR_TCC_SHIFT (0U)
mbed_official 121:7f86b4238bec 5488 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
mbed_official 121:7f86b4238bec 5489
mbed_official 121:7f86b4238bec 5490 /* The count of ENET_TCCR */
mbed_official 121:7f86b4238bec 5491 #define ENET_TCCR_COUNT (4U)
mbed_official 121:7f86b4238bec 5492
mbed_official 121:7f86b4238bec 5493
mbed_official 121:7f86b4238bec 5494 /*!
mbed_official 121:7f86b4238bec 5495 * @}
mbed_official 121:7f86b4238bec 5496 */ /* end of group ENET_Register_Masks */
mbed_official 121:7f86b4238bec 5497
mbed_official 121:7f86b4238bec 5498
mbed_official 121:7f86b4238bec 5499 /* ENET - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 5500 /** Peripheral ENET base address */
mbed_official 121:7f86b4238bec 5501 #define ENET_BASE (0x400C0000u)
mbed_official 121:7f86b4238bec 5502 /** Peripheral ENET base pointer */
mbed_official 121:7f86b4238bec 5503 #define ENET ((ENET_Type *)ENET_BASE)
mbed_official 121:7f86b4238bec 5504 /** Array initializer of ENET peripheral base addresses */
mbed_official 121:7f86b4238bec 5505 #define ENET_BASE_ADDRS { ENET_BASE }
mbed_official 121:7f86b4238bec 5506 /** Array initializer of ENET peripheral base pointers */
mbed_official 121:7f86b4238bec 5507 #define ENET_BASE_PTRS { ENET }
mbed_official 121:7f86b4238bec 5508 /** Interrupt vectors for the ENET peripheral type */
mbed_official 121:7f86b4238bec 5509 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
mbed_official 121:7f86b4238bec 5510 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
mbed_official 121:7f86b4238bec 5511 #define ENET_Error_IRQS { ENET_Error_IRQn }
mbed_official 121:7f86b4238bec 5512 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
mbed_official 121:7f86b4238bec 5513
mbed_official 121:7f86b4238bec 5514 /*!
mbed_official 121:7f86b4238bec 5515 * @}
mbed_official 121:7f86b4238bec 5516 */ /* end of group ENET_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 5517
mbed_official 121:7f86b4238bec 5518
mbed_official 121:7f86b4238bec 5519 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 5520 -- EWM Peripheral Access Layer
mbed_official 121:7f86b4238bec 5521 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 5522
mbed_official 121:7f86b4238bec 5523 /*!
mbed_official 121:7f86b4238bec 5524 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
mbed_official 121:7f86b4238bec 5525 * @{
mbed_official 121:7f86b4238bec 5526 */
mbed_official 121:7f86b4238bec 5527
mbed_official 121:7f86b4238bec 5528 /** EWM - Register Layout Typedef */
mbed_official 121:7f86b4238bec 5529 typedef struct {
mbed_official 121:7f86b4238bec 5530 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 5531 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
mbed_official 121:7f86b4238bec 5532 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
mbed_official 121:7f86b4238bec 5533 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
mbed_official 121:7f86b4238bec 5534 } EWM_Type;
mbed_official 121:7f86b4238bec 5535
mbed_official 121:7f86b4238bec 5536 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 5537 -- EWM Register Masks
mbed_official 121:7f86b4238bec 5538 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 5539
mbed_official 121:7f86b4238bec 5540 /*!
mbed_official 121:7f86b4238bec 5541 * @addtogroup EWM_Register_Masks EWM Register Masks
mbed_official 121:7f86b4238bec 5542 * @{
mbed_official 121:7f86b4238bec 5543 */
mbed_official 121:7f86b4238bec 5544
mbed_official 121:7f86b4238bec 5545 /*! @name CTRL - Control Register */
mbed_official 121:7f86b4238bec 5546 #define EWM_CTRL_EWMEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 5547 #define EWM_CTRL_EWMEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 5548 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
mbed_official 121:7f86b4238bec 5549 #define EWM_CTRL_ASSIN_MASK (0x2U)
mbed_official 121:7f86b4238bec 5550 #define EWM_CTRL_ASSIN_SHIFT (1U)
mbed_official 121:7f86b4238bec 5551 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
mbed_official 121:7f86b4238bec 5552 #define EWM_CTRL_INEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 5553 #define EWM_CTRL_INEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 5554 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
mbed_official 121:7f86b4238bec 5555 #define EWM_CTRL_INTEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 5556 #define EWM_CTRL_INTEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 5557 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
mbed_official 121:7f86b4238bec 5558
mbed_official 121:7f86b4238bec 5559 /*! @name SERV - Service Register */
mbed_official 121:7f86b4238bec 5560 #define EWM_SERV_SERVICE_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5561 #define EWM_SERV_SERVICE_SHIFT (0U)
mbed_official 121:7f86b4238bec 5562 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
mbed_official 121:7f86b4238bec 5563
mbed_official 121:7f86b4238bec 5564 /*! @name CMPL - Compare Low Register */
mbed_official 121:7f86b4238bec 5565 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5566 #define EWM_CMPL_COMPAREL_SHIFT (0U)
mbed_official 121:7f86b4238bec 5567 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
mbed_official 121:7f86b4238bec 5568
mbed_official 121:7f86b4238bec 5569 /*! @name CMPH - Compare High Register */
mbed_official 121:7f86b4238bec 5570 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
mbed_official 121:7f86b4238bec 5571 #define EWM_CMPH_COMPAREH_SHIFT (0U)
mbed_official 121:7f86b4238bec 5572 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
mbed_official 121:7f86b4238bec 5573
mbed_official 121:7f86b4238bec 5574
mbed_official 121:7f86b4238bec 5575 /*!
mbed_official 121:7f86b4238bec 5576 * @}
mbed_official 121:7f86b4238bec 5577 */ /* end of group EWM_Register_Masks */
mbed_official 121:7f86b4238bec 5578
mbed_official 121:7f86b4238bec 5579
mbed_official 121:7f86b4238bec 5580 /* EWM - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 5581 /** Peripheral EWM base address */
mbed_official 121:7f86b4238bec 5582 #define EWM_BASE (0x40061000u)
mbed_official 121:7f86b4238bec 5583 /** Peripheral EWM base pointer */
mbed_official 121:7f86b4238bec 5584 #define EWM ((EWM_Type *)EWM_BASE)
mbed_official 121:7f86b4238bec 5585 /** Array initializer of EWM peripheral base addresses */
mbed_official 121:7f86b4238bec 5586 #define EWM_BASE_ADDRS { EWM_BASE }
mbed_official 121:7f86b4238bec 5587 /** Array initializer of EWM peripheral base pointers */
mbed_official 121:7f86b4238bec 5588 #define EWM_BASE_PTRS { EWM }
mbed_official 121:7f86b4238bec 5589 /** Interrupt vectors for the EWM peripheral type */
mbed_official 121:7f86b4238bec 5590 #define EWM_IRQS { WDOG_EWM_IRQn }
mbed_official 121:7f86b4238bec 5591
mbed_official 121:7f86b4238bec 5592 /*!
mbed_official 121:7f86b4238bec 5593 * @}
mbed_official 121:7f86b4238bec 5594 */ /* end of group EWM_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 5595
mbed_official 121:7f86b4238bec 5596
mbed_official 121:7f86b4238bec 5597 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 5598 -- FB Peripheral Access Layer
mbed_official 121:7f86b4238bec 5599 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 5600
mbed_official 121:7f86b4238bec 5601 /*!
mbed_official 121:7f86b4238bec 5602 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
mbed_official 121:7f86b4238bec 5603 * @{
mbed_official 121:7f86b4238bec 5604 */
mbed_official 121:7f86b4238bec 5605
mbed_official 121:7f86b4238bec 5606 /** FB - Register Layout Typedef */
mbed_official 121:7f86b4238bec 5607 typedef struct {
mbed_official 121:7f86b4238bec 5608 struct { /* offset: 0x0, array step: 0xC */
mbed_official 121:7f86b4238bec 5609 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
mbed_official 121:7f86b4238bec 5610 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
mbed_official 121:7f86b4238bec 5611 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
mbed_official 121:7f86b4238bec 5612 } CS[6];
mbed_official 121:7f86b4238bec 5613 uint8_t RESERVED_0[24];
mbed_official 121:7f86b4238bec 5614 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
mbed_official 121:7f86b4238bec 5615 } FB_Type;
mbed_official 121:7f86b4238bec 5616
mbed_official 121:7f86b4238bec 5617 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 5618 -- FB Register Masks
mbed_official 121:7f86b4238bec 5619 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 5620
mbed_official 121:7f86b4238bec 5621 /*!
mbed_official 121:7f86b4238bec 5622 * @addtogroup FB_Register_Masks FB Register Masks
mbed_official 121:7f86b4238bec 5623 * @{
mbed_official 121:7f86b4238bec 5624 */
mbed_official 121:7f86b4238bec 5625
mbed_official 121:7f86b4238bec 5626 /*! @name CSAR - Chip Select Address Register */
mbed_official 121:7f86b4238bec 5627 #define FB_CSAR_BA_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 5628 #define FB_CSAR_BA_SHIFT (16U)
mbed_official 121:7f86b4238bec 5629 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
mbed_official 121:7f86b4238bec 5630
mbed_official 121:7f86b4238bec 5631 /* The count of FB_CSAR */
mbed_official 121:7f86b4238bec 5632 #define FB_CSAR_COUNT (6U)
mbed_official 121:7f86b4238bec 5633
mbed_official 121:7f86b4238bec 5634 /*! @name CSMR - Chip Select Mask Register */
mbed_official 121:7f86b4238bec 5635 #define FB_CSMR_V_MASK (0x1U)
mbed_official 121:7f86b4238bec 5636 #define FB_CSMR_V_SHIFT (0U)
mbed_official 121:7f86b4238bec 5637 #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
mbed_official 121:7f86b4238bec 5638 #define FB_CSMR_WP_MASK (0x100U)
mbed_official 121:7f86b4238bec 5639 #define FB_CSMR_WP_SHIFT (8U)
mbed_official 121:7f86b4238bec 5640 #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
mbed_official 121:7f86b4238bec 5641 #define FB_CSMR_BAM_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 5642 #define FB_CSMR_BAM_SHIFT (16U)
mbed_official 121:7f86b4238bec 5643 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
mbed_official 121:7f86b4238bec 5644
mbed_official 121:7f86b4238bec 5645 /* The count of FB_CSMR */
mbed_official 121:7f86b4238bec 5646 #define FB_CSMR_COUNT (6U)
mbed_official 121:7f86b4238bec 5647
mbed_official 121:7f86b4238bec 5648 /*! @name CSCR - Chip Select Control Register */
mbed_official 121:7f86b4238bec 5649 #define FB_CSCR_BSTW_MASK (0x8U)
mbed_official 121:7f86b4238bec 5650 #define FB_CSCR_BSTW_SHIFT (3U)
mbed_official 121:7f86b4238bec 5651 #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
mbed_official 121:7f86b4238bec 5652 #define FB_CSCR_BSTR_MASK (0x10U)
mbed_official 121:7f86b4238bec 5653 #define FB_CSCR_BSTR_SHIFT (4U)
mbed_official 121:7f86b4238bec 5654 #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
mbed_official 121:7f86b4238bec 5655 #define FB_CSCR_BEM_MASK (0x20U)
mbed_official 121:7f86b4238bec 5656 #define FB_CSCR_BEM_SHIFT (5U)
mbed_official 121:7f86b4238bec 5657 #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
mbed_official 121:7f86b4238bec 5658 #define FB_CSCR_PS_MASK (0xC0U)
mbed_official 121:7f86b4238bec 5659 #define FB_CSCR_PS_SHIFT (6U)
mbed_official 121:7f86b4238bec 5660 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
mbed_official 121:7f86b4238bec 5661 #define FB_CSCR_AA_MASK (0x100U)
mbed_official 121:7f86b4238bec 5662 #define FB_CSCR_AA_SHIFT (8U)
mbed_official 121:7f86b4238bec 5663 #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
mbed_official 121:7f86b4238bec 5664 #define FB_CSCR_BLS_MASK (0x200U)
mbed_official 121:7f86b4238bec 5665 #define FB_CSCR_BLS_SHIFT (9U)
mbed_official 121:7f86b4238bec 5666 #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
mbed_official 121:7f86b4238bec 5667 #define FB_CSCR_WS_MASK (0xFC00U)
mbed_official 121:7f86b4238bec 5668 #define FB_CSCR_WS_SHIFT (10U)
mbed_official 121:7f86b4238bec 5669 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
mbed_official 121:7f86b4238bec 5670 #define FB_CSCR_WRAH_MASK (0x30000U)
mbed_official 121:7f86b4238bec 5671 #define FB_CSCR_WRAH_SHIFT (16U)
mbed_official 121:7f86b4238bec 5672 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
mbed_official 121:7f86b4238bec 5673 #define FB_CSCR_RDAH_MASK (0xC0000U)
mbed_official 121:7f86b4238bec 5674 #define FB_CSCR_RDAH_SHIFT (18U)
mbed_official 121:7f86b4238bec 5675 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
mbed_official 121:7f86b4238bec 5676 #define FB_CSCR_ASET_MASK (0x300000U)
mbed_official 121:7f86b4238bec 5677 #define FB_CSCR_ASET_SHIFT (20U)
mbed_official 121:7f86b4238bec 5678 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
mbed_official 121:7f86b4238bec 5679 #define FB_CSCR_EXTS_MASK (0x400000U)
mbed_official 121:7f86b4238bec 5680 #define FB_CSCR_EXTS_SHIFT (22U)
mbed_official 121:7f86b4238bec 5681 #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
mbed_official 121:7f86b4238bec 5682 #define FB_CSCR_SWSEN_MASK (0x800000U)
mbed_official 121:7f86b4238bec 5683 #define FB_CSCR_SWSEN_SHIFT (23U)
mbed_official 121:7f86b4238bec 5684 #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
mbed_official 121:7f86b4238bec 5685 #define FB_CSCR_SWS_MASK (0xFC000000U)
mbed_official 121:7f86b4238bec 5686 #define FB_CSCR_SWS_SHIFT (26U)
mbed_official 121:7f86b4238bec 5687 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
mbed_official 121:7f86b4238bec 5688
mbed_official 121:7f86b4238bec 5689 /* The count of FB_CSCR */
mbed_official 121:7f86b4238bec 5690 #define FB_CSCR_COUNT (6U)
mbed_official 121:7f86b4238bec 5691
mbed_official 121:7f86b4238bec 5692 /*! @name CSPMCR - Chip Select port Multiplexing Control Register */
mbed_official 121:7f86b4238bec 5693 #define FB_CSPMCR_GROUP5_MASK (0xF000U)
mbed_official 121:7f86b4238bec 5694 #define FB_CSPMCR_GROUP5_SHIFT (12U)
mbed_official 121:7f86b4238bec 5695 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
mbed_official 121:7f86b4238bec 5696 #define FB_CSPMCR_GROUP4_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 5697 #define FB_CSPMCR_GROUP4_SHIFT (16U)
mbed_official 121:7f86b4238bec 5698 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
mbed_official 121:7f86b4238bec 5699 #define FB_CSPMCR_GROUP3_MASK (0xF00000U)
mbed_official 121:7f86b4238bec 5700 #define FB_CSPMCR_GROUP3_SHIFT (20U)
mbed_official 121:7f86b4238bec 5701 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
mbed_official 121:7f86b4238bec 5702 #define FB_CSPMCR_GROUP2_MASK (0xF000000U)
mbed_official 121:7f86b4238bec 5703 #define FB_CSPMCR_GROUP2_SHIFT (24U)
mbed_official 121:7f86b4238bec 5704 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
mbed_official 121:7f86b4238bec 5705 #define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 5706 #define FB_CSPMCR_GROUP1_SHIFT (28U)
mbed_official 121:7f86b4238bec 5707 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
mbed_official 121:7f86b4238bec 5708
mbed_official 121:7f86b4238bec 5709
mbed_official 121:7f86b4238bec 5710 /*!
mbed_official 121:7f86b4238bec 5711 * @}
mbed_official 121:7f86b4238bec 5712 */ /* end of group FB_Register_Masks */
mbed_official 121:7f86b4238bec 5713
mbed_official 121:7f86b4238bec 5714
mbed_official 121:7f86b4238bec 5715 /* FB - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 5716 /** Peripheral FB base address */
mbed_official 121:7f86b4238bec 5717 #define FB_BASE (0x4000C000u)
mbed_official 121:7f86b4238bec 5718 /** Peripheral FB base pointer */
mbed_official 121:7f86b4238bec 5719 #define FB ((FB_Type *)FB_BASE)
mbed_official 121:7f86b4238bec 5720 /** Array initializer of FB peripheral base addresses */
mbed_official 121:7f86b4238bec 5721 #define FB_BASE_ADDRS { FB_BASE }
mbed_official 121:7f86b4238bec 5722 /** Array initializer of FB peripheral base pointers */
mbed_official 121:7f86b4238bec 5723 #define FB_BASE_PTRS { FB }
mbed_official 121:7f86b4238bec 5724
mbed_official 121:7f86b4238bec 5725 /*!
mbed_official 121:7f86b4238bec 5726 * @}
mbed_official 121:7f86b4238bec 5727 */ /* end of group FB_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 5728
mbed_official 121:7f86b4238bec 5729
mbed_official 121:7f86b4238bec 5730 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 5731 -- FMC Peripheral Access Layer
mbed_official 121:7f86b4238bec 5732 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 5733
mbed_official 121:7f86b4238bec 5734 /*!
mbed_official 121:7f86b4238bec 5735 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
mbed_official 121:7f86b4238bec 5736 * @{
mbed_official 121:7f86b4238bec 5737 */
mbed_official 121:7f86b4238bec 5738
mbed_official 121:7f86b4238bec 5739 /** FMC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 5740 typedef struct {
mbed_official 121:7f86b4238bec 5741 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 5742 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 5743 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 5744 uint8_t RESERVED_0[244];
mbed_official 121:7f86b4238bec 5745 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
mbed_official 121:7f86b4238bec 5746 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
mbed_official 121:7f86b4238bec 5747 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
mbed_official 121:7f86b4238bec 5748 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
mbed_official 121:7f86b4238bec 5749 uint8_t RESERVED_1[192];
mbed_official 121:7f86b4238bec 5750 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
mbed_official 121:7f86b4238bec 5751 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
mbed_official 121:7f86b4238bec 5752 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
mbed_official 121:7f86b4238bec 5753 } SET[4][4];
mbed_official 121:7f86b4238bec 5754 } FMC_Type;
mbed_official 121:7f86b4238bec 5755
mbed_official 121:7f86b4238bec 5756 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 5757 -- FMC Register Masks
mbed_official 121:7f86b4238bec 5758 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 5759
mbed_official 121:7f86b4238bec 5760 /*!
mbed_official 121:7f86b4238bec 5761 * @addtogroup FMC_Register_Masks FMC Register Masks
mbed_official 121:7f86b4238bec 5762 * @{
mbed_official 121:7f86b4238bec 5763 */
mbed_official 121:7f86b4238bec 5764
mbed_official 121:7f86b4238bec 5765 /*! @name PFAPR - Flash Access Protection Register */
mbed_official 121:7f86b4238bec 5766 #define FMC_PFAPR_M0AP_MASK (0x3U)
mbed_official 121:7f86b4238bec 5767 #define FMC_PFAPR_M0AP_SHIFT (0U)
mbed_official 121:7f86b4238bec 5768 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
mbed_official 121:7f86b4238bec 5769 #define FMC_PFAPR_M1AP_MASK (0xCU)
mbed_official 121:7f86b4238bec 5770 #define FMC_PFAPR_M1AP_SHIFT (2U)
mbed_official 121:7f86b4238bec 5771 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
mbed_official 121:7f86b4238bec 5772 #define FMC_PFAPR_M2AP_MASK (0x30U)
mbed_official 121:7f86b4238bec 5773 #define FMC_PFAPR_M2AP_SHIFT (4U)
mbed_official 121:7f86b4238bec 5774 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
mbed_official 121:7f86b4238bec 5775 #define FMC_PFAPR_M3AP_MASK (0xC0U)
mbed_official 121:7f86b4238bec 5776 #define FMC_PFAPR_M3AP_SHIFT (6U)
mbed_official 121:7f86b4238bec 5777 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
mbed_official 121:7f86b4238bec 5778 #define FMC_PFAPR_M4AP_MASK (0x300U)
mbed_official 121:7f86b4238bec 5779 #define FMC_PFAPR_M4AP_SHIFT (8U)
mbed_official 121:7f86b4238bec 5780 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
mbed_official 121:7f86b4238bec 5781 #define FMC_PFAPR_M5AP_MASK (0xC00U)
mbed_official 121:7f86b4238bec 5782 #define FMC_PFAPR_M5AP_SHIFT (10U)
mbed_official 121:7f86b4238bec 5783 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
mbed_official 121:7f86b4238bec 5784 #define FMC_PFAPR_M6AP_MASK (0x3000U)
mbed_official 121:7f86b4238bec 5785 #define FMC_PFAPR_M6AP_SHIFT (12U)
mbed_official 121:7f86b4238bec 5786 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
mbed_official 121:7f86b4238bec 5787 #define FMC_PFAPR_M7AP_MASK (0xC000U)
mbed_official 121:7f86b4238bec 5788 #define FMC_PFAPR_M7AP_SHIFT (14U)
mbed_official 121:7f86b4238bec 5789 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
mbed_official 121:7f86b4238bec 5790 #define FMC_PFAPR_M0PFD_MASK (0x10000U)
mbed_official 121:7f86b4238bec 5791 #define FMC_PFAPR_M0PFD_SHIFT (16U)
mbed_official 121:7f86b4238bec 5792 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
mbed_official 121:7f86b4238bec 5793 #define FMC_PFAPR_M1PFD_MASK (0x20000U)
mbed_official 121:7f86b4238bec 5794 #define FMC_PFAPR_M1PFD_SHIFT (17U)
mbed_official 121:7f86b4238bec 5795 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
mbed_official 121:7f86b4238bec 5796 #define FMC_PFAPR_M2PFD_MASK (0x40000U)
mbed_official 121:7f86b4238bec 5797 #define FMC_PFAPR_M2PFD_SHIFT (18U)
mbed_official 121:7f86b4238bec 5798 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
mbed_official 121:7f86b4238bec 5799 #define FMC_PFAPR_M3PFD_MASK (0x80000U)
mbed_official 121:7f86b4238bec 5800 #define FMC_PFAPR_M3PFD_SHIFT (19U)
mbed_official 121:7f86b4238bec 5801 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
mbed_official 121:7f86b4238bec 5802 #define FMC_PFAPR_M4PFD_MASK (0x100000U)
mbed_official 121:7f86b4238bec 5803 #define FMC_PFAPR_M4PFD_SHIFT (20U)
mbed_official 121:7f86b4238bec 5804 #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
mbed_official 121:7f86b4238bec 5805 #define FMC_PFAPR_M5PFD_MASK (0x200000U)
mbed_official 121:7f86b4238bec 5806 #define FMC_PFAPR_M5PFD_SHIFT (21U)
mbed_official 121:7f86b4238bec 5807 #define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
mbed_official 121:7f86b4238bec 5808 #define FMC_PFAPR_M6PFD_MASK (0x400000U)
mbed_official 121:7f86b4238bec 5809 #define FMC_PFAPR_M6PFD_SHIFT (22U)
mbed_official 121:7f86b4238bec 5810 #define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
mbed_official 121:7f86b4238bec 5811 #define FMC_PFAPR_M7PFD_MASK (0x800000U)
mbed_official 121:7f86b4238bec 5812 #define FMC_PFAPR_M7PFD_SHIFT (23U)
mbed_official 121:7f86b4238bec 5813 #define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
mbed_official 121:7f86b4238bec 5814
mbed_official 121:7f86b4238bec 5815 /*! @name PFB0CR - Flash Bank 0 Control Register */
mbed_official 121:7f86b4238bec 5816 #define FMC_PFB0CR_B0SEBE_MASK (0x1U)
mbed_official 121:7f86b4238bec 5817 #define FMC_PFB0CR_B0SEBE_SHIFT (0U)
mbed_official 121:7f86b4238bec 5818 #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
mbed_official 121:7f86b4238bec 5819 #define FMC_PFB0CR_B0IPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 5820 #define FMC_PFB0CR_B0IPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 5821 #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
mbed_official 121:7f86b4238bec 5822 #define FMC_PFB0CR_B0DPE_MASK (0x4U)
mbed_official 121:7f86b4238bec 5823 #define FMC_PFB0CR_B0DPE_SHIFT (2U)
mbed_official 121:7f86b4238bec 5824 #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
mbed_official 121:7f86b4238bec 5825 #define FMC_PFB0CR_B0ICE_MASK (0x8U)
mbed_official 121:7f86b4238bec 5826 #define FMC_PFB0CR_B0ICE_SHIFT (3U)
mbed_official 121:7f86b4238bec 5827 #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
mbed_official 121:7f86b4238bec 5828 #define FMC_PFB0CR_B0DCE_MASK (0x10U)
mbed_official 121:7f86b4238bec 5829 #define FMC_PFB0CR_B0DCE_SHIFT (4U)
mbed_official 121:7f86b4238bec 5830 #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
mbed_official 121:7f86b4238bec 5831 #define FMC_PFB0CR_CRC_MASK (0xE0U)
mbed_official 121:7f86b4238bec 5832 #define FMC_PFB0CR_CRC_SHIFT (5U)
mbed_official 121:7f86b4238bec 5833 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
mbed_official 121:7f86b4238bec 5834 #define FMC_PFB0CR_B0MW_MASK (0x60000U)
mbed_official 121:7f86b4238bec 5835 #define FMC_PFB0CR_B0MW_SHIFT (17U)
mbed_official 121:7f86b4238bec 5836 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
mbed_official 121:7f86b4238bec 5837 #define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
mbed_official 121:7f86b4238bec 5838 #define FMC_PFB0CR_S_B_INV_SHIFT (19U)
mbed_official 121:7f86b4238bec 5839 #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
mbed_official 121:7f86b4238bec 5840 #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
mbed_official 121:7f86b4238bec 5841 #define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
mbed_official 121:7f86b4238bec 5842 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
mbed_official 121:7f86b4238bec 5843 #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
mbed_official 121:7f86b4238bec 5844 #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
mbed_official 121:7f86b4238bec 5845 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
mbed_official 121:7f86b4238bec 5846 #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 5847 #define FMC_PFB0CR_B0RWSC_SHIFT (28U)
mbed_official 121:7f86b4238bec 5848 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
mbed_official 121:7f86b4238bec 5849
mbed_official 121:7f86b4238bec 5850 /*! @name PFB1CR - Flash Bank 1 Control Register */
mbed_official 121:7f86b4238bec 5851 #define FMC_PFB1CR_B1SEBE_MASK (0x1U)
mbed_official 121:7f86b4238bec 5852 #define FMC_PFB1CR_B1SEBE_SHIFT (0U)
mbed_official 121:7f86b4238bec 5853 #define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
mbed_official 121:7f86b4238bec 5854 #define FMC_PFB1CR_B1IPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 5855 #define FMC_PFB1CR_B1IPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 5856 #define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
mbed_official 121:7f86b4238bec 5857 #define FMC_PFB1CR_B1DPE_MASK (0x4U)
mbed_official 121:7f86b4238bec 5858 #define FMC_PFB1CR_B1DPE_SHIFT (2U)
mbed_official 121:7f86b4238bec 5859 #define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
mbed_official 121:7f86b4238bec 5860 #define FMC_PFB1CR_B1ICE_MASK (0x8U)
mbed_official 121:7f86b4238bec 5861 #define FMC_PFB1CR_B1ICE_SHIFT (3U)
mbed_official 121:7f86b4238bec 5862 #define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
mbed_official 121:7f86b4238bec 5863 #define FMC_PFB1CR_B1DCE_MASK (0x10U)
mbed_official 121:7f86b4238bec 5864 #define FMC_PFB1CR_B1DCE_SHIFT (4U)
mbed_official 121:7f86b4238bec 5865 #define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
mbed_official 121:7f86b4238bec 5866 #define FMC_PFB1CR_B1MW_MASK (0x60000U)
mbed_official 121:7f86b4238bec 5867 #define FMC_PFB1CR_B1MW_SHIFT (17U)
mbed_official 121:7f86b4238bec 5868 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
mbed_official 121:7f86b4238bec 5869 #define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 5870 #define FMC_PFB1CR_B1RWSC_SHIFT (28U)
mbed_official 121:7f86b4238bec 5871 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
mbed_official 121:7f86b4238bec 5872
mbed_official 121:7f86b4238bec 5873 /*! @name TAGVDW0S - Cache Tag Storage */
mbed_official 121:7f86b4238bec 5874 #define FMC_TAGVDW0S_valid_MASK (0x1U)
mbed_official 121:7f86b4238bec 5875 #define FMC_TAGVDW0S_valid_SHIFT (0U)
mbed_official 121:7f86b4238bec 5876 #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
mbed_official 121:7f86b4238bec 5877 #define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
mbed_official 121:7f86b4238bec 5878 #define FMC_TAGVDW0S_tag_SHIFT (5U)
mbed_official 121:7f86b4238bec 5879 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
mbed_official 121:7f86b4238bec 5880
mbed_official 121:7f86b4238bec 5881 /* The count of FMC_TAGVDW0S */
mbed_official 121:7f86b4238bec 5882 #define FMC_TAGVDW0S_COUNT (4U)
mbed_official 121:7f86b4238bec 5883
mbed_official 121:7f86b4238bec 5884 /*! @name TAGVDW1S - Cache Tag Storage */
mbed_official 121:7f86b4238bec 5885 #define FMC_TAGVDW1S_valid_MASK (0x1U)
mbed_official 121:7f86b4238bec 5886 #define FMC_TAGVDW1S_valid_SHIFT (0U)
mbed_official 121:7f86b4238bec 5887 #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
mbed_official 121:7f86b4238bec 5888 #define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
mbed_official 121:7f86b4238bec 5889 #define FMC_TAGVDW1S_tag_SHIFT (5U)
mbed_official 121:7f86b4238bec 5890 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
mbed_official 121:7f86b4238bec 5891
mbed_official 121:7f86b4238bec 5892 /* The count of FMC_TAGVDW1S */
mbed_official 121:7f86b4238bec 5893 #define FMC_TAGVDW1S_COUNT (4U)
mbed_official 121:7f86b4238bec 5894
mbed_official 121:7f86b4238bec 5895 /*! @name TAGVDW2S - Cache Tag Storage */
mbed_official 121:7f86b4238bec 5896 #define FMC_TAGVDW2S_valid_MASK (0x1U)
mbed_official 121:7f86b4238bec 5897 #define FMC_TAGVDW2S_valid_SHIFT (0U)
mbed_official 121:7f86b4238bec 5898 #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
mbed_official 121:7f86b4238bec 5899 #define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
mbed_official 121:7f86b4238bec 5900 #define FMC_TAGVDW2S_tag_SHIFT (5U)
mbed_official 121:7f86b4238bec 5901 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
mbed_official 121:7f86b4238bec 5902
mbed_official 121:7f86b4238bec 5903 /* The count of FMC_TAGVDW2S */
mbed_official 121:7f86b4238bec 5904 #define FMC_TAGVDW2S_COUNT (4U)
mbed_official 121:7f86b4238bec 5905
mbed_official 121:7f86b4238bec 5906 /*! @name TAGVDW3S - Cache Tag Storage */
mbed_official 121:7f86b4238bec 5907 #define FMC_TAGVDW3S_valid_MASK (0x1U)
mbed_official 121:7f86b4238bec 5908 #define FMC_TAGVDW3S_valid_SHIFT (0U)
mbed_official 121:7f86b4238bec 5909 #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
mbed_official 121:7f86b4238bec 5910 #define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
mbed_official 121:7f86b4238bec 5911 #define FMC_TAGVDW3S_tag_SHIFT (5U)
mbed_official 121:7f86b4238bec 5912 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
mbed_official 121:7f86b4238bec 5913
mbed_official 121:7f86b4238bec 5914 /* The count of FMC_TAGVDW3S */
mbed_official 121:7f86b4238bec 5915 #define FMC_TAGVDW3S_COUNT (4U)
mbed_official 121:7f86b4238bec 5916
mbed_official 121:7f86b4238bec 5917 /*! @name DATA_U - Cache Data Storage (upper word) */
mbed_official 121:7f86b4238bec 5918 #define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5919 #define FMC_DATA_U_data_SHIFT (0U)
mbed_official 121:7f86b4238bec 5920 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
mbed_official 121:7f86b4238bec 5921
mbed_official 121:7f86b4238bec 5922 /* The count of FMC_DATA_U */
mbed_official 121:7f86b4238bec 5923 #define FMC_DATA_U_COUNT (4U)
mbed_official 121:7f86b4238bec 5924
mbed_official 121:7f86b4238bec 5925 /* The count of FMC_DATA_U */
mbed_official 121:7f86b4238bec 5926 #define FMC_DATA_U_COUNT2 (4U)
mbed_official 121:7f86b4238bec 5927
mbed_official 121:7f86b4238bec 5928 /*! @name DATA_L - Cache Data Storage (lower word) */
mbed_official 121:7f86b4238bec 5929 #define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 5930 #define FMC_DATA_L_data_SHIFT (0U)
mbed_official 121:7f86b4238bec 5931 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
mbed_official 121:7f86b4238bec 5932
mbed_official 121:7f86b4238bec 5933 /* The count of FMC_DATA_L */
mbed_official 121:7f86b4238bec 5934 #define FMC_DATA_L_COUNT (4U)
mbed_official 121:7f86b4238bec 5935
mbed_official 121:7f86b4238bec 5936 /* The count of FMC_DATA_L */
mbed_official 121:7f86b4238bec 5937 #define FMC_DATA_L_COUNT2 (4U)
mbed_official 121:7f86b4238bec 5938
mbed_official 121:7f86b4238bec 5939
mbed_official 121:7f86b4238bec 5940 /*!
mbed_official 121:7f86b4238bec 5941 * @}
mbed_official 121:7f86b4238bec 5942 */ /* end of group FMC_Register_Masks */
mbed_official 121:7f86b4238bec 5943
mbed_official 121:7f86b4238bec 5944
mbed_official 121:7f86b4238bec 5945 /* FMC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 5946 /** Peripheral FMC base address */
mbed_official 121:7f86b4238bec 5947 #define FMC_BASE (0x4001F000u)
mbed_official 121:7f86b4238bec 5948 /** Peripheral FMC base pointer */
mbed_official 121:7f86b4238bec 5949 #define FMC ((FMC_Type *)FMC_BASE)
mbed_official 121:7f86b4238bec 5950 /** Array initializer of FMC peripheral base addresses */
mbed_official 121:7f86b4238bec 5951 #define FMC_BASE_ADDRS { FMC_BASE }
mbed_official 121:7f86b4238bec 5952 /** Array initializer of FMC peripheral base pointers */
mbed_official 121:7f86b4238bec 5953 #define FMC_BASE_PTRS { FMC }
mbed_official 121:7f86b4238bec 5954
mbed_official 121:7f86b4238bec 5955 /*!
mbed_official 121:7f86b4238bec 5956 * @}
mbed_official 121:7f86b4238bec 5957 */ /* end of group FMC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 5958
mbed_official 121:7f86b4238bec 5959
mbed_official 121:7f86b4238bec 5960 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 5961 -- FTFE Peripheral Access Layer
mbed_official 121:7f86b4238bec 5962 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 5963
mbed_official 121:7f86b4238bec 5964 /*!
mbed_official 121:7f86b4238bec 5965 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
mbed_official 121:7f86b4238bec 5966 * @{
mbed_official 121:7f86b4238bec 5967 */
mbed_official 121:7f86b4238bec 5968
mbed_official 121:7f86b4238bec 5969 /** FTFE - Register Layout Typedef */
mbed_official 121:7f86b4238bec 5970 typedef struct {
mbed_official 121:7f86b4238bec 5971 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 5972 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mbed_official 121:7f86b4238bec 5973 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mbed_official 121:7f86b4238bec 5974 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mbed_official 121:7f86b4238bec 5975 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mbed_official 121:7f86b4238bec 5976 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mbed_official 121:7f86b4238bec 5977 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mbed_official 121:7f86b4238bec 5978 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mbed_official 121:7f86b4238bec 5979 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mbed_official 121:7f86b4238bec 5980 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mbed_official 121:7f86b4238bec 5981 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mbed_official 121:7f86b4238bec 5982 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mbed_official 121:7f86b4238bec 5983 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mbed_official 121:7f86b4238bec 5984 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mbed_official 121:7f86b4238bec 5985 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mbed_official 121:7f86b4238bec 5986 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mbed_official 121:7f86b4238bec 5987 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mbed_official 121:7f86b4238bec 5988 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mbed_official 121:7f86b4238bec 5989 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mbed_official 121:7f86b4238bec 5990 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mbed_official 121:7f86b4238bec 5991 uint8_t RESERVED_0[2];
mbed_official 121:7f86b4238bec 5992 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
mbed_official 121:7f86b4238bec 5993 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
mbed_official 121:7f86b4238bec 5994 } FTFE_Type;
mbed_official 121:7f86b4238bec 5995
mbed_official 121:7f86b4238bec 5996 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 5997 -- FTFE Register Masks
mbed_official 121:7f86b4238bec 5998 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 5999
mbed_official 121:7f86b4238bec 6000 /*!
mbed_official 121:7f86b4238bec 6001 * @addtogroup FTFE_Register_Masks FTFE Register Masks
mbed_official 121:7f86b4238bec 6002 * @{
mbed_official 121:7f86b4238bec 6003 */
mbed_official 121:7f86b4238bec 6004
mbed_official 121:7f86b4238bec 6005 /*! @name FSTAT - Flash Status Register */
mbed_official 121:7f86b4238bec 6006 #define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
mbed_official 121:7f86b4238bec 6007 #define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
mbed_official 121:7f86b4238bec 6008 #define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
mbed_official 121:7f86b4238bec 6009 #define FTFE_FSTAT_FPVIOL_MASK (0x10U)
mbed_official 121:7f86b4238bec 6010 #define FTFE_FSTAT_FPVIOL_SHIFT (4U)
mbed_official 121:7f86b4238bec 6011 #define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
mbed_official 121:7f86b4238bec 6012 #define FTFE_FSTAT_ACCERR_MASK (0x20U)
mbed_official 121:7f86b4238bec 6013 #define FTFE_FSTAT_ACCERR_SHIFT (5U)
mbed_official 121:7f86b4238bec 6014 #define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
mbed_official 121:7f86b4238bec 6015 #define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
mbed_official 121:7f86b4238bec 6016 #define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
mbed_official 121:7f86b4238bec 6017 #define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
mbed_official 121:7f86b4238bec 6018 #define FTFE_FSTAT_CCIF_MASK (0x80U)
mbed_official 121:7f86b4238bec 6019 #define FTFE_FSTAT_CCIF_SHIFT (7U)
mbed_official 121:7f86b4238bec 6020 #define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
mbed_official 121:7f86b4238bec 6021
mbed_official 121:7f86b4238bec 6022 /*! @name FCNFG - Flash Configuration Register */
mbed_official 121:7f86b4238bec 6023 #define FTFE_FCNFG_EEERDY_MASK (0x1U)
mbed_official 121:7f86b4238bec 6024 #define FTFE_FCNFG_EEERDY_SHIFT (0U)
mbed_official 121:7f86b4238bec 6025 #define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
mbed_official 121:7f86b4238bec 6026 #define FTFE_FCNFG_RAMRDY_MASK (0x2U)
mbed_official 121:7f86b4238bec 6027 #define FTFE_FCNFG_RAMRDY_SHIFT (1U)
mbed_official 121:7f86b4238bec 6028 #define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
mbed_official 121:7f86b4238bec 6029 #define FTFE_FCNFG_PFLSH_MASK (0x4U)
mbed_official 121:7f86b4238bec 6030 #define FTFE_FCNFG_PFLSH_SHIFT (2U)
mbed_official 121:7f86b4238bec 6031 #define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
mbed_official 121:7f86b4238bec 6032 #define FTFE_FCNFG_SWAP_MASK (0x8U)
mbed_official 121:7f86b4238bec 6033 #define FTFE_FCNFG_SWAP_SHIFT (3U)
mbed_official 121:7f86b4238bec 6034 #define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
mbed_official 121:7f86b4238bec 6035 #define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
mbed_official 121:7f86b4238bec 6036 #define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
mbed_official 121:7f86b4238bec 6037 #define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
mbed_official 121:7f86b4238bec 6038 #define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
mbed_official 121:7f86b4238bec 6039 #define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
mbed_official 121:7f86b4238bec 6040 #define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
mbed_official 121:7f86b4238bec 6041 #define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
mbed_official 121:7f86b4238bec 6042 #define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
mbed_official 121:7f86b4238bec 6043 #define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
mbed_official 121:7f86b4238bec 6044 #define FTFE_FCNFG_CCIE_MASK (0x80U)
mbed_official 121:7f86b4238bec 6045 #define FTFE_FCNFG_CCIE_SHIFT (7U)
mbed_official 121:7f86b4238bec 6046 #define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
mbed_official 121:7f86b4238bec 6047
mbed_official 121:7f86b4238bec 6048 /*! @name FSEC - Flash Security Register */
mbed_official 121:7f86b4238bec 6049 #define FTFE_FSEC_SEC_MASK (0x3U)
mbed_official 121:7f86b4238bec 6050 #define FTFE_FSEC_SEC_SHIFT (0U)
mbed_official 121:7f86b4238bec 6051 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
mbed_official 121:7f86b4238bec 6052 #define FTFE_FSEC_FSLACC_MASK (0xCU)
mbed_official 121:7f86b4238bec 6053 #define FTFE_FSEC_FSLACC_SHIFT (2U)
mbed_official 121:7f86b4238bec 6054 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
mbed_official 121:7f86b4238bec 6055 #define FTFE_FSEC_MEEN_MASK (0x30U)
mbed_official 121:7f86b4238bec 6056 #define FTFE_FSEC_MEEN_SHIFT (4U)
mbed_official 121:7f86b4238bec 6057 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
mbed_official 121:7f86b4238bec 6058 #define FTFE_FSEC_KEYEN_MASK (0xC0U)
mbed_official 121:7f86b4238bec 6059 #define FTFE_FSEC_KEYEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 6060 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
mbed_official 121:7f86b4238bec 6061
mbed_official 121:7f86b4238bec 6062 /*! @name FOPT - Flash Option Register */
mbed_official 121:7f86b4238bec 6063 #define FTFE_FOPT_OPT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6064 #define FTFE_FOPT_OPT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6065 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
mbed_official 121:7f86b4238bec 6066
mbed_official 121:7f86b4238bec 6067 /*! @name FCCOB3 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6068 #define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6069 #define FTFE_FCCOB3_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6070 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6071
mbed_official 121:7f86b4238bec 6072 /*! @name FCCOB2 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6073 #define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6074 #define FTFE_FCCOB2_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6075 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6076
mbed_official 121:7f86b4238bec 6077 /*! @name FCCOB1 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6078 #define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6079 #define FTFE_FCCOB1_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6080 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6081
mbed_official 121:7f86b4238bec 6082 /*! @name FCCOB0 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6083 #define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6084 #define FTFE_FCCOB0_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6085 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6086
mbed_official 121:7f86b4238bec 6087 /*! @name FCCOB7 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6088 #define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6089 #define FTFE_FCCOB7_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6090 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6091
mbed_official 121:7f86b4238bec 6092 /*! @name FCCOB6 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6093 #define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6094 #define FTFE_FCCOB6_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6095 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6096
mbed_official 121:7f86b4238bec 6097 /*! @name FCCOB5 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6098 #define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6099 #define FTFE_FCCOB5_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6100 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6101
mbed_official 121:7f86b4238bec 6102 /*! @name FCCOB4 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6103 #define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6104 #define FTFE_FCCOB4_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6105 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6106
mbed_official 121:7f86b4238bec 6107 /*! @name FCCOBB - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6108 #define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6109 #define FTFE_FCCOBB_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6110 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6111
mbed_official 121:7f86b4238bec 6112 /*! @name FCCOBA - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6113 #define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6114 #define FTFE_FCCOBA_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6115 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6116
mbed_official 121:7f86b4238bec 6117 /*! @name FCCOB9 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6118 #define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6119 #define FTFE_FCCOB9_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6120 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6121
mbed_official 121:7f86b4238bec 6122 /*! @name FCCOB8 - Flash Common Command Object Registers */
mbed_official 121:7f86b4238bec 6123 #define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6124 #define FTFE_FCCOB8_CCOBn_SHIFT (0U)
mbed_official 121:7f86b4238bec 6125 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
mbed_official 121:7f86b4238bec 6126
mbed_official 121:7f86b4238bec 6127 /*! @name FPROT3 - Program Flash Protection Registers */
mbed_official 121:7f86b4238bec 6128 #define FTFE_FPROT3_PROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6129 #define FTFE_FPROT3_PROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6130 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
mbed_official 121:7f86b4238bec 6131
mbed_official 121:7f86b4238bec 6132 /*! @name FPROT2 - Program Flash Protection Registers */
mbed_official 121:7f86b4238bec 6133 #define FTFE_FPROT2_PROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6134 #define FTFE_FPROT2_PROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6135 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
mbed_official 121:7f86b4238bec 6136
mbed_official 121:7f86b4238bec 6137 /*! @name FPROT1 - Program Flash Protection Registers */
mbed_official 121:7f86b4238bec 6138 #define FTFE_FPROT1_PROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6139 #define FTFE_FPROT1_PROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6140 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
mbed_official 121:7f86b4238bec 6141
mbed_official 121:7f86b4238bec 6142 /*! @name FPROT0 - Program Flash Protection Registers */
mbed_official 121:7f86b4238bec 6143 #define FTFE_FPROT0_PROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6144 #define FTFE_FPROT0_PROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6145 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
mbed_official 121:7f86b4238bec 6146
mbed_official 121:7f86b4238bec 6147 /*! @name FEPROT - EEPROM Protection Register */
mbed_official 121:7f86b4238bec 6148 #define FTFE_FEPROT_EPROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6149 #define FTFE_FEPROT_EPROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6150 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
mbed_official 121:7f86b4238bec 6151
mbed_official 121:7f86b4238bec 6152 /*! @name FDPROT - Data Flash Protection Register */
mbed_official 121:7f86b4238bec 6153 #define FTFE_FDPROT_DPROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 6154 #define FTFE_FDPROT_DPROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6155 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
mbed_official 121:7f86b4238bec 6156
mbed_official 121:7f86b4238bec 6157
mbed_official 121:7f86b4238bec 6158 /*!
mbed_official 121:7f86b4238bec 6159 * @}
mbed_official 121:7f86b4238bec 6160 */ /* end of group FTFE_Register_Masks */
mbed_official 121:7f86b4238bec 6161
mbed_official 121:7f86b4238bec 6162
mbed_official 121:7f86b4238bec 6163 /* FTFE - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 6164 /** Peripheral FTFE base address */
mbed_official 121:7f86b4238bec 6165 #define FTFE_BASE (0x40020000u)
mbed_official 121:7f86b4238bec 6166 /** Peripheral FTFE base pointer */
mbed_official 121:7f86b4238bec 6167 #define FTFE ((FTFE_Type *)FTFE_BASE)
mbed_official 121:7f86b4238bec 6168 /** Array initializer of FTFE peripheral base addresses */
mbed_official 121:7f86b4238bec 6169 #define FTFE_BASE_ADDRS { FTFE_BASE }
mbed_official 121:7f86b4238bec 6170 /** Array initializer of FTFE peripheral base pointers */
mbed_official 121:7f86b4238bec 6171 #define FTFE_BASE_PTRS { FTFE }
mbed_official 121:7f86b4238bec 6172 /** Interrupt vectors for the FTFE peripheral type */
mbed_official 121:7f86b4238bec 6173 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
mbed_official 121:7f86b4238bec 6174 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
mbed_official 121:7f86b4238bec 6175
mbed_official 121:7f86b4238bec 6176 /*!
mbed_official 121:7f86b4238bec 6177 * @}
mbed_official 121:7f86b4238bec 6178 */ /* end of group FTFE_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 6179
mbed_official 121:7f86b4238bec 6180
mbed_official 121:7f86b4238bec 6181 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 6182 -- FTM Peripheral Access Layer
mbed_official 121:7f86b4238bec 6183 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 6184
mbed_official 121:7f86b4238bec 6185 /*!
mbed_official 121:7f86b4238bec 6186 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
mbed_official 121:7f86b4238bec 6187 * @{
mbed_official 121:7f86b4238bec 6188 */
mbed_official 121:7f86b4238bec 6189
mbed_official 121:7f86b4238bec 6190 /** FTM - Register Layout Typedef */
mbed_official 121:7f86b4238bec 6191 typedef struct {
mbed_official 121:7f86b4238bec 6192 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
mbed_official 121:7f86b4238bec 6193 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mbed_official 121:7f86b4238bec 6194 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mbed_official 121:7f86b4238bec 6195 struct { /* offset: 0xC, array step: 0x8 */
mbed_official 121:7f86b4238bec 6196 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
mbed_official 121:7f86b4238bec 6197 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mbed_official 121:7f86b4238bec 6198 } CONTROLS[8];
mbed_official 121:7f86b4238bec 6199 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
mbed_official 121:7f86b4238bec 6200 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
mbed_official 121:7f86b4238bec 6201 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
mbed_official 121:7f86b4238bec 6202 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
mbed_official 121:7f86b4238bec 6203 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
mbed_official 121:7f86b4238bec 6204 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
mbed_official 121:7f86b4238bec 6205 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
mbed_official 121:7f86b4238bec 6206 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
mbed_official 121:7f86b4238bec 6207 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
mbed_official 121:7f86b4238bec 6208 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
mbed_official 121:7f86b4238bec 6209 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
mbed_official 121:7f86b4238bec 6210 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
mbed_official 121:7f86b4238bec 6211 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
mbed_official 121:7f86b4238bec 6212 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
mbed_official 121:7f86b4238bec 6213 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mbed_official 121:7f86b4238bec 6214 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
mbed_official 121:7f86b4238bec 6215 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
mbed_official 121:7f86b4238bec 6216 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
mbed_official 121:7f86b4238bec 6217 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
mbed_official 121:7f86b4238bec 6218 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
mbed_official 121:7f86b4238bec 6219 } FTM_Type;
mbed_official 121:7f86b4238bec 6220
mbed_official 121:7f86b4238bec 6221 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 6222 -- FTM Register Masks
mbed_official 121:7f86b4238bec 6223 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 6224
mbed_official 121:7f86b4238bec 6225 /*!
mbed_official 121:7f86b4238bec 6226 * @addtogroup FTM_Register_Masks FTM Register Masks
mbed_official 121:7f86b4238bec 6227 * @{
mbed_official 121:7f86b4238bec 6228 */
mbed_official 121:7f86b4238bec 6229
mbed_official 121:7f86b4238bec 6230 /*! @name SC - Status And Control */
mbed_official 121:7f86b4238bec 6231 #define FTM_SC_PS_MASK (0x7U)
mbed_official 121:7f86b4238bec 6232 #define FTM_SC_PS_SHIFT (0U)
mbed_official 121:7f86b4238bec 6233 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
mbed_official 121:7f86b4238bec 6234 #define FTM_SC_CLKS_MASK (0x18U)
mbed_official 121:7f86b4238bec 6235 #define FTM_SC_CLKS_SHIFT (3U)
mbed_official 121:7f86b4238bec 6236 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
mbed_official 121:7f86b4238bec 6237 #define FTM_SC_CPWMS_MASK (0x20U)
mbed_official 121:7f86b4238bec 6238 #define FTM_SC_CPWMS_SHIFT (5U)
mbed_official 121:7f86b4238bec 6239 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
mbed_official 121:7f86b4238bec 6240 #define FTM_SC_TOIE_MASK (0x40U)
mbed_official 121:7f86b4238bec 6241 #define FTM_SC_TOIE_SHIFT (6U)
mbed_official 121:7f86b4238bec 6242 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
mbed_official 121:7f86b4238bec 6243 #define FTM_SC_TOF_MASK (0x80U)
mbed_official 121:7f86b4238bec 6244 #define FTM_SC_TOF_SHIFT (7U)
mbed_official 121:7f86b4238bec 6245 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
mbed_official 121:7f86b4238bec 6246
mbed_official 121:7f86b4238bec 6247 /*! @name CNT - Counter */
mbed_official 121:7f86b4238bec 6248 #define FTM_CNT_COUNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 6249 #define FTM_CNT_COUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6250 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
mbed_official 121:7f86b4238bec 6251
mbed_official 121:7f86b4238bec 6252 /*! @name MOD - Modulo */
mbed_official 121:7f86b4238bec 6253 #define FTM_MOD_MOD_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 6254 #define FTM_MOD_MOD_SHIFT (0U)
mbed_official 121:7f86b4238bec 6255 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
mbed_official 121:7f86b4238bec 6256
mbed_official 121:7f86b4238bec 6257 /*! @name CnSC - Channel (n) Status And Control */
mbed_official 121:7f86b4238bec 6258 #define FTM_CnSC_DMA_MASK (0x1U)
mbed_official 121:7f86b4238bec 6259 #define FTM_CnSC_DMA_SHIFT (0U)
mbed_official 121:7f86b4238bec 6260 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
mbed_official 121:7f86b4238bec 6261 #define FTM_CnSC_ELSA_MASK (0x4U)
mbed_official 121:7f86b4238bec 6262 #define FTM_CnSC_ELSA_SHIFT (2U)
mbed_official 121:7f86b4238bec 6263 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
mbed_official 121:7f86b4238bec 6264 #define FTM_CnSC_ELSB_MASK (0x8U)
mbed_official 121:7f86b4238bec 6265 #define FTM_CnSC_ELSB_SHIFT (3U)
mbed_official 121:7f86b4238bec 6266 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
mbed_official 121:7f86b4238bec 6267 #define FTM_CnSC_MSA_MASK (0x10U)
mbed_official 121:7f86b4238bec 6268 #define FTM_CnSC_MSA_SHIFT (4U)
mbed_official 121:7f86b4238bec 6269 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
mbed_official 121:7f86b4238bec 6270 #define FTM_CnSC_MSB_MASK (0x20U)
mbed_official 121:7f86b4238bec 6271 #define FTM_CnSC_MSB_SHIFT (5U)
mbed_official 121:7f86b4238bec 6272 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
mbed_official 121:7f86b4238bec 6273 #define FTM_CnSC_CHIE_MASK (0x40U)
mbed_official 121:7f86b4238bec 6274 #define FTM_CnSC_CHIE_SHIFT (6U)
mbed_official 121:7f86b4238bec 6275 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
mbed_official 121:7f86b4238bec 6276 #define FTM_CnSC_CHF_MASK (0x80U)
mbed_official 121:7f86b4238bec 6277 #define FTM_CnSC_CHF_SHIFT (7U)
mbed_official 121:7f86b4238bec 6278 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
mbed_official 121:7f86b4238bec 6279
mbed_official 121:7f86b4238bec 6280 /* The count of FTM_CnSC */
mbed_official 121:7f86b4238bec 6281 #define FTM_CnSC_COUNT (8U)
mbed_official 121:7f86b4238bec 6282
mbed_official 121:7f86b4238bec 6283 /*! @name CnV - Channel (n) Value */
mbed_official 121:7f86b4238bec 6284 #define FTM_CnV_VAL_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 6285 #define FTM_CnV_VAL_SHIFT (0U)
mbed_official 121:7f86b4238bec 6286 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
mbed_official 121:7f86b4238bec 6287
mbed_official 121:7f86b4238bec 6288 /* The count of FTM_CnV */
mbed_official 121:7f86b4238bec 6289 #define FTM_CnV_COUNT (8U)
mbed_official 121:7f86b4238bec 6290
mbed_official 121:7f86b4238bec 6291 /*! @name CNTIN - Counter Initial Value */
mbed_official 121:7f86b4238bec 6292 #define FTM_CNTIN_INIT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 6293 #define FTM_CNTIN_INIT_SHIFT (0U)
mbed_official 121:7f86b4238bec 6294 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
mbed_official 121:7f86b4238bec 6295
mbed_official 121:7f86b4238bec 6296 /*! @name STATUS - Capture And Compare Status */
mbed_official 121:7f86b4238bec 6297 #define FTM_STATUS_CH0F_MASK (0x1U)
mbed_official 121:7f86b4238bec 6298 #define FTM_STATUS_CH0F_SHIFT (0U)
mbed_official 121:7f86b4238bec 6299 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
mbed_official 121:7f86b4238bec 6300 #define FTM_STATUS_CH1F_MASK (0x2U)
mbed_official 121:7f86b4238bec 6301 #define FTM_STATUS_CH1F_SHIFT (1U)
mbed_official 121:7f86b4238bec 6302 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
mbed_official 121:7f86b4238bec 6303 #define FTM_STATUS_CH2F_MASK (0x4U)
mbed_official 121:7f86b4238bec 6304 #define FTM_STATUS_CH2F_SHIFT (2U)
mbed_official 121:7f86b4238bec 6305 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
mbed_official 121:7f86b4238bec 6306 #define FTM_STATUS_CH3F_MASK (0x8U)
mbed_official 121:7f86b4238bec 6307 #define FTM_STATUS_CH3F_SHIFT (3U)
mbed_official 121:7f86b4238bec 6308 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
mbed_official 121:7f86b4238bec 6309 #define FTM_STATUS_CH4F_MASK (0x10U)
mbed_official 121:7f86b4238bec 6310 #define FTM_STATUS_CH4F_SHIFT (4U)
mbed_official 121:7f86b4238bec 6311 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
mbed_official 121:7f86b4238bec 6312 #define FTM_STATUS_CH5F_MASK (0x20U)
mbed_official 121:7f86b4238bec 6313 #define FTM_STATUS_CH5F_SHIFT (5U)
mbed_official 121:7f86b4238bec 6314 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
mbed_official 121:7f86b4238bec 6315 #define FTM_STATUS_CH6F_MASK (0x40U)
mbed_official 121:7f86b4238bec 6316 #define FTM_STATUS_CH6F_SHIFT (6U)
mbed_official 121:7f86b4238bec 6317 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
mbed_official 121:7f86b4238bec 6318 #define FTM_STATUS_CH7F_MASK (0x80U)
mbed_official 121:7f86b4238bec 6319 #define FTM_STATUS_CH7F_SHIFT (7U)
mbed_official 121:7f86b4238bec 6320 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
mbed_official 121:7f86b4238bec 6321
mbed_official 121:7f86b4238bec 6322 /*! @name MODE - Features Mode Selection */
mbed_official 121:7f86b4238bec 6323 #define FTM_MODE_FTMEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 6324 #define FTM_MODE_FTMEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 6325 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
mbed_official 121:7f86b4238bec 6326 #define FTM_MODE_INIT_MASK (0x2U)
mbed_official 121:7f86b4238bec 6327 #define FTM_MODE_INIT_SHIFT (1U)
mbed_official 121:7f86b4238bec 6328 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
mbed_official 121:7f86b4238bec 6329 #define FTM_MODE_WPDIS_MASK (0x4U)
mbed_official 121:7f86b4238bec 6330 #define FTM_MODE_WPDIS_SHIFT (2U)
mbed_official 121:7f86b4238bec 6331 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
mbed_official 121:7f86b4238bec 6332 #define FTM_MODE_PWMSYNC_MASK (0x8U)
mbed_official 121:7f86b4238bec 6333 #define FTM_MODE_PWMSYNC_SHIFT (3U)
mbed_official 121:7f86b4238bec 6334 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
mbed_official 121:7f86b4238bec 6335 #define FTM_MODE_CAPTEST_MASK (0x10U)
mbed_official 121:7f86b4238bec 6336 #define FTM_MODE_CAPTEST_SHIFT (4U)
mbed_official 121:7f86b4238bec 6337 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
mbed_official 121:7f86b4238bec 6338 #define FTM_MODE_FAULTM_MASK (0x60U)
mbed_official 121:7f86b4238bec 6339 #define FTM_MODE_FAULTM_SHIFT (5U)
mbed_official 121:7f86b4238bec 6340 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
mbed_official 121:7f86b4238bec 6341 #define FTM_MODE_FAULTIE_MASK (0x80U)
mbed_official 121:7f86b4238bec 6342 #define FTM_MODE_FAULTIE_SHIFT (7U)
mbed_official 121:7f86b4238bec 6343 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
mbed_official 121:7f86b4238bec 6344
mbed_official 121:7f86b4238bec 6345 /*! @name SYNC - Synchronization */
mbed_official 121:7f86b4238bec 6346 #define FTM_SYNC_CNTMIN_MASK (0x1U)
mbed_official 121:7f86b4238bec 6347 #define FTM_SYNC_CNTMIN_SHIFT (0U)
mbed_official 121:7f86b4238bec 6348 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
mbed_official 121:7f86b4238bec 6349 #define FTM_SYNC_CNTMAX_MASK (0x2U)
mbed_official 121:7f86b4238bec 6350 #define FTM_SYNC_CNTMAX_SHIFT (1U)
mbed_official 121:7f86b4238bec 6351 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
mbed_official 121:7f86b4238bec 6352 #define FTM_SYNC_REINIT_MASK (0x4U)
mbed_official 121:7f86b4238bec 6353 #define FTM_SYNC_REINIT_SHIFT (2U)
mbed_official 121:7f86b4238bec 6354 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
mbed_official 121:7f86b4238bec 6355 #define FTM_SYNC_SYNCHOM_MASK (0x8U)
mbed_official 121:7f86b4238bec 6356 #define FTM_SYNC_SYNCHOM_SHIFT (3U)
mbed_official 121:7f86b4238bec 6357 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
mbed_official 121:7f86b4238bec 6358 #define FTM_SYNC_TRIG0_MASK (0x10U)
mbed_official 121:7f86b4238bec 6359 #define FTM_SYNC_TRIG0_SHIFT (4U)
mbed_official 121:7f86b4238bec 6360 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
mbed_official 121:7f86b4238bec 6361 #define FTM_SYNC_TRIG1_MASK (0x20U)
mbed_official 121:7f86b4238bec 6362 #define FTM_SYNC_TRIG1_SHIFT (5U)
mbed_official 121:7f86b4238bec 6363 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
mbed_official 121:7f86b4238bec 6364 #define FTM_SYNC_TRIG2_MASK (0x40U)
mbed_official 121:7f86b4238bec 6365 #define FTM_SYNC_TRIG2_SHIFT (6U)
mbed_official 121:7f86b4238bec 6366 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
mbed_official 121:7f86b4238bec 6367 #define FTM_SYNC_SWSYNC_MASK (0x80U)
mbed_official 121:7f86b4238bec 6368 #define FTM_SYNC_SWSYNC_SHIFT (7U)
mbed_official 121:7f86b4238bec 6369 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
mbed_official 121:7f86b4238bec 6370
mbed_official 121:7f86b4238bec 6371 /*! @name OUTINIT - Initial State For Channels Output */
mbed_official 121:7f86b4238bec 6372 #define FTM_OUTINIT_CH0OI_MASK (0x1U)
mbed_official 121:7f86b4238bec 6373 #define FTM_OUTINIT_CH0OI_SHIFT (0U)
mbed_official 121:7f86b4238bec 6374 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
mbed_official 121:7f86b4238bec 6375 #define FTM_OUTINIT_CH1OI_MASK (0x2U)
mbed_official 121:7f86b4238bec 6376 #define FTM_OUTINIT_CH1OI_SHIFT (1U)
mbed_official 121:7f86b4238bec 6377 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
mbed_official 121:7f86b4238bec 6378 #define FTM_OUTINIT_CH2OI_MASK (0x4U)
mbed_official 121:7f86b4238bec 6379 #define FTM_OUTINIT_CH2OI_SHIFT (2U)
mbed_official 121:7f86b4238bec 6380 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
mbed_official 121:7f86b4238bec 6381 #define FTM_OUTINIT_CH3OI_MASK (0x8U)
mbed_official 121:7f86b4238bec 6382 #define FTM_OUTINIT_CH3OI_SHIFT (3U)
mbed_official 121:7f86b4238bec 6383 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
mbed_official 121:7f86b4238bec 6384 #define FTM_OUTINIT_CH4OI_MASK (0x10U)
mbed_official 121:7f86b4238bec 6385 #define FTM_OUTINIT_CH4OI_SHIFT (4U)
mbed_official 121:7f86b4238bec 6386 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
mbed_official 121:7f86b4238bec 6387 #define FTM_OUTINIT_CH5OI_MASK (0x20U)
mbed_official 121:7f86b4238bec 6388 #define FTM_OUTINIT_CH5OI_SHIFT (5U)
mbed_official 121:7f86b4238bec 6389 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
mbed_official 121:7f86b4238bec 6390 #define FTM_OUTINIT_CH6OI_MASK (0x40U)
mbed_official 121:7f86b4238bec 6391 #define FTM_OUTINIT_CH6OI_SHIFT (6U)
mbed_official 121:7f86b4238bec 6392 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
mbed_official 121:7f86b4238bec 6393 #define FTM_OUTINIT_CH7OI_MASK (0x80U)
mbed_official 121:7f86b4238bec 6394 #define FTM_OUTINIT_CH7OI_SHIFT (7U)
mbed_official 121:7f86b4238bec 6395 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
mbed_official 121:7f86b4238bec 6396
mbed_official 121:7f86b4238bec 6397 /*! @name OUTMASK - Output Mask */
mbed_official 121:7f86b4238bec 6398 #define FTM_OUTMASK_CH0OM_MASK (0x1U)
mbed_official 121:7f86b4238bec 6399 #define FTM_OUTMASK_CH0OM_SHIFT (0U)
mbed_official 121:7f86b4238bec 6400 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
mbed_official 121:7f86b4238bec 6401 #define FTM_OUTMASK_CH1OM_MASK (0x2U)
mbed_official 121:7f86b4238bec 6402 #define FTM_OUTMASK_CH1OM_SHIFT (1U)
mbed_official 121:7f86b4238bec 6403 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
mbed_official 121:7f86b4238bec 6404 #define FTM_OUTMASK_CH2OM_MASK (0x4U)
mbed_official 121:7f86b4238bec 6405 #define FTM_OUTMASK_CH2OM_SHIFT (2U)
mbed_official 121:7f86b4238bec 6406 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
mbed_official 121:7f86b4238bec 6407 #define FTM_OUTMASK_CH3OM_MASK (0x8U)
mbed_official 121:7f86b4238bec 6408 #define FTM_OUTMASK_CH3OM_SHIFT (3U)
mbed_official 121:7f86b4238bec 6409 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
mbed_official 121:7f86b4238bec 6410 #define FTM_OUTMASK_CH4OM_MASK (0x10U)
mbed_official 121:7f86b4238bec 6411 #define FTM_OUTMASK_CH4OM_SHIFT (4U)
mbed_official 121:7f86b4238bec 6412 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
mbed_official 121:7f86b4238bec 6413 #define FTM_OUTMASK_CH5OM_MASK (0x20U)
mbed_official 121:7f86b4238bec 6414 #define FTM_OUTMASK_CH5OM_SHIFT (5U)
mbed_official 121:7f86b4238bec 6415 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
mbed_official 121:7f86b4238bec 6416 #define FTM_OUTMASK_CH6OM_MASK (0x40U)
mbed_official 121:7f86b4238bec 6417 #define FTM_OUTMASK_CH6OM_SHIFT (6U)
mbed_official 121:7f86b4238bec 6418 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
mbed_official 121:7f86b4238bec 6419 #define FTM_OUTMASK_CH7OM_MASK (0x80U)
mbed_official 121:7f86b4238bec 6420 #define FTM_OUTMASK_CH7OM_SHIFT (7U)
mbed_official 121:7f86b4238bec 6421 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
mbed_official 121:7f86b4238bec 6422
mbed_official 121:7f86b4238bec 6423 /*! @name COMBINE - Function For Linked Channels */
mbed_official 121:7f86b4238bec 6424 #define FTM_COMBINE_COMBINE0_MASK (0x1U)
mbed_official 121:7f86b4238bec 6425 #define FTM_COMBINE_COMBINE0_SHIFT (0U)
mbed_official 121:7f86b4238bec 6426 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
mbed_official 121:7f86b4238bec 6427 #define FTM_COMBINE_COMP0_MASK (0x2U)
mbed_official 121:7f86b4238bec 6428 #define FTM_COMBINE_COMP0_SHIFT (1U)
mbed_official 121:7f86b4238bec 6429 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
mbed_official 121:7f86b4238bec 6430 #define FTM_COMBINE_DECAPEN0_MASK (0x4U)
mbed_official 121:7f86b4238bec 6431 #define FTM_COMBINE_DECAPEN0_SHIFT (2U)
mbed_official 121:7f86b4238bec 6432 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
mbed_official 121:7f86b4238bec 6433 #define FTM_COMBINE_DECAP0_MASK (0x8U)
mbed_official 121:7f86b4238bec 6434 #define FTM_COMBINE_DECAP0_SHIFT (3U)
mbed_official 121:7f86b4238bec 6435 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
mbed_official 121:7f86b4238bec 6436 #define FTM_COMBINE_DTEN0_MASK (0x10U)
mbed_official 121:7f86b4238bec 6437 #define FTM_COMBINE_DTEN0_SHIFT (4U)
mbed_official 121:7f86b4238bec 6438 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
mbed_official 121:7f86b4238bec 6439 #define FTM_COMBINE_SYNCEN0_MASK (0x20U)
mbed_official 121:7f86b4238bec 6440 #define FTM_COMBINE_SYNCEN0_SHIFT (5U)
mbed_official 121:7f86b4238bec 6441 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
mbed_official 121:7f86b4238bec 6442 #define FTM_COMBINE_FAULTEN0_MASK (0x40U)
mbed_official 121:7f86b4238bec 6443 #define FTM_COMBINE_FAULTEN0_SHIFT (6U)
mbed_official 121:7f86b4238bec 6444 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
mbed_official 121:7f86b4238bec 6445 #define FTM_COMBINE_COMBINE1_MASK (0x100U)
mbed_official 121:7f86b4238bec 6446 #define FTM_COMBINE_COMBINE1_SHIFT (8U)
mbed_official 121:7f86b4238bec 6447 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
mbed_official 121:7f86b4238bec 6448 #define FTM_COMBINE_COMP1_MASK (0x200U)
mbed_official 121:7f86b4238bec 6449 #define FTM_COMBINE_COMP1_SHIFT (9U)
mbed_official 121:7f86b4238bec 6450 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
mbed_official 121:7f86b4238bec 6451 #define FTM_COMBINE_DECAPEN1_MASK (0x400U)
mbed_official 121:7f86b4238bec 6452 #define FTM_COMBINE_DECAPEN1_SHIFT (10U)
mbed_official 121:7f86b4238bec 6453 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
mbed_official 121:7f86b4238bec 6454 #define FTM_COMBINE_DECAP1_MASK (0x800U)
mbed_official 121:7f86b4238bec 6455 #define FTM_COMBINE_DECAP1_SHIFT (11U)
mbed_official 121:7f86b4238bec 6456 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
mbed_official 121:7f86b4238bec 6457 #define FTM_COMBINE_DTEN1_MASK (0x1000U)
mbed_official 121:7f86b4238bec 6458 #define FTM_COMBINE_DTEN1_SHIFT (12U)
mbed_official 121:7f86b4238bec 6459 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
mbed_official 121:7f86b4238bec 6460 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
mbed_official 121:7f86b4238bec 6461 #define FTM_COMBINE_SYNCEN1_SHIFT (13U)
mbed_official 121:7f86b4238bec 6462 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
mbed_official 121:7f86b4238bec 6463 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
mbed_official 121:7f86b4238bec 6464 #define FTM_COMBINE_FAULTEN1_SHIFT (14U)
mbed_official 121:7f86b4238bec 6465 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
mbed_official 121:7f86b4238bec 6466 #define FTM_COMBINE_COMBINE2_MASK (0x10000U)
mbed_official 121:7f86b4238bec 6467 #define FTM_COMBINE_COMBINE2_SHIFT (16U)
mbed_official 121:7f86b4238bec 6468 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
mbed_official 121:7f86b4238bec 6469 #define FTM_COMBINE_COMP2_MASK (0x20000U)
mbed_official 121:7f86b4238bec 6470 #define FTM_COMBINE_COMP2_SHIFT (17U)
mbed_official 121:7f86b4238bec 6471 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
mbed_official 121:7f86b4238bec 6472 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
mbed_official 121:7f86b4238bec 6473 #define FTM_COMBINE_DECAPEN2_SHIFT (18U)
mbed_official 121:7f86b4238bec 6474 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
mbed_official 121:7f86b4238bec 6475 #define FTM_COMBINE_DECAP2_MASK (0x80000U)
mbed_official 121:7f86b4238bec 6476 #define FTM_COMBINE_DECAP2_SHIFT (19U)
mbed_official 121:7f86b4238bec 6477 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
mbed_official 121:7f86b4238bec 6478 #define FTM_COMBINE_DTEN2_MASK (0x100000U)
mbed_official 121:7f86b4238bec 6479 #define FTM_COMBINE_DTEN2_SHIFT (20U)
mbed_official 121:7f86b4238bec 6480 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
mbed_official 121:7f86b4238bec 6481 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
mbed_official 121:7f86b4238bec 6482 #define FTM_COMBINE_SYNCEN2_SHIFT (21U)
mbed_official 121:7f86b4238bec 6483 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
mbed_official 121:7f86b4238bec 6484 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
mbed_official 121:7f86b4238bec 6485 #define FTM_COMBINE_FAULTEN2_SHIFT (22U)
mbed_official 121:7f86b4238bec 6486 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
mbed_official 121:7f86b4238bec 6487 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 6488 #define FTM_COMBINE_COMBINE3_SHIFT (24U)
mbed_official 121:7f86b4238bec 6489 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
mbed_official 121:7f86b4238bec 6490 #define FTM_COMBINE_COMP3_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 6491 #define FTM_COMBINE_COMP3_SHIFT (25U)
mbed_official 121:7f86b4238bec 6492 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
mbed_official 121:7f86b4238bec 6493 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 6494 #define FTM_COMBINE_DECAPEN3_SHIFT (26U)
mbed_official 121:7f86b4238bec 6495 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
mbed_official 121:7f86b4238bec 6496 #define FTM_COMBINE_DECAP3_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 6497 #define FTM_COMBINE_DECAP3_SHIFT (27U)
mbed_official 121:7f86b4238bec 6498 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
mbed_official 121:7f86b4238bec 6499 #define FTM_COMBINE_DTEN3_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 6500 #define FTM_COMBINE_DTEN3_SHIFT (28U)
mbed_official 121:7f86b4238bec 6501 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
mbed_official 121:7f86b4238bec 6502 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 6503 #define FTM_COMBINE_SYNCEN3_SHIFT (29U)
mbed_official 121:7f86b4238bec 6504 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
mbed_official 121:7f86b4238bec 6505 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 6506 #define FTM_COMBINE_FAULTEN3_SHIFT (30U)
mbed_official 121:7f86b4238bec 6507 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
mbed_official 121:7f86b4238bec 6508
mbed_official 121:7f86b4238bec 6509 /*! @name DEADTIME - Deadtime Insertion Control */
mbed_official 121:7f86b4238bec 6510 #define FTM_DEADTIME_DTVAL_MASK (0x3FU)
mbed_official 121:7f86b4238bec 6511 #define FTM_DEADTIME_DTVAL_SHIFT (0U)
mbed_official 121:7f86b4238bec 6512 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
mbed_official 121:7f86b4238bec 6513 #define FTM_DEADTIME_DTPS_MASK (0xC0U)
mbed_official 121:7f86b4238bec 6514 #define FTM_DEADTIME_DTPS_SHIFT (6U)
mbed_official 121:7f86b4238bec 6515 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
mbed_official 121:7f86b4238bec 6516
mbed_official 121:7f86b4238bec 6517 /*! @name EXTTRIG - FTM External Trigger */
mbed_official 121:7f86b4238bec 6518 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
mbed_official 121:7f86b4238bec 6519 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
mbed_official 121:7f86b4238bec 6520 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
mbed_official 121:7f86b4238bec 6521 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
mbed_official 121:7f86b4238bec 6522 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
mbed_official 121:7f86b4238bec 6523 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
mbed_official 121:7f86b4238bec 6524 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
mbed_official 121:7f86b4238bec 6525 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
mbed_official 121:7f86b4238bec 6526 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
mbed_official 121:7f86b4238bec 6527 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
mbed_official 121:7f86b4238bec 6528 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
mbed_official 121:7f86b4238bec 6529 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
mbed_official 121:7f86b4238bec 6530 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
mbed_official 121:7f86b4238bec 6531 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
mbed_official 121:7f86b4238bec 6532 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
mbed_official 121:7f86b4238bec 6533 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
mbed_official 121:7f86b4238bec 6534 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
mbed_official 121:7f86b4238bec 6535 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
mbed_official 121:7f86b4238bec 6536 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 6537 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 6538 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
mbed_official 121:7f86b4238bec 6539 #define FTM_EXTTRIG_TRIGF_MASK (0x80U)
mbed_official 121:7f86b4238bec 6540 #define FTM_EXTTRIG_TRIGF_SHIFT (7U)
mbed_official 121:7f86b4238bec 6541 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
mbed_official 121:7f86b4238bec 6542
mbed_official 121:7f86b4238bec 6543 /*! @name POL - Channels Polarity */
mbed_official 121:7f86b4238bec 6544 #define FTM_POL_POL0_MASK (0x1U)
mbed_official 121:7f86b4238bec 6545 #define FTM_POL_POL0_SHIFT (0U)
mbed_official 121:7f86b4238bec 6546 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
mbed_official 121:7f86b4238bec 6547 #define FTM_POL_POL1_MASK (0x2U)
mbed_official 121:7f86b4238bec 6548 #define FTM_POL_POL1_SHIFT (1U)
mbed_official 121:7f86b4238bec 6549 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
mbed_official 121:7f86b4238bec 6550 #define FTM_POL_POL2_MASK (0x4U)
mbed_official 121:7f86b4238bec 6551 #define FTM_POL_POL2_SHIFT (2U)
mbed_official 121:7f86b4238bec 6552 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
mbed_official 121:7f86b4238bec 6553 #define FTM_POL_POL3_MASK (0x8U)
mbed_official 121:7f86b4238bec 6554 #define FTM_POL_POL3_SHIFT (3U)
mbed_official 121:7f86b4238bec 6555 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
mbed_official 121:7f86b4238bec 6556 #define FTM_POL_POL4_MASK (0x10U)
mbed_official 121:7f86b4238bec 6557 #define FTM_POL_POL4_SHIFT (4U)
mbed_official 121:7f86b4238bec 6558 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
mbed_official 121:7f86b4238bec 6559 #define FTM_POL_POL5_MASK (0x20U)
mbed_official 121:7f86b4238bec 6560 #define FTM_POL_POL5_SHIFT (5U)
mbed_official 121:7f86b4238bec 6561 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
mbed_official 121:7f86b4238bec 6562 #define FTM_POL_POL6_MASK (0x40U)
mbed_official 121:7f86b4238bec 6563 #define FTM_POL_POL6_SHIFT (6U)
mbed_official 121:7f86b4238bec 6564 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
mbed_official 121:7f86b4238bec 6565 #define FTM_POL_POL7_MASK (0x80U)
mbed_official 121:7f86b4238bec 6566 #define FTM_POL_POL7_SHIFT (7U)
mbed_official 121:7f86b4238bec 6567 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
mbed_official 121:7f86b4238bec 6568
mbed_official 121:7f86b4238bec 6569 /*! @name FMS - Fault Mode Status */
mbed_official 121:7f86b4238bec 6570 #define FTM_FMS_FAULTF0_MASK (0x1U)
mbed_official 121:7f86b4238bec 6571 #define FTM_FMS_FAULTF0_SHIFT (0U)
mbed_official 121:7f86b4238bec 6572 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
mbed_official 121:7f86b4238bec 6573 #define FTM_FMS_FAULTF1_MASK (0x2U)
mbed_official 121:7f86b4238bec 6574 #define FTM_FMS_FAULTF1_SHIFT (1U)
mbed_official 121:7f86b4238bec 6575 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
mbed_official 121:7f86b4238bec 6576 #define FTM_FMS_FAULTF2_MASK (0x4U)
mbed_official 121:7f86b4238bec 6577 #define FTM_FMS_FAULTF2_SHIFT (2U)
mbed_official 121:7f86b4238bec 6578 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
mbed_official 121:7f86b4238bec 6579 #define FTM_FMS_FAULTF3_MASK (0x8U)
mbed_official 121:7f86b4238bec 6580 #define FTM_FMS_FAULTF3_SHIFT (3U)
mbed_official 121:7f86b4238bec 6581 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
mbed_official 121:7f86b4238bec 6582 #define FTM_FMS_FAULTIN_MASK (0x20U)
mbed_official 121:7f86b4238bec 6583 #define FTM_FMS_FAULTIN_SHIFT (5U)
mbed_official 121:7f86b4238bec 6584 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
mbed_official 121:7f86b4238bec 6585 #define FTM_FMS_WPEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 6586 #define FTM_FMS_WPEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 6587 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
mbed_official 121:7f86b4238bec 6588 #define FTM_FMS_FAULTF_MASK (0x80U)
mbed_official 121:7f86b4238bec 6589 #define FTM_FMS_FAULTF_SHIFT (7U)
mbed_official 121:7f86b4238bec 6590 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
mbed_official 121:7f86b4238bec 6591
mbed_official 121:7f86b4238bec 6592 /*! @name FILTER - Input Capture Filter Control */
mbed_official 121:7f86b4238bec 6593 #define FTM_FILTER_CH0FVAL_MASK (0xFU)
mbed_official 121:7f86b4238bec 6594 #define FTM_FILTER_CH0FVAL_SHIFT (0U)
mbed_official 121:7f86b4238bec 6595 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
mbed_official 121:7f86b4238bec 6596 #define FTM_FILTER_CH1FVAL_MASK (0xF0U)
mbed_official 121:7f86b4238bec 6597 #define FTM_FILTER_CH1FVAL_SHIFT (4U)
mbed_official 121:7f86b4238bec 6598 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
mbed_official 121:7f86b4238bec 6599 #define FTM_FILTER_CH2FVAL_MASK (0xF00U)
mbed_official 121:7f86b4238bec 6600 #define FTM_FILTER_CH2FVAL_SHIFT (8U)
mbed_official 121:7f86b4238bec 6601 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
mbed_official 121:7f86b4238bec 6602 #define FTM_FILTER_CH3FVAL_MASK (0xF000U)
mbed_official 121:7f86b4238bec 6603 #define FTM_FILTER_CH3FVAL_SHIFT (12U)
mbed_official 121:7f86b4238bec 6604 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
mbed_official 121:7f86b4238bec 6605
mbed_official 121:7f86b4238bec 6606 /*! @name FLTCTRL - Fault Control */
mbed_official 121:7f86b4238bec 6607 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
mbed_official 121:7f86b4238bec 6608 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
mbed_official 121:7f86b4238bec 6609 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
mbed_official 121:7f86b4238bec 6610 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
mbed_official 121:7f86b4238bec 6611 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
mbed_official 121:7f86b4238bec 6612 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
mbed_official 121:7f86b4238bec 6613 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
mbed_official 121:7f86b4238bec 6614 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
mbed_official 121:7f86b4238bec 6615 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
mbed_official 121:7f86b4238bec 6616 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
mbed_official 121:7f86b4238bec 6617 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
mbed_official 121:7f86b4238bec 6618 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
mbed_official 121:7f86b4238bec 6619 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
mbed_official 121:7f86b4238bec 6620 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
mbed_official 121:7f86b4238bec 6621 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
mbed_official 121:7f86b4238bec 6622 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
mbed_official 121:7f86b4238bec 6623 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
mbed_official 121:7f86b4238bec 6624 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
mbed_official 121:7f86b4238bec 6625 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
mbed_official 121:7f86b4238bec 6626 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
mbed_official 121:7f86b4238bec 6627 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
mbed_official 121:7f86b4238bec 6628 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
mbed_official 121:7f86b4238bec 6629 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
mbed_official 121:7f86b4238bec 6630 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
mbed_official 121:7f86b4238bec 6631 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
mbed_official 121:7f86b4238bec 6632 #define FTM_FLTCTRL_FFVAL_SHIFT (8U)
mbed_official 121:7f86b4238bec 6633 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
mbed_official 121:7f86b4238bec 6634
mbed_official 121:7f86b4238bec 6635 /*! @name QDCTRL - Quadrature Decoder Control And Status */
mbed_official 121:7f86b4238bec 6636 #define FTM_QDCTRL_QUADEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 6637 #define FTM_QDCTRL_QUADEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 6638 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
mbed_official 121:7f86b4238bec 6639 #define FTM_QDCTRL_TOFDIR_MASK (0x2U)
mbed_official 121:7f86b4238bec 6640 #define FTM_QDCTRL_TOFDIR_SHIFT (1U)
mbed_official 121:7f86b4238bec 6641 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
mbed_official 121:7f86b4238bec 6642 #define FTM_QDCTRL_QUADIR_MASK (0x4U)
mbed_official 121:7f86b4238bec 6643 #define FTM_QDCTRL_QUADIR_SHIFT (2U)
mbed_official 121:7f86b4238bec 6644 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
mbed_official 121:7f86b4238bec 6645 #define FTM_QDCTRL_QUADMODE_MASK (0x8U)
mbed_official 121:7f86b4238bec 6646 #define FTM_QDCTRL_QUADMODE_SHIFT (3U)
mbed_official 121:7f86b4238bec 6647 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
mbed_official 121:7f86b4238bec 6648 #define FTM_QDCTRL_PHBPOL_MASK (0x10U)
mbed_official 121:7f86b4238bec 6649 #define FTM_QDCTRL_PHBPOL_SHIFT (4U)
mbed_official 121:7f86b4238bec 6650 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
mbed_official 121:7f86b4238bec 6651 #define FTM_QDCTRL_PHAPOL_MASK (0x20U)
mbed_official 121:7f86b4238bec 6652 #define FTM_QDCTRL_PHAPOL_SHIFT (5U)
mbed_official 121:7f86b4238bec 6653 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
mbed_official 121:7f86b4238bec 6654 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
mbed_official 121:7f86b4238bec 6655 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
mbed_official 121:7f86b4238bec 6656 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
mbed_official 121:7f86b4238bec 6657 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
mbed_official 121:7f86b4238bec 6658 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
mbed_official 121:7f86b4238bec 6659 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
mbed_official 121:7f86b4238bec 6660
mbed_official 121:7f86b4238bec 6661 /*! @name CONF - Configuration */
mbed_official 121:7f86b4238bec 6662 #define FTM_CONF_NUMTOF_MASK (0x1FU)
mbed_official 121:7f86b4238bec 6663 #define FTM_CONF_NUMTOF_SHIFT (0U)
mbed_official 121:7f86b4238bec 6664 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
mbed_official 121:7f86b4238bec 6665 #define FTM_CONF_BDMMODE_MASK (0xC0U)
mbed_official 121:7f86b4238bec 6666 #define FTM_CONF_BDMMODE_SHIFT (6U)
mbed_official 121:7f86b4238bec 6667 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
mbed_official 121:7f86b4238bec 6668 #define FTM_CONF_GTBEEN_MASK (0x200U)
mbed_official 121:7f86b4238bec 6669 #define FTM_CONF_GTBEEN_SHIFT (9U)
mbed_official 121:7f86b4238bec 6670 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
mbed_official 121:7f86b4238bec 6671 #define FTM_CONF_GTBEOUT_MASK (0x400U)
mbed_official 121:7f86b4238bec 6672 #define FTM_CONF_GTBEOUT_SHIFT (10U)
mbed_official 121:7f86b4238bec 6673 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
mbed_official 121:7f86b4238bec 6674
mbed_official 121:7f86b4238bec 6675 /*! @name FLTPOL - FTM Fault Input Polarity */
mbed_official 121:7f86b4238bec 6676 #define FTM_FLTPOL_FLT0POL_MASK (0x1U)
mbed_official 121:7f86b4238bec 6677 #define FTM_FLTPOL_FLT0POL_SHIFT (0U)
mbed_official 121:7f86b4238bec 6678 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
mbed_official 121:7f86b4238bec 6679 #define FTM_FLTPOL_FLT1POL_MASK (0x2U)
mbed_official 121:7f86b4238bec 6680 #define FTM_FLTPOL_FLT1POL_SHIFT (1U)
mbed_official 121:7f86b4238bec 6681 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
mbed_official 121:7f86b4238bec 6682 #define FTM_FLTPOL_FLT2POL_MASK (0x4U)
mbed_official 121:7f86b4238bec 6683 #define FTM_FLTPOL_FLT2POL_SHIFT (2U)
mbed_official 121:7f86b4238bec 6684 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
mbed_official 121:7f86b4238bec 6685 #define FTM_FLTPOL_FLT3POL_MASK (0x8U)
mbed_official 121:7f86b4238bec 6686 #define FTM_FLTPOL_FLT3POL_SHIFT (3U)
mbed_official 121:7f86b4238bec 6687 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
mbed_official 121:7f86b4238bec 6688
mbed_official 121:7f86b4238bec 6689 /*! @name SYNCONF - Synchronization Configuration */
mbed_official 121:7f86b4238bec 6690 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
mbed_official 121:7f86b4238bec 6691 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
mbed_official 121:7f86b4238bec 6692 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
mbed_official 121:7f86b4238bec 6693 #define FTM_SYNCONF_CNTINC_MASK (0x4U)
mbed_official 121:7f86b4238bec 6694 #define FTM_SYNCONF_CNTINC_SHIFT (2U)
mbed_official 121:7f86b4238bec 6695 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
mbed_official 121:7f86b4238bec 6696 #define FTM_SYNCONF_INVC_MASK (0x10U)
mbed_official 121:7f86b4238bec 6697 #define FTM_SYNCONF_INVC_SHIFT (4U)
mbed_official 121:7f86b4238bec 6698 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
mbed_official 121:7f86b4238bec 6699 #define FTM_SYNCONF_SWOC_MASK (0x20U)
mbed_official 121:7f86b4238bec 6700 #define FTM_SYNCONF_SWOC_SHIFT (5U)
mbed_official 121:7f86b4238bec 6701 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
mbed_official 121:7f86b4238bec 6702 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
mbed_official 121:7f86b4238bec 6703 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
mbed_official 121:7f86b4238bec 6704 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
mbed_official 121:7f86b4238bec 6705 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
mbed_official 121:7f86b4238bec 6706 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
mbed_official 121:7f86b4238bec 6707 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
mbed_official 121:7f86b4238bec 6708 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
mbed_official 121:7f86b4238bec 6709 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
mbed_official 121:7f86b4238bec 6710 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
mbed_official 121:7f86b4238bec 6711 #define FTM_SYNCONF_SWOM_MASK (0x400U)
mbed_official 121:7f86b4238bec 6712 #define FTM_SYNCONF_SWOM_SHIFT (10U)
mbed_official 121:7f86b4238bec 6713 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
mbed_official 121:7f86b4238bec 6714 #define FTM_SYNCONF_SWINVC_MASK (0x800U)
mbed_official 121:7f86b4238bec 6715 #define FTM_SYNCONF_SWINVC_SHIFT (11U)
mbed_official 121:7f86b4238bec 6716 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
mbed_official 121:7f86b4238bec 6717 #define FTM_SYNCONF_SWSOC_MASK (0x1000U)
mbed_official 121:7f86b4238bec 6718 #define FTM_SYNCONF_SWSOC_SHIFT (12U)
mbed_official 121:7f86b4238bec 6719 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
mbed_official 121:7f86b4238bec 6720 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
mbed_official 121:7f86b4238bec 6721 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
mbed_official 121:7f86b4238bec 6722 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
mbed_official 121:7f86b4238bec 6723 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
mbed_official 121:7f86b4238bec 6724 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
mbed_official 121:7f86b4238bec 6725 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
mbed_official 121:7f86b4238bec 6726 #define FTM_SYNCONF_HWOM_MASK (0x40000U)
mbed_official 121:7f86b4238bec 6727 #define FTM_SYNCONF_HWOM_SHIFT (18U)
mbed_official 121:7f86b4238bec 6728 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
mbed_official 121:7f86b4238bec 6729 #define FTM_SYNCONF_HWINVC_MASK (0x80000U)
mbed_official 121:7f86b4238bec 6730 #define FTM_SYNCONF_HWINVC_SHIFT (19U)
mbed_official 121:7f86b4238bec 6731 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
mbed_official 121:7f86b4238bec 6732 #define FTM_SYNCONF_HWSOC_MASK (0x100000U)
mbed_official 121:7f86b4238bec 6733 #define FTM_SYNCONF_HWSOC_SHIFT (20U)
mbed_official 121:7f86b4238bec 6734 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
mbed_official 121:7f86b4238bec 6735
mbed_official 121:7f86b4238bec 6736 /*! @name INVCTRL - FTM Inverting Control */
mbed_official 121:7f86b4238bec 6737 #define FTM_INVCTRL_INV0EN_MASK (0x1U)
mbed_official 121:7f86b4238bec 6738 #define FTM_INVCTRL_INV0EN_SHIFT (0U)
mbed_official 121:7f86b4238bec 6739 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
mbed_official 121:7f86b4238bec 6740 #define FTM_INVCTRL_INV1EN_MASK (0x2U)
mbed_official 121:7f86b4238bec 6741 #define FTM_INVCTRL_INV1EN_SHIFT (1U)
mbed_official 121:7f86b4238bec 6742 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
mbed_official 121:7f86b4238bec 6743 #define FTM_INVCTRL_INV2EN_MASK (0x4U)
mbed_official 121:7f86b4238bec 6744 #define FTM_INVCTRL_INV2EN_SHIFT (2U)
mbed_official 121:7f86b4238bec 6745 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
mbed_official 121:7f86b4238bec 6746 #define FTM_INVCTRL_INV3EN_MASK (0x8U)
mbed_official 121:7f86b4238bec 6747 #define FTM_INVCTRL_INV3EN_SHIFT (3U)
mbed_official 121:7f86b4238bec 6748 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
mbed_official 121:7f86b4238bec 6749
mbed_official 121:7f86b4238bec 6750 /*! @name SWOCTRL - FTM Software Output Control */
mbed_official 121:7f86b4238bec 6751 #define FTM_SWOCTRL_CH0OC_MASK (0x1U)
mbed_official 121:7f86b4238bec 6752 #define FTM_SWOCTRL_CH0OC_SHIFT (0U)
mbed_official 121:7f86b4238bec 6753 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
mbed_official 121:7f86b4238bec 6754 #define FTM_SWOCTRL_CH1OC_MASK (0x2U)
mbed_official 121:7f86b4238bec 6755 #define FTM_SWOCTRL_CH1OC_SHIFT (1U)
mbed_official 121:7f86b4238bec 6756 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
mbed_official 121:7f86b4238bec 6757 #define FTM_SWOCTRL_CH2OC_MASK (0x4U)
mbed_official 121:7f86b4238bec 6758 #define FTM_SWOCTRL_CH2OC_SHIFT (2U)
mbed_official 121:7f86b4238bec 6759 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
mbed_official 121:7f86b4238bec 6760 #define FTM_SWOCTRL_CH3OC_MASK (0x8U)
mbed_official 121:7f86b4238bec 6761 #define FTM_SWOCTRL_CH3OC_SHIFT (3U)
mbed_official 121:7f86b4238bec 6762 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
mbed_official 121:7f86b4238bec 6763 #define FTM_SWOCTRL_CH4OC_MASK (0x10U)
mbed_official 121:7f86b4238bec 6764 #define FTM_SWOCTRL_CH4OC_SHIFT (4U)
mbed_official 121:7f86b4238bec 6765 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
mbed_official 121:7f86b4238bec 6766 #define FTM_SWOCTRL_CH5OC_MASK (0x20U)
mbed_official 121:7f86b4238bec 6767 #define FTM_SWOCTRL_CH5OC_SHIFT (5U)
mbed_official 121:7f86b4238bec 6768 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
mbed_official 121:7f86b4238bec 6769 #define FTM_SWOCTRL_CH6OC_MASK (0x40U)
mbed_official 121:7f86b4238bec 6770 #define FTM_SWOCTRL_CH6OC_SHIFT (6U)
mbed_official 121:7f86b4238bec 6771 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
mbed_official 121:7f86b4238bec 6772 #define FTM_SWOCTRL_CH7OC_MASK (0x80U)
mbed_official 121:7f86b4238bec 6773 #define FTM_SWOCTRL_CH7OC_SHIFT (7U)
mbed_official 121:7f86b4238bec 6774 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
mbed_official 121:7f86b4238bec 6775 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
mbed_official 121:7f86b4238bec 6776 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
mbed_official 121:7f86b4238bec 6777 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
mbed_official 121:7f86b4238bec 6778 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
mbed_official 121:7f86b4238bec 6779 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
mbed_official 121:7f86b4238bec 6780 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
mbed_official 121:7f86b4238bec 6781 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
mbed_official 121:7f86b4238bec 6782 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
mbed_official 121:7f86b4238bec 6783 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
mbed_official 121:7f86b4238bec 6784 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
mbed_official 121:7f86b4238bec 6785 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
mbed_official 121:7f86b4238bec 6786 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
mbed_official 121:7f86b4238bec 6787 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
mbed_official 121:7f86b4238bec 6788 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
mbed_official 121:7f86b4238bec 6789 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
mbed_official 121:7f86b4238bec 6790 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
mbed_official 121:7f86b4238bec 6791 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
mbed_official 121:7f86b4238bec 6792 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
mbed_official 121:7f86b4238bec 6793 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
mbed_official 121:7f86b4238bec 6794 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
mbed_official 121:7f86b4238bec 6795 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
mbed_official 121:7f86b4238bec 6796 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
mbed_official 121:7f86b4238bec 6797 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
mbed_official 121:7f86b4238bec 6798 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
mbed_official 121:7f86b4238bec 6799
mbed_official 121:7f86b4238bec 6800 /*! @name PWMLOAD - FTM PWM Load */
mbed_official 121:7f86b4238bec 6801 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
mbed_official 121:7f86b4238bec 6802 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 6803 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
mbed_official 121:7f86b4238bec 6804 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
mbed_official 121:7f86b4238bec 6805 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
mbed_official 121:7f86b4238bec 6806 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
mbed_official 121:7f86b4238bec 6807 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
mbed_official 121:7f86b4238bec 6808 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
mbed_official 121:7f86b4238bec 6809 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
mbed_official 121:7f86b4238bec 6810 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
mbed_official 121:7f86b4238bec 6811 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
mbed_official 121:7f86b4238bec 6812 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
mbed_official 121:7f86b4238bec 6813 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
mbed_official 121:7f86b4238bec 6814 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
mbed_official 121:7f86b4238bec 6815 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
mbed_official 121:7f86b4238bec 6816 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
mbed_official 121:7f86b4238bec 6817 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
mbed_official 121:7f86b4238bec 6818 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
mbed_official 121:7f86b4238bec 6819 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
mbed_official 121:7f86b4238bec 6820 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
mbed_official 121:7f86b4238bec 6821 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
mbed_official 121:7f86b4238bec 6822 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
mbed_official 121:7f86b4238bec 6823 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
mbed_official 121:7f86b4238bec 6824 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
mbed_official 121:7f86b4238bec 6825 #define FTM_PWMLOAD_LDOK_MASK (0x200U)
mbed_official 121:7f86b4238bec 6826 #define FTM_PWMLOAD_LDOK_SHIFT (9U)
mbed_official 121:7f86b4238bec 6827 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
mbed_official 121:7f86b4238bec 6828
mbed_official 121:7f86b4238bec 6829
mbed_official 121:7f86b4238bec 6830 /*!
mbed_official 121:7f86b4238bec 6831 * @}
mbed_official 121:7f86b4238bec 6832 */ /* end of group FTM_Register_Masks */
mbed_official 121:7f86b4238bec 6833
mbed_official 121:7f86b4238bec 6834
mbed_official 121:7f86b4238bec 6835 /* FTM - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 6836 /** Peripheral FTM0 base address */
mbed_official 121:7f86b4238bec 6837 #define FTM0_BASE (0x40038000u)
mbed_official 121:7f86b4238bec 6838 /** Peripheral FTM0 base pointer */
mbed_official 121:7f86b4238bec 6839 #define FTM0 ((FTM_Type *)FTM0_BASE)
mbed_official 121:7f86b4238bec 6840 /** Peripheral FTM1 base address */
mbed_official 121:7f86b4238bec 6841 #define FTM1_BASE (0x40039000u)
mbed_official 121:7f86b4238bec 6842 /** Peripheral FTM1 base pointer */
mbed_official 121:7f86b4238bec 6843 #define FTM1 ((FTM_Type *)FTM1_BASE)
mbed_official 121:7f86b4238bec 6844 /** Peripheral FTM2 base address */
mbed_official 121:7f86b4238bec 6845 #define FTM2_BASE (0x4003A000u)
mbed_official 121:7f86b4238bec 6846 /** Peripheral FTM2 base pointer */
mbed_official 121:7f86b4238bec 6847 #define FTM2 ((FTM_Type *)FTM2_BASE)
mbed_official 121:7f86b4238bec 6848 /** Peripheral FTM3 base address */
mbed_official 121:7f86b4238bec 6849 #define FTM3_BASE (0x400B9000u)
mbed_official 121:7f86b4238bec 6850 /** Peripheral FTM3 base pointer */
mbed_official 121:7f86b4238bec 6851 #define FTM3 ((FTM_Type *)FTM3_BASE)
mbed_official 121:7f86b4238bec 6852 /** Array initializer of FTM peripheral base addresses */
mbed_official 121:7f86b4238bec 6853 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
mbed_official 121:7f86b4238bec 6854 /** Array initializer of FTM peripheral base pointers */
mbed_official 121:7f86b4238bec 6855 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
mbed_official 121:7f86b4238bec 6856 /** Interrupt vectors for the FTM peripheral type */
mbed_official 121:7f86b4238bec 6857 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
mbed_official 121:7f86b4238bec 6858
mbed_official 121:7f86b4238bec 6859 /*!
mbed_official 121:7f86b4238bec 6860 * @}
mbed_official 121:7f86b4238bec 6861 */ /* end of group FTM_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 6862
mbed_official 121:7f86b4238bec 6863
mbed_official 121:7f86b4238bec 6864 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 6865 -- GPIO Peripheral Access Layer
mbed_official 121:7f86b4238bec 6866 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 6867
mbed_official 121:7f86b4238bec 6868 /*!
mbed_official 121:7f86b4238bec 6869 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mbed_official 121:7f86b4238bec 6870 * @{
mbed_official 121:7f86b4238bec 6871 */
mbed_official 121:7f86b4238bec 6872
mbed_official 121:7f86b4238bec 6873 /** GPIO - Register Layout Typedef */
mbed_official 121:7f86b4238bec 6874 typedef struct {
mbed_official 121:7f86b4238bec 6875 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 6876 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 6877 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 6878 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 121:7f86b4238bec 6879 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 121:7f86b4238bec 6880 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 121:7f86b4238bec 6881 } GPIO_Type;
mbed_official 121:7f86b4238bec 6882
mbed_official 121:7f86b4238bec 6883 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 6884 -- GPIO Register Masks
mbed_official 121:7f86b4238bec 6885 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 6886
mbed_official 121:7f86b4238bec 6887 /*!
mbed_official 121:7f86b4238bec 6888 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mbed_official 121:7f86b4238bec 6889 * @{
mbed_official 121:7f86b4238bec 6890 */
mbed_official 121:7f86b4238bec 6891
mbed_official 121:7f86b4238bec 6892 /*! @name PDOR - Port Data Output Register */
mbed_official 121:7f86b4238bec 6893 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 6894 #define GPIO_PDOR_PDO_SHIFT (0U)
mbed_official 121:7f86b4238bec 6895 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
mbed_official 121:7f86b4238bec 6896
mbed_official 121:7f86b4238bec 6897 /*! @name PSOR - Port Set Output Register */
mbed_official 121:7f86b4238bec 6898 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 6899 #define GPIO_PSOR_PTSO_SHIFT (0U)
mbed_official 121:7f86b4238bec 6900 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
mbed_official 121:7f86b4238bec 6901
mbed_official 121:7f86b4238bec 6902 /*! @name PCOR - Port Clear Output Register */
mbed_official 121:7f86b4238bec 6903 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 6904 #define GPIO_PCOR_PTCO_SHIFT (0U)
mbed_official 121:7f86b4238bec 6905 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
mbed_official 121:7f86b4238bec 6906
mbed_official 121:7f86b4238bec 6907 /*! @name PTOR - Port Toggle Output Register */
mbed_official 121:7f86b4238bec 6908 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 6909 #define GPIO_PTOR_PTTO_SHIFT (0U)
mbed_official 121:7f86b4238bec 6910 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
mbed_official 121:7f86b4238bec 6911
mbed_official 121:7f86b4238bec 6912 /*! @name PDIR - Port Data Input Register */
mbed_official 121:7f86b4238bec 6913 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 6914 #define GPIO_PDIR_PDI_SHIFT (0U)
mbed_official 121:7f86b4238bec 6915 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
mbed_official 121:7f86b4238bec 6916
mbed_official 121:7f86b4238bec 6917 /*! @name PDDR - Port Data Direction Register */
mbed_official 121:7f86b4238bec 6918 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 6919 #define GPIO_PDDR_PDD_SHIFT (0U)
mbed_official 121:7f86b4238bec 6920 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
mbed_official 121:7f86b4238bec 6921
mbed_official 121:7f86b4238bec 6922
mbed_official 121:7f86b4238bec 6923 /*!
mbed_official 121:7f86b4238bec 6924 * @}
mbed_official 121:7f86b4238bec 6925 */ /* end of group GPIO_Register_Masks */
mbed_official 121:7f86b4238bec 6926
mbed_official 121:7f86b4238bec 6927
mbed_official 121:7f86b4238bec 6928 /* GPIO - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 6929 /** Peripheral PTA base address */
mbed_official 121:7f86b4238bec 6930 #define PTA_BASE (0x400FF000u)
mbed_official 121:7f86b4238bec 6931 /** Peripheral PTA base pointer */
mbed_official 121:7f86b4238bec 6932 #define PTA ((GPIO_Type *)PTA_BASE)
mbed_official 121:7f86b4238bec 6933 /** Peripheral PTB base address */
mbed_official 121:7f86b4238bec 6934 #define PTB_BASE (0x400FF040u)
mbed_official 121:7f86b4238bec 6935 /** Peripheral PTB base pointer */
mbed_official 121:7f86b4238bec 6936 #define PTB ((GPIO_Type *)PTB_BASE)
mbed_official 121:7f86b4238bec 6937 /** Peripheral PTC base address */
mbed_official 121:7f86b4238bec 6938 #define PTC_BASE (0x400FF080u)
mbed_official 121:7f86b4238bec 6939 /** Peripheral PTC base pointer */
mbed_official 121:7f86b4238bec 6940 #define PTC ((GPIO_Type *)PTC_BASE)
mbed_official 121:7f86b4238bec 6941 /** Peripheral PTD base address */
mbed_official 121:7f86b4238bec 6942 #define PTD_BASE (0x400FF0C0u)
mbed_official 121:7f86b4238bec 6943 /** Peripheral PTD base pointer */
mbed_official 121:7f86b4238bec 6944 #define PTD ((GPIO_Type *)PTD_BASE)
mbed_official 121:7f86b4238bec 6945 /** Peripheral PTE base address */
mbed_official 121:7f86b4238bec 6946 #define PTE_BASE (0x400FF100u)
mbed_official 121:7f86b4238bec 6947 /** Peripheral PTE base pointer */
mbed_official 121:7f86b4238bec 6948 #define PTE ((GPIO_Type *)PTE_BASE)
mbed_official 121:7f86b4238bec 6949 /** Array initializer of GPIO peripheral base addresses */
mbed_official 121:7f86b4238bec 6950 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
mbed_official 121:7f86b4238bec 6951 /** Array initializer of GPIO peripheral base pointers */
mbed_official 121:7f86b4238bec 6952 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
mbed_official 121:7f86b4238bec 6953
mbed_official 121:7f86b4238bec 6954 /*!
mbed_official 121:7f86b4238bec 6955 * @}
mbed_official 121:7f86b4238bec 6956 */ /* end of group GPIO_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 6957
mbed_official 121:7f86b4238bec 6958
mbed_official 121:7f86b4238bec 6959 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 6960 -- I2C Peripheral Access Layer
mbed_official 121:7f86b4238bec 6961 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 6962
mbed_official 121:7f86b4238bec 6963 /*!
mbed_official 121:7f86b4238bec 6964 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mbed_official 121:7f86b4238bec 6965 * @{
mbed_official 121:7f86b4238bec 6966 */
mbed_official 121:7f86b4238bec 6967
mbed_official 121:7f86b4238bec 6968 /** I2C - Register Layout Typedef */
mbed_official 121:7f86b4238bec 6969 typedef struct {
mbed_official 121:7f86b4238bec 6970 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mbed_official 121:7f86b4238bec 6971 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mbed_official 121:7f86b4238bec 6972 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mbed_official 121:7f86b4238bec 6973 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
mbed_official 121:7f86b4238bec 6974 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mbed_official 121:7f86b4238bec 6975 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mbed_official 121:7f86b4238bec 6976 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
mbed_official 121:7f86b4238bec 6977 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mbed_official 121:7f86b4238bec 6978 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mbed_official 121:7f86b4238bec 6979 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mbed_official 121:7f86b4238bec 6980 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mbed_official 121:7f86b4238bec 6981 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mbed_official 121:7f86b4238bec 6982 } I2C_Type;
mbed_official 121:7f86b4238bec 6983
mbed_official 121:7f86b4238bec 6984 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 6985 -- I2C Register Masks
mbed_official 121:7f86b4238bec 6986 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 6987
mbed_official 121:7f86b4238bec 6988 /*!
mbed_official 121:7f86b4238bec 6989 * @addtogroup I2C_Register_Masks I2C Register Masks
mbed_official 121:7f86b4238bec 6990 * @{
mbed_official 121:7f86b4238bec 6991 */
mbed_official 121:7f86b4238bec 6992
mbed_official 121:7f86b4238bec 6993 /*! @name A1 - I2C Address Register 1 */
mbed_official 121:7f86b4238bec 6994 #define I2C_A1_AD_MASK (0xFEU)
mbed_official 121:7f86b4238bec 6995 #define I2C_A1_AD_SHIFT (1U)
mbed_official 121:7f86b4238bec 6996 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
mbed_official 121:7f86b4238bec 6997
mbed_official 121:7f86b4238bec 6998 /*! @name F - I2C Frequency Divider register */
mbed_official 121:7f86b4238bec 6999 #define I2C_F_ICR_MASK (0x3FU)
mbed_official 121:7f86b4238bec 7000 #define I2C_F_ICR_SHIFT (0U)
mbed_official 121:7f86b4238bec 7001 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
mbed_official 121:7f86b4238bec 7002 #define I2C_F_MULT_MASK (0xC0U)
mbed_official 121:7f86b4238bec 7003 #define I2C_F_MULT_SHIFT (6U)
mbed_official 121:7f86b4238bec 7004 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
mbed_official 121:7f86b4238bec 7005
mbed_official 121:7f86b4238bec 7006 /*! @name C1 - I2C Control Register 1 */
mbed_official 121:7f86b4238bec 7007 #define I2C_C1_DMAEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 7008 #define I2C_C1_DMAEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 7009 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
mbed_official 121:7f86b4238bec 7010 #define I2C_C1_WUEN_MASK (0x2U)
mbed_official 121:7f86b4238bec 7011 #define I2C_C1_WUEN_SHIFT (1U)
mbed_official 121:7f86b4238bec 7012 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
mbed_official 121:7f86b4238bec 7013 #define I2C_C1_RSTA_MASK (0x4U)
mbed_official 121:7f86b4238bec 7014 #define I2C_C1_RSTA_SHIFT (2U)
mbed_official 121:7f86b4238bec 7015 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
mbed_official 121:7f86b4238bec 7016 #define I2C_C1_TXAK_MASK (0x8U)
mbed_official 121:7f86b4238bec 7017 #define I2C_C1_TXAK_SHIFT (3U)
mbed_official 121:7f86b4238bec 7018 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
mbed_official 121:7f86b4238bec 7019 #define I2C_C1_TX_MASK (0x10U)
mbed_official 121:7f86b4238bec 7020 #define I2C_C1_TX_SHIFT (4U)
mbed_official 121:7f86b4238bec 7021 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
mbed_official 121:7f86b4238bec 7022 #define I2C_C1_MST_MASK (0x20U)
mbed_official 121:7f86b4238bec 7023 #define I2C_C1_MST_SHIFT (5U)
mbed_official 121:7f86b4238bec 7024 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
mbed_official 121:7f86b4238bec 7025 #define I2C_C1_IICIE_MASK (0x40U)
mbed_official 121:7f86b4238bec 7026 #define I2C_C1_IICIE_SHIFT (6U)
mbed_official 121:7f86b4238bec 7027 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
mbed_official 121:7f86b4238bec 7028 #define I2C_C1_IICEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 7029 #define I2C_C1_IICEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 7030 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
mbed_official 121:7f86b4238bec 7031
mbed_official 121:7f86b4238bec 7032 /*! @name S - I2C Status register */
mbed_official 121:7f86b4238bec 7033 #define I2C_S_RXAK_MASK (0x1U)
mbed_official 121:7f86b4238bec 7034 #define I2C_S_RXAK_SHIFT (0U)
mbed_official 121:7f86b4238bec 7035 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
mbed_official 121:7f86b4238bec 7036 #define I2C_S_IICIF_MASK (0x2U)
mbed_official 121:7f86b4238bec 7037 #define I2C_S_IICIF_SHIFT (1U)
mbed_official 121:7f86b4238bec 7038 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
mbed_official 121:7f86b4238bec 7039 #define I2C_S_SRW_MASK (0x4U)
mbed_official 121:7f86b4238bec 7040 #define I2C_S_SRW_SHIFT (2U)
mbed_official 121:7f86b4238bec 7041 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
mbed_official 121:7f86b4238bec 7042 #define I2C_S_RAM_MASK (0x8U)
mbed_official 121:7f86b4238bec 7043 #define I2C_S_RAM_SHIFT (3U)
mbed_official 121:7f86b4238bec 7044 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
mbed_official 121:7f86b4238bec 7045 #define I2C_S_ARBL_MASK (0x10U)
mbed_official 121:7f86b4238bec 7046 #define I2C_S_ARBL_SHIFT (4U)
mbed_official 121:7f86b4238bec 7047 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
mbed_official 121:7f86b4238bec 7048 #define I2C_S_BUSY_MASK (0x20U)
mbed_official 121:7f86b4238bec 7049 #define I2C_S_BUSY_SHIFT (5U)
mbed_official 121:7f86b4238bec 7050 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
mbed_official 121:7f86b4238bec 7051 #define I2C_S_IAAS_MASK (0x40U)
mbed_official 121:7f86b4238bec 7052 #define I2C_S_IAAS_SHIFT (6U)
mbed_official 121:7f86b4238bec 7053 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
mbed_official 121:7f86b4238bec 7054 #define I2C_S_TCF_MASK (0x80U)
mbed_official 121:7f86b4238bec 7055 #define I2C_S_TCF_SHIFT (7U)
mbed_official 121:7f86b4238bec 7056 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
mbed_official 121:7f86b4238bec 7057
mbed_official 121:7f86b4238bec 7058 /*! @name D - I2C Data I/O register */
mbed_official 121:7f86b4238bec 7059 #define I2C_D_DATA_MASK (0xFFU)
mbed_official 121:7f86b4238bec 7060 #define I2C_D_DATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 7061 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
mbed_official 121:7f86b4238bec 7062
mbed_official 121:7f86b4238bec 7063 /*! @name C2 - I2C Control Register 2 */
mbed_official 121:7f86b4238bec 7064 #define I2C_C2_AD_MASK (0x7U)
mbed_official 121:7f86b4238bec 7065 #define I2C_C2_AD_SHIFT (0U)
mbed_official 121:7f86b4238bec 7066 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
mbed_official 121:7f86b4238bec 7067 #define I2C_C2_RMEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 7068 #define I2C_C2_RMEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 7069 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
mbed_official 121:7f86b4238bec 7070 #define I2C_C2_SBRC_MASK (0x10U)
mbed_official 121:7f86b4238bec 7071 #define I2C_C2_SBRC_SHIFT (4U)
mbed_official 121:7f86b4238bec 7072 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
mbed_official 121:7f86b4238bec 7073 #define I2C_C2_HDRS_MASK (0x20U)
mbed_official 121:7f86b4238bec 7074 #define I2C_C2_HDRS_SHIFT (5U)
mbed_official 121:7f86b4238bec 7075 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
mbed_official 121:7f86b4238bec 7076 #define I2C_C2_ADEXT_MASK (0x40U)
mbed_official 121:7f86b4238bec 7077 #define I2C_C2_ADEXT_SHIFT (6U)
mbed_official 121:7f86b4238bec 7078 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
mbed_official 121:7f86b4238bec 7079 #define I2C_C2_GCAEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 7080 #define I2C_C2_GCAEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 7081 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
mbed_official 121:7f86b4238bec 7082
mbed_official 121:7f86b4238bec 7083 /*! @name FLT - I2C Programmable Input Glitch Filter register */
mbed_official 121:7f86b4238bec 7084 #define I2C_FLT_FLT_MASK (0xFU)
mbed_official 121:7f86b4238bec 7085 #define I2C_FLT_FLT_SHIFT (0U)
mbed_official 121:7f86b4238bec 7086 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
mbed_official 121:7f86b4238bec 7087 #define I2C_FLT_STARTF_MASK (0x10U)
mbed_official 121:7f86b4238bec 7088 #define I2C_FLT_STARTF_SHIFT (4U)
mbed_official 121:7f86b4238bec 7089 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
mbed_official 121:7f86b4238bec 7090 #define I2C_FLT_SSIE_MASK (0x20U)
mbed_official 121:7f86b4238bec 7091 #define I2C_FLT_SSIE_SHIFT (5U)
mbed_official 121:7f86b4238bec 7092 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
mbed_official 121:7f86b4238bec 7093 #define I2C_FLT_STOPF_MASK (0x40U)
mbed_official 121:7f86b4238bec 7094 #define I2C_FLT_STOPF_SHIFT (6U)
mbed_official 121:7f86b4238bec 7095 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
mbed_official 121:7f86b4238bec 7096 #define I2C_FLT_SHEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 7097 #define I2C_FLT_SHEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 7098 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
mbed_official 121:7f86b4238bec 7099
mbed_official 121:7f86b4238bec 7100 /*! @name RA - I2C Range Address register */
mbed_official 121:7f86b4238bec 7101 #define I2C_RA_RAD_MASK (0xFEU)
mbed_official 121:7f86b4238bec 7102 #define I2C_RA_RAD_SHIFT (1U)
mbed_official 121:7f86b4238bec 7103 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
mbed_official 121:7f86b4238bec 7104
mbed_official 121:7f86b4238bec 7105 /*! @name SMB - I2C SMBus Control and Status register */
mbed_official 121:7f86b4238bec 7106 #define I2C_SMB_SHTF2IE_MASK (0x1U)
mbed_official 121:7f86b4238bec 7107 #define I2C_SMB_SHTF2IE_SHIFT (0U)
mbed_official 121:7f86b4238bec 7108 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
mbed_official 121:7f86b4238bec 7109 #define I2C_SMB_SHTF2_MASK (0x2U)
mbed_official 121:7f86b4238bec 7110 #define I2C_SMB_SHTF2_SHIFT (1U)
mbed_official 121:7f86b4238bec 7111 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
mbed_official 121:7f86b4238bec 7112 #define I2C_SMB_SHTF1_MASK (0x4U)
mbed_official 121:7f86b4238bec 7113 #define I2C_SMB_SHTF1_SHIFT (2U)
mbed_official 121:7f86b4238bec 7114 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
mbed_official 121:7f86b4238bec 7115 #define I2C_SMB_SLTF_MASK (0x8U)
mbed_official 121:7f86b4238bec 7116 #define I2C_SMB_SLTF_SHIFT (3U)
mbed_official 121:7f86b4238bec 7117 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
mbed_official 121:7f86b4238bec 7118 #define I2C_SMB_TCKSEL_MASK (0x10U)
mbed_official 121:7f86b4238bec 7119 #define I2C_SMB_TCKSEL_SHIFT (4U)
mbed_official 121:7f86b4238bec 7120 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
mbed_official 121:7f86b4238bec 7121 #define I2C_SMB_SIICAEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 7122 #define I2C_SMB_SIICAEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 7123 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
mbed_official 121:7f86b4238bec 7124 #define I2C_SMB_ALERTEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 7125 #define I2C_SMB_ALERTEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 7126 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
mbed_official 121:7f86b4238bec 7127 #define I2C_SMB_FACK_MASK (0x80U)
mbed_official 121:7f86b4238bec 7128 #define I2C_SMB_FACK_SHIFT (7U)
mbed_official 121:7f86b4238bec 7129 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
mbed_official 121:7f86b4238bec 7130
mbed_official 121:7f86b4238bec 7131 /*! @name A2 - I2C Address Register 2 */
mbed_official 121:7f86b4238bec 7132 #define I2C_A2_SAD_MASK (0xFEU)
mbed_official 121:7f86b4238bec 7133 #define I2C_A2_SAD_SHIFT (1U)
mbed_official 121:7f86b4238bec 7134 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
mbed_official 121:7f86b4238bec 7135
mbed_official 121:7f86b4238bec 7136 /*! @name SLTH - I2C SCL Low Timeout Register High */
mbed_official 121:7f86b4238bec 7137 #define I2C_SLTH_SSLT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 7138 #define I2C_SLTH_SSLT_SHIFT (0U)
mbed_official 121:7f86b4238bec 7139 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
mbed_official 121:7f86b4238bec 7140
mbed_official 121:7f86b4238bec 7141 /*! @name SLTL - I2C SCL Low Timeout Register Low */
mbed_official 121:7f86b4238bec 7142 #define I2C_SLTL_SSLT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 7143 #define I2C_SLTL_SSLT_SHIFT (0U)
mbed_official 121:7f86b4238bec 7144 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
mbed_official 121:7f86b4238bec 7145
mbed_official 121:7f86b4238bec 7146
mbed_official 121:7f86b4238bec 7147 /*!
mbed_official 121:7f86b4238bec 7148 * @}
mbed_official 121:7f86b4238bec 7149 */ /* end of group I2C_Register_Masks */
mbed_official 121:7f86b4238bec 7150
mbed_official 121:7f86b4238bec 7151
mbed_official 121:7f86b4238bec 7152 /* I2C - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 7153 /** Peripheral I2C0 base address */
mbed_official 121:7f86b4238bec 7154 #define I2C0_BASE (0x40066000u)
mbed_official 121:7f86b4238bec 7155 /** Peripheral I2C0 base pointer */
mbed_official 121:7f86b4238bec 7156 #define I2C0 ((I2C_Type *)I2C0_BASE)
mbed_official 121:7f86b4238bec 7157 /** Peripheral I2C1 base address */
mbed_official 121:7f86b4238bec 7158 #define I2C1_BASE (0x40067000u)
mbed_official 121:7f86b4238bec 7159 /** Peripheral I2C1 base pointer */
mbed_official 121:7f86b4238bec 7160 #define I2C1 ((I2C_Type *)I2C1_BASE)
mbed_official 121:7f86b4238bec 7161 /** Peripheral I2C2 base address */
mbed_official 121:7f86b4238bec 7162 #define I2C2_BASE (0x400E6000u)
mbed_official 121:7f86b4238bec 7163 /** Peripheral I2C2 base pointer */
mbed_official 121:7f86b4238bec 7164 #define I2C2 ((I2C_Type *)I2C2_BASE)
mbed_official 121:7f86b4238bec 7165 /** Array initializer of I2C peripheral base addresses */
mbed_official 121:7f86b4238bec 7166 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
mbed_official 121:7f86b4238bec 7167 /** Array initializer of I2C peripheral base pointers */
mbed_official 121:7f86b4238bec 7168 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
mbed_official 121:7f86b4238bec 7169 /** Interrupt vectors for the I2C peripheral type */
mbed_official 121:7f86b4238bec 7170 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
mbed_official 121:7f86b4238bec 7171
mbed_official 121:7f86b4238bec 7172 /*!
mbed_official 121:7f86b4238bec 7173 * @}
mbed_official 121:7f86b4238bec 7174 */ /* end of group I2C_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 7175
mbed_official 121:7f86b4238bec 7176
mbed_official 121:7f86b4238bec 7177 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 7178 -- I2S Peripheral Access Layer
mbed_official 121:7f86b4238bec 7179 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 7180
mbed_official 121:7f86b4238bec 7181 /*!
mbed_official 121:7f86b4238bec 7182 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
mbed_official 121:7f86b4238bec 7183 * @{
mbed_official 121:7f86b4238bec 7184 */
mbed_official 121:7f86b4238bec 7185
mbed_official 121:7f86b4238bec 7186 /** I2S - Register Layout Typedef */
mbed_official 121:7f86b4238bec 7187 typedef struct {
mbed_official 121:7f86b4238bec 7188 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 7189 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 7190 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 7191 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
mbed_official 121:7f86b4238bec 7192 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
mbed_official 121:7f86b4238bec 7193 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
mbed_official 121:7f86b4238bec 7194 uint8_t RESERVED_0[8];
mbed_official 121:7f86b4238bec 7195 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
mbed_official 121:7f86b4238bec 7196 uint8_t RESERVED_1[24];
mbed_official 121:7f86b4238bec 7197 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
mbed_official 121:7f86b4238bec 7198 uint8_t RESERVED_2[24];
mbed_official 121:7f86b4238bec 7199 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
mbed_official 121:7f86b4238bec 7200 uint8_t RESERVED_3[28];
mbed_official 121:7f86b4238bec 7201 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
mbed_official 121:7f86b4238bec 7202 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
mbed_official 121:7f86b4238bec 7203 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
mbed_official 121:7f86b4238bec 7204 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
mbed_official 121:7f86b4238bec 7205 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
mbed_official 121:7f86b4238bec 7206 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
mbed_official 121:7f86b4238bec 7207 uint8_t RESERVED_4[8];
mbed_official 121:7f86b4238bec 7208 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
mbed_official 121:7f86b4238bec 7209 uint8_t RESERVED_5[24];
mbed_official 121:7f86b4238bec 7210 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
mbed_official 121:7f86b4238bec 7211 uint8_t RESERVED_6[24];
mbed_official 121:7f86b4238bec 7212 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
mbed_official 121:7f86b4238bec 7213 uint8_t RESERVED_7[28];
mbed_official 121:7f86b4238bec 7214 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
mbed_official 121:7f86b4238bec 7215 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
mbed_official 121:7f86b4238bec 7216 } I2S_Type;
mbed_official 121:7f86b4238bec 7217
mbed_official 121:7f86b4238bec 7218 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 7219 -- I2S Register Masks
mbed_official 121:7f86b4238bec 7220 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 7221
mbed_official 121:7f86b4238bec 7222 /*!
mbed_official 121:7f86b4238bec 7223 * @addtogroup I2S_Register_Masks I2S Register Masks
mbed_official 121:7f86b4238bec 7224 * @{
mbed_official 121:7f86b4238bec 7225 */
mbed_official 121:7f86b4238bec 7226
mbed_official 121:7f86b4238bec 7227 /*! @name TCSR - SAI Transmit Control Register */
mbed_official 121:7f86b4238bec 7228 #define I2S_TCSR_FRDE_MASK (0x1U)
mbed_official 121:7f86b4238bec 7229 #define I2S_TCSR_FRDE_SHIFT (0U)
mbed_official 121:7f86b4238bec 7230 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
mbed_official 121:7f86b4238bec 7231 #define I2S_TCSR_FWDE_MASK (0x2U)
mbed_official 121:7f86b4238bec 7232 #define I2S_TCSR_FWDE_SHIFT (1U)
mbed_official 121:7f86b4238bec 7233 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
mbed_official 121:7f86b4238bec 7234 #define I2S_TCSR_FRIE_MASK (0x100U)
mbed_official 121:7f86b4238bec 7235 #define I2S_TCSR_FRIE_SHIFT (8U)
mbed_official 121:7f86b4238bec 7236 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
mbed_official 121:7f86b4238bec 7237 #define I2S_TCSR_FWIE_MASK (0x200U)
mbed_official 121:7f86b4238bec 7238 #define I2S_TCSR_FWIE_SHIFT (9U)
mbed_official 121:7f86b4238bec 7239 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
mbed_official 121:7f86b4238bec 7240 #define I2S_TCSR_FEIE_MASK (0x400U)
mbed_official 121:7f86b4238bec 7241 #define I2S_TCSR_FEIE_SHIFT (10U)
mbed_official 121:7f86b4238bec 7242 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
mbed_official 121:7f86b4238bec 7243 #define I2S_TCSR_SEIE_MASK (0x800U)
mbed_official 121:7f86b4238bec 7244 #define I2S_TCSR_SEIE_SHIFT (11U)
mbed_official 121:7f86b4238bec 7245 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
mbed_official 121:7f86b4238bec 7246 #define I2S_TCSR_WSIE_MASK (0x1000U)
mbed_official 121:7f86b4238bec 7247 #define I2S_TCSR_WSIE_SHIFT (12U)
mbed_official 121:7f86b4238bec 7248 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
mbed_official 121:7f86b4238bec 7249 #define I2S_TCSR_FRF_MASK (0x10000U)
mbed_official 121:7f86b4238bec 7250 #define I2S_TCSR_FRF_SHIFT (16U)
mbed_official 121:7f86b4238bec 7251 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
mbed_official 121:7f86b4238bec 7252 #define I2S_TCSR_FWF_MASK (0x20000U)
mbed_official 121:7f86b4238bec 7253 #define I2S_TCSR_FWF_SHIFT (17U)
mbed_official 121:7f86b4238bec 7254 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
mbed_official 121:7f86b4238bec 7255 #define I2S_TCSR_FEF_MASK (0x40000U)
mbed_official 121:7f86b4238bec 7256 #define I2S_TCSR_FEF_SHIFT (18U)
mbed_official 121:7f86b4238bec 7257 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
mbed_official 121:7f86b4238bec 7258 #define I2S_TCSR_SEF_MASK (0x80000U)
mbed_official 121:7f86b4238bec 7259 #define I2S_TCSR_SEF_SHIFT (19U)
mbed_official 121:7f86b4238bec 7260 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
mbed_official 121:7f86b4238bec 7261 #define I2S_TCSR_WSF_MASK (0x100000U)
mbed_official 121:7f86b4238bec 7262 #define I2S_TCSR_WSF_SHIFT (20U)
mbed_official 121:7f86b4238bec 7263 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
mbed_official 121:7f86b4238bec 7264 #define I2S_TCSR_SR_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 7265 #define I2S_TCSR_SR_SHIFT (24U)
mbed_official 121:7f86b4238bec 7266 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
mbed_official 121:7f86b4238bec 7267 #define I2S_TCSR_FR_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 7268 #define I2S_TCSR_FR_SHIFT (25U)
mbed_official 121:7f86b4238bec 7269 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
mbed_official 121:7f86b4238bec 7270 #define I2S_TCSR_BCE_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 7271 #define I2S_TCSR_BCE_SHIFT (28U)
mbed_official 121:7f86b4238bec 7272 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
mbed_official 121:7f86b4238bec 7273 #define I2S_TCSR_DBGE_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 7274 #define I2S_TCSR_DBGE_SHIFT (29U)
mbed_official 121:7f86b4238bec 7275 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
mbed_official 121:7f86b4238bec 7276 #define I2S_TCSR_STOPE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 7277 #define I2S_TCSR_STOPE_SHIFT (30U)
mbed_official 121:7f86b4238bec 7278 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
mbed_official 121:7f86b4238bec 7279 #define I2S_TCSR_TE_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 7280 #define I2S_TCSR_TE_SHIFT (31U)
mbed_official 121:7f86b4238bec 7281 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
mbed_official 121:7f86b4238bec 7282
mbed_official 121:7f86b4238bec 7283 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
mbed_official 121:7f86b4238bec 7284 #define I2S_TCR1_TFW_MASK (0x7U)
mbed_official 121:7f86b4238bec 7285 #define I2S_TCR1_TFW_SHIFT (0U)
mbed_official 121:7f86b4238bec 7286 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
mbed_official 121:7f86b4238bec 7287
mbed_official 121:7f86b4238bec 7288 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
mbed_official 121:7f86b4238bec 7289 #define I2S_TCR2_DIV_MASK (0xFFU)
mbed_official 121:7f86b4238bec 7290 #define I2S_TCR2_DIV_SHIFT (0U)
mbed_official 121:7f86b4238bec 7291 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
mbed_official 121:7f86b4238bec 7292 #define I2S_TCR2_BCD_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 7293 #define I2S_TCR2_BCD_SHIFT (24U)
mbed_official 121:7f86b4238bec 7294 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
mbed_official 121:7f86b4238bec 7295 #define I2S_TCR2_BCP_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 7296 #define I2S_TCR2_BCP_SHIFT (25U)
mbed_official 121:7f86b4238bec 7297 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
mbed_official 121:7f86b4238bec 7298 #define I2S_TCR2_MSEL_MASK (0xC000000U)
mbed_official 121:7f86b4238bec 7299 #define I2S_TCR2_MSEL_SHIFT (26U)
mbed_official 121:7f86b4238bec 7300 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
mbed_official 121:7f86b4238bec 7301 #define I2S_TCR2_BCI_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 7302 #define I2S_TCR2_BCI_SHIFT (28U)
mbed_official 121:7f86b4238bec 7303 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
mbed_official 121:7f86b4238bec 7304 #define I2S_TCR2_BCS_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 7305 #define I2S_TCR2_BCS_SHIFT (29U)
mbed_official 121:7f86b4238bec 7306 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
mbed_official 121:7f86b4238bec 7307 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
mbed_official 121:7f86b4238bec 7308 #define I2S_TCR2_SYNC_SHIFT (30U)
mbed_official 121:7f86b4238bec 7309 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
mbed_official 121:7f86b4238bec 7310
mbed_official 121:7f86b4238bec 7311 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
mbed_official 121:7f86b4238bec 7312 #define I2S_TCR3_WDFL_MASK (0x1FU)
mbed_official 121:7f86b4238bec 7313 #define I2S_TCR3_WDFL_SHIFT (0U)
mbed_official 121:7f86b4238bec 7314 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
mbed_official 121:7f86b4238bec 7315 #define I2S_TCR3_TCE_MASK (0x30000U)
mbed_official 121:7f86b4238bec 7316 #define I2S_TCR3_TCE_SHIFT (16U)
mbed_official 121:7f86b4238bec 7317 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
mbed_official 121:7f86b4238bec 7318
mbed_official 121:7f86b4238bec 7319 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
mbed_official 121:7f86b4238bec 7320 #define I2S_TCR4_FSD_MASK (0x1U)
mbed_official 121:7f86b4238bec 7321 #define I2S_TCR4_FSD_SHIFT (0U)
mbed_official 121:7f86b4238bec 7322 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
mbed_official 121:7f86b4238bec 7323 #define I2S_TCR4_FSP_MASK (0x2U)
mbed_official 121:7f86b4238bec 7324 #define I2S_TCR4_FSP_SHIFT (1U)
mbed_official 121:7f86b4238bec 7325 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
mbed_official 121:7f86b4238bec 7326 #define I2S_TCR4_FSE_MASK (0x8U)
mbed_official 121:7f86b4238bec 7327 #define I2S_TCR4_FSE_SHIFT (3U)
mbed_official 121:7f86b4238bec 7328 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
mbed_official 121:7f86b4238bec 7329 #define I2S_TCR4_MF_MASK (0x10U)
mbed_official 121:7f86b4238bec 7330 #define I2S_TCR4_MF_SHIFT (4U)
mbed_official 121:7f86b4238bec 7331 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
mbed_official 121:7f86b4238bec 7332 #define I2S_TCR4_SYWD_MASK (0x1F00U)
mbed_official 121:7f86b4238bec 7333 #define I2S_TCR4_SYWD_SHIFT (8U)
mbed_official 121:7f86b4238bec 7334 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
mbed_official 121:7f86b4238bec 7335 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
mbed_official 121:7f86b4238bec 7336 #define I2S_TCR4_FRSZ_SHIFT (16U)
mbed_official 121:7f86b4238bec 7337 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
mbed_official 121:7f86b4238bec 7338
mbed_official 121:7f86b4238bec 7339 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
mbed_official 121:7f86b4238bec 7340 #define I2S_TCR5_FBT_MASK (0x1F00U)
mbed_official 121:7f86b4238bec 7341 #define I2S_TCR5_FBT_SHIFT (8U)
mbed_official 121:7f86b4238bec 7342 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
mbed_official 121:7f86b4238bec 7343 #define I2S_TCR5_W0W_MASK (0x1F0000U)
mbed_official 121:7f86b4238bec 7344 #define I2S_TCR5_W0W_SHIFT (16U)
mbed_official 121:7f86b4238bec 7345 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
mbed_official 121:7f86b4238bec 7346 #define I2S_TCR5_WNW_MASK (0x1F000000U)
mbed_official 121:7f86b4238bec 7347 #define I2S_TCR5_WNW_SHIFT (24U)
mbed_official 121:7f86b4238bec 7348 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
mbed_official 121:7f86b4238bec 7349
mbed_official 121:7f86b4238bec 7350 /*! @name TDR - SAI Transmit Data Register */
mbed_official 121:7f86b4238bec 7351 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 7352 #define I2S_TDR_TDR_SHIFT (0U)
mbed_official 121:7f86b4238bec 7353 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
mbed_official 121:7f86b4238bec 7354
mbed_official 121:7f86b4238bec 7355 /* The count of I2S_TDR */
mbed_official 121:7f86b4238bec 7356 #define I2S_TDR_COUNT (2U)
mbed_official 121:7f86b4238bec 7357
mbed_official 121:7f86b4238bec 7358 /*! @name TFR - SAI Transmit FIFO Register */
mbed_official 121:7f86b4238bec 7359 #define I2S_TFR_RFP_MASK (0xFU)
mbed_official 121:7f86b4238bec 7360 #define I2S_TFR_RFP_SHIFT (0U)
mbed_official 121:7f86b4238bec 7361 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
mbed_official 121:7f86b4238bec 7362 #define I2S_TFR_WFP_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 7363 #define I2S_TFR_WFP_SHIFT (16U)
mbed_official 121:7f86b4238bec 7364 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
mbed_official 121:7f86b4238bec 7365
mbed_official 121:7f86b4238bec 7366 /* The count of I2S_TFR */
mbed_official 121:7f86b4238bec 7367 #define I2S_TFR_COUNT (2U)
mbed_official 121:7f86b4238bec 7368
mbed_official 121:7f86b4238bec 7369 /*! @name TMR - SAI Transmit Mask Register */
mbed_official 121:7f86b4238bec 7370 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 7371 #define I2S_TMR_TWM_SHIFT (0U)
mbed_official 121:7f86b4238bec 7372 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
mbed_official 121:7f86b4238bec 7373
mbed_official 121:7f86b4238bec 7374 /*! @name RCSR - SAI Receive Control Register */
mbed_official 121:7f86b4238bec 7375 #define I2S_RCSR_FRDE_MASK (0x1U)
mbed_official 121:7f86b4238bec 7376 #define I2S_RCSR_FRDE_SHIFT (0U)
mbed_official 121:7f86b4238bec 7377 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
mbed_official 121:7f86b4238bec 7378 #define I2S_RCSR_FWDE_MASK (0x2U)
mbed_official 121:7f86b4238bec 7379 #define I2S_RCSR_FWDE_SHIFT (1U)
mbed_official 121:7f86b4238bec 7380 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
mbed_official 121:7f86b4238bec 7381 #define I2S_RCSR_FRIE_MASK (0x100U)
mbed_official 121:7f86b4238bec 7382 #define I2S_RCSR_FRIE_SHIFT (8U)
mbed_official 121:7f86b4238bec 7383 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
mbed_official 121:7f86b4238bec 7384 #define I2S_RCSR_FWIE_MASK (0x200U)
mbed_official 121:7f86b4238bec 7385 #define I2S_RCSR_FWIE_SHIFT (9U)
mbed_official 121:7f86b4238bec 7386 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
mbed_official 121:7f86b4238bec 7387 #define I2S_RCSR_FEIE_MASK (0x400U)
mbed_official 121:7f86b4238bec 7388 #define I2S_RCSR_FEIE_SHIFT (10U)
mbed_official 121:7f86b4238bec 7389 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
mbed_official 121:7f86b4238bec 7390 #define I2S_RCSR_SEIE_MASK (0x800U)
mbed_official 121:7f86b4238bec 7391 #define I2S_RCSR_SEIE_SHIFT (11U)
mbed_official 121:7f86b4238bec 7392 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
mbed_official 121:7f86b4238bec 7393 #define I2S_RCSR_WSIE_MASK (0x1000U)
mbed_official 121:7f86b4238bec 7394 #define I2S_RCSR_WSIE_SHIFT (12U)
mbed_official 121:7f86b4238bec 7395 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
mbed_official 121:7f86b4238bec 7396 #define I2S_RCSR_FRF_MASK (0x10000U)
mbed_official 121:7f86b4238bec 7397 #define I2S_RCSR_FRF_SHIFT (16U)
mbed_official 121:7f86b4238bec 7398 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
mbed_official 121:7f86b4238bec 7399 #define I2S_RCSR_FWF_MASK (0x20000U)
mbed_official 121:7f86b4238bec 7400 #define I2S_RCSR_FWF_SHIFT (17U)
mbed_official 121:7f86b4238bec 7401 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
mbed_official 121:7f86b4238bec 7402 #define I2S_RCSR_FEF_MASK (0x40000U)
mbed_official 121:7f86b4238bec 7403 #define I2S_RCSR_FEF_SHIFT (18U)
mbed_official 121:7f86b4238bec 7404 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
mbed_official 121:7f86b4238bec 7405 #define I2S_RCSR_SEF_MASK (0x80000U)
mbed_official 121:7f86b4238bec 7406 #define I2S_RCSR_SEF_SHIFT (19U)
mbed_official 121:7f86b4238bec 7407 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
mbed_official 121:7f86b4238bec 7408 #define I2S_RCSR_WSF_MASK (0x100000U)
mbed_official 121:7f86b4238bec 7409 #define I2S_RCSR_WSF_SHIFT (20U)
mbed_official 121:7f86b4238bec 7410 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
mbed_official 121:7f86b4238bec 7411 #define I2S_RCSR_SR_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 7412 #define I2S_RCSR_SR_SHIFT (24U)
mbed_official 121:7f86b4238bec 7413 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
mbed_official 121:7f86b4238bec 7414 #define I2S_RCSR_FR_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 7415 #define I2S_RCSR_FR_SHIFT (25U)
mbed_official 121:7f86b4238bec 7416 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
mbed_official 121:7f86b4238bec 7417 #define I2S_RCSR_BCE_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 7418 #define I2S_RCSR_BCE_SHIFT (28U)
mbed_official 121:7f86b4238bec 7419 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
mbed_official 121:7f86b4238bec 7420 #define I2S_RCSR_DBGE_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 7421 #define I2S_RCSR_DBGE_SHIFT (29U)
mbed_official 121:7f86b4238bec 7422 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
mbed_official 121:7f86b4238bec 7423 #define I2S_RCSR_STOPE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 7424 #define I2S_RCSR_STOPE_SHIFT (30U)
mbed_official 121:7f86b4238bec 7425 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
mbed_official 121:7f86b4238bec 7426 #define I2S_RCSR_RE_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 7427 #define I2S_RCSR_RE_SHIFT (31U)
mbed_official 121:7f86b4238bec 7428 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
mbed_official 121:7f86b4238bec 7429
mbed_official 121:7f86b4238bec 7430 /*! @name RCR1 - SAI Receive Configuration 1 Register */
mbed_official 121:7f86b4238bec 7431 #define I2S_RCR1_RFW_MASK (0x7U)
mbed_official 121:7f86b4238bec 7432 #define I2S_RCR1_RFW_SHIFT (0U)
mbed_official 121:7f86b4238bec 7433 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
mbed_official 121:7f86b4238bec 7434
mbed_official 121:7f86b4238bec 7435 /*! @name RCR2 - SAI Receive Configuration 2 Register */
mbed_official 121:7f86b4238bec 7436 #define I2S_RCR2_DIV_MASK (0xFFU)
mbed_official 121:7f86b4238bec 7437 #define I2S_RCR2_DIV_SHIFT (0U)
mbed_official 121:7f86b4238bec 7438 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
mbed_official 121:7f86b4238bec 7439 #define I2S_RCR2_BCD_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 7440 #define I2S_RCR2_BCD_SHIFT (24U)
mbed_official 121:7f86b4238bec 7441 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
mbed_official 121:7f86b4238bec 7442 #define I2S_RCR2_BCP_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 7443 #define I2S_RCR2_BCP_SHIFT (25U)
mbed_official 121:7f86b4238bec 7444 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
mbed_official 121:7f86b4238bec 7445 #define I2S_RCR2_MSEL_MASK (0xC000000U)
mbed_official 121:7f86b4238bec 7446 #define I2S_RCR2_MSEL_SHIFT (26U)
mbed_official 121:7f86b4238bec 7447 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
mbed_official 121:7f86b4238bec 7448 #define I2S_RCR2_BCI_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 7449 #define I2S_RCR2_BCI_SHIFT (28U)
mbed_official 121:7f86b4238bec 7450 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
mbed_official 121:7f86b4238bec 7451 #define I2S_RCR2_BCS_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 7452 #define I2S_RCR2_BCS_SHIFT (29U)
mbed_official 121:7f86b4238bec 7453 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
mbed_official 121:7f86b4238bec 7454 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
mbed_official 121:7f86b4238bec 7455 #define I2S_RCR2_SYNC_SHIFT (30U)
mbed_official 121:7f86b4238bec 7456 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
mbed_official 121:7f86b4238bec 7457
mbed_official 121:7f86b4238bec 7458 /*! @name RCR3 - SAI Receive Configuration 3 Register */
mbed_official 121:7f86b4238bec 7459 #define I2S_RCR3_WDFL_MASK (0x1FU)
mbed_official 121:7f86b4238bec 7460 #define I2S_RCR3_WDFL_SHIFT (0U)
mbed_official 121:7f86b4238bec 7461 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
mbed_official 121:7f86b4238bec 7462 #define I2S_RCR3_RCE_MASK (0x30000U)
mbed_official 121:7f86b4238bec 7463 #define I2S_RCR3_RCE_SHIFT (16U)
mbed_official 121:7f86b4238bec 7464 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
mbed_official 121:7f86b4238bec 7465
mbed_official 121:7f86b4238bec 7466 /*! @name RCR4 - SAI Receive Configuration 4 Register */
mbed_official 121:7f86b4238bec 7467 #define I2S_RCR4_FSD_MASK (0x1U)
mbed_official 121:7f86b4238bec 7468 #define I2S_RCR4_FSD_SHIFT (0U)
mbed_official 121:7f86b4238bec 7469 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
mbed_official 121:7f86b4238bec 7470 #define I2S_RCR4_FSP_MASK (0x2U)
mbed_official 121:7f86b4238bec 7471 #define I2S_RCR4_FSP_SHIFT (1U)
mbed_official 121:7f86b4238bec 7472 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
mbed_official 121:7f86b4238bec 7473 #define I2S_RCR4_FSE_MASK (0x8U)
mbed_official 121:7f86b4238bec 7474 #define I2S_RCR4_FSE_SHIFT (3U)
mbed_official 121:7f86b4238bec 7475 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
mbed_official 121:7f86b4238bec 7476 #define I2S_RCR4_MF_MASK (0x10U)
mbed_official 121:7f86b4238bec 7477 #define I2S_RCR4_MF_SHIFT (4U)
mbed_official 121:7f86b4238bec 7478 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
mbed_official 121:7f86b4238bec 7479 #define I2S_RCR4_SYWD_MASK (0x1F00U)
mbed_official 121:7f86b4238bec 7480 #define I2S_RCR4_SYWD_SHIFT (8U)
mbed_official 121:7f86b4238bec 7481 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
mbed_official 121:7f86b4238bec 7482 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
mbed_official 121:7f86b4238bec 7483 #define I2S_RCR4_FRSZ_SHIFT (16U)
mbed_official 121:7f86b4238bec 7484 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
mbed_official 121:7f86b4238bec 7485
mbed_official 121:7f86b4238bec 7486 /*! @name RCR5 - SAI Receive Configuration 5 Register */
mbed_official 121:7f86b4238bec 7487 #define I2S_RCR5_FBT_MASK (0x1F00U)
mbed_official 121:7f86b4238bec 7488 #define I2S_RCR5_FBT_SHIFT (8U)
mbed_official 121:7f86b4238bec 7489 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
mbed_official 121:7f86b4238bec 7490 #define I2S_RCR5_W0W_MASK (0x1F0000U)
mbed_official 121:7f86b4238bec 7491 #define I2S_RCR5_W0W_SHIFT (16U)
mbed_official 121:7f86b4238bec 7492 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
mbed_official 121:7f86b4238bec 7493 #define I2S_RCR5_WNW_MASK (0x1F000000U)
mbed_official 121:7f86b4238bec 7494 #define I2S_RCR5_WNW_SHIFT (24U)
mbed_official 121:7f86b4238bec 7495 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
mbed_official 121:7f86b4238bec 7496
mbed_official 121:7f86b4238bec 7497 /*! @name RDR - SAI Receive Data Register */
mbed_official 121:7f86b4238bec 7498 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 7499 #define I2S_RDR_RDR_SHIFT (0U)
mbed_official 121:7f86b4238bec 7500 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
mbed_official 121:7f86b4238bec 7501
mbed_official 121:7f86b4238bec 7502 /* The count of I2S_RDR */
mbed_official 121:7f86b4238bec 7503 #define I2S_RDR_COUNT (2U)
mbed_official 121:7f86b4238bec 7504
mbed_official 121:7f86b4238bec 7505 /*! @name RFR - SAI Receive FIFO Register */
mbed_official 121:7f86b4238bec 7506 #define I2S_RFR_RFP_MASK (0xFU)
mbed_official 121:7f86b4238bec 7507 #define I2S_RFR_RFP_SHIFT (0U)
mbed_official 121:7f86b4238bec 7508 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
mbed_official 121:7f86b4238bec 7509 #define I2S_RFR_WFP_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 7510 #define I2S_RFR_WFP_SHIFT (16U)
mbed_official 121:7f86b4238bec 7511 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
mbed_official 121:7f86b4238bec 7512
mbed_official 121:7f86b4238bec 7513 /* The count of I2S_RFR */
mbed_official 121:7f86b4238bec 7514 #define I2S_RFR_COUNT (2U)
mbed_official 121:7f86b4238bec 7515
mbed_official 121:7f86b4238bec 7516 /*! @name RMR - SAI Receive Mask Register */
mbed_official 121:7f86b4238bec 7517 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 7518 #define I2S_RMR_RWM_SHIFT (0U)
mbed_official 121:7f86b4238bec 7519 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
mbed_official 121:7f86b4238bec 7520
mbed_official 121:7f86b4238bec 7521 /*! @name MCR - SAI MCLK Control Register */
mbed_official 121:7f86b4238bec 7522 #define I2S_MCR_MICS_MASK (0x3000000U)
mbed_official 121:7f86b4238bec 7523 #define I2S_MCR_MICS_SHIFT (24U)
mbed_official 121:7f86b4238bec 7524 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
mbed_official 121:7f86b4238bec 7525 #define I2S_MCR_MOE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 7526 #define I2S_MCR_MOE_SHIFT (30U)
mbed_official 121:7f86b4238bec 7527 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
mbed_official 121:7f86b4238bec 7528 #define I2S_MCR_DUF_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 7529 #define I2S_MCR_DUF_SHIFT (31U)
mbed_official 121:7f86b4238bec 7530 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
mbed_official 121:7f86b4238bec 7531
mbed_official 121:7f86b4238bec 7532 /*! @name MDR - SAI MCLK Divide Register */
mbed_official 121:7f86b4238bec 7533 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
mbed_official 121:7f86b4238bec 7534 #define I2S_MDR_DIVIDE_SHIFT (0U)
mbed_official 121:7f86b4238bec 7535 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
mbed_official 121:7f86b4238bec 7536 #define I2S_MDR_FRACT_MASK (0xFF000U)
mbed_official 121:7f86b4238bec 7537 #define I2S_MDR_FRACT_SHIFT (12U)
mbed_official 121:7f86b4238bec 7538 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
mbed_official 121:7f86b4238bec 7539
mbed_official 121:7f86b4238bec 7540
mbed_official 121:7f86b4238bec 7541 /*!
mbed_official 121:7f86b4238bec 7542 * @}
mbed_official 121:7f86b4238bec 7543 */ /* end of group I2S_Register_Masks */
mbed_official 121:7f86b4238bec 7544
mbed_official 121:7f86b4238bec 7545
mbed_official 121:7f86b4238bec 7546 /* I2S - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 7547 /** Peripheral I2S0 base address */
mbed_official 121:7f86b4238bec 7548 #define I2S0_BASE (0x4002F000u)
mbed_official 121:7f86b4238bec 7549 /** Peripheral I2S0 base pointer */
mbed_official 121:7f86b4238bec 7550 #define I2S0 ((I2S_Type *)I2S0_BASE)
mbed_official 121:7f86b4238bec 7551 /** Array initializer of I2S peripheral base addresses */
mbed_official 121:7f86b4238bec 7552 #define I2S_BASE_ADDRS { I2S0_BASE }
mbed_official 121:7f86b4238bec 7553 /** Array initializer of I2S peripheral base pointers */
mbed_official 121:7f86b4238bec 7554 #define I2S_BASE_PTRS { I2S0 }
mbed_official 121:7f86b4238bec 7555 /** Interrupt vectors for the I2S peripheral type */
mbed_official 121:7f86b4238bec 7556 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
mbed_official 121:7f86b4238bec 7557 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
mbed_official 121:7f86b4238bec 7558
mbed_official 121:7f86b4238bec 7559 /*!
mbed_official 121:7f86b4238bec 7560 * @}
mbed_official 121:7f86b4238bec 7561 */ /* end of group I2S_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 7562
mbed_official 121:7f86b4238bec 7563
mbed_official 121:7f86b4238bec 7564 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 7565 -- LLWU Peripheral Access Layer
mbed_official 121:7f86b4238bec 7566 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 7567
mbed_official 121:7f86b4238bec 7568 /*!
mbed_official 121:7f86b4238bec 7569 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mbed_official 121:7f86b4238bec 7570 * @{
mbed_official 121:7f86b4238bec 7571 */
mbed_official 121:7f86b4238bec 7572
mbed_official 121:7f86b4238bec 7573 /** LLWU - Register Layout Typedef */
mbed_official 121:7f86b4238bec 7574 typedef struct {
mbed_official 121:7f86b4238bec 7575 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
mbed_official 121:7f86b4238bec 7576 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
mbed_official 121:7f86b4238bec 7577 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
mbed_official 121:7f86b4238bec 7578 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
mbed_official 121:7f86b4238bec 7579 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
mbed_official 121:7f86b4238bec 7580 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
mbed_official 121:7f86b4238bec 7581 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
mbed_official 121:7f86b4238bec 7582 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
mbed_official 121:7f86b4238bec 7583 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
mbed_official 121:7f86b4238bec 7584 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
mbed_official 121:7f86b4238bec 7585 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
mbed_official 121:7f86b4238bec 7586 } LLWU_Type;
mbed_official 121:7f86b4238bec 7587
mbed_official 121:7f86b4238bec 7588 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 7589 -- LLWU Register Masks
mbed_official 121:7f86b4238bec 7590 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 7591
mbed_official 121:7f86b4238bec 7592 /*!
mbed_official 121:7f86b4238bec 7593 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mbed_official 121:7f86b4238bec 7594 * @{
mbed_official 121:7f86b4238bec 7595 */
mbed_official 121:7f86b4238bec 7596
mbed_official 121:7f86b4238bec 7597 /*! @name PE1 - LLWU Pin Enable 1 register */
mbed_official 121:7f86b4238bec 7598 #define LLWU_PE1_WUPE0_MASK (0x3U)
mbed_official 121:7f86b4238bec 7599 #define LLWU_PE1_WUPE0_SHIFT (0U)
mbed_official 121:7f86b4238bec 7600 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
mbed_official 121:7f86b4238bec 7601 #define LLWU_PE1_WUPE1_MASK (0xCU)
mbed_official 121:7f86b4238bec 7602 #define LLWU_PE1_WUPE1_SHIFT (2U)
mbed_official 121:7f86b4238bec 7603 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
mbed_official 121:7f86b4238bec 7604 #define LLWU_PE1_WUPE2_MASK (0x30U)
mbed_official 121:7f86b4238bec 7605 #define LLWU_PE1_WUPE2_SHIFT (4U)
mbed_official 121:7f86b4238bec 7606 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
mbed_official 121:7f86b4238bec 7607 #define LLWU_PE1_WUPE3_MASK (0xC0U)
mbed_official 121:7f86b4238bec 7608 #define LLWU_PE1_WUPE3_SHIFT (6U)
mbed_official 121:7f86b4238bec 7609 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
mbed_official 121:7f86b4238bec 7610
mbed_official 121:7f86b4238bec 7611 /*! @name PE2 - LLWU Pin Enable 2 register */
mbed_official 121:7f86b4238bec 7612 #define LLWU_PE2_WUPE4_MASK (0x3U)
mbed_official 121:7f86b4238bec 7613 #define LLWU_PE2_WUPE4_SHIFT (0U)
mbed_official 121:7f86b4238bec 7614 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
mbed_official 121:7f86b4238bec 7615 #define LLWU_PE2_WUPE5_MASK (0xCU)
mbed_official 121:7f86b4238bec 7616 #define LLWU_PE2_WUPE5_SHIFT (2U)
mbed_official 121:7f86b4238bec 7617 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
mbed_official 121:7f86b4238bec 7618 #define LLWU_PE2_WUPE6_MASK (0x30U)
mbed_official 121:7f86b4238bec 7619 #define LLWU_PE2_WUPE6_SHIFT (4U)
mbed_official 121:7f86b4238bec 7620 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
mbed_official 121:7f86b4238bec 7621 #define LLWU_PE2_WUPE7_MASK (0xC0U)
mbed_official 121:7f86b4238bec 7622 #define LLWU_PE2_WUPE7_SHIFT (6U)
mbed_official 121:7f86b4238bec 7623 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
mbed_official 121:7f86b4238bec 7624
mbed_official 121:7f86b4238bec 7625 /*! @name PE3 - LLWU Pin Enable 3 register */
mbed_official 121:7f86b4238bec 7626 #define LLWU_PE3_WUPE8_MASK (0x3U)
mbed_official 121:7f86b4238bec 7627 #define LLWU_PE3_WUPE8_SHIFT (0U)
mbed_official 121:7f86b4238bec 7628 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
mbed_official 121:7f86b4238bec 7629 #define LLWU_PE3_WUPE9_MASK (0xCU)
mbed_official 121:7f86b4238bec 7630 #define LLWU_PE3_WUPE9_SHIFT (2U)
mbed_official 121:7f86b4238bec 7631 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
mbed_official 121:7f86b4238bec 7632 #define LLWU_PE3_WUPE10_MASK (0x30U)
mbed_official 121:7f86b4238bec 7633 #define LLWU_PE3_WUPE10_SHIFT (4U)
mbed_official 121:7f86b4238bec 7634 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
mbed_official 121:7f86b4238bec 7635 #define LLWU_PE3_WUPE11_MASK (0xC0U)
mbed_official 121:7f86b4238bec 7636 #define LLWU_PE3_WUPE11_SHIFT (6U)
mbed_official 121:7f86b4238bec 7637 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
mbed_official 121:7f86b4238bec 7638
mbed_official 121:7f86b4238bec 7639 /*! @name PE4 - LLWU Pin Enable 4 register */
mbed_official 121:7f86b4238bec 7640 #define LLWU_PE4_WUPE12_MASK (0x3U)
mbed_official 121:7f86b4238bec 7641 #define LLWU_PE4_WUPE12_SHIFT (0U)
mbed_official 121:7f86b4238bec 7642 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
mbed_official 121:7f86b4238bec 7643 #define LLWU_PE4_WUPE13_MASK (0xCU)
mbed_official 121:7f86b4238bec 7644 #define LLWU_PE4_WUPE13_SHIFT (2U)
mbed_official 121:7f86b4238bec 7645 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
mbed_official 121:7f86b4238bec 7646 #define LLWU_PE4_WUPE14_MASK (0x30U)
mbed_official 121:7f86b4238bec 7647 #define LLWU_PE4_WUPE14_SHIFT (4U)
mbed_official 121:7f86b4238bec 7648 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
mbed_official 121:7f86b4238bec 7649 #define LLWU_PE4_WUPE15_MASK (0xC0U)
mbed_official 121:7f86b4238bec 7650 #define LLWU_PE4_WUPE15_SHIFT (6U)
mbed_official 121:7f86b4238bec 7651 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
mbed_official 121:7f86b4238bec 7652
mbed_official 121:7f86b4238bec 7653 /*! @name ME - LLWU Module Enable register */
mbed_official 121:7f86b4238bec 7654 #define LLWU_ME_WUME0_MASK (0x1U)
mbed_official 121:7f86b4238bec 7655 #define LLWU_ME_WUME0_SHIFT (0U)
mbed_official 121:7f86b4238bec 7656 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
mbed_official 121:7f86b4238bec 7657 #define LLWU_ME_WUME1_MASK (0x2U)
mbed_official 121:7f86b4238bec 7658 #define LLWU_ME_WUME1_SHIFT (1U)
mbed_official 121:7f86b4238bec 7659 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
mbed_official 121:7f86b4238bec 7660 #define LLWU_ME_WUME2_MASK (0x4U)
mbed_official 121:7f86b4238bec 7661 #define LLWU_ME_WUME2_SHIFT (2U)
mbed_official 121:7f86b4238bec 7662 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
mbed_official 121:7f86b4238bec 7663 #define LLWU_ME_WUME3_MASK (0x8U)
mbed_official 121:7f86b4238bec 7664 #define LLWU_ME_WUME3_SHIFT (3U)
mbed_official 121:7f86b4238bec 7665 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
mbed_official 121:7f86b4238bec 7666 #define LLWU_ME_WUME4_MASK (0x10U)
mbed_official 121:7f86b4238bec 7667 #define LLWU_ME_WUME4_SHIFT (4U)
mbed_official 121:7f86b4238bec 7668 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
mbed_official 121:7f86b4238bec 7669 #define LLWU_ME_WUME5_MASK (0x20U)
mbed_official 121:7f86b4238bec 7670 #define LLWU_ME_WUME5_SHIFT (5U)
mbed_official 121:7f86b4238bec 7671 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
mbed_official 121:7f86b4238bec 7672 #define LLWU_ME_WUME6_MASK (0x40U)
mbed_official 121:7f86b4238bec 7673 #define LLWU_ME_WUME6_SHIFT (6U)
mbed_official 121:7f86b4238bec 7674 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
mbed_official 121:7f86b4238bec 7675 #define LLWU_ME_WUME7_MASK (0x80U)
mbed_official 121:7f86b4238bec 7676 #define LLWU_ME_WUME7_SHIFT (7U)
mbed_official 121:7f86b4238bec 7677 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
mbed_official 121:7f86b4238bec 7678
mbed_official 121:7f86b4238bec 7679 /*! @name F1 - LLWU Flag 1 register */
mbed_official 121:7f86b4238bec 7680 #define LLWU_F1_WUF0_MASK (0x1U)
mbed_official 121:7f86b4238bec 7681 #define LLWU_F1_WUF0_SHIFT (0U)
mbed_official 121:7f86b4238bec 7682 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
mbed_official 121:7f86b4238bec 7683 #define LLWU_F1_WUF1_MASK (0x2U)
mbed_official 121:7f86b4238bec 7684 #define LLWU_F1_WUF1_SHIFT (1U)
mbed_official 121:7f86b4238bec 7685 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
mbed_official 121:7f86b4238bec 7686 #define LLWU_F1_WUF2_MASK (0x4U)
mbed_official 121:7f86b4238bec 7687 #define LLWU_F1_WUF2_SHIFT (2U)
mbed_official 121:7f86b4238bec 7688 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
mbed_official 121:7f86b4238bec 7689 #define LLWU_F1_WUF3_MASK (0x8U)
mbed_official 121:7f86b4238bec 7690 #define LLWU_F1_WUF3_SHIFT (3U)
mbed_official 121:7f86b4238bec 7691 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
mbed_official 121:7f86b4238bec 7692 #define LLWU_F1_WUF4_MASK (0x10U)
mbed_official 121:7f86b4238bec 7693 #define LLWU_F1_WUF4_SHIFT (4U)
mbed_official 121:7f86b4238bec 7694 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
mbed_official 121:7f86b4238bec 7695 #define LLWU_F1_WUF5_MASK (0x20U)
mbed_official 121:7f86b4238bec 7696 #define LLWU_F1_WUF5_SHIFT (5U)
mbed_official 121:7f86b4238bec 7697 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
mbed_official 121:7f86b4238bec 7698 #define LLWU_F1_WUF6_MASK (0x40U)
mbed_official 121:7f86b4238bec 7699 #define LLWU_F1_WUF6_SHIFT (6U)
mbed_official 121:7f86b4238bec 7700 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
mbed_official 121:7f86b4238bec 7701 #define LLWU_F1_WUF7_MASK (0x80U)
mbed_official 121:7f86b4238bec 7702 #define LLWU_F1_WUF7_SHIFT (7U)
mbed_official 121:7f86b4238bec 7703 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
mbed_official 121:7f86b4238bec 7704
mbed_official 121:7f86b4238bec 7705 /*! @name F2 - LLWU Flag 2 register */
mbed_official 121:7f86b4238bec 7706 #define LLWU_F2_WUF8_MASK (0x1U)
mbed_official 121:7f86b4238bec 7707 #define LLWU_F2_WUF8_SHIFT (0U)
mbed_official 121:7f86b4238bec 7708 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
mbed_official 121:7f86b4238bec 7709 #define LLWU_F2_WUF9_MASK (0x2U)
mbed_official 121:7f86b4238bec 7710 #define LLWU_F2_WUF9_SHIFT (1U)
mbed_official 121:7f86b4238bec 7711 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
mbed_official 121:7f86b4238bec 7712 #define LLWU_F2_WUF10_MASK (0x4U)
mbed_official 121:7f86b4238bec 7713 #define LLWU_F2_WUF10_SHIFT (2U)
mbed_official 121:7f86b4238bec 7714 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
mbed_official 121:7f86b4238bec 7715 #define LLWU_F2_WUF11_MASK (0x8U)
mbed_official 121:7f86b4238bec 7716 #define LLWU_F2_WUF11_SHIFT (3U)
mbed_official 121:7f86b4238bec 7717 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
mbed_official 121:7f86b4238bec 7718 #define LLWU_F2_WUF12_MASK (0x10U)
mbed_official 121:7f86b4238bec 7719 #define LLWU_F2_WUF12_SHIFT (4U)
mbed_official 121:7f86b4238bec 7720 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
mbed_official 121:7f86b4238bec 7721 #define LLWU_F2_WUF13_MASK (0x20U)
mbed_official 121:7f86b4238bec 7722 #define LLWU_F2_WUF13_SHIFT (5U)
mbed_official 121:7f86b4238bec 7723 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
mbed_official 121:7f86b4238bec 7724 #define LLWU_F2_WUF14_MASK (0x40U)
mbed_official 121:7f86b4238bec 7725 #define LLWU_F2_WUF14_SHIFT (6U)
mbed_official 121:7f86b4238bec 7726 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
mbed_official 121:7f86b4238bec 7727 #define LLWU_F2_WUF15_MASK (0x80U)
mbed_official 121:7f86b4238bec 7728 #define LLWU_F2_WUF15_SHIFT (7U)
mbed_official 121:7f86b4238bec 7729 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
mbed_official 121:7f86b4238bec 7730
mbed_official 121:7f86b4238bec 7731 /*! @name F3 - LLWU Flag 3 register */
mbed_official 121:7f86b4238bec 7732 #define LLWU_F3_MWUF0_MASK (0x1U)
mbed_official 121:7f86b4238bec 7733 #define LLWU_F3_MWUF0_SHIFT (0U)
mbed_official 121:7f86b4238bec 7734 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
mbed_official 121:7f86b4238bec 7735 #define LLWU_F3_MWUF1_MASK (0x2U)
mbed_official 121:7f86b4238bec 7736 #define LLWU_F3_MWUF1_SHIFT (1U)
mbed_official 121:7f86b4238bec 7737 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
mbed_official 121:7f86b4238bec 7738 #define LLWU_F3_MWUF2_MASK (0x4U)
mbed_official 121:7f86b4238bec 7739 #define LLWU_F3_MWUF2_SHIFT (2U)
mbed_official 121:7f86b4238bec 7740 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
mbed_official 121:7f86b4238bec 7741 #define LLWU_F3_MWUF3_MASK (0x8U)
mbed_official 121:7f86b4238bec 7742 #define LLWU_F3_MWUF3_SHIFT (3U)
mbed_official 121:7f86b4238bec 7743 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
mbed_official 121:7f86b4238bec 7744 #define LLWU_F3_MWUF4_MASK (0x10U)
mbed_official 121:7f86b4238bec 7745 #define LLWU_F3_MWUF4_SHIFT (4U)
mbed_official 121:7f86b4238bec 7746 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
mbed_official 121:7f86b4238bec 7747 #define LLWU_F3_MWUF5_MASK (0x20U)
mbed_official 121:7f86b4238bec 7748 #define LLWU_F3_MWUF5_SHIFT (5U)
mbed_official 121:7f86b4238bec 7749 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
mbed_official 121:7f86b4238bec 7750 #define LLWU_F3_MWUF6_MASK (0x40U)
mbed_official 121:7f86b4238bec 7751 #define LLWU_F3_MWUF6_SHIFT (6U)
mbed_official 121:7f86b4238bec 7752 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
mbed_official 121:7f86b4238bec 7753 #define LLWU_F3_MWUF7_MASK (0x80U)
mbed_official 121:7f86b4238bec 7754 #define LLWU_F3_MWUF7_SHIFT (7U)
mbed_official 121:7f86b4238bec 7755 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
mbed_official 121:7f86b4238bec 7756
mbed_official 121:7f86b4238bec 7757 /*! @name FILT1 - LLWU Pin Filter 1 register */
mbed_official 121:7f86b4238bec 7758 #define LLWU_FILT1_FILTSEL_MASK (0xFU)
mbed_official 121:7f86b4238bec 7759 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 7760 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
mbed_official 121:7f86b4238bec 7761 #define LLWU_FILT1_FILTE_MASK (0x60U)
mbed_official 121:7f86b4238bec 7762 #define LLWU_FILT1_FILTE_SHIFT (5U)
mbed_official 121:7f86b4238bec 7763 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
mbed_official 121:7f86b4238bec 7764 #define LLWU_FILT1_FILTF_MASK (0x80U)
mbed_official 121:7f86b4238bec 7765 #define LLWU_FILT1_FILTF_SHIFT (7U)
mbed_official 121:7f86b4238bec 7766 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
mbed_official 121:7f86b4238bec 7767
mbed_official 121:7f86b4238bec 7768 /*! @name FILT2 - LLWU Pin Filter 2 register */
mbed_official 121:7f86b4238bec 7769 #define LLWU_FILT2_FILTSEL_MASK (0xFU)
mbed_official 121:7f86b4238bec 7770 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 7771 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
mbed_official 121:7f86b4238bec 7772 #define LLWU_FILT2_FILTE_MASK (0x60U)
mbed_official 121:7f86b4238bec 7773 #define LLWU_FILT2_FILTE_SHIFT (5U)
mbed_official 121:7f86b4238bec 7774 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
mbed_official 121:7f86b4238bec 7775 #define LLWU_FILT2_FILTF_MASK (0x80U)
mbed_official 121:7f86b4238bec 7776 #define LLWU_FILT2_FILTF_SHIFT (7U)
mbed_official 121:7f86b4238bec 7777 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
mbed_official 121:7f86b4238bec 7778
mbed_official 121:7f86b4238bec 7779 /*! @name RST - LLWU Reset Enable register */
mbed_official 121:7f86b4238bec 7780 #define LLWU_RST_RSTFILT_MASK (0x1U)
mbed_official 121:7f86b4238bec 7781 #define LLWU_RST_RSTFILT_SHIFT (0U)
mbed_official 121:7f86b4238bec 7782 #define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
mbed_official 121:7f86b4238bec 7783 #define LLWU_RST_LLRSTE_MASK (0x2U)
mbed_official 121:7f86b4238bec 7784 #define LLWU_RST_LLRSTE_SHIFT (1U)
mbed_official 121:7f86b4238bec 7785 #define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
mbed_official 121:7f86b4238bec 7786
mbed_official 121:7f86b4238bec 7787
mbed_official 121:7f86b4238bec 7788 /*!
mbed_official 121:7f86b4238bec 7789 * @}
mbed_official 121:7f86b4238bec 7790 */ /* end of group LLWU_Register_Masks */
mbed_official 121:7f86b4238bec 7791
mbed_official 121:7f86b4238bec 7792
mbed_official 121:7f86b4238bec 7793 /* LLWU - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 7794 /** Peripheral LLWU base address */
mbed_official 121:7f86b4238bec 7795 #define LLWU_BASE (0x4007C000u)
mbed_official 121:7f86b4238bec 7796 /** Peripheral LLWU base pointer */
mbed_official 121:7f86b4238bec 7797 #define LLWU ((LLWU_Type *)LLWU_BASE)
mbed_official 121:7f86b4238bec 7798 /** Array initializer of LLWU peripheral base addresses */
mbed_official 121:7f86b4238bec 7799 #define LLWU_BASE_ADDRS { LLWU_BASE }
mbed_official 121:7f86b4238bec 7800 /** Array initializer of LLWU peripheral base pointers */
mbed_official 121:7f86b4238bec 7801 #define LLWU_BASE_PTRS { LLWU }
mbed_official 121:7f86b4238bec 7802 /** Interrupt vectors for the LLWU peripheral type */
mbed_official 121:7f86b4238bec 7803 #define LLWU_IRQS { LLWU_IRQn }
mbed_official 121:7f86b4238bec 7804
mbed_official 121:7f86b4238bec 7805 /*!
mbed_official 121:7f86b4238bec 7806 * @}
mbed_official 121:7f86b4238bec 7807 */ /* end of group LLWU_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 7808
mbed_official 121:7f86b4238bec 7809
mbed_official 121:7f86b4238bec 7810 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 7811 -- LPTMR Peripheral Access Layer
mbed_official 121:7f86b4238bec 7812 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 7813
mbed_official 121:7f86b4238bec 7814 /*!
mbed_official 121:7f86b4238bec 7815 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mbed_official 121:7f86b4238bec 7816 * @{
mbed_official 121:7f86b4238bec 7817 */
mbed_official 121:7f86b4238bec 7818
mbed_official 121:7f86b4238bec 7819 /** LPTMR - Register Layout Typedef */
mbed_official 121:7f86b4238bec 7820 typedef struct {
mbed_official 121:7f86b4238bec 7821 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 7822 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 7823 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 7824 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mbed_official 121:7f86b4238bec 7825 } LPTMR_Type;
mbed_official 121:7f86b4238bec 7826
mbed_official 121:7f86b4238bec 7827 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 7828 -- LPTMR Register Masks
mbed_official 121:7f86b4238bec 7829 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 7830
mbed_official 121:7f86b4238bec 7831 /*!
mbed_official 121:7f86b4238bec 7832 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mbed_official 121:7f86b4238bec 7833 * @{
mbed_official 121:7f86b4238bec 7834 */
mbed_official 121:7f86b4238bec 7835
mbed_official 121:7f86b4238bec 7836 /*! @name CSR - Low Power Timer Control Status Register */
mbed_official 121:7f86b4238bec 7837 #define LPTMR_CSR_TEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 7838 #define LPTMR_CSR_TEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 7839 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
mbed_official 121:7f86b4238bec 7840 #define LPTMR_CSR_TMS_MASK (0x2U)
mbed_official 121:7f86b4238bec 7841 #define LPTMR_CSR_TMS_SHIFT (1U)
mbed_official 121:7f86b4238bec 7842 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
mbed_official 121:7f86b4238bec 7843 #define LPTMR_CSR_TFC_MASK (0x4U)
mbed_official 121:7f86b4238bec 7844 #define LPTMR_CSR_TFC_SHIFT (2U)
mbed_official 121:7f86b4238bec 7845 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
mbed_official 121:7f86b4238bec 7846 #define LPTMR_CSR_TPP_MASK (0x8U)
mbed_official 121:7f86b4238bec 7847 #define LPTMR_CSR_TPP_SHIFT (3U)
mbed_official 121:7f86b4238bec 7848 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
mbed_official 121:7f86b4238bec 7849 #define LPTMR_CSR_TPS_MASK (0x30U)
mbed_official 121:7f86b4238bec 7850 #define LPTMR_CSR_TPS_SHIFT (4U)
mbed_official 121:7f86b4238bec 7851 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
mbed_official 121:7f86b4238bec 7852 #define LPTMR_CSR_TIE_MASK (0x40U)
mbed_official 121:7f86b4238bec 7853 #define LPTMR_CSR_TIE_SHIFT (6U)
mbed_official 121:7f86b4238bec 7854 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
mbed_official 121:7f86b4238bec 7855 #define LPTMR_CSR_TCF_MASK (0x80U)
mbed_official 121:7f86b4238bec 7856 #define LPTMR_CSR_TCF_SHIFT (7U)
mbed_official 121:7f86b4238bec 7857 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
mbed_official 121:7f86b4238bec 7858
mbed_official 121:7f86b4238bec 7859 /*! @name PSR - Low Power Timer Prescale Register */
mbed_official 121:7f86b4238bec 7860 #define LPTMR_PSR_PCS_MASK (0x3U)
mbed_official 121:7f86b4238bec 7861 #define LPTMR_PSR_PCS_SHIFT (0U)
mbed_official 121:7f86b4238bec 7862 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
mbed_official 121:7f86b4238bec 7863 #define LPTMR_PSR_PBYP_MASK (0x4U)
mbed_official 121:7f86b4238bec 7864 #define LPTMR_PSR_PBYP_SHIFT (2U)
mbed_official 121:7f86b4238bec 7865 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
mbed_official 121:7f86b4238bec 7866 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
mbed_official 121:7f86b4238bec 7867 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
mbed_official 121:7f86b4238bec 7868 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
mbed_official 121:7f86b4238bec 7869
mbed_official 121:7f86b4238bec 7870 /*! @name CMR - Low Power Timer Compare Register */
mbed_official 121:7f86b4238bec 7871 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 7872 #define LPTMR_CMR_COMPARE_SHIFT (0U)
mbed_official 121:7f86b4238bec 7873 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
mbed_official 121:7f86b4238bec 7874
mbed_official 121:7f86b4238bec 7875 /*! @name CNR - Low Power Timer Counter Register */
mbed_official 121:7f86b4238bec 7876 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 7877 #define LPTMR_CNR_COUNTER_SHIFT (0U)
mbed_official 121:7f86b4238bec 7878 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
mbed_official 121:7f86b4238bec 7879
mbed_official 121:7f86b4238bec 7880
mbed_official 121:7f86b4238bec 7881 /*!
mbed_official 121:7f86b4238bec 7882 * @}
mbed_official 121:7f86b4238bec 7883 */ /* end of group LPTMR_Register_Masks */
mbed_official 121:7f86b4238bec 7884
mbed_official 121:7f86b4238bec 7885
mbed_official 121:7f86b4238bec 7886 /* LPTMR - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 7887 /** Peripheral LPTMR0 base address */
mbed_official 121:7f86b4238bec 7888 #define LPTMR0_BASE (0x40040000u)
mbed_official 121:7f86b4238bec 7889 /** Peripheral LPTMR0 base pointer */
mbed_official 121:7f86b4238bec 7890 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mbed_official 121:7f86b4238bec 7891 /** Array initializer of LPTMR peripheral base addresses */
mbed_official 121:7f86b4238bec 7892 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
mbed_official 121:7f86b4238bec 7893 /** Array initializer of LPTMR peripheral base pointers */
mbed_official 121:7f86b4238bec 7894 #define LPTMR_BASE_PTRS { LPTMR0 }
mbed_official 121:7f86b4238bec 7895 /** Interrupt vectors for the LPTMR peripheral type */
mbed_official 121:7f86b4238bec 7896 #define LPTMR_IRQS { LPTMR0_IRQn }
mbed_official 121:7f86b4238bec 7897
mbed_official 121:7f86b4238bec 7898 /*!
mbed_official 121:7f86b4238bec 7899 * @}
mbed_official 121:7f86b4238bec 7900 */ /* end of group LPTMR_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 7901
mbed_official 121:7f86b4238bec 7902
mbed_official 121:7f86b4238bec 7903 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 7904 -- MCG Peripheral Access Layer
mbed_official 121:7f86b4238bec 7905 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 7906
mbed_official 121:7f86b4238bec 7907 /*!
mbed_official 121:7f86b4238bec 7908 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mbed_official 121:7f86b4238bec 7909 * @{
mbed_official 121:7f86b4238bec 7910 */
mbed_official 121:7f86b4238bec 7911
mbed_official 121:7f86b4238bec 7912 /** MCG - Register Layout Typedef */
mbed_official 121:7f86b4238bec 7913 typedef struct {
mbed_official 121:7f86b4238bec 7914 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 7915 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
mbed_official 121:7f86b4238bec 7916 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
mbed_official 121:7f86b4238bec 7917 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
mbed_official 121:7f86b4238bec 7918 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 7919 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
mbed_official 121:7f86b4238bec 7920 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
mbed_official 121:7f86b4238bec 7921 uint8_t RESERVED_0[1];
mbed_official 121:7f86b4238bec 7922 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 7923 uint8_t RESERVED_1[1];
mbed_official 121:7f86b4238bec 7924 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
mbed_official 121:7f86b4238bec 7925 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
mbed_official 121:7f86b4238bec 7926 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
mbed_official 121:7f86b4238bec 7927 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
mbed_official 121:7f86b4238bec 7928 } MCG_Type;
mbed_official 121:7f86b4238bec 7929
mbed_official 121:7f86b4238bec 7930 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 7931 -- MCG Register Masks
mbed_official 121:7f86b4238bec 7932 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 7933
mbed_official 121:7f86b4238bec 7934 /*!
mbed_official 121:7f86b4238bec 7935 * @addtogroup MCG_Register_Masks MCG Register Masks
mbed_official 121:7f86b4238bec 7936 * @{
mbed_official 121:7f86b4238bec 7937 */
mbed_official 121:7f86b4238bec 7938
mbed_official 121:7f86b4238bec 7939 /*! @name C1 - MCG Control 1 Register */
mbed_official 121:7f86b4238bec 7940 #define MCG_C1_IREFSTEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 7941 #define MCG_C1_IREFSTEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 7942 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
mbed_official 121:7f86b4238bec 7943 #define MCG_C1_IRCLKEN_MASK (0x2U)
mbed_official 121:7f86b4238bec 7944 #define MCG_C1_IRCLKEN_SHIFT (1U)
mbed_official 121:7f86b4238bec 7945 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
mbed_official 121:7f86b4238bec 7946 #define MCG_C1_IREFS_MASK (0x4U)
mbed_official 121:7f86b4238bec 7947 #define MCG_C1_IREFS_SHIFT (2U)
mbed_official 121:7f86b4238bec 7948 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
mbed_official 121:7f86b4238bec 7949 #define MCG_C1_FRDIV_MASK (0x38U)
mbed_official 121:7f86b4238bec 7950 #define MCG_C1_FRDIV_SHIFT (3U)
mbed_official 121:7f86b4238bec 7951 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
mbed_official 121:7f86b4238bec 7952 #define MCG_C1_CLKS_MASK (0xC0U)
mbed_official 121:7f86b4238bec 7953 #define MCG_C1_CLKS_SHIFT (6U)
mbed_official 121:7f86b4238bec 7954 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
mbed_official 121:7f86b4238bec 7955
mbed_official 121:7f86b4238bec 7956 /*! @name C2 - MCG Control 2 Register */
mbed_official 121:7f86b4238bec 7957 #define MCG_C2_IRCS_MASK (0x1U)
mbed_official 121:7f86b4238bec 7958 #define MCG_C2_IRCS_SHIFT (0U)
mbed_official 121:7f86b4238bec 7959 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
mbed_official 121:7f86b4238bec 7960 #define MCG_C2_LP_MASK (0x2U)
mbed_official 121:7f86b4238bec 7961 #define MCG_C2_LP_SHIFT (1U)
mbed_official 121:7f86b4238bec 7962 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
mbed_official 121:7f86b4238bec 7963 #define MCG_C2_EREFS_MASK (0x4U)
mbed_official 121:7f86b4238bec 7964 #define MCG_C2_EREFS_SHIFT (2U)
mbed_official 121:7f86b4238bec 7965 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
mbed_official 121:7f86b4238bec 7966 #define MCG_C2_HGO_MASK (0x8U)
mbed_official 121:7f86b4238bec 7967 #define MCG_C2_HGO_SHIFT (3U)
mbed_official 121:7f86b4238bec 7968 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
mbed_official 121:7f86b4238bec 7969 #define MCG_C2_RANGE_MASK (0x30U)
mbed_official 121:7f86b4238bec 7970 #define MCG_C2_RANGE_SHIFT (4U)
mbed_official 121:7f86b4238bec 7971 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
mbed_official 121:7f86b4238bec 7972 #define MCG_C2_FCFTRIM_MASK (0x40U)
mbed_official 121:7f86b4238bec 7973 #define MCG_C2_FCFTRIM_SHIFT (6U)
mbed_official 121:7f86b4238bec 7974 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
mbed_official 121:7f86b4238bec 7975 #define MCG_C2_LOCRE0_MASK (0x80U)
mbed_official 121:7f86b4238bec 7976 #define MCG_C2_LOCRE0_SHIFT (7U)
mbed_official 121:7f86b4238bec 7977 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
mbed_official 121:7f86b4238bec 7978
mbed_official 121:7f86b4238bec 7979 /*! @name C3 - MCG Control 3 Register */
mbed_official 121:7f86b4238bec 7980 #define MCG_C3_SCTRIM_MASK (0xFFU)
mbed_official 121:7f86b4238bec 7981 #define MCG_C3_SCTRIM_SHIFT (0U)
mbed_official 121:7f86b4238bec 7982 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
mbed_official 121:7f86b4238bec 7983
mbed_official 121:7f86b4238bec 7984 /*! @name C4 - MCG Control 4 Register */
mbed_official 121:7f86b4238bec 7985 #define MCG_C4_SCFTRIM_MASK (0x1U)
mbed_official 121:7f86b4238bec 7986 #define MCG_C4_SCFTRIM_SHIFT (0U)
mbed_official 121:7f86b4238bec 7987 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
mbed_official 121:7f86b4238bec 7988 #define MCG_C4_FCTRIM_MASK (0x1EU)
mbed_official 121:7f86b4238bec 7989 #define MCG_C4_FCTRIM_SHIFT (1U)
mbed_official 121:7f86b4238bec 7990 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
mbed_official 121:7f86b4238bec 7991 #define MCG_C4_DRST_DRS_MASK (0x60U)
mbed_official 121:7f86b4238bec 7992 #define MCG_C4_DRST_DRS_SHIFT (5U)
mbed_official 121:7f86b4238bec 7993 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
mbed_official 121:7f86b4238bec 7994 #define MCG_C4_DMX32_MASK (0x80U)
mbed_official 121:7f86b4238bec 7995 #define MCG_C4_DMX32_SHIFT (7U)
mbed_official 121:7f86b4238bec 7996 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
mbed_official 121:7f86b4238bec 7997
mbed_official 121:7f86b4238bec 7998 /*! @name C5 - MCG Control 5 Register */
mbed_official 121:7f86b4238bec 7999 #define MCG_C5_PRDIV0_MASK (0x1FU)
mbed_official 121:7f86b4238bec 8000 #define MCG_C5_PRDIV0_SHIFT (0U)
mbed_official 121:7f86b4238bec 8001 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
mbed_official 121:7f86b4238bec 8002 #define MCG_C5_PLLSTEN0_MASK (0x20U)
mbed_official 121:7f86b4238bec 8003 #define MCG_C5_PLLSTEN0_SHIFT (5U)
mbed_official 121:7f86b4238bec 8004 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
mbed_official 121:7f86b4238bec 8005 #define MCG_C5_PLLCLKEN0_MASK (0x40U)
mbed_official 121:7f86b4238bec 8006 #define MCG_C5_PLLCLKEN0_SHIFT (6U)
mbed_official 121:7f86b4238bec 8007 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
mbed_official 121:7f86b4238bec 8008
mbed_official 121:7f86b4238bec 8009 /*! @name C6 - MCG Control 6 Register */
mbed_official 121:7f86b4238bec 8010 #define MCG_C6_VDIV0_MASK (0x1FU)
mbed_official 121:7f86b4238bec 8011 #define MCG_C6_VDIV0_SHIFT (0U)
mbed_official 121:7f86b4238bec 8012 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
mbed_official 121:7f86b4238bec 8013 #define MCG_C6_CME0_MASK (0x20U)
mbed_official 121:7f86b4238bec 8014 #define MCG_C6_CME0_SHIFT (5U)
mbed_official 121:7f86b4238bec 8015 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
mbed_official 121:7f86b4238bec 8016 #define MCG_C6_PLLS_MASK (0x40U)
mbed_official 121:7f86b4238bec 8017 #define MCG_C6_PLLS_SHIFT (6U)
mbed_official 121:7f86b4238bec 8018 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
mbed_official 121:7f86b4238bec 8019 #define MCG_C6_LOLIE0_MASK (0x80U)
mbed_official 121:7f86b4238bec 8020 #define MCG_C6_LOLIE0_SHIFT (7U)
mbed_official 121:7f86b4238bec 8021 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
mbed_official 121:7f86b4238bec 8022
mbed_official 121:7f86b4238bec 8023 /*! @name S - MCG Status Register */
mbed_official 121:7f86b4238bec 8024 #define MCG_S_IRCST_MASK (0x1U)
mbed_official 121:7f86b4238bec 8025 #define MCG_S_IRCST_SHIFT (0U)
mbed_official 121:7f86b4238bec 8026 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
mbed_official 121:7f86b4238bec 8027 #define MCG_S_OSCINIT0_MASK (0x2U)
mbed_official 121:7f86b4238bec 8028 #define MCG_S_OSCINIT0_SHIFT (1U)
mbed_official 121:7f86b4238bec 8029 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
mbed_official 121:7f86b4238bec 8030 #define MCG_S_CLKST_MASK (0xCU)
mbed_official 121:7f86b4238bec 8031 #define MCG_S_CLKST_SHIFT (2U)
mbed_official 121:7f86b4238bec 8032 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
mbed_official 121:7f86b4238bec 8033 #define MCG_S_IREFST_MASK (0x10U)
mbed_official 121:7f86b4238bec 8034 #define MCG_S_IREFST_SHIFT (4U)
mbed_official 121:7f86b4238bec 8035 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
mbed_official 121:7f86b4238bec 8036 #define MCG_S_PLLST_MASK (0x20U)
mbed_official 121:7f86b4238bec 8037 #define MCG_S_PLLST_SHIFT (5U)
mbed_official 121:7f86b4238bec 8038 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
mbed_official 121:7f86b4238bec 8039 #define MCG_S_LOCK0_MASK (0x40U)
mbed_official 121:7f86b4238bec 8040 #define MCG_S_LOCK0_SHIFT (6U)
mbed_official 121:7f86b4238bec 8041 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
mbed_official 121:7f86b4238bec 8042 #define MCG_S_LOLS0_MASK (0x80U)
mbed_official 121:7f86b4238bec 8043 #define MCG_S_LOLS0_SHIFT (7U)
mbed_official 121:7f86b4238bec 8044 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
mbed_official 121:7f86b4238bec 8045
mbed_official 121:7f86b4238bec 8046 /*! @name SC - MCG Status and Control Register */
mbed_official 121:7f86b4238bec 8047 #define MCG_SC_LOCS0_MASK (0x1U)
mbed_official 121:7f86b4238bec 8048 #define MCG_SC_LOCS0_SHIFT (0U)
mbed_official 121:7f86b4238bec 8049 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
mbed_official 121:7f86b4238bec 8050 #define MCG_SC_FCRDIV_MASK (0xEU)
mbed_official 121:7f86b4238bec 8051 #define MCG_SC_FCRDIV_SHIFT (1U)
mbed_official 121:7f86b4238bec 8052 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
mbed_official 121:7f86b4238bec 8053 #define MCG_SC_FLTPRSRV_MASK (0x10U)
mbed_official 121:7f86b4238bec 8054 #define MCG_SC_FLTPRSRV_SHIFT (4U)
mbed_official 121:7f86b4238bec 8055 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
mbed_official 121:7f86b4238bec 8056 #define MCG_SC_ATMF_MASK (0x20U)
mbed_official 121:7f86b4238bec 8057 #define MCG_SC_ATMF_SHIFT (5U)
mbed_official 121:7f86b4238bec 8058 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
mbed_official 121:7f86b4238bec 8059 #define MCG_SC_ATMS_MASK (0x40U)
mbed_official 121:7f86b4238bec 8060 #define MCG_SC_ATMS_SHIFT (6U)
mbed_official 121:7f86b4238bec 8061 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
mbed_official 121:7f86b4238bec 8062 #define MCG_SC_ATME_MASK (0x80U)
mbed_official 121:7f86b4238bec 8063 #define MCG_SC_ATME_SHIFT (7U)
mbed_official 121:7f86b4238bec 8064 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
mbed_official 121:7f86b4238bec 8065
mbed_official 121:7f86b4238bec 8066 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
mbed_official 121:7f86b4238bec 8067 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8068 #define MCG_ATCVH_ATCVH_SHIFT (0U)
mbed_official 121:7f86b4238bec 8069 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
mbed_official 121:7f86b4238bec 8070
mbed_official 121:7f86b4238bec 8071 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
mbed_official 121:7f86b4238bec 8072 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8073 #define MCG_ATCVL_ATCVL_SHIFT (0U)
mbed_official 121:7f86b4238bec 8074 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
mbed_official 121:7f86b4238bec 8075
mbed_official 121:7f86b4238bec 8076 /*! @name C7 - MCG Control 7 Register */
mbed_official 121:7f86b4238bec 8077 #define MCG_C7_OSCSEL_MASK (0x3U)
mbed_official 121:7f86b4238bec 8078 #define MCG_C7_OSCSEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 8079 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
mbed_official 121:7f86b4238bec 8080
mbed_official 121:7f86b4238bec 8081 /*! @name C8 - MCG Control 8 Register */
mbed_official 121:7f86b4238bec 8082 #define MCG_C8_LOCS1_MASK (0x1U)
mbed_official 121:7f86b4238bec 8083 #define MCG_C8_LOCS1_SHIFT (0U)
mbed_official 121:7f86b4238bec 8084 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
mbed_official 121:7f86b4238bec 8085 #define MCG_C8_CME1_MASK (0x20U)
mbed_official 121:7f86b4238bec 8086 #define MCG_C8_CME1_SHIFT (5U)
mbed_official 121:7f86b4238bec 8087 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
mbed_official 121:7f86b4238bec 8088 #define MCG_C8_LOLRE_MASK (0x40U)
mbed_official 121:7f86b4238bec 8089 #define MCG_C8_LOLRE_SHIFT (6U)
mbed_official 121:7f86b4238bec 8090 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
mbed_official 121:7f86b4238bec 8091 #define MCG_C8_LOCRE1_MASK (0x80U)
mbed_official 121:7f86b4238bec 8092 #define MCG_C8_LOCRE1_SHIFT (7U)
mbed_official 121:7f86b4238bec 8093 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
mbed_official 121:7f86b4238bec 8094
mbed_official 121:7f86b4238bec 8095
mbed_official 121:7f86b4238bec 8096 /*!
mbed_official 121:7f86b4238bec 8097 * @}
mbed_official 121:7f86b4238bec 8098 */ /* end of group MCG_Register_Masks */
mbed_official 121:7f86b4238bec 8099
mbed_official 121:7f86b4238bec 8100
mbed_official 121:7f86b4238bec 8101 /* MCG - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 8102 /** Peripheral MCG base address */
mbed_official 121:7f86b4238bec 8103 #define MCG_BASE (0x40064000u)
mbed_official 121:7f86b4238bec 8104 /** Peripheral MCG base pointer */
mbed_official 121:7f86b4238bec 8105 #define MCG ((MCG_Type *)MCG_BASE)
mbed_official 121:7f86b4238bec 8106 /** Array initializer of MCG peripheral base addresses */
mbed_official 121:7f86b4238bec 8107 #define MCG_BASE_ADDRS { MCG_BASE }
mbed_official 121:7f86b4238bec 8108 /** Array initializer of MCG peripheral base pointers */
mbed_official 121:7f86b4238bec 8109 #define MCG_BASE_PTRS { MCG }
mbed_official 121:7f86b4238bec 8110
mbed_official 121:7f86b4238bec 8111 /*!
mbed_official 121:7f86b4238bec 8112 * @}
mbed_official 121:7f86b4238bec 8113 */ /* end of group MCG_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 8114
mbed_official 121:7f86b4238bec 8115
mbed_official 121:7f86b4238bec 8116 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8117 -- MCM Peripheral Access Layer
mbed_official 121:7f86b4238bec 8118 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8119
mbed_official 121:7f86b4238bec 8120 /*!
mbed_official 121:7f86b4238bec 8121 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
mbed_official 121:7f86b4238bec 8122 * @{
mbed_official 121:7f86b4238bec 8123 */
mbed_official 121:7f86b4238bec 8124
mbed_official 121:7f86b4238bec 8125 /** MCM - Register Layout Typedef */
mbed_official 121:7f86b4238bec 8126 typedef struct {
mbed_official 121:7f86b4238bec 8127 uint8_t RESERVED_0[8];
mbed_official 121:7f86b4238bec 8128 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
mbed_official 121:7f86b4238bec 8129 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
mbed_official 121:7f86b4238bec 8130 __IO uint32_t CR; /**< Control Register, offset: 0xC */
mbed_official 121:7f86b4238bec 8131 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
mbed_official 121:7f86b4238bec 8132 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
mbed_official 121:7f86b4238bec 8133 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
mbed_official 121:7f86b4238bec 8134 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
mbed_official 121:7f86b4238bec 8135 uint8_t RESERVED_1[16];
mbed_official 121:7f86b4238bec 8136 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
mbed_official 121:7f86b4238bec 8137 } MCM_Type;
mbed_official 121:7f86b4238bec 8138
mbed_official 121:7f86b4238bec 8139 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8140 -- MCM Register Masks
mbed_official 121:7f86b4238bec 8141 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8142
mbed_official 121:7f86b4238bec 8143 /*!
mbed_official 121:7f86b4238bec 8144 * @addtogroup MCM_Register_Masks MCM Register Masks
mbed_official 121:7f86b4238bec 8145 * @{
mbed_official 121:7f86b4238bec 8146 */
mbed_official 121:7f86b4238bec 8147
mbed_official 121:7f86b4238bec 8148 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
mbed_official 121:7f86b4238bec 8149 #define MCM_PLASC_ASC_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8150 #define MCM_PLASC_ASC_SHIFT (0U)
mbed_official 121:7f86b4238bec 8151 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
mbed_official 121:7f86b4238bec 8152
mbed_official 121:7f86b4238bec 8153 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
mbed_official 121:7f86b4238bec 8154 #define MCM_PLAMC_AMC_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8155 #define MCM_PLAMC_AMC_SHIFT (0U)
mbed_official 121:7f86b4238bec 8156 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
mbed_official 121:7f86b4238bec 8157
mbed_official 121:7f86b4238bec 8158 /*! @name CR - Control Register */
mbed_official 121:7f86b4238bec 8159 #define MCM_CR_SRAMUAP_MASK (0x3000000U)
mbed_official 121:7f86b4238bec 8160 #define MCM_CR_SRAMUAP_SHIFT (24U)
mbed_official 121:7f86b4238bec 8161 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
mbed_official 121:7f86b4238bec 8162 #define MCM_CR_SRAMUWP_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 8163 #define MCM_CR_SRAMUWP_SHIFT (26U)
mbed_official 121:7f86b4238bec 8164 #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
mbed_official 121:7f86b4238bec 8165 #define MCM_CR_SRAMLAP_MASK (0x30000000U)
mbed_official 121:7f86b4238bec 8166 #define MCM_CR_SRAMLAP_SHIFT (28U)
mbed_official 121:7f86b4238bec 8167 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
mbed_official 121:7f86b4238bec 8168 #define MCM_CR_SRAMLWP_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 8169 #define MCM_CR_SRAMLWP_SHIFT (30U)
mbed_official 121:7f86b4238bec 8170 #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
mbed_official 121:7f86b4238bec 8171
mbed_official 121:7f86b4238bec 8172 /*! @name ISCR - Interrupt Status Register */
mbed_official 121:7f86b4238bec 8173 #define MCM_ISCR_IRQ_MASK (0x2U)
mbed_official 121:7f86b4238bec 8174 #define MCM_ISCR_IRQ_SHIFT (1U)
mbed_official 121:7f86b4238bec 8175 #define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
mbed_official 121:7f86b4238bec 8176 #define MCM_ISCR_NMI_MASK (0x4U)
mbed_official 121:7f86b4238bec 8177 #define MCM_ISCR_NMI_SHIFT (2U)
mbed_official 121:7f86b4238bec 8178 #define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
mbed_official 121:7f86b4238bec 8179 #define MCM_ISCR_DHREQ_MASK (0x8U)
mbed_official 121:7f86b4238bec 8180 #define MCM_ISCR_DHREQ_SHIFT (3U)
mbed_official 121:7f86b4238bec 8181 #define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
mbed_official 121:7f86b4238bec 8182 #define MCM_ISCR_FIOC_MASK (0x100U)
mbed_official 121:7f86b4238bec 8183 #define MCM_ISCR_FIOC_SHIFT (8U)
mbed_official 121:7f86b4238bec 8184 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
mbed_official 121:7f86b4238bec 8185 #define MCM_ISCR_FDZC_MASK (0x200U)
mbed_official 121:7f86b4238bec 8186 #define MCM_ISCR_FDZC_SHIFT (9U)
mbed_official 121:7f86b4238bec 8187 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
mbed_official 121:7f86b4238bec 8188 #define MCM_ISCR_FOFC_MASK (0x400U)
mbed_official 121:7f86b4238bec 8189 #define MCM_ISCR_FOFC_SHIFT (10U)
mbed_official 121:7f86b4238bec 8190 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
mbed_official 121:7f86b4238bec 8191 #define MCM_ISCR_FUFC_MASK (0x800U)
mbed_official 121:7f86b4238bec 8192 #define MCM_ISCR_FUFC_SHIFT (11U)
mbed_official 121:7f86b4238bec 8193 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
mbed_official 121:7f86b4238bec 8194 #define MCM_ISCR_FIXC_MASK (0x1000U)
mbed_official 121:7f86b4238bec 8195 #define MCM_ISCR_FIXC_SHIFT (12U)
mbed_official 121:7f86b4238bec 8196 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
mbed_official 121:7f86b4238bec 8197 #define MCM_ISCR_FIDC_MASK (0x8000U)
mbed_official 121:7f86b4238bec 8198 #define MCM_ISCR_FIDC_SHIFT (15U)
mbed_official 121:7f86b4238bec 8199 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
mbed_official 121:7f86b4238bec 8200 #define MCM_ISCR_FIOCE_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 8201 #define MCM_ISCR_FIOCE_SHIFT (24U)
mbed_official 121:7f86b4238bec 8202 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
mbed_official 121:7f86b4238bec 8203 #define MCM_ISCR_FDZCE_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 8204 #define MCM_ISCR_FDZCE_SHIFT (25U)
mbed_official 121:7f86b4238bec 8205 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
mbed_official 121:7f86b4238bec 8206 #define MCM_ISCR_FOFCE_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 8207 #define MCM_ISCR_FOFCE_SHIFT (26U)
mbed_official 121:7f86b4238bec 8208 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
mbed_official 121:7f86b4238bec 8209 #define MCM_ISCR_FUFCE_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 8210 #define MCM_ISCR_FUFCE_SHIFT (27U)
mbed_official 121:7f86b4238bec 8211 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
mbed_official 121:7f86b4238bec 8212 #define MCM_ISCR_FIXCE_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 8213 #define MCM_ISCR_FIXCE_SHIFT (28U)
mbed_official 121:7f86b4238bec 8214 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
mbed_official 121:7f86b4238bec 8215 #define MCM_ISCR_FIDCE_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 8216 #define MCM_ISCR_FIDCE_SHIFT (31U)
mbed_official 121:7f86b4238bec 8217 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
mbed_official 121:7f86b4238bec 8218
mbed_official 121:7f86b4238bec 8219 /*! @name ETBCC - ETB Counter Control register */
mbed_official 121:7f86b4238bec 8220 #define MCM_ETBCC_CNTEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 8221 #define MCM_ETBCC_CNTEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 8222 #define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
mbed_official 121:7f86b4238bec 8223 #define MCM_ETBCC_RSPT_MASK (0x6U)
mbed_official 121:7f86b4238bec 8224 #define MCM_ETBCC_RSPT_SHIFT (1U)
mbed_official 121:7f86b4238bec 8225 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
mbed_official 121:7f86b4238bec 8226 #define MCM_ETBCC_RLRQ_MASK (0x8U)
mbed_official 121:7f86b4238bec 8227 #define MCM_ETBCC_RLRQ_SHIFT (3U)
mbed_official 121:7f86b4238bec 8228 #define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
mbed_official 121:7f86b4238bec 8229 #define MCM_ETBCC_ETDIS_MASK (0x10U)
mbed_official 121:7f86b4238bec 8230 #define MCM_ETBCC_ETDIS_SHIFT (4U)
mbed_official 121:7f86b4238bec 8231 #define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
mbed_official 121:7f86b4238bec 8232 #define MCM_ETBCC_ITDIS_MASK (0x20U)
mbed_official 121:7f86b4238bec 8233 #define MCM_ETBCC_ITDIS_SHIFT (5U)
mbed_official 121:7f86b4238bec 8234 #define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
mbed_official 121:7f86b4238bec 8235
mbed_official 121:7f86b4238bec 8236 /*! @name ETBRL - ETB Reload register */
mbed_official 121:7f86b4238bec 8237 #define MCM_ETBRL_RELOAD_MASK (0x7FFU)
mbed_official 121:7f86b4238bec 8238 #define MCM_ETBRL_RELOAD_SHIFT (0U)
mbed_official 121:7f86b4238bec 8239 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
mbed_official 121:7f86b4238bec 8240
mbed_official 121:7f86b4238bec 8241 /*! @name ETBCNT - ETB Counter Value register */
mbed_official 121:7f86b4238bec 8242 #define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
mbed_official 121:7f86b4238bec 8243 #define MCM_ETBCNT_COUNTER_SHIFT (0U)
mbed_official 121:7f86b4238bec 8244 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
mbed_official 121:7f86b4238bec 8245
mbed_official 121:7f86b4238bec 8246 /*! @name PID - Process ID register */
mbed_official 121:7f86b4238bec 8247 #define MCM_PID_PID_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8248 #define MCM_PID_PID_SHIFT (0U)
mbed_official 121:7f86b4238bec 8249 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
mbed_official 121:7f86b4238bec 8250
mbed_official 121:7f86b4238bec 8251
mbed_official 121:7f86b4238bec 8252 /*!
mbed_official 121:7f86b4238bec 8253 * @}
mbed_official 121:7f86b4238bec 8254 */ /* end of group MCM_Register_Masks */
mbed_official 121:7f86b4238bec 8255
mbed_official 121:7f86b4238bec 8256
mbed_official 121:7f86b4238bec 8257 /* MCM - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 8258 /** Peripheral MCM base address */
mbed_official 121:7f86b4238bec 8259 #define MCM_BASE (0xE0080000u)
mbed_official 121:7f86b4238bec 8260 /** Peripheral MCM base pointer */
mbed_official 121:7f86b4238bec 8261 #define MCM ((MCM_Type *)MCM_BASE)
mbed_official 121:7f86b4238bec 8262 /** Array initializer of MCM peripheral base addresses */
mbed_official 121:7f86b4238bec 8263 #define MCM_BASE_ADDRS { MCM_BASE }
mbed_official 121:7f86b4238bec 8264 /** Array initializer of MCM peripheral base pointers */
mbed_official 121:7f86b4238bec 8265 #define MCM_BASE_PTRS { MCM }
mbed_official 121:7f86b4238bec 8266 /** Interrupt vectors for the MCM peripheral type */
mbed_official 121:7f86b4238bec 8267 #define MCM_IRQS { MCM_IRQn }
mbed_official 121:7f86b4238bec 8268
mbed_official 121:7f86b4238bec 8269 /*!
mbed_official 121:7f86b4238bec 8270 * @}
mbed_official 121:7f86b4238bec 8271 */ /* end of group MCM_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 8272
mbed_official 121:7f86b4238bec 8273
mbed_official 121:7f86b4238bec 8274 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8275 -- MPU Peripheral Access Layer
mbed_official 121:7f86b4238bec 8276 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8277
mbed_official 121:7f86b4238bec 8278 /*!
mbed_official 121:7f86b4238bec 8279 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
mbed_official 121:7f86b4238bec 8280 * @{
mbed_official 121:7f86b4238bec 8281 */
mbed_official 121:7f86b4238bec 8282
mbed_official 121:7f86b4238bec 8283 /** MPU - Register Layout Typedef */
mbed_official 121:7f86b4238bec 8284 typedef struct {
mbed_official 121:7f86b4238bec 8285 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 8286 uint8_t RESERVED_0[12];
mbed_official 121:7f86b4238bec 8287 struct { /* offset: 0x10, array step: 0x8 */
mbed_official 121:7f86b4238bec 8288 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
mbed_official 121:7f86b4238bec 8289 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
mbed_official 121:7f86b4238bec 8290 } SP[5];
mbed_official 121:7f86b4238bec 8291 uint8_t RESERVED_1[968];
mbed_official 121:7f86b4238bec 8292 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
mbed_official 121:7f86b4238bec 8293 uint8_t RESERVED_2[832];
mbed_official 121:7f86b4238bec 8294 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
mbed_official 121:7f86b4238bec 8295 } MPU_Type;
mbed_official 121:7f86b4238bec 8296
mbed_official 121:7f86b4238bec 8297 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8298 -- MPU Register Masks
mbed_official 121:7f86b4238bec 8299 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8300
mbed_official 121:7f86b4238bec 8301 /*!
mbed_official 121:7f86b4238bec 8302 * @addtogroup MPU_Register_Masks MPU Register Masks
mbed_official 121:7f86b4238bec 8303 * @{
mbed_official 121:7f86b4238bec 8304 */
mbed_official 121:7f86b4238bec 8305
mbed_official 121:7f86b4238bec 8306 /*! @name CESR - Control/Error Status Register */
mbed_official 121:7f86b4238bec 8307 #define MPU_CESR_VLD_MASK (0x1U)
mbed_official 121:7f86b4238bec 8308 #define MPU_CESR_VLD_SHIFT (0U)
mbed_official 121:7f86b4238bec 8309 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK)
mbed_official 121:7f86b4238bec 8310 #define MPU_CESR_NRGD_MASK (0xF00U)
mbed_official 121:7f86b4238bec 8311 #define MPU_CESR_NRGD_SHIFT (8U)
mbed_official 121:7f86b4238bec 8312 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
mbed_official 121:7f86b4238bec 8313 #define MPU_CESR_NSP_MASK (0xF000U)
mbed_official 121:7f86b4238bec 8314 #define MPU_CESR_NSP_SHIFT (12U)
mbed_official 121:7f86b4238bec 8315 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
mbed_official 121:7f86b4238bec 8316 #define MPU_CESR_HRL_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 8317 #define MPU_CESR_HRL_SHIFT (16U)
mbed_official 121:7f86b4238bec 8318 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
mbed_official 121:7f86b4238bec 8319 #define MPU_CESR_SPERR_MASK (0xF8000000U)
mbed_official 121:7f86b4238bec 8320 #define MPU_CESR_SPERR_SHIFT (27U)
mbed_official 121:7f86b4238bec 8321 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
mbed_official 121:7f86b4238bec 8322
mbed_official 121:7f86b4238bec 8323 /*! @name EAR - Error Address Register, slave port n */
mbed_official 121:7f86b4238bec 8324 #define MPU_EAR_EADDR_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 8325 #define MPU_EAR_EADDR_SHIFT (0U)
mbed_official 121:7f86b4238bec 8326 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK)
mbed_official 121:7f86b4238bec 8327
mbed_official 121:7f86b4238bec 8328 /* The count of MPU_EAR */
mbed_official 121:7f86b4238bec 8329 #define MPU_EAR_COUNT (5U)
mbed_official 121:7f86b4238bec 8330
mbed_official 121:7f86b4238bec 8331 /*! @name EDR - Error Detail Register, slave port n */
mbed_official 121:7f86b4238bec 8332 #define MPU_EDR_ERW_MASK (0x1U)
mbed_official 121:7f86b4238bec 8333 #define MPU_EDR_ERW_SHIFT (0U)
mbed_official 121:7f86b4238bec 8334 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK)
mbed_official 121:7f86b4238bec 8335 #define MPU_EDR_EATTR_MASK (0xEU)
mbed_official 121:7f86b4238bec 8336 #define MPU_EDR_EATTR_SHIFT (1U)
mbed_official 121:7f86b4238bec 8337 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
mbed_official 121:7f86b4238bec 8338 #define MPU_EDR_EMN_MASK (0xF0U)
mbed_official 121:7f86b4238bec 8339 #define MPU_EDR_EMN_SHIFT (4U)
mbed_official 121:7f86b4238bec 8340 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
mbed_official 121:7f86b4238bec 8341 #define MPU_EDR_EPID_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 8342 #define MPU_EDR_EPID_SHIFT (8U)
mbed_official 121:7f86b4238bec 8343 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
mbed_official 121:7f86b4238bec 8344 #define MPU_EDR_EACD_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 8345 #define MPU_EDR_EACD_SHIFT (16U)
mbed_official 121:7f86b4238bec 8346 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
mbed_official 121:7f86b4238bec 8347
mbed_official 121:7f86b4238bec 8348 /* The count of MPU_EDR */
mbed_official 121:7f86b4238bec 8349 #define MPU_EDR_COUNT (5U)
mbed_official 121:7f86b4238bec 8350
mbed_official 121:7f86b4238bec 8351 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
mbed_official 121:7f86b4238bec 8352 #define MPU_WORD_VLD_MASK (0x1U)
mbed_official 121:7f86b4238bec 8353 #define MPU_WORD_VLD_SHIFT (0U)
mbed_official 121:7f86b4238bec 8354 #define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK)
mbed_official 121:7f86b4238bec 8355 #define MPU_WORD_M0UM_MASK (0x7U)
mbed_official 121:7f86b4238bec 8356 #define MPU_WORD_M0UM_SHIFT (0U)
mbed_official 121:7f86b4238bec 8357 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
mbed_official 121:7f86b4238bec 8358 #define MPU_WORD_M0SM_MASK (0x18U)
mbed_official 121:7f86b4238bec 8359 #define MPU_WORD_M0SM_SHIFT (3U)
mbed_official 121:7f86b4238bec 8360 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
mbed_official 121:7f86b4238bec 8361 #define MPU_WORD_M0PE_MASK (0x20U)
mbed_official 121:7f86b4238bec 8362 #define MPU_WORD_M0PE_SHIFT (5U)
mbed_official 121:7f86b4238bec 8363 #define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK)
mbed_official 121:7f86b4238bec 8364 #define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
mbed_official 121:7f86b4238bec 8365 #define MPU_WORD_ENDADDR_SHIFT (5U)
mbed_official 121:7f86b4238bec 8366 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
mbed_official 121:7f86b4238bec 8367 #define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
mbed_official 121:7f86b4238bec 8368 #define MPU_WORD_SRTADDR_SHIFT (5U)
mbed_official 121:7f86b4238bec 8369 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
mbed_official 121:7f86b4238bec 8370 #define MPU_WORD_M1UM_MASK (0x1C0U)
mbed_official 121:7f86b4238bec 8371 #define MPU_WORD_M1UM_SHIFT (6U)
mbed_official 121:7f86b4238bec 8372 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
mbed_official 121:7f86b4238bec 8373 #define MPU_WORD_M1SM_MASK (0x600U)
mbed_official 121:7f86b4238bec 8374 #define MPU_WORD_M1SM_SHIFT (9U)
mbed_official 121:7f86b4238bec 8375 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
mbed_official 121:7f86b4238bec 8376 #define MPU_WORD_M1PE_MASK (0x800U)
mbed_official 121:7f86b4238bec 8377 #define MPU_WORD_M1PE_SHIFT (11U)
mbed_official 121:7f86b4238bec 8378 #define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK)
mbed_official 121:7f86b4238bec 8379 #define MPU_WORD_M2UM_MASK (0x7000U)
mbed_official 121:7f86b4238bec 8380 #define MPU_WORD_M2UM_SHIFT (12U)
mbed_official 121:7f86b4238bec 8381 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
mbed_official 121:7f86b4238bec 8382 #define MPU_WORD_M2SM_MASK (0x18000U)
mbed_official 121:7f86b4238bec 8383 #define MPU_WORD_M2SM_SHIFT (15U)
mbed_official 121:7f86b4238bec 8384 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
mbed_official 121:7f86b4238bec 8385 #define MPU_WORD_PIDMASK_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 8386 #define MPU_WORD_PIDMASK_SHIFT (16U)
mbed_official 121:7f86b4238bec 8387 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
mbed_official 121:7f86b4238bec 8388 #define MPU_WORD_M2PE_MASK (0x20000U)
mbed_official 121:7f86b4238bec 8389 #define MPU_WORD_M2PE_SHIFT (17U)
mbed_official 121:7f86b4238bec 8390 #define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK)
mbed_official 121:7f86b4238bec 8391 #define MPU_WORD_M3UM_MASK (0x1C0000U)
mbed_official 121:7f86b4238bec 8392 #define MPU_WORD_M3UM_SHIFT (18U)
mbed_official 121:7f86b4238bec 8393 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
mbed_official 121:7f86b4238bec 8394 #define MPU_WORD_M3SM_MASK (0x600000U)
mbed_official 121:7f86b4238bec 8395 #define MPU_WORD_M3SM_SHIFT (21U)
mbed_official 121:7f86b4238bec 8396 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
mbed_official 121:7f86b4238bec 8397 #define MPU_WORD_M3PE_MASK (0x800000U)
mbed_official 121:7f86b4238bec 8398 #define MPU_WORD_M3PE_SHIFT (23U)
mbed_official 121:7f86b4238bec 8399 #define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK)
mbed_official 121:7f86b4238bec 8400 #define MPU_WORD_PID_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 8401 #define MPU_WORD_PID_SHIFT (24U)
mbed_official 121:7f86b4238bec 8402 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
mbed_official 121:7f86b4238bec 8403 #define MPU_WORD_M4WE_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 8404 #define MPU_WORD_M4WE_SHIFT (24U)
mbed_official 121:7f86b4238bec 8405 #define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK)
mbed_official 121:7f86b4238bec 8406 #define MPU_WORD_M4RE_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 8407 #define MPU_WORD_M4RE_SHIFT (25U)
mbed_official 121:7f86b4238bec 8408 #define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK)
mbed_official 121:7f86b4238bec 8409 #define MPU_WORD_M5WE_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 8410 #define MPU_WORD_M5WE_SHIFT (26U)
mbed_official 121:7f86b4238bec 8411 #define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK)
mbed_official 121:7f86b4238bec 8412 #define MPU_WORD_M5RE_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 8413 #define MPU_WORD_M5RE_SHIFT (27U)
mbed_official 121:7f86b4238bec 8414 #define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK)
mbed_official 121:7f86b4238bec 8415 #define MPU_WORD_M6WE_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 8416 #define MPU_WORD_M6WE_SHIFT (28U)
mbed_official 121:7f86b4238bec 8417 #define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK)
mbed_official 121:7f86b4238bec 8418 #define MPU_WORD_M6RE_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 8419 #define MPU_WORD_M6RE_SHIFT (29U)
mbed_official 121:7f86b4238bec 8420 #define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK)
mbed_official 121:7f86b4238bec 8421 #define MPU_WORD_M7WE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 8422 #define MPU_WORD_M7WE_SHIFT (30U)
mbed_official 121:7f86b4238bec 8423 #define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK)
mbed_official 121:7f86b4238bec 8424 #define MPU_WORD_M7RE_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 8425 #define MPU_WORD_M7RE_SHIFT (31U)
mbed_official 121:7f86b4238bec 8426 #define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK)
mbed_official 121:7f86b4238bec 8427
mbed_official 121:7f86b4238bec 8428 /* The count of MPU_WORD */
mbed_official 121:7f86b4238bec 8429 #define MPU_WORD_COUNT (12U)
mbed_official 121:7f86b4238bec 8430
mbed_official 121:7f86b4238bec 8431 /* The count of MPU_WORD */
mbed_official 121:7f86b4238bec 8432 #define MPU_WORD_COUNT2 (4U)
mbed_official 121:7f86b4238bec 8433
mbed_official 121:7f86b4238bec 8434 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */
mbed_official 121:7f86b4238bec 8435 #define MPU_RGDAAC_M0UM_MASK (0x7U)
mbed_official 121:7f86b4238bec 8436 #define MPU_RGDAAC_M0UM_SHIFT (0U)
mbed_official 121:7f86b4238bec 8437 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
mbed_official 121:7f86b4238bec 8438 #define MPU_RGDAAC_M0SM_MASK (0x18U)
mbed_official 121:7f86b4238bec 8439 #define MPU_RGDAAC_M0SM_SHIFT (3U)
mbed_official 121:7f86b4238bec 8440 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
mbed_official 121:7f86b4238bec 8441 #define MPU_RGDAAC_M0PE_MASK (0x20U)
mbed_official 121:7f86b4238bec 8442 #define MPU_RGDAAC_M0PE_SHIFT (5U)
mbed_official 121:7f86b4238bec 8443 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK)
mbed_official 121:7f86b4238bec 8444 #define MPU_RGDAAC_M1UM_MASK (0x1C0U)
mbed_official 121:7f86b4238bec 8445 #define MPU_RGDAAC_M1UM_SHIFT (6U)
mbed_official 121:7f86b4238bec 8446 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
mbed_official 121:7f86b4238bec 8447 #define MPU_RGDAAC_M1SM_MASK (0x600U)
mbed_official 121:7f86b4238bec 8448 #define MPU_RGDAAC_M1SM_SHIFT (9U)
mbed_official 121:7f86b4238bec 8449 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
mbed_official 121:7f86b4238bec 8450 #define MPU_RGDAAC_M1PE_MASK (0x800U)
mbed_official 121:7f86b4238bec 8451 #define MPU_RGDAAC_M1PE_SHIFT (11U)
mbed_official 121:7f86b4238bec 8452 #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK)
mbed_official 121:7f86b4238bec 8453 #define MPU_RGDAAC_M2UM_MASK (0x7000U)
mbed_official 121:7f86b4238bec 8454 #define MPU_RGDAAC_M2UM_SHIFT (12U)
mbed_official 121:7f86b4238bec 8455 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
mbed_official 121:7f86b4238bec 8456 #define MPU_RGDAAC_M2SM_MASK (0x18000U)
mbed_official 121:7f86b4238bec 8457 #define MPU_RGDAAC_M2SM_SHIFT (15U)
mbed_official 121:7f86b4238bec 8458 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
mbed_official 121:7f86b4238bec 8459 #define MPU_RGDAAC_M2PE_MASK (0x20000U)
mbed_official 121:7f86b4238bec 8460 #define MPU_RGDAAC_M2PE_SHIFT (17U)
mbed_official 121:7f86b4238bec 8461 #define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK)
mbed_official 121:7f86b4238bec 8462 #define MPU_RGDAAC_M3UM_MASK (0x1C0000U)
mbed_official 121:7f86b4238bec 8463 #define MPU_RGDAAC_M3UM_SHIFT (18U)
mbed_official 121:7f86b4238bec 8464 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
mbed_official 121:7f86b4238bec 8465 #define MPU_RGDAAC_M3SM_MASK (0x600000U)
mbed_official 121:7f86b4238bec 8466 #define MPU_RGDAAC_M3SM_SHIFT (21U)
mbed_official 121:7f86b4238bec 8467 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
mbed_official 121:7f86b4238bec 8468 #define MPU_RGDAAC_M3PE_MASK (0x800000U)
mbed_official 121:7f86b4238bec 8469 #define MPU_RGDAAC_M3PE_SHIFT (23U)
mbed_official 121:7f86b4238bec 8470 #define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK)
mbed_official 121:7f86b4238bec 8471 #define MPU_RGDAAC_M4WE_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 8472 #define MPU_RGDAAC_M4WE_SHIFT (24U)
mbed_official 121:7f86b4238bec 8473 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK)
mbed_official 121:7f86b4238bec 8474 #define MPU_RGDAAC_M4RE_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 8475 #define MPU_RGDAAC_M4RE_SHIFT (25U)
mbed_official 121:7f86b4238bec 8476 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK)
mbed_official 121:7f86b4238bec 8477 #define MPU_RGDAAC_M5WE_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 8478 #define MPU_RGDAAC_M5WE_SHIFT (26U)
mbed_official 121:7f86b4238bec 8479 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK)
mbed_official 121:7f86b4238bec 8480 #define MPU_RGDAAC_M5RE_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 8481 #define MPU_RGDAAC_M5RE_SHIFT (27U)
mbed_official 121:7f86b4238bec 8482 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK)
mbed_official 121:7f86b4238bec 8483 #define MPU_RGDAAC_M6WE_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 8484 #define MPU_RGDAAC_M6WE_SHIFT (28U)
mbed_official 121:7f86b4238bec 8485 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK)
mbed_official 121:7f86b4238bec 8486 #define MPU_RGDAAC_M6RE_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 8487 #define MPU_RGDAAC_M6RE_SHIFT (29U)
mbed_official 121:7f86b4238bec 8488 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK)
mbed_official 121:7f86b4238bec 8489 #define MPU_RGDAAC_M7WE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 8490 #define MPU_RGDAAC_M7WE_SHIFT (30U)
mbed_official 121:7f86b4238bec 8491 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK)
mbed_official 121:7f86b4238bec 8492 #define MPU_RGDAAC_M7RE_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 8493 #define MPU_RGDAAC_M7RE_SHIFT (31U)
mbed_official 121:7f86b4238bec 8494 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK)
mbed_official 121:7f86b4238bec 8495
mbed_official 121:7f86b4238bec 8496 /* The count of MPU_RGDAAC */
mbed_official 121:7f86b4238bec 8497 #define MPU_RGDAAC_COUNT (12U)
mbed_official 121:7f86b4238bec 8498
mbed_official 121:7f86b4238bec 8499
mbed_official 121:7f86b4238bec 8500 /*!
mbed_official 121:7f86b4238bec 8501 * @}
mbed_official 121:7f86b4238bec 8502 */ /* end of group MPU_Register_Masks */
mbed_official 121:7f86b4238bec 8503
mbed_official 121:7f86b4238bec 8504
mbed_official 121:7f86b4238bec 8505 /* MPU - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 8506 /** Peripheral MPU base address */
mbed_official 121:7f86b4238bec 8507 #define MPU_BASE (0x4000D000u)
mbed_official 121:7f86b4238bec 8508 /** Peripheral MPU base pointer */
mbed_official 121:7f86b4238bec 8509 #define MPU ((MPU_Type *)MPU_BASE)
mbed_official 121:7f86b4238bec 8510 /** Array initializer of MPU peripheral base addresses */
mbed_official 121:7f86b4238bec 8511 #define MPU_BASE_ADDRS { MPU_BASE }
mbed_official 121:7f86b4238bec 8512 /** Array initializer of MPU peripheral base pointers */
mbed_official 121:7f86b4238bec 8513 #define MPU_BASE_PTRS { MPU }
mbed_official 121:7f86b4238bec 8514
mbed_official 121:7f86b4238bec 8515 /*!
mbed_official 121:7f86b4238bec 8516 * @}
mbed_official 121:7f86b4238bec 8517 */ /* end of group MPU_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 8518
mbed_official 121:7f86b4238bec 8519
mbed_official 121:7f86b4238bec 8520 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8521 -- NV Peripheral Access Layer
mbed_official 121:7f86b4238bec 8522 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8523
mbed_official 121:7f86b4238bec 8524 /*!
mbed_official 121:7f86b4238bec 8525 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mbed_official 121:7f86b4238bec 8526 * @{
mbed_official 121:7f86b4238bec 8527 */
mbed_official 121:7f86b4238bec 8528
mbed_official 121:7f86b4238bec 8529 /** NV - Register Layout Typedef */
mbed_official 121:7f86b4238bec 8530 typedef struct {
mbed_official 121:7f86b4238bec 8531 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mbed_official 121:7f86b4238bec 8532 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mbed_official 121:7f86b4238bec 8533 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mbed_official 121:7f86b4238bec 8534 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mbed_official 121:7f86b4238bec 8535 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mbed_official 121:7f86b4238bec 8536 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mbed_official 121:7f86b4238bec 8537 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mbed_official 121:7f86b4238bec 8538 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mbed_official 121:7f86b4238bec 8539 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 8540 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mbed_official 121:7f86b4238bec 8541 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mbed_official 121:7f86b4238bec 8542 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mbed_official 121:7f86b4238bec 8543 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mbed_official 121:7f86b4238bec 8544 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mbed_official 121:7f86b4238bec 8545 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
mbed_official 121:7f86b4238bec 8546 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
mbed_official 121:7f86b4238bec 8547 } NV_Type;
mbed_official 121:7f86b4238bec 8548
mbed_official 121:7f86b4238bec 8549 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8550 -- NV Register Masks
mbed_official 121:7f86b4238bec 8551 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8552
mbed_official 121:7f86b4238bec 8553 /*!
mbed_official 121:7f86b4238bec 8554 * @addtogroup NV_Register_Masks NV Register Masks
mbed_official 121:7f86b4238bec 8555 * @{
mbed_official 121:7f86b4238bec 8556 */
mbed_official 121:7f86b4238bec 8557
mbed_official 121:7f86b4238bec 8558 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
mbed_official 121:7f86b4238bec 8559 #define NV_BACKKEY3_KEY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8560 #define NV_BACKKEY3_KEY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8561 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
mbed_official 121:7f86b4238bec 8562
mbed_official 121:7f86b4238bec 8563 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
mbed_official 121:7f86b4238bec 8564 #define NV_BACKKEY2_KEY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8565 #define NV_BACKKEY2_KEY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8566 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
mbed_official 121:7f86b4238bec 8567
mbed_official 121:7f86b4238bec 8568 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
mbed_official 121:7f86b4238bec 8569 #define NV_BACKKEY1_KEY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8570 #define NV_BACKKEY1_KEY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8571 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
mbed_official 121:7f86b4238bec 8572
mbed_official 121:7f86b4238bec 8573 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
mbed_official 121:7f86b4238bec 8574 #define NV_BACKKEY0_KEY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8575 #define NV_BACKKEY0_KEY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8576 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
mbed_official 121:7f86b4238bec 8577
mbed_official 121:7f86b4238bec 8578 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
mbed_official 121:7f86b4238bec 8579 #define NV_BACKKEY7_KEY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8580 #define NV_BACKKEY7_KEY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8581 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
mbed_official 121:7f86b4238bec 8582
mbed_official 121:7f86b4238bec 8583 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
mbed_official 121:7f86b4238bec 8584 #define NV_BACKKEY6_KEY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8585 #define NV_BACKKEY6_KEY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8586 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
mbed_official 121:7f86b4238bec 8587
mbed_official 121:7f86b4238bec 8588 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
mbed_official 121:7f86b4238bec 8589 #define NV_BACKKEY5_KEY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8590 #define NV_BACKKEY5_KEY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8591 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
mbed_official 121:7f86b4238bec 8592
mbed_official 121:7f86b4238bec 8593 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
mbed_official 121:7f86b4238bec 8594 #define NV_BACKKEY4_KEY_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8595 #define NV_BACKKEY4_KEY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8596 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
mbed_official 121:7f86b4238bec 8597
mbed_official 121:7f86b4238bec 8598 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
mbed_official 121:7f86b4238bec 8599 #define NV_FPROT3_PROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8600 #define NV_FPROT3_PROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8601 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
mbed_official 121:7f86b4238bec 8602
mbed_official 121:7f86b4238bec 8603 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
mbed_official 121:7f86b4238bec 8604 #define NV_FPROT2_PROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8605 #define NV_FPROT2_PROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8606 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
mbed_official 121:7f86b4238bec 8607
mbed_official 121:7f86b4238bec 8608 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
mbed_official 121:7f86b4238bec 8609 #define NV_FPROT1_PROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8610 #define NV_FPROT1_PROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8611 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
mbed_official 121:7f86b4238bec 8612
mbed_official 121:7f86b4238bec 8613 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
mbed_official 121:7f86b4238bec 8614 #define NV_FPROT0_PROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8615 #define NV_FPROT0_PROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8616 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
mbed_official 121:7f86b4238bec 8617
mbed_official 121:7f86b4238bec 8618 /*! @name FSEC - Non-volatile Flash Security Register */
mbed_official 121:7f86b4238bec 8619 #define NV_FSEC_SEC_MASK (0x3U)
mbed_official 121:7f86b4238bec 8620 #define NV_FSEC_SEC_SHIFT (0U)
mbed_official 121:7f86b4238bec 8621 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
mbed_official 121:7f86b4238bec 8622 #define NV_FSEC_FSLACC_MASK (0xCU)
mbed_official 121:7f86b4238bec 8623 #define NV_FSEC_FSLACC_SHIFT (2U)
mbed_official 121:7f86b4238bec 8624 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
mbed_official 121:7f86b4238bec 8625 #define NV_FSEC_MEEN_MASK (0x30U)
mbed_official 121:7f86b4238bec 8626 #define NV_FSEC_MEEN_SHIFT (4U)
mbed_official 121:7f86b4238bec 8627 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
mbed_official 121:7f86b4238bec 8628 #define NV_FSEC_KEYEN_MASK (0xC0U)
mbed_official 121:7f86b4238bec 8629 #define NV_FSEC_KEYEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 8630 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
mbed_official 121:7f86b4238bec 8631
mbed_official 121:7f86b4238bec 8632 /*! @name FOPT - Non-volatile Flash Option Register */
mbed_official 121:7f86b4238bec 8633 #define NV_FOPT_LPBOOT_MASK (0x1U)
mbed_official 121:7f86b4238bec 8634 #define NV_FOPT_LPBOOT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8635 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
mbed_official 121:7f86b4238bec 8636 #define NV_FOPT_EZPORT_DIS_MASK (0x2U)
mbed_official 121:7f86b4238bec 8637 #define NV_FOPT_EZPORT_DIS_SHIFT (1U)
mbed_official 121:7f86b4238bec 8638 #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
mbed_official 121:7f86b4238bec 8639
mbed_official 121:7f86b4238bec 8640 /*! @name FEPROT - Non-volatile EERAM Protection Register */
mbed_official 121:7f86b4238bec 8641 #define NV_FEPROT_EPROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8642 #define NV_FEPROT_EPROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8643 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
mbed_official 121:7f86b4238bec 8644
mbed_official 121:7f86b4238bec 8645 /*! @name FDPROT - Non-volatile D-Flash Protection Register */
mbed_official 121:7f86b4238bec 8646 #define NV_FDPROT_DPROT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8647 #define NV_FDPROT_DPROT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8648 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
mbed_official 121:7f86b4238bec 8649
mbed_official 121:7f86b4238bec 8650
mbed_official 121:7f86b4238bec 8651 /*!
mbed_official 121:7f86b4238bec 8652 * @}
mbed_official 121:7f86b4238bec 8653 */ /* end of group NV_Register_Masks */
mbed_official 121:7f86b4238bec 8654
mbed_official 121:7f86b4238bec 8655
mbed_official 121:7f86b4238bec 8656 /* NV - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 8657 /** Peripheral FTFE_FlashConfig base address */
mbed_official 121:7f86b4238bec 8658 #define FTFE_FlashConfig_BASE (0x400u)
mbed_official 121:7f86b4238bec 8659 /** Peripheral FTFE_FlashConfig base pointer */
mbed_official 121:7f86b4238bec 8660 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
mbed_official 121:7f86b4238bec 8661 /** Array initializer of NV peripheral base addresses */
mbed_official 121:7f86b4238bec 8662 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
mbed_official 121:7f86b4238bec 8663 /** Array initializer of NV peripheral base pointers */
mbed_official 121:7f86b4238bec 8664 #define NV_BASE_PTRS { FTFE_FlashConfig }
mbed_official 121:7f86b4238bec 8665
mbed_official 121:7f86b4238bec 8666 /*!
mbed_official 121:7f86b4238bec 8667 * @}
mbed_official 121:7f86b4238bec 8668 */ /* end of group NV_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 8669
mbed_official 121:7f86b4238bec 8670
mbed_official 121:7f86b4238bec 8671 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8672 -- OSC Peripheral Access Layer
mbed_official 121:7f86b4238bec 8673 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8674
mbed_official 121:7f86b4238bec 8675 /*!
mbed_official 121:7f86b4238bec 8676 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mbed_official 121:7f86b4238bec 8677 * @{
mbed_official 121:7f86b4238bec 8678 */
mbed_official 121:7f86b4238bec 8679
mbed_official 121:7f86b4238bec 8680 /** OSC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 8681 typedef struct {
mbed_official 121:7f86b4238bec 8682 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 8683 } OSC_Type;
mbed_official 121:7f86b4238bec 8684
mbed_official 121:7f86b4238bec 8685 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8686 -- OSC Register Masks
mbed_official 121:7f86b4238bec 8687 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8688
mbed_official 121:7f86b4238bec 8689 /*!
mbed_official 121:7f86b4238bec 8690 * @addtogroup OSC_Register_Masks OSC Register Masks
mbed_official 121:7f86b4238bec 8691 * @{
mbed_official 121:7f86b4238bec 8692 */
mbed_official 121:7f86b4238bec 8693
mbed_official 121:7f86b4238bec 8694 /*! @name CR - OSC Control Register */
mbed_official 121:7f86b4238bec 8695 #define OSC_CR_SC16P_MASK (0x1U)
mbed_official 121:7f86b4238bec 8696 #define OSC_CR_SC16P_SHIFT (0U)
mbed_official 121:7f86b4238bec 8697 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
mbed_official 121:7f86b4238bec 8698 #define OSC_CR_SC8P_MASK (0x2U)
mbed_official 121:7f86b4238bec 8699 #define OSC_CR_SC8P_SHIFT (1U)
mbed_official 121:7f86b4238bec 8700 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
mbed_official 121:7f86b4238bec 8701 #define OSC_CR_SC4P_MASK (0x4U)
mbed_official 121:7f86b4238bec 8702 #define OSC_CR_SC4P_SHIFT (2U)
mbed_official 121:7f86b4238bec 8703 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
mbed_official 121:7f86b4238bec 8704 #define OSC_CR_SC2P_MASK (0x8U)
mbed_official 121:7f86b4238bec 8705 #define OSC_CR_SC2P_SHIFT (3U)
mbed_official 121:7f86b4238bec 8706 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
mbed_official 121:7f86b4238bec 8707 #define OSC_CR_EREFSTEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 8708 #define OSC_CR_EREFSTEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 8709 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
mbed_official 121:7f86b4238bec 8710 #define OSC_CR_ERCLKEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 8711 #define OSC_CR_ERCLKEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 8712 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
mbed_official 121:7f86b4238bec 8713
mbed_official 121:7f86b4238bec 8714
mbed_official 121:7f86b4238bec 8715 /*!
mbed_official 121:7f86b4238bec 8716 * @}
mbed_official 121:7f86b4238bec 8717 */ /* end of group OSC_Register_Masks */
mbed_official 121:7f86b4238bec 8718
mbed_official 121:7f86b4238bec 8719
mbed_official 121:7f86b4238bec 8720 /* OSC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 8721 /** Peripheral OSC base address */
mbed_official 121:7f86b4238bec 8722 #define OSC_BASE (0x40065000u)
mbed_official 121:7f86b4238bec 8723 /** Peripheral OSC base pointer */
mbed_official 121:7f86b4238bec 8724 #define OSC ((OSC_Type *)OSC_BASE)
mbed_official 121:7f86b4238bec 8725 /** Array initializer of OSC peripheral base addresses */
mbed_official 121:7f86b4238bec 8726 #define OSC_BASE_ADDRS { OSC_BASE }
mbed_official 121:7f86b4238bec 8727 /** Array initializer of OSC peripheral base pointers */
mbed_official 121:7f86b4238bec 8728 #define OSC_BASE_PTRS { OSC }
mbed_official 121:7f86b4238bec 8729
mbed_official 121:7f86b4238bec 8730 /*!
mbed_official 121:7f86b4238bec 8731 * @}
mbed_official 121:7f86b4238bec 8732 */ /* end of group OSC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 8733
mbed_official 121:7f86b4238bec 8734
mbed_official 121:7f86b4238bec 8735 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8736 -- PDB Peripheral Access Layer
mbed_official 121:7f86b4238bec 8737 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8738
mbed_official 121:7f86b4238bec 8739 /*!
mbed_official 121:7f86b4238bec 8740 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
mbed_official 121:7f86b4238bec 8741 * @{
mbed_official 121:7f86b4238bec 8742 */
mbed_official 121:7f86b4238bec 8743
mbed_official 121:7f86b4238bec 8744 /** PDB - Register Layout Typedef */
mbed_official 121:7f86b4238bec 8745 typedef struct {
mbed_official 121:7f86b4238bec 8746 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
mbed_official 121:7f86b4238bec 8747 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
mbed_official 121:7f86b4238bec 8748 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
mbed_official 121:7f86b4238bec 8749 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
mbed_official 121:7f86b4238bec 8750 struct { /* offset: 0x10, array step: 0x28 */
mbed_official 121:7f86b4238bec 8751 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
mbed_official 121:7f86b4238bec 8752 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
mbed_official 121:7f86b4238bec 8753 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
mbed_official 121:7f86b4238bec 8754 uint8_t RESERVED_0[24];
mbed_official 121:7f86b4238bec 8755 } CH[2];
mbed_official 121:7f86b4238bec 8756 uint8_t RESERVED_0[240];
mbed_official 121:7f86b4238bec 8757 struct { /* offset: 0x150, array step: 0x8 */
mbed_official 121:7f86b4238bec 8758 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
mbed_official 121:7f86b4238bec 8759 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
mbed_official 121:7f86b4238bec 8760 } DAC[2];
mbed_official 121:7f86b4238bec 8761 uint8_t RESERVED_1[48];
mbed_official 121:7f86b4238bec 8762 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
mbed_official 121:7f86b4238bec 8763 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
mbed_official 121:7f86b4238bec 8764 } PDB_Type;
mbed_official 121:7f86b4238bec 8765
mbed_official 121:7f86b4238bec 8766 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8767 -- PDB Register Masks
mbed_official 121:7f86b4238bec 8768 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8769
mbed_official 121:7f86b4238bec 8770 /*!
mbed_official 121:7f86b4238bec 8771 * @addtogroup PDB_Register_Masks PDB Register Masks
mbed_official 121:7f86b4238bec 8772 * @{
mbed_official 121:7f86b4238bec 8773 */
mbed_official 121:7f86b4238bec 8774
mbed_official 121:7f86b4238bec 8775 /*! @name SC - Status and Control register */
mbed_official 121:7f86b4238bec 8776 #define PDB_SC_LDOK_MASK (0x1U)
mbed_official 121:7f86b4238bec 8777 #define PDB_SC_LDOK_SHIFT (0U)
mbed_official 121:7f86b4238bec 8778 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
mbed_official 121:7f86b4238bec 8779 #define PDB_SC_CONT_MASK (0x2U)
mbed_official 121:7f86b4238bec 8780 #define PDB_SC_CONT_SHIFT (1U)
mbed_official 121:7f86b4238bec 8781 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
mbed_official 121:7f86b4238bec 8782 #define PDB_SC_MULT_MASK (0xCU)
mbed_official 121:7f86b4238bec 8783 #define PDB_SC_MULT_SHIFT (2U)
mbed_official 121:7f86b4238bec 8784 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
mbed_official 121:7f86b4238bec 8785 #define PDB_SC_PDBIE_MASK (0x20U)
mbed_official 121:7f86b4238bec 8786 #define PDB_SC_PDBIE_SHIFT (5U)
mbed_official 121:7f86b4238bec 8787 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
mbed_official 121:7f86b4238bec 8788 #define PDB_SC_PDBIF_MASK (0x40U)
mbed_official 121:7f86b4238bec 8789 #define PDB_SC_PDBIF_SHIFT (6U)
mbed_official 121:7f86b4238bec 8790 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
mbed_official 121:7f86b4238bec 8791 #define PDB_SC_PDBEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 8792 #define PDB_SC_PDBEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 8793 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
mbed_official 121:7f86b4238bec 8794 #define PDB_SC_TRGSEL_MASK (0xF00U)
mbed_official 121:7f86b4238bec 8795 #define PDB_SC_TRGSEL_SHIFT (8U)
mbed_official 121:7f86b4238bec 8796 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
mbed_official 121:7f86b4238bec 8797 #define PDB_SC_PRESCALER_MASK (0x7000U)
mbed_official 121:7f86b4238bec 8798 #define PDB_SC_PRESCALER_SHIFT (12U)
mbed_official 121:7f86b4238bec 8799 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
mbed_official 121:7f86b4238bec 8800 #define PDB_SC_DMAEN_MASK (0x8000U)
mbed_official 121:7f86b4238bec 8801 #define PDB_SC_DMAEN_SHIFT (15U)
mbed_official 121:7f86b4238bec 8802 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
mbed_official 121:7f86b4238bec 8803 #define PDB_SC_SWTRIG_MASK (0x10000U)
mbed_official 121:7f86b4238bec 8804 #define PDB_SC_SWTRIG_SHIFT (16U)
mbed_official 121:7f86b4238bec 8805 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
mbed_official 121:7f86b4238bec 8806 #define PDB_SC_PDBEIE_MASK (0x20000U)
mbed_official 121:7f86b4238bec 8807 #define PDB_SC_PDBEIE_SHIFT (17U)
mbed_official 121:7f86b4238bec 8808 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
mbed_official 121:7f86b4238bec 8809 #define PDB_SC_LDMOD_MASK (0xC0000U)
mbed_official 121:7f86b4238bec 8810 #define PDB_SC_LDMOD_SHIFT (18U)
mbed_official 121:7f86b4238bec 8811 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
mbed_official 121:7f86b4238bec 8812
mbed_official 121:7f86b4238bec 8813 /*! @name MOD - Modulus register */
mbed_official 121:7f86b4238bec 8814 #define PDB_MOD_MOD_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 8815 #define PDB_MOD_MOD_SHIFT (0U)
mbed_official 121:7f86b4238bec 8816 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
mbed_official 121:7f86b4238bec 8817
mbed_official 121:7f86b4238bec 8818 /*! @name CNT - Counter register */
mbed_official 121:7f86b4238bec 8819 #define PDB_CNT_CNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 8820 #define PDB_CNT_CNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8821 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
mbed_official 121:7f86b4238bec 8822
mbed_official 121:7f86b4238bec 8823 /*! @name IDLY - Interrupt Delay register */
mbed_official 121:7f86b4238bec 8824 #define PDB_IDLY_IDLY_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 8825 #define PDB_IDLY_IDLY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8826 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
mbed_official 121:7f86b4238bec 8827
mbed_official 121:7f86b4238bec 8828 /*! @name C1 - Channel n Control register 1 */
mbed_official 121:7f86b4238bec 8829 #define PDB_C1_EN_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8830 #define PDB_C1_EN_SHIFT (0U)
mbed_official 121:7f86b4238bec 8831 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
mbed_official 121:7f86b4238bec 8832 #define PDB_C1_TOS_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 8833 #define PDB_C1_TOS_SHIFT (8U)
mbed_official 121:7f86b4238bec 8834 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
mbed_official 121:7f86b4238bec 8835 #define PDB_C1_BB_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 8836 #define PDB_C1_BB_SHIFT (16U)
mbed_official 121:7f86b4238bec 8837 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
mbed_official 121:7f86b4238bec 8838
mbed_official 121:7f86b4238bec 8839 /* The count of PDB_C1 */
mbed_official 121:7f86b4238bec 8840 #define PDB_C1_COUNT (2U)
mbed_official 121:7f86b4238bec 8841
mbed_official 121:7f86b4238bec 8842 /*! @name S - Channel n Status register */
mbed_official 121:7f86b4238bec 8843 #define PDB_S_ERR_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8844 #define PDB_S_ERR_SHIFT (0U)
mbed_official 121:7f86b4238bec 8845 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
mbed_official 121:7f86b4238bec 8846 #define PDB_S_CF_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 8847 #define PDB_S_CF_SHIFT (16U)
mbed_official 121:7f86b4238bec 8848 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
mbed_official 121:7f86b4238bec 8849
mbed_official 121:7f86b4238bec 8850 /* The count of PDB_S */
mbed_official 121:7f86b4238bec 8851 #define PDB_S_COUNT (2U)
mbed_official 121:7f86b4238bec 8852
mbed_official 121:7f86b4238bec 8853 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
mbed_official 121:7f86b4238bec 8854 #define PDB_DLY_DLY_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 8855 #define PDB_DLY_DLY_SHIFT (0U)
mbed_official 121:7f86b4238bec 8856 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
mbed_official 121:7f86b4238bec 8857
mbed_official 121:7f86b4238bec 8858 /* The count of PDB_DLY */
mbed_official 121:7f86b4238bec 8859 #define PDB_DLY_COUNT (2U)
mbed_official 121:7f86b4238bec 8860
mbed_official 121:7f86b4238bec 8861 /* The count of PDB_DLY */
mbed_official 121:7f86b4238bec 8862 #define PDB_DLY_COUNT2 (2U)
mbed_official 121:7f86b4238bec 8863
mbed_official 121:7f86b4238bec 8864 /*! @name INTC - DAC Interval Trigger n Control register */
mbed_official 121:7f86b4238bec 8865 #define PDB_INTC_TOE_MASK (0x1U)
mbed_official 121:7f86b4238bec 8866 #define PDB_INTC_TOE_SHIFT (0U)
mbed_official 121:7f86b4238bec 8867 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
mbed_official 121:7f86b4238bec 8868 #define PDB_INTC_EXT_MASK (0x2U)
mbed_official 121:7f86b4238bec 8869 #define PDB_INTC_EXT_SHIFT (1U)
mbed_official 121:7f86b4238bec 8870 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
mbed_official 121:7f86b4238bec 8871
mbed_official 121:7f86b4238bec 8872 /* The count of PDB_INTC */
mbed_official 121:7f86b4238bec 8873 #define PDB_INTC_COUNT (2U)
mbed_official 121:7f86b4238bec 8874
mbed_official 121:7f86b4238bec 8875 /*! @name INT - DAC Interval n register */
mbed_official 121:7f86b4238bec 8876 #define PDB_INT_INT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 8877 #define PDB_INT_INT_SHIFT (0U)
mbed_official 121:7f86b4238bec 8878 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
mbed_official 121:7f86b4238bec 8879
mbed_official 121:7f86b4238bec 8880 /* The count of PDB_INT */
mbed_official 121:7f86b4238bec 8881 #define PDB_INT_COUNT (2U)
mbed_official 121:7f86b4238bec 8882
mbed_official 121:7f86b4238bec 8883 /*! @name POEN - Pulse-Out n Enable register */
mbed_official 121:7f86b4238bec 8884 #define PDB_POEN_POEN_MASK (0xFFU)
mbed_official 121:7f86b4238bec 8885 #define PDB_POEN_POEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 8886 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
mbed_official 121:7f86b4238bec 8887
mbed_official 121:7f86b4238bec 8888 /*! @name PODLY - Pulse-Out n Delay register */
mbed_official 121:7f86b4238bec 8889 #define PDB_PODLY_DLY2_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 8890 #define PDB_PODLY_DLY2_SHIFT (0U)
mbed_official 121:7f86b4238bec 8891 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
mbed_official 121:7f86b4238bec 8892 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 8893 #define PDB_PODLY_DLY1_SHIFT (16U)
mbed_official 121:7f86b4238bec 8894 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
mbed_official 121:7f86b4238bec 8895
mbed_official 121:7f86b4238bec 8896 /* The count of PDB_PODLY */
mbed_official 121:7f86b4238bec 8897 #define PDB_PODLY_COUNT (3U)
mbed_official 121:7f86b4238bec 8898
mbed_official 121:7f86b4238bec 8899
mbed_official 121:7f86b4238bec 8900 /*!
mbed_official 121:7f86b4238bec 8901 * @}
mbed_official 121:7f86b4238bec 8902 */ /* end of group PDB_Register_Masks */
mbed_official 121:7f86b4238bec 8903
mbed_official 121:7f86b4238bec 8904
mbed_official 121:7f86b4238bec 8905 /* PDB - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 8906 /** Peripheral PDB0 base address */
mbed_official 121:7f86b4238bec 8907 #define PDB0_BASE (0x40036000u)
mbed_official 121:7f86b4238bec 8908 /** Peripheral PDB0 base pointer */
mbed_official 121:7f86b4238bec 8909 #define PDB0 ((PDB_Type *)PDB0_BASE)
mbed_official 121:7f86b4238bec 8910 /** Array initializer of PDB peripheral base addresses */
mbed_official 121:7f86b4238bec 8911 #define PDB_BASE_ADDRS { PDB0_BASE }
mbed_official 121:7f86b4238bec 8912 /** Array initializer of PDB peripheral base pointers */
mbed_official 121:7f86b4238bec 8913 #define PDB_BASE_PTRS { PDB0 }
mbed_official 121:7f86b4238bec 8914 /** Interrupt vectors for the PDB peripheral type */
mbed_official 121:7f86b4238bec 8915 #define PDB_IRQS { PDB0_IRQn }
mbed_official 121:7f86b4238bec 8916
mbed_official 121:7f86b4238bec 8917 /*!
mbed_official 121:7f86b4238bec 8918 * @}
mbed_official 121:7f86b4238bec 8919 */ /* end of group PDB_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 8920
mbed_official 121:7f86b4238bec 8921
mbed_official 121:7f86b4238bec 8922 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8923 -- PIT Peripheral Access Layer
mbed_official 121:7f86b4238bec 8924 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8925
mbed_official 121:7f86b4238bec 8926 /*!
mbed_official 121:7f86b4238bec 8927 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mbed_official 121:7f86b4238bec 8928 * @{
mbed_official 121:7f86b4238bec 8929 */
mbed_official 121:7f86b4238bec 8930
mbed_official 121:7f86b4238bec 8931 /** PIT - Register Layout Typedef */
mbed_official 121:7f86b4238bec 8932 typedef struct {
mbed_official 121:7f86b4238bec 8933 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 8934 uint8_t RESERVED_0[252];
mbed_official 121:7f86b4238bec 8935 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 121:7f86b4238bec 8936 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mbed_official 121:7f86b4238bec 8937 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mbed_official 121:7f86b4238bec 8938 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mbed_official 121:7f86b4238bec 8939 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mbed_official 121:7f86b4238bec 8940 } CHANNEL[4];
mbed_official 121:7f86b4238bec 8941 } PIT_Type;
mbed_official 121:7f86b4238bec 8942
mbed_official 121:7f86b4238bec 8943 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 8944 -- PIT Register Masks
mbed_official 121:7f86b4238bec 8945 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 8946
mbed_official 121:7f86b4238bec 8947 /*!
mbed_official 121:7f86b4238bec 8948 * @addtogroup PIT_Register_Masks PIT Register Masks
mbed_official 121:7f86b4238bec 8949 * @{
mbed_official 121:7f86b4238bec 8950 */
mbed_official 121:7f86b4238bec 8951
mbed_official 121:7f86b4238bec 8952 /*! @name MCR - PIT Module Control Register */
mbed_official 121:7f86b4238bec 8953 #define PIT_MCR_FRZ_MASK (0x1U)
mbed_official 121:7f86b4238bec 8954 #define PIT_MCR_FRZ_SHIFT (0U)
mbed_official 121:7f86b4238bec 8955 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
mbed_official 121:7f86b4238bec 8956 #define PIT_MCR_MDIS_MASK (0x2U)
mbed_official 121:7f86b4238bec 8957 #define PIT_MCR_MDIS_SHIFT (1U)
mbed_official 121:7f86b4238bec 8958 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
mbed_official 121:7f86b4238bec 8959
mbed_official 121:7f86b4238bec 8960 /*! @name LDVAL - Timer Load Value Register */
mbed_official 121:7f86b4238bec 8961 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 8962 #define PIT_LDVAL_TSV_SHIFT (0U)
mbed_official 121:7f86b4238bec 8963 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
mbed_official 121:7f86b4238bec 8964
mbed_official 121:7f86b4238bec 8965 /* The count of PIT_LDVAL */
mbed_official 121:7f86b4238bec 8966 #define PIT_LDVAL_COUNT (4U)
mbed_official 121:7f86b4238bec 8967
mbed_official 121:7f86b4238bec 8968 /*! @name CVAL - Current Timer Value Register */
mbed_official 121:7f86b4238bec 8969 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 8970 #define PIT_CVAL_TVL_SHIFT (0U)
mbed_official 121:7f86b4238bec 8971 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
mbed_official 121:7f86b4238bec 8972
mbed_official 121:7f86b4238bec 8973 /* The count of PIT_CVAL */
mbed_official 121:7f86b4238bec 8974 #define PIT_CVAL_COUNT (4U)
mbed_official 121:7f86b4238bec 8975
mbed_official 121:7f86b4238bec 8976 /*! @name TCTRL - Timer Control Register */
mbed_official 121:7f86b4238bec 8977 #define PIT_TCTRL_TEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 8978 #define PIT_TCTRL_TEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 8979 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
mbed_official 121:7f86b4238bec 8980 #define PIT_TCTRL_TIE_MASK (0x2U)
mbed_official 121:7f86b4238bec 8981 #define PIT_TCTRL_TIE_SHIFT (1U)
mbed_official 121:7f86b4238bec 8982 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
mbed_official 121:7f86b4238bec 8983 #define PIT_TCTRL_CHN_MASK (0x4U)
mbed_official 121:7f86b4238bec 8984 #define PIT_TCTRL_CHN_SHIFT (2U)
mbed_official 121:7f86b4238bec 8985 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
mbed_official 121:7f86b4238bec 8986
mbed_official 121:7f86b4238bec 8987 /* The count of PIT_TCTRL */
mbed_official 121:7f86b4238bec 8988 #define PIT_TCTRL_COUNT (4U)
mbed_official 121:7f86b4238bec 8989
mbed_official 121:7f86b4238bec 8990 /*! @name TFLG - Timer Flag Register */
mbed_official 121:7f86b4238bec 8991 #define PIT_TFLG_TIF_MASK (0x1U)
mbed_official 121:7f86b4238bec 8992 #define PIT_TFLG_TIF_SHIFT (0U)
mbed_official 121:7f86b4238bec 8993 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
mbed_official 121:7f86b4238bec 8994
mbed_official 121:7f86b4238bec 8995 /* The count of PIT_TFLG */
mbed_official 121:7f86b4238bec 8996 #define PIT_TFLG_COUNT (4U)
mbed_official 121:7f86b4238bec 8997
mbed_official 121:7f86b4238bec 8998
mbed_official 121:7f86b4238bec 8999 /*!
mbed_official 121:7f86b4238bec 9000 * @}
mbed_official 121:7f86b4238bec 9001 */ /* end of group PIT_Register_Masks */
mbed_official 121:7f86b4238bec 9002
mbed_official 121:7f86b4238bec 9003
mbed_official 121:7f86b4238bec 9004 /* PIT - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 9005 /** Peripheral PIT base address */
mbed_official 121:7f86b4238bec 9006 #define PIT_BASE (0x40037000u)
mbed_official 121:7f86b4238bec 9007 /** Peripheral PIT base pointer */
mbed_official 121:7f86b4238bec 9008 #define PIT ((PIT_Type *)PIT_BASE)
mbed_official 121:7f86b4238bec 9009 /** Array initializer of PIT peripheral base addresses */
mbed_official 121:7f86b4238bec 9010 #define PIT_BASE_ADDRS { PIT_BASE }
mbed_official 121:7f86b4238bec 9011 /** Array initializer of PIT peripheral base pointers */
mbed_official 121:7f86b4238bec 9012 #define PIT_BASE_PTRS { PIT }
mbed_official 121:7f86b4238bec 9013 /** Interrupt vectors for the PIT peripheral type */
mbed_official 121:7f86b4238bec 9014 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
mbed_official 121:7f86b4238bec 9015
mbed_official 121:7f86b4238bec 9016 /*!
mbed_official 121:7f86b4238bec 9017 * @}
mbed_official 121:7f86b4238bec 9018 */ /* end of group PIT_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 9019
mbed_official 121:7f86b4238bec 9020
mbed_official 121:7f86b4238bec 9021 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9022 -- PMC Peripheral Access Layer
mbed_official 121:7f86b4238bec 9023 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9024
mbed_official 121:7f86b4238bec 9025 /*!
mbed_official 121:7f86b4238bec 9026 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mbed_official 121:7f86b4238bec 9027 * @{
mbed_official 121:7f86b4238bec 9028 */
mbed_official 121:7f86b4238bec 9029
mbed_official 121:7f86b4238bec 9030 /** PMC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 9031 typedef struct {
mbed_official 121:7f86b4238bec 9032 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
mbed_official 121:7f86b4238bec 9033 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
mbed_official 121:7f86b4238bec 9034 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
mbed_official 121:7f86b4238bec 9035 } PMC_Type;
mbed_official 121:7f86b4238bec 9036
mbed_official 121:7f86b4238bec 9037 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9038 -- PMC Register Masks
mbed_official 121:7f86b4238bec 9039 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9040
mbed_official 121:7f86b4238bec 9041 /*!
mbed_official 121:7f86b4238bec 9042 * @addtogroup PMC_Register_Masks PMC Register Masks
mbed_official 121:7f86b4238bec 9043 * @{
mbed_official 121:7f86b4238bec 9044 */
mbed_official 121:7f86b4238bec 9045
mbed_official 121:7f86b4238bec 9046 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
mbed_official 121:7f86b4238bec 9047 #define PMC_LVDSC1_LVDV_MASK (0x3U)
mbed_official 121:7f86b4238bec 9048 #define PMC_LVDSC1_LVDV_SHIFT (0U)
mbed_official 121:7f86b4238bec 9049 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
mbed_official 121:7f86b4238bec 9050 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
mbed_official 121:7f86b4238bec 9051 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
mbed_official 121:7f86b4238bec 9052 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
mbed_official 121:7f86b4238bec 9053 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
mbed_official 121:7f86b4238bec 9054 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
mbed_official 121:7f86b4238bec 9055 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
mbed_official 121:7f86b4238bec 9056 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
mbed_official 121:7f86b4238bec 9057 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
mbed_official 121:7f86b4238bec 9058 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
mbed_official 121:7f86b4238bec 9059 #define PMC_LVDSC1_LVDF_MASK (0x80U)
mbed_official 121:7f86b4238bec 9060 #define PMC_LVDSC1_LVDF_SHIFT (7U)
mbed_official 121:7f86b4238bec 9061 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
mbed_official 121:7f86b4238bec 9062
mbed_official 121:7f86b4238bec 9063 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
mbed_official 121:7f86b4238bec 9064 #define PMC_LVDSC2_LVWV_MASK (0x3U)
mbed_official 121:7f86b4238bec 9065 #define PMC_LVDSC2_LVWV_SHIFT (0U)
mbed_official 121:7f86b4238bec 9066 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
mbed_official 121:7f86b4238bec 9067 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
mbed_official 121:7f86b4238bec 9068 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
mbed_official 121:7f86b4238bec 9069 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
mbed_official 121:7f86b4238bec 9070 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
mbed_official 121:7f86b4238bec 9071 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
mbed_official 121:7f86b4238bec 9072 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
mbed_official 121:7f86b4238bec 9073 #define PMC_LVDSC2_LVWF_MASK (0x80U)
mbed_official 121:7f86b4238bec 9074 #define PMC_LVDSC2_LVWF_SHIFT (7U)
mbed_official 121:7f86b4238bec 9075 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
mbed_official 121:7f86b4238bec 9076
mbed_official 121:7f86b4238bec 9077 /*! @name REGSC - Regulator Status And Control register */
mbed_official 121:7f86b4238bec 9078 #define PMC_REGSC_BGBE_MASK (0x1U)
mbed_official 121:7f86b4238bec 9079 #define PMC_REGSC_BGBE_SHIFT (0U)
mbed_official 121:7f86b4238bec 9080 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
mbed_official 121:7f86b4238bec 9081 #define PMC_REGSC_REGONS_MASK (0x4U)
mbed_official 121:7f86b4238bec 9082 #define PMC_REGSC_REGONS_SHIFT (2U)
mbed_official 121:7f86b4238bec 9083 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
mbed_official 121:7f86b4238bec 9084 #define PMC_REGSC_ACKISO_MASK (0x8U)
mbed_official 121:7f86b4238bec 9085 #define PMC_REGSC_ACKISO_SHIFT (3U)
mbed_official 121:7f86b4238bec 9086 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
mbed_official 121:7f86b4238bec 9087 #define PMC_REGSC_BGEN_MASK (0x10U)
mbed_official 121:7f86b4238bec 9088 #define PMC_REGSC_BGEN_SHIFT (4U)
mbed_official 121:7f86b4238bec 9089 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
mbed_official 121:7f86b4238bec 9090
mbed_official 121:7f86b4238bec 9091
mbed_official 121:7f86b4238bec 9092 /*!
mbed_official 121:7f86b4238bec 9093 * @}
mbed_official 121:7f86b4238bec 9094 */ /* end of group PMC_Register_Masks */
mbed_official 121:7f86b4238bec 9095
mbed_official 121:7f86b4238bec 9096
mbed_official 121:7f86b4238bec 9097 /* PMC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 9098 /** Peripheral PMC base address */
mbed_official 121:7f86b4238bec 9099 #define PMC_BASE (0x4007D000u)
mbed_official 121:7f86b4238bec 9100 /** Peripheral PMC base pointer */
mbed_official 121:7f86b4238bec 9101 #define PMC ((PMC_Type *)PMC_BASE)
mbed_official 121:7f86b4238bec 9102 /** Array initializer of PMC peripheral base addresses */
mbed_official 121:7f86b4238bec 9103 #define PMC_BASE_ADDRS { PMC_BASE }
mbed_official 121:7f86b4238bec 9104 /** Array initializer of PMC peripheral base pointers */
mbed_official 121:7f86b4238bec 9105 #define PMC_BASE_PTRS { PMC }
mbed_official 121:7f86b4238bec 9106 /** Interrupt vectors for the PMC peripheral type */
mbed_official 121:7f86b4238bec 9107 #define PMC_IRQS { LVD_LVW_IRQn }
mbed_official 121:7f86b4238bec 9108
mbed_official 121:7f86b4238bec 9109 /*!
mbed_official 121:7f86b4238bec 9110 * @}
mbed_official 121:7f86b4238bec 9111 */ /* end of group PMC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 9112
mbed_official 121:7f86b4238bec 9113
mbed_official 121:7f86b4238bec 9114 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9115 -- PORT Peripheral Access Layer
mbed_official 121:7f86b4238bec 9116 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9117
mbed_official 121:7f86b4238bec 9118 /*!
mbed_official 121:7f86b4238bec 9119 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mbed_official 121:7f86b4238bec 9120 * @{
mbed_official 121:7f86b4238bec 9121 */
mbed_official 121:7f86b4238bec 9122
mbed_official 121:7f86b4238bec 9123 /** PORT - Register Layout Typedef */
mbed_official 121:7f86b4238bec 9124 typedef struct {
mbed_official 121:7f86b4238bec 9125 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mbed_official 121:7f86b4238bec 9126 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mbed_official 121:7f86b4238bec 9127 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mbed_official 121:7f86b4238bec 9128 uint8_t RESERVED_0[24];
mbed_official 121:7f86b4238bec 9129 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mbed_official 121:7f86b4238bec 9130 uint8_t RESERVED_1[28];
mbed_official 121:7f86b4238bec 9131 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
mbed_official 121:7f86b4238bec 9132 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
mbed_official 121:7f86b4238bec 9133 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
mbed_official 121:7f86b4238bec 9134 } PORT_Type;
mbed_official 121:7f86b4238bec 9135
mbed_official 121:7f86b4238bec 9136 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9137 -- PORT Register Masks
mbed_official 121:7f86b4238bec 9138 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9139
mbed_official 121:7f86b4238bec 9140 /*!
mbed_official 121:7f86b4238bec 9141 * @addtogroup PORT_Register_Masks PORT Register Masks
mbed_official 121:7f86b4238bec 9142 * @{
mbed_official 121:7f86b4238bec 9143 */
mbed_official 121:7f86b4238bec 9144
mbed_official 121:7f86b4238bec 9145 /*! @name PCR - Pin Control Register n */
mbed_official 121:7f86b4238bec 9146 #define PORT_PCR_PS_MASK (0x1U)
mbed_official 121:7f86b4238bec 9147 #define PORT_PCR_PS_SHIFT (0U)
mbed_official 121:7f86b4238bec 9148 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
mbed_official 121:7f86b4238bec 9149 #define PORT_PCR_PE_MASK (0x2U)
mbed_official 121:7f86b4238bec 9150 #define PORT_PCR_PE_SHIFT (1U)
mbed_official 121:7f86b4238bec 9151 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
mbed_official 121:7f86b4238bec 9152 #define PORT_PCR_SRE_MASK (0x4U)
mbed_official 121:7f86b4238bec 9153 #define PORT_PCR_SRE_SHIFT (2U)
mbed_official 121:7f86b4238bec 9154 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
mbed_official 121:7f86b4238bec 9155 #define PORT_PCR_PFE_MASK (0x10U)
mbed_official 121:7f86b4238bec 9156 #define PORT_PCR_PFE_SHIFT (4U)
mbed_official 121:7f86b4238bec 9157 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
mbed_official 121:7f86b4238bec 9158 #define PORT_PCR_ODE_MASK (0x20U)
mbed_official 121:7f86b4238bec 9159 #define PORT_PCR_ODE_SHIFT (5U)
mbed_official 121:7f86b4238bec 9160 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
mbed_official 121:7f86b4238bec 9161 #define PORT_PCR_DSE_MASK (0x40U)
mbed_official 121:7f86b4238bec 9162 #define PORT_PCR_DSE_SHIFT (6U)
mbed_official 121:7f86b4238bec 9163 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
mbed_official 121:7f86b4238bec 9164 #define PORT_PCR_MUX_MASK (0x700U)
mbed_official 121:7f86b4238bec 9165 #define PORT_PCR_MUX_SHIFT (8U)
mbed_official 121:7f86b4238bec 9166 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
mbed_official 121:7f86b4238bec 9167 #define PORT_PCR_LK_MASK (0x8000U)
mbed_official 121:7f86b4238bec 9168 #define PORT_PCR_LK_SHIFT (15U)
mbed_official 121:7f86b4238bec 9169 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
mbed_official 121:7f86b4238bec 9170 #define PORT_PCR_IRQC_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 9171 #define PORT_PCR_IRQC_SHIFT (16U)
mbed_official 121:7f86b4238bec 9172 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
mbed_official 121:7f86b4238bec 9173 #define PORT_PCR_ISF_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 9174 #define PORT_PCR_ISF_SHIFT (24U)
mbed_official 121:7f86b4238bec 9175 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
mbed_official 121:7f86b4238bec 9176
mbed_official 121:7f86b4238bec 9177 /* The count of PORT_PCR */
mbed_official 121:7f86b4238bec 9178 #define PORT_PCR_COUNT (32U)
mbed_official 121:7f86b4238bec 9179
mbed_official 121:7f86b4238bec 9180 /*! @name GPCLR - Global Pin Control Low Register */
mbed_official 121:7f86b4238bec 9181 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 9182 #define PORT_GPCLR_GPWD_SHIFT (0U)
mbed_official 121:7f86b4238bec 9183 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
mbed_official 121:7f86b4238bec 9184 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 9185 #define PORT_GPCLR_GPWE_SHIFT (16U)
mbed_official 121:7f86b4238bec 9186 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
mbed_official 121:7f86b4238bec 9187
mbed_official 121:7f86b4238bec 9188 /*! @name GPCHR - Global Pin Control High Register */
mbed_official 121:7f86b4238bec 9189 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 9190 #define PORT_GPCHR_GPWD_SHIFT (0U)
mbed_official 121:7f86b4238bec 9191 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
mbed_official 121:7f86b4238bec 9192 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 9193 #define PORT_GPCHR_GPWE_SHIFT (16U)
mbed_official 121:7f86b4238bec 9194 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
mbed_official 121:7f86b4238bec 9195
mbed_official 121:7f86b4238bec 9196 /*! @name ISFR - Interrupt Status Flag Register */
mbed_official 121:7f86b4238bec 9197 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9198 #define PORT_ISFR_ISF_SHIFT (0U)
mbed_official 121:7f86b4238bec 9199 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
mbed_official 121:7f86b4238bec 9200
mbed_official 121:7f86b4238bec 9201 /*! @name DFER - Digital Filter Enable Register */
mbed_official 121:7f86b4238bec 9202 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9203 #define PORT_DFER_DFE_SHIFT (0U)
mbed_official 121:7f86b4238bec 9204 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
mbed_official 121:7f86b4238bec 9205
mbed_official 121:7f86b4238bec 9206 /*! @name DFCR - Digital Filter Clock Register */
mbed_official 121:7f86b4238bec 9207 #define PORT_DFCR_CS_MASK (0x1U)
mbed_official 121:7f86b4238bec 9208 #define PORT_DFCR_CS_SHIFT (0U)
mbed_official 121:7f86b4238bec 9209 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
mbed_official 121:7f86b4238bec 9210
mbed_official 121:7f86b4238bec 9211 /*! @name DFWR - Digital Filter Width Register */
mbed_official 121:7f86b4238bec 9212 #define PORT_DFWR_FILT_MASK (0x1FU)
mbed_official 121:7f86b4238bec 9213 #define PORT_DFWR_FILT_SHIFT (0U)
mbed_official 121:7f86b4238bec 9214 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
mbed_official 121:7f86b4238bec 9215
mbed_official 121:7f86b4238bec 9216
mbed_official 121:7f86b4238bec 9217 /*!
mbed_official 121:7f86b4238bec 9218 * @}
mbed_official 121:7f86b4238bec 9219 */ /* end of group PORT_Register_Masks */
mbed_official 121:7f86b4238bec 9220
mbed_official 121:7f86b4238bec 9221
mbed_official 121:7f86b4238bec 9222 /* PORT - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 9223 /** Peripheral PORTA base address */
mbed_official 121:7f86b4238bec 9224 #define PORTA_BASE (0x40049000u)
mbed_official 121:7f86b4238bec 9225 /** Peripheral PORTA base pointer */
mbed_official 121:7f86b4238bec 9226 #define PORTA ((PORT_Type *)PORTA_BASE)
mbed_official 121:7f86b4238bec 9227 /** Peripheral PORTB base address */
mbed_official 121:7f86b4238bec 9228 #define PORTB_BASE (0x4004A000u)
mbed_official 121:7f86b4238bec 9229 /** Peripheral PORTB base pointer */
mbed_official 121:7f86b4238bec 9230 #define PORTB ((PORT_Type *)PORTB_BASE)
mbed_official 121:7f86b4238bec 9231 /** Peripheral PORTC base address */
mbed_official 121:7f86b4238bec 9232 #define PORTC_BASE (0x4004B000u)
mbed_official 121:7f86b4238bec 9233 /** Peripheral PORTC base pointer */
mbed_official 121:7f86b4238bec 9234 #define PORTC ((PORT_Type *)PORTC_BASE)
mbed_official 121:7f86b4238bec 9235 /** Peripheral PORTD base address */
mbed_official 121:7f86b4238bec 9236 #define PORTD_BASE (0x4004C000u)
mbed_official 121:7f86b4238bec 9237 /** Peripheral PORTD base pointer */
mbed_official 121:7f86b4238bec 9238 #define PORTD ((PORT_Type *)PORTD_BASE)
mbed_official 121:7f86b4238bec 9239 /** Peripheral PORTE base address */
mbed_official 121:7f86b4238bec 9240 #define PORTE_BASE (0x4004D000u)
mbed_official 121:7f86b4238bec 9241 /** Peripheral PORTE base pointer */
mbed_official 121:7f86b4238bec 9242 #define PORTE ((PORT_Type *)PORTE_BASE)
mbed_official 121:7f86b4238bec 9243 /** Array initializer of PORT peripheral base addresses */
mbed_official 121:7f86b4238bec 9244 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
mbed_official 121:7f86b4238bec 9245 /** Array initializer of PORT peripheral base pointers */
mbed_official 121:7f86b4238bec 9246 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
mbed_official 121:7f86b4238bec 9247 /** Interrupt vectors for the PORT peripheral type */
mbed_official 121:7f86b4238bec 9248 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
mbed_official 121:7f86b4238bec 9249
mbed_official 121:7f86b4238bec 9250 /*!
mbed_official 121:7f86b4238bec 9251 * @}
mbed_official 121:7f86b4238bec 9252 */ /* end of group PORT_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 9253
mbed_official 121:7f86b4238bec 9254
mbed_official 121:7f86b4238bec 9255 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9256 -- RCM Peripheral Access Layer
mbed_official 121:7f86b4238bec 9257 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9258
mbed_official 121:7f86b4238bec 9259 /*!
mbed_official 121:7f86b4238bec 9260 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mbed_official 121:7f86b4238bec 9261 * @{
mbed_official 121:7f86b4238bec 9262 */
mbed_official 121:7f86b4238bec 9263
mbed_official 121:7f86b4238bec 9264 /** RCM - Register Layout Typedef */
mbed_official 121:7f86b4238bec 9265 typedef struct {
mbed_official 121:7f86b4238bec 9266 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mbed_official 121:7f86b4238bec 9267 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mbed_official 121:7f86b4238bec 9268 uint8_t RESERVED_0[2];
mbed_official 121:7f86b4238bec 9269 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
mbed_official 121:7f86b4238bec 9270 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
mbed_official 121:7f86b4238bec 9271 uint8_t RESERVED_1[1];
mbed_official 121:7f86b4238bec 9272 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
mbed_official 121:7f86b4238bec 9273 } RCM_Type;
mbed_official 121:7f86b4238bec 9274
mbed_official 121:7f86b4238bec 9275 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9276 -- RCM Register Masks
mbed_official 121:7f86b4238bec 9277 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9278
mbed_official 121:7f86b4238bec 9279 /*!
mbed_official 121:7f86b4238bec 9280 * @addtogroup RCM_Register_Masks RCM Register Masks
mbed_official 121:7f86b4238bec 9281 * @{
mbed_official 121:7f86b4238bec 9282 */
mbed_official 121:7f86b4238bec 9283
mbed_official 121:7f86b4238bec 9284 /*! @name SRS0 - System Reset Status Register 0 */
mbed_official 121:7f86b4238bec 9285 #define RCM_SRS0_WAKEUP_MASK (0x1U)
mbed_official 121:7f86b4238bec 9286 #define RCM_SRS0_WAKEUP_SHIFT (0U)
mbed_official 121:7f86b4238bec 9287 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
mbed_official 121:7f86b4238bec 9288 #define RCM_SRS0_LVD_MASK (0x2U)
mbed_official 121:7f86b4238bec 9289 #define RCM_SRS0_LVD_SHIFT (1U)
mbed_official 121:7f86b4238bec 9290 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
mbed_official 121:7f86b4238bec 9291 #define RCM_SRS0_LOC_MASK (0x4U)
mbed_official 121:7f86b4238bec 9292 #define RCM_SRS0_LOC_SHIFT (2U)
mbed_official 121:7f86b4238bec 9293 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
mbed_official 121:7f86b4238bec 9294 #define RCM_SRS0_LOL_MASK (0x8U)
mbed_official 121:7f86b4238bec 9295 #define RCM_SRS0_LOL_SHIFT (3U)
mbed_official 121:7f86b4238bec 9296 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
mbed_official 121:7f86b4238bec 9297 #define RCM_SRS0_WDOG_MASK (0x20U)
mbed_official 121:7f86b4238bec 9298 #define RCM_SRS0_WDOG_SHIFT (5U)
mbed_official 121:7f86b4238bec 9299 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
mbed_official 121:7f86b4238bec 9300 #define RCM_SRS0_PIN_MASK (0x40U)
mbed_official 121:7f86b4238bec 9301 #define RCM_SRS0_PIN_SHIFT (6U)
mbed_official 121:7f86b4238bec 9302 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
mbed_official 121:7f86b4238bec 9303 #define RCM_SRS0_POR_MASK (0x80U)
mbed_official 121:7f86b4238bec 9304 #define RCM_SRS0_POR_SHIFT (7U)
mbed_official 121:7f86b4238bec 9305 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
mbed_official 121:7f86b4238bec 9306
mbed_official 121:7f86b4238bec 9307 /*! @name SRS1 - System Reset Status Register 1 */
mbed_official 121:7f86b4238bec 9308 #define RCM_SRS1_JTAG_MASK (0x1U)
mbed_official 121:7f86b4238bec 9309 #define RCM_SRS1_JTAG_SHIFT (0U)
mbed_official 121:7f86b4238bec 9310 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
mbed_official 121:7f86b4238bec 9311 #define RCM_SRS1_LOCKUP_MASK (0x2U)
mbed_official 121:7f86b4238bec 9312 #define RCM_SRS1_LOCKUP_SHIFT (1U)
mbed_official 121:7f86b4238bec 9313 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
mbed_official 121:7f86b4238bec 9314 #define RCM_SRS1_SW_MASK (0x4U)
mbed_official 121:7f86b4238bec 9315 #define RCM_SRS1_SW_SHIFT (2U)
mbed_official 121:7f86b4238bec 9316 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
mbed_official 121:7f86b4238bec 9317 #define RCM_SRS1_MDM_AP_MASK (0x8U)
mbed_official 121:7f86b4238bec 9318 #define RCM_SRS1_MDM_AP_SHIFT (3U)
mbed_official 121:7f86b4238bec 9319 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
mbed_official 121:7f86b4238bec 9320 #define RCM_SRS1_EZPT_MASK (0x10U)
mbed_official 121:7f86b4238bec 9321 #define RCM_SRS1_EZPT_SHIFT (4U)
mbed_official 121:7f86b4238bec 9322 #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
mbed_official 121:7f86b4238bec 9323 #define RCM_SRS1_SACKERR_MASK (0x20U)
mbed_official 121:7f86b4238bec 9324 #define RCM_SRS1_SACKERR_SHIFT (5U)
mbed_official 121:7f86b4238bec 9325 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
mbed_official 121:7f86b4238bec 9326
mbed_official 121:7f86b4238bec 9327 /*! @name RPFC - Reset Pin Filter Control register */
mbed_official 121:7f86b4238bec 9328 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
mbed_official 121:7f86b4238bec 9329 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
mbed_official 121:7f86b4238bec 9330 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
mbed_official 121:7f86b4238bec 9331 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
mbed_official 121:7f86b4238bec 9332 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
mbed_official 121:7f86b4238bec 9333 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
mbed_official 121:7f86b4238bec 9334
mbed_official 121:7f86b4238bec 9335 /*! @name RPFW - Reset Pin Filter Width register */
mbed_official 121:7f86b4238bec 9336 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
mbed_official 121:7f86b4238bec 9337 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 9338 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
mbed_official 121:7f86b4238bec 9339
mbed_official 121:7f86b4238bec 9340 /*! @name MR - Mode Register */
mbed_official 121:7f86b4238bec 9341 #define RCM_MR_EZP_MS_MASK (0x2U)
mbed_official 121:7f86b4238bec 9342 #define RCM_MR_EZP_MS_SHIFT (1U)
mbed_official 121:7f86b4238bec 9343 #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
mbed_official 121:7f86b4238bec 9344
mbed_official 121:7f86b4238bec 9345
mbed_official 121:7f86b4238bec 9346 /*!
mbed_official 121:7f86b4238bec 9347 * @}
mbed_official 121:7f86b4238bec 9348 */ /* end of group RCM_Register_Masks */
mbed_official 121:7f86b4238bec 9349
mbed_official 121:7f86b4238bec 9350
mbed_official 121:7f86b4238bec 9351 /* RCM - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 9352 /** Peripheral RCM base address */
mbed_official 121:7f86b4238bec 9353 #define RCM_BASE (0x4007F000u)
mbed_official 121:7f86b4238bec 9354 /** Peripheral RCM base pointer */
mbed_official 121:7f86b4238bec 9355 #define RCM ((RCM_Type *)RCM_BASE)
mbed_official 121:7f86b4238bec 9356 /** Array initializer of RCM peripheral base addresses */
mbed_official 121:7f86b4238bec 9357 #define RCM_BASE_ADDRS { RCM_BASE }
mbed_official 121:7f86b4238bec 9358 /** Array initializer of RCM peripheral base pointers */
mbed_official 121:7f86b4238bec 9359 #define RCM_BASE_PTRS { RCM }
mbed_official 121:7f86b4238bec 9360
mbed_official 121:7f86b4238bec 9361 /*!
mbed_official 121:7f86b4238bec 9362 * @}
mbed_official 121:7f86b4238bec 9363 */ /* end of group RCM_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 9364
mbed_official 121:7f86b4238bec 9365
mbed_official 121:7f86b4238bec 9366 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9367 -- RFSYS Peripheral Access Layer
mbed_official 121:7f86b4238bec 9368 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9369
mbed_official 121:7f86b4238bec 9370 /*!
mbed_official 121:7f86b4238bec 9371 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
mbed_official 121:7f86b4238bec 9372 * @{
mbed_official 121:7f86b4238bec 9373 */
mbed_official 121:7f86b4238bec 9374
mbed_official 121:7f86b4238bec 9375 /** RFSYS - Register Layout Typedef */
mbed_official 121:7f86b4238bec 9376 typedef struct {
mbed_official 121:7f86b4238bec 9377 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
mbed_official 121:7f86b4238bec 9378 } RFSYS_Type;
mbed_official 121:7f86b4238bec 9379
mbed_official 121:7f86b4238bec 9380 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9381 -- RFSYS Register Masks
mbed_official 121:7f86b4238bec 9382 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9383
mbed_official 121:7f86b4238bec 9384 /*!
mbed_official 121:7f86b4238bec 9385 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
mbed_official 121:7f86b4238bec 9386 * @{
mbed_official 121:7f86b4238bec 9387 */
mbed_official 121:7f86b4238bec 9388
mbed_official 121:7f86b4238bec 9389 /*! @name REG - Register file register */
mbed_official 121:7f86b4238bec 9390 #define RFSYS_REG_LL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 9391 #define RFSYS_REG_LL_SHIFT (0U)
mbed_official 121:7f86b4238bec 9392 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
mbed_official 121:7f86b4238bec 9393 #define RFSYS_REG_LH_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 9394 #define RFSYS_REG_LH_SHIFT (8U)
mbed_official 121:7f86b4238bec 9395 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
mbed_official 121:7f86b4238bec 9396 #define RFSYS_REG_HL_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 9397 #define RFSYS_REG_HL_SHIFT (16U)
mbed_official 121:7f86b4238bec 9398 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
mbed_official 121:7f86b4238bec 9399 #define RFSYS_REG_HH_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 9400 #define RFSYS_REG_HH_SHIFT (24U)
mbed_official 121:7f86b4238bec 9401 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
mbed_official 121:7f86b4238bec 9402
mbed_official 121:7f86b4238bec 9403 /* The count of RFSYS_REG */
mbed_official 121:7f86b4238bec 9404 #define RFSYS_REG_COUNT (8U)
mbed_official 121:7f86b4238bec 9405
mbed_official 121:7f86b4238bec 9406
mbed_official 121:7f86b4238bec 9407 /*!
mbed_official 121:7f86b4238bec 9408 * @}
mbed_official 121:7f86b4238bec 9409 */ /* end of group RFSYS_Register_Masks */
mbed_official 121:7f86b4238bec 9410
mbed_official 121:7f86b4238bec 9411
mbed_official 121:7f86b4238bec 9412 /* RFSYS - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 9413 /** Peripheral RFSYS base address */
mbed_official 121:7f86b4238bec 9414 #define RFSYS_BASE (0x40041000u)
mbed_official 121:7f86b4238bec 9415 /** Peripheral RFSYS base pointer */
mbed_official 121:7f86b4238bec 9416 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
mbed_official 121:7f86b4238bec 9417 /** Array initializer of RFSYS peripheral base addresses */
mbed_official 121:7f86b4238bec 9418 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
mbed_official 121:7f86b4238bec 9419 /** Array initializer of RFSYS peripheral base pointers */
mbed_official 121:7f86b4238bec 9420 #define RFSYS_BASE_PTRS { RFSYS }
mbed_official 121:7f86b4238bec 9421
mbed_official 121:7f86b4238bec 9422 /*!
mbed_official 121:7f86b4238bec 9423 * @}
mbed_official 121:7f86b4238bec 9424 */ /* end of group RFSYS_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 9425
mbed_official 121:7f86b4238bec 9426
mbed_official 121:7f86b4238bec 9427 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9428 -- RFVBAT Peripheral Access Layer
mbed_official 121:7f86b4238bec 9429 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9430
mbed_official 121:7f86b4238bec 9431 /*!
mbed_official 121:7f86b4238bec 9432 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
mbed_official 121:7f86b4238bec 9433 * @{
mbed_official 121:7f86b4238bec 9434 */
mbed_official 121:7f86b4238bec 9435
mbed_official 121:7f86b4238bec 9436 /** RFVBAT - Register Layout Typedef */
mbed_official 121:7f86b4238bec 9437 typedef struct {
mbed_official 121:7f86b4238bec 9438 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
mbed_official 121:7f86b4238bec 9439 } RFVBAT_Type;
mbed_official 121:7f86b4238bec 9440
mbed_official 121:7f86b4238bec 9441 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9442 -- RFVBAT Register Masks
mbed_official 121:7f86b4238bec 9443 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9444
mbed_official 121:7f86b4238bec 9445 /*!
mbed_official 121:7f86b4238bec 9446 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
mbed_official 121:7f86b4238bec 9447 * @{
mbed_official 121:7f86b4238bec 9448 */
mbed_official 121:7f86b4238bec 9449
mbed_official 121:7f86b4238bec 9450 /*! @name REG - VBAT register file register */
mbed_official 121:7f86b4238bec 9451 #define RFVBAT_REG_LL_MASK (0xFFU)
mbed_official 121:7f86b4238bec 9452 #define RFVBAT_REG_LL_SHIFT (0U)
mbed_official 121:7f86b4238bec 9453 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
mbed_official 121:7f86b4238bec 9454 #define RFVBAT_REG_LH_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 9455 #define RFVBAT_REG_LH_SHIFT (8U)
mbed_official 121:7f86b4238bec 9456 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
mbed_official 121:7f86b4238bec 9457 #define RFVBAT_REG_HL_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 9458 #define RFVBAT_REG_HL_SHIFT (16U)
mbed_official 121:7f86b4238bec 9459 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
mbed_official 121:7f86b4238bec 9460 #define RFVBAT_REG_HH_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 9461 #define RFVBAT_REG_HH_SHIFT (24U)
mbed_official 121:7f86b4238bec 9462 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
mbed_official 121:7f86b4238bec 9463
mbed_official 121:7f86b4238bec 9464 /* The count of RFVBAT_REG */
mbed_official 121:7f86b4238bec 9465 #define RFVBAT_REG_COUNT (8U)
mbed_official 121:7f86b4238bec 9466
mbed_official 121:7f86b4238bec 9467
mbed_official 121:7f86b4238bec 9468 /*!
mbed_official 121:7f86b4238bec 9469 * @}
mbed_official 121:7f86b4238bec 9470 */ /* end of group RFVBAT_Register_Masks */
mbed_official 121:7f86b4238bec 9471
mbed_official 121:7f86b4238bec 9472
mbed_official 121:7f86b4238bec 9473 /* RFVBAT - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 9474 /** Peripheral RFVBAT base address */
mbed_official 121:7f86b4238bec 9475 #define RFVBAT_BASE (0x4003E000u)
mbed_official 121:7f86b4238bec 9476 /** Peripheral RFVBAT base pointer */
mbed_official 121:7f86b4238bec 9477 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
mbed_official 121:7f86b4238bec 9478 /** Array initializer of RFVBAT peripheral base addresses */
mbed_official 121:7f86b4238bec 9479 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
mbed_official 121:7f86b4238bec 9480 /** Array initializer of RFVBAT peripheral base pointers */
mbed_official 121:7f86b4238bec 9481 #define RFVBAT_BASE_PTRS { RFVBAT }
mbed_official 121:7f86b4238bec 9482
mbed_official 121:7f86b4238bec 9483 /*!
mbed_official 121:7f86b4238bec 9484 * @}
mbed_official 121:7f86b4238bec 9485 */ /* end of group RFVBAT_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 9486
mbed_official 121:7f86b4238bec 9487
mbed_official 121:7f86b4238bec 9488 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9489 -- RNG Peripheral Access Layer
mbed_official 121:7f86b4238bec 9490 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9491
mbed_official 121:7f86b4238bec 9492 /*!
mbed_official 121:7f86b4238bec 9493 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
mbed_official 121:7f86b4238bec 9494 * @{
mbed_official 121:7f86b4238bec 9495 */
mbed_official 121:7f86b4238bec 9496
mbed_official 121:7f86b4238bec 9497 /** RNG - Register Layout Typedef */
mbed_official 121:7f86b4238bec 9498 typedef struct {
mbed_official 121:7f86b4238bec 9499 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 9500 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 9501 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 9502 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
mbed_official 121:7f86b4238bec 9503 } RNG_Type;
mbed_official 121:7f86b4238bec 9504
mbed_official 121:7f86b4238bec 9505 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9506 -- RNG Register Masks
mbed_official 121:7f86b4238bec 9507 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9508
mbed_official 121:7f86b4238bec 9509 /*!
mbed_official 121:7f86b4238bec 9510 * @addtogroup RNG_Register_Masks RNG Register Masks
mbed_official 121:7f86b4238bec 9511 * @{
mbed_official 121:7f86b4238bec 9512 */
mbed_official 121:7f86b4238bec 9513
mbed_official 121:7f86b4238bec 9514 /*! @name CR - RNGA Control Register */
mbed_official 121:7f86b4238bec 9515 #define RNG_CR_GO_MASK (0x1U)
mbed_official 121:7f86b4238bec 9516 #define RNG_CR_GO_SHIFT (0U)
mbed_official 121:7f86b4238bec 9517 #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
mbed_official 121:7f86b4238bec 9518 #define RNG_CR_HA_MASK (0x2U)
mbed_official 121:7f86b4238bec 9519 #define RNG_CR_HA_SHIFT (1U)
mbed_official 121:7f86b4238bec 9520 #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
mbed_official 121:7f86b4238bec 9521 #define RNG_CR_INTM_MASK (0x4U)
mbed_official 121:7f86b4238bec 9522 #define RNG_CR_INTM_SHIFT (2U)
mbed_official 121:7f86b4238bec 9523 #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
mbed_official 121:7f86b4238bec 9524 #define RNG_CR_CLRI_MASK (0x8U)
mbed_official 121:7f86b4238bec 9525 #define RNG_CR_CLRI_SHIFT (3U)
mbed_official 121:7f86b4238bec 9526 #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
mbed_official 121:7f86b4238bec 9527 #define RNG_CR_SLP_MASK (0x10U)
mbed_official 121:7f86b4238bec 9528 #define RNG_CR_SLP_SHIFT (4U)
mbed_official 121:7f86b4238bec 9529 #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
mbed_official 121:7f86b4238bec 9530
mbed_official 121:7f86b4238bec 9531 /*! @name SR - RNGA Status Register */
mbed_official 121:7f86b4238bec 9532 #define RNG_SR_SECV_MASK (0x1U)
mbed_official 121:7f86b4238bec 9533 #define RNG_SR_SECV_SHIFT (0U)
mbed_official 121:7f86b4238bec 9534 #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
mbed_official 121:7f86b4238bec 9535 #define RNG_SR_LRS_MASK (0x2U)
mbed_official 121:7f86b4238bec 9536 #define RNG_SR_LRS_SHIFT (1U)
mbed_official 121:7f86b4238bec 9537 #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
mbed_official 121:7f86b4238bec 9538 #define RNG_SR_ORU_MASK (0x4U)
mbed_official 121:7f86b4238bec 9539 #define RNG_SR_ORU_SHIFT (2U)
mbed_official 121:7f86b4238bec 9540 #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
mbed_official 121:7f86b4238bec 9541 #define RNG_SR_ERRI_MASK (0x8U)
mbed_official 121:7f86b4238bec 9542 #define RNG_SR_ERRI_SHIFT (3U)
mbed_official 121:7f86b4238bec 9543 #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
mbed_official 121:7f86b4238bec 9544 #define RNG_SR_SLP_MASK (0x10U)
mbed_official 121:7f86b4238bec 9545 #define RNG_SR_SLP_SHIFT (4U)
mbed_official 121:7f86b4238bec 9546 #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
mbed_official 121:7f86b4238bec 9547 #define RNG_SR_OREG_LVL_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 9548 #define RNG_SR_OREG_LVL_SHIFT (8U)
mbed_official 121:7f86b4238bec 9549 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
mbed_official 121:7f86b4238bec 9550 #define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 9551 #define RNG_SR_OREG_SIZE_SHIFT (16U)
mbed_official 121:7f86b4238bec 9552 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
mbed_official 121:7f86b4238bec 9553
mbed_official 121:7f86b4238bec 9554 /*! @name ER - RNGA Entropy Register */
mbed_official 121:7f86b4238bec 9555 #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9556 #define RNG_ER_EXT_ENT_SHIFT (0U)
mbed_official 121:7f86b4238bec 9557 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
mbed_official 121:7f86b4238bec 9558
mbed_official 121:7f86b4238bec 9559 /*! @name OR - RNGA Output Register */
mbed_official 121:7f86b4238bec 9560 #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9561 #define RNG_OR_RANDOUT_SHIFT (0U)
mbed_official 121:7f86b4238bec 9562 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
mbed_official 121:7f86b4238bec 9563
mbed_official 121:7f86b4238bec 9564
mbed_official 121:7f86b4238bec 9565 /*!
mbed_official 121:7f86b4238bec 9566 * @}
mbed_official 121:7f86b4238bec 9567 */ /* end of group RNG_Register_Masks */
mbed_official 121:7f86b4238bec 9568
mbed_official 121:7f86b4238bec 9569
mbed_official 121:7f86b4238bec 9570 /* RNG - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 9571 /** Peripheral RNG base address */
mbed_official 121:7f86b4238bec 9572 #define RNG_BASE (0x40029000u)
mbed_official 121:7f86b4238bec 9573 /** Peripheral RNG base pointer */
mbed_official 121:7f86b4238bec 9574 #define RNG ((RNG_Type *)RNG_BASE)
mbed_official 121:7f86b4238bec 9575 /** Array initializer of RNG peripheral base addresses */
mbed_official 121:7f86b4238bec 9576 #define RNG_BASE_ADDRS { RNG_BASE }
mbed_official 121:7f86b4238bec 9577 /** Array initializer of RNG peripheral base pointers */
mbed_official 121:7f86b4238bec 9578 #define RNG_BASE_PTRS { RNG }
mbed_official 121:7f86b4238bec 9579 /** Interrupt vectors for the RNG peripheral type */
mbed_official 121:7f86b4238bec 9580 #define RNG_IRQS { RNG_IRQn }
mbed_official 121:7f86b4238bec 9581
mbed_official 121:7f86b4238bec 9582 /*!
mbed_official 121:7f86b4238bec 9583 * @}
mbed_official 121:7f86b4238bec 9584 */ /* end of group RNG_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 9585
mbed_official 121:7f86b4238bec 9586
mbed_official 121:7f86b4238bec 9587 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9588 -- RTC Peripheral Access Layer
mbed_official 121:7f86b4238bec 9589 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9590
mbed_official 121:7f86b4238bec 9591 /*!
mbed_official 121:7f86b4238bec 9592 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mbed_official 121:7f86b4238bec 9593 * @{
mbed_official 121:7f86b4238bec 9594 */
mbed_official 121:7f86b4238bec 9595
mbed_official 121:7f86b4238bec 9596 /** RTC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 9597 typedef struct {
mbed_official 121:7f86b4238bec 9598 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 9599 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 9600 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 9601 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mbed_official 121:7f86b4238bec 9602 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mbed_official 121:7f86b4238bec 9603 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mbed_official 121:7f86b4238bec 9604 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mbed_official 121:7f86b4238bec 9605 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mbed_official 121:7f86b4238bec 9606 uint8_t RESERVED_0[2016];
mbed_official 121:7f86b4238bec 9607 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
mbed_official 121:7f86b4238bec 9608 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
mbed_official 121:7f86b4238bec 9609 } RTC_Type;
mbed_official 121:7f86b4238bec 9610
mbed_official 121:7f86b4238bec 9611 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9612 -- RTC Register Masks
mbed_official 121:7f86b4238bec 9613 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9614
mbed_official 121:7f86b4238bec 9615 /*!
mbed_official 121:7f86b4238bec 9616 * @addtogroup RTC_Register_Masks RTC Register Masks
mbed_official 121:7f86b4238bec 9617 * @{
mbed_official 121:7f86b4238bec 9618 */
mbed_official 121:7f86b4238bec 9619
mbed_official 121:7f86b4238bec 9620 /*! @name TSR - RTC Time Seconds Register */
mbed_official 121:7f86b4238bec 9621 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9622 #define RTC_TSR_TSR_SHIFT (0U)
mbed_official 121:7f86b4238bec 9623 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
mbed_official 121:7f86b4238bec 9624
mbed_official 121:7f86b4238bec 9625 /*! @name TPR - RTC Time Prescaler Register */
mbed_official 121:7f86b4238bec 9626 #define RTC_TPR_TPR_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 9627 #define RTC_TPR_TPR_SHIFT (0U)
mbed_official 121:7f86b4238bec 9628 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
mbed_official 121:7f86b4238bec 9629
mbed_official 121:7f86b4238bec 9630 /*! @name TAR - RTC Time Alarm Register */
mbed_official 121:7f86b4238bec 9631 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9632 #define RTC_TAR_TAR_SHIFT (0U)
mbed_official 121:7f86b4238bec 9633 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
mbed_official 121:7f86b4238bec 9634
mbed_official 121:7f86b4238bec 9635 /*! @name TCR - RTC Time Compensation Register */
mbed_official 121:7f86b4238bec 9636 #define RTC_TCR_TCR_MASK (0xFFU)
mbed_official 121:7f86b4238bec 9637 #define RTC_TCR_TCR_SHIFT (0U)
mbed_official 121:7f86b4238bec 9638 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
mbed_official 121:7f86b4238bec 9639 #define RTC_TCR_CIR_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 9640 #define RTC_TCR_CIR_SHIFT (8U)
mbed_official 121:7f86b4238bec 9641 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
mbed_official 121:7f86b4238bec 9642 #define RTC_TCR_TCV_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 9643 #define RTC_TCR_TCV_SHIFT (16U)
mbed_official 121:7f86b4238bec 9644 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
mbed_official 121:7f86b4238bec 9645 #define RTC_TCR_CIC_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 9646 #define RTC_TCR_CIC_SHIFT (24U)
mbed_official 121:7f86b4238bec 9647 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
mbed_official 121:7f86b4238bec 9648
mbed_official 121:7f86b4238bec 9649 /*! @name CR - RTC Control Register */
mbed_official 121:7f86b4238bec 9650 #define RTC_CR_SWR_MASK (0x1U)
mbed_official 121:7f86b4238bec 9651 #define RTC_CR_SWR_SHIFT (0U)
mbed_official 121:7f86b4238bec 9652 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
mbed_official 121:7f86b4238bec 9653 #define RTC_CR_WPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 9654 #define RTC_CR_WPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 9655 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
mbed_official 121:7f86b4238bec 9656 #define RTC_CR_SUP_MASK (0x4U)
mbed_official 121:7f86b4238bec 9657 #define RTC_CR_SUP_SHIFT (2U)
mbed_official 121:7f86b4238bec 9658 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
mbed_official 121:7f86b4238bec 9659 #define RTC_CR_UM_MASK (0x8U)
mbed_official 121:7f86b4238bec 9660 #define RTC_CR_UM_SHIFT (3U)
mbed_official 121:7f86b4238bec 9661 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
mbed_official 121:7f86b4238bec 9662 #define RTC_CR_WPS_MASK (0x10U)
mbed_official 121:7f86b4238bec 9663 #define RTC_CR_WPS_SHIFT (4U)
mbed_official 121:7f86b4238bec 9664 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
mbed_official 121:7f86b4238bec 9665 #define RTC_CR_OSCE_MASK (0x100U)
mbed_official 121:7f86b4238bec 9666 #define RTC_CR_OSCE_SHIFT (8U)
mbed_official 121:7f86b4238bec 9667 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
mbed_official 121:7f86b4238bec 9668 #define RTC_CR_CLKO_MASK (0x200U)
mbed_official 121:7f86b4238bec 9669 #define RTC_CR_CLKO_SHIFT (9U)
mbed_official 121:7f86b4238bec 9670 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
mbed_official 121:7f86b4238bec 9671 #define RTC_CR_SC16P_MASK (0x400U)
mbed_official 121:7f86b4238bec 9672 #define RTC_CR_SC16P_SHIFT (10U)
mbed_official 121:7f86b4238bec 9673 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
mbed_official 121:7f86b4238bec 9674 #define RTC_CR_SC8P_MASK (0x800U)
mbed_official 121:7f86b4238bec 9675 #define RTC_CR_SC8P_SHIFT (11U)
mbed_official 121:7f86b4238bec 9676 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
mbed_official 121:7f86b4238bec 9677 #define RTC_CR_SC4P_MASK (0x1000U)
mbed_official 121:7f86b4238bec 9678 #define RTC_CR_SC4P_SHIFT (12U)
mbed_official 121:7f86b4238bec 9679 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
mbed_official 121:7f86b4238bec 9680 #define RTC_CR_SC2P_MASK (0x2000U)
mbed_official 121:7f86b4238bec 9681 #define RTC_CR_SC2P_SHIFT (13U)
mbed_official 121:7f86b4238bec 9682 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
mbed_official 121:7f86b4238bec 9683
mbed_official 121:7f86b4238bec 9684 /*! @name SR - RTC Status Register */
mbed_official 121:7f86b4238bec 9685 #define RTC_SR_TIF_MASK (0x1U)
mbed_official 121:7f86b4238bec 9686 #define RTC_SR_TIF_SHIFT (0U)
mbed_official 121:7f86b4238bec 9687 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
mbed_official 121:7f86b4238bec 9688 #define RTC_SR_TOF_MASK (0x2U)
mbed_official 121:7f86b4238bec 9689 #define RTC_SR_TOF_SHIFT (1U)
mbed_official 121:7f86b4238bec 9690 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
mbed_official 121:7f86b4238bec 9691 #define RTC_SR_TAF_MASK (0x4U)
mbed_official 121:7f86b4238bec 9692 #define RTC_SR_TAF_SHIFT (2U)
mbed_official 121:7f86b4238bec 9693 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
mbed_official 121:7f86b4238bec 9694 #define RTC_SR_TCE_MASK (0x10U)
mbed_official 121:7f86b4238bec 9695 #define RTC_SR_TCE_SHIFT (4U)
mbed_official 121:7f86b4238bec 9696 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
mbed_official 121:7f86b4238bec 9697
mbed_official 121:7f86b4238bec 9698 /*! @name LR - RTC Lock Register */
mbed_official 121:7f86b4238bec 9699 #define RTC_LR_TCL_MASK (0x8U)
mbed_official 121:7f86b4238bec 9700 #define RTC_LR_TCL_SHIFT (3U)
mbed_official 121:7f86b4238bec 9701 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
mbed_official 121:7f86b4238bec 9702 #define RTC_LR_CRL_MASK (0x10U)
mbed_official 121:7f86b4238bec 9703 #define RTC_LR_CRL_SHIFT (4U)
mbed_official 121:7f86b4238bec 9704 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
mbed_official 121:7f86b4238bec 9705 #define RTC_LR_SRL_MASK (0x20U)
mbed_official 121:7f86b4238bec 9706 #define RTC_LR_SRL_SHIFT (5U)
mbed_official 121:7f86b4238bec 9707 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
mbed_official 121:7f86b4238bec 9708 #define RTC_LR_LRL_MASK (0x40U)
mbed_official 121:7f86b4238bec 9709 #define RTC_LR_LRL_SHIFT (6U)
mbed_official 121:7f86b4238bec 9710 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
mbed_official 121:7f86b4238bec 9711
mbed_official 121:7f86b4238bec 9712 /*! @name IER - RTC Interrupt Enable Register */
mbed_official 121:7f86b4238bec 9713 #define RTC_IER_TIIE_MASK (0x1U)
mbed_official 121:7f86b4238bec 9714 #define RTC_IER_TIIE_SHIFT (0U)
mbed_official 121:7f86b4238bec 9715 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
mbed_official 121:7f86b4238bec 9716 #define RTC_IER_TOIE_MASK (0x2U)
mbed_official 121:7f86b4238bec 9717 #define RTC_IER_TOIE_SHIFT (1U)
mbed_official 121:7f86b4238bec 9718 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
mbed_official 121:7f86b4238bec 9719 #define RTC_IER_TAIE_MASK (0x4U)
mbed_official 121:7f86b4238bec 9720 #define RTC_IER_TAIE_SHIFT (2U)
mbed_official 121:7f86b4238bec 9721 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
mbed_official 121:7f86b4238bec 9722 #define RTC_IER_TSIE_MASK (0x10U)
mbed_official 121:7f86b4238bec 9723 #define RTC_IER_TSIE_SHIFT (4U)
mbed_official 121:7f86b4238bec 9724 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
mbed_official 121:7f86b4238bec 9725 #define RTC_IER_WPON_MASK (0x80U)
mbed_official 121:7f86b4238bec 9726 #define RTC_IER_WPON_SHIFT (7U)
mbed_official 121:7f86b4238bec 9727 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
mbed_official 121:7f86b4238bec 9728
mbed_official 121:7f86b4238bec 9729 /*! @name WAR - RTC Write Access Register */
mbed_official 121:7f86b4238bec 9730 #define RTC_WAR_TSRW_MASK (0x1U)
mbed_official 121:7f86b4238bec 9731 #define RTC_WAR_TSRW_SHIFT (0U)
mbed_official 121:7f86b4238bec 9732 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
mbed_official 121:7f86b4238bec 9733 #define RTC_WAR_TPRW_MASK (0x2U)
mbed_official 121:7f86b4238bec 9734 #define RTC_WAR_TPRW_SHIFT (1U)
mbed_official 121:7f86b4238bec 9735 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
mbed_official 121:7f86b4238bec 9736 #define RTC_WAR_TARW_MASK (0x4U)
mbed_official 121:7f86b4238bec 9737 #define RTC_WAR_TARW_SHIFT (2U)
mbed_official 121:7f86b4238bec 9738 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
mbed_official 121:7f86b4238bec 9739 #define RTC_WAR_TCRW_MASK (0x8U)
mbed_official 121:7f86b4238bec 9740 #define RTC_WAR_TCRW_SHIFT (3U)
mbed_official 121:7f86b4238bec 9741 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
mbed_official 121:7f86b4238bec 9742 #define RTC_WAR_CRW_MASK (0x10U)
mbed_official 121:7f86b4238bec 9743 #define RTC_WAR_CRW_SHIFT (4U)
mbed_official 121:7f86b4238bec 9744 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
mbed_official 121:7f86b4238bec 9745 #define RTC_WAR_SRW_MASK (0x20U)
mbed_official 121:7f86b4238bec 9746 #define RTC_WAR_SRW_SHIFT (5U)
mbed_official 121:7f86b4238bec 9747 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
mbed_official 121:7f86b4238bec 9748 #define RTC_WAR_LRW_MASK (0x40U)
mbed_official 121:7f86b4238bec 9749 #define RTC_WAR_LRW_SHIFT (6U)
mbed_official 121:7f86b4238bec 9750 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
mbed_official 121:7f86b4238bec 9751 #define RTC_WAR_IERW_MASK (0x80U)
mbed_official 121:7f86b4238bec 9752 #define RTC_WAR_IERW_SHIFT (7U)
mbed_official 121:7f86b4238bec 9753 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
mbed_official 121:7f86b4238bec 9754
mbed_official 121:7f86b4238bec 9755 /*! @name RAR - RTC Read Access Register */
mbed_official 121:7f86b4238bec 9756 #define RTC_RAR_TSRR_MASK (0x1U)
mbed_official 121:7f86b4238bec 9757 #define RTC_RAR_TSRR_SHIFT (0U)
mbed_official 121:7f86b4238bec 9758 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
mbed_official 121:7f86b4238bec 9759 #define RTC_RAR_TPRR_MASK (0x2U)
mbed_official 121:7f86b4238bec 9760 #define RTC_RAR_TPRR_SHIFT (1U)
mbed_official 121:7f86b4238bec 9761 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
mbed_official 121:7f86b4238bec 9762 #define RTC_RAR_TARR_MASK (0x4U)
mbed_official 121:7f86b4238bec 9763 #define RTC_RAR_TARR_SHIFT (2U)
mbed_official 121:7f86b4238bec 9764 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
mbed_official 121:7f86b4238bec 9765 #define RTC_RAR_TCRR_MASK (0x8U)
mbed_official 121:7f86b4238bec 9766 #define RTC_RAR_TCRR_SHIFT (3U)
mbed_official 121:7f86b4238bec 9767 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
mbed_official 121:7f86b4238bec 9768 #define RTC_RAR_CRR_MASK (0x10U)
mbed_official 121:7f86b4238bec 9769 #define RTC_RAR_CRR_SHIFT (4U)
mbed_official 121:7f86b4238bec 9770 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
mbed_official 121:7f86b4238bec 9771 #define RTC_RAR_SRR_MASK (0x20U)
mbed_official 121:7f86b4238bec 9772 #define RTC_RAR_SRR_SHIFT (5U)
mbed_official 121:7f86b4238bec 9773 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
mbed_official 121:7f86b4238bec 9774 #define RTC_RAR_LRR_MASK (0x40U)
mbed_official 121:7f86b4238bec 9775 #define RTC_RAR_LRR_SHIFT (6U)
mbed_official 121:7f86b4238bec 9776 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
mbed_official 121:7f86b4238bec 9777 #define RTC_RAR_IERR_MASK (0x80U)
mbed_official 121:7f86b4238bec 9778 #define RTC_RAR_IERR_SHIFT (7U)
mbed_official 121:7f86b4238bec 9779 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
mbed_official 121:7f86b4238bec 9780
mbed_official 121:7f86b4238bec 9781
mbed_official 121:7f86b4238bec 9782 /*!
mbed_official 121:7f86b4238bec 9783 * @}
mbed_official 121:7f86b4238bec 9784 */ /* end of group RTC_Register_Masks */
mbed_official 121:7f86b4238bec 9785
mbed_official 121:7f86b4238bec 9786
mbed_official 121:7f86b4238bec 9787 /* RTC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 9788 /** Peripheral RTC base address */
mbed_official 121:7f86b4238bec 9789 #define RTC_BASE (0x4003D000u)
mbed_official 121:7f86b4238bec 9790 /** Peripheral RTC base pointer */
mbed_official 121:7f86b4238bec 9791 #define RTC ((RTC_Type *)RTC_BASE)
mbed_official 121:7f86b4238bec 9792 /** Array initializer of RTC peripheral base addresses */
mbed_official 121:7f86b4238bec 9793 #define RTC_BASE_ADDRS { RTC_BASE }
mbed_official 121:7f86b4238bec 9794 /** Array initializer of RTC peripheral base pointers */
mbed_official 121:7f86b4238bec 9795 #define RTC_BASE_PTRS { RTC }
mbed_official 121:7f86b4238bec 9796 /** Interrupt vectors for the RTC peripheral type */
mbed_official 121:7f86b4238bec 9797 #define RTC_IRQS { RTC_IRQn }
mbed_official 121:7f86b4238bec 9798 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
mbed_official 121:7f86b4238bec 9799
mbed_official 121:7f86b4238bec 9800 /*!
mbed_official 121:7f86b4238bec 9801 * @}
mbed_official 121:7f86b4238bec 9802 */ /* end of group RTC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 9803
mbed_official 121:7f86b4238bec 9804
mbed_official 121:7f86b4238bec 9805 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9806 -- SDHC Peripheral Access Layer
mbed_official 121:7f86b4238bec 9807 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9808
mbed_official 121:7f86b4238bec 9809 /*!
mbed_official 121:7f86b4238bec 9810 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
mbed_official 121:7f86b4238bec 9811 * @{
mbed_official 121:7f86b4238bec 9812 */
mbed_official 121:7f86b4238bec 9813
mbed_official 121:7f86b4238bec 9814 /** SDHC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 9815 typedef struct {
mbed_official 121:7f86b4238bec 9816 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
mbed_official 121:7f86b4238bec 9817 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
mbed_official 121:7f86b4238bec 9818 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
mbed_official 121:7f86b4238bec 9819 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
mbed_official 121:7f86b4238bec 9820 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
mbed_official 121:7f86b4238bec 9821 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
mbed_official 121:7f86b4238bec 9822 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
mbed_official 121:7f86b4238bec 9823 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
mbed_official 121:7f86b4238bec 9824 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
mbed_official 121:7f86b4238bec 9825 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
mbed_official 121:7f86b4238bec 9826 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
mbed_official 121:7f86b4238bec 9827 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
mbed_official 121:7f86b4238bec 9828 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
mbed_official 121:7f86b4238bec 9829 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
mbed_official 121:7f86b4238bec 9830 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
mbed_official 121:7f86b4238bec 9831 uint8_t RESERVED_0[8];
mbed_official 121:7f86b4238bec 9832 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
mbed_official 121:7f86b4238bec 9833 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
mbed_official 121:7f86b4238bec 9834 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
mbed_official 121:7f86b4238bec 9835 uint8_t RESERVED_1[100];
mbed_official 121:7f86b4238bec 9836 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
mbed_official 121:7f86b4238bec 9837 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
mbed_official 121:7f86b4238bec 9838 uint8_t RESERVED_2[52];
mbed_official 121:7f86b4238bec 9839 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
mbed_official 121:7f86b4238bec 9840 } SDHC_Type;
mbed_official 121:7f86b4238bec 9841
mbed_official 121:7f86b4238bec 9842 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 9843 -- SDHC Register Masks
mbed_official 121:7f86b4238bec 9844 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 9845
mbed_official 121:7f86b4238bec 9846 /*!
mbed_official 121:7f86b4238bec 9847 * @addtogroup SDHC_Register_Masks SDHC Register Masks
mbed_official 121:7f86b4238bec 9848 * @{
mbed_official 121:7f86b4238bec 9849 */
mbed_official 121:7f86b4238bec 9850
mbed_official 121:7f86b4238bec 9851 /*! @name DSADDR - DMA System Address register */
mbed_official 121:7f86b4238bec 9852 #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
mbed_official 121:7f86b4238bec 9853 #define SDHC_DSADDR_DSADDR_SHIFT (2U)
mbed_official 121:7f86b4238bec 9854 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
mbed_official 121:7f86b4238bec 9855
mbed_official 121:7f86b4238bec 9856 /*! @name BLKATTR - Block Attributes register */
mbed_official 121:7f86b4238bec 9857 #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
mbed_official 121:7f86b4238bec 9858 #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
mbed_official 121:7f86b4238bec 9859 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
mbed_official 121:7f86b4238bec 9860 #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 9861 #define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
mbed_official 121:7f86b4238bec 9862 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
mbed_official 121:7f86b4238bec 9863
mbed_official 121:7f86b4238bec 9864 /*! @name CMDARG - Command Argument register */
mbed_official 121:7f86b4238bec 9865 #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9866 #define SDHC_CMDARG_CMDARG_SHIFT (0U)
mbed_official 121:7f86b4238bec 9867 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
mbed_official 121:7f86b4238bec 9868
mbed_official 121:7f86b4238bec 9869 /*! @name XFERTYP - Transfer Type register */
mbed_official 121:7f86b4238bec 9870 #define SDHC_XFERTYP_DMAEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 9871 #define SDHC_XFERTYP_DMAEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 9872 #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
mbed_official 121:7f86b4238bec 9873 #define SDHC_XFERTYP_BCEN_MASK (0x2U)
mbed_official 121:7f86b4238bec 9874 #define SDHC_XFERTYP_BCEN_SHIFT (1U)
mbed_official 121:7f86b4238bec 9875 #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
mbed_official 121:7f86b4238bec 9876 #define SDHC_XFERTYP_AC12EN_MASK (0x4U)
mbed_official 121:7f86b4238bec 9877 #define SDHC_XFERTYP_AC12EN_SHIFT (2U)
mbed_official 121:7f86b4238bec 9878 #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
mbed_official 121:7f86b4238bec 9879 #define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
mbed_official 121:7f86b4238bec 9880 #define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
mbed_official 121:7f86b4238bec 9881 #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
mbed_official 121:7f86b4238bec 9882 #define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
mbed_official 121:7f86b4238bec 9883 #define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
mbed_official 121:7f86b4238bec 9884 #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
mbed_official 121:7f86b4238bec 9885 #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
mbed_official 121:7f86b4238bec 9886 #define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
mbed_official 121:7f86b4238bec 9887 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
mbed_official 121:7f86b4238bec 9888 #define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
mbed_official 121:7f86b4238bec 9889 #define SDHC_XFERTYP_CCCEN_SHIFT (19U)
mbed_official 121:7f86b4238bec 9890 #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
mbed_official 121:7f86b4238bec 9891 #define SDHC_XFERTYP_CICEN_MASK (0x100000U)
mbed_official 121:7f86b4238bec 9892 #define SDHC_XFERTYP_CICEN_SHIFT (20U)
mbed_official 121:7f86b4238bec 9893 #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
mbed_official 121:7f86b4238bec 9894 #define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
mbed_official 121:7f86b4238bec 9895 #define SDHC_XFERTYP_DPSEL_SHIFT (21U)
mbed_official 121:7f86b4238bec 9896 #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
mbed_official 121:7f86b4238bec 9897 #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
mbed_official 121:7f86b4238bec 9898 #define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
mbed_official 121:7f86b4238bec 9899 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
mbed_official 121:7f86b4238bec 9900 #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
mbed_official 121:7f86b4238bec 9901 #define SDHC_XFERTYP_CMDINX_SHIFT (24U)
mbed_official 121:7f86b4238bec 9902 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
mbed_official 121:7f86b4238bec 9903
mbed_official 121:7f86b4238bec 9904 /*! @name CMDRSP - Command Response 0..Command Response 3 */
mbed_official 121:7f86b4238bec 9905 #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9906 #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
mbed_official 121:7f86b4238bec 9907 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
mbed_official 121:7f86b4238bec 9908 #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9909 #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
mbed_official 121:7f86b4238bec 9910 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
mbed_official 121:7f86b4238bec 9911 #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9912 #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
mbed_official 121:7f86b4238bec 9913 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
mbed_official 121:7f86b4238bec 9914 #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9915 #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
mbed_official 121:7f86b4238bec 9916 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
mbed_official 121:7f86b4238bec 9917
mbed_official 121:7f86b4238bec 9918 /* The count of SDHC_CMDRSP */
mbed_official 121:7f86b4238bec 9919 #define SDHC_CMDRSP_COUNT (4U)
mbed_official 121:7f86b4238bec 9920
mbed_official 121:7f86b4238bec 9921 /*! @name DATPORT - Buffer Data Port register */
mbed_official 121:7f86b4238bec 9922 #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 9923 #define SDHC_DATPORT_DATCONT_SHIFT (0U)
mbed_official 121:7f86b4238bec 9924 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
mbed_official 121:7f86b4238bec 9925
mbed_official 121:7f86b4238bec 9926 /*! @name PRSSTAT - Present State register */
mbed_official 121:7f86b4238bec 9927 #define SDHC_PRSSTAT_CIHB_MASK (0x1U)
mbed_official 121:7f86b4238bec 9928 #define SDHC_PRSSTAT_CIHB_SHIFT (0U)
mbed_official 121:7f86b4238bec 9929 #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
mbed_official 121:7f86b4238bec 9930 #define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
mbed_official 121:7f86b4238bec 9931 #define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
mbed_official 121:7f86b4238bec 9932 #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
mbed_official 121:7f86b4238bec 9933 #define SDHC_PRSSTAT_DLA_MASK (0x4U)
mbed_official 121:7f86b4238bec 9934 #define SDHC_PRSSTAT_DLA_SHIFT (2U)
mbed_official 121:7f86b4238bec 9935 #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
mbed_official 121:7f86b4238bec 9936 #define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
mbed_official 121:7f86b4238bec 9937 #define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
mbed_official 121:7f86b4238bec 9938 #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
mbed_official 121:7f86b4238bec 9939 #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
mbed_official 121:7f86b4238bec 9940 #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
mbed_official 121:7f86b4238bec 9941 #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
mbed_official 121:7f86b4238bec 9942 #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
mbed_official 121:7f86b4238bec 9943 #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
mbed_official 121:7f86b4238bec 9944 #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
mbed_official 121:7f86b4238bec 9945 #define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
mbed_official 121:7f86b4238bec 9946 #define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
mbed_official 121:7f86b4238bec 9947 #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
mbed_official 121:7f86b4238bec 9948 #define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
mbed_official 121:7f86b4238bec 9949 #define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
mbed_official 121:7f86b4238bec 9950 #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
mbed_official 121:7f86b4238bec 9951 #define SDHC_PRSSTAT_WTA_MASK (0x100U)
mbed_official 121:7f86b4238bec 9952 #define SDHC_PRSSTAT_WTA_SHIFT (8U)
mbed_official 121:7f86b4238bec 9953 #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
mbed_official 121:7f86b4238bec 9954 #define SDHC_PRSSTAT_RTA_MASK (0x200U)
mbed_official 121:7f86b4238bec 9955 #define SDHC_PRSSTAT_RTA_SHIFT (9U)
mbed_official 121:7f86b4238bec 9956 #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
mbed_official 121:7f86b4238bec 9957 #define SDHC_PRSSTAT_BWEN_MASK (0x400U)
mbed_official 121:7f86b4238bec 9958 #define SDHC_PRSSTAT_BWEN_SHIFT (10U)
mbed_official 121:7f86b4238bec 9959 #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
mbed_official 121:7f86b4238bec 9960 #define SDHC_PRSSTAT_BREN_MASK (0x800U)
mbed_official 121:7f86b4238bec 9961 #define SDHC_PRSSTAT_BREN_SHIFT (11U)
mbed_official 121:7f86b4238bec 9962 #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
mbed_official 121:7f86b4238bec 9963 #define SDHC_PRSSTAT_CINS_MASK (0x10000U)
mbed_official 121:7f86b4238bec 9964 #define SDHC_PRSSTAT_CINS_SHIFT (16U)
mbed_official 121:7f86b4238bec 9965 #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
mbed_official 121:7f86b4238bec 9966 #define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
mbed_official 121:7f86b4238bec 9967 #define SDHC_PRSSTAT_CLSL_SHIFT (23U)
mbed_official 121:7f86b4238bec 9968 #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
mbed_official 121:7f86b4238bec 9969 #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
mbed_official 121:7f86b4238bec 9970 #define SDHC_PRSSTAT_DLSL_SHIFT (24U)
mbed_official 121:7f86b4238bec 9971 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
mbed_official 121:7f86b4238bec 9972
mbed_official 121:7f86b4238bec 9973 /*! @name PROCTL - Protocol Control register */
mbed_official 121:7f86b4238bec 9974 #define SDHC_PROCTL_LCTL_MASK (0x1U)
mbed_official 121:7f86b4238bec 9975 #define SDHC_PROCTL_LCTL_SHIFT (0U)
mbed_official 121:7f86b4238bec 9976 #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
mbed_official 121:7f86b4238bec 9977 #define SDHC_PROCTL_DTW_MASK (0x6U)
mbed_official 121:7f86b4238bec 9978 #define SDHC_PROCTL_DTW_SHIFT (1U)
mbed_official 121:7f86b4238bec 9979 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
mbed_official 121:7f86b4238bec 9980 #define SDHC_PROCTL_D3CD_MASK (0x8U)
mbed_official 121:7f86b4238bec 9981 #define SDHC_PROCTL_D3CD_SHIFT (3U)
mbed_official 121:7f86b4238bec 9982 #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
mbed_official 121:7f86b4238bec 9983 #define SDHC_PROCTL_EMODE_MASK (0x30U)
mbed_official 121:7f86b4238bec 9984 #define SDHC_PROCTL_EMODE_SHIFT (4U)
mbed_official 121:7f86b4238bec 9985 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
mbed_official 121:7f86b4238bec 9986 #define SDHC_PROCTL_CDTL_MASK (0x40U)
mbed_official 121:7f86b4238bec 9987 #define SDHC_PROCTL_CDTL_SHIFT (6U)
mbed_official 121:7f86b4238bec 9988 #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
mbed_official 121:7f86b4238bec 9989 #define SDHC_PROCTL_CDSS_MASK (0x80U)
mbed_official 121:7f86b4238bec 9990 #define SDHC_PROCTL_CDSS_SHIFT (7U)
mbed_official 121:7f86b4238bec 9991 #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
mbed_official 121:7f86b4238bec 9992 #define SDHC_PROCTL_DMAS_MASK (0x300U)
mbed_official 121:7f86b4238bec 9993 #define SDHC_PROCTL_DMAS_SHIFT (8U)
mbed_official 121:7f86b4238bec 9994 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
mbed_official 121:7f86b4238bec 9995 #define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
mbed_official 121:7f86b4238bec 9996 #define SDHC_PROCTL_SABGREQ_SHIFT (16U)
mbed_official 121:7f86b4238bec 9997 #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
mbed_official 121:7f86b4238bec 9998 #define SDHC_PROCTL_CREQ_MASK (0x20000U)
mbed_official 121:7f86b4238bec 9999 #define SDHC_PROCTL_CREQ_SHIFT (17U)
mbed_official 121:7f86b4238bec 10000 #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
mbed_official 121:7f86b4238bec 10001 #define SDHC_PROCTL_RWCTL_MASK (0x40000U)
mbed_official 121:7f86b4238bec 10002 #define SDHC_PROCTL_RWCTL_SHIFT (18U)
mbed_official 121:7f86b4238bec 10003 #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
mbed_official 121:7f86b4238bec 10004 #define SDHC_PROCTL_IABG_MASK (0x80000U)
mbed_official 121:7f86b4238bec 10005 #define SDHC_PROCTL_IABG_SHIFT (19U)
mbed_official 121:7f86b4238bec 10006 #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
mbed_official 121:7f86b4238bec 10007 #define SDHC_PROCTL_WECINT_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10008 #define SDHC_PROCTL_WECINT_SHIFT (24U)
mbed_official 121:7f86b4238bec 10009 #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
mbed_official 121:7f86b4238bec 10010 #define SDHC_PROCTL_WECINS_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 10011 #define SDHC_PROCTL_WECINS_SHIFT (25U)
mbed_official 121:7f86b4238bec 10012 #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
mbed_official 121:7f86b4238bec 10013 #define SDHC_PROCTL_WECRM_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 10014 #define SDHC_PROCTL_WECRM_SHIFT (26U)
mbed_official 121:7f86b4238bec 10015 #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
mbed_official 121:7f86b4238bec 10016
mbed_official 121:7f86b4238bec 10017 /*! @name SYSCTL - System Control register */
mbed_official 121:7f86b4238bec 10018 #define SDHC_SYSCTL_IPGEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 10019 #define SDHC_SYSCTL_IPGEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 10020 #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
mbed_official 121:7f86b4238bec 10021 #define SDHC_SYSCTL_HCKEN_MASK (0x2U)
mbed_official 121:7f86b4238bec 10022 #define SDHC_SYSCTL_HCKEN_SHIFT (1U)
mbed_official 121:7f86b4238bec 10023 #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
mbed_official 121:7f86b4238bec 10024 #define SDHC_SYSCTL_PEREN_MASK (0x4U)
mbed_official 121:7f86b4238bec 10025 #define SDHC_SYSCTL_PEREN_SHIFT (2U)
mbed_official 121:7f86b4238bec 10026 #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
mbed_official 121:7f86b4238bec 10027 #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 10028 #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 10029 #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
mbed_official 121:7f86b4238bec 10030 #define SDHC_SYSCTL_DVS_MASK (0xF0U)
mbed_official 121:7f86b4238bec 10031 #define SDHC_SYSCTL_DVS_SHIFT (4U)
mbed_official 121:7f86b4238bec 10032 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
mbed_official 121:7f86b4238bec 10033 #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 10034 #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
mbed_official 121:7f86b4238bec 10035 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
mbed_official 121:7f86b4238bec 10036 #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 10037 #define SDHC_SYSCTL_DTOCV_SHIFT (16U)
mbed_official 121:7f86b4238bec 10038 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
mbed_official 121:7f86b4238bec 10039 #define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10040 #define SDHC_SYSCTL_RSTA_SHIFT (24U)
mbed_official 121:7f86b4238bec 10041 #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
mbed_official 121:7f86b4238bec 10042 #define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 10043 #define SDHC_SYSCTL_RSTC_SHIFT (25U)
mbed_official 121:7f86b4238bec 10044 #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
mbed_official 121:7f86b4238bec 10045 #define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 10046 #define SDHC_SYSCTL_RSTD_SHIFT (26U)
mbed_official 121:7f86b4238bec 10047 #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
mbed_official 121:7f86b4238bec 10048 #define SDHC_SYSCTL_INITA_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 10049 #define SDHC_SYSCTL_INITA_SHIFT (27U)
mbed_official 121:7f86b4238bec 10050 #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
mbed_official 121:7f86b4238bec 10051
mbed_official 121:7f86b4238bec 10052 /*! @name IRQSTAT - Interrupt Status register */
mbed_official 121:7f86b4238bec 10053 #define SDHC_IRQSTAT_CC_MASK (0x1U)
mbed_official 121:7f86b4238bec 10054 #define SDHC_IRQSTAT_CC_SHIFT (0U)
mbed_official 121:7f86b4238bec 10055 #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
mbed_official 121:7f86b4238bec 10056 #define SDHC_IRQSTAT_TC_MASK (0x2U)
mbed_official 121:7f86b4238bec 10057 #define SDHC_IRQSTAT_TC_SHIFT (1U)
mbed_official 121:7f86b4238bec 10058 #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
mbed_official 121:7f86b4238bec 10059 #define SDHC_IRQSTAT_BGE_MASK (0x4U)
mbed_official 121:7f86b4238bec 10060 #define SDHC_IRQSTAT_BGE_SHIFT (2U)
mbed_official 121:7f86b4238bec 10061 #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
mbed_official 121:7f86b4238bec 10062 #define SDHC_IRQSTAT_DINT_MASK (0x8U)
mbed_official 121:7f86b4238bec 10063 #define SDHC_IRQSTAT_DINT_SHIFT (3U)
mbed_official 121:7f86b4238bec 10064 #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
mbed_official 121:7f86b4238bec 10065 #define SDHC_IRQSTAT_BWR_MASK (0x10U)
mbed_official 121:7f86b4238bec 10066 #define SDHC_IRQSTAT_BWR_SHIFT (4U)
mbed_official 121:7f86b4238bec 10067 #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
mbed_official 121:7f86b4238bec 10068 #define SDHC_IRQSTAT_BRR_MASK (0x20U)
mbed_official 121:7f86b4238bec 10069 #define SDHC_IRQSTAT_BRR_SHIFT (5U)
mbed_official 121:7f86b4238bec 10070 #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
mbed_official 121:7f86b4238bec 10071 #define SDHC_IRQSTAT_CINS_MASK (0x40U)
mbed_official 121:7f86b4238bec 10072 #define SDHC_IRQSTAT_CINS_SHIFT (6U)
mbed_official 121:7f86b4238bec 10073 #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
mbed_official 121:7f86b4238bec 10074 #define SDHC_IRQSTAT_CRM_MASK (0x80U)
mbed_official 121:7f86b4238bec 10075 #define SDHC_IRQSTAT_CRM_SHIFT (7U)
mbed_official 121:7f86b4238bec 10076 #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
mbed_official 121:7f86b4238bec 10077 #define SDHC_IRQSTAT_CINT_MASK (0x100U)
mbed_official 121:7f86b4238bec 10078 #define SDHC_IRQSTAT_CINT_SHIFT (8U)
mbed_official 121:7f86b4238bec 10079 #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
mbed_official 121:7f86b4238bec 10080 #define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
mbed_official 121:7f86b4238bec 10081 #define SDHC_IRQSTAT_CTOE_SHIFT (16U)
mbed_official 121:7f86b4238bec 10082 #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
mbed_official 121:7f86b4238bec 10083 #define SDHC_IRQSTAT_CCE_MASK (0x20000U)
mbed_official 121:7f86b4238bec 10084 #define SDHC_IRQSTAT_CCE_SHIFT (17U)
mbed_official 121:7f86b4238bec 10085 #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
mbed_official 121:7f86b4238bec 10086 #define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
mbed_official 121:7f86b4238bec 10087 #define SDHC_IRQSTAT_CEBE_SHIFT (18U)
mbed_official 121:7f86b4238bec 10088 #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
mbed_official 121:7f86b4238bec 10089 #define SDHC_IRQSTAT_CIE_MASK (0x80000U)
mbed_official 121:7f86b4238bec 10090 #define SDHC_IRQSTAT_CIE_SHIFT (19U)
mbed_official 121:7f86b4238bec 10091 #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
mbed_official 121:7f86b4238bec 10092 #define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
mbed_official 121:7f86b4238bec 10093 #define SDHC_IRQSTAT_DTOE_SHIFT (20U)
mbed_official 121:7f86b4238bec 10094 #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
mbed_official 121:7f86b4238bec 10095 #define SDHC_IRQSTAT_DCE_MASK (0x200000U)
mbed_official 121:7f86b4238bec 10096 #define SDHC_IRQSTAT_DCE_SHIFT (21U)
mbed_official 121:7f86b4238bec 10097 #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
mbed_official 121:7f86b4238bec 10098 #define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
mbed_official 121:7f86b4238bec 10099 #define SDHC_IRQSTAT_DEBE_SHIFT (22U)
mbed_official 121:7f86b4238bec 10100 #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
mbed_official 121:7f86b4238bec 10101 #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10102 #define SDHC_IRQSTAT_AC12E_SHIFT (24U)
mbed_official 121:7f86b4238bec 10103 #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
mbed_official 121:7f86b4238bec 10104 #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 10105 #define SDHC_IRQSTAT_DMAE_SHIFT (28U)
mbed_official 121:7f86b4238bec 10106 #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
mbed_official 121:7f86b4238bec 10107
mbed_official 121:7f86b4238bec 10108 /*! @name IRQSTATEN - Interrupt Status Enable register */
mbed_official 121:7f86b4238bec 10109 #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 10110 #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 10111 #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
mbed_official 121:7f86b4238bec 10112 #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
mbed_official 121:7f86b4238bec 10113 #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
mbed_official 121:7f86b4238bec 10114 #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
mbed_official 121:7f86b4238bec 10115 #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 10116 #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 10117 #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
mbed_official 121:7f86b4238bec 10118 #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 10119 #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 10120 #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
mbed_official 121:7f86b4238bec 10121 #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
mbed_official 121:7f86b4238bec 10122 #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
mbed_official 121:7f86b4238bec 10123 #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
mbed_official 121:7f86b4238bec 10124 #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 10125 #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 10126 #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
mbed_official 121:7f86b4238bec 10127 #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 10128 #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 10129 #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
mbed_official 121:7f86b4238bec 10130 #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 10131 #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 10132 #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
mbed_official 121:7f86b4238bec 10133 #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
mbed_official 121:7f86b4238bec 10134 #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
mbed_official 121:7f86b4238bec 10135 #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
mbed_official 121:7f86b4238bec 10136 #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
mbed_official 121:7f86b4238bec 10137 #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
mbed_official 121:7f86b4238bec 10138 #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
mbed_official 121:7f86b4238bec 10139 #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
mbed_official 121:7f86b4238bec 10140 #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
mbed_official 121:7f86b4238bec 10141 #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
mbed_official 121:7f86b4238bec 10142 #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
mbed_official 121:7f86b4238bec 10143 #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
mbed_official 121:7f86b4238bec 10144 #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
mbed_official 121:7f86b4238bec 10145 #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
mbed_official 121:7f86b4238bec 10146 #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
mbed_official 121:7f86b4238bec 10147 #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
mbed_official 121:7f86b4238bec 10148 #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
mbed_official 121:7f86b4238bec 10149 #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
mbed_official 121:7f86b4238bec 10150 #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
mbed_official 121:7f86b4238bec 10151 #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
mbed_official 121:7f86b4238bec 10152 #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
mbed_official 121:7f86b4238bec 10153 #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
mbed_official 121:7f86b4238bec 10154 #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
mbed_official 121:7f86b4238bec 10155 #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
mbed_official 121:7f86b4238bec 10156 #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
mbed_official 121:7f86b4238bec 10157 #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10158 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
mbed_official 121:7f86b4238bec 10159 #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
mbed_official 121:7f86b4238bec 10160 #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 10161 #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
mbed_official 121:7f86b4238bec 10162 #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
mbed_official 121:7f86b4238bec 10163
mbed_official 121:7f86b4238bec 10164 /*! @name IRQSIGEN - Interrupt Signal Enable register */
mbed_official 121:7f86b4238bec 10165 #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 10166 #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 10167 #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
mbed_official 121:7f86b4238bec 10168 #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
mbed_official 121:7f86b4238bec 10169 #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
mbed_official 121:7f86b4238bec 10170 #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
mbed_official 121:7f86b4238bec 10171 #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 10172 #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 10173 #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
mbed_official 121:7f86b4238bec 10174 #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 10175 #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 10176 #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
mbed_official 121:7f86b4238bec 10177 #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
mbed_official 121:7f86b4238bec 10178 #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
mbed_official 121:7f86b4238bec 10179 #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
mbed_official 121:7f86b4238bec 10180 #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 10181 #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 10182 #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
mbed_official 121:7f86b4238bec 10183 #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 10184 #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 10185 #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
mbed_official 121:7f86b4238bec 10186 #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 10187 #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 10188 #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
mbed_official 121:7f86b4238bec 10189 #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
mbed_official 121:7f86b4238bec 10190 #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
mbed_official 121:7f86b4238bec 10191 #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
mbed_official 121:7f86b4238bec 10192 #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
mbed_official 121:7f86b4238bec 10193 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
mbed_official 121:7f86b4238bec 10194 #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
mbed_official 121:7f86b4238bec 10195 #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
mbed_official 121:7f86b4238bec 10196 #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
mbed_official 121:7f86b4238bec 10197 #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
mbed_official 121:7f86b4238bec 10198 #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
mbed_official 121:7f86b4238bec 10199 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
mbed_official 121:7f86b4238bec 10200 #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
mbed_official 121:7f86b4238bec 10201 #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
mbed_official 121:7f86b4238bec 10202 #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
mbed_official 121:7f86b4238bec 10203 #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
mbed_official 121:7f86b4238bec 10204 #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
mbed_official 121:7f86b4238bec 10205 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
mbed_official 121:7f86b4238bec 10206 #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
mbed_official 121:7f86b4238bec 10207 #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
mbed_official 121:7f86b4238bec 10208 #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
mbed_official 121:7f86b4238bec 10209 #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
mbed_official 121:7f86b4238bec 10210 #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
mbed_official 121:7f86b4238bec 10211 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
mbed_official 121:7f86b4238bec 10212 #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
mbed_official 121:7f86b4238bec 10213 #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10214 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
mbed_official 121:7f86b4238bec 10215 #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
mbed_official 121:7f86b4238bec 10216 #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 10217 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
mbed_official 121:7f86b4238bec 10218 #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
mbed_official 121:7f86b4238bec 10219
mbed_official 121:7f86b4238bec 10220 /*! @name AC12ERR - Auto CMD12 Error Status Register */
mbed_official 121:7f86b4238bec 10221 #define SDHC_AC12ERR_AC12NE_MASK (0x1U)
mbed_official 121:7f86b4238bec 10222 #define SDHC_AC12ERR_AC12NE_SHIFT (0U)
mbed_official 121:7f86b4238bec 10223 #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
mbed_official 121:7f86b4238bec 10224 #define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
mbed_official 121:7f86b4238bec 10225 #define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
mbed_official 121:7f86b4238bec 10226 #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
mbed_official 121:7f86b4238bec 10227 #define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
mbed_official 121:7f86b4238bec 10228 #define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
mbed_official 121:7f86b4238bec 10229 #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
mbed_official 121:7f86b4238bec 10230 #define SDHC_AC12ERR_AC12CE_MASK (0x8U)
mbed_official 121:7f86b4238bec 10231 #define SDHC_AC12ERR_AC12CE_SHIFT (3U)
mbed_official 121:7f86b4238bec 10232 #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
mbed_official 121:7f86b4238bec 10233 #define SDHC_AC12ERR_AC12IE_MASK (0x10U)
mbed_official 121:7f86b4238bec 10234 #define SDHC_AC12ERR_AC12IE_SHIFT (4U)
mbed_official 121:7f86b4238bec 10235 #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
mbed_official 121:7f86b4238bec 10236 #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
mbed_official 121:7f86b4238bec 10237 #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
mbed_official 121:7f86b4238bec 10238 #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
mbed_official 121:7f86b4238bec 10239
mbed_official 121:7f86b4238bec 10240 /*! @name HTCAPBLT - Host Controller Capabilities */
mbed_official 121:7f86b4238bec 10241 #define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
mbed_official 121:7f86b4238bec 10242 #define SDHC_HTCAPBLT_MBL_SHIFT (16U)
mbed_official 121:7f86b4238bec 10243 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
mbed_official 121:7f86b4238bec 10244 #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
mbed_official 121:7f86b4238bec 10245 #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
mbed_official 121:7f86b4238bec 10246 #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
mbed_official 121:7f86b4238bec 10247 #define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
mbed_official 121:7f86b4238bec 10248 #define SDHC_HTCAPBLT_HSS_SHIFT (21U)
mbed_official 121:7f86b4238bec 10249 #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
mbed_official 121:7f86b4238bec 10250 #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
mbed_official 121:7f86b4238bec 10251 #define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
mbed_official 121:7f86b4238bec 10252 #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
mbed_official 121:7f86b4238bec 10253 #define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
mbed_official 121:7f86b4238bec 10254 #define SDHC_HTCAPBLT_SRS_SHIFT (23U)
mbed_official 121:7f86b4238bec 10255 #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
mbed_official 121:7f86b4238bec 10256 #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10257 #define SDHC_HTCAPBLT_VS33_SHIFT (24U)
mbed_official 121:7f86b4238bec 10258 #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
mbed_official 121:7f86b4238bec 10259
mbed_official 121:7f86b4238bec 10260 /*! @name WML - Watermark Level Register */
mbed_official 121:7f86b4238bec 10261 #define SDHC_WML_RDWML_MASK (0xFFU)
mbed_official 121:7f86b4238bec 10262 #define SDHC_WML_RDWML_SHIFT (0U)
mbed_official 121:7f86b4238bec 10263 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
mbed_official 121:7f86b4238bec 10264 #define SDHC_WML_WRWML_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 10265 #define SDHC_WML_WRWML_SHIFT (16U)
mbed_official 121:7f86b4238bec 10266 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
mbed_official 121:7f86b4238bec 10267
mbed_official 121:7f86b4238bec 10268 /*! @name FEVT - Force Event register */
mbed_official 121:7f86b4238bec 10269 #define SDHC_FEVT_AC12NE_MASK (0x1U)
mbed_official 121:7f86b4238bec 10270 #define SDHC_FEVT_AC12NE_SHIFT (0U)
mbed_official 121:7f86b4238bec 10271 #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
mbed_official 121:7f86b4238bec 10272 #define SDHC_FEVT_AC12TOE_MASK (0x2U)
mbed_official 121:7f86b4238bec 10273 #define SDHC_FEVT_AC12TOE_SHIFT (1U)
mbed_official 121:7f86b4238bec 10274 #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
mbed_official 121:7f86b4238bec 10275 #define SDHC_FEVT_AC12CE_MASK (0x4U)
mbed_official 121:7f86b4238bec 10276 #define SDHC_FEVT_AC12CE_SHIFT (2U)
mbed_official 121:7f86b4238bec 10277 #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
mbed_official 121:7f86b4238bec 10278 #define SDHC_FEVT_AC12EBE_MASK (0x8U)
mbed_official 121:7f86b4238bec 10279 #define SDHC_FEVT_AC12EBE_SHIFT (3U)
mbed_official 121:7f86b4238bec 10280 #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
mbed_official 121:7f86b4238bec 10281 #define SDHC_FEVT_AC12IE_MASK (0x10U)
mbed_official 121:7f86b4238bec 10282 #define SDHC_FEVT_AC12IE_SHIFT (4U)
mbed_official 121:7f86b4238bec 10283 #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
mbed_official 121:7f86b4238bec 10284 #define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
mbed_official 121:7f86b4238bec 10285 #define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
mbed_official 121:7f86b4238bec 10286 #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
mbed_official 121:7f86b4238bec 10287 #define SDHC_FEVT_CTOE_MASK (0x10000U)
mbed_official 121:7f86b4238bec 10288 #define SDHC_FEVT_CTOE_SHIFT (16U)
mbed_official 121:7f86b4238bec 10289 #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
mbed_official 121:7f86b4238bec 10290 #define SDHC_FEVT_CCE_MASK (0x20000U)
mbed_official 121:7f86b4238bec 10291 #define SDHC_FEVT_CCE_SHIFT (17U)
mbed_official 121:7f86b4238bec 10292 #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
mbed_official 121:7f86b4238bec 10293 #define SDHC_FEVT_CEBE_MASK (0x40000U)
mbed_official 121:7f86b4238bec 10294 #define SDHC_FEVT_CEBE_SHIFT (18U)
mbed_official 121:7f86b4238bec 10295 #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
mbed_official 121:7f86b4238bec 10296 #define SDHC_FEVT_CIE_MASK (0x80000U)
mbed_official 121:7f86b4238bec 10297 #define SDHC_FEVT_CIE_SHIFT (19U)
mbed_official 121:7f86b4238bec 10298 #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
mbed_official 121:7f86b4238bec 10299 #define SDHC_FEVT_DTOE_MASK (0x100000U)
mbed_official 121:7f86b4238bec 10300 #define SDHC_FEVT_DTOE_SHIFT (20U)
mbed_official 121:7f86b4238bec 10301 #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
mbed_official 121:7f86b4238bec 10302 #define SDHC_FEVT_DCE_MASK (0x200000U)
mbed_official 121:7f86b4238bec 10303 #define SDHC_FEVT_DCE_SHIFT (21U)
mbed_official 121:7f86b4238bec 10304 #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
mbed_official 121:7f86b4238bec 10305 #define SDHC_FEVT_DEBE_MASK (0x400000U)
mbed_official 121:7f86b4238bec 10306 #define SDHC_FEVT_DEBE_SHIFT (22U)
mbed_official 121:7f86b4238bec 10307 #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
mbed_official 121:7f86b4238bec 10308 #define SDHC_FEVT_AC12E_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10309 #define SDHC_FEVT_AC12E_SHIFT (24U)
mbed_official 121:7f86b4238bec 10310 #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
mbed_official 121:7f86b4238bec 10311 #define SDHC_FEVT_DMAE_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 10312 #define SDHC_FEVT_DMAE_SHIFT (28U)
mbed_official 121:7f86b4238bec 10313 #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
mbed_official 121:7f86b4238bec 10314 #define SDHC_FEVT_CINT_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 10315 #define SDHC_FEVT_CINT_SHIFT (31U)
mbed_official 121:7f86b4238bec 10316 #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
mbed_official 121:7f86b4238bec 10317
mbed_official 121:7f86b4238bec 10318 /*! @name ADMAES - ADMA Error Status register */
mbed_official 121:7f86b4238bec 10319 #define SDHC_ADMAES_ADMAES_MASK (0x3U)
mbed_official 121:7f86b4238bec 10320 #define SDHC_ADMAES_ADMAES_SHIFT (0U)
mbed_official 121:7f86b4238bec 10321 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
mbed_official 121:7f86b4238bec 10322 #define SDHC_ADMAES_ADMALME_MASK (0x4U)
mbed_official 121:7f86b4238bec 10323 #define SDHC_ADMAES_ADMALME_SHIFT (2U)
mbed_official 121:7f86b4238bec 10324 #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
mbed_official 121:7f86b4238bec 10325 #define SDHC_ADMAES_ADMADCE_MASK (0x8U)
mbed_official 121:7f86b4238bec 10326 #define SDHC_ADMAES_ADMADCE_SHIFT (3U)
mbed_official 121:7f86b4238bec 10327 #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
mbed_official 121:7f86b4238bec 10328
mbed_official 121:7f86b4238bec 10329 /*! @name ADSADDR - ADMA System Addressregister */
mbed_official 121:7f86b4238bec 10330 #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
mbed_official 121:7f86b4238bec 10331 #define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
mbed_official 121:7f86b4238bec 10332 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
mbed_official 121:7f86b4238bec 10333
mbed_official 121:7f86b4238bec 10334 /*! @name VENDOR - Vendor Specific register */
mbed_official 121:7f86b4238bec 10335 #define SDHC_VENDOR_EXTDMAEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 10336 #define SDHC_VENDOR_EXTDMAEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 10337 #define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
mbed_official 121:7f86b4238bec 10338 #define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
mbed_official 121:7f86b4238bec 10339 #define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
mbed_official 121:7f86b4238bec 10340 #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
mbed_official 121:7f86b4238bec 10341 #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
mbed_official 121:7f86b4238bec 10342 #define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
mbed_official 121:7f86b4238bec 10343 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
mbed_official 121:7f86b4238bec 10344
mbed_official 121:7f86b4238bec 10345 /*! @name MMCBOOT - MMC Boot register */
mbed_official 121:7f86b4238bec 10346 #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
mbed_official 121:7f86b4238bec 10347 #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
mbed_official 121:7f86b4238bec 10348 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
mbed_official 121:7f86b4238bec 10349 #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
mbed_official 121:7f86b4238bec 10350 #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
mbed_official 121:7f86b4238bec 10351 #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
mbed_official 121:7f86b4238bec 10352 #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
mbed_official 121:7f86b4238bec 10353 #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
mbed_official 121:7f86b4238bec 10354 #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
mbed_official 121:7f86b4238bec 10355 #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 10356 #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 10357 #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
mbed_official 121:7f86b4238bec 10358 #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 10359 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 10360 #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
mbed_official 121:7f86b4238bec 10361 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 10362 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
mbed_official 121:7f86b4238bec 10363 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
mbed_official 121:7f86b4238bec 10364
mbed_official 121:7f86b4238bec 10365 /*! @name HOSTVER - Host Controller Version */
mbed_official 121:7f86b4238bec 10366 #define SDHC_HOSTVER_SVN_MASK (0xFFU)
mbed_official 121:7f86b4238bec 10367 #define SDHC_HOSTVER_SVN_SHIFT (0U)
mbed_official 121:7f86b4238bec 10368 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
mbed_official 121:7f86b4238bec 10369 #define SDHC_HOSTVER_VVN_MASK (0xFF00U)
mbed_official 121:7f86b4238bec 10370 #define SDHC_HOSTVER_VVN_SHIFT (8U)
mbed_official 121:7f86b4238bec 10371 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
mbed_official 121:7f86b4238bec 10372
mbed_official 121:7f86b4238bec 10373
mbed_official 121:7f86b4238bec 10374 /*!
mbed_official 121:7f86b4238bec 10375 * @}
mbed_official 121:7f86b4238bec 10376 */ /* end of group SDHC_Register_Masks */
mbed_official 121:7f86b4238bec 10377
mbed_official 121:7f86b4238bec 10378
mbed_official 121:7f86b4238bec 10379 /* SDHC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 10380 /** Peripheral SDHC base address */
mbed_official 121:7f86b4238bec 10381 #define SDHC_BASE (0x400B1000u)
mbed_official 121:7f86b4238bec 10382 /** Peripheral SDHC base pointer */
mbed_official 121:7f86b4238bec 10383 #define SDHC ((SDHC_Type *)SDHC_BASE)
mbed_official 121:7f86b4238bec 10384 /** Array initializer of SDHC peripheral base addresses */
mbed_official 121:7f86b4238bec 10385 #define SDHC_BASE_ADDRS { SDHC_BASE }
mbed_official 121:7f86b4238bec 10386 /** Array initializer of SDHC peripheral base pointers */
mbed_official 121:7f86b4238bec 10387 #define SDHC_BASE_PTRS { SDHC }
mbed_official 121:7f86b4238bec 10388 /** Interrupt vectors for the SDHC peripheral type */
mbed_official 121:7f86b4238bec 10389 #define SDHC_IRQS { SDHC_IRQn }
mbed_official 121:7f86b4238bec 10390
mbed_official 121:7f86b4238bec 10391 /*!
mbed_official 121:7f86b4238bec 10392 * @}
mbed_official 121:7f86b4238bec 10393 */ /* end of group SDHC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 10394
mbed_official 121:7f86b4238bec 10395
mbed_official 121:7f86b4238bec 10396 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 10397 -- SIM Peripheral Access Layer
mbed_official 121:7f86b4238bec 10398 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 10399
mbed_official 121:7f86b4238bec 10400 /*!
mbed_official 121:7f86b4238bec 10401 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mbed_official 121:7f86b4238bec 10402 * @{
mbed_official 121:7f86b4238bec 10403 */
mbed_official 121:7f86b4238bec 10404
mbed_official 121:7f86b4238bec 10405 /** SIM - Register Layout Typedef */
mbed_official 121:7f86b4238bec 10406 typedef struct {
mbed_official 121:7f86b4238bec 10407 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mbed_official 121:7f86b4238bec 10408 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mbed_official 121:7f86b4238bec 10409 uint8_t RESERVED_0[4092];
mbed_official 121:7f86b4238bec 10410 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mbed_official 121:7f86b4238bec 10411 uint8_t RESERVED_1[4];
mbed_official 121:7f86b4238bec 10412 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mbed_official 121:7f86b4238bec 10413 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mbed_official 121:7f86b4238bec 10414 uint8_t RESERVED_2[4];
mbed_official 121:7f86b4238bec 10415 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mbed_official 121:7f86b4238bec 10416 uint8_t RESERVED_3[8];
mbed_official 121:7f86b4238bec 10417 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mbed_official 121:7f86b4238bec 10418 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
mbed_official 121:7f86b4238bec 10419 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
mbed_official 121:7f86b4238bec 10420 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
mbed_official 121:7f86b4238bec 10421 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mbed_official 121:7f86b4238bec 10422 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mbed_official 121:7f86b4238bec 10423 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mbed_official 121:7f86b4238bec 10424 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mbed_official 121:7f86b4238bec 10425 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mbed_official 121:7f86b4238bec 10426 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
mbed_official 121:7f86b4238bec 10427 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mbed_official 121:7f86b4238bec 10428 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mbed_official 121:7f86b4238bec 10429 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
mbed_official 121:7f86b4238bec 10430 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mbed_official 121:7f86b4238bec 10431 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mbed_official 121:7f86b4238bec 10432 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mbed_official 121:7f86b4238bec 10433 } SIM_Type;
mbed_official 121:7f86b4238bec 10434
mbed_official 121:7f86b4238bec 10435 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 10436 -- SIM Register Masks
mbed_official 121:7f86b4238bec 10437 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 10438
mbed_official 121:7f86b4238bec 10439 /*!
mbed_official 121:7f86b4238bec 10440 * @addtogroup SIM_Register_Masks SIM Register Masks
mbed_official 121:7f86b4238bec 10441 * @{
mbed_official 121:7f86b4238bec 10442 */
mbed_official 121:7f86b4238bec 10443
mbed_official 121:7f86b4238bec 10444 /*! @name SOPT1 - System Options Register 1 */
mbed_official 121:7f86b4238bec 10445 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
mbed_official 121:7f86b4238bec 10446 #define SIM_SOPT1_RAMSIZE_SHIFT (12U)
mbed_official 121:7f86b4238bec 10447 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
mbed_official 121:7f86b4238bec 10448 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
mbed_official 121:7f86b4238bec 10449 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
mbed_official 121:7f86b4238bec 10450 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
mbed_official 121:7f86b4238bec 10451 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 10452 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
mbed_official 121:7f86b4238bec 10453 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
mbed_official 121:7f86b4238bec 10454 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 10455 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
mbed_official 121:7f86b4238bec 10456 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
mbed_official 121:7f86b4238bec 10457 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 10458 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
mbed_official 121:7f86b4238bec 10459 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
mbed_official 121:7f86b4238bec 10460
mbed_official 121:7f86b4238bec 10461 /*! @name SOPT1CFG - SOPT1 Configuration Register */
mbed_official 121:7f86b4238bec 10462 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10463 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
mbed_official 121:7f86b4238bec 10464 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
mbed_official 121:7f86b4238bec 10465 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 10466 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
mbed_official 121:7f86b4238bec 10467 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
mbed_official 121:7f86b4238bec 10468 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 10469 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
mbed_official 121:7f86b4238bec 10470 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
mbed_official 121:7f86b4238bec 10471
mbed_official 121:7f86b4238bec 10472 /*! @name SOPT2 - System Options Register 2 */
mbed_official 121:7f86b4238bec 10473 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
mbed_official 121:7f86b4238bec 10474 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
mbed_official 121:7f86b4238bec 10475 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
mbed_official 121:7f86b4238bec 10476 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
mbed_official 121:7f86b4238bec 10477 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
mbed_official 121:7f86b4238bec 10478 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
mbed_official 121:7f86b4238bec 10479 #define SIM_SOPT2_FBSL_MASK (0x300U)
mbed_official 121:7f86b4238bec 10480 #define SIM_SOPT2_FBSL_SHIFT (8U)
mbed_official 121:7f86b4238bec 10481 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
mbed_official 121:7f86b4238bec 10482 #define SIM_SOPT2_PTD7PAD_MASK (0x800U)
mbed_official 121:7f86b4238bec 10483 #define SIM_SOPT2_PTD7PAD_SHIFT (11U)
mbed_official 121:7f86b4238bec 10484 #define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
mbed_official 121:7f86b4238bec 10485 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
mbed_official 121:7f86b4238bec 10486 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
mbed_official 121:7f86b4238bec 10487 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
mbed_official 121:7f86b4238bec 10488 #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
mbed_official 121:7f86b4238bec 10489 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
mbed_official 121:7f86b4238bec 10490 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
mbed_official 121:7f86b4238bec 10491 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
mbed_official 121:7f86b4238bec 10492 #define SIM_SOPT2_USBSRC_SHIFT (18U)
mbed_official 121:7f86b4238bec 10493 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
mbed_official 121:7f86b4238bec 10494 #define SIM_SOPT2_RMIISRC_MASK (0x80000U)
mbed_official 121:7f86b4238bec 10495 #define SIM_SOPT2_RMIISRC_SHIFT (19U)
mbed_official 121:7f86b4238bec 10496 #define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
mbed_official 121:7f86b4238bec 10497 #define SIM_SOPT2_TIMESRC_MASK (0x300000U)
mbed_official 121:7f86b4238bec 10498 #define SIM_SOPT2_TIMESRC_SHIFT (20U)
mbed_official 121:7f86b4238bec 10499 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
mbed_official 121:7f86b4238bec 10500 #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
mbed_official 121:7f86b4238bec 10501 #define SIM_SOPT2_SDHCSRC_SHIFT (28U)
mbed_official 121:7f86b4238bec 10502 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
mbed_official 121:7f86b4238bec 10503
mbed_official 121:7f86b4238bec 10504 /*! @name SOPT4 - System Options Register 4 */
mbed_official 121:7f86b4238bec 10505 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
mbed_official 121:7f86b4238bec 10506 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
mbed_official 121:7f86b4238bec 10507 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
mbed_official 121:7f86b4238bec 10508 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
mbed_official 121:7f86b4238bec 10509 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
mbed_official 121:7f86b4238bec 10510 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
mbed_official 121:7f86b4238bec 10511 #define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
mbed_official 121:7f86b4238bec 10512 #define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
mbed_official 121:7f86b4238bec 10513 #define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
mbed_official 121:7f86b4238bec 10514 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
mbed_official 121:7f86b4238bec 10515 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
mbed_official 121:7f86b4238bec 10516 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
mbed_official 121:7f86b4238bec 10517 #define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
mbed_official 121:7f86b4238bec 10518 #define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
mbed_official 121:7f86b4238bec 10519 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
mbed_official 121:7f86b4238bec 10520 #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
mbed_official 121:7f86b4238bec 10521 #define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
mbed_official 121:7f86b4238bec 10522 #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
mbed_official 121:7f86b4238bec 10523 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
mbed_official 121:7f86b4238bec 10524 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
mbed_official 121:7f86b4238bec 10525 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
mbed_official 121:7f86b4238bec 10526 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
mbed_official 121:7f86b4238bec 10527 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
mbed_official 121:7f86b4238bec 10528 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
mbed_official 121:7f86b4238bec 10529 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10530 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
mbed_official 121:7f86b4238bec 10531 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
mbed_official 121:7f86b4238bec 10532 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 10533 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
mbed_official 121:7f86b4238bec 10534 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
mbed_official 121:7f86b4238bec 10535 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 10536 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
mbed_official 121:7f86b4238bec 10537 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
mbed_official 121:7f86b4238bec 10538 #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 10539 #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
mbed_official 121:7f86b4238bec 10540 #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
mbed_official 121:7f86b4238bec 10541 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 10542 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
mbed_official 121:7f86b4238bec 10543 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
mbed_official 121:7f86b4238bec 10544 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 10545 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
mbed_official 121:7f86b4238bec 10546 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
mbed_official 121:7f86b4238bec 10547 #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 10548 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
mbed_official 121:7f86b4238bec 10549 #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
mbed_official 121:7f86b4238bec 10550 #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 10551 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
mbed_official 121:7f86b4238bec 10552 #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
mbed_official 121:7f86b4238bec 10553
mbed_official 121:7f86b4238bec 10554 /*! @name SOPT5 - System Options Register 5 */
mbed_official 121:7f86b4238bec 10555 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
mbed_official 121:7f86b4238bec 10556 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
mbed_official 121:7f86b4238bec 10557 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
mbed_official 121:7f86b4238bec 10558 #define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
mbed_official 121:7f86b4238bec 10559 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
mbed_official 121:7f86b4238bec 10560 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
mbed_official 121:7f86b4238bec 10561 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
mbed_official 121:7f86b4238bec 10562 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
mbed_official 121:7f86b4238bec 10563 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
mbed_official 121:7f86b4238bec 10564 #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
mbed_official 121:7f86b4238bec 10565 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
mbed_official 121:7f86b4238bec 10566 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
mbed_official 121:7f86b4238bec 10567
mbed_official 121:7f86b4238bec 10568 /*! @name SOPT7 - System Options Register 7 */
mbed_official 121:7f86b4238bec 10569 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
mbed_official 121:7f86b4238bec 10570 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
mbed_official 121:7f86b4238bec 10571 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
mbed_official 121:7f86b4238bec 10572 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
mbed_official 121:7f86b4238bec 10573 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
mbed_official 121:7f86b4238bec 10574 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
mbed_official 121:7f86b4238bec 10575 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 10576 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 10577 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
mbed_official 121:7f86b4238bec 10578 #define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
mbed_official 121:7f86b4238bec 10579 #define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
mbed_official 121:7f86b4238bec 10580 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
mbed_official 121:7f86b4238bec 10581 #define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
mbed_official 121:7f86b4238bec 10582 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
mbed_official 121:7f86b4238bec 10583 #define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
mbed_official 121:7f86b4238bec 10584 #define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
mbed_official 121:7f86b4238bec 10585 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
mbed_official 121:7f86b4238bec 10586 #define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
mbed_official 121:7f86b4238bec 10587
mbed_official 121:7f86b4238bec 10588 /*! @name SDID - System Device Identification Register */
mbed_official 121:7f86b4238bec 10589 #define SIM_SDID_PINID_MASK (0xFU)
mbed_official 121:7f86b4238bec 10590 #define SIM_SDID_PINID_SHIFT (0U)
mbed_official 121:7f86b4238bec 10591 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
mbed_official 121:7f86b4238bec 10592 #define SIM_SDID_FAMID_MASK (0x70U)
mbed_official 121:7f86b4238bec 10593 #define SIM_SDID_FAMID_SHIFT (4U)
mbed_official 121:7f86b4238bec 10594 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
mbed_official 121:7f86b4238bec 10595 #define SIM_SDID_DIEID_MASK (0xF80U)
mbed_official 121:7f86b4238bec 10596 #define SIM_SDID_DIEID_SHIFT (7U)
mbed_official 121:7f86b4238bec 10597 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
mbed_official 121:7f86b4238bec 10598 #define SIM_SDID_REVID_MASK (0xF000U)
mbed_official 121:7f86b4238bec 10599 #define SIM_SDID_REVID_SHIFT (12U)
mbed_official 121:7f86b4238bec 10600 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
mbed_official 121:7f86b4238bec 10601 #define SIM_SDID_SERIESID_MASK (0xF00000U)
mbed_official 121:7f86b4238bec 10602 #define SIM_SDID_SERIESID_SHIFT (20U)
mbed_official 121:7f86b4238bec 10603 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
mbed_official 121:7f86b4238bec 10604 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
mbed_official 121:7f86b4238bec 10605 #define SIM_SDID_SUBFAMID_SHIFT (24U)
mbed_official 121:7f86b4238bec 10606 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
mbed_official 121:7f86b4238bec 10607 #define SIM_SDID_FAMILYID_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 10608 #define SIM_SDID_FAMILYID_SHIFT (28U)
mbed_official 121:7f86b4238bec 10609 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
mbed_official 121:7f86b4238bec 10610
mbed_official 121:7f86b4238bec 10611 /*! @name SCGC1 - System Clock Gating Control Register 1 */
mbed_official 121:7f86b4238bec 10612 #define SIM_SCGC1_I2C2_MASK (0x40U)
mbed_official 121:7f86b4238bec 10613 #define SIM_SCGC1_I2C2_SHIFT (6U)
mbed_official 121:7f86b4238bec 10614 #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
mbed_official 121:7f86b4238bec 10615 #define SIM_SCGC1_UART4_MASK (0x400U)
mbed_official 121:7f86b4238bec 10616 #define SIM_SCGC1_UART4_SHIFT (10U)
mbed_official 121:7f86b4238bec 10617 #define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
mbed_official 121:7f86b4238bec 10618 #define SIM_SCGC1_UART5_MASK (0x800U)
mbed_official 121:7f86b4238bec 10619 #define SIM_SCGC1_UART5_SHIFT (11U)
mbed_official 121:7f86b4238bec 10620 #define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
mbed_official 121:7f86b4238bec 10621
mbed_official 121:7f86b4238bec 10622 /*! @name SCGC2 - System Clock Gating Control Register 2 */
mbed_official 121:7f86b4238bec 10623 #define SIM_SCGC2_ENET_MASK (0x1U)
mbed_official 121:7f86b4238bec 10624 #define SIM_SCGC2_ENET_SHIFT (0U)
mbed_official 121:7f86b4238bec 10625 #define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
mbed_official 121:7f86b4238bec 10626 #define SIM_SCGC2_DAC0_MASK (0x1000U)
mbed_official 121:7f86b4238bec 10627 #define SIM_SCGC2_DAC0_SHIFT (12U)
mbed_official 121:7f86b4238bec 10628 #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
mbed_official 121:7f86b4238bec 10629 #define SIM_SCGC2_DAC1_MASK (0x2000U)
mbed_official 121:7f86b4238bec 10630 #define SIM_SCGC2_DAC1_SHIFT (13U)
mbed_official 121:7f86b4238bec 10631 #define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
mbed_official 121:7f86b4238bec 10632
mbed_official 121:7f86b4238bec 10633 /*! @name SCGC3 - System Clock Gating Control Register 3 */
mbed_official 121:7f86b4238bec 10634 #define SIM_SCGC3_RNGA_MASK (0x1U)
mbed_official 121:7f86b4238bec 10635 #define SIM_SCGC3_RNGA_SHIFT (0U)
mbed_official 121:7f86b4238bec 10636 #define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
mbed_official 121:7f86b4238bec 10637 #define SIM_SCGC3_SPI2_MASK (0x1000U)
mbed_official 121:7f86b4238bec 10638 #define SIM_SCGC3_SPI2_SHIFT (12U)
mbed_official 121:7f86b4238bec 10639 #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
mbed_official 121:7f86b4238bec 10640 #define SIM_SCGC3_SDHC_MASK (0x20000U)
mbed_official 121:7f86b4238bec 10641 #define SIM_SCGC3_SDHC_SHIFT (17U)
mbed_official 121:7f86b4238bec 10642 #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
mbed_official 121:7f86b4238bec 10643 #define SIM_SCGC3_FTM2_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10644 #define SIM_SCGC3_FTM2_SHIFT (24U)
mbed_official 121:7f86b4238bec 10645 #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
mbed_official 121:7f86b4238bec 10646 #define SIM_SCGC3_FTM3_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 10647 #define SIM_SCGC3_FTM3_SHIFT (25U)
mbed_official 121:7f86b4238bec 10648 #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
mbed_official 121:7f86b4238bec 10649 #define SIM_SCGC3_ADC1_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 10650 #define SIM_SCGC3_ADC1_SHIFT (27U)
mbed_official 121:7f86b4238bec 10651 #define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
mbed_official 121:7f86b4238bec 10652
mbed_official 121:7f86b4238bec 10653 /*! @name SCGC4 - System Clock Gating Control Register 4 */
mbed_official 121:7f86b4238bec 10654 #define SIM_SCGC4_EWM_MASK (0x2U)
mbed_official 121:7f86b4238bec 10655 #define SIM_SCGC4_EWM_SHIFT (1U)
mbed_official 121:7f86b4238bec 10656 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
mbed_official 121:7f86b4238bec 10657 #define SIM_SCGC4_CMT_MASK (0x4U)
mbed_official 121:7f86b4238bec 10658 #define SIM_SCGC4_CMT_SHIFT (2U)
mbed_official 121:7f86b4238bec 10659 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
mbed_official 121:7f86b4238bec 10660 #define SIM_SCGC4_I2C0_MASK (0x40U)
mbed_official 121:7f86b4238bec 10661 #define SIM_SCGC4_I2C0_SHIFT (6U)
mbed_official 121:7f86b4238bec 10662 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
mbed_official 121:7f86b4238bec 10663 #define SIM_SCGC4_I2C1_MASK (0x80U)
mbed_official 121:7f86b4238bec 10664 #define SIM_SCGC4_I2C1_SHIFT (7U)
mbed_official 121:7f86b4238bec 10665 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
mbed_official 121:7f86b4238bec 10666 #define SIM_SCGC4_UART0_MASK (0x400U)
mbed_official 121:7f86b4238bec 10667 #define SIM_SCGC4_UART0_SHIFT (10U)
mbed_official 121:7f86b4238bec 10668 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
mbed_official 121:7f86b4238bec 10669 #define SIM_SCGC4_UART1_MASK (0x800U)
mbed_official 121:7f86b4238bec 10670 #define SIM_SCGC4_UART1_SHIFT (11U)
mbed_official 121:7f86b4238bec 10671 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
mbed_official 121:7f86b4238bec 10672 #define SIM_SCGC4_UART2_MASK (0x1000U)
mbed_official 121:7f86b4238bec 10673 #define SIM_SCGC4_UART2_SHIFT (12U)
mbed_official 121:7f86b4238bec 10674 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
mbed_official 121:7f86b4238bec 10675 #define SIM_SCGC4_UART3_MASK (0x2000U)
mbed_official 121:7f86b4238bec 10676 #define SIM_SCGC4_UART3_SHIFT (13U)
mbed_official 121:7f86b4238bec 10677 #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
mbed_official 121:7f86b4238bec 10678 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
mbed_official 121:7f86b4238bec 10679 #define SIM_SCGC4_USBOTG_SHIFT (18U)
mbed_official 121:7f86b4238bec 10680 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
mbed_official 121:7f86b4238bec 10681 #define SIM_SCGC4_CMP_MASK (0x80000U)
mbed_official 121:7f86b4238bec 10682 #define SIM_SCGC4_CMP_SHIFT (19U)
mbed_official 121:7f86b4238bec 10683 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
mbed_official 121:7f86b4238bec 10684 #define SIM_SCGC4_VREF_MASK (0x100000U)
mbed_official 121:7f86b4238bec 10685 #define SIM_SCGC4_VREF_SHIFT (20U)
mbed_official 121:7f86b4238bec 10686 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
mbed_official 121:7f86b4238bec 10687
mbed_official 121:7f86b4238bec 10688 /*! @name SCGC5 - System Clock Gating Control Register 5 */
mbed_official 121:7f86b4238bec 10689 #define SIM_SCGC5_LPTMR_MASK (0x1U)
mbed_official 121:7f86b4238bec 10690 #define SIM_SCGC5_LPTMR_SHIFT (0U)
mbed_official 121:7f86b4238bec 10691 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
mbed_official 121:7f86b4238bec 10692 #define SIM_SCGC5_PORTA_MASK (0x200U)
mbed_official 121:7f86b4238bec 10693 #define SIM_SCGC5_PORTA_SHIFT (9U)
mbed_official 121:7f86b4238bec 10694 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
mbed_official 121:7f86b4238bec 10695 #define SIM_SCGC5_PORTB_MASK (0x400U)
mbed_official 121:7f86b4238bec 10696 #define SIM_SCGC5_PORTB_SHIFT (10U)
mbed_official 121:7f86b4238bec 10697 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
mbed_official 121:7f86b4238bec 10698 #define SIM_SCGC5_PORTC_MASK (0x800U)
mbed_official 121:7f86b4238bec 10699 #define SIM_SCGC5_PORTC_SHIFT (11U)
mbed_official 121:7f86b4238bec 10700 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
mbed_official 121:7f86b4238bec 10701 #define SIM_SCGC5_PORTD_MASK (0x1000U)
mbed_official 121:7f86b4238bec 10702 #define SIM_SCGC5_PORTD_SHIFT (12U)
mbed_official 121:7f86b4238bec 10703 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
mbed_official 121:7f86b4238bec 10704 #define SIM_SCGC5_PORTE_MASK (0x2000U)
mbed_official 121:7f86b4238bec 10705 #define SIM_SCGC5_PORTE_SHIFT (13U)
mbed_official 121:7f86b4238bec 10706 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
mbed_official 121:7f86b4238bec 10707
mbed_official 121:7f86b4238bec 10708 /*! @name SCGC6 - System Clock Gating Control Register 6 */
mbed_official 121:7f86b4238bec 10709 #define SIM_SCGC6_FTF_MASK (0x1U)
mbed_official 121:7f86b4238bec 10710 #define SIM_SCGC6_FTF_SHIFT (0U)
mbed_official 121:7f86b4238bec 10711 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
mbed_official 121:7f86b4238bec 10712 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
mbed_official 121:7f86b4238bec 10713 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
mbed_official 121:7f86b4238bec 10714 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
mbed_official 121:7f86b4238bec 10715 #define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
mbed_official 121:7f86b4238bec 10716 #define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
mbed_official 121:7f86b4238bec 10717 #define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
mbed_official 121:7f86b4238bec 10718 #define SIM_SCGC6_RNGA_MASK (0x200U)
mbed_official 121:7f86b4238bec 10719 #define SIM_SCGC6_RNGA_SHIFT (9U)
mbed_official 121:7f86b4238bec 10720 #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
mbed_official 121:7f86b4238bec 10721 #define SIM_SCGC6_SPI0_MASK (0x1000U)
mbed_official 121:7f86b4238bec 10722 #define SIM_SCGC6_SPI0_SHIFT (12U)
mbed_official 121:7f86b4238bec 10723 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
mbed_official 121:7f86b4238bec 10724 #define SIM_SCGC6_SPI1_MASK (0x2000U)
mbed_official 121:7f86b4238bec 10725 #define SIM_SCGC6_SPI1_SHIFT (13U)
mbed_official 121:7f86b4238bec 10726 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
mbed_official 121:7f86b4238bec 10727 #define SIM_SCGC6_I2S_MASK (0x8000U)
mbed_official 121:7f86b4238bec 10728 #define SIM_SCGC6_I2S_SHIFT (15U)
mbed_official 121:7f86b4238bec 10729 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
mbed_official 121:7f86b4238bec 10730 #define SIM_SCGC6_CRC_MASK (0x40000U)
mbed_official 121:7f86b4238bec 10731 #define SIM_SCGC6_CRC_SHIFT (18U)
mbed_official 121:7f86b4238bec 10732 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
mbed_official 121:7f86b4238bec 10733 #define SIM_SCGC6_USBDCD_MASK (0x200000U)
mbed_official 121:7f86b4238bec 10734 #define SIM_SCGC6_USBDCD_SHIFT (21U)
mbed_official 121:7f86b4238bec 10735 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
mbed_official 121:7f86b4238bec 10736 #define SIM_SCGC6_PDB_MASK (0x400000U)
mbed_official 121:7f86b4238bec 10737 #define SIM_SCGC6_PDB_SHIFT (22U)
mbed_official 121:7f86b4238bec 10738 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
mbed_official 121:7f86b4238bec 10739 #define SIM_SCGC6_PIT_MASK (0x800000U)
mbed_official 121:7f86b4238bec 10740 #define SIM_SCGC6_PIT_SHIFT (23U)
mbed_official 121:7f86b4238bec 10741 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
mbed_official 121:7f86b4238bec 10742 #define SIM_SCGC6_FTM0_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 10743 #define SIM_SCGC6_FTM0_SHIFT (24U)
mbed_official 121:7f86b4238bec 10744 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
mbed_official 121:7f86b4238bec 10745 #define SIM_SCGC6_FTM1_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 10746 #define SIM_SCGC6_FTM1_SHIFT (25U)
mbed_official 121:7f86b4238bec 10747 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
mbed_official 121:7f86b4238bec 10748 #define SIM_SCGC6_FTM2_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 10749 #define SIM_SCGC6_FTM2_SHIFT (26U)
mbed_official 121:7f86b4238bec 10750 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
mbed_official 121:7f86b4238bec 10751 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 10752 #define SIM_SCGC6_ADC0_SHIFT (27U)
mbed_official 121:7f86b4238bec 10753 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
mbed_official 121:7f86b4238bec 10754 #define SIM_SCGC6_RTC_MASK (0x20000000U)
mbed_official 121:7f86b4238bec 10755 #define SIM_SCGC6_RTC_SHIFT (29U)
mbed_official 121:7f86b4238bec 10756 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
mbed_official 121:7f86b4238bec 10757 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 10758 #define SIM_SCGC6_DAC0_SHIFT (31U)
mbed_official 121:7f86b4238bec 10759 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
mbed_official 121:7f86b4238bec 10760
mbed_official 121:7f86b4238bec 10761 /*! @name SCGC7 - System Clock Gating Control Register 7 */
mbed_official 121:7f86b4238bec 10762 #define SIM_SCGC7_FLEXBUS_MASK (0x1U)
mbed_official 121:7f86b4238bec 10763 #define SIM_SCGC7_FLEXBUS_SHIFT (0U)
mbed_official 121:7f86b4238bec 10764 #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
mbed_official 121:7f86b4238bec 10765 #define SIM_SCGC7_DMA_MASK (0x2U)
mbed_official 121:7f86b4238bec 10766 #define SIM_SCGC7_DMA_SHIFT (1U)
mbed_official 121:7f86b4238bec 10767 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
mbed_official 121:7f86b4238bec 10768 #define SIM_SCGC7_MPU_MASK (0x4U)
mbed_official 121:7f86b4238bec 10769 #define SIM_SCGC7_MPU_SHIFT (2U)
mbed_official 121:7f86b4238bec 10770 #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
mbed_official 121:7f86b4238bec 10771
mbed_official 121:7f86b4238bec 10772 /*! @name CLKDIV1 - System Clock Divider Register 1 */
mbed_official 121:7f86b4238bec 10773 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 10774 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
mbed_official 121:7f86b4238bec 10775 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
mbed_official 121:7f86b4238bec 10776 #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
mbed_official 121:7f86b4238bec 10777 #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
mbed_official 121:7f86b4238bec 10778 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
mbed_official 121:7f86b4238bec 10779 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
mbed_official 121:7f86b4238bec 10780 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
mbed_official 121:7f86b4238bec 10781 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
mbed_official 121:7f86b4238bec 10782 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 10783 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
mbed_official 121:7f86b4238bec 10784 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
mbed_official 121:7f86b4238bec 10785
mbed_official 121:7f86b4238bec 10786 /*! @name CLKDIV2 - System Clock Divider Register 2 */
mbed_official 121:7f86b4238bec 10787 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
mbed_official 121:7f86b4238bec 10788 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
mbed_official 121:7f86b4238bec 10789 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
mbed_official 121:7f86b4238bec 10790 #define SIM_CLKDIV2_USBDIV_MASK (0xEU)
mbed_official 121:7f86b4238bec 10791 #define SIM_CLKDIV2_USBDIV_SHIFT (1U)
mbed_official 121:7f86b4238bec 10792 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
mbed_official 121:7f86b4238bec 10793
mbed_official 121:7f86b4238bec 10794 /*! @name FCFG1 - Flash Configuration Register 1 */
mbed_official 121:7f86b4238bec 10795 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
mbed_official 121:7f86b4238bec 10796 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
mbed_official 121:7f86b4238bec 10797 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
mbed_official 121:7f86b4238bec 10798 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
mbed_official 121:7f86b4238bec 10799 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
mbed_official 121:7f86b4238bec 10800 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
mbed_official 121:7f86b4238bec 10801 #define SIM_FCFG1_DEPART_MASK (0xF00U)
mbed_official 121:7f86b4238bec 10802 #define SIM_FCFG1_DEPART_SHIFT (8U)
mbed_official 121:7f86b4238bec 10803 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
mbed_official 121:7f86b4238bec 10804 #define SIM_FCFG1_EESIZE_MASK (0xF0000U)
mbed_official 121:7f86b4238bec 10805 #define SIM_FCFG1_EESIZE_SHIFT (16U)
mbed_official 121:7f86b4238bec 10806 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
mbed_official 121:7f86b4238bec 10807 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
mbed_official 121:7f86b4238bec 10808 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
mbed_official 121:7f86b4238bec 10809 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
mbed_official 121:7f86b4238bec 10810 #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
mbed_official 121:7f86b4238bec 10811 #define SIM_FCFG1_NVMSIZE_SHIFT (28U)
mbed_official 121:7f86b4238bec 10812 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
mbed_official 121:7f86b4238bec 10813
mbed_official 121:7f86b4238bec 10814 /*! @name FCFG2 - Flash Configuration Register 2 */
mbed_official 121:7f86b4238bec 10815 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
mbed_official 121:7f86b4238bec 10816 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
mbed_official 121:7f86b4238bec 10817 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
mbed_official 121:7f86b4238bec 10818 #define SIM_FCFG2_PFLSH_MASK (0x800000U)
mbed_official 121:7f86b4238bec 10819 #define SIM_FCFG2_PFLSH_SHIFT (23U)
mbed_official 121:7f86b4238bec 10820 #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
mbed_official 121:7f86b4238bec 10821 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
mbed_official 121:7f86b4238bec 10822 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
mbed_official 121:7f86b4238bec 10823 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
mbed_official 121:7f86b4238bec 10824
mbed_official 121:7f86b4238bec 10825 /*! @name UIDH - Unique Identification Register High */
mbed_official 121:7f86b4238bec 10826 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 10827 #define SIM_UIDH_UID_SHIFT (0U)
mbed_official 121:7f86b4238bec 10828 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
mbed_official 121:7f86b4238bec 10829
mbed_official 121:7f86b4238bec 10830 /*! @name UIDMH - Unique Identification Register Mid-High */
mbed_official 121:7f86b4238bec 10831 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 10832 #define SIM_UIDMH_UID_SHIFT (0U)
mbed_official 121:7f86b4238bec 10833 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
mbed_official 121:7f86b4238bec 10834
mbed_official 121:7f86b4238bec 10835 /*! @name UIDML - Unique Identification Register Mid Low */
mbed_official 121:7f86b4238bec 10836 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 10837 #define SIM_UIDML_UID_SHIFT (0U)
mbed_official 121:7f86b4238bec 10838 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
mbed_official 121:7f86b4238bec 10839
mbed_official 121:7f86b4238bec 10840 /*! @name UIDL - Unique Identification Register Low */
mbed_official 121:7f86b4238bec 10841 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 10842 #define SIM_UIDL_UID_SHIFT (0U)
mbed_official 121:7f86b4238bec 10843 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
mbed_official 121:7f86b4238bec 10844
mbed_official 121:7f86b4238bec 10845
mbed_official 121:7f86b4238bec 10846 /*!
mbed_official 121:7f86b4238bec 10847 * @}
mbed_official 121:7f86b4238bec 10848 */ /* end of group SIM_Register_Masks */
mbed_official 121:7f86b4238bec 10849
mbed_official 121:7f86b4238bec 10850
mbed_official 121:7f86b4238bec 10851 /* SIM - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 10852 /** Peripheral SIM base address */
mbed_official 121:7f86b4238bec 10853 #define SIM_BASE (0x40047000u)
mbed_official 121:7f86b4238bec 10854 /** Peripheral SIM base pointer */
mbed_official 121:7f86b4238bec 10855 #define SIM ((SIM_Type *)SIM_BASE)
mbed_official 121:7f86b4238bec 10856 /** Array initializer of SIM peripheral base addresses */
mbed_official 121:7f86b4238bec 10857 #define SIM_BASE_ADDRS { SIM_BASE }
mbed_official 121:7f86b4238bec 10858 /** Array initializer of SIM peripheral base pointers */
mbed_official 121:7f86b4238bec 10859 #define SIM_BASE_PTRS { SIM }
mbed_official 121:7f86b4238bec 10860
mbed_official 121:7f86b4238bec 10861 /*!
mbed_official 121:7f86b4238bec 10862 * @}
mbed_official 121:7f86b4238bec 10863 */ /* end of group SIM_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 10864
mbed_official 121:7f86b4238bec 10865
mbed_official 121:7f86b4238bec 10866 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 10867 -- SMC Peripheral Access Layer
mbed_official 121:7f86b4238bec 10868 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 10869
mbed_official 121:7f86b4238bec 10870 /*!
mbed_official 121:7f86b4238bec 10871 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mbed_official 121:7f86b4238bec 10872 * @{
mbed_official 121:7f86b4238bec 10873 */
mbed_official 121:7f86b4238bec 10874
mbed_official 121:7f86b4238bec 10875 /** SMC - Register Layout Typedef */
mbed_official 121:7f86b4238bec 10876 typedef struct {
mbed_official 121:7f86b4238bec 10877 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
mbed_official 121:7f86b4238bec 10878 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
mbed_official 121:7f86b4238bec 10879 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
mbed_official 121:7f86b4238bec 10880 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
mbed_official 121:7f86b4238bec 10881 } SMC_Type;
mbed_official 121:7f86b4238bec 10882
mbed_official 121:7f86b4238bec 10883 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 10884 -- SMC Register Masks
mbed_official 121:7f86b4238bec 10885 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 10886
mbed_official 121:7f86b4238bec 10887 /*!
mbed_official 121:7f86b4238bec 10888 * @addtogroup SMC_Register_Masks SMC Register Masks
mbed_official 121:7f86b4238bec 10889 * @{
mbed_official 121:7f86b4238bec 10890 */
mbed_official 121:7f86b4238bec 10891
mbed_official 121:7f86b4238bec 10892 /*! @name PMPROT - Power Mode Protection register */
mbed_official 121:7f86b4238bec 10893 #define SMC_PMPROT_AVLLS_MASK (0x2U)
mbed_official 121:7f86b4238bec 10894 #define SMC_PMPROT_AVLLS_SHIFT (1U)
mbed_official 121:7f86b4238bec 10895 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
mbed_official 121:7f86b4238bec 10896 #define SMC_PMPROT_ALLS_MASK (0x8U)
mbed_official 121:7f86b4238bec 10897 #define SMC_PMPROT_ALLS_SHIFT (3U)
mbed_official 121:7f86b4238bec 10898 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
mbed_official 121:7f86b4238bec 10899 #define SMC_PMPROT_AVLP_MASK (0x20U)
mbed_official 121:7f86b4238bec 10900 #define SMC_PMPROT_AVLP_SHIFT (5U)
mbed_official 121:7f86b4238bec 10901 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
mbed_official 121:7f86b4238bec 10902
mbed_official 121:7f86b4238bec 10903 /*! @name PMCTRL - Power Mode Control register */
mbed_official 121:7f86b4238bec 10904 #define SMC_PMCTRL_STOPM_MASK (0x7U)
mbed_official 121:7f86b4238bec 10905 #define SMC_PMCTRL_STOPM_SHIFT (0U)
mbed_official 121:7f86b4238bec 10906 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
mbed_official 121:7f86b4238bec 10907 #define SMC_PMCTRL_STOPA_MASK (0x8U)
mbed_official 121:7f86b4238bec 10908 #define SMC_PMCTRL_STOPA_SHIFT (3U)
mbed_official 121:7f86b4238bec 10909 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
mbed_official 121:7f86b4238bec 10910 #define SMC_PMCTRL_RUNM_MASK (0x60U)
mbed_official 121:7f86b4238bec 10911 #define SMC_PMCTRL_RUNM_SHIFT (5U)
mbed_official 121:7f86b4238bec 10912 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
mbed_official 121:7f86b4238bec 10913 #define SMC_PMCTRL_LPWUI_MASK (0x80U)
mbed_official 121:7f86b4238bec 10914 #define SMC_PMCTRL_LPWUI_SHIFT (7U)
mbed_official 121:7f86b4238bec 10915 #define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
mbed_official 121:7f86b4238bec 10916
mbed_official 121:7f86b4238bec 10917 /*! @name VLLSCTRL - VLLS Control register */
mbed_official 121:7f86b4238bec 10918 #define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
mbed_official 121:7f86b4238bec 10919 #define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
mbed_official 121:7f86b4238bec 10920 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
mbed_official 121:7f86b4238bec 10921 #define SMC_VLLSCTRL_PORPO_MASK (0x20U)
mbed_official 121:7f86b4238bec 10922 #define SMC_VLLSCTRL_PORPO_SHIFT (5U)
mbed_official 121:7f86b4238bec 10923 #define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK)
mbed_official 121:7f86b4238bec 10924
mbed_official 121:7f86b4238bec 10925 /*! @name PMSTAT - Power Mode Status register */
mbed_official 121:7f86b4238bec 10926 #define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
mbed_official 121:7f86b4238bec 10927 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
mbed_official 121:7f86b4238bec 10928 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
mbed_official 121:7f86b4238bec 10929
mbed_official 121:7f86b4238bec 10930
mbed_official 121:7f86b4238bec 10931 /*!
mbed_official 121:7f86b4238bec 10932 * @}
mbed_official 121:7f86b4238bec 10933 */ /* end of group SMC_Register_Masks */
mbed_official 121:7f86b4238bec 10934
mbed_official 121:7f86b4238bec 10935
mbed_official 121:7f86b4238bec 10936 /* SMC - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 10937 /** Peripheral SMC base address */
mbed_official 121:7f86b4238bec 10938 #define SMC_BASE (0x4007E000u)
mbed_official 121:7f86b4238bec 10939 /** Peripheral SMC base pointer */
mbed_official 121:7f86b4238bec 10940 #define SMC ((SMC_Type *)SMC_BASE)
mbed_official 121:7f86b4238bec 10941 /** Array initializer of SMC peripheral base addresses */
mbed_official 121:7f86b4238bec 10942 #define SMC_BASE_ADDRS { SMC_BASE }
mbed_official 121:7f86b4238bec 10943 /** Array initializer of SMC peripheral base pointers */
mbed_official 121:7f86b4238bec 10944 #define SMC_BASE_PTRS { SMC }
mbed_official 121:7f86b4238bec 10945
mbed_official 121:7f86b4238bec 10946 /*!
mbed_official 121:7f86b4238bec 10947 * @}
mbed_official 121:7f86b4238bec 10948 */ /* end of group SMC_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 10949
mbed_official 121:7f86b4238bec 10950
mbed_official 121:7f86b4238bec 10951 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 10952 -- SPI Peripheral Access Layer
mbed_official 121:7f86b4238bec 10953 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 10954
mbed_official 121:7f86b4238bec 10955 /*!
mbed_official 121:7f86b4238bec 10956 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mbed_official 121:7f86b4238bec 10957 * @{
mbed_official 121:7f86b4238bec 10958 */
mbed_official 121:7f86b4238bec 10959
mbed_official 121:7f86b4238bec 10960 /** SPI - Register Layout Typedef */
mbed_official 121:7f86b4238bec 10961 typedef struct {
mbed_official 121:7f86b4238bec 10962 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 10963 uint8_t RESERVED_0[4];
mbed_official 121:7f86b4238bec 10964 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
mbed_official 121:7f86b4238bec 10965 union { /* offset: 0xC */
mbed_official 121:7f86b4238bec 10966 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
mbed_official 121:7f86b4238bec 10967 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
mbed_official 121:7f86b4238bec 10968 };
mbed_official 121:7f86b4238bec 10969 uint8_t RESERVED_1[24];
mbed_official 121:7f86b4238bec 10970 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
mbed_official 121:7f86b4238bec 10971 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
mbed_official 121:7f86b4238bec 10972 union { /* offset: 0x34 */
mbed_official 121:7f86b4238bec 10973 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
mbed_official 121:7f86b4238bec 10974 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
mbed_official 121:7f86b4238bec 10975 };
mbed_official 121:7f86b4238bec 10976 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
mbed_official 121:7f86b4238bec 10977 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
mbed_official 121:7f86b4238bec 10978 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
mbed_official 121:7f86b4238bec 10979 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
mbed_official 121:7f86b4238bec 10980 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
mbed_official 121:7f86b4238bec 10981 uint8_t RESERVED_2[48];
mbed_official 121:7f86b4238bec 10982 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
mbed_official 121:7f86b4238bec 10983 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
mbed_official 121:7f86b4238bec 10984 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
mbed_official 121:7f86b4238bec 10985 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
mbed_official 121:7f86b4238bec 10986 } SPI_Type;
mbed_official 121:7f86b4238bec 10987
mbed_official 121:7f86b4238bec 10988 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 10989 -- SPI Register Masks
mbed_official 121:7f86b4238bec 10990 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 10991
mbed_official 121:7f86b4238bec 10992 /*!
mbed_official 121:7f86b4238bec 10993 * @addtogroup SPI_Register_Masks SPI Register Masks
mbed_official 121:7f86b4238bec 10994 * @{
mbed_official 121:7f86b4238bec 10995 */
mbed_official 121:7f86b4238bec 10996
mbed_official 121:7f86b4238bec 10997 /*! @name MCR - Module Configuration Register */
mbed_official 121:7f86b4238bec 10998 #define SPI_MCR_HALT_MASK (0x1U)
mbed_official 121:7f86b4238bec 10999 #define SPI_MCR_HALT_SHIFT (0U)
mbed_official 121:7f86b4238bec 11000 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
mbed_official 121:7f86b4238bec 11001 #define SPI_MCR_SMPL_PT_MASK (0x300U)
mbed_official 121:7f86b4238bec 11002 #define SPI_MCR_SMPL_PT_SHIFT (8U)
mbed_official 121:7f86b4238bec 11003 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
mbed_official 121:7f86b4238bec 11004 #define SPI_MCR_CLR_RXF_MASK (0x400U)
mbed_official 121:7f86b4238bec 11005 #define SPI_MCR_CLR_RXF_SHIFT (10U)
mbed_official 121:7f86b4238bec 11006 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
mbed_official 121:7f86b4238bec 11007 #define SPI_MCR_CLR_TXF_MASK (0x800U)
mbed_official 121:7f86b4238bec 11008 #define SPI_MCR_CLR_TXF_SHIFT (11U)
mbed_official 121:7f86b4238bec 11009 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
mbed_official 121:7f86b4238bec 11010 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
mbed_official 121:7f86b4238bec 11011 #define SPI_MCR_DIS_RXF_SHIFT (12U)
mbed_official 121:7f86b4238bec 11012 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
mbed_official 121:7f86b4238bec 11013 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
mbed_official 121:7f86b4238bec 11014 #define SPI_MCR_DIS_TXF_SHIFT (13U)
mbed_official 121:7f86b4238bec 11015 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
mbed_official 121:7f86b4238bec 11016 #define SPI_MCR_MDIS_MASK (0x4000U)
mbed_official 121:7f86b4238bec 11017 #define SPI_MCR_MDIS_SHIFT (14U)
mbed_official 121:7f86b4238bec 11018 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
mbed_official 121:7f86b4238bec 11019 #define SPI_MCR_DOZE_MASK (0x8000U)
mbed_official 121:7f86b4238bec 11020 #define SPI_MCR_DOZE_SHIFT (15U)
mbed_official 121:7f86b4238bec 11021 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
mbed_official 121:7f86b4238bec 11022 #define SPI_MCR_PCSIS_MASK (0x3F0000U)
mbed_official 121:7f86b4238bec 11023 #define SPI_MCR_PCSIS_SHIFT (16U)
mbed_official 121:7f86b4238bec 11024 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
mbed_official 121:7f86b4238bec 11025 #define SPI_MCR_ROOE_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 11026 #define SPI_MCR_ROOE_SHIFT (24U)
mbed_official 121:7f86b4238bec 11027 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
mbed_official 121:7f86b4238bec 11028 #define SPI_MCR_PCSSE_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 11029 #define SPI_MCR_PCSSE_SHIFT (25U)
mbed_official 121:7f86b4238bec 11030 #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
mbed_official 121:7f86b4238bec 11031 #define SPI_MCR_MTFE_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 11032 #define SPI_MCR_MTFE_SHIFT (26U)
mbed_official 121:7f86b4238bec 11033 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
mbed_official 121:7f86b4238bec 11034 #define SPI_MCR_FRZ_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 11035 #define SPI_MCR_FRZ_SHIFT (27U)
mbed_official 121:7f86b4238bec 11036 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
mbed_official 121:7f86b4238bec 11037 #define SPI_MCR_DCONF_MASK (0x30000000U)
mbed_official 121:7f86b4238bec 11038 #define SPI_MCR_DCONF_SHIFT (28U)
mbed_official 121:7f86b4238bec 11039 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
mbed_official 121:7f86b4238bec 11040 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 11041 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
mbed_official 121:7f86b4238bec 11042 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
mbed_official 121:7f86b4238bec 11043 #define SPI_MCR_MSTR_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 11044 #define SPI_MCR_MSTR_SHIFT (31U)
mbed_official 121:7f86b4238bec 11045 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
mbed_official 121:7f86b4238bec 11046
mbed_official 121:7f86b4238bec 11047 /*! @name TCR - Transfer Count Register */
mbed_official 121:7f86b4238bec 11048 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 11049 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
mbed_official 121:7f86b4238bec 11050 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
mbed_official 121:7f86b4238bec 11051
mbed_official 121:7f86b4238bec 11052 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
mbed_official 121:7f86b4238bec 11053 #define SPI_CTAR_BR_MASK (0xFU)
mbed_official 121:7f86b4238bec 11054 #define SPI_CTAR_BR_SHIFT (0U)
mbed_official 121:7f86b4238bec 11055 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
mbed_official 121:7f86b4238bec 11056 #define SPI_CTAR_DT_MASK (0xF0U)
mbed_official 121:7f86b4238bec 11057 #define SPI_CTAR_DT_SHIFT (4U)
mbed_official 121:7f86b4238bec 11058 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
mbed_official 121:7f86b4238bec 11059 #define SPI_CTAR_ASC_MASK (0xF00U)
mbed_official 121:7f86b4238bec 11060 #define SPI_CTAR_ASC_SHIFT (8U)
mbed_official 121:7f86b4238bec 11061 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
mbed_official 121:7f86b4238bec 11062 #define SPI_CTAR_CSSCK_MASK (0xF000U)
mbed_official 121:7f86b4238bec 11063 #define SPI_CTAR_CSSCK_SHIFT (12U)
mbed_official 121:7f86b4238bec 11064 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
mbed_official 121:7f86b4238bec 11065 #define SPI_CTAR_PBR_MASK (0x30000U)
mbed_official 121:7f86b4238bec 11066 #define SPI_CTAR_PBR_SHIFT (16U)
mbed_official 121:7f86b4238bec 11067 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
mbed_official 121:7f86b4238bec 11068 #define SPI_CTAR_PDT_MASK (0xC0000U)
mbed_official 121:7f86b4238bec 11069 #define SPI_CTAR_PDT_SHIFT (18U)
mbed_official 121:7f86b4238bec 11070 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
mbed_official 121:7f86b4238bec 11071 #define SPI_CTAR_PASC_MASK (0x300000U)
mbed_official 121:7f86b4238bec 11072 #define SPI_CTAR_PASC_SHIFT (20U)
mbed_official 121:7f86b4238bec 11073 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
mbed_official 121:7f86b4238bec 11074 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
mbed_official 121:7f86b4238bec 11075 #define SPI_CTAR_PCSSCK_SHIFT (22U)
mbed_official 121:7f86b4238bec 11076 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
mbed_official 121:7f86b4238bec 11077 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 11078 #define SPI_CTAR_LSBFE_SHIFT (24U)
mbed_official 121:7f86b4238bec 11079 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
mbed_official 121:7f86b4238bec 11080 #define SPI_CTAR_CPHA_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 11081 #define SPI_CTAR_CPHA_SHIFT (25U)
mbed_official 121:7f86b4238bec 11082 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
mbed_official 121:7f86b4238bec 11083 #define SPI_CTAR_CPOL_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 11084 #define SPI_CTAR_CPOL_SHIFT (26U)
mbed_official 121:7f86b4238bec 11085 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
mbed_official 121:7f86b4238bec 11086 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
mbed_official 121:7f86b4238bec 11087 #define SPI_CTAR_FMSZ_SHIFT (27U)
mbed_official 121:7f86b4238bec 11088 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
mbed_official 121:7f86b4238bec 11089 #define SPI_CTAR_DBR_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 11090 #define SPI_CTAR_DBR_SHIFT (31U)
mbed_official 121:7f86b4238bec 11091 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
mbed_official 121:7f86b4238bec 11092
mbed_official 121:7f86b4238bec 11093 /* The count of SPI_CTAR */
mbed_official 121:7f86b4238bec 11094 #define SPI_CTAR_COUNT (2U)
mbed_official 121:7f86b4238bec 11095
mbed_official 121:7f86b4238bec 11096 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
mbed_official 121:7f86b4238bec 11097 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 11098 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
mbed_official 121:7f86b4238bec 11099 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
mbed_official 121:7f86b4238bec 11100 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 11101 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
mbed_official 121:7f86b4238bec 11102 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
mbed_official 121:7f86b4238bec 11103 #define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
mbed_official 121:7f86b4238bec 11104 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
mbed_official 121:7f86b4238bec 11105 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
mbed_official 121:7f86b4238bec 11106
mbed_official 121:7f86b4238bec 11107 /* The count of SPI_CTAR_SLAVE */
mbed_official 121:7f86b4238bec 11108 #define SPI_CTAR_SLAVE_COUNT (1U)
mbed_official 121:7f86b4238bec 11109
mbed_official 121:7f86b4238bec 11110 /*! @name SR - Status Register */
mbed_official 121:7f86b4238bec 11111 #define SPI_SR_POPNXTPTR_MASK (0xFU)
mbed_official 121:7f86b4238bec 11112 #define SPI_SR_POPNXTPTR_SHIFT (0U)
mbed_official 121:7f86b4238bec 11113 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
mbed_official 121:7f86b4238bec 11114 #define SPI_SR_RXCTR_MASK (0xF0U)
mbed_official 121:7f86b4238bec 11115 #define SPI_SR_RXCTR_SHIFT (4U)
mbed_official 121:7f86b4238bec 11116 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
mbed_official 121:7f86b4238bec 11117 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
mbed_official 121:7f86b4238bec 11118 #define SPI_SR_TXNXTPTR_SHIFT (8U)
mbed_official 121:7f86b4238bec 11119 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
mbed_official 121:7f86b4238bec 11120 #define SPI_SR_TXCTR_MASK (0xF000U)
mbed_official 121:7f86b4238bec 11121 #define SPI_SR_TXCTR_SHIFT (12U)
mbed_official 121:7f86b4238bec 11122 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
mbed_official 121:7f86b4238bec 11123 #define SPI_SR_RFDF_MASK (0x20000U)
mbed_official 121:7f86b4238bec 11124 #define SPI_SR_RFDF_SHIFT (17U)
mbed_official 121:7f86b4238bec 11125 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
mbed_official 121:7f86b4238bec 11126 #define SPI_SR_RFOF_MASK (0x80000U)
mbed_official 121:7f86b4238bec 11127 #define SPI_SR_RFOF_SHIFT (19U)
mbed_official 121:7f86b4238bec 11128 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
mbed_official 121:7f86b4238bec 11129 #define SPI_SR_TFFF_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 11130 #define SPI_SR_TFFF_SHIFT (25U)
mbed_official 121:7f86b4238bec 11131 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
mbed_official 121:7f86b4238bec 11132 #define SPI_SR_TFUF_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 11133 #define SPI_SR_TFUF_SHIFT (27U)
mbed_official 121:7f86b4238bec 11134 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
mbed_official 121:7f86b4238bec 11135 #define SPI_SR_EOQF_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 11136 #define SPI_SR_EOQF_SHIFT (28U)
mbed_official 121:7f86b4238bec 11137 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
mbed_official 121:7f86b4238bec 11138 #define SPI_SR_TXRXS_MASK (0x40000000U)
mbed_official 121:7f86b4238bec 11139 #define SPI_SR_TXRXS_SHIFT (30U)
mbed_official 121:7f86b4238bec 11140 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
mbed_official 121:7f86b4238bec 11141 #define SPI_SR_TCF_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 11142 #define SPI_SR_TCF_SHIFT (31U)
mbed_official 121:7f86b4238bec 11143 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
mbed_official 121:7f86b4238bec 11144
mbed_official 121:7f86b4238bec 11145 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
mbed_official 121:7f86b4238bec 11146 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
mbed_official 121:7f86b4238bec 11147 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
mbed_official 121:7f86b4238bec 11148 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
mbed_official 121:7f86b4238bec 11149 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
mbed_official 121:7f86b4238bec 11150 #define SPI_RSER_RFDF_RE_SHIFT (17U)
mbed_official 121:7f86b4238bec 11151 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
mbed_official 121:7f86b4238bec 11152 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
mbed_official 121:7f86b4238bec 11153 #define SPI_RSER_RFOF_RE_SHIFT (19U)
mbed_official 121:7f86b4238bec 11154 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
mbed_official 121:7f86b4238bec 11155 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 11156 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
mbed_official 121:7f86b4238bec 11157 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
mbed_official 121:7f86b4238bec 11158 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 11159 #define SPI_RSER_TFFF_RE_SHIFT (25U)
mbed_official 121:7f86b4238bec 11160 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
mbed_official 121:7f86b4238bec 11161 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 11162 #define SPI_RSER_TFUF_RE_SHIFT (27U)
mbed_official 121:7f86b4238bec 11163 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
mbed_official 121:7f86b4238bec 11164 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
mbed_official 121:7f86b4238bec 11165 #define SPI_RSER_EOQF_RE_SHIFT (28U)
mbed_official 121:7f86b4238bec 11166 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
mbed_official 121:7f86b4238bec 11167 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 11168 #define SPI_RSER_TCF_RE_SHIFT (31U)
mbed_official 121:7f86b4238bec 11169 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
mbed_official 121:7f86b4238bec 11170
mbed_official 121:7f86b4238bec 11171 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
mbed_official 121:7f86b4238bec 11172 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 11173 #define SPI_PUSHR_TXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11174 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11175 #define SPI_PUSHR_PCS_MASK (0x3F0000U)
mbed_official 121:7f86b4238bec 11176 #define SPI_PUSHR_PCS_SHIFT (16U)
mbed_official 121:7f86b4238bec 11177 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
mbed_official 121:7f86b4238bec 11178 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
mbed_official 121:7f86b4238bec 11179 #define SPI_PUSHR_CTCNT_SHIFT (26U)
mbed_official 121:7f86b4238bec 11180 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
mbed_official 121:7f86b4238bec 11181 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
mbed_official 121:7f86b4238bec 11182 #define SPI_PUSHR_EOQ_SHIFT (27U)
mbed_official 121:7f86b4238bec 11183 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
mbed_official 121:7f86b4238bec 11184 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
mbed_official 121:7f86b4238bec 11185 #define SPI_PUSHR_CTAS_SHIFT (28U)
mbed_official 121:7f86b4238bec 11186 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
mbed_official 121:7f86b4238bec 11187 #define SPI_PUSHR_CONT_MASK (0x80000000U)
mbed_official 121:7f86b4238bec 11188 #define SPI_PUSHR_CONT_SHIFT (31U)
mbed_official 121:7f86b4238bec 11189 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
mbed_official 121:7f86b4238bec 11190
mbed_official 121:7f86b4238bec 11191 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
mbed_official 121:7f86b4238bec 11192 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 11193 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11194 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11195
mbed_official 121:7f86b4238bec 11196 /*! @name POPR - POP RX FIFO Register */
mbed_official 121:7f86b4238bec 11197 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 11198 #define SPI_POPR_RXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11199 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
mbed_official 121:7f86b4238bec 11200
mbed_official 121:7f86b4238bec 11201 /*! @name TXFR0 - Transmit FIFO Registers */
mbed_official 121:7f86b4238bec 11202 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 11203 #define SPI_TXFR0_TXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11204 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11205 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 11206 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
mbed_official 121:7f86b4238bec 11207 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11208
mbed_official 121:7f86b4238bec 11209 /*! @name TXFR1 - Transmit FIFO Registers */
mbed_official 121:7f86b4238bec 11210 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 11211 #define SPI_TXFR1_TXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11212 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11213 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 11214 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
mbed_official 121:7f86b4238bec 11215 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11216
mbed_official 121:7f86b4238bec 11217 /*! @name TXFR2 - Transmit FIFO Registers */
mbed_official 121:7f86b4238bec 11218 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 11219 #define SPI_TXFR2_TXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11220 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11221 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 11222 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
mbed_official 121:7f86b4238bec 11223 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11224
mbed_official 121:7f86b4238bec 11225 /*! @name TXFR3 - Transmit FIFO Registers */
mbed_official 121:7f86b4238bec 11226 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 11227 #define SPI_TXFR3_TXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11228 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11229 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
mbed_official 121:7f86b4238bec 11230 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
mbed_official 121:7f86b4238bec 11231 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
mbed_official 121:7f86b4238bec 11232
mbed_official 121:7f86b4238bec 11233 /*! @name RXFR0 - Receive FIFO Registers */
mbed_official 121:7f86b4238bec 11234 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 11235 #define SPI_RXFR0_RXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11236 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
mbed_official 121:7f86b4238bec 11237
mbed_official 121:7f86b4238bec 11238 /*! @name RXFR1 - Receive FIFO Registers */
mbed_official 121:7f86b4238bec 11239 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 11240 #define SPI_RXFR1_RXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11241 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
mbed_official 121:7f86b4238bec 11242
mbed_official 121:7f86b4238bec 11243 /*! @name RXFR2 - Receive FIFO Registers */
mbed_official 121:7f86b4238bec 11244 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 11245 #define SPI_RXFR2_RXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11246 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
mbed_official 121:7f86b4238bec 11247
mbed_official 121:7f86b4238bec 11248 /*! @name RXFR3 - Receive FIFO Registers */
mbed_official 121:7f86b4238bec 11249 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
mbed_official 121:7f86b4238bec 11250 #define SPI_RXFR3_RXDATA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11251 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
mbed_official 121:7f86b4238bec 11252
mbed_official 121:7f86b4238bec 11253
mbed_official 121:7f86b4238bec 11254 /*!
mbed_official 121:7f86b4238bec 11255 * @}
mbed_official 121:7f86b4238bec 11256 */ /* end of group SPI_Register_Masks */
mbed_official 121:7f86b4238bec 11257
mbed_official 121:7f86b4238bec 11258
mbed_official 121:7f86b4238bec 11259 /* SPI - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 11260 /** Peripheral SPI0 base address */
mbed_official 121:7f86b4238bec 11261 #define SPI0_BASE (0x4002C000u)
mbed_official 121:7f86b4238bec 11262 /** Peripheral SPI0 base pointer */
mbed_official 121:7f86b4238bec 11263 #define SPI0 ((SPI_Type *)SPI0_BASE)
mbed_official 121:7f86b4238bec 11264 /** Peripheral SPI1 base address */
mbed_official 121:7f86b4238bec 11265 #define SPI1_BASE (0x4002D000u)
mbed_official 121:7f86b4238bec 11266 /** Peripheral SPI1 base pointer */
mbed_official 121:7f86b4238bec 11267 #define SPI1 ((SPI_Type *)SPI1_BASE)
mbed_official 121:7f86b4238bec 11268 /** Peripheral SPI2 base address */
mbed_official 121:7f86b4238bec 11269 #define SPI2_BASE (0x400AC000u)
mbed_official 121:7f86b4238bec 11270 /** Peripheral SPI2 base pointer */
mbed_official 121:7f86b4238bec 11271 #define SPI2 ((SPI_Type *)SPI2_BASE)
mbed_official 121:7f86b4238bec 11272 /** Array initializer of SPI peripheral base addresses */
mbed_official 121:7f86b4238bec 11273 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
mbed_official 121:7f86b4238bec 11274 /** Array initializer of SPI peripheral base pointers */
mbed_official 121:7f86b4238bec 11275 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
mbed_official 121:7f86b4238bec 11276 /** Interrupt vectors for the SPI peripheral type */
mbed_official 121:7f86b4238bec 11277 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
mbed_official 121:7f86b4238bec 11278
mbed_official 121:7f86b4238bec 11279 /*!
mbed_official 121:7f86b4238bec 11280 * @}
mbed_official 121:7f86b4238bec 11281 */ /* end of group SPI_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 11282
mbed_official 121:7f86b4238bec 11283
mbed_official 121:7f86b4238bec 11284 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 11285 -- UART Peripheral Access Layer
mbed_official 121:7f86b4238bec 11286 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 11287
mbed_official 121:7f86b4238bec 11288 /*!
mbed_official 121:7f86b4238bec 11289 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
mbed_official 121:7f86b4238bec 11290 * @{
mbed_official 121:7f86b4238bec 11291 */
mbed_official 121:7f86b4238bec 11292
mbed_official 121:7f86b4238bec 11293 /** UART - Register Layout Typedef */
mbed_official 121:7f86b4238bec 11294 typedef struct {
mbed_official 121:7f86b4238bec 11295 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
mbed_official 121:7f86b4238bec 11296 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
mbed_official 121:7f86b4238bec 11297 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 121:7f86b4238bec 11298 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 121:7f86b4238bec 11299 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 121:7f86b4238bec 11300 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 121:7f86b4238bec 11301 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 121:7f86b4238bec 11302 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 121:7f86b4238bec 11303 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mbed_official 121:7f86b4238bec 11304 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mbed_official 121:7f86b4238bec 11305 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mbed_official 121:7f86b4238bec 11306 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mbed_official 121:7f86b4238bec 11307 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
mbed_official 121:7f86b4238bec 11308 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
mbed_official 121:7f86b4238bec 11309 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
mbed_official 121:7f86b4238bec 11310 uint8_t RESERVED_0[1];
mbed_official 121:7f86b4238bec 11311 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
mbed_official 121:7f86b4238bec 11312 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
mbed_official 121:7f86b4238bec 11313 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
mbed_official 121:7f86b4238bec 11314 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
mbed_official 121:7f86b4238bec 11315 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
mbed_official 121:7f86b4238bec 11316 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
mbed_official 121:7f86b4238bec 11317 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
mbed_official 121:7f86b4238bec 11318 uint8_t RESERVED_1[1];
mbed_official 121:7f86b4238bec 11319 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
mbed_official 121:7f86b4238bec 11320 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
mbed_official 121:7f86b4238bec 11321 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
mbed_official 121:7f86b4238bec 11322 union { /* offset: 0x1B */
mbed_official 121:7f86b4238bec 11323 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
mbed_official 121:7f86b4238bec 11324 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
mbed_official 121:7f86b4238bec 11325 };
mbed_official 121:7f86b4238bec 11326 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
mbed_official 121:7f86b4238bec 11327 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
mbed_official 121:7f86b4238bec 11328 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
mbed_official 121:7f86b4238bec 11329 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
mbed_official 121:7f86b4238bec 11330 } UART_Type;
mbed_official 121:7f86b4238bec 11331
mbed_official 121:7f86b4238bec 11332 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 11333 -- UART Register Masks
mbed_official 121:7f86b4238bec 11334 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 11335
mbed_official 121:7f86b4238bec 11336 /*!
mbed_official 121:7f86b4238bec 11337 * @addtogroup UART_Register_Masks UART Register Masks
mbed_official 121:7f86b4238bec 11338 * @{
mbed_official 121:7f86b4238bec 11339 */
mbed_official 121:7f86b4238bec 11340
mbed_official 121:7f86b4238bec 11341 /*! @name BDH - UART Baud Rate Registers: High */
mbed_official 121:7f86b4238bec 11342 #define UART_BDH_SBR_MASK (0x1FU)
mbed_official 121:7f86b4238bec 11343 #define UART_BDH_SBR_SHIFT (0U)
mbed_official 121:7f86b4238bec 11344 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
mbed_official 121:7f86b4238bec 11345 #define UART_BDH_SBNS_MASK (0x20U)
mbed_official 121:7f86b4238bec 11346 #define UART_BDH_SBNS_SHIFT (5U)
mbed_official 121:7f86b4238bec 11347 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
mbed_official 121:7f86b4238bec 11348 #define UART_BDH_RXEDGIE_MASK (0x40U)
mbed_official 121:7f86b4238bec 11349 #define UART_BDH_RXEDGIE_SHIFT (6U)
mbed_official 121:7f86b4238bec 11350 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
mbed_official 121:7f86b4238bec 11351 #define UART_BDH_LBKDIE_MASK (0x80U)
mbed_official 121:7f86b4238bec 11352 #define UART_BDH_LBKDIE_SHIFT (7U)
mbed_official 121:7f86b4238bec 11353 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
mbed_official 121:7f86b4238bec 11354
mbed_official 121:7f86b4238bec 11355 /*! @name BDL - UART Baud Rate Registers: Low */
mbed_official 121:7f86b4238bec 11356 #define UART_BDL_SBR_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11357 #define UART_BDL_SBR_SHIFT (0U)
mbed_official 121:7f86b4238bec 11358 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
mbed_official 121:7f86b4238bec 11359
mbed_official 121:7f86b4238bec 11360 /*! @name C1 - UART Control Register 1 */
mbed_official 121:7f86b4238bec 11361 #define UART_C1_PT_MASK (0x1U)
mbed_official 121:7f86b4238bec 11362 #define UART_C1_PT_SHIFT (0U)
mbed_official 121:7f86b4238bec 11363 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
mbed_official 121:7f86b4238bec 11364 #define UART_C1_PE_MASK (0x2U)
mbed_official 121:7f86b4238bec 11365 #define UART_C1_PE_SHIFT (1U)
mbed_official 121:7f86b4238bec 11366 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
mbed_official 121:7f86b4238bec 11367 #define UART_C1_ILT_MASK (0x4U)
mbed_official 121:7f86b4238bec 11368 #define UART_C1_ILT_SHIFT (2U)
mbed_official 121:7f86b4238bec 11369 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
mbed_official 121:7f86b4238bec 11370 #define UART_C1_WAKE_MASK (0x8U)
mbed_official 121:7f86b4238bec 11371 #define UART_C1_WAKE_SHIFT (3U)
mbed_official 121:7f86b4238bec 11372 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
mbed_official 121:7f86b4238bec 11373 #define UART_C1_M_MASK (0x10U)
mbed_official 121:7f86b4238bec 11374 #define UART_C1_M_SHIFT (4U)
mbed_official 121:7f86b4238bec 11375 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
mbed_official 121:7f86b4238bec 11376 #define UART_C1_RSRC_MASK (0x20U)
mbed_official 121:7f86b4238bec 11377 #define UART_C1_RSRC_SHIFT (5U)
mbed_official 121:7f86b4238bec 11378 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
mbed_official 121:7f86b4238bec 11379 #define UART_C1_UARTSWAI_MASK (0x40U)
mbed_official 121:7f86b4238bec 11380 #define UART_C1_UARTSWAI_SHIFT (6U)
mbed_official 121:7f86b4238bec 11381 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
mbed_official 121:7f86b4238bec 11382 #define UART_C1_LOOPS_MASK (0x80U)
mbed_official 121:7f86b4238bec 11383 #define UART_C1_LOOPS_SHIFT (7U)
mbed_official 121:7f86b4238bec 11384 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
mbed_official 121:7f86b4238bec 11385
mbed_official 121:7f86b4238bec 11386 /*! @name C2 - UART Control Register 2 */
mbed_official 121:7f86b4238bec 11387 #define UART_C2_SBK_MASK (0x1U)
mbed_official 121:7f86b4238bec 11388 #define UART_C2_SBK_SHIFT (0U)
mbed_official 121:7f86b4238bec 11389 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
mbed_official 121:7f86b4238bec 11390 #define UART_C2_RWU_MASK (0x2U)
mbed_official 121:7f86b4238bec 11391 #define UART_C2_RWU_SHIFT (1U)
mbed_official 121:7f86b4238bec 11392 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
mbed_official 121:7f86b4238bec 11393 #define UART_C2_RE_MASK (0x4U)
mbed_official 121:7f86b4238bec 11394 #define UART_C2_RE_SHIFT (2U)
mbed_official 121:7f86b4238bec 11395 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
mbed_official 121:7f86b4238bec 11396 #define UART_C2_TE_MASK (0x8U)
mbed_official 121:7f86b4238bec 11397 #define UART_C2_TE_SHIFT (3U)
mbed_official 121:7f86b4238bec 11398 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
mbed_official 121:7f86b4238bec 11399 #define UART_C2_ILIE_MASK (0x10U)
mbed_official 121:7f86b4238bec 11400 #define UART_C2_ILIE_SHIFT (4U)
mbed_official 121:7f86b4238bec 11401 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
mbed_official 121:7f86b4238bec 11402 #define UART_C2_RIE_MASK (0x20U)
mbed_official 121:7f86b4238bec 11403 #define UART_C2_RIE_SHIFT (5U)
mbed_official 121:7f86b4238bec 11404 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
mbed_official 121:7f86b4238bec 11405 #define UART_C2_TCIE_MASK (0x40U)
mbed_official 121:7f86b4238bec 11406 #define UART_C2_TCIE_SHIFT (6U)
mbed_official 121:7f86b4238bec 11407 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
mbed_official 121:7f86b4238bec 11408 #define UART_C2_TIE_MASK (0x80U)
mbed_official 121:7f86b4238bec 11409 #define UART_C2_TIE_SHIFT (7U)
mbed_official 121:7f86b4238bec 11410 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
mbed_official 121:7f86b4238bec 11411
mbed_official 121:7f86b4238bec 11412 /*! @name S1 - UART Status Register 1 */
mbed_official 121:7f86b4238bec 11413 #define UART_S1_PF_MASK (0x1U)
mbed_official 121:7f86b4238bec 11414 #define UART_S1_PF_SHIFT (0U)
mbed_official 121:7f86b4238bec 11415 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
mbed_official 121:7f86b4238bec 11416 #define UART_S1_FE_MASK (0x2U)
mbed_official 121:7f86b4238bec 11417 #define UART_S1_FE_SHIFT (1U)
mbed_official 121:7f86b4238bec 11418 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
mbed_official 121:7f86b4238bec 11419 #define UART_S1_NF_MASK (0x4U)
mbed_official 121:7f86b4238bec 11420 #define UART_S1_NF_SHIFT (2U)
mbed_official 121:7f86b4238bec 11421 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
mbed_official 121:7f86b4238bec 11422 #define UART_S1_OR_MASK (0x8U)
mbed_official 121:7f86b4238bec 11423 #define UART_S1_OR_SHIFT (3U)
mbed_official 121:7f86b4238bec 11424 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
mbed_official 121:7f86b4238bec 11425 #define UART_S1_IDLE_MASK (0x10U)
mbed_official 121:7f86b4238bec 11426 #define UART_S1_IDLE_SHIFT (4U)
mbed_official 121:7f86b4238bec 11427 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
mbed_official 121:7f86b4238bec 11428 #define UART_S1_RDRF_MASK (0x20U)
mbed_official 121:7f86b4238bec 11429 #define UART_S1_RDRF_SHIFT (5U)
mbed_official 121:7f86b4238bec 11430 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
mbed_official 121:7f86b4238bec 11431 #define UART_S1_TC_MASK (0x40U)
mbed_official 121:7f86b4238bec 11432 #define UART_S1_TC_SHIFT (6U)
mbed_official 121:7f86b4238bec 11433 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
mbed_official 121:7f86b4238bec 11434 #define UART_S1_TDRE_MASK (0x80U)
mbed_official 121:7f86b4238bec 11435 #define UART_S1_TDRE_SHIFT (7U)
mbed_official 121:7f86b4238bec 11436 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
mbed_official 121:7f86b4238bec 11437
mbed_official 121:7f86b4238bec 11438 /*! @name S2 - UART Status Register 2 */
mbed_official 121:7f86b4238bec 11439 #define UART_S2_RAF_MASK (0x1U)
mbed_official 121:7f86b4238bec 11440 #define UART_S2_RAF_SHIFT (0U)
mbed_official 121:7f86b4238bec 11441 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
mbed_official 121:7f86b4238bec 11442 #define UART_S2_LBKDE_MASK (0x2U)
mbed_official 121:7f86b4238bec 11443 #define UART_S2_LBKDE_SHIFT (1U)
mbed_official 121:7f86b4238bec 11444 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
mbed_official 121:7f86b4238bec 11445 #define UART_S2_BRK13_MASK (0x4U)
mbed_official 121:7f86b4238bec 11446 #define UART_S2_BRK13_SHIFT (2U)
mbed_official 121:7f86b4238bec 11447 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
mbed_official 121:7f86b4238bec 11448 #define UART_S2_RWUID_MASK (0x8U)
mbed_official 121:7f86b4238bec 11449 #define UART_S2_RWUID_SHIFT (3U)
mbed_official 121:7f86b4238bec 11450 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
mbed_official 121:7f86b4238bec 11451 #define UART_S2_RXINV_MASK (0x10U)
mbed_official 121:7f86b4238bec 11452 #define UART_S2_RXINV_SHIFT (4U)
mbed_official 121:7f86b4238bec 11453 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
mbed_official 121:7f86b4238bec 11454 #define UART_S2_MSBF_MASK (0x20U)
mbed_official 121:7f86b4238bec 11455 #define UART_S2_MSBF_SHIFT (5U)
mbed_official 121:7f86b4238bec 11456 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
mbed_official 121:7f86b4238bec 11457 #define UART_S2_RXEDGIF_MASK (0x40U)
mbed_official 121:7f86b4238bec 11458 #define UART_S2_RXEDGIF_SHIFT (6U)
mbed_official 121:7f86b4238bec 11459 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
mbed_official 121:7f86b4238bec 11460 #define UART_S2_LBKDIF_MASK (0x80U)
mbed_official 121:7f86b4238bec 11461 #define UART_S2_LBKDIF_SHIFT (7U)
mbed_official 121:7f86b4238bec 11462 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
mbed_official 121:7f86b4238bec 11463
mbed_official 121:7f86b4238bec 11464 /*! @name C3 - UART Control Register 3 */
mbed_official 121:7f86b4238bec 11465 #define UART_C3_PEIE_MASK (0x1U)
mbed_official 121:7f86b4238bec 11466 #define UART_C3_PEIE_SHIFT (0U)
mbed_official 121:7f86b4238bec 11467 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
mbed_official 121:7f86b4238bec 11468 #define UART_C3_FEIE_MASK (0x2U)
mbed_official 121:7f86b4238bec 11469 #define UART_C3_FEIE_SHIFT (1U)
mbed_official 121:7f86b4238bec 11470 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
mbed_official 121:7f86b4238bec 11471 #define UART_C3_NEIE_MASK (0x4U)
mbed_official 121:7f86b4238bec 11472 #define UART_C3_NEIE_SHIFT (2U)
mbed_official 121:7f86b4238bec 11473 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
mbed_official 121:7f86b4238bec 11474 #define UART_C3_ORIE_MASK (0x8U)
mbed_official 121:7f86b4238bec 11475 #define UART_C3_ORIE_SHIFT (3U)
mbed_official 121:7f86b4238bec 11476 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
mbed_official 121:7f86b4238bec 11477 #define UART_C3_TXINV_MASK (0x10U)
mbed_official 121:7f86b4238bec 11478 #define UART_C3_TXINV_SHIFT (4U)
mbed_official 121:7f86b4238bec 11479 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
mbed_official 121:7f86b4238bec 11480 #define UART_C3_TXDIR_MASK (0x20U)
mbed_official 121:7f86b4238bec 11481 #define UART_C3_TXDIR_SHIFT (5U)
mbed_official 121:7f86b4238bec 11482 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
mbed_official 121:7f86b4238bec 11483 #define UART_C3_T8_MASK (0x40U)
mbed_official 121:7f86b4238bec 11484 #define UART_C3_T8_SHIFT (6U)
mbed_official 121:7f86b4238bec 11485 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
mbed_official 121:7f86b4238bec 11486 #define UART_C3_R8_MASK (0x80U)
mbed_official 121:7f86b4238bec 11487 #define UART_C3_R8_SHIFT (7U)
mbed_official 121:7f86b4238bec 11488 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
mbed_official 121:7f86b4238bec 11489
mbed_official 121:7f86b4238bec 11490 /*! @name D - UART Data Register */
mbed_official 121:7f86b4238bec 11491 #define UART_D_RT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11492 #define UART_D_RT_SHIFT (0U)
mbed_official 121:7f86b4238bec 11493 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
mbed_official 121:7f86b4238bec 11494
mbed_official 121:7f86b4238bec 11495 /*! @name MA1 - UART Match Address Registers 1 */
mbed_official 121:7f86b4238bec 11496 #define UART_MA1_MA_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11497 #define UART_MA1_MA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11498 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
mbed_official 121:7f86b4238bec 11499
mbed_official 121:7f86b4238bec 11500 /*! @name MA2 - UART Match Address Registers 2 */
mbed_official 121:7f86b4238bec 11501 #define UART_MA2_MA_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11502 #define UART_MA2_MA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11503 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
mbed_official 121:7f86b4238bec 11504
mbed_official 121:7f86b4238bec 11505 /*! @name C4 - UART Control Register 4 */
mbed_official 121:7f86b4238bec 11506 #define UART_C4_BRFA_MASK (0x1FU)
mbed_official 121:7f86b4238bec 11507 #define UART_C4_BRFA_SHIFT (0U)
mbed_official 121:7f86b4238bec 11508 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
mbed_official 121:7f86b4238bec 11509 #define UART_C4_M10_MASK (0x20U)
mbed_official 121:7f86b4238bec 11510 #define UART_C4_M10_SHIFT (5U)
mbed_official 121:7f86b4238bec 11511 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
mbed_official 121:7f86b4238bec 11512 #define UART_C4_MAEN2_MASK (0x40U)
mbed_official 121:7f86b4238bec 11513 #define UART_C4_MAEN2_SHIFT (6U)
mbed_official 121:7f86b4238bec 11514 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
mbed_official 121:7f86b4238bec 11515 #define UART_C4_MAEN1_MASK (0x80U)
mbed_official 121:7f86b4238bec 11516 #define UART_C4_MAEN1_SHIFT (7U)
mbed_official 121:7f86b4238bec 11517 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
mbed_official 121:7f86b4238bec 11518
mbed_official 121:7f86b4238bec 11519 /*! @name C5 - UART Control Register 5 */
mbed_official 121:7f86b4238bec 11520 #define UART_C5_LBKDDMAS_MASK (0x8U)
mbed_official 121:7f86b4238bec 11521 #define UART_C5_LBKDDMAS_SHIFT (3U)
mbed_official 121:7f86b4238bec 11522 #define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK)
mbed_official 121:7f86b4238bec 11523 #define UART_C5_ILDMAS_MASK (0x10U)
mbed_official 121:7f86b4238bec 11524 #define UART_C5_ILDMAS_SHIFT (4U)
mbed_official 121:7f86b4238bec 11525 #define UART_C5_ILDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_ILDMAS_SHIFT)) & UART_C5_ILDMAS_MASK)
mbed_official 121:7f86b4238bec 11526 #define UART_C5_RDMAS_MASK (0x20U)
mbed_official 121:7f86b4238bec 11527 #define UART_C5_RDMAS_SHIFT (5U)
mbed_official 121:7f86b4238bec 11528 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
mbed_official 121:7f86b4238bec 11529 #define UART_C5_TCDMAS_MASK (0x40U)
mbed_official 121:7f86b4238bec 11530 #define UART_C5_TCDMAS_SHIFT (6U)
mbed_official 121:7f86b4238bec 11531 #define UART_C5_TCDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TCDMAS_SHIFT)) & UART_C5_TCDMAS_MASK)
mbed_official 121:7f86b4238bec 11532 #define UART_C5_TDMAS_MASK (0x80U)
mbed_official 121:7f86b4238bec 11533 #define UART_C5_TDMAS_SHIFT (7U)
mbed_official 121:7f86b4238bec 11534 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
mbed_official 121:7f86b4238bec 11535
mbed_official 121:7f86b4238bec 11536 /*! @name ED - UART Extended Data Register */
mbed_official 121:7f86b4238bec 11537 #define UART_ED_PARITYE_MASK (0x40U)
mbed_official 121:7f86b4238bec 11538 #define UART_ED_PARITYE_SHIFT (6U)
mbed_official 121:7f86b4238bec 11539 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
mbed_official 121:7f86b4238bec 11540 #define UART_ED_NOISY_MASK (0x80U)
mbed_official 121:7f86b4238bec 11541 #define UART_ED_NOISY_SHIFT (7U)
mbed_official 121:7f86b4238bec 11542 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
mbed_official 121:7f86b4238bec 11543
mbed_official 121:7f86b4238bec 11544 /*! @name MODEM - UART Modem Register */
mbed_official 121:7f86b4238bec 11545 #define UART_MODEM_TXCTSE_MASK (0x1U)
mbed_official 121:7f86b4238bec 11546 #define UART_MODEM_TXCTSE_SHIFT (0U)
mbed_official 121:7f86b4238bec 11547 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
mbed_official 121:7f86b4238bec 11548 #define UART_MODEM_TXRTSE_MASK (0x2U)
mbed_official 121:7f86b4238bec 11549 #define UART_MODEM_TXRTSE_SHIFT (1U)
mbed_official 121:7f86b4238bec 11550 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
mbed_official 121:7f86b4238bec 11551 #define UART_MODEM_TXRTSPOL_MASK (0x4U)
mbed_official 121:7f86b4238bec 11552 #define UART_MODEM_TXRTSPOL_SHIFT (2U)
mbed_official 121:7f86b4238bec 11553 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
mbed_official 121:7f86b4238bec 11554 #define UART_MODEM_RXRTSE_MASK (0x8U)
mbed_official 121:7f86b4238bec 11555 #define UART_MODEM_RXRTSE_SHIFT (3U)
mbed_official 121:7f86b4238bec 11556 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
mbed_official 121:7f86b4238bec 11557
mbed_official 121:7f86b4238bec 11558 /*! @name IR - UART Infrared Register */
mbed_official 121:7f86b4238bec 11559 #define UART_IR_TNP_MASK (0x3U)
mbed_official 121:7f86b4238bec 11560 #define UART_IR_TNP_SHIFT (0U)
mbed_official 121:7f86b4238bec 11561 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
mbed_official 121:7f86b4238bec 11562 #define UART_IR_IREN_MASK (0x4U)
mbed_official 121:7f86b4238bec 11563 #define UART_IR_IREN_SHIFT (2U)
mbed_official 121:7f86b4238bec 11564 #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
mbed_official 121:7f86b4238bec 11565
mbed_official 121:7f86b4238bec 11566 /*! @name PFIFO - UART FIFO Parameters */
mbed_official 121:7f86b4238bec 11567 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
mbed_official 121:7f86b4238bec 11568 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
mbed_official 121:7f86b4238bec 11569 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
mbed_official 121:7f86b4238bec 11570 #define UART_PFIFO_RXFE_MASK (0x8U)
mbed_official 121:7f86b4238bec 11571 #define UART_PFIFO_RXFE_SHIFT (3U)
mbed_official 121:7f86b4238bec 11572 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
mbed_official 121:7f86b4238bec 11573 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
mbed_official 121:7f86b4238bec 11574 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
mbed_official 121:7f86b4238bec 11575 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
mbed_official 121:7f86b4238bec 11576 #define UART_PFIFO_TXFE_MASK (0x80U)
mbed_official 121:7f86b4238bec 11577 #define UART_PFIFO_TXFE_SHIFT (7U)
mbed_official 121:7f86b4238bec 11578 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
mbed_official 121:7f86b4238bec 11579
mbed_official 121:7f86b4238bec 11580 /*! @name CFIFO - UART FIFO Control Register */
mbed_official 121:7f86b4238bec 11581 #define UART_CFIFO_RXUFE_MASK (0x1U)
mbed_official 121:7f86b4238bec 11582 #define UART_CFIFO_RXUFE_SHIFT (0U)
mbed_official 121:7f86b4238bec 11583 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
mbed_official 121:7f86b4238bec 11584 #define UART_CFIFO_TXOFE_MASK (0x2U)
mbed_official 121:7f86b4238bec 11585 #define UART_CFIFO_TXOFE_SHIFT (1U)
mbed_official 121:7f86b4238bec 11586 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
mbed_official 121:7f86b4238bec 11587 #define UART_CFIFO_RXOFE_MASK (0x4U)
mbed_official 121:7f86b4238bec 11588 #define UART_CFIFO_RXOFE_SHIFT (2U)
mbed_official 121:7f86b4238bec 11589 #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
mbed_official 121:7f86b4238bec 11590 #define UART_CFIFO_RXFLUSH_MASK (0x40U)
mbed_official 121:7f86b4238bec 11591 #define UART_CFIFO_RXFLUSH_SHIFT (6U)
mbed_official 121:7f86b4238bec 11592 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
mbed_official 121:7f86b4238bec 11593 #define UART_CFIFO_TXFLUSH_MASK (0x80U)
mbed_official 121:7f86b4238bec 11594 #define UART_CFIFO_TXFLUSH_SHIFT (7U)
mbed_official 121:7f86b4238bec 11595 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
mbed_official 121:7f86b4238bec 11596
mbed_official 121:7f86b4238bec 11597 /*! @name SFIFO - UART FIFO Status Register */
mbed_official 121:7f86b4238bec 11598 #define UART_SFIFO_RXUF_MASK (0x1U)
mbed_official 121:7f86b4238bec 11599 #define UART_SFIFO_RXUF_SHIFT (0U)
mbed_official 121:7f86b4238bec 11600 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
mbed_official 121:7f86b4238bec 11601 #define UART_SFIFO_TXOF_MASK (0x2U)
mbed_official 121:7f86b4238bec 11602 #define UART_SFIFO_TXOF_SHIFT (1U)
mbed_official 121:7f86b4238bec 11603 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
mbed_official 121:7f86b4238bec 11604 #define UART_SFIFO_RXOF_MASK (0x4U)
mbed_official 121:7f86b4238bec 11605 #define UART_SFIFO_RXOF_SHIFT (2U)
mbed_official 121:7f86b4238bec 11606 #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
mbed_official 121:7f86b4238bec 11607 #define UART_SFIFO_RXEMPT_MASK (0x40U)
mbed_official 121:7f86b4238bec 11608 #define UART_SFIFO_RXEMPT_SHIFT (6U)
mbed_official 121:7f86b4238bec 11609 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
mbed_official 121:7f86b4238bec 11610 #define UART_SFIFO_TXEMPT_MASK (0x80U)
mbed_official 121:7f86b4238bec 11611 #define UART_SFIFO_TXEMPT_SHIFT (7U)
mbed_official 121:7f86b4238bec 11612 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
mbed_official 121:7f86b4238bec 11613
mbed_official 121:7f86b4238bec 11614 /*! @name TWFIFO - UART FIFO Transmit Watermark */
mbed_official 121:7f86b4238bec 11615 #define UART_TWFIFO_TXWATER_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11616 #define UART_TWFIFO_TXWATER_SHIFT (0U)
mbed_official 121:7f86b4238bec 11617 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
mbed_official 121:7f86b4238bec 11618
mbed_official 121:7f86b4238bec 11619 /*! @name TCFIFO - UART FIFO Transmit Count */
mbed_official 121:7f86b4238bec 11620 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11621 #define UART_TCFIFO_TXCOUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 11622 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
mbed_official 121:7f86b4238bec 11623
mbed_official 121:7f86b4238bec 11624 /*! @name RWFIFO - UART FIFO Receive Watermark */
mbed_official 121:7f86b4238bec 11625 #define UART_RWFIFO_RXWATER_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11626 #define UART_RWFIFO_RXWATER_SHIFT (0U)
mbed_official 121:7f86b4238bec 11627 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
mbed_official 121:7f86b4238bec 11628
mbed_official 121:7f86b4238bec 11629 /*! @name RCFIFO - UART FIFO Receive Count */
mbed_official 121:7f86b4238bec 11630 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11631 #define UART_RCFIFO_RXCOUNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 11632 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
mbed_official 121:7f86b4238bec 11633
mbed_official 121:7f86b4238bec 11634 /*! @name C7816 - UART 7816 Control Register */
mbed_official 121:7f86b4238bec 11635 #define UART_C7816_ISO_7816E_MASK (0x1U)
mbed_official 121:7f86b4238bec 11636 #define UART_C7816_ISO_7816E_SHIFT (0U)
mbed_official 121:7f86b4238bec 11637 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
mbed_official 121:7f86b4238bec 11638 #define UART_C7816_TTYPE_MASK (0x2U)
mbed_official 121:7f86b4238bec 11639 #define UART_C7816_TTYPE_SHIFT (1U)
mbed_official 121:7f86b4238bec 11640 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
mbed_official 121:7f86b4238bec 11641 #define UART_C7816_INIT_MASK (0x4U)
mbed_official 121:7f86b4238bec 11642 #define UART_C7816_INIT_SHIFT (2U)
mbed_official 121:7f86b4238bec 11643 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
mbed_official 121:7f86b4238bec 11644 #define UART_C7816_ANACK_MASK (0x8U)
mbed_official 121:7f86b4238bec 11645 #define UART_C7816_ANACK_SHIFT (3U)
mbed_official 121:7f86b4238bec 11646 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
mbed_official 121:7f86b4238bec 11647 #define UART_C7816_ONACK_MASK (0x10U)
mbed_official 121:7f86b4238bec 11648 #define UART_C7816_ONACK_SHIFT (4U)
mbed_official 121:7f86b4238bec 11649 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
mbed_official 121:7f86b4238bec 11650
mbed_official 121:7f86b4238bec 11651 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
mbed_official 121:7f86b4238bec 11652 #define UART_IE7816_RXTE_MASK (0x1U)
mbed_official 121:7f86b4238bec 11653 #define UART_IE7816_RXTE_SHIFT (0U)
mbed_official 121:7f86b4238bec 11654 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
mbed_official 121:7f86b4238bec 11655 #define UART_IE7816_TXTE_MASK (0x2U)
mbed_official 121:7f86b4238bec 11656 #define UART_IE7816_TXTE_SHIFT (1U)
mbed_official 121:7f86b4238bec 11657 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
mbed_official 121:7f86b4238bec 11658 #define UART_IE7816_GTVE_MASK (0x4U)
mbed_official 121:7f86b4238bec 11659 #define UART_IE7816_GTVE_SHIFT (2U)
mbed_official 121:7f86b4238bec 11660 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
mbed_official 121:7f86b4238bec 11661 #define UART_IE7816_INITDE_MASK (0x10U)
mbed_official 121:7f86b4238bec 11662 #define UART_IE7816_INITDE_SHIFT (4U)
mbed_official 121:7f86b4238bec 11663 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
mbed_official 121:7f86b4238bec 11664 #define UART_IE7816_BWTE_MASK (0x20U)
mbed_official 121:7f86b4238bec 11665 #define UART_IE7816_BWTE_SHIFT (5U)
mbed_official 121:7f86b4238bec 11666 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
mbed_official 121:7f86b4238bec 11667 #define UART_IE7816_CWTE_MASK (0x40U)
mbed_official 121:7f86b4238bec 11668 #define UART_IE7816_CWTE_SHIFT (6U)
mbed_official 121:7f86b4238bec 11669 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
mbed_official 121:7f86b4238bec 11670 #define UART_IE7816_WTE_MASK (0x80U)
mbed_official 121:7f86b4238bec 11671 #define UART_IE7816_WTE_SHIFT (7U)
mbed_official 121:7f86b4238bec 11672 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
mbed_official 121:7f86b4238bec 11673
mbed_official 121:7f86b4238bec 11674 /*! @name IS7816 - UART 7816 Interrupt Status Register */
mbed_official 121:7f86b4238bec 11675 #define UART_IS7816_RXT_MASK (0x1U)
mbed_official 121:7f86b4238bec 11676 #define UART_IS7816_RXT_SHIFT (0U)
mbed_official 121:7f86b4238bec 11677 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
mbed_official 121:7f86b4238bec 11678 #define UART_IS7816_TXT_MASK (0x2U)
mbed_official 121:7f86b4238bec 11679 #define UART_IS7816_TXT_SHIFT (1U)
mbed_official 121:7f86b4238bec 11680 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
mbed_official 121:7f86b4238bec 11681 #define UART_IS7816_GTV_MASK (0x4U)
mbed_official 121:7f86b4238bec 11682 #define UART_IS7816_GTV_SHIFT (2U)
mbed_official 121:7f86b4238bec 11683 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
mbed_official 121:7f86b4238bec 11684 #define UART_IS7816_INITD_MASK (0x10U)
mbed_official 121:7f86b4238bec 11685 #define UART_IS7816_INITD_SHIFT (4U)
mbed_official 121:7f86b4238bec 11686 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
mbed_official 121:7f86b4238bec 11687 #define UART_IS7816_BWT_MASK (0x20U)
mbed_official 121:7f86b4238bec 11688 #define UART_IS7816_BWT_SHIFT (5U)
mbed_official 121:7f86b4238bec 11689 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
mbed_official 121:7f86b4238bec 11690 #define UART_IS7816_CWT_MASK (0x40U)
mbed_official 121:7f86b4238bec 11691 #define UART_IS7816_CWT_SHIFT (6U)
mbed_official 121:7f86b4238bec 11692 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
mbed_official 121:7f86b4238bec 11693 #define UART_IS7816_WT_MASK (0x80U)
mbed_official 121:7f86b4238bec 11694 #define UART_IS7816_WT_SHIFT (7U)
mbed_official 121:7f86b4238bec 11695 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
mbed_official 121:7f86b4238bec 11696
mbed_official 121:7f86b4238bec 11697 /*! @name WP7816T0 - UART 7816 Wait Parameter Register */
mbed_official 121:7f86b4238bec 11698 #define UART_WP7816T0_WI_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11699 #define UART_WP7816T0_WI_SHIFT (0U)
mbed_official 121:7f86b4238bec 11700 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
mbed_official 121:7f86b4238bec 11701
mbed_official 121:7f86b4238bec 11702 /*! @name WP7816T1 - UART 7816 Wait Parameter Register */
mbed_official 121:7f86b4238bec 11703 #define UART_WP7816T1_BWI_MASK (0xFU)
mbed_official 121:7f86b4238bec 11704 #define UART_WP7816T1_BWI_SHIFT (0U)
mbed_official 121:7f86b4238bec 11705 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
mbed_official 121:7f86b4238bec 11706 #define UART_WP7816T1_CWI_MASK (0xF0U)
mbed_official 121:7f86b4238bec 11707 #define UART_WP7816T1_CWI_SHIFT (4U)
mbed_official 121:7f86b4238bec 11708 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
mbed_official 121:7f86b4238bec 11709
mbed_official 121:7f86b4238bec 11710 /*! @name WN7816 - UART 7816 Wait N Register */
mbed_official 121:7f86b4238bec 11711 #define UART_WN7816_GTN_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11712 #define UART_WN7816_GTN_SHIFT (0U)
mbed_official 121:7f86b4238bec 11713 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
mbed_official 121:7f86b4238bec 11714
mbed_official 121:7f86b4238bec 11715 /*! @name WF7816 - UART 7816 Wait FD Register */
mbed_official 121:7f86b4238bec 11716 #define UART_WF7816_GTFD_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11717 #define UART_WF7816_GTFD_SHIFT (0U)
mbed_official 121:7f86b4238bec 11718 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
mbed_official 121:7f86b4238bec 11719
mbed_official 121:7f86b4238bec 11720 /*! @name ET7816 - UART 7816 Error Threshold Register */
mbed_official 121:7f86b4238bec 11721 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
mbed_official 121:7f86b4238bec 11722 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
mbed_official 121:7f86b4238bec 11723 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
mbed_official 121:7f86b4238bec 11724 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
mbed_official 121:7f86b4238bec 11725 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
mbed_official 121:7f86b4238bec 11726 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
mbed_official 121:7f86b4238bec 11727
mbed_official 121:7f86b4238bec 11728 /*! @name TL7816 - UART 7816 Transmit Length Register */
mbed_official 121:7f86b4238bec 11729 #define UART_TL7816_TLEN_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11730 #define UART_TL7816_TLEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 11731 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
mbed_official 121:7f86b4238bec 11732
mbed_official 121:7f86b4238bec 11733
mbed_official 121:7f86b4238bec 11734 /*!
mbed_official 121:7f86b4238bec 11735 * @}
mbed_official 121:7f86b4238bec 11736 */ /* end of group UART_Register_Masks */
mbed_official 121:7f86b4238bec 11737
mbed_official 121:7f86b4238bec 11738
mbed_official 121:7f86b4238bec 11739 /* UART - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 11740 /** Peripheral UART0 base address */
mbed_official 121:7f86b4238bec 11741 #define UART0_BASE (0x4006A000u)
mbed_official 121:7f86b4238bec 11742 /** Peripheral UART0 base pointer */
mbed_official 121:7f86b4238bec 11743 #define UART0 ((UART_Type *)UART0_BASE)
mbed_official 121:7f86b4238bec 11744 /** Peripheral UART1 base address */
mbed_official 121:7f86b4238bec 11745 #define UART1_BASE (0x4006B000u)
mbed_official 121:7f86b4238bec 11746 /** Peripheral UART1 base pointer */
mbed_official 121:7f86b4238bec 11747 #define UART1 ((UART_Type *)UART1_BASE)
mbed_official 121:7f86b4238bec 11748 /** Peripheral UART2 base address */
mbed_official 121:7f86b4238bec 11749 #define UART2_BASE (0x4006C000u)
mbed_official 121:7f86b4238bec 11750 /** Peripheral UART2 base pointer */
mbed_official 121:7f86b4238bec 11751 #define UART2 ((UART_Type *)UART2_BASE)
mbed_official 121:7f86b4238bec 11752 /** Peripheral UART3 base address */
mbed_official 121:7f86b4238bec 11753 #define UART3_BASE (0x4006D000u)
mbed_official 121:7f86b4238bec 11754 /** Peripheral UART3 base pointer */
mbed_official 121:7f86b4238bec 11755 #define UART3 ((UART_Type *)UART3_BASE)
mbed_official 121:7f86b4238bec 11756 /** Peripheral UART4 base address */
mbed_official 121:7f86b4238bec 11757 #define UART4_BASE (0x400EA000u)
mbed_official 121:7f86b4238bec 11758 /** Peripheral UART4 base pointer */
mbed_official 121:7f86b4238bec 11759 #define UART4 ((UART_Type *)UART4_BASE)
mbed_official 121:7f86b4238bec 11760 /** Peripheral UART5 base address */
mbed_official 121:7f86b4238bec 11761 #define UART5_BASE (0x400EB000u)
mbed_official 121:7f86b4238bec 11762 /** Peripheral UART5 base pointer */
mbed_official 121:7f86b4238bec 11763 #define UART5 ((UART_Type *)UART5_BASE)
mbed_official 121:7f86b4238bec 11764 /** Array initializer of UART peripheral base addresses */
mbed_official 121:7f86b4238bec 11765 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
mbed_official 121:7f86b4238bec 11766 /** Array initializer of UART peripheral base pointers */
mbed_official 121:7f86b4238bec 11767 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
mbed_official 121:7f86b4238bec 11768 /** Interrupt vectors for the UART peripheral type */
mbed_official 121:7f86b4238bec 11769 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
mbed_official 121:7f86b4238bec 11770 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
mbed_official 121:7f86b4238bec 11771 #define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
mbed_official 121:7f86b4238bec 11772
mbed_official 121:7f86b4238bec 11773 /*!
mbed_official 121:7f86b4238bec 11774 * @}
mbed_official 121:7f86b4238bec 11775 */ /* end of group UART_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 11776
mbed_official 121:7f86b4238bec 11777
mbed_official 121:7f86b4238bec 11778 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 11779 -- USB Peripheral Access Layer
mbed_official 121:7f86b4238bec 11780 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 11781
mbed_official 121:7f86b4238bec 11782 /*!
mbed_official 121:7f86b4238bec 11783 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
mbed_official 121:7f86b4238bec 11784 * @{
mbed_official 121:7f86b4238bec 11785 */
mbed_official 121:7f86b4238bec 11786
mbed_official 121:7f86b4238bec 11787 /** USB - Register Layout Typedef */
mbed_official 121:7f86b4238bec 11788 typedef struct {
mbed_official 121:7f86b4238bec 11789 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
mbed_official 121:7f86b4238bec 11790 uint8_t RESERVED_0[3];
mbed_official 121:7f86b4238bec 11791 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
mbed_official 121:7f86b4238bec 11792 uint8_t RESERVED_1[3];
mbed_official 121:7f86b4238bec 11793 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
mbed_official 121:7f86b4238bec 11794 uint8_t RESERVED_2[3];
mbed_official 121:7f86b4238bec 11795 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
mbed_official 121:7f86b4238bec 11796 uint8_t RESERVED_3[3];
mbed_official 121:7f86b4238bec 11797 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
mbed_official 121:7f86b4238bec 11798 uint8_t RESERVED_4[3];
mbed_official 121:7f86b4238bec 11799 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
mbed_official 121:7f86b4238bec 11800 uint8_t RESERVED_5[3];
mbed_official 121:7f86b4238bec 11801 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
mbed_official 121:7f86b4238bec 11802 uint8_t RESERVED_6[3];
mbed_official 121:7f86b4238bec 11803 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
mbed_official 121:7f86b4238bec 11804 uint8_t RESERVED_7[99];
mbed_official 121:7f86b4238bec 11805 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
mbed_official 121:7f86b4238bec 11806 uint8_t RESERVED_8[3];
mbed_official 121:7f86b4238bec 11807 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
mbed_official 121:7f86b4238bec 11808 uint8_t RESERVED_9[3];
mbed_official 121:7f86b4238bec 11809 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
mbed_official 121:7f86b4238bec 11810 uint8_t RESERVED_10[3];
mbed_official 121:7f86b4238bec 11811 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
mbed_official 121:7f86b4238bec 11812 uint8_t RESERVED_11[3];
mbed_official 121:7f86b4238bec 11813 __I uint8_t STAT; /**< Status register, offset: 0x90 */
mbed_official 121:7f86b4238bec 11814 uint8_t RESERVED_12[3];
mbed_official 121:7f86b4238bec 11815 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
mbed_official 121:7f86b4238bec 11816 uint8_t RESERVED_13[3];
mbed_official 121:7f86b4238bec 11817 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
mbed_official 121:7f86b4238bec 11818 uint8_t RESERVED_14[3];
mbed_official 121:7f86b4238bec 11819 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
mbed_official 121:7f86b4238bec 11820 uint8_t RESERVED_15[3];
mbed_official 121:7f86b4238bec 11821 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
mbed_official 121:7f86b4238bec 11822 uint8_t RESERVED_16[3];
mbed_official 121:7f86b4238bec 11823 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
mbed_official 121:7f86b4238bec 11824 uint8_t RESERVED_17[3];
mbed_official 121:7f86b4238bec 11825 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
mbed_official 121:7f86b4238bec 11826 uint8_t RESERVED_18[3];
mbed_official 121:7f86b4238bec 11827 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
mbed_official 121:7f86b4238bec 11828 uint8_t RESERVED_19[3];
mbed_official 121:7f86b4238bec 11829 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
mbed_official 121:7f86b4238bec 11830 uint8_t RESERVED_20[3];
mbed_official 121:7f86b4238bec 11831 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
mbed_official 121:7f86b4238bec 11832 uint8_t RESERVED_21[11];
mbed_official 121:7f86b4238bec 11833 struct { /* offset: 0xC0, array step: 0x4 */
mbed_official 121:7f86b4238bec 11834 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
mbed_official 121:7f86b4238bec 11835 uint8_t RESERVED_0[3];
mbed_official 121:7f86b4238bec 11836 } ENDPOINT[16];
mbed_official 121:7f86b4238bec 11837 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
mbed_official 121:7f86b4238bec 11838 uint8_t RESERVED_22[3];
mbed_official 121:7f86b4238bec 11839 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
mbed_official 121:7f86b4238bec 11840 uint8_t RESERVED_23[3];
mbed_official 121:7f86b4238bec 11841 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
mbed_official 121:7f86b4238bec 11842 uint8_t RESERVED_24[3];
mbed_official 121:7f86b4238bec 11843 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
mbed_official 121:7f86b4238bec 11844 uint8_t RESERVED_25[7];
mbed_official 121:7f86b4238bec 11845 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
mbed_official 121:7f86b4238bec 11846 uint8_t RESERVED_26[43];
mbed_official 121:7f86b4238bec 11847 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
mbed_official 121:7f86b4238bec 11848 uint8_t RESERVED_27[3];
mbed_official 121:7f86b4238bec 11849 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
mbed_official 121:7f86b4238bec 11850 uint8_t RESERVED_28[23];
mbed_official 121:7f86b4238bec 11851 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
mbed_official 121:7f86b4238bec 11852 } USB_Type;
mbed_official 121:7f86b4238bec 11853
mbed_official 121:7f86b4238bec 11854 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 11855 -- USB Register Masks
mbed_official 121:7f86b4238bec 11856 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 11857
mbed_official 121:7f86b4238bec 11858 /*!
mbed_official 121:7f86b4238bec 11859 * @addtogroup USB_Register_Masks USB Register Masks
mbed_official 121:7f86b4238bec 11860 * @{
mbed_official 121:7f86b4238bec 11861 */
mbed_official 121:7f86b4238bec 11862
mbed_official 121:7f86b4238bec 11863 /*! @name PERID - Peripheral ID register */
mbed_official 121:7f86b4238bec 11864 #define USB_PERID_ID_MASK (0x3FU)
mbed_official 121:7f86b4238bec 11865 #define USB_PERID_ID_SHIFT (0U)
mbed_official 121:7f86b4238bec 11866 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
mbed_official 121:7f86b4238bec 11867
mbed_official 121:7f86b4238bec 11868 /*! @name IDCOMP - Peripheral ID Complement register */
mbed_official 121:7f86b4238bec 11869 #define USB_IDCOMP_NID_MASK (0x3FU)
mbed_official 121:7f86b4238bec 11870 #define USB_IDCOMP_NID_SHIFT (0U)
mbed_official 121:7f86b4238bec 11871 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
mbed_official 121:7f86b4238bec 11872
mbed_official 121:7f86b4238bec 11873 /*! @name REV - Peripheral Revision register */
mbed_official 121:7f86b4238bec 11874 #define USB_REV_REV_MASK (0xFFU)
mbed_official 121:7f86b4238bec 11875 #define USB_REV_REV_SHIFT (0U)
mbed_official 121:7f86b4238bec 11876 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
mbed_official 121:7f86b4238bec 11877
mbed_official 121:7f86b4238bec 11878 /*! @name ADDINFO - Peripheral Additional Info register */
mbed_official 121:7f86b4238bec 11879 #define USB_ADDINFO_IEHOST_MASK (0x1U)
mbed_official 121:7f86b4238bec 11880 #define USB_ADDINFO_IEHOST_SHIFT (0U)
mbed_official 121:7f86b4238bec 11881 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
mbed_official 121:7f86b4238bec 11882 #define USB_ADDINFO_IRQNUM_MASK (0xF8U)
mbed_official 121:7f86b4238bec 11883 #define USB_ADDINFO_IRQNUM_SHIFT (3U)
mbed_official 121:7f86b4238bec 11884 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
mbed_official 121:7f86b4238bec 11885
mbed_official 121:7f86b4238bec 11886 /*! @name OTGISTAT - OTG Interrupt Status register */
mbed_official 121:7f86b4238bec 11887 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
mbed_official 121:7f86b4238bec 11888 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
mbed_official 121:7f86b4238bec 11889 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
mbed_official 121:7f86b4238bec 11890 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
mbed_official 121:7f86b4238bec 11891 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
mbed_official 121:7f86b4238bec 11892 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
mbed_official 121:7f86b4238bec 11893 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
mbed_official 121:7f86b4238bec 11894 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
mbed_official 121:7f86b4238bec 11895 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
mbed_official 121:7f86b4238bec 11896 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
mbed_official 121:7f86b4238bec 11897 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
mbed_official 121:7f86b4238bec 11898 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
mbed_official 121:7f86b4238bec 11899 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
mbed_official 121:7f86b4238bec 11900 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
mbed_official 121:7f86b4238bec 11901 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
mbed_official 121:7f86b4238bec 11902 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
mbed_official 121:7f86b4238bec 11903 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
mbed_official 121:7f86b4238bec 11904 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
mbed_official 121:7f86b4238bec 11905
mbed_official 121:7f86b4238bec 11906 /*! @name OTGICR - OTG Interrupt Control register */
mbed_official 121:7f86b4238bec 11907 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 11908 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 11909 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
mbed_official 121:7f86b4238bec 11910 #define USB_OTGICR_BSESSEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 11911 #define USB_OTGICR_BSESSEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 11912 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
mbed_official 121:7f86b4238bec 11913 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 11914 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 11915 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
mbed_official 121:7f86b4238bec 11916 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 11917 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 11918 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
mbed_official 121:7f86b4238bec 11919 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 11920 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 11921 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
mbed_official 121:7f86b4238bec 11922 #define USB_OTGICR_IDEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 11923 #define USB_OTGICR_IDEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 11924 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
mbed_official 121:7f86b4238bec 11925
mbed_official 121:7f86b4238bec 11926 /*! @name OTGSTAT - OTG Status register */
mbed_official 121:7f86b4238bec 11927 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
mbed_official 121:7f86b4238bec 11928 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
mbed_official 121:7f86b4238bec 11929 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
mbed_official 121:7f86b4238bec 11930 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
mbed_official 121:7f86b4238bec 11931 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
mbed_official 121:7f86b4238bec 11932 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
mbed_official 121:7f86b4238bec 11933 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
mbed_official 121:7f86b4238bec 11934 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
mbed_official 121:7f86b4238bec 11935 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
mbed_official 121:7f86b4238bec 11936 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
mbed_official 121:7f86b4238bec 11937 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
mbed_official 121:7f86b4238bec 11938 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
mbed_official 121:7f86b4238bec 11939 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 11940 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 11941 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
mbed_official 121:7f86b4238bec 11942 #define USB_OTGSTAT_ID_MASK (0x80U)
mbed_official 121:7f86b4238bec 11943 #define USB_OTGSTAT_ID_SHIFT (7U)
mbed_official 121:7f86b4238bec 11944 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
mbed_official 121:7f86b4238bec 11945
mbed_official 121:7f86b4238bec 11946 /*! @name OTGCTL - OTG Control register */
mbed_official 121:7f86b4238bec 11947 #define USB_OTGCTL_OTGEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 11948 #define USB_OTGCTL_OTGEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 11949 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
mbed_official 121:7f86b4238bec 11950 #define USB_OTGCTL_DMLOW_MASK (0x10U)
mbed_official 121:7f86b4238bec 11951 #define USB_OTGCTL_DMLOW_SHIFT (4U)
mbed_official 121:7f86b4238bec 11952 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
mbed_official 121:7f86b4238bec 11953 #define USB_OTGCTL_DPLOW_MASK (0x20U)
mbed_official 121:7f86b4238bec 11954 #define USB_OTGCTL_DPLOW_SHIFT (5U)
mbed_official 121:7f86b4238bec 11955 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
mbed_official 121:7f86b4238bec 11956 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
mbed_official 121:7f86b4238bec 11957 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
mbed_official 121:7f86b4238bec 11958 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
mbed_official 121:7f86b4238bec 11959
mbed_official 121:7f86b4238bec 11960 /*! @name ISTAT - Interrupt Status register */
mbed_official 121:7f86b4238bec 11961 #define USB_ISTAT_USBRST_MASK (0x1U)
mbed_official 121:7f86b4238bec 11962 #define USB_ISTAT_USBRST_SHIFT (0U)
mbed_official 121:7f86b4238bec 11963 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
mbed_official 121:7f86b4238bec 11964 #define USB_ISTAT_ERROR_MASK (0x2U)
mbed_official 121:7f86b4238bec 11965 #define USB_ISTAT_ERROR_SHIFT (1U)
mbed_official 121:7f86b4238bec 11966 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
mbed_official 121:7f86b4238bec 11967 #define USB_ISTAT_SOFTOK_MASK (0x4U)
mbed_official 121:7f86b4238bec 11968 #define USB_ISTAT_SOFTOK_SHIFT (2U)
mbed_official 121:7f86b4238bec 11969 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
mbed_official 121:7f86b4238bec 11970 #define USB_ISTAT_TOKDNE_MASK (0x8U)
mbed_official 121:7f86b4238bec 11971 #define USB_ISTAT_TOKDNE_SHIFT (3U)
mbed_official 121:7f86b4238bec 11972 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
mbed_official 121:7f86b4238bec 11973 #define USB_ISTAT_SLEEP_MASK (0x10U)
mbed_official 121:7f86b4238bec 11974 #define USB_ISTAT_SLEEP_SHIFT (4U)
mbed_official 121:7f86b4238bec 11975 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
mbed_official 121:7f86b4238bec 11976 #define USB_ISTAT_RESUME_MASK (0x20U)
mbed_official 121:7f86b4238bec 11977 #define USB_ISTAT_RESUME_SHIFT (5U)
mbed_official 121:7f86b4238bec 11978 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
mbed_official 121:7f86b4238bec 11979 #define USB_ISTAT_ATTACH_MASK (0x40U)
mbed_official 121:7f86b4238bec 11980 #define USB_ISTAT_ATTACH_SHIFT (6U)
mbed_official 121:7f86b4238bec 11981 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
mbed_official 121:7f86b4238bec 11982 #define USB_ISTAT_STALL_MASK (0x80U)
mbed_official 121:7f86b4238bec 11983 #define USB_ISTAT_STALL_SHIFT (7U)
mbed_official 121:7f86b4238bec 11984 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
mbed_official 121:7f86b4238bec 11985
mbed_official 121:7f86b4238bec 11986 /*! @name INTEN - Interrupt Enable register */
mbed_official 121:7f86b4238bec 11987 #define USB_INTEN_USBRSTEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 11988 #define USB_INTEN_USBRSTEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 11989 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
mbed_official 121:7f86b4238bec 11990 #define USB_INTEN_ERROREN_MASK (0x2U)
mbed_official 121:7f86b4238bec 11991 #define USB_INTEN_ERROREN_SHIFT (1U)
mbed_official 121:7f86b4238bec 11992 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
mbed_official 121:7f86b4238bec 11993 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 11994 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 11995 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
mbed_official 121:7f86b4238bec 11996 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 11997 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 11998 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
mbed_official 121:7f86b4238bec 11999 #define USB_INTEN_SLEEPEN_MASK (0x10U)
mbed_official 121:7f86b4238bec 12000 #define USB_INTEN_SLEEPEN_SHIFT (4U)
mbed_official 121:7f86b4238bec 12001 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
mbed_official 121:7f86b4238bec 12002 #define USB_INTEN_RESUMEEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 12003 #define USB_INTEN_RESUMEEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 12004 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
mbed_official 121:7f86b4238bec 12005 #define USB_INTEN_ATTACHEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 12006 #define USB_INTEN_ATTACHEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 12007 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
mbed_official 121:7f86b4238bec 12008 #define USB_INTEN_STALLEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 12009 #define USB_INTEN_STALLEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 12010 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
mbed_official 121:7f86b4238bec 12011
mbed_official 121:7f86b4238bec 12012 /*! @name ERRSTAT - Error Interrupt Status register */
mbed_official 121:7f86b4238bec 12013 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
mbed_official 121:7f86b4238bec 12014 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
mbed_official 121:7f86b4238bec 12015 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
mbed_official 121:7f86b4238bec 12016 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
mbed_official 121:7f86b4238bec 12017 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
mbed_official 121:7f86b4238bec 12018 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
mbed_official 121:7f86b4238bec 12019 #define USB_ERRSTAT_CRC16_MASK (0x4U)
mbed_official 121:7f86b4238bec 12020 #define USB_ERRSTAT_CRC16_SHIFT (2U)
mbed_official 121:7f86b4238bec 12021 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
mbed_official 121:7f86b4238bec 12022 #define USB_ERRSTAT_DFN8_MASK (0x8U)
mbed_official 121:7f86b4238bec 12023 #define USB_ERRSTAT_DFN8_SHIFT (3U)
mbed_official 121:7f86b4238bec 12024 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
mbed_official 121:7f86b4238bec 12025 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
mbed_official 121:7f86b4238bec 12026 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
mbed_official 121:7f86b4238bec 12027 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
mbed_official 121:7f86b4238bec 12028 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
mbed_official 121:7f86b4238bec 12029 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
mbed_official 121:7f86b4238bec 12030 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
mbed_official 121:7f86b4238bec 12031 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
mbed_official 121:7f86b4238bec 12032 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
mbed_official 121:7f86b4238bec 12033 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
mbed_official 121:7f86b4238bec 12034
mbed_official 121:7f86b4238bec 12035 /*! @name ERREN - Error Interrupt Enable register */
mbed_official 121:7f86b4238bec 12036 #define USB_ERREN_PIDERREN_MASK (0x1U)
mbed_official 121:7f86b4238bec 12037 #define USB_ERREN_PIDERREN_SHIFT (0U)
mbed_official 121:7f86b4238bec 12038 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
mbed_official 121:7f86b4238bec 12039 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
mbed_official 121:7f86b4238bec 12040 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
mbed_official 121:7f86b4238bec 12041 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
mbed_official 121:7f86b4238bec 12042 #define USB_ERREN_CRC16EN_MASK (0x4U)
mbed_official 121:7f86b4238bec 12043 #define USB_ERREN_CRC16EN_SHIFT (2U)
mbed_official 121:7f86b4238bec 12044 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
mbed_official 121:7f86b4238bec 12045 #define USB_ERREN_DFN8EN_MASK (0x8U)
mbed_official 121:7f86b4238bec 12046 #define USB_ERREN_DFN8EN_SHIFT (3U)
mbed_official 121:7f86b4238bec 12047 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
mbed_official 121:7f86b4238bec 12048 #define USB_ERREN_BTOERREN_MASK (0x10U)
mbed_official 121:7f86b4238bec 12049 #define USB_ERREN_BTOERREN_SHIFT (4U)
mbed_official 121:7f86b4238bec 12050 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
mbed_official 121:7f86b4238bec 12051 #define USB_ERREN_DMAERREN_MASK (0x20U)
mbed_official 121:7f86b4238bec 12052 #define USB_ERREN_DMAERREN_SHIFT (5U)
mbed_official 121:7f86b4238bec 12053 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
mbed_official 121:7f86b4238bec 12054 #define USB_ERREN_BTSERREN_MASK (0x80U)
mbed_official 121:7f86b4238bec 12055 #define USB_ERREN_BTSERREN_SHIFT (7U)
mbed_official 121:7f86b4238bec 12056 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
mbed_official 121:7f86b4238bec 12057
mbed_official 121:7f86b4238bec 12058 /*! @name STAT - Status register */
mbed_official 121:7f86b4238bec 12059 #define USB_STAT_ODD_MASK (0x4U)
mbed_official 121:7f86b4238bec 12060 #define USB_STAT_ODD_SHIFT (2U)
mbed_official 121:7f86b4238bec 12061 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
mbed_official 121:7f86b4238bec 12062 #define USB_STAT_TX_MASK (0x8U)
mbed_official 121:7f86b4238bec 12063 #define USB_STAT_TX_SHIFT (3U)
mbed_official 121:7f86b4238bec 12064 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
mbed_official 121:7f86b4238bec 12065 #define USB_STAT_ENDP_MASK (0xF0U)
mbed_official 121:7f86b4238bec 12066 #define USB_STAT_ENDP_SHIFT (4U)
mbed_official 121:7f86b4238bec 12067 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
mbed_official 121:7f86b4238bec 12068
mbed_official 121:7f86b4238bec 12069 /*! @name CTL - Control register */
mbed_official 121:7f86b4238bec 12070 #define USB_CTL_USBENSOFEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 12071 #define USB_CTL_USBENSOFEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 12072 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
mbed_official 121:7f86b4238bec 12073 #define USB_CTL_ODDRST_MASK (0x2U)
mbed_official 121:7f86b4238bec 12074 #define USB_CTL_ODDRST_SHIFT (1U)
mbed_official 121:7f86b4238bec 12075 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
mbed_official 121:7f86b4238bec 12076 #define USB_CTL_RESUME_MASK (0x4U)
mbed_official 121:7f86b4238bec 12077 #define USB_CTL_RESUME_SHIFT (2U)
mbed_official 121:7f86b4238bec 12078 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
mbed_official 121:7f86b4238bec 12079 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 12080 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 12081 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
mbed_official 121:7f86b4238bec 12082 #define USB_CTL_RESET_MASK (0x10U)
mbed_official 121:7f86b4238bec 12083 #define USB_CTL_RESET_SHIFT (4U)
mbed_official 121:7f86b4238bec 12084 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
mbed_official 121:7f86b4238bec 12085 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
mbed_official 121:7f86b4238bec 12086 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
mbed_official 121:7f86b4238bec 12087 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
mbed_official 121:7f86b4238bec 12088 #define USB_CTL_SE0_MASK (0x40U)
mbed_official 121:7f86b4238bec 12089 #define USB_CTL_SE0_SHIFT (6U)
mbed_official 121:7f86b4238bec 12090 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
mbed_official 121:7f86b4238bec 12091 #define USB_CTL_JSTATE_MASK (0x80U)
mbed_official 121:7f86b4238bec 12092 #define USB_CTL_JSTATE_SHIFT (7U)
mbed_official 121:7f86b4238bec 12093 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
mbed_official 121:7f86b4238bec 12094
mbed_official 121:7f86b4238bec 12095 /*! @name ADDR - Address register */
mbed_official 121:7f86b4238bec 12096 #define USB_ADDR_ADDR_MASK (0x7FU)
mbed_official 121:7f86b4238bec 12097 #define USB_ADDR_ADDR_SHIFT (0U)
mbed_official 121:7f86b4238bec 12098 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
mbed_official 121:7f86b4238bec 12099 #define USB_ADDR_LSEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 12100 #define USB_ADDR_LSEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 12101 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
mbed_official 121:7f86b4238bec 12102
mbed_official 121:7f86b4238bec 12103 /*! @name BDTPAGE1 - BDT Page register 1 */
mbed_official 121:7f86b4238bec 12104 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
mbed_official 121:7f86b4238bec 12105 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
mbed_official 121:7f86b4238bec 12106 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
mbed_official 121:7f86b4238bec 12107
mbed_official 121:7f86b4238bec 12108 /*! @name FRMNUML - Frame Number register Low */
mbed_official 121:7f86b4238bec 12109 #define USB_FRMNUML_FRM_MASK (0xFFU)
mbed_official 121:7f86b4238bec 12110 #define USB_FRMNUML_FRM_SHIFT (0U)
mbed_official 121:7f86b4238bec 12111 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
mbed_official 121:7f86b4238bec 12112
mbed_official 121:7f86b4238bec 12113 /*! @name FRMNUMH - Frame Number register High */
mbed_official 121:7f86b4238bec 12114 #define USB_FRMNUMH_FRM_MASK (0x7U)
mbed_official 121:7f86b4238bec 12115 #define USB_FRMNUMH_FRM_SHIFT (0U)
mbed_official 121:7f86b4238bec 12116 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
mbed_official 121:7f86b4238bec 12117
mbed_official 121:7f86b4238bec 12118 /*! @name TOKEN - Token register */
mbed_official 121:7f86b4238bec 12119 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
mbed_official 121:7f86b4238bec 12120 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
mbed_official 121:7f86b4238bec 12121 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
mbed_official 121:7f86b4238bec 12122 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
mbed_official 121:7f86b4238bec 12123 #define USB_TOKEN_TOKENPID_SHIFT (4U)
mbed_official 121:7f86b4238bec 12124 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
mbed_official 121:7f86b4238bec 12125
mbed_official 121:7f86b4238bec 12126 /*! @name SOFTHLD - SOF Threshold register */
mbed_official 121:7f86b4238bec 12127 #define USB_SOFTHLD_CNT_MASK (0xFFU)
mbed_official 121:7f86b4238bec 12128 #define USB_SOFTHLD_CNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 12129 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
mbed_official 121:7f86b4238bec 12130
mbed_official 121:7f86b4238bec 12131 /*! @name BDTPAGE2 - BDT Page Register 2 */
mbed_official 121:7f86b4238bec 12132 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
mbed_official 121:7f86b4238bec 12133 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
mbed_official 121:7f86b4238bec 12134 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
mbed_official 121:7f86b4238bec 12135
mbed_official 121:7f86b4238bec 12136 /*! @name BDTPAGE3 - BDT Page Register 3 */
mbed_official 121:7f86b4238bec 12137 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
mbed_official 121:7f86b4238bec 12138 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
mbed_official 121:7f86b4238bec 12139 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
mbed_official 121:7f86b4238bec 12140
mbed_official 121:7f86b4238bec 12141 /*! @name ENDPT - Endpoint Control register */
mbed_official 121:7f86b4238bec 12142 #define USB_ENDPT_EPHSHK_MASK (0x1U)
mbed_official 121:7f86b4238bec 12143 #define USB_ENDPT_EPHSHK_SHIFT (0U)
mbed_official 121:7f86b4238bec 12144 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
mbed_official 121:7f86b4238bec 12145 #define USB_ENDPT_EPSTALL_MASK (0x2U)
mbed_official 121:7f86b4238bec 12146 #define USB_ENDPT_EPSTALL_SHIFT (1U)
mbed_official 121:7f86b4238bec 12147 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
mbed_official 121:7f86b4238bec 12148 #define USB_ENDPT_EPTXEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 12149 #define USB_ENDPT_EPTXEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 12150 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
mbed_official 121:7f86b4238bec 12151 #define USB_ENDPT_EPRXEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 12152 #define USB_ENDPT_EPRXEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 12153 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
mbed_official 121:7f86b4238bec 12154 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
mbed_official 121:7f86b4238bec 12155 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
mbed_official 121:7f86b4238bec 12156 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
mbed_official 121:7f86b4238bec 12157 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
mbed_official 121:7f86b4238bec 12158 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
mbed_official 121:7f86b4238bec 12159 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
mbed_official 121:7f86b4238bec 12160 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
mbed_official 121:7f86b4238bec 12161 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
mbed_official 121:7f86b4238bec 12162 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
mbed_official 121:7f86b4238bec 12163
mbed_official 121:7f86b4238bec 12164 /* The count of USB_ENDPT */
mbed_official 121:7f86b4238bec 12165 #define USB_ENDPT_COUNT (16U)
mbed_official 121:7f86b4238bec 12166
mbed_official 121:7f86b4238bec 12167 /*! @name USBCTRL - USB Control register */
mbed_official 121:7f86b4238bec 12168 #define USB_USBCTRL_PDE_MASK (0x40U)
mbed_official 121:7f86b4238bec 12169 #define USB_USBCTRL_PDE_SHIFT (6U)
mbed_official 121:7f86b4238bec 12170 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
mbed_official 121:7f86b4238bec 12171 #define USB_USBCTRL_SUSP_MASK (0x80U)
mbed_official 121:7f86b4238bec 12172 #define USB_USBCTRL_SUSP_SHIFT (7U)
mbed_official 121:7f86b4238bec 12173 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
mbed_official 121:7f86b4238bec 12174
mbed_official 121:7f86b4238bec 12175 /*! @name OBSERVE - USB OTG Observe register */
mbed_official 121:7f86b4238bec 12176 #define USB_OBSERVE_DMPD_MASK (0x10U)
mbed_official 121:7f86b4238bec 12177 #define USB_OBSERVE_DMPD_SHIFT (4U)
mbed_official 121:7f86b4238bec 12178 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
mbed_official 121:7f86b4238bec 12179 #define USB_OBSERVE_DPPD_MASK (0x40U)
mbed_official 121:7f86b4238bec 12180 #define USB_OBSERVE_DPPD_SHIFT (6U)
mbed_official 121:7f86b4238bec 12181 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
mbed_official 121:7f86b4238bec 12182 #define USB_OBSERVE_DPPU_MASK (0x80U)
mbed_official 121:7f86b4238bec 12183 #define USB_OBSERVE_DPPU_SHIFT (7U)
mbed_official 121:7f86b4238bec 12184 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
mbed_official 121:7f86b4238bec 12185
mbed_official 121:7f86b4238bec 12186 /*! @name CONTROL - USB OTG Control register */
mbed_official 121:7f86b4238bec 12187 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
mbed_official 121:7f86b4238bec 12188 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
mbed_official 121:7f86b4238bec 12189 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
mbed_official 121:7f86b4238bec 12190
mbed_official 121:7f86b4238bec 12191 /*! @name USBTRC0 - USB Transceiver Control register 0 */
mbed_official 121:7f86b4238bec 12192 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
mbed_official 121:7f86b4238bec 12193 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
mbed_official 121:7f86b4238bec 12194 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
mbed_official 121:7f86b4238bec 12195 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
mbed_official 121:7f86b4238bec 12196 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
mbed_official 121:7f86b4238bec 12197 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
mbed_official 121:7f86b4238bec 12198 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
mbed_official 121:7f86b4238bec 12199 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
mbed_official 121:7f86b4238bec 12200 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
mbed_official 121:7f86b4238bec 12201 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 12202 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 12203 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
mbed_official 121:7f86b4238bec 12204 #define USB_USBTRC0_USBRESET_MASK (0x80U)
mbed_official 121:7f86b4238bec 12205 #define USB_USBTRC0_USBRESET_SHIFT (7U)
mbed_official 121:7f86b4238bec 12206 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
mbed_official 121:7f86b4238bec 12207
mbed_official 121:7f86b4238bec 12208 /*! @name USBFRMADJUST - Frame Adjust Register */
mbed_official 121:7f86b4238bec 12209 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
mbed_official 121:7f86b4238bec 12210 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
mbed_official 121:7f86b4238bec 12211 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
mbed_official 121:7f86b4238bec 12212
mbed_official 121:7f86b4238bec 12213 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
mbed_official 121:7f86b4238bec 12214 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
mbed_official 121:7f86b4238bec 12215 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
mbed_official 121:7f86b4238bec 12216 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
mbed_official 121:7f86b4238bec 12217 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
mbed_official 121:7f86b4238bec 12218 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
mbed_official 121:7f86b4238bec 12219 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
mbed_official 121:7f86b4238bec 12220 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
mbed_official 121:7f86b4238bec 12221 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
mbed_official 121:7f86b4238bec 12222 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
mbed_official 121:7f86b4238bec 12223
mbed_official 121:7f86b4238bec 12224 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
mbed_official 121:7f86b4238bec 12225 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
mbed_official 121:7f86b4238bec 12226 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
mbed_official 121:7f86b4238bec 12227 #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
mbed_official 121:7f86b4238bec 12228 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
mbed_official 121:7f86b4238bec 12229 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
mbed_official 121:7f86b4238bec 12230 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
mbed_official 121:7f86b4238bec 12231
mbed_official 121:7f86b4238bec 12232 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
mbed_official 121:7f86b4238bec 12233 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
mbed_official 121:7f86b4238bec 12234 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
mbed_official 121:7f86b4238bec 12235 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
mbed_official 121:7f86b4238bec 12236
mbed_official 121:7f86b4238bec 12237
mbed_official 121:7f86b4238bec 12238 /*!
mbed_official 121:7f86b4238bec 12239 * @}
mbed_official 121:7f86b4238bec 12240 */ /* end of group USB_Register_Masks */
mbed_official 121:7f86b4238bec 12241
mbed_official 121:7f86b4238bec 12242
mbed_official 121:7f86b4238bec 12243 /* USB - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 12244 /** Peripheral USB0 base address */
mbed_official 121:7f86b4238bec 12245 #define USB0_BASE (0x40072000u)
mbed_official 121:7f86b4238bec 12246 /** Peripheral USB0 base pointer */
mbed_official 121:7f86b4238bec 12247 #define USB0 ((USB_Type *)USB0_BASE)
mbed_official 121:7f86b4238bec 12248 /** Array initializer of USB peripheral base addresses */
mbed_official 121:7f86b4238bec 12249 #define USB_BASE_ADDRS { USB0_BASE }
mbed_official 121:7f86b4238bec 12250 /** Array initializer of USB peripheral base pointers */
mbed_official 121:7f86b4238bec 12251 #define USB_BASE_PTRS { USB0 }
mbed_official 121:7f86b4238bec 12252 /** Interrupt vectors for the USB peripheral type */
mbed_official 121:7f86b4238bec 12253 #define USB_IRQS { USB0_IRQn }
mbed_official 121:7f86b4238bec 12254
mbed_official 121:7f86b4238bec 12255 /*!
mbed_official 121:7f86b4238bec 12256 * @}
mbed_official 121:7f86b4238bec 12257 */ /* end of group USB_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 12258
mbed_official 121:7f86b4238bec 12259
mbed_official 121:7f86b4238bec 12260 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 12261 -- USBDCD Peripheral Access Layer
mbed_official 121:7f86b4238bec 12262 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 12263
mbed_official 121:7f86b4238bec 12264 /*!
mbed_official 121:7f86b4238bec 12265 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
mbed_official 121:7f86b4238bec 12266 * @{
mbed_official 121:7f86b4238bec 12267 */
mbed_official 121:7f86b4238bec 12268
mbed_official 121:7f86b4238bec 12269 /** USBDCD - Register Layout Typedef */
mbed_official 121:7f86b4238bec 12270 typedef struct {
mbed_official 121:7f86b4238bec 12271 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
mbed_official 121:7f86b4238bec 12272 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
mbed_official 121:7f86b4238bec 12273 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
mbed_official 121:7f86b4238bec 12274 uint8_t RESERVED_0[4];
mbed_official 121:7f86b4238bec 12275 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
mbed_official 121:7f86b4238bec 12276 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
mbed_official 121:7f86b4238bec 12277 union { /* offset: 0x18 */
mbed_official 121:7f86b4238bec 12278 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
mbed_official 121:7f86b4238bec 12279 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
mbed_official 121:7f86b4238bec 12280 };
mbed_official 121:7f86b4238bec 12281 } USBDCD_Type;
mbed_official 121:7f86b4238bec 12282
mbed_official 121:7f86b4238bec 12283 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 12284 -- USBDCD Register Masks
mbed_official 121:7f86b4238bec 12285 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 12286
mbed_official 121:7f86b4238bec 12287 /*!
mbed_official 121:7f86b4238bec 12288 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
mbed_official 121:7f86b4238bec 12289 * @{
mbed_official 121:7f86b4238bec 12290 */
mbed_official 121:7f86b4238bec 12291
mbed_official 121:7f86b4238bec 12292 /*! @name CONTROL - Control register */
mbed_official 121:7f86b4238bec 12293 #define USBDCD_CONTROL_IACK_MASK (0x1U)
mbed_official 121:7f86b4238bec 12294 #define USBDCD_CONTROL_IACK_SHIFT (0U)
mbed_official 121:7f86b4238bec 12295 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
mbed_official 121:7f86b4238bec 12296 #define USBDCD_CONTROL_IF_MASK (0x100U)
mbed_official 121:7f86b4238bec 12297 #define USBDCD_CONTROL_IF_SHIFT (8U)
mbed_official 121:7f86b4238bec 12298 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
mbed_official 121:7f86b4238bec 12299 #define USBDCD_CONTROL_IE_MASK (0x10000U)
mbed_official 121:7f86b4238bec 12300 #define USBDCD_CONTROL_IE_SHIFT (16U)
mbed_official 121:7f86b4238bec 12301 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
mbed_official 121:7f86b4238bec 12302 #define USBDCD_CONTROL_BC12_MASK (0x20000U)
mbed_official 121:7f86b4238bec 12303 #define USBDCD_CONTROL_BC12_SHIFT (17U)
mbed_official 121:7f86b4238bec 12304 #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
mbed_official 121:7f86b4238bec 12305 #define USBDCD_CONTROL_START_MASK (0x1000000U)
mbed_official 121:7f86b4238bec 12306 #define USBDCD_CONTROL_START_SHIFT (24U)
mbed_official 121:7f86b4238bec 12307 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
mbed_official 121:7f86b4238bec 12308 #define USBDCD_CONTROL_SR_MASK (0x2000000U)
mbed_official 121:7f86b4238bec 12309 #define USBDCD_CONTROL_SR_SHIFT (25U)
mbed_official 121:7f86b4238bec 12310 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
mbed_official 121:7f86b4238bec 12311
mbed_official 121:7f86b4238bec 12312 /*! @name CLOCK - Clock register */
mbed_official 121:7f86b4238bec 12313 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
mbed_official 121:7f86b4238bec 12314 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
mbed_official 121:7f86b4238bec 12315 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
mbed_official 121:7f86b4238bec 12316 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
mbed_official 121:7f86b4238bec 12317 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
mbed_official 121:7f86b4238bec 12318 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
mbed_official 121:7f86b4238bec 12319
mbed_official 121:7f86b4238bec 12320 /*! @name STATUS - Status register */
mbed_official 121:7f86b4238bec 12321 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
mbed_official 121:7f86b4238bec 12322 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
mbed_official 121:7f86b4238bec 12323 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
mbed_official 121:7f86b4238bec 12324 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
mbed_official 121:7f86b4238bec 12325 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
mbed_official 121:7f86b4238bec 12326 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
mbed_official 121:7f86b4238bec 12327 #define USBDCD_STATUS_ERR_MASK (0x100000U)
mbed_official 121:7f86b4238bec 12328 #define USBDCD_STATUS_ERR_SHIFT (20U)
mbed_official 121:7f86b4238bec 12329 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
mbed_official 121:7f86b4238bec 12330 #define USBDCD_STATUS_TO_MASK (0x200000U)
mbed_official 121:7f86b4238bec 12331 #define USBDCD_STATUS_TO_SHIFT (21U)
mbed_official 121:7f86b4238bec 12332 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
mbed_official 121:7f86b4238bec 12333 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
mbed_official 121:7f86b4238bec 12334 #define USBDCD_STATUS_ACTIVE_SHIFT (22U)
mbed_official 121:7f86b4238bec 12335 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
mbed_official 121:7f86b4238bec 12336
mbed_official 121:7f86b4238bec 12337 /*! @name TIMER0 - TIMER0 register */
mbed_official 121:7f86b4238bec 12338 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
mbed_official 121:7f86b4238bec 12339 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
mbed_official 121:7f86b4238bec 12340 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
mbed_official 121:7f86b4238bec 12341 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
mbed_official 121:7f86b4238bec 12342 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
mbed_official 121:7f86b4238bec 12343 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
mbed_official 121:7f86b4238bec 12344
mbed_official 121:7f86b4238bec 12345 /*! @name TIMER1 - TIMER1 register */
mbed_official 121:7f86b4238bec 12346 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
mbed_official 121:7f86b4238bec 12347 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
mbed_official 121:7f86b4238bec 12348 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
mbed_official 121:7f86b4238bec 12349 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
mbed_official 121:7f86b4238bec 12350 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
mbed_official 121:7f86b4238bec 12351 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
mbed_official 121:7f86b4238bec 12352
mbed_official 121:7f86b4238bec 12353 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
mbed_official 121:7f86b4238bec 12354 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
mbed_official 121:7f86b4238bec 12355 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
mbed_official 121:7f86b4238bec 12356 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
mbed_official 121:7f86b4238bec 12357 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
mbed_official 121:7f86b4238bec 12358 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
mbed_official 121:7f86b4238bec 12359 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
mbed_official 121:7f86b4238bec 12360
mbed_official 121:7f86b4238bec 12361 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
mbed_official 121:7f86b4238bec 12362 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
mbed_official 121:7f86b4238bec 12363 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
mbed_official 121:7f86b4238bec 12364 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
mbed_official 121:7f86b4238bec 12365 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
mbed_official 121:7f86b4238bec 12366 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
mbed_official 121:7f86b4238bec 12367 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
mbed_official 121:7f86b4238bec 12368
mbed_official 121:7f86b4238bec 12369
mbed_official 121:7f86b4238bec 12370 /*!
mbed_official 121:7f86b4238bec 12371 * @}
mbed_official 121:7f86b4238bec 12372 */ /* end of group USBDCD_Register_Masks */
mbed_official 121:7f86b4238bec 12373
mbed_official 121:7f86b4238bec 12374
mbed_official 121:7f86b4238bec 12375 /* USBDCD - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 12376 /** Peripheral USBDCD base address */
mbed_official 121:7f86b4238bec 12377 #define USBDCD_BASE (0x40035000u)
mbed_official 121:7f86b4238bec 12378 /** Peripheral USBDCD base pointer */
mbed_official 121:7f86b4238bec 12379 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
mbed_official 121:7f86b4238bec 12380 /** Array initializer of USBDCD peripheral base addresses */
mbed_official 121:7f86b4238bec 12381 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
mbed_official 121:7f86b4238bec 12382 /** Array initializer of USBDCD peripheral base pointers */
mbed_official 121:7f86b4238bec 12383 #define USBDCD_BASE_PTRS { USBDCD }
mbed_official 121:7f86b4238bec 12384 /** Interrupt vectors for the USBDCD peripheral type */
mbed_official 121:7f86b4238bec 12385 #define USBDCD_IRQS { USBDCD_IRQn }
mbed_official 121:7f86b4238bec 12386
mbed_official 121:7f86b4238bec 12387 /*!
mbed_official 121:7f86b4238bec 12388 * @}
mbed_official 121:7f86b4238bec 12389 */ /* end of group USBDCD_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 12390
mbed_official 121:7f86b4238bec 12391
mbed_official 121:7f86b4238bec 12392 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 12393 -- VREF Peripheral Access Layer
mbed_official 121:7f86b4238bec 12394 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 12395
mbed_official 121:7f86b4238bec 12396 /*!
mbed_official 121:7f86b4238bec 12397 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
mbed_official 121:7f86b4238bec 12398 * @{
mbed_official 121:7f86b4238bec 12399 */
mbed_official 121:7f86b4238bec 12400
mbed_official 121:7f86b4238bec 12401 /** VREF - Register Layout Typedef */
mbed_official 121:7f86b4238bec 12402 typedef struct {
mbed_official 121:7f86b4238bec 12403 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
mbed_official 121:7f86b4238bec 12404 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
mbed_official 121:7f86b4238bec 12405 } VREF_Type;
mbed_official 121:7f86b4238bec 12406
mbed_official 121:7f86b4238bec 12407 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 12408 -- VREF Register Masks
mbed_official 121:7f86b4238bec 12409 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 12410
mbed_official 121:7f86b4238bec 12411 /*!
mbed_official 121:7f86b4238bec 12412 * @addtogroup VREF_Register_Masks VREF Register Masks
mbed_official 121:7f86b4238bec 12413 * @{
mbed_official 121:7f86b4238bec 12414 */
mbed_official 121:7f86b4238bec 12415
mbed_official 121:7f86b4238bec 12416 /*! @name TRM - VREF Trim Register */
mbed_official 121:7f86b4238bec 12417 #define VREF_TRM_TRIM_MASK (0x3FU)
mbed_official 121:7f86b4238bec 12418 #define VREF_TRM_TRIM_SHIFT (0U)
mbed_official 121:7f86b4238bec 12419 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
mbed_official 121:7f86b4238bec 12420 #define VREF_TRM_CHOPEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 12421 #define VREF_TRM_CHOPEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 12422 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
mbed_official 121:7f86b4238bec 12423
mbed_official 121:7f86b4238bec 12424 /*! @name SC - VREF Status and Control Register */
mbed_official 121:7f86b4238bec 12425 #define VREF_SC_MODE_LV_MASK (0x3U)
mbed_official 121:7f86b4238bec 12426 #define VREF_SC_MODE_LV_SHIFT (0U)
mbed_official 121:7f86b4238bec 12427 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
mbed_official 121:7f86b4238bec 12428 #define VREF_SC_VREFST_MASK (0x4U)
mbed_official 121:7f86b4238bec 12429 #define VREF_SC_VREFST_SHIFT (2U)
mbed_official 121:7f86b4238bec 12430 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
mbed_official 121:7f86b4238bec 12431 #define VREF_SC_ICOMPEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 12432 #define VREF_SC_ICOMPEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 12433 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
mbed_official 121:7f86b4238bec 12434 #define VREF_SC_REGEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 12435 #define VREF_SC_REGEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 12436 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
mbed_official 121:7f86b4238bec 12437 #define VREF_SC_VREFEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 12438 #define VREF_SC_VREFEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 12439 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
mbed_official 121:7f86b4238bec 12440
mbed_official 121:7f86b4238bec 12441
mbed_official 121:7f86b4238bec 12442 /*!
mbed_official 121:7f86b4238bec 12443 * @}
mbed_official 121:7f86b4238bec 12444 */ /* end of group VREF_Register_Masks */
mbed_official 121:7f86b4238bec 12445
mbed_official 121:7f86b4238bec 12446
mbed_official 121:7f86b4238bec 12447 /* VREF - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 12448 /** Peripheral VREF base address */
mbed_official 121:7f86b4238bec 12449 #define VREF_BASE (0x40074000u)
mbed_official 121:7f86b4238bec 12450 /** Peripheral VREF base pointer */
mbed_official 121:7f86b4238bec 12451 #define VREF ((VREF_Type *)VREF_BASE)
mbed_official 121:7f86b4238bec 12452 /** Array initializer of VREF peripheral base addresses */
mbed_official 121:7f86b4238bec 12453 #define VREF_BASE_ADDRS { VREF_BASE }
mbed_official 121:7f86b4238bec 12454 /** Array initializer of VREF peripheral base pointers */
mbed_official 121:7f86b4238bec 12455 #define VREF_BASE_PTRS { VREF }
mbed_official 121:7f86b4238bec 12456
mbed_official 121:7f86b4238bec 12457 /*!
mbed_official 121:7f86b4238bec 12458 * @}
mbed_official 121:7f86b4238bec 12459 */ /* end of group VREF_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 12460
mbed_official 121:7f86b4238bec 12461
mbed_official 121:7f86b4238bec 12462 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 12463 -- WDOG Peripheral Access Layer
mbed_official 121:7f86b4238bec 12464 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 12465
mbed_official 121:7f86b4238bec 12466 /*!
mbed_official 121:7f86b4238bec 12467 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
mbed_official 121:7f86b4238bec 12468 * @{
mbed_official 121:7f86b4238bec 12469 */
mbed_official 121:7f86b4238bec 12470
mbed_official 121:7f86b4238bec 12471 /** WDOG - Register Layout Typedef */
mbed_official 121:7f86b4238bec 12472 typedef struct {
mbed_official 121:7f86b4238bec 12473 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
mbed_official 121:7f86b4238bec 12474 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
mbed_official 121:7f86b4238bec 12475 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
mbed_official 121:7f86b4238bec 12476 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
mbed_official 121:7f86b4238bec 12477 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
mbed_official 121:7f86b4238bec 12478 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
mbed_official 121:7f86b4238bec 12479 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
mbed_official 121:7f86b4238bec 12480 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
mbed_official 121:7f86b4238bec 12481 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
mbed_official 121:7f86b4238bec 12482 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
mbed_official 121:7f86b4238bec 12483 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
mbed_official 121:7f86b4238bec 12484 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
mbed_official 121:7f86b4238bec 12485 } WDOG_Type;
mbed_official 121:7f86b4238bec 12486
mbed_official 121:7f86b4238bec 12487 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 12488 -- WDOG Register Masks
mbed_official 121:7f86b4238bec 12489 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 12490
mbed_official 121:7f86b4238bec 12491 /*!
mbed_official 121:7f86b4238bec 12492 * @addtogroup WDOG_Register_Masks WDOG Register Masks
mbed_official 121:7f86b4238bec 12493 * @{
mbed_official 121:7f86b4238bec 12494 */
mbed_official 121:7f86b4238bec 12495
mbed_official 121:7f86b4238bec 12496 /*! @name STCTRLH - Watchdog Status and Control Register High */
mbed_official 121:7f86b4238bec 12497 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
mbed_official 121:7f86b4238bec 12498 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
mbed_official 121:7f86b4238bec 12499 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
mbed_official 121:7f86b4238bec 12500 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
mbed_official 121:7f86b4238bec 12501 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
mbed_official 121:7f86b4238bec 12502 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
mbed_official 121:7f86b4238bec 12503 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
mbed_official 121:7f86b4238bec 12504 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
mbed_official 121:7f86b4238bec 12505 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
mbed_official 121:7f86b4238bec 12506 #define WDOG_STCTRLH_WINEN_MASK (0x8U)
mbed_official 121:7f86b4238bec 12507 #define WDOG_STCTRLH_WINEN_SHIFT (3U)
mbed_official 121:7f86b4238bec 12508 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
mbed_official 121:7f86b4238bec 12509 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
mbed_official 121:7f86b4238bec 12510 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
mbed_official 121:7f86b4238bec 12511 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
mbed_official 121:7f86b4238bec 12512 #define WDOG_STCTRLH_DBGEN_MASK (0x20U)
mbed_official 121:7f86b4238bec 12513 #define WDOG_STCTRLH_DBGEN_SHIFT (5U)
mbed_official 121:7f86b4238bec 12514 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
mbed_official 121:7f86b4238bec 12515 #define WDOG_STCTRLH_STOPEN_MASK (0x40U)
mbed_official 121:7f86b4238bec 12516 #define WDOG_STCTRLH_STOPEN_SHIFT (6U)
mbed_official 121:7f86b4238bec 12517 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
mbed_official 121:7f86b4238bec 12518 #define WDOG_STCTRLH_WAITEN_MASK (0x80U)
mbed_official 121:7f86b4238bec 12519 #define WDOG_STCTRLH_WAITEN_SHIFT (7U)
mbed_official 121:7f86b4238bec 12520 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
mbed_official 121:7f86b4238bec 12521 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
mbed_official 121:7f86b4238bec 12522 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
mbed_official 121:7f86b4238bec 12523 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
mbed_official 121:7f86b4238bec 12524 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
mbed_official 121:7f86b4238bec 12525 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
mbed_official 121:7f86b4238bec 12526 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
mbed_official 121:7f86b4238bec 12527 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
mbed_official 121:7f86b4238bec 12528 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
mbed_official 121:7f86b4238bec 12529 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
mbed_official 121:7f86b4238bec 12530 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
mbed_official 121:7f86b4238bec 12531 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
mbed_official 121:7f86b4238bec 12532 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
mbed_official 121:7f86b4238bec 12533
mbed_official 121:7f86b4238bec 12534 /*! @name STCTRLL - Watchdog Status and Control Register Low */
mbed_official 121:7f86b4238bec 12535 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
mbed_official 121:7f86b4238bec 12536 #define WDOG_STCTRLL_INTFLG_SHIFT (15U)
mbed_official 121:7f86b4238bec 12537 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
mbed_official 121:7f86b4238bec 12538
mbed_official 121:7f86b4238bec 12539 /*! @name TOVALH - Watchdog Time-out Value Register High */
mbed_official 121:7f86b4238bec 12540 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12541 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
mbed_official 121:7f86b4238bec 12542 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
mbed_official 121:7f86b4238bec 12543
mbed_official 121:7f86b4238bec 12544 /*! @name TOVALL - Watchdog Time-out Value Register Low */
mbed_official 121:7f86b4238bec 12545 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12546 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
mbed_official 121:7f86b4238bec 12547 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
mbed_official 121:7f86b4238bec 12548
mbed_official 121:7f86b4238bec 12549 /*! @name WINH - Watchdog Window Register High */
mbed_official 121:7f86b4238bec 12550 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12551 #define WDOG_WINH_WINHIGH_SHIFT (0U)
mbed_official 121:7f86b4238bec 12552 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
mbed_official 121:7f86b4238bec 12553
mbed_official 121:7f86b4238bec 12554 /*! @name WINL - Watchdog Window Register Low */
mbed_official 121:7f86b4238bec 12555 #define WDOG_WINL_WINLOW_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12556 #define WDOG_WINL_WINLOW_SHIFT (0U)
mbed_official 121:7f86b4238bec 12557 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
mbed_official 121:7f86b4238bec 12558
mbed_official 121:7f86b4238bec 12559 /*! @name REFRESH - Watchdog Refresh register */
mbed_official 121:7f86b4238bec 12560 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12561 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
mbed_official 121:7f86b4238bec 12562 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
mbed_official 121:7f86b4238bec 12563
mbed_official 121:7f86b4238bec 12564 /*! @name UNLOCK - Watchdog Unlock register */
mbed_official 121:7f86b4238bec 12565 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12566 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
mbed_official 121:7f86b4238bec 12567 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
mbed_official 121:7f86b4238bec 12568
mbed_official 121:7f86b4238bec 12569 /*! @name TMROUTH - Watchdog Timer Output Register High */
mbed_official 121:7f86b4238bec 12570 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12571 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
mbed_official 121:7f86b4238bec 12572 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
mbed_official 121:7f86b4238bec 12573
mbed_official 121:7f86b4238bec 12574 /*! @name TMROUTL - Watchdog Timer Output Register Low */
mbed_official 121:7f86b4238bec 12575 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12576 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
mbed_official 121:7f86b4238bec 12577 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
mbed_official 121:7f86b4238bec 12578
mbed_official 121:7f86b4238bec 12579 /*! @name RSTCNT - Watchdog Reset Count register */
mbed_official 121:7f86b4238bec 12580 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
mbed_official 121:7f86b4238bec 12581 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
mbed_official 121:7f86b4238bec 12582 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
mbed_official 121:7f86b4238bec 12583
mbed_official 121:7f86b4238bec 12584 /*! @name PRESC - Watchdog Prescaler register */
mbed_official 121:7f86b4238bec 12585 #define WDOG_PRESC_PRESCVAL_MASK (0x700U)
mbed_official 121:7f86b4238bec 12586 #define WDOG_PRESC_PRESCVAL_SHIFT (8U)
mbed_official 121:7f86b4238bec 12587 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
mbed_official 121:7f86b4238bec 12588
mbed_official 121:7f86b4238bec 12589
mbed_official 121:7f86b4238bec 12590 /*!
mbed_official 121:7f86b4238bec 12591 * @}
mbed_official 121:7f86b4238bec 12592 */ /* end of group WDOG_Register_Masks */
mbed_official 121:7f86b4238bec 12593
mbed_official 121:7f86b4238bec 12594
mbed_official 121:7f86b4238bec 12595 /* WDOG - Peripheral instance base addresses */
mbed_official 121:7f86b4238bec 12596 /** Peripheral WDOG base address */
mbed_official 121:7f86b4238bec 12597 #define WDOG_BASE (0x40052000u)
mbed_official 121:7f86b4238bec 12598 /** Peripheral WDOG base pointer */
mbed_official 121:7f86b4238bec 12599 #define WDOG ((WDOG_Type *)WDOG_BASE)
mbed_official 121:7f86b4238bec 12600 /** Array initializer of WDOG peripheral base addresses */
mbed_official 121:7f86b4238bec 12601 #define WDOG_BASE_ADDRS { WDOG_BASE }
mbed_official 121:7f86b4238bec 12602 /** Array initializer of WDOG peripheral base pointers */
mbed_official 121:7f86b4238bec 12603 #define WDOG_BASE_PTRS { WDOG }
mbed_official 121:7f86b4238bec 12604 /** Interrupt vectors for the WDOG peripheral type */
mbed_official 121:7f86b4238bec 12605 #define WDOG_IRQS { WDOG_EWM_IRQn }
mbed_official 121:7f86b4238bec 12606
mbed_official 121:7f86b4238bec 12607 /*!
mbed_official 121:7f86b4238bec 12608 * @}
mbed_official 121:7f86b4238bec 12609 */ /* end of group WDOG_Peripheral_Access_Layer */
mbed_official 121:7f86b4238bec 12610
mbed_official 121:7f86b4238bec 12611
mbed_official 121:7f86b4238bec 12612 /*
mbed_official 121:7f86b4238bec 12613 ** End of section using anonymous unions
mbed_official 121:7f86b4238bec 12614 */
mbed_official 121:7f86b4238bec 12615
mbed_official 121:7f86b4238bec 12616 #if defined(__ARMCC_VERSION)
mbed_official 121:7f86b4238bec 12617 #pragma pop
mbed_official 121:7f86b4238bec 12618 #elif defined(__CWCC__)
mbed_official 121:7f86b4238bec 12619 #pragma pop
mbed_official 121:7f86b4238bec 12620 #elif defined(__GNUC__)
mbed_official 121:7f86b4238bec 12621 /* leave anonymous unions enabled */
mbed_official 121:7f86b4238bec 12622 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 121:7f86b4238bec 12623 #pragma language=default
mbed_official 121:7f86b4238bec 12624 #else
mbed_official 121:7f86b4238bec 12625 #error Not supported compiler type
mbed_official 121:7f86b4238bec 12626 #endif
mbed_official 121:7f86b4238bec 12627
mbed_official 121:7f86b4238bec 12628 /*!
mbed_official 121:7f86b4238bec 12629 * @}
mbed_official 121:7f86b4238bec 12630 */ /* end of group Peripheral_access_layer */
mbed_official 121:7f86b4238bec 12631
mbed_official 121:7f86b4238bec 12632
mbed_official 121:7f86b4238bec 12633 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 12634 -- SDK Compatibility
mbed_official 121:7f86b4238bec 12635 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 12636
mbed_official 121:7f86b4238bec 12637 /*!
mbed_official 121:7f86b4238bec 12638 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
mbed_official 121:7f86b4238bec 12639 * @{
mbed_official 121:7f86b4238bec 12640 */
mbed_official 121:7f86b4238bec 12641
mbed_official 121:7f86b4238bec 12642 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
mbed_official 121:7f86b4238bec 12643 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
mbed_official 121:7f86b4238bec 12644 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
mbed_official 121:7f86b4238bec 12645 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
mbed_official 121:7f86b4238bec 12646 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
mbed_official 121:7f86b4238bec 12647 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
mbed_official 121:7f86b4238bec 12648 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
mbed_official 121:7f86b4238bec 12649 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
mbed_official 121:7f86b4238bec 12650 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
mbed_official 121:7f86b4238bec 12651 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
mbed_official 121:7f86b4238bec 12652 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
mbed_official 121:7f86b4238bec 12653 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
mbed_official 121:7f86b4238bec 12654 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
mbed_official 121:7f86b4238bec 12655 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
mbed_official 121:7f86b4238bec 12656 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
mbed_official 121:7f86b4238bec 12657 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
mbed_official 121:7f86b4238bec 12658 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
mbed_official 121:7f86b4238bec 12659 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
mbed_official 121:7f86b4238bec 12660 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
mbed_official 121:7f86b4238bec 12661 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
mbed_official 121:7f86b4238bec 12662 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
mbed_official 121:7f86b4238bec 12663 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
mbed_official 121:7f86b4238bec 12664 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
mbed_official 121:7f86b4238bec 12665 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
mbed_official 121:7f86b4238bec 12666 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
mbed_official 121:7f86b4238bec 12667 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
mbed_official 121:7f86b4238bec 12668 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
mbed_official 121:7f86b4238bec 12669 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
mbed_official 121:7f86b4238bec 12670 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
mbed_official 121:7f86b4238bec 12671 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
mbed_official 121:7f86b4238bec 12672 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
mbed_official 121:7f86b4238bec 12673 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
mbed_official 121:7f86b4238bec 12674 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
mbed_official 121:7f86b4238bec 12675 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
mbed_official 121:7f86b4238bec 12676 #define DSPI0 SPI0
mbed_official 121:7f86b4238bec 12677 #define DSPI1 SPI1
mbed_official 121:7f86b4238bec 12678 #define DSPI2 SPI2
mbed_official 121:7f86b4238bec 12679 #define FLEXCAN0 CAN0
mbed_official 121:7f86b4238bec 12680 #define GPIOA_BASE PTA_BASE
mbed_official 121:7f86b4238bec 12681 #define GPIOA PTA
mbed_official 121:7f86b4238bec 12682 #define GPIOB_BASE PTB_BASE
mbed_official 121:7f86b4238bec 12683 #define GPIOB PTB
mbed_official 121:7f86b4238bec 12684 #define GPIOC_BASE PTC_BASE
mbed_official 121:7f86b4238bec 12685 #define GPIOC PTC
mbed_official 121:7f86b4238bec 12686 #define GPIOD_BASE PTD_BASE
mbed_official 121:7f86b4238bec 12687 #define GPIOD PTD
mbed_official 121:7f86b4238bec 12688 #define GPIOE_BASE PTE_BASE
mbed_official 121:7f86b4238bec 12689 #define GPIOE PTE
mbed_official 121:7f86b4238bec 12690 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
mbed_official 121:7f86b4238bec 12691 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
mbed_official 121:7f86b4238bec 12692 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
mbed_official 121:7f86b4238bec 12693 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
mbed_official 121:7f86b4238bec 12694 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
mbed_official 121:7f86b4238bec 12695 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
mbed_official 121:7f86b4238bec 12696 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
mbed_official 121:7f86b4238bec 12697 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
mbed_official 121:7f86b4238bec 12698 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
mbed_official 121:7f86b4238bec 12699 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
mbed_official 121:7f86b4238bec 12700 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
mbed_official 121:7f86b4238bec 12701 #define Watchdog_IRQn WDOG_EWM_IRQn
mbed_official 121:7f86b4238bec 12702 #define Watchdog_IRQHandler WDOG_EWM_IRQHandler
mbed_official 121:7f86b4238bec 12703 #define LPTimer_IRQn LPTMR0_IRQn
mbed_official 121:7f86b4238bec 12704 #define LPTimer_IRQHandler LPTMR0_IRQHandler
mbed_official 121:7f86b4238bec 12705 #define LLW_IRQn LLWU_IRQn
mbed_official 121:7f86b4238bec 12706 #define LLW_IRQHandler LLWU_IRQHandler
mbed_official 121:7f86b4238bec 12707 #define DMAMUX0 DMAMUX
mbed_official 121:7f86b4238bec 12708 #define WDOG0 WDOG
mbed_official 121:7f86b4238bec 12709 #define MCM0 MCM
mbed_official 121:7f86b4238bec 12710 #define RTC0 RTC
mbed_official 121:7f86b4238bec 12711
mbed_official 121:7f86b4238bec 12712 /*!
mbed_official 121:7f86b4238bec 12713 * @}
mbed_official 121:7f86b4238bec 12714 */ /* end of group SDK_Compatibility_Symbols */
mbed_official 121:7f86b4238bec 12715
mbed_official 121:7f86b4238bec 12716
mbed_official 121:7f86b4238bec 12717 #endif /* _MK64F12_H_ */
mbed_official 121:7f86b4238bec 12718