en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c@19:112740acecfa, 2015-11-10 (annotated)

Committer:
mbed_official
Date:
Tue Nov 10 09:30:11 2015 +0000
Revision:
19:112740acecfa
Parent:
0:9b334a45a8ff 
Synchronized with git revision 7218418919aeaf775fb8d386ea7ee0dfc0c80ff9



Full URL: https://github.com/mbedmicro/mbed/commit/7218418919aeaf775fb8d386ea7ee0dfc0c80ff9/



DISCO_F469NI - add disco F469NI support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_pwr.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief PWR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Power Controller (PWR) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 ******************************************************************************
bogdanm 0:9b334a45a8ff 14 * @attention
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 19 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 20 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 21 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 23 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 24 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 26 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 27 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 39 *
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 44 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 */
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /** @defgroup PWR PWR
bogdanm 0:9b334a45a8ff 51 * @brief PWR HAL module driver
bogdanm 0:9b334a45a8ff 52 * @{
bogdanm 0:9b334a45a8ff 53 */
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 #ifdef HAL_PWR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59 /** @addtogroup PWR_Private_Constants
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
bogdanm 0:9b334a45a8ff 64 * @{
bogdanm 0:9b334a45a8ff 65 */
bogdanm 0:9b334a45a8ff 66 #define PVD_MODE_IT ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 67 #define PVD_MODE_EVT ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 68 #define PVD_RISING_EDGE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 69 #define PVD_FALLING_EDGE ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 70 /**
bogdanm 0:9b334a45a8ff 71 * @}
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /**
bogdanm 0:9b334a45a8ff 75 * @}
bogdanm 0:9b334a45a8ff 76 */
bogdanm 0:9b334a45a8ff 77 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 78 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 79 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 80 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 /** @defgroup PWR_Exported_Functions PWR Exported Functions
bogdanm 0:9b334a45a8ff 83 * @{
bogdanm 0:9b334a45a8ff 84 */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 87 * @brief Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 88 *
bogdanm 0:9b334a45a8ff 89 @verbatim
bogdanm 0:9b334a45a8ff 90 ===============================================================================
bogdanm 0:9b334a45a8ff 91 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 92 ===============================================================================
bogdanm 0:9b334a45a8ff 93 [..]
bogdanm 0:9b334a45a8ff 94 After reset, the backup domain (RTC registers, RTC backup data
bogdanm 0:9b334a45a8ff 95 registers and backup SRAM) is protected against possible unwanted
bogdanm 0:9b334a45a8ff 96 write accesses.
bogdanm 0:9b334a45a8ff 97 To enable access to the RTC Domain and RTC registers, proceed as follows:
bogdanm 0:9b334a45a8ff 98 (+) Enable the Power Controller (PWR) APB1 interface clock using the
bogdanm 0:9b334a45a8ff 99 __HAL_RCC_PWR_CLK_ENABLE() macro.
bogdanm 0:9b334a45a8ff 100 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 @endverbatim
bogdanm 0:9b334a45a8ff 103 * @{
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /**
bogdanm 0:9b334a45a8ff 107 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
bogdanm 0:9b334a45a8ff 108 * @retval None
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110 void HAL_PWR_DeInit(void)
bogdanm 0:9b334a45a8ff 111 {
bogdanm 0:9b334a45a8ff 112 __HAL_RCC_PWR_FORCE_RESET();
bogdanm 0:9b334a45a8ff 113 __HAL_RCC_PWR_RELEASE_RESET();
bogdanm 0:9b334a45a8ff 114 }
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /**
bogdanm 0:9b334a45a8ff 117 * @brief Enables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 118 * backup data registers and backup SRAM).
bogdanm 0:9b334a45a8ff 119 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 120 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 121 * @retval None
bogdanm 0:9b334a45a8ff 122 */
bogdanm 0:9b334a45a8ff 123 void HAL_PWR_EnableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 124 {
bogdanm 0:9b334a45a8ff 125 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
bogdanm 0:9b334a45a8ff 126 }
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /**
bogdanm 0:9b334a45a8ff 129 * @brief Disables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 130 * backup data registers and backup SRAM).
bogdanm 0:9b334a45a8ff 131 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 132 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 133 * @retval None
bogdanm 0:9b334a45a8ff 134 */
bogdanm 0:9b334a45a8ff 135 void HAL_PWR_DisableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 136 {
bogdanm 0:9b334a45a8ff 137 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
bogdanm 0:9b334a45a8ff 138 }
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /**
bogdanm 0:9b334a45a8ff 141 * @}
bogdanm 0:9b334a45a8ff 142 */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 145 * @brief Low Power modes configuration functions
bogdanm 0:9b334a45a8ff 146 *
bogdanm 0:9b334a45a8ff 147 @verbatim
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 ===============================================================================
bogdanm 0:9b334a45a8ff 150 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 151 ===============================================================================
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 *** PVD configuration ***
bogdanm 0:9b334a45a8ff 154 =========================
bogdanm 0:9b334a45a8ff 155 [..]
bogdanm 0:9b334a45a8ff 156 (+) The PVD is used to monitor the VDD power supply by comparing it to a
bogdanm 0:9b334a45a8ff 157 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
bogdanm 0:9b334a45a8ff 158 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
bogdanm 0:9b334a45a8ff 159 than the PVD threshold. This event is internally connected to the EXTI
bogdanm 0:9b334a45a8ff 160 line16 and can generate an interrupt if enabled. This is done through
bogdanm 0:9b334a45a8ff 161 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
bogdanm 0:9b334a45a8ff 162 (+) The PVD is stopped in Standby mode.
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 *** Wake-up pin configuration ***
bogdanm 0:9b334a45a8ff 165 ================================
bogdanm 0:9b334a45a8ff 166 [..]
bogdanm 0:9b334a45a8ff 167 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
bogdanm 0:9b334a45a8ff 168 forced in input pull-down configuration and is active on rising edges.
bogdanm 0:9b334a45a8ff 169 (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
mbed_official 19:112740acecfa 170 (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
mbed_official 19:112740acecfa 171 (++) For STM32F410xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 *** Low Power modes configuration ***
bogdanm 0:9b334a45a8ff 174 =====================================
bogdanm 0:9b334a45a8ff 175 [..]
bogdanm 0:9b334a45a8ff 176 The devices feature 3 low-power modes:
bogdanm 0:9b334a45a8ff 177 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
bogdanm 0:9b334a45a8ff 178 (+) Stop mode: all clocks are stopped, regulator running, regulator
bogdanm 0:9b334a45a8ff 179 in low power mode
bogdanm 0:9b334a45a8ff 180 (+) Standby mode: 1.2V domain powered off.
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 *** Sleep mode ***
bogdanm 0:9b334a45a8ff 183 ==================
bogdanm 0:9b334a45a8ff 184 [..]
bogdanm 0:9b334a45a8ff 185 (+) Entry:
bogdanm 0:9b334a45a8ff 186 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
bogdanm 0:9b334a45a8ff 187 functions with
bogdanm 0:9b334a45a8ff 188 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 189 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 -@@- The Regulator parameter is not used for the STM32F4 family
bogdanm 0:9b334a45a8ff 192 and is kept as parameter just to maintain compatibility with the
bogdanm 0:9b334a45a8ff 193 lower power families (STM32L).
bogdanm 0:9b334a45a8ff 194 (+) Exit:
bogdanm 0:9b334a45a8ff 195 Any peripheral interrupt acknowledged by the nested vectored interrupt
bogdanm 0:9b334a45a8ff 196 controller (NVIC) can wake up the device from Sleep mode.
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 *** Stop mode ***
bogdanm 0:9b334a45a8ff 199 =================
bogdanm 0:9b334a45a8ff 200 [..]
bogdanm 0:9b334a45a8ff 201 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
bogdanm 0:9b334a45a8ff 202 and the HSE RC oscillators are disabled. Internal SRAM and register contents
bogdanm 0:9b334a45a8ff 203 are preserved.
bogdanm 0:9b334a45a8ff 204 The voltage regulator can be configured either in normal or low-power mode.
bogdanm 0:9b334a45a8ff 205 To minimize the consumption In Stop mode, FLASH can be powered off before
bogdanm 0:9b334a45a8ff 206 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
bogdanm 0:9b334a45a8ff 207 It can be switched on again by software after exiting the Stop mode using
bogdanm 0:9b334a45a8ff 208 the HAL_PWREx_DisableFlashPowerDown() function.
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 (+) Entry:
bogdanm 0:9b334a45a8ff 211 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
bogdanm 0:9b334a45a8ff 212 function with:
bogdanm 0:9b334a45a8ff 213 (++) Main regulator ON.
bogdanm 0:9b334a45a8ff 214 (++) Low Power regulator ON.
bogdanm 0:9b334a45a8ff 215 (+) Exit:
bogdanm 0:9b334a45a8ff 216 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 *** Standby mode ***
bogdanm 0:9b334a45a8ff 219 ====================
bogdanm 0:9b334a45a8ff 220 [..]
bogdanm 0:9b334a45a8ff 221 (+)
bogdanm 0:9b334a45a8ff 222 The Standby mode allows to achieve the lowest power consumption. It is based
bogdanm 0:9b334a45a8ff 223 on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
bogdanm 0:9b334a45a8ff 224 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
bogdanm 0:9b334a45a8ff 225 the HSE oscillator are also switched off. SRAM and register contents are lost
bogdanm 0:9b334a45a8ff 226 except for the RTC registers, RTC backup registers, backup SRAM and Standby
bogdanm 0:9b334a45a8ff 227 circuitry.
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 The voltage regulator is OFF.
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 (++) Entry:
bogdanm 0:9b334a45a8ff 232 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
bogdanm 0:9b334a45a8ff 233 (++) Exit:
bogdanm 0:9b334a45a8ff 234 (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
bogdanm 0:9b334a45a8ff 235 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 *** Auto-wake-up (AWU) from low-power mode ***
bogdanm 0:9b334a45a8ff 238 =============================================
bogdanm 0:9b334a45a8ff 239 [..]
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
bogdanm 0:9b334a45a8ff 242 Wake-up event, a tamper event or a time-stamp event, without depending on
bogdanm 0:9b334a45a8ff 243 an external interrupt (Auto-wake-up mode).
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
bogdanm 0:9b334a45a8ff 248 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
bogdanm 0:9b334a45a8ff 251 is necessary to configure the RTC to detect the tamper or time stamp event using the
bogdanm 0:9b334a45a8ff 252 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
bogdanm 0:9b334a45a8ff 255 configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 @endverbatim
bogdanm 0:9b334a45a8ff 258 * @{
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 /**
bogdanm 0:9b334a45a8ff 262 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 263 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
bogdanm 0:9b334a45a8ff 264 * information for the PVD.
bogdanm 0:9b334a45a8ff 265 * @note Refer to the electrical characteristics of your device datasheet for
bogdanm 0:9b334a45a8ff 266 * more details about the voltage threshold corresponding to each
bogdanm 0:9b334a45a8ff 267 * detection level.
bogdanm 0:9b334a45a8ff 268 * @retval None
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
bogdanm 0:9b334a45a8ff 271 {
bogdanm 0:9b334a45a8ff 272 /* Check the parameters */
bogdanm 0:9b334a45a8ff 273 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
bogdanm 0:9b334a45a8ff 274 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /* Set PLS[7:5] bits according to PVDLevel value */
bogdanm 0:9b334a45a8ff 277 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
bogdanm 0:9b334a45a8ff 280 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
bogdanm 0:9b334a45a8ff 281 __HAL_PWR_PVD_EXTI_DISABLE_IT();
bogdanm 0:9b334a45a8ff 282 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 283 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /* Configure interrupt mode */
bogdanm 0:9b334a45a8ff 286 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 __HAL_PWR_PVD_EXTI_ENABLE_IT();
bogdanm 0:9b334a45a8ff 289 }
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* Configure event mode */
bogdanm 0:9b334a45a8ff 292 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
bogdanm 0:9b334a45a8ff 293 {
bogdanm 0:9b334a45a8ff 294 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
bogdanm 0:9b334a45a8ff 295 }
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /* Configure the edge */
bogdanm 0:9b334a45a8ff 298 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
bogdanm 0:9b334a45a8ff 299 {
bogdanm 0:9b334a45a8ff 300 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
bogdanm 0:9b334a45a8ff 304 {
bogdanm 0:9b334a45a8ff 305 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 }
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /**
bogdanm 0:9b334a45a8ff 310 * @brief Enables the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 311 * @retval None
bogdanm 0:9b334a45a8ff 312 */
bogdanm 0:9b334a45a8ff 313 void HAL_PWR_EnablePVD(void)
bogdanm 0:9b334a45a8ff 314 {
bogdanm 0:9b334a45a8ff 315 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /**
bogdanm 0:9b334a45a8ff 319 * @brief Disables the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 320 * @retval None
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322 void HAL_PWR_DisablePVD(void)
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /**
bogdanm 0:9b334a45a8ff 328 * @brief Enables the Wake-up PINx functionality.
bogdanm 0:9b334a45a8ff 329 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
bogdanm 0:9b334a45a8ff 330 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 331 * @arg PWR_WAKEUP_PIN1
mbed_official 19:112740acecfa 332 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
mbed_official 19:112740acecfa 333 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices
bogdanm 0:9b334a45a8ff 334 * @retval None
bogdanm 0:9b334a45a8ff 335 */
bogdanm 0:9b334a45a8ff 336 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 337 {
bogdanm 0:9b334a45a8ff 338 /* Check the parameter */
bogdanm 0:9b334a45a8ff 339 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 /* Enable the wake up pin */
bogdanm 0:9b334a45a8ff 342 SET_BIT(PWR->CSR, WakeUpPinx);
bogdanm 0:9b334a45a8ff 343 }
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /**
bogdanm 0:9b334a45a8ff 346 * @brief Disables the Wake-up PINx functionality.
bogdanm 0:9b334a45a8ff 347 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
bogdanm 0:9b334a45a8ff 348 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 349 * @arg PWR_WAKEUP_PIN1
mbed_official 19:112740acecfa 350 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
mbed_official 19:112740acecfa 351 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices
bogdanm 0:9b334a45a8ff 352 * @retval None
bogdanm 0:9b334a45a8ff 353 */
bogdanm 0:9b334a45a8ff 354 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 355 {
bogdanm 0:9b334a45a8ff 356 /* Check the parameter */
bogdanm 0:9b334a45a8ff 357 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Disable the wake up pin */
bogdanm 0:9b334a45a8ff 360 CLEAR_BIT(PWR->CSR, WakeUpPinx);
bogdanm 0:9b334a45a8ff 361 }
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /**
bogdanm 0:9b334a45a8ff 364 * @brief Enters Sleep mode.
bogdanm 0:9b334a45a8ff 365 *
bogdanm 0:9b334a45a8ff 366 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 367 *
bogdanm 0:9b334a45a8ff 368 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
bogdanm 0:9b334a45a8ff 369 * systick interrupt when used as time base for Timeout
bogdanm 0:9b334a45a8ff 370 *
bogdanm 0:9b334a45a8ff 371 * @param Regulator: Specifies the regulator state in SLEEP mode.
bogdanm 0:9b334a45a8ff 372 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 373 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
bogdanm 0:9b334a45a8ff 374 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
bogdanm 0:9b334a45a8ff 375 * @note This parameter is not used for the STM32F4 family and is kept as parameter
bogdanm 0:9b334a45a8ff 376 * just to maintain compatibility with the lower power families.
bogdanm 0:9b334a45a8ff 377 * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 378 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 379 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 380 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 381 * @retval None
bogdanm 0:9b334a45a8ff 382 */
bogdanm 0:9b334a45a8ff 383 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
bogdanm 0:9b334a45a8ff 384 {
bogdanm 0:9b334a45a8ff 385 /* Check the parameters */
bogdanm 0:9b334a45a8ff 386 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 387 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 /* Clear SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 390 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /* Select SLEEP mode entry -------------------------------------------------*/
bogdanm 0:9b334a45a8ff 393 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
bogdanm 0:9b334a45a8ff 394 {
bogdanm 0:9b334a45a8ff 395 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 396 __WFI();
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398 else
bogdanm 0:9b334a45a8ff 399 {
bogdanm 0:9b334a45a8ff 400 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 401 __SEV();
bogdanm 0:9b334a45a8ff 402 __WFE();
bogdanm 0:9b334a45a8ff 403 __WFE();
bogdanm 0:9b334a45a8ff 404 }
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /**
bogdanm 0:9b334a45a8ff 408 * @brief Enters Stop mode.
bogdanm 0:9b334a45a8ff 409 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 410 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
bogdanm 0:9b334a45a8ff 411 * the HSI RC oscillator is selected as system clock.
bogdanm 0:9b334a45a8ff 412 * @note When the voltage regulator operates in low power mode, an additional
bogdanm 0:9b334a45a8ff 413 * startup delay is incurred when waking up from Stop mode.
bogdanm 0:9b334a45a8ff 414 * By keeping the internal regulator ON during Stop mode, the consumption
bogdanm 0:9b334a45a8ff 415 * is higher although the startup time is reduced.
bogdanm 0:9b334a45a8ff 416 * @param Regulator: Specifies the regulator state in Stop mode.
bogdanm 0:9b334a45a8ff 417 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 418 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
bogdanm 0:9b334a45a8ff 419 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
bogdanm 0:9b334a45a8ff 420 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 421 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 422 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
bogdanm 0:9b334a45a8ff 423 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
bogdanm 0:9b334a45a8ff 424 * @retval None
bogdanm 0:9b334a45a8ff 425 */
bogdanm 0:9b334a45a8ff 426 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
bogdanm 0:9b334a45a8ff 427 {
bogdanm 0:9b334a45a8ff 428 /* Check the parameters */
bogdanm 0:9b334a45a8ff 429 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 430 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
bogdanm 0:9b334a45a8ff 433 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 436 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /* Select Stop mode entry --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 439 if(STOPEntry == PWR_STOPENTRY_WFI)
bogdanm 0:9b334a45a8ff 440 {
bogdanm 0:9b334a45a8ff 441 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 442 __WFI();
bogdanm 0:9b334a45a8ff 443 }
bogdanm 0:9b334a45a8ff 444 else
bogdanm 0:9b334a45a8ff 445 {
bogdanm 0:9b334a45a8ff 446 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 447 __SEV();
bogdanm 0:9b334a45a8ff 448 __WFE();
bogdanm 0:9b334a45a8ff 449 __WFE();
bogdanm 0:9b334a45a8ff 450 }
bogdanm 0:9b334a45a8ff 451 /* Reset SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 452 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 /**
bogdanm 0:9b334a45a8ff 456 * @brief Enters Standby mode.
bogdanm 0:9b334a45a8ff 457 * @note In Standby mode, all I/O pins are high impedance except for:
bogdanm 0:9b334a45a8ff 458 * - Reset pad (still available)
bogdanm 0:9b334a45a8ff 459 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
bogdanm 0:9b334a45a8ff 460 * Alarm out, or RTC clock calibration out.
bogdanm 0:9b334a45a8ff 461 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
bogdanm 0:9b334a45a8ff 462 * - WKUP pin 1 (PA0) if enabled.
bogdanm 0:9b334a45a8ff 463 * @retval None
bogdanm 0:9b334a45a8ff 464 */
bogdanm 0:9b334a45a8ff 465 void HAL_PWR_EnterSTANDBYMode(void)
bogdanm 0:9b334a45a8ff 466 {
bogdanm 0:9b334a45a8ff 467 /* Select Standby mode */
bogdanm 0:9b334a45a8ff 468 SET_BIT(PWR->CR, PWR_CR_PDDS);
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 471 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* This option is used to ensure that store operations are completed */
bogdanm 0:9b334a45a8ff 474 #if defined ( __CC_ARM)
bogdanm 0:9b334a45a8ff 475 __force_stores();
bogdanm 0:9b334a45a8ff 476 #endif
bogdanm 0:9b334a45a8ff 477 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 478 __WFI();
bogdanm 0:9b334a45a8ff 479 }
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 /**
bogdanm 0:9b334a45a8ff 482 * @brief This function handles the PWR PVD interrupt request.
bogdanm 0:9b334a45a8ff 483 * @note This API should be called under the PVD_IRQHandler().
bogdanm 0:9b334a45a8ff 484 * @retval None
bogdanm 0:9b334a45a8ff 485 */
bogdanm 0:9b334a45a8ff 486 void HAL_PWR_PVD_IRQHandler(void)
bogdanm 0:9b334a45a8ff 487 {
bogdanm 0:9b334a45a8ff 488 /* Check PWR Exti flag */
bogdanm 0:9b334a45a8ff 489 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 /* PWR PVD interrupt user callback */
bogdanm 0:9b334a45a8ff 492 HAL_PWR_PVDCallback();
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /* Clear PWR Exti pending bit */
bogdanm 0:9b334a45a8ff 495 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 496 }
bogdanm 0:9b334a45a8ff 497 }
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 /**
bogdanm 0:9b334a45a8ff 500 * @brief PWR PVD interrupt callback
bogdanm 0:9b334a45a8ff 501 * @retval None
bogdanm 0:9b334a45a8ff 502 */
bogdanm 0:9b334a45a8ff 503 __weak void HAL_PWR_PVDCallback(void)
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 506 the HAL_PWR_PVDCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 507 */
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /**
bogdanm 0:9b334a45a8ff 511 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 512 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 513 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 514 * Setting this bit is useful when the processor is expected to run only on
bogdanm 0:9b334a45a8ff 515 * interruptions handling.
bogdanm 0:9b334a45a8ff 516 * @retval None
bogdanm 0:9b334a45a8ff 517 */
bogdanm 0:9b334a45a8ff 518 void HAL_PWR_EnableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 519 {
bogdanm 0:9b334a45a8ff 520 /* Set SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 521 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 522 }
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /**
bogdanm 0:9b334a45a8ff 525 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 526 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 527 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 528 * @retval None
bogdanm 0:9b334a45a8ff 529 */
bogdanm 0:9b334a45a8ff 530 void HAL_PWR_DisableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 531 {
bogdanm 0:9b334a45a8ff 532 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 533 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 534 }
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 /**
bogdanm 0:9b334a45a8ff 537 * @brief Enables CORTEX M4 SEVONPEND bit.
bogdanm 0:9b334a45a8ff 538 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 539 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 540 * @retval None
bogdanm 0:9b334a45a8ff 541 */
bogdanm 0:9b334a45a8ff 542 void HAL_PWR_EnableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 543 {
bogdanm 0:9b334a45a8ff 544 /* Set SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 545 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 546 }
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /**
bogdanm 0:9b334a45a8ff 549 * @brief Disables CORTEX M4 SEVONPEND bit.
bogdanm 0:9b334a45a8ff 550 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 551 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 552 * @retval None
bogdanm 0:9b334a45a8ff 553 */
bogdanm 0:9b334a45a8ff 554 void HAL_PWR_DisableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 555 {
bogdanm 0:9b334a45a8ff 556 /* Clear SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 557 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 558 }
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /**
bogdanm 0:9b334a45a8ff 561 * @}
bogdanm 0:9b334a45a8ff 562 */
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /**
bogdanm 0:9b334a45a8ff 565 * @}
bogdanm 0:9b334a45a8ff 566 */
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 #endif /* HAL_PWR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 569 /**
bogdanm 0:9b334a45a8ff 570 * @}
bogdanm 0:9b334a45a8ff 571 */
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 /**
bogdanm 0:9b334a45a8ff 574 * @}
bogdanm 0:9b334a45a8ff 575 */
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/