en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c@19:112740acecfa, 2015-11-10 (annotated)

Committer:
mbed_official
Date:
Tue Nov 10 09:30:11 2015 +0000
Revision:
19:112740acecfa
Parent:
0:9b334a45a8ff 
Synchronized with git revision 7218418919aeaf775fb8d386ea7ee0dfc0c80ff9



Full URL: https://github.com/mbedmicro/mbed/commit/7218418919aeaf775fb8d386ea7ee0dfc0c80ff9/



DISCO_F469NI - add disco F469NI support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_nor.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief NOR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive NOR memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control NOR flash memories. It uses the FMC/FSMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with NOR devices. This driver is used as follows:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
bogdanm 0:9b334a45a8ff 21 with control and timing parameters for both normal and extended mode.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
bogdanm 0:9b334a45a8ff 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
bogdanm 0:9b334a45a8ff 25 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (+) Access NOR flash memory by read/write data unit operations using the functions
bogdanm 0:9b334a45a8ff 28 HAL_NOR_Read(), HAL_NOR_Program().
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 (+) Perform NOR flash erase block/chip operations using the functions
bogdanm 0:9b334a45a8ff 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
bogdanm 0:9b334a45a8ff 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
bogdanm 0:9b334a45a8ff 35 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (+) You can monitor the NOR device HAL state by calling the function
bogdanm 0:9b334a45a8ff 41 HAL_NOR_GetState()
bogdanm 0:9b334a45a8ff 42 [..]
bogdanm 0:9b334a45a8ff 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
bogdanm 0:9b334a45a8ff 44 If a NOR flash device contains different operations and/or implementations,
bogdanm 0:9b334a45a8ff 45 it should be implemented separately.
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 *** NOR HAL driver macros list ***
bogdanm 0:9b334a45a8ff 48 =============================================
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 Below the list of most used macros in NOR HAL driver.
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 (+) NOR_WRITE : NOR memory write data to specified address
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
bogdanm 0:9b334a45a8ff 58 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 /** @defgroup NOR NOR
bogdanm 0:9b334a45a8ff 93 * @brief NOR driver modules
bogdanm 0:9b334a45a8ff 94 * @{
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96 #ifdef HAL_NOR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 97 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
bogdanm 0:9b334a45a8ff 98 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
mbed_official 19:112740acecfa 99 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 100 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 101 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /** @defgroup NOR_Private_Defines NOR Private Defines
bogdanm 0:9b334a45a8ff 104 * @{
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /* Constants to define address to set to write a command */
bogdanm 0:9b334a45a8ff 108 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 109 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 110 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 111 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 112 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 113 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 114 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /* Constants to define data to program a command */
bogdanm 0:9b334a45a8ff 117 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
bogdanm 0:9b334a45a8ff 118 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 119 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 120 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
bogdanm 0:9b334a45a8ff 121 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
bogdanm 0:9b334a45a8ff 122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
bogdanm 0:9b334a45a8ff 123 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 124 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 125 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
bogdanm 0:9b334a45a8ff 126 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
bogdanm 0:9b334a45a8ff 129 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
bogdanm 0:9b334a45a8ff 130 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /* Mask on NOR STATUS REGISTER */
bogdanm 0:9b334a45a8ff 133 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
bogdanm 0:9b334a45a8ff 134 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /**
bogdanm 0:9b334a45a8ff 137 * @}
bogdanm 0:9b334a45a8ff 138 */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 141 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 142 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 143 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 144 /** @defgroup NOR_Exported_Functions NOR Exported Functions
bogdanm 0:9b334a45a8ff 145 * @{
bogdanm 0:9b334a45a8ff 146 */
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 149 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 150 *
bogdanm 0:9b334a45a8ff 151 @verbatim
bogdanm 0:9b334a45a8ff 152 ==============================================================================
bogdanm 0:9b334a45a8ff 153 ##### NOR Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 154 ==============================================================================
bogdanm 0:9b334a45a8ff 155 [..]
bogdanm 0:9b334a45a8ff 156 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 157 the NOR memory
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 @endverbatim
bogdanm 0:9b334a45a8ff 160 * @{
bogdanm 0:9b334a45a8ff 161 */
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /**
bogdanm 0:9b334a45a8ff 164 * @brief Perform the NOR memory Initialization sequence
bogdanm 0:9b334a45a8ff 165 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 166 * @param Timing: pointer to NOR control timing structure
bogdanm 0:9b334a45a8ff 167 * @param ExtTiming: pointer to NOR extended mode timing structure
bogdanm 0:9b334a45a8ff 168 * @retval HAL status
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
bogdanm 0:9b334a45a8ff 171 {
bogdanm 0:9b334a45a8ff 172 /* Check the NOR handle parameter */
bogdanm 0:9b334a45a8ff 173 if(hnor == NULL)
bogdanm 0:9b334a45a8ff 174 {
bogdanm 0:9b334a45a8ff 175 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 176 }
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 if(hnor->State == HAL_NOR_STATE_RESET)
bogdanm 0:9b334a45a8ff 179 {
bogdanm 0:9b334a45a8ff 180 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 181 hnor->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 182 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 183 HAL_NOR_MspInit(hnor);
bogdanm 0:9b334a45a8ff 184 }
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* Initialize NOR control Interface */
bogdanm 0:9b334a45a8ff 187 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /* Initialize NOR timing Interface */
bogdanm 0:9b334a45a8ff 190 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 /* Initialize NOR extended mode timing Interface */
bogdanm 0:9b334a45a8ff 193 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 /* Enable the NORSRAM device */
bogdanm 0:9b334a45a8ff 196 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 199 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 return HAL_OK;
bogdanm 0:9b334a45a8ff 202 }
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /**
bogdanm 0:9b334a45a8ff 205 * @brief Perform NOR memory De-Initialization sequence
bogdanm 0:9b334a45a8ff 206 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 207 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 208 * @retval HAL status
bogdanm 0:9b334a45a8ff 209 */
bogdanm 0:9b334a45a8ff 210 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 211 {
bogdanm 0:9b334a45a8ff 212 /* De-Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 213 HAL_NOR_MspDeInit(hnor);
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* Configure the NOR registers with their reset values */
bogdanm 0:9b334a45a8ff 216 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 219 hnor->State = HAL_NOR_STATE_RESET;
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 /* Release Lock */
bogdanm 0:9b334a45a8ff 222 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 return HAL_OK;
bogdanm 0:9b334a45a8ff 225 }
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /**
bogdanm 0:9b334a45a8ff 228 * @brief NOR MSP Init
bogdanm 0:9b334a45a8ff 229 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 230 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 231 * @retval None
bogdanm 0:9b334a45a8ff 232 */
bogdanm 0:9b334a45a8ff 233 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 234 {
bogdanm 0:9b334a45a8ff 235 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 236 the HAL_NOR_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 237 */
bogdanm 0:9b334a45a8ff 238 }
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 /**
bogdanm 0:9b334a45a8ff 241 * @brief NOR MSP DeInit
bogdanm 0:9b334a45a8ff 242 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 243 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 244 * @retval None
bogdanm 0:9b334a45a8ff 245 */
bogdanm 0:9b334a45a8ff 246 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 247 {
bogdanm 0:9b334a45a8ff 248 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 249 the HAL_NOR_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 250 */
bogdanm 0:9b334a45a8ff 251 }
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /**
bogdanm 0:9b334a45a8ff 254 * @brief NOR BSP Wait for Ready/Busy signal
bogdanm 0:9b334a45a8ff 255 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 256 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 257 * @param Timeout: Maximum timeout value
bogdanm 0:9b334a45a8ff 258 * @retval None
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 261 {
bogdanm 0:9b334a45a8ff 262 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 263 the HAL_NOR_BspWait could be implemented in the user file
bogdanm 0:9b334a45a8ff 264 */
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 /**
bogdanm 0:9b334a45a8ff 268 * @}
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 272 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 273 *
bogdanm 0:9b334a45a8ff 274 @verbatim
bogdanm 0:9b334a45a8ff 275 ==============================================================================
bogdanm 0:9b334a45a8ff 276 ##### NOR Input and Output functions #####
bogdanm 0:9b334a45a8ff 277 ==============================================================================
bogdanm 0:9b334a45a8ff 278 [..]
bogdanm 0:9b334a45a8ff 279 This section provides functions allowing to use and control the NOR memory
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 @endverbatim
bogdanm 0:9b334a45a8ff 282 * @{
bogdanm 0:9b334a45a8ff 283 */
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /**
bogdanm 0:9b334a45a8ff 286 * @brief Read NOR flash IDs
bogdanm 0:9b334a45a8ff 287 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 288 * @param pNOR_ID : pointer to NOR ID structure
bogdanm 0:9b334a45a8ff 289 * @retval HAL status
bogdanm 0:9b334a45a8ff 290 */
bogdanm 0:9b334a45a8ff 291 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 /* Process Locked */
bogdanm 0:9b334a45a8ff 296 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 299 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 300 {
bogdanm 0:9b334a45a8ff 301 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 302 }
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 305 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 306 {
bogdanm 0:9b334a45a8ff 307 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 310 {
bogdanm 0:9b334a45a8ff 311 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 314 {
bogdanm 0:9b334a45a8ff 315 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 318 {
bogdanm 0:9b334a45a8ff 319 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 320 }
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 323 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 /* Send read ID command */
bogdanm 0:9b334a45a8ff 326 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 327 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 328 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /* Read the NOR IDs */
bogdanm 0:9b334a45a8ff 331 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
bogdanm 0:9b334a45a8ff 332 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
bogdanm 0:9b334a45a8ff 333 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
bogdanm 0:9b334a45a8ff 334 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 337 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /* Process unlocked */
bogdanm 0:9b334a45a8ff 340 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 return HAL_OK;
bogdanm 0:9b334a45a8ff 343 }
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /**
bogdanm 0:9b334a45a8ff 346 * @brief Returns the NOR memory to Read mode.
bogdanm 0:9b334a45a8ff 347 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 348 * @retval HAL status
bogdanm 0:9b334a45a8ff 349 */
bogdanm 0:9b334a45a8ff 350 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 351 {
bogdanm 0:9b334a45a8ff 352 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /* Process Locked */
bogdanm 0:9b334a45a8ff 355 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 358 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 361 }
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 364 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 365 {
bogdanm 0:9b334a45a8ff 366 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 369 {
bogdanm 0:9b334a45a8ff 370 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 373 {
bogdanm 0:9b334a45a8ff 374 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 375 }
bogdanm 0:9b334a45a8ff 376 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 377 {
bogdanm 0:9b334a45a8ff 378 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 379 }
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 384 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Process unlocked */
bogdanm 0:9b334a45a8ff 387 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 return HAL_OK;
bogdanm 0:9b334a45a8ff 390 }
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /**
bogdanm 0:9b334a45a8ff 393 * @brief Read data from NOR memory
bogdanm 0:9b334a45a8ff 394 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 395 * @param pAddress: pointer to Device address
bogdanm 0:9b334a45a8ff 396 * @param pData : pointer to read data
bogdanm 0:9b334a45a8ff 397 * @retval HAL status
bogdanm 0:9b334a45a8ff 398 */
bogdanm 0:9b334a45a8ff 399 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 400 {
bogdanm 0:9b334a45a8ff 401 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 /* Process Locked */
bogdanm 0:9b334a45a8ff 404 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 407 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 408 {
bogdanm 0:9b334a45a8ff 409 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 410 }
bogdanm 0:9b334a45a8ff 411
bogdanm 0:9b334a45a8ff 412 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 413 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 414 {
bogdanm 0:9b334a45a8ff 415 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 416 }
bogdanm 0:9b334a45a8ff 417 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 418 {
bogdanm 0:9b334a45a8ff 419 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 420 }
bogdanm 0:9b334a45a8ff 421 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 422 {
bogdanm 0:9b334a45a8ff 423 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 424 }
bogdanm 0:9b334a45a8ff 425 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 426 {
bogdanm 0:9b334a45a8ff 427 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 428 }
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 431 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 /* Send read data command */
bogdanm 0:9b334a45a8ff 434 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 435 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 436 NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /* Read the data */
bogdanm 0:9b334a45a8ff 439 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 442 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /* Process unlocked */
bogdanm 0:9b334a45a8ff 445 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 return HAL_OK;
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /**
bogdanm 0:9b334a45a8ff 451 * @brief Program data to NOR memory
bogdanm 0:9b334a45a8ff 452 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 453 * @param pAddress: Device address
bogdanm 0:9b334a45a8ff 454 * @param pData : pointer to the data to write
bogdanm 0:9b334a45a8ff 455 * @retval HAL status
bogdanm 0:9b334a45a8ff 456 */
bogdanm 0:9b334a45a8ff 457 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /* Process Locked */
bogdanm 0:9b334a45a8ff 462 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 465 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 466 {
bogdanm 0:9b334a45a8ff 467 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 468 }
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 471 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 472 {
bogdanm 0:9b334a45a8ff 473 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 474 }
bogdanm 0:9b334a45a8ff 475 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 476 {
bogdanm 0:9b334a45a8ff 477 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 478 }
bogdanm 0:9b334a45a8ff 479 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 480 {
bogdanm 0:9b334a45a8ff 481 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 482 }
bogdanm 0:9b334a45a8ff 483 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 484 {
bogdanm 0:9b334a45a8ff 485 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 486 }
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 489 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 /* Send program data command */
bogdanm 0:9b334a45a8ff 492 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 493 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 494 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Write the data */
bogdanm 0:9b334a45a8ff 497 NOR_WRITE(pAddress, *pData);
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 500 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Process unlocked */
bogdanm 0:9b334a45a8ff 503 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 return HAL_OK;
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /**
bogdanm 0:9b334a45a8ff 509 * @brief Reads a half-word buffer from the NOR memory.
bogdanm 0:9b334a45a8ff 510 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 511 * @param uwAddress: NOR memory internal address to read from.
bogdanm 0:9b334a45a8ff 512 * @param pData: pointer to the buffer that receives the data read from the
bogdanm 0:9b334a45a8ff 513 * NOR memory.
bogdanm 0:9b334a45a8ff 514 * @param uwBufferSize : number of Half word to read.
bogdanm 0:9b334a45a8ff 515 * @retval HAL status
bogdanm 0:9b334a45a8ff 516 */
bogdanm 0:9b334a45a8ff 517 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 /* Process Locked */
bogdanm 0:9b334a45a8ff 522 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 525 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 526 {
bogdanm 0:9b334a45a8ff 527 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 528 }
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 531 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 532 {
bogdanm 0:9b334a45a8ff 533 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 534 }
bogdanm 0:9b334a45a8ff 535 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 536 {
bogdanm 0:9b334a45a8ff 537 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 538 }
bogdanm 0:9b334a45a8ff 539 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 540 {
bogdanm 0:9b334a45a8ff 541 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 542 }
bogdanm 0:9b334a45a8ff 543 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 544 {
bogdanm 0:9b334a45a8ff 545 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 546 }
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 549 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* Send read data command */
bogdanm 0:9b334a45a8ff 552 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 553 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 554 NOR_WRITE(uwAddress, 0x00F0);
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 /* Read buffer */
bogdanm 0:9b334a45a8ff 557 while( uwBufferSize > 0)
bogdanm 0:9b334a45a8ff 558 {
bogdanm 0:9b334a45a8ff 559 *pData++ = *(__IO uint16_t *)uwAddress;
bogdanm 0:9b334a45a8ff 560 uwAddress += 2;
bogdanm 0:9b334a45a8ff 561 uwBufferSize--;
bogdanm 0:9b334a45a8ff 562 }
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 565 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /* Process unlocked */
bogdanm 0:9b334a45a8ff 568 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 return HAL_OK;
bogdanm 0:9b334a45a8ff 571 }
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 /**
bogdanm 0:9b334a45a8ff 574 * @brief Writes a half-word buffer to the NOR memory. This function must be used
bogdanm 0:9b334a45a8ff 575 only with S29GL128P NOR memory.
bogdanm 0:9b334a45a8ff 576 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 577 * @param uwAddress: NOR memory internal start write address
bogdanm 0:9b334a45a8ff 578 * @param pData: pointer to source data buffer.
bogdanm 0:9b334a45a8ff 579 * @param uwBufferSize: Size of the buffer to write
bogdanm 0:9b334a45a8ff 580 * @retval HAL status
bogdanm 0:9b334a45a8ff 581 */
bogdanm 0:9b334a45a8ff 582 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 583 {
bogdanm 0:9b334a45a8ff 584 uint16_t * p_currentaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 585 uint16_t * p_endaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 586 uint32_t lastloadedaddress = 0, deviceaddress = 0;
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 /* Process Locked */
bogdanm 0:9b334a45a8ff 589 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 592 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 593 {
bogdanm 0:9b334a45a8ff 594 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 595 }
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 598 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 599 {
bogdanm 0:9b334a45a8ff 600 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 601 }
bogdanm 0:9b334a45a8ff 602 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 603 {
bogdanm 0:9b334a45a8ff 604 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 605 }
bogdanm 0:9b334a45a8ff 606 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 607 {
bogdanm 0:9b334a45a8ff 608 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 609 }
bogdanm 0:9b334a45a8ff 610 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 611 {
bogdanm 0:9b334a45a8ff 612 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 613 }
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 616 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 /* Initialize variables */
bogdanm 0:9b334a45a8ff 619 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
bogdanm 0:9b334a45a8ff 620 p_endaddress = p_currentaddress + (uwBufferSize-1);
bogdanm 0:9b334a45a8ff 621 lastloadedaddress = (uint32_t)(uwAddress);
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /* Issue unlock command sequence */
bogdanm 0:9b334a45a8ff 624 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 625 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 /* Write Buffer Load Command */
bogdanm 0:9b334a45a8ff 628 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
bogdanm 0:9b334a45a8ff 629 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 /* Load Data into NOR Buffer */
bogdanm 0:9b334a45a8ff 632 while(p_currentaddress <= p_endaddress)
bogdanm 0:9b334a45a8ff 633 {
bogdanm 0:9b334a45a8ff 634 /* Store last loaded address & data value (for polling) */
bogdanm 0:9b334a45a8ff 635 lastloadedaddress = (uint32_t)p_currentaddress;
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 NOR_WRITE(p_currentaddress, *pData++);
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 p_currentaddress ++;
bogdanm 0:9b334a45a8ff 640 }
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 645 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647 /* Process unlocked */
bogdanm 0:9b334a45a8ff 648 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 return HAL_OK;
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 }
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /**
bogdanm 0:9b334a45a8ff 655 * @brief Erase the specified block of the NOR memory
bogdanm 0:9b334a45a8ff 656 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 657 * @param BlockAddress : Block to erase address
bogdanm 0:9b334a45a8ff 658 * @param Address: Device address
bogdanm 0:9b334a45a8ff 659 * @retval HAL status
bogdanm 0:9b334a45a8ff 660 */
bogdanm 0:9b334a45a8ff 661 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
bogdanm 0:9b334a45a8ff 662 {
bogdanm 0:9b334a45a8ff 663 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 664
bogdanm 0:9b334a45a8ff 665 /* Process Locked */
bogdanm 0:9b334a45a8ff 666 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 667
bogdanm 0:9b334a45a8ff 668 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 669 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 670 {
bogdanm 0:9b334a45a8ff 671 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 672 }
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 675 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 676 {
bogdanm 0:9b334a45a8ff 677 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 678 }
bogdanm 0:9b334a45a8ff 679 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 680 {
bogdanm 0:9b334a45a8ff 681 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 682 }
bogdanm 0:9b334a45a8ff 683 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 684 {
bogdanm 0:9b334a45a8ff 685 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 686 }
bogdanm 0:9b334a45a8ff 687 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 688 {
bogdanm 0:9b334a45a8ff 689 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 693 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /* Send block erase command sequence */
bogdanm 0:9b334a45a8ff 696 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 697 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 698 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
bogdanm 0:9b334a45a8ff 699 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
bogdanm 0:9b334a45a8ff 700 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
bogdanm 0:9b334a45a8ff 701 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 704 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 /* Process unlocked */
bogdanm 0:9b334a45a8ff 707 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 return HAL_OK;
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /**
bogdanm 0:9b334a45a8ff 714 * @brief Erase the entire NOR chip.
bogdanm 0:9b334a45a8ff 715 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 716 * @param Address : Device address
bogdanm 0:9b334a45a8ff 717 * @retval HAL status
bogdanm 0:9b334a45a8ff 718 */
bogdanm 0:9b334a45a8ff 719 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
bogdanm 0:9b334a45a8ff 720 {
bogdanm 0:9b334a45a8ff 721 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 722
bogdanm 0:9b334a45a8ff 723 /* Process Locked */
bogdanm 0:9b334a45a8ff 724 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 727 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 728 {
bogdanm 0:9b334a45a8ff 729 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 730 }
bogdanm 0:9b334a45a8ff 731
bogdanm 0:9b334a45a8ff 732 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 733 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 734 {
bogdanm 0:9b334a45a8ff 735 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 736 }
bogdanm 0:9b334a45a8ff 737 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 738 {
bogdanm 0:9b334a45a8ff 739 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 740 }
bogdanm 0:9b334a45a8ff 741 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 742 {
bogdanm 0:9b334a45a8ff 743 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 744 }
bogdanm 0:9b334a45a8ff 745 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 746 {
bogdanm 0:9b334a45a8ff 747 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 748 }
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 751 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 752
bogdanm 0:9b334a45a8ff 753 /* Send NOR chip erase command sequence */
bogdanm 0:9b334a45a8ff 754 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 755 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 756 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
bogdanm 0:9b334a45a8ff 757 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
bogdanm 0:9b334a45a8ff 758 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
bogdanm 0:9b334a45a8ff 759 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 762 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 763
bogdanm 0:9b334a45a8ff 764 /* Process unlocked */
bogdanm 0:9b334a45a8ff 765 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 return HAL_OK;
bogdanm 0:9b334a45a8ff 768 }
bogdanm 0:9b334a45a8ff 769
bogdanm 0:9b334a45a8ff 770 /**
bogdanm 0:9b334a45a8ff 771 * @brief Read NOR flash CFI IDs
bogdanm 0:9b334a45a8ff 772 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 773 * @param pNOR_CFI : pointer to NOR CFI IDs structure
bogdanm 0:9b334a45a8ff 774 * @retval HAL status
bogdanm 0:9b334a45a8ff 775 */
bogdanm 0:9b334a45a8ff 776 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
bogdanm 0:9b334a45a8ff 777 {
bogdanm 0:9b334a45a8ff 778 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 779
bogdanm 0:9b334a45a8ff 780 /* Process Locked */
bogdanm 0:9b334a45a8ff 781 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 784 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 785 {
bogdanm 0:9b334a45a8ff 786 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 787 }
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 790 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 791 {
bogdanm 0:9b334a45a8ff 792 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 793 }
bogdanm 0:9b334a45a8ff 794 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 795 {
bogdanm 0:9b334a45a8ff 796 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 797 }
bogdanm 0:9b334a45a8ff 798 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 799 {
bogdanm 0:9b334a45a8ff 800 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 801 }
bogdanm 0:9b334a45a8ff 802 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 803 {
bogdanm 0:9b334a45a8ff 804 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 805 }
bogdanm 0:9b334a45a8ff 806
bogdanm 0:9b334a45a8ff 807 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 808 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 809
bogdanm 0:9b334a45a8ff 810 /* Send read CFI query command */
bogdanm 0:9b334a45a8ff 811 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /* read the NOR CFI information */
bogdanm 0:9b334a45a8ff 814 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
bogdanm 0:9b334a45a8ff 815 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
bogdanm 0:9b334a45a8ff 816 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
bogdanm 0:9b334a45a8ff 817 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
bogdanm 0:9b334a45a8ff 818
bogdanm 0:9b334a45a8ff 819 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 820 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 821
bogdanm 0:9b334a45a8ff 822 /* Process unlocked */
bogdanm 0:9b334a45a8ff 823 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 824
bogdanm 0:9b334a45a8ff 825 return HAL_OK;
bogdanm 0:9b334a45a8ff 826 }
bogdanm 0:9b334a45a8ff 827
bogdanm 0:9b334a45a8ff 828 /**
bogdanm 0:9b334a45a8ff 829 * @}
bogdanm 0:9b334a45a8ff 830 */
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /** @defgroup NOR_Exported_Functions_Group3 Control functions
bogdanm 0:9b334a45a8ff 833 * @brief management functions
bogdanm 0:9b334a45a8ff 834 *
bogdanm 0:9b334a45a8ff 835 @verbatim
bogdanm 0:9b334a45a8ff 836 ==============================================================================
bogdanm 0:9b334a45a8ff 837 ##### NOR Control functions #####
bogdanm 0:9b334a45a8ff 838 ==============================================================================
bogdanm 0:9b334a45a8ff 839 [..]
bogdanm 0:9b334a45a8ff 840 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 841 the NOR interface.
bogdanm 0:9b334a45a8ff 842
bogdanm 0:9b334a45a8ff 843 @endverbatim
bogdanm 0:9b334a45a8ff 844 * @{
bogdanm 0:9b334a45a8ff 845 */
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 /**
bogdanm 0:9b334a45a8ff 848 * @brief Enables dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 849 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 850 * @retval HAL status
bogdanm 0:9b334a45a8ff 851 */
bogdanm 0:9b334a45a8ff 852 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 853 {
bogdanm 0:9b334a45a8ff 854 /* Process Locked */
bogdanm 0:9b334a45a8ff 855 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 856
bogdanm 0:9b334a45a8ff 857 /* Enable write operation */
bogdanm 0:9b334a45a8ff 858 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 859
bogdanm 0:9b334a45a8ff 860 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 861 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 862
bogdanm 0:9b334a45a8ff 863 /* Process unlocked */
bogdanm 0:9b334a45a8ff 864 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 865
bogdanm 0:9b334a45a8ff 866 return HAL_OK;
bogdanm 0:9b334a45a8ff 867 }
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 /**
bogdanm 0:9b334a45a8ff 870 * @brief Disables dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 871 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 872 * @retval HAL status
bogdanm 0:9b334a45a8ff 873 */
bogdanm 0:9b334a45a8ff 874 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 875 {
bogdanm 0:9b334a45a8ff 876 /* Process Locked */
bogdanm 0:9b334a45a8ff 877 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 878
bogdanm 0:9b334a45a8ff 879 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 880 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 881
bogdanm 0:9b334a45a8ff 882 /* Disable write operation */
bogdanm 0:9b334a45a8ff 883 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 884
bogdanm 0:9b334a45a8ff 885 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 886 hnor->State = HAL_NOR_STATE_PROTECTED;
bogdanm 0:9b334a45a8ff 887
bogdanm 0:9b334a45a8ff 888 /* Process unlocked */
bogdanm 0:9b334a45a8ff 889 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 890
bogdanm 0:9b334a45a8ff 891 return HAL_OK;
bogdanm 0:9b334a45a8ff 892 }
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 /**
bogdanm 0:9b334a45a8ff 895 * @}
bogdanm 0:9b334a45a8ff 896 */
bogdanm 0:9b334a45a8ff 897
bogdanm 0:9b334a45a8ff 898 /** @defgroup NOR_Exported_Functions_Group4 State functions
bogdanm 0:9b334a45a8ff 899 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 900 *
bogdanm 0:9b334a45a8ff 901 @verbatim
bogdanm 0:9b334a45a8ff 902 ==============================================================================
bogdanm 0:9b334a45a8ff 903 ##### NOR State functions #####
bogdanm 0:9b334a45a8ff 904 ==============================================================================
bogdanm 0:9b334a45a8ff 905 [..]
bogdanm 0:9b334a45a8ff 906 This subsection permits to get in run-time the status of the NOR controller
bogdanm 0:9b334a45a8ff 907 and the data flow.
bogdanm 0:9b334a45a8ff 908
bogdanm 0:9b334a45a8ff 909 @endverbatim
bogdanm 0:9b334a45a8ff 910 * @{
bogdanm 0:9b334a45a8ff 911 */
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 /**
bogdanm 0:9b334a45a8ff 914 * @brief return the NOR controller state
bogdanm 0:9b334a45a8ff 915 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 916 * @retval NOR controller state
bogdanm 0:9b334a45a8ff 917 */
bogdanm 0:9b334a45a8ff 918 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 919 {
bogdanm 0:9b334a45a8ff 920 return hnor->State;
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922
bogdanm 0:9b334a45a8ff 923 /**
bogdanm 0:9b334a45a8ff 924 * @brief Returns the NOR operation status.
bogdanm 0:9b334a45a8ff 925 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 926 * @param Address: Device address
bogdanm 0:9b334a45a8ff 927 * @param Timeout: NOR programming Timeout
bogdanm 0:9b334a45a8ff 928 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
bogdanm 0:9b334a45a8ff 929 * or HAL_NOR_STATUS_TIMEOUT
bogdanm 0:9b334a45a8ff 930 */
bogdanm 0:9b334a45a8ff 931 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 932 {
bogdanm 0:9b334a45a8ff 933 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 934 uint16_t tmpSR1 = 0, tmpSR2 = 0;
bogdanm 0:9b334a45a8ff 935 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 936
bogdanm 0:9b334a45a8ff 937 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
bogdanm 0:9b334a45a8ff 938 HAL_NOR_MspWait(hnor, Timeout);
bogdanm 0:9b334a45a8ff 939
bogdanm 0:9b334a45a8ff 940 /* Get the NOR memory operation status -------------------------------------*/
bogdanm 0:9b334a45a8ff 941
bogdanm 0:9b334a45a8ff 942 /* Get tick */
bogdanm 0:9b334a45a8ff 943 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 944 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
bogdanm 0:9b334a45a8ff 945 {
bogdanm 0:9b334a45a8ff 946 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 947 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 948 {
bogdanm 0:9b334a45a8ff 949 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 950 {
bogdanm 0:9b334a45a8ff 951 status = HAL_NOR_STATUS_TIMEOUT;
bogdanm 0:9b334a45a8ff 952 }
bogdanm 0:9b334a45a8ff 953 }
bogdanm 0:9b334a45a8ff 954
bogdanm 0:9b334a45a8ff 955 /* Read NOR status register (DQ6 and DQ5) */
bogdanm 0:9b334a45a8ff 956 tmpSR1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 957 tmpSR2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 958
bogdanm 0:9b334a45a8ff 959 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
bogdanm 0:9b334a45a8ff 960 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 961 {
bogdanm 0:9b334a45a8ff 962 return HAL_NOR_STATUS_SUCCESS ;
bogdanm 0:9b334a45a8ff 963 }
bogdanm 0:9b334a45a8ff 964
bogdanm 0:9b334a45a8ff 965 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 966 {
bogdanm 0:9b334a45a8ff 967 status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 968 }
bogdanm 0:9b334a45a8ff 969
bogdanm 0:9b334a45a8ff 970 tmpSR1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 971 tmpSR2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 972
bogdanm 0:9b334a45a8ff 973 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
bogdanm 0:9b334a45a8ff 974 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 975 {
bogdanm 0:9b334a45a8ff 976 return HAL_NOR_STATUS_SUCCESS;
bogdanm 0:9b334a45a8ff 977 }
bogdanm 0:9b334a45a8ff 978 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 979 {
bogdanm 0:9b334a45a8ff 980 return HAL_NOR_STATUS_ERROR;
bogdanm 0:9b334a45a8ff 981 }
bogdanm 0:9b334a45a8ff 982 }
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 /* Return the operation status */
bogdanm 0:9b334a45a8ff 985 return status;
bogdanm 0:9b334a45a8ff 986 }
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /**
bogdanm 0:9b334a45a8ff 989 * @}
bogdanm 0:9b334a45a8ff 990 */
bogdanm 0:9b334a45a8ff 991
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 /**
bogdanm 0:9b334a45a8ff 994 * @}
bogdanm 0:9b334a45a8ff 995 */
bogdanm 0:9b334a45a8ff 996 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
mbed_official 19:112740acecfa 997 STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
mbed_official 19:112740acecfa 998 STM32F479xx */
bogdanm 0:9b334a45a8ff 999 #endif /* HAL_NOR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1000 /**
bogdanm 0:9b334a45a8ff 1001 * @}
bogdanm 0:9b334a45a8ff 1002 */
bogdanm 0:9b334a45a8ff 1003
bogdanm 0:9b334a45a8ff 1004 /**
bogdanm 0:9b334a45a8ff 1005 * @}
bogdanm 0:9b334a45a8ff 1006 */
bogdanm 0:9b334a45a8ff 1007
bogdanm 0:9b334a45a8ff 1008 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/