en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.c@19:112740acecfa, 2015-11-10 (annotated)

Committer:
mbed_official
Date:
Tue Nov 10 09:30:11 2015 +0000
Revision:
19:112740acecfa
Synchronized with git revision 7218418919aeaf775fb8d386ea7ee0dfc0c80ff9



Full URL: https://github.com/mbedmicro/mbed/commit/7218418919aeaf775fb8d386ea7ee0dfc0c80ff9/



DISCO_F469NI - add disco F469NI support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 19:112740acecfa 1 /**
mbed_official 19:112740acecfa 2 ******************************************************************************
mbed_official 19:112740acecfa 3 * @file stm32f4xx_hal_dsi.c
mbed_official 19:112740acecfa 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
mbed_official 19:112740acecfa 7 * @brief DSI HAL module driver.
mbed_official 19:112740acecfa 8 * This file provides firmware functions to manage the following
mbed_official 19:112740acecfa 9 * functionalities of the DSI peripheral:
mbed_official 19:112740acecfa 10 * + Initialization and de-initialization functions
mbed_official 19:112740acecfa 11 * + IO operation functions
mbed_official 19:112740acecfa 12 * + Peripheral Control functions
mbed_official 19:112740acecfa 13 * + Peripheral State and Errors functions
mbed_official 19:112740acecfa 14 ******************************************************************************
mbed_official 19:112740acecfa 15 * @attention
mbed_official 19:112740acecfa 16 *
mbed_official 19:112740acecfa 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 19:112740acecfa 18 *
mbed_official 19:112740acecfa 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 19:112740acecfa 20 * are permitted provided that the following conditions are met:
mbed_official 19:112740acecfa 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 19:112740acecfa 22 * this list of conditions and the following disclaimer.
mbed_official 19:112740acecfa 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 19:112740acecfa 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 19:112740acecfa 25 * and/or other materials provided with the distribution.
mbed_official 19:112740acecfa 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 19:112740acecfa 27 * may be used to endorse or promote products derived from this software
mbed_official 19:112740acecfa 28 * without specific prior written permission.
mbed_official 19:112740acecfa 29 *
mbed_official 19:112740acecfa 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 19:112740acecfa 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 19:112740acecfa 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 19:112740acecfa 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 19:112740acecfa 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 19:112740acecfa 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 19:112740acecfa 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 19:112740acecfa 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 19:112740acecfa 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 19:112740acecfa 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 19:112740acecfa 40 *
mbed_official 19:112740acecfa 41 ******************************************************************************
mbed_official 19:112740acecfa 42 */
mbed_official 19:112740acecfa 43
mbed_official 19:112740acecfa 44 /* Includes ------------------------------------------------------------------*/
mbed_official 19:112740acecfa 45 #include "stm32f4xx_hal.h"
mbed_official 19:112740acecfa 46
mbed_official 19:112740acecfa 47 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 19:112740acecfa 48 * @{
mbed_official 19:112740acecfa 49 */
mbed_official 19:112740acecfa 50 /** @addtogroup DSI
mbed_official 19:112740acecfa 51 * @{
mbed_official 19:112740acecfa 52 */
mbed_official 19:112740acecfa 53
mbed_official 19:112740acecfa 54 #ifdef HAL_DSI_MODULE_ENABLED
mbed_official 19:112740acecfa 55
mbed_official 19:112740acecfa 56 #if defined(STM32F469xx) || defined(STM32F479xx)
mbed_official 19:112740acecfa 57
mbed_official 19:112740acecfa 58 /* Private types -------------------------------------------------------------*/
mbed_official 19:112740acecfa 59 /* Private defines -----------------------------------------------------------*/
mbed_official 19:112740acecfa 60 /** @addtogroup DSI_Private_Constants
mbed_official 19:112740acecfa 61 * @{
mbed_official 19:112740acecfa 62 */
mbed_official 19:112740acecfa 63 #define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
mbed_official 19:112740acecfa 64
mbed_official 19:112740acecfa 65 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
mbed_official 19:112740acecfa 66 DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
mbed_official 19:112740acecfa 67 DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
mbed_official 19:112740acecfa 68 DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
mbed_official 19:112740acecfa 69 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
mbed_official 19:112740acecfa 70 #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
mbed_official 19:112740acecfa 71 #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
mbed_official 19:112740acecfa 72 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
mbed_official 19:112740acecfa 73 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
mbed_official 19:112740acecfa 74 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
mbed_official 19:112740acecfa 75 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
mbed_official 19:112740acecfa 76 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
mbed_official 19:112740acecfa 77 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
mbed_official 19:112740acecfa 78 /**
mbed_official 19:112740acecfa 79 * @}
mbed_official 19:112740acecfa 80 */
mbed_official 19:112740acecfa 81
mbed_official 19:112740acecfa 82 /* Private variables ---------------------------------------------------------*/
mbed_official 19:112740acecfa 83 /* Private constants ---------------------------------------------------------*/
mbed_official 19:112740acecfa 84 /* Private macros ------------------------------------------------------------*/
mbed_official 19:112740acecfa 85 /* Private function prototypes -----------------------------------------------*/
mbed_official 19:112740acecfa 86 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
mbed_official 19:112740acecfa 87
mbed_official 19:112740acecfa 88 /* Private functions ---------------------------------------------------------*/
mbed_official 19:112740acecfa 89 /**
mbed_official 19:112740acecfa 90 * @brief Generic DSI packet header configuration
mbed_official 19:112740acecfa 91 * @param DSIx: Pointer to DSI register base
mbed_official 19:112740acecfa 92 * @param ChannelID: Virtual channel ID of the header packet
mbed_official 19:112740acecfa 93 * @param DataType: Packet data type of the header packet
mbed_official 19:112740acecfa 94 * This parameter can be any value of :
mbed_official 19:112740acecfa 95 * @ref DSI_SHORT_WRITE_PKT_Data_Type
mbed_official 19:112740acecfa 96 * or @ref DSI_LONG_WRITE_PKT_Data_Type
mbed_official 19:112740acecfa 97 * or @ref DSI_SHORT_READ_PKT_Data_Type
mbed_official 19:112740acecfa 98 * or DSI_MAX_RETURN_PKT_SIZE
mbed_official 19:112740acecfa 99 * @param Data0: Word count LSB
mbed_official 19:112740acecfa 100 * @param Data1: Word count MSB
mbed_official 19:112740acecfa 101 * @retval None
mbed_official 19:112740acecfa 102 */
mbed_official 19:112740acecfa 103 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
mbed_official 19:112740acecfa 104 uint32_t ChannelID,
mbed_official 19:112740acecfa 105 uint32_t DataType,
mbed_official 19:112740acecfa 106 uint32_t Data0,
mbed_official 19:112740acecfa 107 uint32_t Data1)
mbed_official 19:112740acecfa 108 {
mbed_official 19:112740acecfa 109 /* Update the DSI packet header with new information */
mbed_official 19:112740acecfa 110 DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));
mbed_official 19:112740acecfa 111 }
mbed_official 19:112740acecfa 112
mbed_official 19:112740acecfa 113 /* Exported functions --------------------------------------------------------*/
mbed_official 19:112740acecfa 114 /** @addtogroup DSI_Exported_Functions
mbed_official 19:112740acecfa 115 * @{
mbed_official 19:112740acecfa 116 */
mbed_official 19:112740acecfa 117
mbed_official 19:112740acecfa 118 /** @defgroup DSI_Group1 Initialization and Configuration functions
mbed_official 19:112740acecfa 119 * @brief Initialization and Configuration functions
mbed_official 19:112740acecfa 120 *
mbed_official 19:112740acecfa 121 @verbatim
mbed_official 19:112740acecfa 122 ===============================================================================
mbed_official 19:112740acecfa 123 ##### Initialization and Configuration functions #####
mbed_official 19:112740acecfa 124 ===============================================================================
mbed_official 19:112740acecfa 125 [..] This section provides functions allowing to:
mbed_official 19:112740acecfa 126 (+) Initialize and configure the DSI
mbed_official 19:112740acecfa 127 (+) De-initialize the DSI
mbed_official 19:112740acecfa 128
mbed_official 19:112740acecfa 129 @endverbatim
mbed_official 19:112740acecfa 130 * @{
mbed_official 19:112740acecfa 131 */
mbed_official 19:112740acecfa 132
mbed_official 19:112740acecfa 133 /**
mbed_official 19:112740acecfa 134 * @brief Initializes the DSI according to the specified
mbed_official 19:112740acecfa 135 * parameters in the DSI_InitTypeDef and create the associated handle.
mbed_official 19:112740acecfa 136 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 137 * the configuration information for the DSI.
mbed_official 19:112740acecfa 138 * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
mbed_official 19:112740acecfa 139 * the PLL Clock structure definition for the DSI.
mbed_official 19:112740acecfa 140 * @retval HAL status
mbed_official 19:112740acecfa 141 */
mbed_official 19:112740acecfa 142 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
mbed_official 19:112740acecfa 143 {
mbed_official 19:112740acecfa 144 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 145 uint32_t unitIntervalx4 = 0;
mbed_official 19:112740acecfa 146 uint32_t tempIDF = 0;
mbed_official 19:112740acecfa 147
mbed_official 19:112740acecfa 148 /* Check the DSI handle allocation */
mbed_official 19:112740acecfa 149 if(hdsi == NULL)
mbed_official 19:112740acecfa 150 {
mbed_official 19:112740acecfa 151 return HAL_ERROR;
mbed_official 19:112740acecfa 152 }
mbed_official 19:112740acecfa 153
mbed_official 19:112740acecfa 154 /* Check function parameters */
mbed_official 19:112740acecfa 155 assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
mbed_official 19:112740acecfa 156 assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
mbed_official 19:112740acecfa 157 assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
mbed_official 19:112740acecfa 158 assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
mbed_official 19:112740acecfa 159 assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
mbed_official 19:112740acecfa 160
mbed_official 19:112740acecfa 161 if(hdsi->State == HAL_DSI_STATE_RESET)
mbed_official 19:112740acecfa 162 {
mbed_official 19:112740acecfa 163 /* Initialize the low level hardware */
mbed_official 19:112740acecfa 164 HAL_DSI_MspInit(hdsi);
mbed_official 19:112740acecfa 165 }
mbed_official 19:112740acecfa 166
mbed_official 19:112740acecfa 167 /* Change DSI peripheral state */
mbed_official 19:112740acecfa 168 hdsi->State = HAL_DSI_STATE_BUSY;
mbed_official 19:112740acecfa 169
mbed_official 19:112740acecfa 170 /**************** Turn on the regulator and enable the DSI PLL ****************/
mbed_official 19:112740acecfa 171
mbed_official 19:112740acecfa 172 /* Enable the regulator */
mbed_official 19:112740acecfa 173 __HAL_DSI_REG_ENABLE(hdsi);
mbed_official 19:112740acecfa 174
mbed_official 19:112740acecfa 175 /* Get tick */
mbed_official 19:112740acecfa 176 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 177
mbed_official 19:112740acecfa 178 /* Wait until the regulator is ready */
mbed_official 19:112740acecfa 179 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
mbed_official 19:112740acecfa 180 {
mbed_official 19:112740acecfa 181 /* Check for the Timeout */
mbed_official 19:112740acecfa 182 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 183 {
mbed_official 19:112740acecfa 184 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 185 }
mbed_official 19:112740acecfa 186 }
mbed_official 19:112740acecfa 187
mbed_official 19:112740acecfa 188 /* Set the PLL division factors */
mbed_official 19:112740acecfa 189 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
mbed_official 19:112740acecfa 190 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));
mbed_official 19:112740acecfa 191
mbed_official 19:112740acecfa 192 /* Enable the DSI PLL */
mbed_official 19:112740acecfa 193 __HAL_DSI_PLL_ENABLE(hdsi);
mbed_official 19:112740acecfa 194
mbed_official 19:112740acecfa 195 /* Get tick */
mbed_official 19:112740acecfa 196 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 197
mbed_official 19:112740acecfa 198 /* Wait for the lock of the PLL */
mbed_official 19:112740acecfa 199 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
mbed_official 19:112740acecfa 200 {
mbed_official 19:112740acecfa 201 /* Check for the Timeout */
mbed_official 19:112740acecfa 202 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 203 {
mbed_official 19:112740acecfa 204 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 205 }
mbed_official 19:112740acecfa 206 }
mbed_official 19:112740acecfa 207
mbed_official 19:112740acecfa 208 /*************************** Set the PHY parameters ***************************/
mbed_official 19:112740acecfa 209
mbed_official 19:112740acecfa 210 /* D-PHY clock and digital enable*/
mbed_official 19:112740acecfa 211 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
mbed_official 19:112740acecfa 212
mbed_official 19:112740acecfa 213 /* Clock lane configuration */
mbed_official 19:112740acecfa 214 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
mbed_official 19:112740acecfa 215 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
mbed_official 19:112740acecfa 216
mbed_official 19:112740acecfa 217 /* Configure the number of active data lanes */
mbed_official 19:112740acecfa 218 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
mbed_official 19:112740acecfa 219 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
mbed_official 19:112740acecfa 220
mbed_official 19:112740acecfa 221 /************************ Set the DSI clock parameters ************************/
mbed_official 19:112740acecfa 222
mbed_official 19:112740acecfa 223 /* Set the TX escape clock division factor */
mbed_official 19:112740acecfa 224 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
mbed_official 19:112740acecfa 225 hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;
mbed_official 19:112740acecfa 226
mbed_official 19:112740acecfa 227 /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
mbed_official 19:112740acecfa 228 /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
mbed_official 19:112740acecfa 229 /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
mbed_official 19:112740acecfa 230 tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;
mbed_official 19:112740acecfa 231 unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);
mbed_official 19:112740acecfa 232
mbed_official 19:112740acecfa 233 /* Set the bit period in high-speed mode */
mbed_official 19:112740acecfa 234 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4;
mbed_official 19:112740acecfa 235 hdsi->Instance->WPCR[0] |= unitIntervalx4;
mbed_official 19:112740acecfa 236
mbed_official 19:112740acecfa 237 /****************************** Error management *****************************/
mbed_official 19:112740acecfa 238
mbed_official 19:112740acecfa 239 /* Disable all error interrupts and reset the Error Mask */
mbed_official 19:112740acecfa 240 hdsi->Instance->IER[0] = 0;
mbed_official 19:112740acecfa 241 hdsi->Instance->IER[1] = 0;
mbed_official 19:112740acecfa 242 hdsi->ErrorMsk = 0;
mbed_official 19:112740acecfa 243
mbed_official 19:112740acecfa 244 /* Initialise the error code */
mbed_official 19:112740acecfa 245 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
mbed_official 19:112740acecfa 246
mbed_official 19:112740acecfa 247 /* Initialize the DSI state*/
mbed_official 19:112740acecfa 248 hdsi->State = HAL_DSI_STATE_READY;
mbed_official 19:112740acecfa 249
mbed_official 19:112740acecfa 250 return HAL_OK;
mbed_official 19:112740acecfa 251 }
mbed_official 19:112740acecfa 252
mbed_official 19:112740acecfa 253 /**
mbed_official 19:112740acecfa 254 * @brief De-initializes the DSI peripheral registers to their default reset
mbed_official 19:112740acecfa 255 * values.
mbed_official 19:112740acecfa 256 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 257 * the configuration information for the DSI.
mbed_official 19:112740acecfa 258 * @retval HAL status
mbed_official 19:112740acecfa 259 */
mbed_official 19:112740acecfa 260 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 261 {
mbed_official 19:112740acecfa 262 /* Check the DSI handle allocation */
mbed_official 19:112740acecfa 263 if(hdsi == NULL)
mbed_official 19:112740acecfa 264 {
mbed_official 19:112740acecfa 265 return HAL_ERROR;
mbed_official 19:112740acecfa 266 }
mbed_official 19:112740acecfa 267
mbed_official 19:112740acecfa 268 /* Change DSI peripheral state */
mbed_official 19:112740acecfa 269 hdsi->State = HAL_DSI_STATE_BUSY;
mbed_official 19:112740acecfa 270
mbed_official 19:112740acecfa 271 /* Disable the DSI wrapper */
mbed_official 19:112740acecfa 272 __HAL_DSI_WRAPPER_DISABLE(hdsi);
mbed_official 19:112740acecfa 273
mbed_official 19:112740acecfa 274 /* Disable the DSI host */
mbed_official 19:112740acecfa 275 __HAL_DSI_DISABLE(hdsi);
mbed_official 19:112740acecfa 276
mbed_official 19:112740acecfa 277 /* D-PHY clock and digital disable */
mbed_official 19:112740acecfa 278 hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
mbed_official 19:112740acecfa 279
mbed_official 19:112740acecfa 280 /* Turn off the DSI PLL */
mbed_official 19:112740acecfa 281 __HAL_DSI_PLL_DISABLE(hdsi);
mbed_official 19:112740acecfa 282
mbed_official 19:112740acecfa 283 /* Disable the regulator */
mbed_official 19:112740acecfa 284 __HAL_DSI_REG_DISABLE(hdsi);
mbed_official 19:112740acecfa 285
mbed_official 19:112740acecfa 286 /* DeInit the low level hardware */
mbed_official 19:112740acecfa 287 HAL_DSI_MspDeInit(hdsi);
mbed_official 19:112740acecfa 288
mbed_official 19:112740acecfa 289 /* Initialise the error code */
mbed_official 19:112740acecfa 290 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
mbed_official 19:112740acecfa 291
mbed_official 19:112740acecfa 292 /* Initialize the DSI state*/
mbed_official 19:112740acecfa 293 hdsi->State = HAL_DSI_STATE_RESET;
mbed_official 19:112740acecfa 294
mbed_official 19:112740acecfa 295 /* Release Lock */
mbed_official 19:112740acecfa 296 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 297
mbed_official 19:112740acecfa 298 return HAL_OK;
mbed_official 19:112740acecfa 299 }
mbed_official 19:112740acecfa 300
mbed_official 19:112740acecfa 301 /**
mbed_official 19:112740acecfa 302 * @brief Return the DSI error code
mbed_official 19:112740acecfa 303 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 304 * the configuration information for the DSI.
mbed_official 19:112740acecfa 305 * @retval DSI Error Code
mbed_official 19:112740acecfa 306 */
mbed_official 19:112740acecfa 307 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 308 {
mbed_official 19:112740acecfa 309 /* Get the error code */
mbed_official 19:112740acecfa 310 return hdsi->ErrorCode;
mbed_official 19:112740acecfa 311 }
mbed_official 19:112740acecfa 312
mbed_official 19:112740acecfa 313 /**
mbed_official 19:112740acecfa 314 * @brief Enable the error monitor flags
mbed_official 19:112740acecfa 315 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 316 * the configuration information for the DSI.
mbed_official 19:112740acecfa 317 * @param ActiveErrors: indicates which error interrupts will be enabled.
mbed_official 19:112740acecfa 318 * This parameter can be any combination of @ref DSI_Error_Data_Type.
mbed_official 19:112740acecfa 319 * @retval HAL status
mbed_official 19:112740acecfa 320 */
mbed_official 19:112740acecfa 321 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
mbed_official 19:112740acecfa 322 {
mbed_official 19:112740acecfa 323 /* Process locked */
mbed_official 19:112740acecfa 324 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 325
mbed_official 19:112740acecfa 326 hdsi->Instance->IER[0] = 0;
mbed_official 19:112740acecfa 327 hdsi->Instance->IER[1] = 0;
mbed_official 19:112740acecfa 328
mbed_official 19:112740acecfa 329 /* Store active errors to the handle */
mbed_official 19:112740acecfa 330 hdsi->ErrorMsk = ActiveErrors;
mbed_official 19:112740acecfa 331
mbed_official 19:112740acecfa 332 if(ActiveErrors & HAL_DSI_ERROR_ACK)
mbed_official 19:112740acecfa 333 {
mbed_official 19:112740acecfa 334 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 335 hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK;
mbed_official 19:112740acecfa 336 }
mbed_official 19:112740acecfa 337
mbed_official 19:112740acecfa 338 if(ActiveErrors & HAL_DSI_ERROR_PHY)
mbed_official 19:112740acecfa 339 {
mbed_official 19:112740acecfa 340 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 341 hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK;
mbed_official 19:112740acecfa 342 }
mbed_official 19:112740acecfa 343
mbed_official 19:112740acecfa 344 if(ActiveErrors & HAL_DSI_ERROR_TX)
mbed_official 19:112740acecfa 345 {
mbed_official 19:112740acecfa 346 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 347 hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK;
mbed_official 19:112740acecfa 348 }
mbed_official 19:112740acecfa 349
mbed_official 19:112740acecfa 350 if(ActiveErrors & HAL_DSI_ERROR_RX)
mbed_official 19:112740acecfa 351 {
mbed_official 19:112740acecfa 352 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 353 hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK;
mbed_official 19:112740acecfa 354 }
mbed_official 19:112740acecfa 355
mbed_official 19:112740acecfa 356 if(ActiveErrors & HAL_DSI_ERROR_ECC)
mbed_official 19:112740acecfa 357 {
mbed_official 19:112740acecfa 358 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 359 hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK;
mbed_official 19:112740acecfa 360 }
mbed_official 19:112740acecfa 361
mbed_official 19:112740acecfa 362 if(ActiveErrors & HAL_DSI_ERROR_CRC)
mbed_official 19:112740acecfa 363 {
mbed_official 19:112740acecfa 364 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 365 hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK;
mbed_official 19:112740acecfa 366 }
mbed_official 19:112740acecfa 367
mbed_official 19:112740acecfa 368 if(ActiveErrors & HAL_DSI_ERROR_PSE)
mbed_official 19:112740acecfa 369 {
mbed_official 19:112740acecfa 370 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 371 hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK;
mbed_official 19:112740acecfa 372 }
mbed_official 19:112740acecfa 373
mbed_official 19:112740acecfa 374 if(ActiveErrors & HAL_DSI_ERROR_EOT)
mbed_official 19:112740acecfa 375 {
mbed_official 19:112740acecfa 376 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 377 hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK;
mbed_official 19:112740acecfa 378 }
mbed_official 19:112740acecfa 379
mbed_official 19:112740acecfa 380 if(ActiveErrors & HAL_DSI_ERROR_OVF)
mbed_official 19:112740acecfa 381 {
mbed_official 19:112740acecfa 382 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 383 hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK;
mbed_official 19:112740acecfa 384 }
mbed_official 19:112740acecfa 385
mbed_official 19:112740acecfa 386 if(ActiveErrors & HAL_DSI_ERROR_GEN)
mbed_official 19:112740acecfa 387 {
mbed_official 19:112740acecfa 388 /* Enable the interrupt generation on selected errors */
mbed_official 19:112740acecfa 389 hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK;
mbed_official 19:112740acecfa 390 }
mbed_official 19:112740acecfa 391
mbed_official 19:112740acecfa 392 /* Process Unlocked */
mbed_official 19:112740acecfa 393 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 394
mbed_official 19:112740acecfa 395 return HAL_OK;
mbed_official 19:112740acecfa 396 }
mbed_official 19:112740acecfa 397
mbed_official 19:112740acecfa 398 /**
mbed_official 19:112740acecfa 399 * @brief Initializes the DSI MSP.
mbed_official 19:112740acecfa 400 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 401 * the configuration information for the DSI.
mbed_official 19:112740acecfa 402 * @retval None
mbed_official 19:112740acecfa 403 */
mbed_official 19:112740acecfa 404 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
mbed_official 19:112740acecfa 405 {
mbed_official 19:112740acecfa 406 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 19:112740acecfa 407 the HAL_DSI_MspInit could be implemented in the user file
mbed_official 19:112740acecfa 408 */
mbed_official 19:112740acecfa 409 }
mbed_official 19:112740acecfa 410
mbed_official 19:112740acecfa 411 /**
mbed_official 19:112740acecfa 412 * @brief De-initializes the DSI MSP.
mbed_official 19:112740acecfa 413 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 414 * the configuration information for the DSI.
mbed_official 19:112740acecfa 415 * @retval None
mbed_official 19:112740acecfa 416 */
mbed_official 19:112740acecfa 417 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
mbed_official 19:112740acecfa 418 {
mbed_official 19:112740acecfa 419 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 19:112740acecfa 420 the HAL_DSI_MspDeInit could be implemented in the user file
mbed_official 19:112740acecfa 421 */
mbed_official 19:112740acecfa 422 }
mbed_official 19:112740acecfa 423
mbed_official 19:112740acecfa 424 /**
mbed_official 19:112740acecfa 425 * @}
mbed_official 19:112740acecfa 426 */
mbed_official 19:112740acecfa 427
mbed_official 19:112740acecfa 428 /** @defgroup DSI_Group2 IO operation functions
mbed_official 19:112740acecfa 429 * @brief IO operation functions
mbed_official 19:112740acecfa 430 *
mbed_official 19:112740acecfa 431 @verbatim
mbed_official 19:112740acecfa 432 ===============================================================================
mbed_official 19:112740acecfa 433 ##### IO operation functions #####
mbed_official 19:112740acecfa 434 ===============================================================================
mbed_official 19:112740acecfa 435 [..] This section provides function allowing to:
mbed_official 19:112740acecfa 436 (+) Handle DSI interrupt request
mbed_official 19:112740acecfa 437
mbed_official 19:112740acecfa 438 @endverbatim
mbed_official 19:112740acecfa 439 * @{
mbed_official 19:112740acecfa 440 */
mbed_official 19:112740acecfa 441 /**
mbed_official 19:112740acecfa 442 * @brief Handles DSI interrupt request.
mbed_official 19:112740acecfa 443 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 444 * the configuration information for the DSI.
mbed_official 19:112740acecfa 445 * @retval HAL status
mbed_official 19:112740acecfa 446 */
mbed_official 19:112740acecfa 447 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 448 {
mbed_official 19:112740acecfa 449 uint32_t ErrorStatus0, ErrorStatus1;
mbed_official 19:112740acecfa 450
mbed_official 19:112740acecfa 451 /* Tearing Effect Interrupt management ***************************************/
mbed_official 19:112740acecfa 452 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
mbed_official 19:112740acecfa 453 {
mbed_official 19:112740acecfa 454 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
mbed_official 19:112740acecfa 455 {
mbed_official 19:112740acecfa 456 /* Clear the Tearing Effect Interrupt Flag */
mbed_official 19:112740acecfa 457 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
mbed_official 19:112740acecfa 458
mbed_official 19:112740acecfa 459 /* Tearing Effect Callback */
mbed_official 19:112740acecfa 460 HAL_DSI_TearingEffectCallback(hdsi);
mbed_official 19:112740acecfa 461 }
mbed_official 19:112740acecfa 462 }
mbed_official 19:112740acecfa 463
mbed_official 19:112740acecfa 464 /* End of Refresh Interrupt management ***************************************/
mbed_official 19:112740acecfa 465 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
mbed_official 19:112740acecfa 466 {
mbed_official 19:112740acecfa 467 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
mbed_official 19:112740acecfa 468 {
mbed_official 19:112740acecfa 469 /* Clear the End of Refresh Interrupt Flag */
mbed_official 19:112740acecfa 470 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
mbed_official 19:112740acecfa 471
mbed_official 19:112740acecfa 472 /* End of Refresh Callback */
mbed_official 19:112740acecfa 473 HAL_DSI_EndOfRefreshCallback(hdsi);
mbed_official 19:112740acecfa 474 }
mbed_official 19:112740acecfa 475 }
mbed_official 19:112740acecfa 476
mbed_official 19:112740acecfa 477 /* Error Interrupts management ***********************************************/
mbed_official 19:112740acecfa 478 if(hdsi->ErrorMsk != 0)
mbed_official 19:112740acecfa 479 {
mbed_official 19:112740acecfa 480 ErrorStatus0 = hdsi->Instance->ISR[0];
mbed_official 19:112740acecfa 481 ErrorStatus0 &= hdsi->Instance->IER[0];
mbed_official 19:112740acecfa 482 ErrorStatus1 = hdsi->Instance->ISR[1];
mbed_official 19:112740acecfa 483 ErrorStatus1 &= hdsi->Instance->IER[1];
mbed_official 19:112740acecfa 484
mbed_official 19:112740acecfa 485 if(ErrorStatus0 & DSI_ERROR_ACK_MASK)
mbed_official 19:112740acecfa 486 {
mbed_official 19:112740acecfa 487 hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
mbed_official 19:112740acecfa 488 }
mbed_official 19:112740acecfa 489
mbed_official 19:112740acecfa 490 if(ErrorStatus0 & DSI_ERROR_PHY_MASK)
mbed_official 19:112740acecfa 491 {
mbed_official 19:112740acecfa 492 hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
mbed_official 19:112740acecfa 493 }
mbed_official 19:112740acecfa 494
mbed_official 19:112740acecfa 495 if(ErrorStatus1 & DSI_ERROR_TX_MASK)
mbed_official 19:112740acecfa 496 {
mbed_official 19:112740acecfa 497 hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
mbed_official 19:112740acecfa 498 }
mbed_official 19:112740acecfa 499
mbed_official 19:112740acecfa 500 if(ErrorStatus1 & DSI_ERROR_RX_MASK)
mbed_official 19:112740acecfa 501 {
mbed_official 19:112740acecfa 502 hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
mbed_official 19:112740acecfa 503 }
mbed_official 19:112740acecfa 504
mbed_official 19:112740acecfa 505 if(ErrorStatus1 & DSI_ERROR_ECC_MASK)
mbed_official 19:112740acecfa 506 {
mbed_official 19:112740acecfa 507 hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
mbed_official 19:112740acecfa 508 }
mbed_official 19:112740acecfa 509
mbed_official 19:112740acecfa 510 if(ErrorStatus1 & DSI_ERROR_CRC_MASK)
mbed_official 19:112740acecfa 511 {
mbed_official 19:112740acecfa 512 hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
mbed_official 19:112740acecfa 513 }
mbed_official 19:112740acecfa 514
mbed_official 19:112740acecfa 515 if(ErrorStatus1 & DSI_ERROR_PSE_MASK)
mbed_official 19:112740acecfa 516 {
mbed_official 19:112740acecfa 517 hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
mbed_official 19:112740acecfa 518 }
mbed_official 19:112740acecfa 519
mbed_official 19:112740acecfa 520 if(ErrorStatus1 & DSI_ERROR_EOT_MASK)
mbed_official 19:112740acecfa 521 {
mbed_official 19:112740acecfa 522 hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
mbed_official 19:112740acecfa 523 }
mbed_official 19:112740acecfa 524
mbed_official 19:112740acecfa 525 if(ErrorStatus1 & DSI_ERROR_OVF_MASK)
mbed_official 19:112740acecfa 526 {
mbed_official 19:112740acecfa 527 hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
mbed_official 19:112740acecfa 528 }
mbed_official 19:112740acecfa 529
mbed_official 19:112740acecfa 530 if(ErrorStatus1 & DSI_ERROR_GEN_MASK)
mbed_official 19:112740acecfa 531 {
mbed_official 19:112740acecfa 532 hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
mbed_official 19:112740acecfa 533 }
mbed_official 19:112740acecfa 534
mbed_official 19:112740acecfa 535 /* Check only selected errors */
mbed_official 19:112740acecfa 536 if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
mbed_official 19:112740acecfa 537 {
mbed_official 19:112740acecfa 538 /* DSI error interrupt user callback */
mbed_official 19:112740acecfa 539 HAL_DSI_ErrorCallback(hdsi);
mbed_official 19:112740acecfa 540 }
mbed_official 19:112740acecfa 541 }
mbed_official 19:112740acecfa 542 }
mbed_official 19:112740acecfa 543
mbed_official 19:112740acecfa 544 /**
mbed_official 19:112740acecfa 545 * @brief Tearing Effect DSI callback.
mbed_official 19:112740acecfa 546 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 547 * the configuration information for the DSI.
mbed_official 19:112740acecfa 548 * @retval None
mbed_official 19:112740acecfa 549 */
mbed_official 19:112740acecfa 550 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 551 {
mbed_official 19:112740acecfa 552 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 19:112740acecfa 553 the HAL_DSI_TearingEffectCallback could be implemented in the user file
mbed_official 19:112740acecfa 554 */
mbed_official 19:112740acecfa 555 }
mbed_official 19:112740acecfa 556
mbed_official 19:112740acecfa 557 /**
mbed_official 19:112740acecfa 558 * @brief End of Refresh DSI callback.
mbed_official 19:112740acecfa 559 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 560 * the configuration information for the DSI.
mbed_official 19:112740acecfa 561 * @retval None
mbed_official 19:112740acecfa 562 */
mbed_official 19:112740acecfa 563 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 564 {
mbed_official 19:112740acecfa 565 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 19:112740acecfa 566 the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
mbed_official 19:112740acecfa 567 */
mbed_official 19:112740acecfa 568 }
mbed_official 19:112740acecfa 569
mbed_official 19:112740acecfa 570 /**
mbed_official 19:112740acecfa 571 * @brief Operation Error DSI callback.
mbed_official 19:112740acecfa 572 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 573 * the configuration information for the DSI.
mbed_official 19:112740acecfa 574 * @retval None
mbed_official 19:112740acecfa 575 */
mbed_official 19:112740acecfa 576 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 577 {
mbed_official 19:112740acecfa 578 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 19:112740acecfa 579 the HAL_DSI_ErrorCallback could be implemented in the user file
mbed_official 19:112740acecfa 580 */
mbed_official 19:112740acecfa 581 }
mbed_official 19:112740acecfa 582
mbed_official 19:112740acecfa 583 /**
mbed_official 19:112740acecfa 584 * @}
mbed_official 19:112740acecfa 585 */
mbed_official 19:112740acecfa 586
mbed_official 19:112740acecfa 587 /** @defgroup DSI_Group3 Peripheral Control functions
mbed_official 19:112740acecfa 588 * @brief Peripheral Control functions
mbed_official 19:112740acecfa 589 *
mbed_official 19:112740acecfa 590 @verbatim
mbed_official 19:112740acecfa 591 ===============================================================================
mbed_official 19:112740acecfa 592 ##### Peripheral Control functions #####
mbed_official 19:112740acecfa 593 ===============================================================================
mbed_official 19:112740acecfa 594 [..] This section provides functions allowing to:
mbed_official 19:112740acecfa 595 (+)
mbed_official 19:112740acecfa 596 (+)
mbed_official 19:112740acecfa 597 (+)
mbed_official 19:112740acecfa 598
mbed_official 19:112740acecfa 599 @endverbatim
mbed_official 19:112740acecfa 600 * @{
mbed_official 19:112740acecfa 601 */
mbed_official 19:112740acecfa 602
mbed_official 19:112740acecfa 603 /**
mbed_official 19:112740acecfa 604 * @brief Configure the Generic interface read-back Virtual Channel ID.
mbed_official 19:112740acecfa 605 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 606 * the configuration information for the DSI.
mbed_official 19:112740acecfa 607 * @param VirtualChannelID: Virtual channel ID
mbed_official 19:112740acecfa 608 * @retval HAL status
mbed_official 19:112740acecfa 609 */
mbed_official 19:112740acecfa 610 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
mbed_official 19:112740acecfa 611 {
mbed_official 19:112740acecfa 612 /* Process locked */
mbed_official 19:112740acecfa 613 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 614
mbed_official 19:112740acecfa 615 /* Update the GVCID register */
mbed_official 19:112740acecfa 616 hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
mbed_official 19:112740acecfa 617 hdsi->Instance->GVCIDR |= VirtualChannelID;
mbed_official 19:112740acecfa 618
mbed_official 19:112740acecfa 619 /* Process unlocked */
mbed_official 19:112740acecfa 620 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 621
mbed_official 19:112740acecfa 622 return HAL_OK;
mbed_official 19:112740acecfa 623 }
mbed_official 19:112740acecfa 624
mbed_official 19:112740acecfa 625 /**
mbed_official 19:112740acecfa 626 * @brief Select video mode and configure the corresponding parameters
mbed_official 19:112740acecfa 627 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 628 * the configuration information for the DSI.
mbed_official 19:112740acecfa 629 * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
mbed_official 19:112740acecfa 630 * the DSI video mode configuration parameters
mbed_official 19:112740acecfa 631 * @retval HAL status
mbed_official 19:112740acecfa 632 */
mbed_official 19:112740acecfa 633 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
mbed_official 19:112740acecfa 634 {
mbed_official 19:112740acecfa 635 /* Process locked */
mbed_official 19:112740acecfa 636 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 637
mbed_official 19:112740acecfa 638 /* Check the parameters */
mbed_official 19:112740acecfa 639 assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
mbed_official 19:112740acecfa 640 assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
mbed_official 19:112740acecfa 641 assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
mbed_official 19:112740acecfa 642 assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
mbed_official 19:112740acecfa 643 assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
mbed_official 19:112740acecfa 644 assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
mbed_official 19:112740acecfa 645 assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
mbed_official 19:112740acecfa 646 assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
mbed_official 19:112740acecfa 647 assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
mbed_official 19:112740acecfa 648 assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
mbed_official 19:112740acecfa 649 assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
mbed_official 19:112740acecfa 650 assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
mbed_official 19:112740acecfa 651 assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
mbed_official 19:112740acecfa 652 /* Check the LooselyPacked variant only in 18-bit mode */
mbed_official 19:112740acecfa 653 if(VidCfg->ColorCoding == DSI_RGB666)
mbed_official 19:112740acecfa 654 {
mbed_official 19:112740acecfa 655 assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
mbed_official 19:112740acecfa 656 }
mbed_official 19:112740acecfa 657
mbed_official 19:112740acecfa 658 /* Select video mode by resetting CMDM and DSIM bits */
mbed_official 19:112740acecfa 659 hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
mbed_official 19:112740acecfa 660 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
mbed_official 19:112740acecfa 661
mbed_official 19:112740acecfa 662 /* Configure the video mode transmission type */
mbed_official 19:112740acecfa 663 hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
mbed_official 19:112740acecfa 664 hdsi->Instance->VMCR |= VidCfg->Mode;
mbed_official 19:112740acecfa 665
mbed_official 19:112740acecfa 666 /* Configure the video packet size */
mbed_official 19:112740acecfa 667 hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
mbed_official 19:112740acecfa 668 hdsi->Instance->VPCR |= VidCfg->PacketSize;
mbed_official 19:112740acecfa 669
mbed_official 19:112740acecfa 670 /* Set the chunks number to be transmitted through the DSI link */
mbed_official 19:112740acecfa 671 hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
mbed_official 19:112740acecfa 672 hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
mbed_official 19:112740acecfa 673
mbed_official 19:112740acecfa 674 /* Set the size of the null packet */
mbed_official 19:112740acecfa 675 hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
mbed_official 19:112740acecfa 676 hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
mbed_official 19:112740acecfa 677
mbed_official 19:112740acecfa 678 /* Select the virtual channel for the LTDC interface traffic */
mbed_official 19:112740acecfa 679 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
mbed_official 19:112740acecfa 680 hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
mbed_official 19:112740acecfa 681
mbed_official 19:112740acecfa 682 /* Configure the polarity of control signals */
mbed_official 19:112740acecfa 683 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
mbed_official 19:112740acecfa 684 hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
mbed_official 19:112740acecfa 685
mbed_official 19:112740acecfa 686 /* Select the color coding for the host */
mbed_official 19:112740acecfa 687 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
mbed_official 19:112740acecfa 688 hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
mbed_official 19:112740acecfa 689
mbed_official 19:112740acecfa 690 /* Select the color coding for the wrapper */
mbed_official 19:112740acecfa 691 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
mbed_official 19:112740acecfa 692 hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1);
mbed_official 19:112740acecfa 693
mbed_official 19:112740acecfa 694 /* Enable/disable the loosely packed variant to 18-bit configuration */
mbed_official 19:112740acecfa 695 if(VidCfg->ColorCoding == DSI_RGB666)
mbed_official 19:112740acecfa 696 {
mbed_official 19:112740acecfa 697 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
mbed_official 19:112740acecfa 698 hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
mbed_official 19:112740acecfa 699 }
mbed_official 19:112740acecfa 700
mbed_official 19:112740acecfa 701 /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
mbed_official 19:112740acecfa 702 hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
mbed_official 19:112740acecfa 703 hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
mbed_official 19:112740acecfa 704
mbed_official 19:112740acecfa 705 /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
mbed_official 19:112740acecfa 706 hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
mbed_official 19:112740acecfa 707 hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
mbed_official 19:112740acecfa 708
mbed_official 19:112740acecfa 709 /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
mbed_official 19:112740acecfa 710 hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
mbed_official 19:112740acecfa 711 hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
mbed_official 19:112740acecfa 712
mbed_official 19:112740acecfa 713 /* Set the Vertical Synchronization Active (VSA) */
mbed_official 19:112740acecfa 714 hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
mbed_official 19:112740acecfa 715 hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
mbed_official 19:112740acecfa 716
mbed_official 19:112740acecfa 717 /* Set the Vertical Back Porch (VBP)*/
mbed_official 19:112740acecfa 718 hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
mbed_official 19:112740acecfa 719 hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
mbed_official 19:112740acecfa 720
mbed_official 19:112740acecfa 721 /* Set the Vertical Front Porch (VFP)*/
mbed_official 19:112740acecfa 722 hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
mbed_official 19:112740acecfa 723 hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
mbed_official 19:112740acecfa 724
mbed_official 19:112740acecfa 725 /* Set the Vertical Active period*/
mbed_official 19:112740acecfa 726 hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
mbed_official 19:112740acecfa 727 hdsi->Instance->VVACR |= VidCfg->VerticalActive;
mbed_official 19:112740acecfa 728
mbed_official 19:112740acecfa 729 /* Configure the command transmission mode */
mbed_official 19:112740acecfa 730 hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
mbed_official 19:112740acecfa 731 hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
mbed_official 19:112740acecfa 732
mbed_official 19:112740acecfa 733 /* Low power largest packet size */
mbed_official 19:112740acecfa 734 hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
mbed_official 19:112740acecfa 735 hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);
mbed_official 19:112740acecfa 736
mbed_official 19:112740acecfa 737 /* Low power VACT largest packet size */
mbed_official 19:112740acecfa 738 hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
mbed_official 19:112740acecfa 739 hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
mbed_official 19:112740acecfa 740
mbed_official 19:112740acecfa 741 /* Enable LP transition in HFP period */
mbed_official 19:112740acecfa 742 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
mbed_official 19:112740acecfa 743 hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
mbed_official 19:112740acecfa 744
mbed_official 19:112740acecfa 745 /* Enable LP transition in HBP period */
mbed_official 19:112740acecfa 746 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
mbed_official 19:112740acecfa 747 hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
mbed_official 19:112740acecfa 748
mbed_official 19:112740acecfa 749 /* Enable LP transition in VACT period */
mbed_official 19:112740acecfa 750 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
mbed_official 19:112740acecfa 751 hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
mbed_official 19:112740acecfa 752
mbed_official 19:112740acecfa 753 /* Enable LP transition in VFP period */
mbed_official 19:112740acecfa 754 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
mbed_official 19:112740acecfa 755 hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
mbed_official 19:112740acecfa 756
mbed_official 19:112740acecfa 757 /* Enable LP transition in VBP period */
mbed_official 19:112740acecfa 758 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
mbed_official 19:112740acecfa 759 hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
mbed_official 19:112740acecfa 760
mbed_official 19:112740acecfa 761 /* Enable LP transition in vertical sync period */
mbed_official 19:112740acecfa 762 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
mbed_official 19:112740acecfa 763 hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
mbed_official 19:112740acecfa 764
mbed_official 19:112740acecfa 765 /* Enable the request for an acknowledge response at the end of a frame */
mbed_official 19:112740acecfa 766 hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
mbed_official 19:112740acecfa 767 hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
mbed_official 19:112740acecfa 768
mbed_official 19:112740acecfa 769 /* Process unlocked */
mbed_official 19:112740acecfa 770 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 771
mbed_official 19:112740acecfa 772 return HAL_OK;
mbed_official 19:112740acecfa 773 }
mbed_official 19:112740acecfa 774
mbed_official 19:112740acecfa 775 /**
mbed_official 19:112740acecfa 776 * @brief Select adapted command mode and configure the corresponding parameters
mbed_official 19:112740acecfa 777 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 778 * the configuration information for the DSI.
mbed_official 19:112740acecfa 779 * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
mbed_official 19:112740acecfa 780 * the DSI command mode configuration parameters
mbed_official 19:112740acecfa 781 * @retval HAL status
mbed_official 19:112740acecfa 782 */
mbed_official 19:112740acecfa 783 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
mbed_official 19:112740acecfa 784 {
mbed_official 19:112740acecfa 785 /* Process locked */
mbed_official 19:112740acecfa 786 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 787
mbed_official 19:112740acecfa 788 /* Check the parameters */
mbed_official 19:112740acecfa 789 assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
mbed_official 19:112740acecfa 790 assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
mbed_official 19:112740acecfa 791 assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
mbed_official 19:112740acecfa 792 assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
mbed_official 19:112740acecfa 793 assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
mbed_official 19:112740acecfa 794 assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
mbed_official 19:112740acecfa 795 assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
mbed_official 19:112740acecfa 796 assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
mbed_official 19:112740acecfa 797 assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
mbed_official 19:112740acecfa 798
mbed_official 19:112740acecfa 799 /* Select command mode by setting CMDM and DSIM bits */
mbed_official 19:112740acecfa 800 hdsi->Instance->MCR |= DSI_MCR_CMDM;
mbed_official 19:112740acecfa 801 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
mbed_official 19:112740acecfa 802 hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
mbed_official 19:112740acecfa 803
mbed_official 19:112740acecfa 804 /* Select the virtual channel for the LTDC interface traffic */
mbed_official 19:112740acecfa 805 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
mbed_official 19:112740acecfa 806 hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
mbed_official 19:112740acecfa 807
mbed_official 19:112740acecfa 808 /* Configure the polarity of control signals */
mbed_official 19:112740acecfa 809 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
mbed_official 19:112740acecfa 810 hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
mbed_official 19:112740acecfa 811
mbed_official 19:112740acecfa 812 /* Select the color coding for the host */
mbed_official 19:112740acecfa 813 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
mbed_official 19:112740acecfa 814 hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
mbed_official 19:112740acecfa 815
mbed_official 19:112740acecfa 816 /* Select the color coding for the wrapper */
mbed_official 19:112740acecfa 817 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
mbed_official 19:112740acecfa 818 hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1);
mbed_official 19:112740acecfa 819
mbed_official 19:112740acecfa 820 /* Configure the maximum allowed size for write memory command */
mbed_official 19:112740acecfa 821 hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
mbed_official 19:112740acecfa 822 hdsi->Instance->LCCR |= CmdCfg->CommandSize;
mbed_official 19:112740acecfa 823
mbed_official 19:112740acecfa 824 /* Configure the tearing effect source and polarity and select the refresh mode */
mbed_official 19:112740acecfa 825 hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
mbed_official 19:112740acecfa 826 hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
mbed_official 19:112740acecfa 827
mbed_official 19:112740acecfa 828 /* Configure the tearing effect acknowledge request */
mbed_official 19:112740acecfa 829 hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
mbed_official 19:112740acecfa 830 hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
mbed_official 19:112740acecfa 831
mbed_official 19:112740acecfa 832 /* Enable the Tearing Effect interrupt */
mbed_official 19:112740acecfa 833 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
mbed_official 19:112740acecfa 834
mbed_official 19:112740acecfa 835 /* Enable the End of Refresh interrupt */
mbed_official 19:112740acecfa 836 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
mbed_official 19:112740acecfa 837
mbed_official 19:112740acecfa 838 /* Process unlocked */
mbed_official 19:112740acecfa 839 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 840
mbed_official 19:112740acecfa 841 return HAL_OK;
mbed_official 19:112740acecfa 842 }
mbed_official 19:112740acecfa 843
mbed_official 19:112740acecfa 844 /**
mbed_official 19:112740acecfa 845 * @brief Configure command transmission mode: High-speed or Low-power
mbed_official 19:112740acecfa 846 * and enable/disable acknowledge request after packet transmission
mbed_official 19:112740acecfa 847 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 848 * the configuration information for the DSI.
mbed_official 19:112740acecfa 849 * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
mbed_official 19:112740acecfa 850 * the DSI command transmission mode configuration parameters
mbed_official 19:112740acecfa 851 * @retval HAL status
mbed_official 19:112740acecfa 852 */
mbed_official 19:112740acecfa 853 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
mbed_official 19:112740acecfa 854 {
mbed_official 19:112740acecfa 855 /* Process locked */
mbed_official 19:112740acecfa 856 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 857
mbed_official 19:112740acecfa 858 assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
mbed_official 19:112740acecfa 859 assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
mbed_official 19:112740acecfa 860 assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
mbed_official 19:112740acecfa 861 assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
mbed_official 19:112740acecfa 862 assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
mbed_official 19:112740acecfa 863 assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
mbed_official 19:112740acecfa 864 assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
mbed_official 19:112740acecfa 865 assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
mbed_official 19:112740acecfa 866 assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
mbed_official 19:112740acecfa 867 assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
mbed_official 19:112740acecfa 868 assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
mbed_official 19:112740acecfa 869 assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
mbed_official 19:112740acecfa 870 assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
mbed_official 19:112740acecfa 871
mbed_official 19:112740acecfa 872 /* Select High-speed or Low-power for command transmission */
mbed_official 19:112740acecfa 873 hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
mbed_official 19:112740acecfa 874 DSI_CMCR_GSW1TX |\
mbed_official 19:112740acecfa 875 DSI_CMCR_GSW2TX |\
mbed_official 19:112740acecfa 876 DSI_CMCR_GSR0TX |\
mbed_official 19:112740acecfa 877 DSI_CMCR_GSR1TX |\
mbed_official 19:112740acecfa 878 DSI_CMCR_GSR2TX |\
mbed_official 19:112740acecfa 879 DSI_CMCR_GLWTX |\
mbed_official 19:112740acecfa 880 DSI_CMCR_DSW0TX |\
mbed_official 19:112740acecfa 881 DSI_CMCR_DSW1TX |\
mbed_official 19:112740acecfa 882 DSI_CMCR_DSR0TX |\
mbed_official 19:112740acecfa 883 DSI_CMCR_DLWTX |\
mbed_official 19:112740acecfa 884 DSI_CMCR_MRDPS);
mbed_official 19:112740acecfa 885 hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
mbed_official 19:112740acecfa 886 LPCmd->LPGenShortWriteOneP |\
mbed_official 19:112740acecfa 887 LPCmd->LPGenShortWriteTwoP |\
mbed_official 19:112740acecfa 888 LPCmd->LPGenShortReadNoP |\
mbed_official 19:112740acecfa 889 LPCmd->LPGenShortReadOneP |\
mbed_official 19:112740acecfa 890 LPCmd->LPGenShortReadTwoP |\
mbed_official 19:112740acecfa 891 LPCmd->LPGenLongWrite |\
mbed_official 19:112740acecfa 892 LPCmd->LPDcsShortWriteNoP |\
mbed_official 19:112740acecfa 893 LPCmd->LPDcsShortWriteOneP |\
mbed_official 19:112740acecfa 894 LPCmd->LPDcsShortReadNoP |\
mbed_official 19:112740acecfa 895 LPCmd->LPDcsLongWrite |\
mbed_official 19:112740acecfa 896 LPCmd->LPMaxReadPacket);
mbed_official 19:112740acecfa 897
mbed_official 19:112740acecfa 898 /* Configure the acknowledge request after each packet transmission */
mbed_official 19:112740acecfa 899 hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
mbed_official 19:112740acecfa 900 hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
mbed_official 19:112740acecfa 901
mbed_official 19:112740acecfa 902 /* Process unlocked */
mbed_official 19:112740acecfa 903 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 904
mbed_official 19:112740acecfa 905 return HAL_OK;
mbed_official 19:112740acecfa 906 }
mbed_official 19:112740acecfa 907
mbed_official 19:112740acecfa 908 /**
mbed_official 19:112740acecfa 909 * @brief Configure the flow control parameters
mbed_official 19:112740acecfa 910 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 911 * the configuration information for the DSI.
mbed_official 19:112740acecfa 912 * @param FlowControl: flow control feature(s) to be enabled.
mbed_official 19:112740acecfa 913 * This parameter can be any combination of @ref DSI_FlowControl.
mbed_official 19:112740acecfa 914 * @retval HAL status
mbed_official 19:112740acecfa 915 */
mbed_official 19:112740acecfa 916 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
mbed_official 19:112740acecfa 917 {
mbed_official 19:112740acecfa 918 /* Process locked */
mbed_official 19:112740acecfa 919 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 920
mbed_official 19:112740acecfa 921 /* Check the parameters */
mbed_official 19:112740acecfa 922 assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
mbed_official 19:112740acecfa 923
mbed_official 19:112740acecfa 924 /* Set the DSI Host Protocol Configuration Register */
mbed_official 19:112740acecfa 925 hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
mbed_official 19:112740acecfa 926 hdsi->Instance->PCR |= FlowControl;
mbed_official 19:112740acecfa 927
mbed_official 19:112740acecfa 928 /* Process unlocked */
mbed_official 19:112740acecfa 929 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 930
mbed_official 19:112740acecfa 931 return HAL_OK;
mbed_official 19:112740acecfa 932 }
mbed_official 19:112740acecfa 933
mbed_official 19:112740acecfa 934 /**
mbed_official 19:112740acecfa 935 * @brief Configure the DSI PHY timer parameters
mbed_official 19:112740acecfa 936 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 937 * the configuration information for the DSI.
mbed_official 19:112740acecfa 938 * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
mbed_official 19:112740acecfa 939 * the DSI PHY timing parameters
mbed_official 19:112740acecfa 940 * @retval HAL status
mbed_official 19:112740acecfa 941 */
mbed_official 19:112740acecfa 942 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
mbed_official 19:112740acecfa 943 {
mbed_official 19:112740acecfa 944 uint32_t maxTime;
mbed_official 19:112740acecfa 945 /* Process locked */
mbed_official 19:112740acecfa 946 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 947
mbed_official 19:112740acecfa 948 maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
mbed_official 19:112740acecfa 949
mbed_official 19:112740acecfa 950 /* Clock lane timer configuration */
mbed_official 19:112740acecfa 951
mbed_official 19:112740acecfa 952 /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
mbed_official 19:112740acecfa 953 High-Speed transmission.
mbed_official 19:112740acecfa 954 To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
mbed_official 19:112740acecfa 955 to Low-Power and from Low-Power to High-Speed.
mbed_official 19:112740acecfa 956 This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
mbed_official 19:112740acecfa 957 But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
mbed_official 19:112740acecfa 958
mbed_official 19:112740acecfa 959 Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
mbed_official 19:112740acecfa 960 */
mbed_official 19:112740acecfa 961 hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
mbed_official 19:112740acecfa 962 hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16));
mbed_official 19:112740acecfa 963
mbed_official 19:112740acecfa 964 /* Data lane timer configuration */
mbed_official 19:112740acecfa 965 hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
mbed_official 19:112740acecfa 966 hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));
mbed_official 19:112740acecfa 967
mbed_official 19:112740acecfa 968 /* Configure the wait period to request HS transmission after a stop state */
mbed_official 19:112740acecfa 969 hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
mbed_official 19:112740acecfa 970 hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8);
mbed_official 19:112740acecfa 971
mbed_official 19:112740acecfa 972 /* Process unlocked */
mbed_official 19:112740acecfa 973 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 974
mbed_official 19:112740acecfa 975 return HAL_OK;
mbed_official 19:112740acecfa 976 }
mbed_official 19:112740acecfa 977
mbed_official 19:112740acecfa 978 /**
mbed_official 19:112740acecfa 979 * @brief Configure the DSI HOST timeout parameters
mbed_official 19:112740acecfa 980 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 981 * the configuration information for the DSI.
mbed_official 19:112740acecfa 982 * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
mbed_official 19:112740acecfa 983 * the DSI host timeout parameters
mbed_official 19:112740acecfa 984 * @retval HAL status
mbed_official 19:112740acecfa 985 */
mbed_official 19:112740acecfa 986 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
mbed_official 19:112740acecfa 987 {
mbed_official 19:112740acecfa 988 /* Process locked */
mbed_official 19:112740acecfa 989 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 990
mbed_official 19:112740acecfa 991 /* Set the timeout clock division factor */
mbed_official 19:112740acecfa 992 hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
mbed_official 19:112740acecfa 993 hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8);
mbed_official 19:112740acecfa 994
mbed_official 19:112740acecfa 995 /* High-speed transmission timeout */
mbed_official 19:112740acecfa 996 hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;
mbed_official 19:112740acecfa 997 hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);
mbed_official 19:112740acecfa 998
mbed_official 19:112740acecfa 999 /* Low-power reception timeout */
mbed_official 19:112740acecfa 1000 hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;
mbed_official 19:112740acecfa 1001 hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;
mbed_official 19:112740acecfa 1002
mbed_official 19:112740acecfa 1003 /* High-speed read timeout */
mbed_official 19:112740acecfa 1004 hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;
mbed_official 19:112740acecfa 1005 hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;
mbed_official 19:112740acecfa 1006
mbed_official 19:112740acecfa 1007 /* Low-power read timeout */
mbed_official 19:112740acecfa 1008 hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;
mbed_official 19:112740acecfa 1009 hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;
mbed_official 19:112740acecfa 1010
mbed_official 19:112740acecfa 1011 /* High-speed write timeout */
mbed_official 19:112740acecfa 1012 hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;
mbed_official 19:112740acecfa 1013 hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;
mbed_official 19:112740acecfa 1014
mbed_official 19:112740acecfa 1015 /* High-speed write presp mode */
mbed_official 19:112740acecfa 1016 hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM;
mbed_official 19:112740acecfa 1017 hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;
mbed_official 19:112740acecfa 1018
mbed_official 19:112740acecfa 1019 /* Low-speed write timeout */
mbed_official 19:112740acecfa 1020 hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;
mbed_official 19:112740acecfa 1021 hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;
mbed_official 19:112740acecfa 1022
mbed_official 19:112740acecfa 1023 /* BTA timeout */
mbed_official 19:112740acecfa 1024 hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;
mbed_official 19:112740acecfa 1025 hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout;
mbed_official 19:112740acecfa 1026
mbed_official 19:112740acecfa 1027 /* Process unlocked */
mbed_official 19:112740acecfa 1028 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1029
mbed_official 19:112740acecfa 1030 return HAL_OK;
mbed_official 19:112740acecfa 1031 }
mbed_official 19:112740acecfa 1032
mbed_official 19:112740acecfa 1033 /**
mbed_official 19:112740acecfa 1034 * @brief Start the DSI module
mbed_official 19:112740acecfa 1035 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1036 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1037 * @retval HAL status
mbed_official 19:112740acecfa 1038 */
mbed_official 19:112740acecfa 1039 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 1040 {
mbed_official 19:112740acecfa 1041 /* Process locked */
mbed_official 19:112740acecfa 1042 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1043
mbed_official 19:112740acecfa 1044 /* Enable the DSI host */
mbed_official 19:112740acecfa 1045 __HAL_DSI_ENABLE(hdsi);
mbed_official 19:112740acecfa 1046
mbed_official 19:112740acecfa 1047 /* Enable the DSI wrapper */
mbed_official 19:112740acecfa 1048 __HAL_DSI_WRAPPER_ENABLE(hdsi);
mbed_official 19:112740acecfa 1049
mbed_official 19:112740acecfa 1050 /* Process unlocked */
mbed_official 19:112740acecfa 1051 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1052
mbed_official 19:112740acecfa 1053 return HAL_OK;
mbed_official 19:112740acecfa 1054 }
mbed_official 19:112740acecfa 1055
mbed_official 19:112740acecfa 1056 /**
mbed_official 19:112740acecfa 1057 * @brief Stop the DSI module
mbed_official 19:112740acecfa 1058 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1059 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1060 * @retval HAL status
mbed_official 19:112740acecfa 1061 */
mbed_official 19:112740acecfa 1062 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 1063 {
mbed_official 19:112740acecfa 1064 /* Process locked */
mbed_official 19:112740acecfa 1065 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1066
mbed_official 19:112740acecfa 1067 /* Disable the DSI host */
mbed_official 19:112740acecfa 1068 __HAL_DSI_DISABLE(hdsi);
mbed_official 19:112740acecfa 1069
mbed_official 19:112740acecfa 1070 /* Disable the DSI wrapper */
mbed_official 19:112740acecfa 1071 __HAL_DSI_WRAPPER_DISABLE(hdsi);
mbed_official 19:112740acecfa 1072
mbed_official 19:112740acecfa 1073 /* Process unlocked */
mbed_official 19:112740acecfa 1074 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1075
mbed_official 19:112740acecfa 1076 return HAL_OK;
mbed_official 19:112740acecfa 1077 }
mbed_official 19:112740acecfa 1078
mbed_official 19:112740acecfa 1079 /**
mbed_official 19:112740acecfa 1080 * @brief Refresh the display in command mode
mbed_official 19:112740acecfa 1081 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1082 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1083 * @retval HAL status
mbed_official 19:112740acecfa 1084 */
mbed_official 19:112740acecfa 1085 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 1086 {
mbed_official 19:112740acecfa 1087 /* Process locked */
mbed_official 19:112740acecfa 1088 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1089
mbed_official 19:112740acecfa 1090 /* Update the display */
mbed_official 19:112740acecfa 1091 hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
mbed_official 19:112740acecfa 1092
mbed_official 19:112740acecfa 1093 /* Process unlocked */
mbed_official 19:112740acecfa 1094 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1095
mbed_official 19:112740acecfa 1096 return HAL_OK;
mbed_official 19:112740acecfa 1097 }
mbed_official 19:112740acecfa 1098
mbed_official 19:112740acecfa 1099 /**
mbed_official 19:112740acecfa 1100 * @brief Controls the display color mode in Video mode
mbed_official 19:112740acecfa 1101 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1102 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1103 * @param ColorMode: Color mode (full or 8-colors).
mbed_official 19:112740acecfa 1104 * This parameter can be any value of @ref DSI_Color_Mode
mbed_official 19:112740acecfa 1105 * @retval HAL status
mbed_official 19:112740acecfa 1106 */
mbed_official 19:112740acecfa 1107 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
mbed_official 19:112740acecfa 1108 {
mbed_official 19:112740acecfa 1109 /* Process locked */
mbed_official 19:112740acecfa 1110 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1111
mbed_official 19:112740acecfa 1112 /* Check the parameters */
mbed_official 19:112740acecfa 1113 assert_param(IS_DSI_COLOR_MODE(ColorMode));
mbed_official 19:112740acecfa 1114
mbed_official 19:112740acecfa 1115 /* Update the display color mode */
mbed_official 19:112740acecfa 1116 hdsi->Instance->WCR &= ~DSI_WCR_COLM;
mbed_official 19:112740acecfa 1117 hdsi->Instance->WCR |= ColorMode;
mbed_official 19:112740acecfa 1118
mbed_official 19:112740acecfa 1119 /* Process unlocked */
mbed_official 19:112740acecfa 1120 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1121
mbed_official 19:112740acecfa 1122 return HAL_OK;
mbed_official 19:112740acecfa 1123 }
mbed_official 19:112740acecfa 1124
mbed_official 19:112740acecfa 1125 /**
mbed_official 19:112740acecfa 1126 * @brief Control the display shutdown in Video mode
mbed_official 19:112740acecfa 1127 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1128 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1129 * @param Shutdown: Shut-down (Display-ON or Display-OFF).
mbed_official 19:112740acecfa 1130 * This parameter can be any value of @ref DSI_ShutDown
mbed_official 19:112740acecfa 1131 * @retval HAL status
mbed_official 19:112740acecfa 1132 */
mbed_official 19:112740acecfa 1133 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
mbed_official 19:112740acecfa 1134 {
mbed_official 19:112740acecfa 1135 /* Process locked */
mbed_official 19:112740acecfa 1136 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1137
mbed_official 19:112740acecfa 1138 /* Check the parameters */
mbed_official 19:112740acecfa 1139 assert_param(IS_DSI_SHUT_DOWN(Shutdown));
mbed_official 19:112740acecfa 1140
mbed_official 19:112740acecfa 1141 /* Update the display Shutdown */
mbed_official 19:112740acecfa 1142 hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
mbed_official 19:112740acecfa 1143 hdsi->Instance->WCR |= Shutdown;
mbed_official 19:112740acecfa 1144
mbed_official 19:112740acecfa 1145 /* Process unlocked */
mbed_official 19:112740acecfa 1146 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1147
mbed_official 19:112740acecfa 1148 return HAL_OK;
mbed_official 19:112740acecfa 1149 }
mbed_official 19:112740acecfa 1150
mbed_official 19:112740acecfa 1151 /**
mbed_official 19:112740acecfa 1152 * @brief DCS or Generic short write command
mbed_official 19:112740acecfa 1153 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1154 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1155 * @param ChannelID: Virtual channel ID.
mbed_official 19:112740acecfa 1156 * @param Mode: DSI short packet data type.
mbed_official 19:112740acecfa 1157 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
mbed_official 19:112740acecfa 1158 * @param Param1: DSC command or first generic parameter.
mbed_official 19:112740acecfa 1159 * This parameter can be any value of @ref DSI_DCS_Command or a
mbed_official 19:112740acecfa 1160 * generic command code.
mbed_official 19:112740acecfa 1161 * @param Param2: DSC parameter or second generic parameter.
mbed_official 19:112740acecfa 1162 * @retval HAL status
mbed_official 19:112740acecfa 1163 */
mbed_official 19:112740acecfa 1164 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
mbed_official 19:112740acecfa 1165 uint32_t ChannelID,
mbed_official 19:112740acecfa 1166 uint32_t Mode,
mbed_official 19:112740acecfa 1167 uint32_t Param1,
mbed_official 19:112740acecfa 1168 uint32_t Param2)
mbed_official 19:112740acecfa 1169 {
mbed_official 19:112740acecfa 1170 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 1171
mbed_official 19:112740acecfa 1172 /* Process locked */
mbed_official 19:112740acecfa 1173 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1174
mbed_official 19:112740acecfa 1175 /* Check the parameters */
mbed_official 19:112740acecfa 1176 assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
mbed_official 19:112740acecfa 1177
mbed_official 19:112740acecfa 1178 /* Get tick */
mbed_official 19:112740acecfa 1179 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1180
mbed_official 19:112740acecfa 1181 /* Wait for Command FIFO Empty */
mbed_official 19:112740acecfa 1182 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0)
mbed_official 19:112740acecfa 1183 {
mbed_official 19:112740acecfa 1184 /* Check for the Timeout */
mbed_official 19:112740acecfa 1185 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1186 {
mbed_official 19:112740acecfa 1187 /* Process Unlocked */
mbed_official 19:112740acecfa 1188 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1189
mbed_official 19:112740acecfa 1190 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1191 }
mbed_official 19:112740acecfa 1192 }
mbed_official 19:112740acecfa 1193
mbed_official 19:112740acecfa 1194 /* Configure the packet to send a short DCS command with 0 or 1 parameter */
mbed_official 19:112740acecfa 1195 DSI_ConfigPacketHeader(hdsi->Instance,
mbed_official 19:112740acecfa 1196 ChannelID,
mbed_official 19:112740acecfa 1197 Mode,
mbed_official 19:112740acecfa 1198 Param1,
mbed_official 19:112740acecfa 1199 Param2);
mbed_official 19:112740acecfa 1200
mbed_official 19:112740acecfa 1201 /* Process unlocked */
mbed_official 19:112740acecfa 1202 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1203
mbed_official 19:112740acecfa 1204 return HAL_OK;
mbed_official 19:112740acecfa 1205 }
mbed_official 19:112740acecfa 1206
mbed_official 19:112740acecfa 1207 /**
mbed_official 19:112740acecfa 1208 * @brief DCS or Generic long write command
mbed_official 19:112740acecfa 1209 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1210 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1211 * @param ChannelID: Virtual channel ID.
mbed_official 19:112740acecfa 1212 * @param Mode: DSI long packet data type.
mbed_official 19:112740acecfa 1213 * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
mbed_official 19:112740acecfa 1214 * @param NbParams: Number of parameters.
mbed_official 19:112740acecfa 1215 * @param Param1: DSC command or first generic parameter.
mbed_official 19:112740acecfa 1216 * This parameter can be any value of @ref DSI_DCS_Command or a
mbed_official 19:112740acecfa 1217 * generic command code
mbed_official 19:112740acecfa 1218 * @param ParametersTable: Pointer to parameter values table.
mbed_official 19:112740acecfa 1219 * @retval HAL status
mbed_official 19:112740acecfa 1220 */
mbed_official 19:112740acecfa 1221 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
mbed_official 19:112740acecfa 1222 uint32_t ChannelID,
mbed_official 19:112740acecfa 1223 uint32_t Mode,
mbed_official 19:112740acecfa 1224 uint32_t NbParams,
mbed_official 19:112740acecfa 1225 uint32_t Param1,
mbed_official 19:112740acecfa 1226 uint8_t* ParametersTable)
mbed_official 19:112740acecfa 1227 {
mbed_official 19:112740acecfa 1228 uint32_t uicounter = 0;
mbed_official 19:112740acecfa 1229 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 1230
mbed_official 19:112740acecfa 1231 /* Process locked */
mbed_official 19:112740acecfa 1232 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1233
mbed_official 19:112740acecfa 1234 /* Check the parameters */
mbed_official 19:112740acecfa 1235 assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
mbed_official 19:112740acecfa 1236
mbed_official 19:112740acecfa 1237 /* Get tick */
mbed_official 19:112740acecfa 1238 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1239
mbed_official 19:112740acecfa 1240 /* Wait for Command FIFO Empty */
mbed_official 19:112740acecfa 1241 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
mbed_official 19:112740acecfa 1242 {
mbed_official 19:112740acecfa 1243 /* Check for the Timeout */
mbed_official 19:112740acecfa 1244 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1245 {
mbed_official 19:112740acecfa 1246 /* Process Unlocked */
mbed_official 19:112740acecfa 1247 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1248
mbed_official 19:112740acecfa 1249 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1250 }
mbed_official 19:112740acecfa 1251 }
mbed_official 19:112740acecfa 1252
mbed_official 19:112740acecfa 1253 /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
mbed_official 19:112740acecfa 1254 while(uicounter < NbParams)
mbed_official 19:112740acecfa 1255 {
mbed_official 19:112740acecfa 1256 if(uicounter == 0x00)
mbed_official 19:112740acecfa 1257 {
mbed_official 19:112740acecfa 1258 hdsi->Instance->GPDR=(Param1 | \
mbed_official 19:112740acecfa 1259 ((*(ParametersTable+uicounter))<<8) | \
mbed_official 19:112740acecfa 1260 ((*(ParametersTable+uicounter+1))<<16) | \
mbed_official 19:112740acecfa 1261 ((*(ParametersTable+uicounter+2))<<24));
mbed_official 19:112740acecfa 1262 uicounter += 3;
mbed_official 19:112740acecfa 1263 }
mbed_official 19:112740acecfa 1264 else
mbed_official 19:112740acecfa 1265 {
mbed_official 19:112740acecfa 1266 hdsi->Instance->GPDR=((*(ParametersTable+uicounter)) | \
mbed_official 19:112740acecfa 1267 ((*(ParametersTable+uicounter+1))<<8) | \
mbed_official 19:112740acecfa 1268 ((*(ParametersTable+uicounter+2))<<16) | \
mbed_official 19:112740acecfa 1269 ((*(ParametersTable+uicounter+3))<<24));
mbed_official 19:112740acecfa 1270 uicounter+=4;
mbed_official 19:112740acecfa 1271 }
mbed_official 19:112740acecfa 1272 }
mbed_official 19:112740acecfa 1273
mbed_official 19:112740acecfa 1274 /* Configure the packet to send a long DCS command */
mbed_official 19:112740acecfa 1275 DSI_ConfigPacketHeader(hdsi->Instance,
mbed_official 19:112740acecfa 1276 ChannelID,
mbed_official 19:112740acecfa 1277 Mode,
mbed_official 19:112740acecfa 1278 ((NbParams+1)&0x00FF),
mbed_official 19:112740acecfa 1279 (((NbParams+1)&0xFF00)>>8));
mbed_official 19:112740acecfa 1280
mbed_official 19:112740acecfa 1281 /* Process unlocked */
mbed_official 19:112740acecfa 1282 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1283
mbed_official 19:112740acecfa 1284 return HAL_OK;
mbed_official 19:112740acecfa 1285 }
mbed_official 19:112740acecfa 1286
mbed_official 19:112740acecfa 1287 /**
mbed_official 19:112740acecfa 1288 * @brief Read command (DCS or generic)
mbed_official 19:112740acecfa 1289 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1290 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1291 * @param ChannelNbr: Virtual channel ID
mbed_official 19:112740acecfa 1292 * @param Array: pointer to a buffer to store the payload of a read back operation.
mbed_official 19:112740acecfa 1293 * @param Size: Data size to be read (in byte).
mbed_official 19:112740acecfa 1294 * @param Mode: DSI read packet data type.
mbed_official 19:112740acecfa 1295 * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
mbed_official 19:112740acecfa 1296 * @param DCSCmd: DCS get/read command.
mbed_official 19:112740acecfa 1297 * @param ParametersTable: Pointer to parameter values table.
mbed_official 19:112740acecfa 1298 * @retval HAL status
mbed_official 19:112740acecfa 1299 */
mbed_official 19:112740acecfa 1300 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
mbed_official 19:112740acecfa 1301 uint32_t ChannelNbr,
mbed_official 19:112740acecfa 1302 uint8_t* Array,
mbed_official 19:112740acecfa 1303 uint32_t Size,
mbed_official 19:112740acecfa 1304 uint32_t Mode,
mbed_official 19:112740acecfa 1305 uint32_t DCSCmd,
mbed_official 19:112740acecfa 1306 uint8_t* ParametersTable)
mbed_official 19:112740acecfa 1307 {
mbed_official 19:112740acecfa 1308 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 1309
mbed_official 19:112740acecfa 1310 /* Process locked */
mbed_official 19:112740acecfa 1311 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1312
mbed_official 19:112740acecfa 1313 /* Check the parameters */
mbed_official 19:112740acecfa 1314 assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
mbed_official 19:112740acecfa 1315
mbed_official 19:112740acecfa 1316 if(Size > 2)
mbed_official 19:112740acecfa 1317 {
mbed_official 19:112740acecfa 1318 /* set max return packet size */
mbed_official 19:112740acecfa 1319 HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));
mbed_official 19:112740acecfa 1320 }
mbed_official 19:112740acecfa 1321
mbed_official 19:112740acecfa 1322 /* Configure the packet to read command */
mbed_official 19:112740acecfa 1323 if (Mode == DSI_DCS_SHORT_PKT_READ)
mbed_official 19:112740acecfa 1324 {
mbed_official 19:112740acecfa 1325 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0);
mbed_official 19:112740acecfa 1326 }
mbed_official 19:112740acecfa 1327 else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
mbed_official 19:112740acecfa 1328 {
mbed_official 19:112740acecfa 1329 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0);
mbed_official 19:112740acecfa 1330 }
mbed_official 19:112740acecfa 1331 else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
mbed_official 19:112740acecfa 1332 {
mbed_official 19:112740acecfa 1333 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0);
mbed_official 19:112740acecfa 1334 }
mbed_official 19:112740acecfa 1335 else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
mbed_official 19:112740acecfa 1336 {
mbed_official 19:112740acecfa 1337 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);
mbed_official 19:112740acecfa 1338 }
mbed_official 19:112740acecfa 1339
mbed_official 19:112740acecfa 1340 /* Get tick */
mbed_official 19:112740acecfa 1341 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1342
mbed_official 19:112740acecfa 1343 /* Check that the payload read FIFO is not empty */
mbed_official 19:112740acecfa 1344 while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
mbed_official 19:112740acecfa 1345 {
mbed_official 19:112740acecfa 1346 /* Check for the Timeout */
mbed_official 19:112740acecfa 1347 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1348 {
mbed_official 19:112740acecfa 1349 /* Process Unlocked */
mbed_official 19:112740acecfa 1350 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1351
mbed_official 19:112740acecfa 1352 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1353 }
mbed_official 19:112740acecfa 1354 }
mbed_official 19:112740acecfa 1355
mbed_official 19:112740acecfa 1356 /* Get the first byte */
mbed_official 19:112740acecfa 1357 *((uint32_t *)Array) = (hdsi->Instance->GPDR);
mbed_official 19:112740acecfa 1358 if (Size > 4)
mbed_official 19:112740acecfa 1359 {
mbed_official 19:112740acecfa 1360 Size -= 4;
mbed_official 19:112740acecfa 1361 Array += 4;
mbed_official 19:112740acecfa 1362 }
mbed_official 19:112740acecfa 1363 else
mbed_official 19:112740acecfa 1364 {
mbed_official 19:112740acecfa 1365 /* Process unlocked */
mbed_official 19:112740acecfa 1366 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1367
mbed_official 19:112740acecfa 1368 return HAL_OK;
mbed_official 19:112740acecfa 1369 }
mbed_official 19:112740acecfa 1370
mbed_official 19:112740acecfa 1371 /* Get tick */
mbed_official 19:112740acecfa 1372 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1373
mbed_official 19:112740acecfa 1374 /* Get the remaining bytes if any */
mbed_official 19:112740acecfa 1375 while(((int)(Size)) > 0)
mbed_official 19:112740acecfa 1376 {
mbed_official 19:112740acecfa 1377 if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0)
mbed_official 19:112740acecfa 1378 {
mbed_official 19:112740acecfa 1379 *((uint32_t *)Array) = (hdsi->Instance->GPDR);
mbed_official 19:112740acecfa 1380 Size -= 4;
mbed_official 19:112740acecfa 1381 Array += 4;
mbed_official 19:112740acecfa 1382 }
mbed_official 19:112740acecfa 1383
mbed_official 19:112740acecfa 1384 /* Check for the Timeout */
mbed_official 19:112740acecfa 1385 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1386 {
mbed_official 19:112740acecfa 1387 /* Process Unlocked */
mbed_official 19:112740acecfa 1388 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1389
mbed_official 19:112740acecfa 1390 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1391 }
mbed_official 19:112740acecfa 1392 }
mbed_official 19:112740acecfa 1393
mbed_official 19:112740acecfa 1394 /* Process unlocked */
mbed_official 19:112740acecfa 1395 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1396
mbed_official 19:112740acecfa 1397 return HAL_OK;
mbed_official 19:112740acecfa 1398 }
mbed_official 19:112740acecfa 1399
mbed_official 19:112740acecfa 1400 /**
mbed_official 19:112740acecfa 1401 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
mbed_official 19:112740acecfa 1402 * (only data lanes are in ULPM)
mbed_official 19:112740acecfa 1403 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1404 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1405 * @retval HAL status
mbed_official 19:112740acecfa 1406 */
mbed_official 19:112740acecfa 1407 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 1408 {
mbed_official 19:112740acecfa 1409 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 1410
mbed_official 19:112740acecfa 1411 /* Process locked */
mbed_official 19:112740acecfa 1412 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1413
mbed_official 19:112740acecfa 1414 /* ULPS Request on Data Lanes */
mbed_official 19:112740acecfa 1415 hdsi->Instance->PUCR |= DSI_PUCR_URDL;
mbed_official 19:112740acecfa 1416
mbed_official 19:112740acecfa 1417 /* Get tick */
mbed_official 19:112740acecfa 1418 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1419
mbed_official 19:112740acecfa 1420 /* Wait until the D-PHY active lanes enter into ULPM */
mbed_official 19:112740acecfa 1421 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
mbed_official 19:112740acecfa 1422 {
mbed_official 19:112740acecfa 1423 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
mbed_official 19:112740acecfa 1424 {
mbed_official 19:112740acecfa 1425 /* Check for the Timeout */
mbed_official 19:112740acecfa 1426 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1427 {
mbed_official 19:112740acecfa 1428 /* Process Unlocked */
mbed_official 19:112740acecfa 1429 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1430
mbed_official 19:112740acecfa 1431 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1432 }
mbed_official 19:112740acecfa 1433 }
mbed_official 19:112740acecfa 1434 }
mbed_official 19:112740acecfa 1435 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
mbed_official 19:112740acecfa 1436 {
mbed_official 19:112740acecfa 1437 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
mbed_official 19:112740acecfa 1438 {
mbed_official 19:112740acecfa 1439 /* Check for the Timeout */
mbed_official 19:112740acecfa 1440 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1441 {
mbed_official 19:112740acecfa 1442 /* Process Unlocked */
mbed_official 19:112740acecfa 1443 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1444
mbed_official 19:112740acecfa 1445 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1446 }
mbed_official 19:112740acecfa 1447 }
mbed_official 19:112740acecfa 1448 }
mbed_official 19:112740acecfa 1449
mbed_official 19:112740acecfa 1450 /* Process unlocked */
mbed_official 19:112740acecfa 1451 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1452
mbed_official 19:112740acecfa 1453 return HAL_OK;
mbed_official 19:112740acecfa 1454 }
mbed_official 19:112740acecfa 1455
mbed_official 19:112740acecfa 1456 /**
mbed_official 19:112740acecfa 1457 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
mbed_official 19:112740acecfa 1458 * (only data lanes are in ULPM)
mbed_official 19:112740acecfa 1459 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1460 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1461 * @retval HAL status
mbed_official 19:112740acecfa 1462 */
mbed_official 19:112740acecfa 1463 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 1464 {
mbed_official 19:112740acecfa 1465 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 1466
mbed_official 19:112740acecfa 1467 /* Process locked */
mbed_official 19:112740acecfa 1468 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1469
mbed_official 19:112740acecfa 1470 /* Exit ULPS on Data Lanes */
mbed_official 19:112740acecfa 1471 hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
mbed_official 19:112740acecfa 1472
mbed_official 19:112740acecfa 1473 /* Get tick */
mbed_official 19:112740acecfa 1474 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1475
mbed_official 19:112740acecfa 1476 /* Wait until all active lanes exit ULPM */
mbed_official 19:112740acecfa 1477 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
mbed_official 19:112740acecfa 1478 {
mbed_official 19:112740acecfa 1479 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
mbed_official 19:112740acecfa 1480 {
mbed_official 19:112740acecfa 1481 /* Check for the Timeout */
mbed_official 19:112740acecfa 1482 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1483 {
mbed_official 19:112740acecfa 1484 /* Process Unlocked */
mbed_official 19:112740acecfa 1485 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1486
mbed_official 19:112740acecfa 1487 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1488 }
mbed_official 19:112740acecfa 1489 }
mbed_official 19:112740acecfa 1490 }
mbed_official 19:112740acecfa 1491 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
mbed_official 19:112740acecfa 1492 {
mbed_official 19:112740acecfa 1493 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
mbed_official 19:112740acecfa 1494 {
mbed_official 19:112740acecfa 1495 /* Check for the Timeout */
mbed_official 19:112740acecfa 1496 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1497 {
mbed_official 19:112740acecfa 1498 /* Process Unlocked */
mbed_official 19:112740acecfa 1499 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1500
mbed_official 19:112740acecfa 1501 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1502 }
mbed_official 19:112740acecfa 1503 }
mbed_official 19:112740acecfa 1504 }
mbed_official 19:112740acecfa 1505
mbed_official 19:112740acecfa 1506 /* De-assert the ULPM requests and the ULPM exit bits */
mbed_official 19:112740acecfa 1507 hdsi->Instance->PUCR = 0;
mbed_official 19:112740acecfa 1508
mbed_official 19:112740acecfa 1509 /* Process unlocked */
mbed_official 19:112740acecfa 1510 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1511
mbed_official 19:112740acecfa 1512 return HAL_OK;
mbed_official 19:112740acecfa 1513 }
mbed_official 19:112740acecfa 1514
mbed_official 19:112740acecfa 1515 /**
mbed_official 19:112740acecfa 1516 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
mbed_official 19:112740acecfa 1517 * (both data and clock lanes are in ULPM)
mbed_official 19:112740acecfa 1518 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1519 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1520 * @retval HAL status
mbed_official 19:112740acecfa 1521 */
mbed_official 19:112740acecfa 1522 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 1523 {
mbed_official 19:112740acecfa 1524 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 1525
mbed_official 19:112740acecfa 1526 /* Process locked */
mbed_official 19:112740acecfa 1527 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1528
mbed_official 19:112740acecfa 1529 /* Clock lane configuration: no more HS request */
mbed_official 19:112740acecfa 1530 hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
mbed_official 19:112740acecfa 1531
mbed_official 19:112740acecfa 1532 /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
mbed_official 19:112740acecfa 1533 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
mbed_official 19:112740acecfa 1534
mbed_official 19:112740acecfa 1535 /* ULPS Request on Clock and Data Lanes */
mbed_official 19:112740acecfa 1536 hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
mbed_official 19:112740acecfa 1537
mbed_official 19:112740acecfa 1538 /* Get tick */
mbed_official 19:112740acecfa 1539 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1540
mbed_official 19:112740acecfa 1541 /* Wait until all active lanes exit ULPM */
mbed_official 19:112740acecfa 1542 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
mbed_official 19:112740acecfa 1543 {
mbed_official 19:112740acecfa 1544 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
mbed_official 19:112740acecfa 1545 {
mbed_official 19:112740acecfa 1546 /* Check for the Timeout */
mbed_official 19:112740acecfa 1547 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1548 {
mbed_official 19:112740acecfa 1549 /* Process Unlocked */
mbed_official 19:112740acecfa 1550 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1551
mbed_official 19:112740acecfa 1552 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1553 }
mbed_official 19:112740acecfa 1554 }
mbed_official 19:112740acecfa 1555 }
mbed_official 19:112740acecfa 1556 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
mbed_official 19:112740acecfa 1557 {
mbed_official 19:112740acecfa 1558 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
mbed_official 19:112740acecfa 1559 {
mbed_official 19:112740acecfa 1560 /* Check for the Timeout */
mbed_official 19:112740acecfa 1561 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1562 {
mbed_official 19:112740acecfa 1563 /* Process Unlocked */
mbed_official 19:112740acecfa 1564 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1565
mbed_official 19:112740acecfa 1566 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1567 }
mbed_official 19:112740acecfa 1568 }
mbed_official 19:112740acecfa 1569 }
mbed_official 19:112740acecfa 1570
mbed_official 19:112740acecfa 1571 /* Turn off the DSI PLL */
mbed_official 19:112740acecfa 1572 __HAL_DSI_PLL_DISABLE(hdsi);
mbed_official 19:112740acecfa 1573
mbed_official 19:112740acecfa 1574 /* Process unlocked */
mbed_official 19:112740acecfa 1575 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1576
mbed_official 19:112740acecfa 1577 return HAL_OK;
mbed_official 19:112740acecfa 1578 }
mbed_official 19:112740acecfa 1579
mbed_official 19:112740acecfa 1580 /**
mbed_official 19:112740acecfa 1581 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
mbed_official 19:112740acecfa 1582 * (both data and clock lanes are in ULPM)
mbed_official 19:112740acecfa 1583 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1584 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1585 * @retval HAL status
mbed_official 19:112740acecfa 1586 */
mbed_official 19:112740acecfa 1587 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 1588 {
mbed_official 19:112740acecfa 1589 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 1590
mbed_official 19:112740acecfa 1591 /* Process locked */
mbed_official 19:112740acecfa 1592 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1593
mbed_official 19:112740acecfa 1594 /* Turn on the DSI PLL */
mbed_official 19:112740acecfa 1595 __HAL_DSI_PLL_ENABLE(hdsi);
mbed_official 19:112740acecfa 1596
mbed_official 19:112740acecfa 1597 /* Get tick */
mbed_official 19:112740acecfa 1598 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1599
mbed_official 19:112740acecfa 1600 /* Wait for the lock of the PLL */
mbed_official 19:112740acecfa 1601 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
mbed_official 19:112740acecfa 1602 {
mbed_official 19:112740acecfa 1603 /* Check for the Timeout */
mbed_official 19:112740acecfa 1604 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1605 {
mbed_official 19:112740acecfa 1606 /* Process Unlocked */
mbed_official 19:112740acecfa 1607 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1608
mbed_official 19:112740acecfa 1609 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1610 }
mbed_official 19:112740acecfa 1611 }
mbed_official 19:112740acecfa 1612
mbed_official 19:112740acecfa 1613 /* Exit ULPS on Clock and Data Lanes */
mbed_official 19:112740acecfa 1614 hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
mbed_official 19:112740acecfa 1615
mbed_official 19:112740acecfa 1616 /* Get tick */
mbed_official 19:112740acecfa 1617 tickstart = HAL_GetTick();
mbed_official 19:112740acecfa 1618
mbed_official 19:112740acecfa 1619 /* Wait until all active lanes exit ULPM */
mbed_official 19:112740acecfa 1620 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
mbed_official 19:112740acecfa 1621 {
mbed_official 19:112740acecfa 1622 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
mbed_official 19:112740acecfa 1623 {
mbed_official 19:112740acecfa 1624 /* Check for the Timeout */
mbed_official 19:112740acecfa 1625 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1626 {
mbed_official 19:112740acecfa 1627 /* Process Unlocked */
mbed_official 19:112740acecfa 1628 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1629
mbed_official 19:112740acecfa 1630 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1631 }
mbed_official 19:112740acecfa 1632 }
mbed_official 19:112740acecfa 1633 }
mbed_official 19:112740acecfa 1634 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
mbed_official 19:112740acecfa 1635 {
mbed_official 19:112740acecfa 1636 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
mbed_official 19:112740acecfa 1637 {
mbed_official 19:112740acecfa 1638 /* Check for the Timeout */
mbed_official 19:112740acecfa 1639 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
mbed_official 19:112740acecfa 1640 {
mbed_official 19:112740acecfa 1641 /* Process Unlocked */
mbed_official 19:112740acecfa 1642 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1643
mbed_official 19:112740acecfa 1644 return HAL_TIMEOUT;
mbed_official 19:112740acecfa 1645 }
mbed_official 19:112740acecfa 1646 }
mbed_official 19:112740acecfa 1647 }
mbed_official 19:112740acecfa 1648
mbed_official 19:112740acecfa 1649 /* De-assert the ULPM requests and the ULPM exit bits */
mbed_official 19:112740acecfa 1650 hdsi->Instance->PUCR = 0;
mbed_official 19:112740acecfa 1651
mbed_official 19:112740acecfa 1652 /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
mbed_official 19:112740acecfa 1653 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
mbed_official 19:112740acecfa 1654
mbed_official 19:112740acecfa 1655 /* Restore clock lane configuration to HS */
mbed_official 19:112740acecfa 1656 hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
mbed_official 19:112740acecfa 1657
mbed_official 19:112740acecfa 1658 /* Process unlocked */
mbed_official 19:112740acecfa 1659 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1660
mbed_official 19:112740acecfa 1661 return HAL_OK;
mbed_official 19:112740acecfa 1662 }
mbed_official 19:112740acecfa 1663
mbed_official 19:112740acecfa 1664 /**
mbed_official 19:112740acecfa 1665 * @brief Start test pattern generation
mbed_official 19:112740acecfa 1666 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1667 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1668 * @param Mode: Pattern generator mode
mbed_official 19:112740acecfa 1669 * This parameter can be one of the following values:
mbed_official 19:112740acecfa 1670 * 0 : Color bars (horizontal or vertical)
mbed_official 19:112740acecfa 1671 * 1 : BER pattern (vertical only)
mbed_official 19:112740acecfa 1672 * @param Orientation: Pattern generator orientation
mbed_official 19:112740acecfa 1673 * This parameter can be one of the following values:
mbed_official 19:112740acecfa 1674 * 0 : Vertical color bars
mbed_official 19:112740acecfa 1675 * 1 : Horizontal color bars
mbed_official 19:112740acecfa 1676 * @retval HAL status
mbed_official 19:112740acecfa 1677 */
mbed_official 19:112740acecfa 1678 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
mbed_official 19:112740acecfa 1679 {
mbed_official 19:112740acecfa 1680 /* Process locked */
mbed_official 19:112740acecfa 1681 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1682
mbed_official 19:112740acecfa 1683 /* Configure pattern generator mode and orientation */
mbed_official 19:112740acecfa 1684 hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
mbed_official 19:112740acecfa 1685 hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24));
mbed_official 19:112740acecfa 1686
mbed_official 19:112740acecfa 1687 /* Enable pattern generator by setting PGE bit */
mbed_official 19:112740acecfa 1688 hdsi->Instance->VMCR |= DSI_VMCR_PGE;
mbed_official 19:112740acecfa 1689
mbed_official 19:112740acecfa 1690 /* Process unlocked */
mbed_official 19:112740acecfa 1691 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1692
mbed_official 19:112740acecfa 1693 return HAL_OK;
mbed_official 19:112740acecfa 1694 }
mbed_official 19:112740acecfa 1695
mbed_official 19:112740acecfa 1696 /**
mbed_official 19:112740acecfa 1697 * @brief Stop test pattern generation
mbed_official 19:112740acecfa 1698 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1699 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1700 * @retval HAL status
mbed_official 19:112740acecfa 1701 */
mbed_official 19:112740acecfa 1702 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 1703 {
mbed_official 19:112740acecfa 1704 /* Process locked */
mbed_official 19:112740acecfa 1705 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1706
mbed_official 19:112740acecfa 1707 /* Disable pattern generator by clearing PGE bit */
mbed_official 19:112740acecfa 1708 hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
mbed_official 19:112740acecfa 1709
mbed_official 19:112740acecfa 1710 /* Process unlocked */
mbed_official 19:112740acecfa 1711 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1712
mbed_official 19:112740acecfa 1713 return HAL_OK;
mbed_official 19:112740acecfa 1714 }
mbed_official 19:112740acecfa 1715
mbed_official 19:112740acecfa 1716 /**
mbed_official 19:112740acecfa 1717 * @brief Set Slew-Rate And Delay Tuning
mbed_official 19:112740acecfa 1718 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1719 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1720 * @param CommDelay: Communication delay to be adjusted.
mbed_official 19:112740acecfa 1721 * This parameter can be any value of @ref DSI_Communication_Delay
mbed_official 19:112740acecfa 1722 * @param Lane: select between clock or data lanes.
mbed_official 19:112740acecfa 1723 * This parameter can be any value of @ref DSI_Lane_Group
mbed_official 19:112740acecfa 1724 * @param Value: Custom value of the slew-rate or delay
mbed_official 19:112740acecfa 1725 * @retval HAL status
mbed_official 19:112740acecfa 1726 */
mbed_official 19:112740acecfa 1727 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
mbed_official 19:112740acecfa 1728 {
mbed_official 19:112740acecfa 1729 /* Process locked */
mbed_official 19:112740acecfa 1730 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1731
mbed_official 19:112740acecfa 1732 /* Check function parameters */
mbed_official 19:112740acecfa 1733 assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
mbed_official 19:112740acecfa 1734 assert_param(IS_DSI_LANE_GROUP(Lane));
mbed_official 19:112740acecfa 1735
mbed_official 19:112740acecfa 1736 switch(CommDelay)
mbed_official 19:112740acecfa 1737 {
mbed_official 19:112740acecfa 1738 case DSI_SLEW_RATE_HSTX:
mbed_official 19:112740acecfa 1739 if(Lane == DSI_CLOCK_LANE)
mbed_official 19:112740acecfa 1740 {
mbed_official 19:112740acecfa 1741 /* High-Speed Transmission Slew Rate Control on Clock Lane */
mbed_official 19:112740acecfa 1742 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;
mbed_official 19:112740acecfa 1743 hdsi->Instance->WPCR[1] |= Value<<16;
mbed_official 19:112740acecfa 1744 }
mbed_official 19:112740acecfa 1745 else if(Lane == DSI_DATA_LANES)
mbed_official 19:112740acecfa 1746 {
mbed_official 19:112740acecfa 1747 /* High-Speed Transmission Slew Rate Control on Data Lanes */
mbed_official 19:112740acecfa 1748 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;
mbed_official 19:112740acecfa 1749 hdsi->Instance->WPCR[1] |= Value<<18;
mbed_official 19:112740acecfa 1750 }
mbed_official 19:112740acecfa 1751 break;
mbed_official 19:112740acecfa 1752 case DSI_SLEW_RATE_LPTX:
mbed_official 19:112740acecfa 1753 if(Lane == DSI_CLOCK_LANE)
mbed_official 19:112740acecfa 1754 {
mbed_official 19:112740acecfa 1755 /* Low-Power transmission Slew Rate Compensation on Clock Lane */
mbed_official 19:112740acecfa 1756 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;
mbed_official 19:112740acecfa 1757 hdsi->Instance->WPCR[1] |= Value<<6;
mbed_official 19:112740acecfa 1758 }
mbed_official 19:112740acecfa 1759 else if(Lane == DSI_DATA_LANES)
mbed_official 19:112740acecfa 1760 {
mbed_official 19:112740acecfa 1761 /* Low-Power transmission Slew Rate Compensation on Data Lanes */
mbed_official 19:112740acecfa 1762 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;
mbed_official 19:112740acecfa 1763 hdsi->Instance->WPCR[1] |= Value<<8;
mbed_official 19:112740acecfa 1764 }
mbed_official 19:112740acecfa 1765 break;
mbed_official 19:112740acecfa 1766 case DSI_HS_DELAY:
mbed_official 19:112740acecfa 1767 if(Lane == DSI_CLOCK_LANE)
mbed_official 19:112740acecfa 1768 {
mbed_official 19:112740acecfa 1769 /* High-Speed Transmission Delay on Clock Lane */
mbed_official 19:112740acecfa 1770 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;
mbed_official 19:112740acecfa 1771 hdsi->Instance->WPCR[1] |= Value;
mbed_official 19:112740acecfa 1772 }
mbed_official 19:112740acecfa 1773 else if(Lane == DSI_DATA_LANES)
mbed_official 19:112740acecfa 1774 {
mbed_official 19:112740acecfa 1775 /* High-Speed Transmission Delay on Data Lanes */
mbed_official 19:112740acecfa 1776 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;
mbed_official 19:112740acecfa 1777 hdsi->Instance->WPCR[1] |= Value<<2;
mbed_official 19:112740acecfa 1778 }
mbed_official 19:112740acecfa 1779 break;
mbed_official 19:112740acecfa 1780 default:
mbed_official 19:112740acecfa 1781 break;
mbed_official 19:112740acecfa 1782 }
mbed_official 19:112740acecfa 1783
mbed_official 19:112740acecfa 1784 /* Process unlocked */
mbed_official 19:112740acecfa 1785 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1786
mbed_official 19:112740acecfa 1787 return HAL_OK;
mbed_official 19:112740acecfa 1788 }
mbed_official 19:112740acecfa 1789
mbed_official 19:112740acecfa 1790 /**
mbed_official 19:112740acecfa 1791 * @brief Low-Power Reception Filter Tuning
mbed_official 19:112740acecfa 1792 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1793 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1794 * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
mbed_official 19:112740acecfa 1795 * @retval HAL status
mbed_official 19:112740acecfa 1796 */
mbed_official 19:112740acecfa 1797 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
mbed_official 19:112740acecfa 1798 {
mbed_official 19:112740acecfa 1799 /* Process locked */
mbed_official 19:112740acecfa 1800 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1801
mbed_official 19:112740acecfa 1802 /* Low-Power RX low-pass Filtering Tuning */
mbed_official 19:112740acecfa 1803 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT;
mbed_official 19:112740acecfa 1804 hdsi->Instance->WPCR[1] |= Frequency<<25;
mbed_official 19:112740acecfa 1805
mbed_official 19:112740acecfa 1806 /* Process unlocked */
mbed_official 19:112740acecfa 1807 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1808
mbed_official 19:112740acecfa 1809 return HAL_OK;
mbed_official 19:112740acecfa 1810 }
mbed_official 19:112740acecfa 1811
mbed_official 19:112740acecfa 1812 /**
mbed_official 19:112740acecfa 1813 * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
mbed_official 19:112740acecfa 1814 * defined in the MIPI D-PHY specification
mbed_official 19:112740acecfa 1815 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1816 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1817 * @param State: ENABLE or DISABLE
mbed_official 19:112740acecfa 1818 * @retval HAL status
mbed_official 19:112740acecfa 1819 */
mbed_official 19:112740acecfa 1820 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
mbed_official 19:112740acecfa 1821 {
mbed_official 19:112740acecfa 1822 /* Process locked */
mbed_official 19:112740acecfa 1823 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1824
mbed_official 19:112740acecfa 1825 /* Check function parameters */
mbed_official 19:112740acecfa 1826 assert_param(IS_FUNCTIONAL_STATE(State));
mbed_official 19:112740acecfa 1827
mbed_official 19:112740acecfa 1828 /* Activate/Disactivate additional current path on all lanes */
mbed_official 19:112740acecfa 1829 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC;
mbed_official 19:112740acecfa 1830 hdsi->Instance->WPCR[1] |= State<<12;
mbed_official 19:112740acecfa 1831
mbed_official 19:112740acecfa 1832 /* Process unlocked */
mbed_official 19:112740acecfa 1833 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1834
mbed_official 19:112740acecfa 1835 return HAL_OK;
mbed_official 19:112740acecfa 1836 }
mbed_official 19:112740acecfa 1837
mbed_official 19:112740acecfa 1838 /**
mbed_official 19:112740acecfa 1839 * @brief Custom lane pins configuration
mbed_official 19:112740acecfa 1840 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1841 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1842 * @param CustomLane: Function to be applyed on selected lane.
mbed_official 19:112740acecfa 1843 * This parameter can be any value of @ref DSI_CustomLane
mbed_official 19:112740acecfa 1844 * @param Lane: select between clock or data lane 0 or data lane 1.
mbed_official 19:112740acecfa 1845 * This parameter can be any value of @ref DSI_Lane_Select
mbed_official 19:112740acecfa 1846 * @param State: ENABLE or DISABLE
mbed_official 19:112740acecfa 1847 * @retval HAL status
mbed_official 19:112740acecfa 1848 */
mbed_official 19:112740acecfa 1849 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
mbed_official 19:112740acecfa 1850 {
mbed_official 19:112740acecfa 1851 /* Process locked */
mbed_official 19:112740acecfa 1852 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1853
mbed_official 19:112740acecfa 1854 /* Check function parameters */
mbed_official 19:112740acecfa 1855 assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
mbed_official 19:112740acecfa 1856 assert_param(IS_DSI_LANE(Lane));
mbed_official 19:112740acecfa 1857 assert_param(IS_FUNCTIONAL_STATE(State));
mbed_official 19:112740acecfa 1858
mbed_official 19:112740acecfa 1859 switch(CustomLane)
mbed_official 19:112740acecfa 1860 {
mbed_official 19:112740acecfa 1861 case DSI_SWAP_LANE_PINS:
mbed_official 19:112740acecfa 1862 if(Lane == DSI_CLOCK_LANE)
mbed_official 19:112740acecfa 1863 {
mbed_official 19:112740acecfa 1864 /* Swap pins on clock lane */
mbed_official 19:112740acecfa 1865 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL;
mbed_official 19:112740acecfa 1866 hdsi->Instance->WPCR[0] |= (State<<6);
mbed_official 19:112740acecfa 1867 }
mbed_official 19:112740acecfa 1868 else if(Lane == DSI_DATA_LANE0)
mbed_official 19:112740acecfa 1869 {
mbed_official 19:112740acecfa 1870 /* Swap pins on data lane 0 */
mbed_official 19:112740acecfa 1871 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0;
mbed_official 19:112740acecfa 1872 hdsi->Instance->WPCR[0] |= (State<<7);
mbed_official 19:112740acecfa 1873 }
mbed_official 19:112740acecfa 1874 else if(Lane == DSI_DATA_LANE1)
mbed_official 19:112740acecfa 1875 {
mbed_official 19:112740acecfa 1876 /* Swap pins on data lane 1 */
mbed_official 19:112740acecfa 1877 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1;
mbed_official 19:112740acecfa 1878 hdsi->Instance->WPCR[0] |= (State<<8);
mbed_official 19:112740acecfa 1879 }
mbed_official 19:112740acecfa 1880 break;
mbed_official 19:112740acecfa 1881 case DSI_INVERT_HS_SIGNAL:
mbed_official 19:112740acecfa 1882 if(Lane == DSI_CLOCK_LANE)
mbed_official 19:112740acecfa 1883 {
mbed_official 19:112740acecfa 1884 /* Invert HS signal on clock lane */
mbed_official 19:112740acecfa 1885 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL;
mbed_official 19:112740acecfa 1886 hdsi->Instance->WPCR[0] |= (State<<9);
mbed_official 19:112740acecfa 1887 }
mbed_official 19:112740acecfa 1888 else if(Lane == DSI_DATA_LANE0)
mbed_official 19:112740acecfa 1889 {
mbed_official 19:112740acecfa 1890 /* Invert HS signal on data lane 0 */
mbed_official 19:112740acecfa 1891 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0;
mbed_official 19:112740acecfa 1892 hdsi->Instance->WPCR[0] |= (State<<10);
mbed_official 19:112740acecfa 1893 }
mbed_official 19:112740acecfa 1894 else if(Lane == DSI_DATA_LANE1)
mbed_official 19:112740acecfa 1895 {
mbed_official 19:112740acecfa 1896 /* Invert HS signal on data lane 1 */
mbed_official 19:112740acecfa 1897 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1;
mbed_official 19:112740acecfa 1898 hdsi->Instance->WPCR[0] |= (State<<11);
mbed_official 19:112740acecfa 1899 }
mbed_official 19:112740acecfa 1900 break;
mbed_official 19:112740acecfa 1901 default:
mbed_official 19:112740acecfa 1902 break;
mbed_official 19:112740acecfa 1903 }
mbed_official 19:112740acecfa 1904
mbed_official 19:112740acecfa 1905 /* Process unlocked */
mbed_official 19:112740acecfa 1906 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 1907
mbed_official 19:112740acecfa 1908 return HAL_OK;
mbed_official 19:112740acecfa 1909 }
mbed_official 19:112740acecfa 1910
mbed_official 19:112740acecfa 1911 /**
mbed_official 19:112740acecfa 1912 * @brief Set custom timing for the PHY
mbed_official 19:112740acecfa 1913 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 1914 * the configuration information for the DSI.
mbed_official 19:112740acecfa 1915 * @param Timing: PHY timing to be adjusted.
mbed_official 19:112740acecfa 1916 * This parameter can be any value of @ref DSI_PHY_Timing
mbed_official 19:112740acecfa 1917 * @param State: ENABLE or DISABLE
mbed_official 19:112740acecfa 1918 * @param Value: Custom value of the timing
mbed_official 19:112740acecfa 1919 * @retval HAL status
mbed_official 19:112740acecfa 1920 */
mbed_official 19:112740acecfa 1921 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
mbed_official 19:112740acecfa 1922 {
mbed_official 19:112740acecfa 1923 /* Process locked */
mbed_official 19:112740acecfa 1924 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 1925
mbed_official 19:112740acecfa 1926 /* Check function parameters */
mbed_official 19:112740acecfa 1927 assert_param(IS_DSI_PHY_TIMING(Timing));
mbed_official 19:112740acecfa 1928 assert_param(IS_FUNCTIONAL_STATE(State));
mbed_official 19:112740acecfa 1929
mbed_official 19:112740acecfa 1930 switch(Timing)
mbed_official 19:112740acecfa 1931 {
mbed_official 19:112740acecfa 1932 case DSI_TCLK_POST:
mbed_official 19:112740acecfa 1933 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 1934 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;
mbed_official 19:112740acecfa 1935 hdsi->Instance->WPCR[0] |= (State<<27);
mbed_official 19:112740acecfa 1936
mbed_official 19:112740acecfa 1937 if(State)
mbed_official 19:112740acecfa 1938 {
mbed_official 19:112740acecfa 1939 /* Set custom value */
mbed_official 19:112740acecfa 1940 hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;
mbed_official 19:112740acecfa 1941 hdsi->Instance->WPCR[4] |= Value;
mbed_official 19:112740acecfa 1942 }
mbed_official 19:112740acecfa 1943
mbed_official 19:112740acecfa 1944 break;
mbed_official 19:112740acecfa 1945 case DSI_TLPX_CLK:
mbed_official 19:112740acecfa 1946 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 1947 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;
mbed_official 19:112740acecfa 1948 hdsi->Instance->WPCR[0] |= (State<<26);
mbed_official 19:112740acecfa 1949
mbed_official 19:112740acecfa 1950 if(State)
mbed_official 19:112740acecfa 1951 {
mbed_official 19:112740acecfa 1952 /* Set custom value */
mbed_official 19:112740acecfa 1953 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC;
mbed_official 19:112740acecfa 1954 hdsi->Instance->WPCR[3] |= Value;
mbed_official 19:112740acecfa 1955 }
mbed_official 19:112740acecfa 1956
mbed_official 19:112740acecfa 1957 break;
mbed_official 19:112740acecfa 1958 case DSI_THS_EXIT:
mbed_official 19:112740acecfa 1959 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 1960 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;
mbed_official 19:112740acecfa 1961 hdsi->Instance->WPCR[0] |= (State<<25);
mbed_official 19:112740acecfa 1962
mbed_official 19:112740acecfa 1963 if(State)
mbed_official 19:112740acecfa 1964 {
mbed_official 19:112740acecfa 1965 /* Set custom value */
mbed_official 19:112740acecfa 1966 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT;
mbed_official 19:112740acecfa 1967 hdsi->Instance->WPCR[3] |= Value;
mbed_official 19:112740acecfa 1968 }
mbed_official 19:112740acecfa 1969
mbed_official 19:112740acecfa 1970 break;
mbed_official 19:112740acecfa 1971 case DSI_TLPX_DATA:
mbed_official 19:112740acecfa 1972 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 1973 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;
mbed_official 19:112740acecfa 1974 hdsi->Instance->WPCR[0] |= (State<<24);
mbed_official 19:112740acecfa 1975
mbed_official 19:112740acecfa 1976 if(State)
mbed_official 19:112740acecfa 1977 {
mbed_official 19:112740acecfa 1978 /* Set custom value */
mbed_official 19:112740acecfa 1979 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD;
mbed_official 19:112740acecfa 1980 hdsi->Instance->WPCR[3] |= Value;
mbed_official 19:112740acecfa 1981 }
mbed_official 19:112740acecfa 1982
mbed_official 19:112740acecfa 1983 break;
mbed_official 19:112740acecfa 1984 case DSI_THS_ZERO:
mbed_official 19:112740acecfa 1985 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 1986 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;
mbed_official 19:112740acecfa 1987 hdsi->Instance->WPCR[0] |= (State<<23);
mbed_official 19:112740acecfa 1988
mbed_official 19:112740acecfa 1989 if(State)
mbed_official 19:112740acecfa 1990 {
mbed_official 19:112740acecfa 1991 /* Set custom value */
mbed_official 19:112740acecfa 1992 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO;
mbed_official 19:112740acecfa 1993 hdsi->Instance->WPCR[3] |= Value;
mbed_official 19:112740acecfa 1994 }
mbed_official 19:112740acecfa 1995
mbed_official 19:112740acecfa 1996 break;
mbed_official 19:112740acecfa 1997 case DSI_THS_TRAIL:
mbed_official 19:112740acecfa 1998 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 1999 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;
mbed_official 19:112740acecfa 2000 hdsi->Instance->WPCR[0] |= (State<<22);
mbed_official 19:112740acecfa 2001
mbed_official 19:112740acecfa 2002 if(State)
mbed_official 19:112740acecfa 2003 {
mbed_official 19:112740acecfa 2004 /* Set custom value */
mbed_official 19:112740acecfa 2005 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;
mbed_official 19:112740acecfa 2006 hdsi->Instance->WPCR[2] |= Value;
mbed_official 19:112740acecfa 2007 }
mbed_official 19:112740acecfa 2008
mbed_official 19:112740acecfa 2009 break;
mbed_official 19:112740acecfa 2010 case DSI_THS_PREPARE:
mbed_official 19:112740acecfa 2011 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 2012 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;
mbed_official 19:112740acecfa 2013 hdsi->Instance->WPCR[0] |= (State<<21);
mbed_official 19:112740acecfa 2014
mbed_official 19:112740acecfa 2015 if(State)
mbed_official 19:112740acecfa 2016 {
mbed_official 19:112740acecfa 2017 /* Set custom value */
mbed_official 19:112740acecfa 2018 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP;
mbed_official 19:112740acecfa 2019 hdsi->Instance->WPCR[2] |= Value;
mbed_official 19:112740acecfa 2020 }
mbed_official 19:112740acecfa 2021
mbed_official 19:112740acecfa 2022 break;
mbed_official 19:112740acecfa 2023 case DSI_TCLK_ZERO:
mbed_official 19:112740acecfa 2024 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 2025 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;
mbed_official 19:112740acecfa 2026 hdsi->Instance->WPCR[0] |= (State<<20);
mbed_official 19:112740acecfa 2027
mbed_official 19:112740acecfa 2028 if(State)
mbed_official 19:112740acecfa 2029 {
mbed_official 19:112740acecfa 2030 /* Set custom value */
mbed_official 19:112740acecfa 2031 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;
mbed_official 19:112740acecfa 2032 hdsi->Instance->WPCR[2] |= Value;
mbed_official 19:112740acecfa 2033 }
mbed_official 19:112740acecfa 2034
mbed_official 19:112740acecfa 2035 break;
mbed_official 19:112740acecfa 2036 case DSI_TCLK_PREPARE:
mbed_official 19:112740acecfa 2037 /* Enable/Disable custom timing setting */
mbed_official 19:112740acecfa 2038 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;
mbed_official 19:112740acecfa 2039 hdsi->Instance->WPCR[0] |= (State<<19);
mbed_official 19:112740acecfa 2040
mbed_official 19:112740acecfa 2041 if(State)
mbed_official 19:112740acecfa 2042 {
mbed_official 19:112740acecfa 2043 /* Set custom value */
mbed_official 19:112740acecfa 2044 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;
mbed_official 19:112740acecfa 2045 hdsi->Instance->WPCR[2] |= Value;
mbed_official 19:112740acecfa 2046 }
mbed_official 19:112740acecfa 2047
mbed_official 19:112740acecfa 2048 break;
mbed_official 19:112740acecfa 2049 default:
mbed_official 19:112740acecfa 2050 break;
mbed_official 19:112740acecfa 2051 }
mbed_official 19:112740acecfa 2052
mbed_official 19:112740acecfa 2053 /* Process unlocked */
mbed_official 19:112740acecfa 2054 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 2055
mbed_official 19:112740acecfa 2056 return HAL_OK;
mbed_official 19:112740acecfa 2057 }
mbed_official 19:112740acecfa 2058
mbed_official 19:112740acecfa 2059 /**
mbed_official 19:112740acecfa 2060 * @brief Force the Clock/Data Lane in TX Stop Mode
mbed_official 19:112740acecfa 2061 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 2062 * the configuration information for the DSI.
mbed_official 19:112740acecfa 2063 * @param Lane: select between clock or data lanes.
mbed_official 19:112740acecfa 2064 * This parameter can be any value of @ref DSI_Lane_Group
mbed_official 19:112740acecfa 2065 * @param State: ENABLE or DISABLE
mbed_official 19:112740acecfa 2066 * @retval HAL status
mbed_official 19:112740acecfa 2067 */
mbed_official 19:112740acecfa 2068 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
mbed_official 19:112740acecfa 2069 {
mbed_official 19:112740acecfa 2070 /* Process locked */
mbed_official 19:112740acecfa 2071 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 2072
mbed_official 19:112740acecfa 2073 /* Check function parameters */
mbed_official 19:112740acecfa 2074 assert_param(IS_DSI_LANE_GROUP(Lane));
mbed_official 19:112740acecfa 2075 assert_param(IS_FUNCTIONAL_STATE(State));
mbed_official 19:112740acecfa 2076
mbed_official 19:112740acecfa 2077 if(Lane == DSI_CLOCK_LANE)
mbed_official 19:112740acecfa 2078 {
mbed_official 19:112740acecfa 2079 /* Force/Unforce the Clock Lane in TX Stop Mode */
mbed_official 19:112740acecfa 2080 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;
mbed_official 19:112740acecfa 2081 hdsi->Instance->WPCR[0] |= (State<<12);
mbed_official 19:112740acecfa 2082 }
mbed_official 19:112740acecfa 2083 else if(Lane == DSI_DATA_LANES)
mbed_official 19:112740acecfa 2084 {
mbed_official 19:112740acecfa 2085 /* Force/Unforce the Data Lanes in TX Stop Mode */
mbed_official 19:112740acecfa 2086 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;
mbed_official 19:112740acecfa 2087 hdsi->Instance->WPCR[0] |= (State<<13);
mbed_official 19:112740acecfa 2088 }
mbed_official 19:112740acecfa 2089
mbed_official 19:112740acecfa 2090 /* Process unlocked */
mbed_official 19:112740acecfa 2091 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 2092
mbed_official 19:112740acecfa 2093 return HAL_OK;
mbed_official 19:112740acecfa 2094 }
mbed_official 19:112740acecfa 2095
mbed_official 19:112740acecfa 2096 /**
mbed_official 19:112740acecfa 2097 * @brief Forces LP Receiver in Low-Power Mode
mbed_official 19:112740acecfa 2098 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 2099 * the configuration information for the DSI.
mbed_official 19:112740acecfa 2100 * @param State: ENABLE or DISABLE
mbed_official 19:112740acecfa 2101 * @retval HAL status
mbed_official 19:112740acecfa 2102 */
mbed_official 19:112740acecfa 2103 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
mbed_official 19:112740acecfa 2104 {
mbed_official 19:112740acecfa 2105 /* Process locked */
mbed_official 19:112740acecfa 2106 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 2107
mbed_official 19:112740acecfa 2108 /* Check function parameters */
mbed_official 19:112740acecfa 2109 assert_param(IS_FUNCTIONAL_STATE(State));
mbed_official 19:112740acecfa 2110
mbed_official 19:112740acecfa 2111 /* Force/Unforce LP Receiver in Low-Power Mode */
mbed_official 19:112740acecfa 2112 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;
mbed_official 19:112740acecfa 2113 hdsi->Instance->WPCR[1] |= State<<22;
mbed_official 19:112740acecfa 2114
mbed_official 19:112740acecfa 2115 /* Process unlocked */
mbed_official 19:112740acecfa 2116 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 2117
mbed_official 19:112740acecfa 2118 return HAL_OK;
mbed_official 19:112740acecfa 2119 }
mbed_official 19:112740acecfa 2120
mbed_official 19:112740acecfa 2121 /**
mbed_official 19:112740acecfa 2122 * @brief Force Data Lanes in RX Mode after a BTA
mbed_official 19:112740acecfa 2123 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 2124 * the configuration information for the DSI.
mbed_official 19:112740acecfa 2125 * @param State: ENABLE or DISABLE
mbed_official 19:112740acecfa 2126 * @retval HAL status
mbed_official 19:112740acecfa 2127 */
mbed_official 19:112740acecfa 2128 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
mbed_official 19:112740acecfa 2129 {
mbed_official 19:112740acecfa 2130 /* Process locked */
mbed_official 19:112740acecfa 2131 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 2132
mbed_official 19:112740acecfa 2133 /* Check function parameters */
mbed_official 19:112740acecfa 2134 assert_param(IS_FUNCTIONAL_STATE(State));
mbed_official 19:112740acecfa 2135
mbed_official 19:112740acecfa 2136 /* Force Data Lanes in RX Mode */
mbed_official 19:112740acecfa 2137 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL;
mbed_official 19:112740acecfa 2138 hdsi->Instance->WPCR[0] |= State<<16;
mbed_official 19:112740acecfa 2139
mbed_official 19:112740acecfa 2140 /* Process unlocked */
mbed_official 19:112740acecfa 2141 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 2142
mbed_official 19:112740acecfa 2143 return HAL_OK;
mbed_official 19:112740acecfa 2144 }
mbed_official 19:112740acecfa 2145
mbed_official 19:112740acecfa 2146 /**
mbed_official 19:112740acecfa 2147 * @brief Enable a pull-down on the lanes to prevent from floating states when unused
mbed_official 19:112740acecfa 2148 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 2149 * the configuration information for the DSI.
mbed_official 19:112740acecfa 2150 * @param State: ENABLE or DISABLE
mbed_official 19:112740acecfa 2151 * @retval HAL status
mbed_official 19:112740acecfa 2152 */
mbed_official 19:112740acecfa 2153 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
mbed_official 19:112740acecfa 2154 {
mbed_official 19:112740acecfa 2155 /* Process locked */
mbed_official 19:112740acecfa 2156 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 2157
mbed_official 19:112740acecfa 2158 /* Check function parameters */
mbed_official 19:112740acecfa 2159 assert_param(IS_FUNCTIONAL_STATE(State));
mbed_official 19:112740acecfa 2160
mbed_official 19:112740acecfa 2161 /* Enable/Disable pull-down on lanes */
mbed_official 19:112740acecfa 2162 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN;
mbed_official 19:112740acecfa 2163 hdsi->Instance->WPCR[0] |= State<<18;
mbed_official 19:112740acecfa 2164
mbed_official 19:112740acecfa 2165 /* Process unlocked */
mbed_official 19:112740acecfa 2166 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 2167
mbed_official 19:112740acecfa 2168 return HAL_OK;
mbed_official 19:112740acecfa 2169 }
mbed_official 19:112740acecfa 2170
mbed_official 19:112740acecfa 2171 /**
mbed_official 19:112740acecfa 2172 * @brief Switch off the contention detection on data lanes
mbed_official 19:112740acecfa 2173 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 2174 * the configuration information for the DSI.
mbed_official 19:112740acecfa 2175 * @param State: ENABLE or DISABLE
mbed_official 19:112740acecfa 2176 * @retval HAL status
mbed_official 19:112740acecfa 2177 */
mbed_official 19:112740acecfa 2178 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
mbed_official 19:112740acecfa 2179 {
mbed_official 19:112740acecfa 2180 /* Process locked */
mbed_official 19:112740acecfa 2181 __HAL_LOCK(hdsi);
mbed_official 19:112740acecfa 2182
mbed_official 19:112740acecfa 2183 /* Check function parameters */
mbed_official 19:112740acecfa 2184 assert_param(IS_FUNCTIONAL_STATE(State));
mbed_official 19:112740acecfa 2185
mbed_official 19:112740acecfa 2186 /* Contention Detection on Data Lanes OFF */
mbed_official 19:112740acecfa 2187 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;
mbed_official 19:112740acecfa 2188 hdsi->Instance->WPCR[0] |= State<<14;
mbed_official 19:112740acecfa 2189
mbed_official 19:112740acecfa 2190 /* Process unlocked */
mbed_official 19:112740acecfa 2191 __HAL_UNLOCK(hdsi);
mbed_official 19:112740acecfa 2192
mbed_official 19:112740acecfa 2193 return HAL_OK;
mbed_official 19:112740acecfa 2194 }
mbed_official 19:112740acecfa 2195
mbed_official 19:112740acecfa 2196 /**
mbed_official 19:112740acecfa 2197 * @}
mbed_official 19:112740acecfa 2198 */
mbed_official 19:112740acecfa 2199
mbed_official 19:112740acecfa 2200 /** @defgroup DSI_Group4 Peripheral State and Errors functions
mbed_official 19:112740acecfa 2201 * @brief Peripheral State and Errors functions
mbed_official 19:112740acecfa 2202 *
mbed_official 19:112740acecfa 2203 @verbatim
mbed_official 19:112740acecfa 2204 ===============================================================================
mbed_official 19:112740acecfa 2205 ##### Peripheral State and Errors functions #####
mbed_official 19:112740acecfa 2206 ===============================================================================
mbed_official 19:112740acecfa 2207 [..]
mbed_official 19:112740acecfa 2208 This subsection provides functions allowing to
mbed_official 19:112740acecfa 2209 (+) Check the DSI state.
mbed_official 19:112740acecfa 2210 (+) Get error code.
mbed_official 19:112740acecfa 2211
mbed_official 19:112740acecfa 2212 @endverbatim
mbed_official 19:112740acecfa 2213 * @{
mbed_official 19:112740acecfa 2214 */
mbed_official 19:112740acecfa 2215
mbed_official 19:112740acecfa 2216 /**
mbed_official 19:112740acecfa 2217 * @brief Return the DSI state
mbed_official 19:112740acecfa 2218 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 2219 * the configuration information for the DSI.
mbed_official 19:112740acecfa 2220 * @retval HAL state
mbed_official 19:112740acecfa 2221 */
mbed_official 19:112740acecfa 2222 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
mbed_official 19:112740acecfa 2223 {
mbed_official 19:112740acecfa 2224 return hdsi->State;
mbed_official 19:112740acecfa 2225 }
mbed_official 19:112740acecfa 2226
mbed_official 19:112740acecfa 2227 /**
mbed_official 19:112740acecfa 2228 * @}
mbed_official 19:112740acecfa 2229 */
mbed_official 19:112740acecfa 2230
mbed_official 19:112740acecfa 2231 /**
mbed_official 19:112740acecfa 2232 * @}
mbed_official 19:112740acecfa 2233 */
mbed_official 19:112740acecfa 2234 #endif /* STM32F469xx || STM32F479xx */
mbed_official 19:112740acecfa 2235 #endif /* HAL_DSI_MODULE_ENABLED */
mbed_official 19:112740acecfa 2236 /**
mbed_official 19:112740acecfa 2237 * @}
mbed_official 19:112740acecfa 2238 */
mbed_official 19:112740acecfa 2239
mbed_official 19:112740acecfa 2240 /**
mbed_official 19:112740acecfa 2241 * @}
mbed_official 19:112740acecfa 2242 */
mbed_official 19:112740acecfa 2243
mbed_official 19:112740acecfa 2244 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/