mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

Dependents: IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h@19:112740acecfa, 2015-11-10 (annotated)

Committer:: mbed_official
Date:: Tue Nov 10 09:30:11 2015 +0000
Revision:: 19:112740acecfa
Parent:: 0:9b334a45a8ff

Synchronized with git revision 7218418919aeaf775fb8d386ea7ee0dfc0c80ff9

Full URL: https://github.com/mbedmicro/mbed/commit/7218418919aeaf775fb8d386ea7ee0dfc0c80ff9/

DISCO_F469NI - add disco F469NI support

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32_hal_legacy.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
bogdanm	0:9b334a45a8ff	8	* macros and functions maintained for legacy purpose.
bogdanm	0:9b334a45a8ff	9	******************************************************************************
bogdanm	0:9b334a45a8ff	10	* @attention
bogdanm	0:9b334a45a8ff	11	*
bogdanm	0:9b334a45a8ff	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	15	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	17	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	20	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	22	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	23	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	24	*
bogdanm	0:9b334a45a8ff	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	35	*
bogdanm	0:9b334a45a8ff	36	******************************************************************************
bogdanm	0:9b334a45a8ff	37	*/
bogdanm	0:9b334a45a8ff	38
bogdanm	0:9b334a45a8ff	39	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	40	#ifndef __STM32_HAL_LEGACY
bogdanm	0:9b334a45a8ff	41	#define __STM32_HAL_LEGACY
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	44	extern "C" {
bogdanm	0:9b334a45a8ff	45	#endif
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	48	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	49	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	52	* @{
bogdanm	0:9b334a45a8ff	53	*/
bogdanm	0:9b334a45a8ff	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
bogdanm	0:9b334a45a8ff	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
bogdanm	0:9b334a45a8ff	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
bogdanm	0:9b334a45a8ff	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
bogdanm	0:9b334a45a8ff	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	/**
bogdanm	0:9b334a45a8ff	61	* @}
bogdanm	0:9b334a45a8ff	62	*/
bogdanm	0:9b334a45a8ff	63
bogdanm	0:9b334a45a8ff	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	65	* @{
bogdanm	0:9b334a45a8ff	66	*/
bogdanm	0:9b334a45a8ff	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
bogdanm	0:9b334a45a8ff	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
bogdanm	0:9b334a45a8ff	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
bogdanm	0:9b334a45a8ff	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
bogdanm	0:9b334a45a8ff	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
bogdanm	0:9b334a45a8ff	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
bogdanm	0:9b334a45a8ff	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
bogdanm	0:9b334a45a8ff	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
bogdanm	0:9b334a45a8ff	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
bogdanm	0:9b334a45a8ff	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
bogdanm	0:9b334a45a8ff	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
bogdanm	0:9b334a45a8ff	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
bogdanm	0:9b334a45a8ff	79	#define AWD_EVENT ADC_AWD_EVENT
bogdanm	0:9b334a45a8ff	80	#define AWD1_EVENT ADC_AWD1_EVENT
bogdanm	0:9b334a45a8ff	81	#define AWD2_EVENT ADC_AWD2_EVENT
bogdanm	0:9b334a45a8ff	82	#define AWD3_EVENT ADC_AWD3_EVENT
bogdanm	0:9b334a45a8ff	83	#define OVR_EVENT ADC_OVR_EVENT
bogdanm	0:9b334a45a8ff	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
bogdanm	0:9b334a45a8ff	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
bogdanm	0:9b334a45a8ff	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
bogdanm	0:9b334a45a8ff	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
bogdanm	0:9b334a45a8ff	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
bogdanm	0:9b334a45a8ff	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
mbed_official	19:112740acecfa	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
mbed_official	19:112740acecfa	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
mbed_official	19:112740acecfa	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
mbed_official	19:112740acecfa	93	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
mbed_official	19:112740acecfa	94	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
bogdanm	0:9b334a45a8ff	95	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
bogdanm	0:9b334a45a8ff	96	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
bogdanm	0:9b334a45a8ff	97	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
bogdanm	0:9b334a45a8ff	98	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
bogdanm	0:9b334a45a8ff	99	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
bogdanm	0:9b334a45a8ff	100	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
bogdanm	0:9b334a45a8ff	101	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
bogdanm	0:9b334a45a8ff	102	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
bogdanm	0:9b334a45a8ff	103	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
bogdanm	0:9b334a45a8ff	104	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
bogdanm	0:9b334a45a8ff	105	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
bogdanm	0:9b334a45a8ff	106	/**
bogdanm	0:9b334a45a8ff	107	* @}
bogdanm	0:9b334a45a8ff	108	*/
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	111	* @{
bogdanm	0:9b334a45a8ff	112	*/
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	/**
bogdanm	0:9b334a45a8ff	117	* @}
bogdanm	0:9b334a45a8ff	118	*/
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	121	* @{
bogdanm	0:9b334a45a8ff	122	*/
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
bogdanm	0:9b334a45a8ff	125	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
bogdanm	0:9b334a45a8ff	126	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
bogdanm	0:9b334a45a8ff	127	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	/**
bogdanm	0:9b334a45a8ff	130	* @}
bogdanm	0:9b334a45a8ff	131	*/
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	134	* @{
bogdanm	0:9b334a45a8ff	135	*/
bogdanm	0:9b334a45a8ff	136
bogdanm	0:9b334a45a8ff	137	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
bogdanm	0:9b334a45a8ff	138	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	/**
bogdanm	0:9b334a45a8ff	141	* @}
bogdanm	0:9b334a45a8ff	142	*/
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	145	* @{
bogdanm	0:9b334a45a8ff	146	*/
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
bogdanm	0:9b334a45a8ff	149	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
bogdanm	0:9b334a45a8ff	150	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
bogdanm	0:9b334a45a8ff	151	#define DAC_WAVE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	152	#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
bogdanm	0:9b334a45a8ff	153	#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
bogdanm	0:9b334a45a8ff	154	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
bogdanm	0:9b334a45a8ff	155	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
bogdanm	0:9b334a45a8ff	156	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	/**
bogdanm	0:9b334a45a8ff	159	* @}
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	163	* @{
bogdanm	0:9b334a45a8ff	164	*/
bogdanm	0:9b334a45a8ff	165	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
bogdanm	0:9b334a45a8ff	166	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
bogdanm	0:9b334a45a8ff	167	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
bogdanm	0:9b334a45a8ff	168	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
bogdanm	0:9b334a45a8ff	169	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
bogdanm	0:9b334a45a8ff	170	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
bogdanm	0:9b334a45a8ff	171	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
bogdanm	0:9b334a45a8ff	172	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
bogdanm	0:9b334a45a8ff	173	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
bogdanm	0:9b334a45a8ff	174	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
bogdanm	0:9b334a45a8ff	175	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
bogdanm	0:9b334a45a8ff	176	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
bogdanm	0:9b334a45a8ff	177	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
bogdanm	0:9b334a45a8ff	178	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
bogdanm	0:9b334a45a8ff	179	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	#define IS_HAL_REMAPDMA IS_DMA_REMAP
bogdanm	0:9b334a45a8ff	182	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
bogdanm	0:9b334a45a8ff	183	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186
bogdanm	0:9b334a45a8ff	187	/**
bogdanm	0:9b334a45a8ff	188	* @}
bogdanm	0:9b334a45a8ff	189	*/
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	192	* @{
bogdanm	0:9b334a45a8ff	193	*/
bogdanm	0:9b334a45a8ff	194
bogdanm	0:9b334a45a8ff	195	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
bogdanm	0:9b334a45a8ff	196	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
bogdanm	0:9b334a45a8ff	197	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
bogdanm	0:9b334a45a8ff	198	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
bogdanm	0:9b334a45a8ff	199	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
bogdanm	0:9b334a45a8ff	200	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
bogdanm	0:9b334a45a8ff	201	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
bogdanm	0:9b334a45a8ff	202	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
bogdanm	0:9b334a45a8ff	203	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
bogdanm	0:9b334a45a8ff	204	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
bogdanm	0:9b334a45a8ff	205	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	206	#define OBEX_PCROP OPTIONBYTE_PCROP
bogdanm	0:9b334a45a8ff	207	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
bogdanm	0:9b334a45a8ff	208	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
bogdanm	0:9b334a45a8ff	209	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
bogdanm	0:9b334a45a8ff	210	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
bogdanm	0:9b334a45a8ff	211	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
bogdanm	0:9b334a45a8ff	212	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
bogdanm	0:9b334a45a8ff	213	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
bogdanm	0:9b334a45a8ff	214	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
bogdanm	0:9b334a45a8ff	215	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
bogdanm	0:9b334a45a8ff	216	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
bogdanm	0:9b334a45a8ff	217	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
bogdanm	0:9b334a45a8ff	218	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
bogdanm	0:9b334a45a8ff	219	#define PAGESIZE FLASH_PAGE_SIZE
bogdanm	0:9b334a45a8ff	220	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
bogdanm	0:9b334a45a8ff	221	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
bogdanm	0:9b334a45a8ff	222	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
bogdanm	0:9b334a45a8ff	223	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
bogdanm	0:9b334a45a8ff	224	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
bogdanm	0:9b334a45a8ff	225	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
bogdanm	0:9b334a45a8ff	226	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
bogdanm	0:9b334a45a8ff	227	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
bogdanm	0:9b334a45a8ff	228	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
bogdanm	0:9b334a45a8ff	229	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
bogdanm	0:9b334a45a8ff	230	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
bogdanm	0:9b334a45a8ff	231	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
bogdanm	0:9b334a45a8ff	232	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
bogdanm	0:9b334a45a8ff	233	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
bogdanm	0:9b334a45a8ff	234	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
bogdanm	0:9b334a45a8ff	235	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
bogdanm	0:9b334a45a8ff	236	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
bogdanm	0:9b334a45a8ff	237	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
bogdanm	0:9b334a45a8ff	238	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
bogdanm	0:9b334a45a8ff	239	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
bogdanm	0:9b334a45a8ff	240	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
bogdanm	0:9b334a45a8ff	241	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
bogdanm	0:9b334a45a8ff	242	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
bogdanm	0:9b334a45a8ff	243	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
bogdanm	0:9b334a45a8ff	244	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
bogdanm	0:9b334a45a8ff	245	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
bogdanm	0:9b334a45a8ff	246	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
bogdanm	0:9b334a45a8ff	247	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
bogdanm	0:9b334a45a8ff	248	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
bogdanm	0:9b334a45a8ff	249	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
bogdanm	0:9b334a45a8ff	250	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
bogdanm	0:9b334a45a8ff	251	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
bogdanm	0:9b334a45a8ff	252	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
bogdanm	0:9b334a45a8ff	253	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
bogdanm	0:9b334a45a8ff	254	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
bogdanm	0:9b334a45a8ff	255	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
bogdanm	0:9b334a45a8ff	256	#define OB_WDG_SW OB_IWDG_SW
bogdanm	0:9b334a45a8ff	257	#define OB_WDG_HW OB_IWDG_HW
mbed_official	19:112740acecfa	258	#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
mbed_official	19:112740acecfa	259	#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
mbed_official	19:112740acecfa	260	#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
mbed_official	19:112740acecfa	261	#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
mbed_official	19:112740acecfa	262	#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
mbed_official	19:112740acecfa	263	#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
mbed_official	19:112740acecfa	264	#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
mbed_official	19:112740acecfa	265	#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
bogdanm	0:9b334a45a8ff	266	/**
bogdanm	0:9b334a45a8ff	267	* @}
bogdanm	0:9b334a45a8ff	268	*/
bogdanm	0:9b334a45a8ff	269
bogdanm	0:9b334a45a8ff	270	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	271	* @{
bogdanm	0:9b334a45a8ff	272	*/
bogdanm	0:9b334a45a8ff	273
mbed_official	19:112740acecfa	274	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
mbed_official	19:112740acecfa	275	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
mbed_official	19:112740acecfa	276	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
mbed_official	19:112740acecfa	277	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
mbed_official	19:112740acecfa	278	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
mbed_official	19:112740acecfa	279	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
mbed_official	19:112740acecfa	280	#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
mbed_official	19:112740acecfa	281	#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
mbed_official	19:112740acecfa	282	#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
bogdanm	0:9b334a45a8ff	283	/**
bogdanm	0:9b334a45a8ff	284	* @}
bogdanm	0:9b334a45a8ff	285	*/
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
bogdanm	0:9b334a45a8ff	289	* @{
bogdanm	0:9b334a45a8ff	290	*/
bogdanm	0:9b334a45a8ff	291	#if defined(STM32L4) \|\| defined(STM32F7)
bogdanm	0:9b334a45a8ff	292	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
bogdanm	0:9b334a45a8ff	293	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
bogdanm	0:9b334a45a8ff	294	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
bogdanm	0:9b334a45a8ff	295	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
bogdanm	0:9b334a45a8ff	296	#else
bogdanm	0:9b334a45a8ff	297	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
bogdanm	0:9b334a45a8ff	298	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
bogdanm	0:9b334a45a8ff	299	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
bogdanm	0:9b334a45a8ff	300	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
bogdanm	0:9b334a45a8ff	301	#endif
bogdanm	0:9b334a45a8ff	302	/**
bogdanm	0:9b334a45a8ff	303	* @}
bogdanm	0:9b334a45a8ff	304	*/
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	307	* @{
bogdanm	0:9b334a45a8ff	308	*/
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
bogdanm	0:9b334a45a8ff	311	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm	0:9b334a45a8ff	312	/**
bogdanm	0:9b334a45a8ff	313	* @}
bogdanm	0:9b334a45a8ff	314	*/
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	317	* @{
bogdanm	0:9b334a45a8ff	318	*/
bogdanm	0:9b334a45a8ff	319	#define GET_GPIO_SOURCE GPIO_GET_INDEX
bogdanm	0:9b334a45a8ff	320	#define GET_GPIO_INDEX GPIO_GET_INDEX
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	#if defined(STM32F4)
bogdanm	0:9b334a45a8ff	323	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
bogdanm	0:9b334a45a8ff	324	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
bogdanm	0:9b334a45a8ff	325	#endif
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	#if defined(STM32F7)
bogdanm	0:9b334a45a8ff	328	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
bogdanm	0:9b334a45a8ff	329	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
bogdanm	0:9b334a45a8ff	330	#endif
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	#if defined(STM32L4)
bogdanm	0:9b334a45a8ff	333	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
bogdanm	0:9b334a45a8ff	334	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
bogdanm	0:9b334a45a8ff	335	#endif
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
bogdanm	0:9b334a45a8ff	338	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
bogdanm	0:9b334a45a8ff	339	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
bogdanm	0:9b334a45a8ff	340
mbed_official	19:112740acecfa	341	#if defined(STM32L0) \|\| defined(STM32F4)
mbed_official	19:112740acecfa	342	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
mbed_official	19:112740acecfa	343	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
mbed_official	19:112740acecfa	344	#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
mbed_official	19:112740acecfa	345	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
mbed_official	19:112740acecfa	346	#endif /* STM32L0 \|\| STM32F4 */
mbed_official	19:112740acecfa	347
bogdanm	0:9b334a45a8ff	348	/**
bogdanm	0:9b334a45a8ff	349	* @}
bogdanm	0:9b334a45a8ff	350	*/
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	353	* @{
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
bogdanm	0:9b334a45a8ff	356	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
bogdanm	0:9b334a45a8ff	357	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
bogdanm	0:9b334a45a8ff	358	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
bogdanm	0:9b334a45a8ff	359	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
bogdanm	0:9b334a45a8ff	360	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
bogdanm	0:9b334a45a8ff	361	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
bogdanm	0:9b334a45a8ff	362	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
bogdanm	0:9b334a45a8ff	363	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
bogdanm	0:9b334a45a8ff	364	/**
bogdanm	0:9b334a45a8ff	365	* @}
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	369	* @{
bogdanm	0:9b334a45a8ff	370	*/
bogdanm	0:9b334a45a8ff	371	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
bogdanm	0:9b334a45a8ff	372	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
bogdanm	0:9b334a45a8ff	373	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
bogdanm	0:9b334a45a8ff	374	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
bogdanm	0:9b334a45a8ff	375	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
bogdanm	0:9b334a45a8ff	376	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
bogdanm	0:9b334a45a8ff	377	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
bogdanm	0:9b334a45a8ff	378	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
bogdanm	0:9b334a45a8ff	379	/**
bogdanm	0:9b334a45a8ff	380	* @}
bogdanm	0:9b334a45a8ff	381	*/
bogdanm	0:9b334a45a8ff	382
bogdanm	0:9b334a45a8ff	383	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	384	* @{
bogdanm	0:9b334a45a8ff	385	*/
bogdanm	0:9b334a45a8ff	386	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	387	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	/**
bogdanm	0:9b334a45a8ff	390	* @}
bogdanm	0:9b334a45a8ff	391	*/
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	394	* @{
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
bogdanm	0:9b334a45a8ff	397	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
bogdanm	0:9b334a45a8ff	398	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
bogdanm	0:9b334a45a8ff	399	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
bogdanm	0:9b334a45a8ff	400	/**
bogdanm	0:9b334a45a8ff	401	* @}
bogdanm	0:9b334a45a8ff	402	*/
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	405	* @{
bogdanm	0:9b334a45a8ff	406	*/
bogdanm	0:9b334a45a8ff	407
bogdanm	0:9b334a45a8ff	408	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
bogdanm	0:9b334a45a8ff	409	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
bogdanm	0:9b334a45a8ff	410	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
bogdanm	0:9b334a45a8ff	411	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
bogdanm	0:9b334a45a8ff	414	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
bogdanm	0:9b334a45a8ff	415	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
bogdanm	0:9b334a45a8ff	416
bogdanm	0:9b334a45a8ff	417	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
bogdanm	0:9b334a45a8ff	418	#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
bogdanm	0:9b334a45a8ff	419	#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
bogdanm	0:9b334a45a8ff	420	#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
bogdanm	0:9b334a45a8ff	421
bogdanm	0:9b334a45a8ff	422	/* The following 3 definition have also been present in a temporary version of lptim.h */
bogdanm	0:9b334a45a8ff	423	/* They need to be renamed also to the right name, just in case */
bogdanm	0:9b334a45a8ff	424	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
bogdanm	0:9b334a45a8ff	425	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
bogdanm	0:9b334a45a8ff	426	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	/**
bogdanm	0:9b334a45a8ff	429	* @}
bogdanm	0:9b334a45a8ff	430	*/
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	433	* @{
bogdanm	0:9b334a45a8ff	434	*/
bogdanm	0:9b334a45a8ff	435	#define NAND_AddressTypedef NAND_AddressTypeDef
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	#define __ARRAY_ADDRESS ARRAY_ADDRESS
bogdanm	0:9b334a45a8ff	438	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
bogdanm	0:9b334a45a8ff	439	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
bogdanm	0:9b334a45a8ff	440	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
bogdanm	0:9b334a45a8ff	441	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
bogdanm	0:9b334a45a8ff	442	/**
bogdanm	0:9b334a45a8ff	443	* @}
bogdanm	0:9b334a45a8ff	444	*/
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	447	* @{
bogdanm	0:9b334a45a8ff	448	*/
bogdanm	0:9b334a45a8ff	449	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
bogdanm	0:9b334a45a8ff	450	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
bogdanm	0:9b334a45a8ff	451	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
bogdanm	0:9b334a45a8ff	452	#define NOR_ERROR HAL_NOR_STATUS_ERROR
bogdanm	0:9b334a45a8ff	453	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
bogdanm	0:9b334a45a8ff	454
bogdanm	0:9b334a45a8ff	455	#define __NOR_WRITE NOR_WRITE
bogdanm	0:9b334a45a8ff	456	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
bogdanm	0:9b334a45a8ff	457	/**
bogdanm	0:9b334a45a8ff	458	* @}
bogdanm	0:9b334a45a8ff	459	*/
bogdanm	0:9b334a45a8ff	460
bogdanm	0:9b334a45a8ff	461	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	462	* @{
bogdanm	0:9b334a45a8ff	463	*/
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	466	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	467	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
bogdanm	0:9b334a45a8ff	468	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	471	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	472	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
bogdanm	0:9b334a45a8ff	473	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	476	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	479	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	480
bogdanm	0:9b334a45a8ff	481	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	482	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
bogdanm	0:9b334a45a8ff	487	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	488	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	/**
bogdanm	0:9b334a45a8ff	491	* @}
bogdanm	0:9b334a45a8ff	492	*/
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	495	* @{
bogdanm	0:9b334a45a8ff	496	*/
bogdanm	0:9b334a45a8ff	497	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
bogdanm	0:9b334a45a8ff	498	/**
bogdanm	0:9b334a45a8ff	499	* @}
bogdanm	0:9b334a45a8ff	500	*/
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	503	* @{
bogdanm	0:9b334a45a8ff	504	*/
bogdanm	0:9b334a45a8ff	505
bogdanm	0:9b334a45a8ff	506	/* Compact Flash-ATA registers description */
bogdanm	0:9b334a45a8ff	507	#define CF_DATA ATA_DATA
bogdanm	0:9b334a45a8ff	508	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
bogdanm	0:9b334a45a8ff	509	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
bogdanm	0:9b334a45a8ff	510	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
bogdanm	0:9b334a45a8ff	511	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
bogdanm	0:9b334a45a8ff	512	#define CF_CARD_HEAD ATA_CARD_HEAD
bogdanm	0:9b334a45a8ff	513	#define CF_STATUS_CMD ATA_STATUS_CMD
bogdanm	0:9b334a45a8ff	514	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
bogdanm	0:9b334a45a8ff	515	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/* Compact Flash-ATA commands */
bogdanm	0:9b334a45a8ff	518	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
bogdanm	0:9b334a45a8ff	519	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
bogdanm	0:9b334a45a8ff	520	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
bogdanm	0:9b334a45a8ff	521	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
bogdanm	0:9b334a45a8ff	524	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
bogdanm	0:9b334a45a8ff	525	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
bogdanm	0:9b334a45a8ff	526	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
bogdanm	0:9b334a45a8ff	527	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
bogdanm	0:9b334a45a8ff	528	/**
bogdanm	0:9b334a45a8ff	529	* @}
bogdanm	0:9b334a45a8ff	530	*/
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	533	* @{
bogdanm	0:9b334a45a8ff	534	*/
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	#define FORMAT_BIN RTC_FORMAT_BIN
bogdanm	0:9b334a45a8ff	537	#define FORMAT_BCD RTC_FORMAT_BCD
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
bogdanm	0:9b334a45a8ff	540	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
bogdanm	0:9b334a45a8ff	541	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
bogdanm	0:9b334a45a8ff	542	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	543	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	546	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
bogdanm	0:9b334a45a8ff	547	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
bogdanm	0:9b334a45a8ff	548	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
bogdanm	0:9b334a45a8ff	549	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	550	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
bogdanm	0:9b334a45a8ff	551	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
bogdanm	0:9b334a45a8ff	552	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
bogdanm	0:9b334a45a8ff	555	#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
bogdanm	0:9b334a45a8ff	556	#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
bogdanm	0:9b334a45a8ff	557	#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
bogdanm	0:9b334a45a8ff	560	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
bogdanm	0:9b334a45a8ff	561	#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
bogdanm	0:9b334a45a8ff	564	#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
bogdanm	0:9b334a45a8ff	565	#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/**
bogdanm	0:9b334a45a8ff	568	* @}
bogdanm	0:9b334a45a8ff	569	*/
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	573	* @{
bogdanm	0:9b334a45a8ff	574	*/
bogdanm	0:9b334a45a8ff	575	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
bogdanm	0:9b334a45a8ff	576	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	579	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	580	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	581	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
bogdanm	0:9b334a45a8ff	584	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
bogdanm	0:9b334a45a8ff	585
bogdanm	0:9b334a45a8ff	586	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
bogdanm	0:9b334a45a8ff	587	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
bogdanm	0:9b334a45a8ff	588	/**
bogdanm	0:9b334a45a8ff	589	* @}
bogdanm	0:9b334a45a8ff	590	*/
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592
bogdanm	0:9b334a45a8ff	593	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	594	* @{
bogdanm	0:9b334a45a8ff	595	*/
bogdanm	0:9b334a45a8ff	596	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
bogdanm	0:9b334a45a8ff	597	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
bogdanm	0:9b334a45a8ff	598	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
bogdanm	0:9b334a45a8ff	599	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
bogdanm	0:9b334a45a8ff	600	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
bogdanm	0:9b334a45a8ff	601	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
bogdanm	0:9b334a45a8ff	602	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
bogdanm	0:9b334a45a8ff	603	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
bogdanm	0:9b334a45a8ff	604	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
bogdanm	0:9b334a45a8ff	605	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
bogdanm	0:9b334a45a8ff	606	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
bogdanm	0:9b334a45a8ff	607	/**
bogdanm	0:9b334a45a8ff	608	* @}
bogdanm	0:9b334a45a8ff	609	*/
bogdanm	0:9b334a45a8ff	610
bogdanm	0:9b334a45a8ff	611	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	612	* @{
bogdanm	0:9b334a45a8ff	613	*/
bogdanm	0:9b334a45a8ff	614	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
bogdanm	0:9b334a45a8ff	615	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
bogdanm	0:9b334a45a8ff	618	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
bogdanm	0:9b334a45a8ff	621	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
bogdanm	0:9b334a45a8ff	622
bogdanm	0:9b334a45a8ff	623	/**
bogdanm	0:9b334a45a8ff	624	* @}
bogdanm	0:9b334a45a8ff	625	*/
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	628	* @{
bogdanm	0:9b334a45a8ff	629	*/
bogdanm	0:9b334a45a8ff	630	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
bogdanm	0:9b334a45a8ff	631	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
bogdanm	0:9b334a45a8ff	632
bogdanm	0:9b334a45a8ff	633	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	634	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	635	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	636	#define TIM_DMABase_DIER TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	637	#define TIM_DMABase_SR TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	638	#define TIM_DMABase_EGR TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	639	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	640	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	641	#define TIM_DMABase_CCER TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	642	#define TIM_DMABase_CNT TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	643	#define TIM_DMABase_PSC TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	644	#define TIM_DMABase_ARR TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	645	#define TIM_DMABase_RCR TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	646	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	647	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	648	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	649	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	650	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	651	#define TIM_DMABase_DCR TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	652	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
bogdanm	0:9b334a45a8ff	653	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
bogdanm	0:9b334a45a8ff	654	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
bogdanm	0:9b334a45a8ff	655	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
bogdanm	0:9b334a45a8ff	656	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
bogdanm	0:9b334a45a8ff	657	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
bogdanm	0:9b334a45a8ff	658	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
bogdanm	0:9b334a45a8ff	659	#define TIM_DMABase_OR TIM_DMABASE_OR
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
bogdanm	0:9b334a45a8ff	662	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
bogdanm	0:9b334a45a8ff	663	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
bogdanm	0:9b334a45a8ff	664	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
bogdanm	0:9b334a45a8ff	665	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
bogdanm	0:9b334a45a8ff	666	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
bogdanm	0:9b334a45a8ff	667	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
bogdanm	0:9b334a45a8ff	668	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
bogdanm	0:9b334a45a8ff	669	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
bogdanm	0:9b334a45a8ff	672	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
bogdanm	0:9b334a45a8ff	673	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
bogdanm	0:9b334a45a8ff	674	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
bogdanm	0:9b334a45a8ff	675	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
bogdanm	0:9b334a45a8ff	676	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
bogdanm	0:9b334a45a8ff	677	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
bogdanm	0:9b334a45a8ff	678	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
bogdanm	0:9b334a45a8ff	679	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
bogdanm	0:9b334a45a8ff	680	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
bogdanm	0:9b334a45a8ff	681	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
bogdanm	0:9b334a45a8ff	682	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
bogdanm	0:9b334a45a8ff	683	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
bogdanm	0:9b334a45a8ff	684	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
bogdanm	0:9b334a45a8ff	685	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
bogdanm	0:9b334a45a8ff	686	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
bogdanm	0:9b334a45a8ff	687	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
bogdanm	0:9b334a45a8ff	688	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	/**
bogdanm	0:9b334a45a8ff	691	* @}
bogdanm	0:9b334a45a8ff	692	*/
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	695	* @{
bogdanm	0:9b334a45a8ff	696	*/
bogdanm	0:9b334a45a8ff	697	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
bogdanm	0:9b334a45a8ff	698	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
bogdanm	0:9b334a45a8ff	699	/**
bogdanm	0:9b334a45a8ff	700	* @}
bogdanm	0:9b334a45a8ff	701	*/
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	704	* @{
bogdanm	0:9b334a45a8ff	705	*/
bogdanm	0:9b334a45a8ff	706	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	707	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	708	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	709	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	712	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	713
bogdanm	0:9b334a45a8ff	714	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
bogdanm	0:9b334a45a8ff	715	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
bogdanm	0:9b334a45a8ff	716	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
bogdanm	0:9b334a45a8ff	717	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
bogdanm	0:9b334a45a8ff	720	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
bogdanm	0:9b334a45a8ff	721	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
bogdanm	0:9b334a45a8ff	722	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
bogdanm	0:9b334a45a8ff	725	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	/**
bogdanm	0:9b334a45a8ff	728	* @}
bogdanm	0:9b334a45a8ff	729	*/
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731
bogdanm	0:9b334a45a8ff	732	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	733	* @{
bogdanm	0:9b334a45a8ff	734	*/
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
bogdanm	0:9b334a45a8ff	737	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	#define USARTNACK_ENABLED USART_NACK_ENABLE
bogdanm	0:9b334a45a8ff	740	#define USARTNACK_DISABLED USART_NACK_DISABLE
bogdanm	0:9b334a45a8ff	741	/**
bogdanm	0:9b334a45a8ff	742	* @}
bogdanm	0:9b334a45a8ff	743	*/
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	746	* @{
bogdanm	0:9b334a45a8ff	747	*/
bogdanm	0:9b334a45a8ff	748	#define CFR_BASE WWDG_CFR_BASE
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	/**
bogdanm	0:9b334a45a8ff	751	* @}
bogdanm	0:9b334a45a8ff	752	*/
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	755	* @{
bogdanm	0:9b334a45a8ff	756	*/
bogdanm	0:9b334a45a8ff	757	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
bogdanm	0:9b334a45a8ff	758	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
bogdanm	0:9b334a45a8ff	759	#define CAN_IT_RQCP0 CAN_IT_TME
bogdanm	0:9b334a45a8ff	760	#define CAN_IT_RQCP1 CAN_IT_TME
bogdanm	0:9b334a45a8ff	761	#define CAN_IT_RQCP2 CAN_IT_TME
bogdanm	0:9b334a45a8ff	762	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	763	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	764	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	765	#define CAN_TXSTATUS_OK ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	766	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
bogdanm	0:9b334a45a8ff	767
bogdanm	0:9b334a45a8ff	768	/**
bogdanm	0:9b334a45a8ff	769	* @}
bogdanm	0:9b334a45a8ff	770	*/
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	773	* @{
bogdanm	0:9b334a45a8ff	774	*/
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	#define VLAN_TAG ETH_VLAN_TAG
bogdanm	0:9b334a45a8ff	777	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
bogdanm	0:9b334a45a8ff	778	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
bogdanm	0:9b334a45a8ff	779	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
bogdanm	0:9b334a45a8ff	780	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
bogdanm	0:9b334a45a8ff	781	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	782	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	783	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	784
bogdanm	0:9b334a45a8ff	785	#define ETH_MMCCR ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	786	#define ETH_MMCRIR ((uint32_t)0x00000104)
bogdanm	0:9b334a45a8ff	787	#define ETH_MMCTIR ((uint32_t)0x00000108)
bogdanm	0:9b334a45a8ff	788	#define ETH_MMCRIMR ((uint32_t)0x0000010C)
bogdanm	0:9b334a45a8ff	789	#define ETH_MMCTIMR ((uint32_t)0x00000110)
bogdanm	0:9b334a45a8ff	790	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
bogdanm	0:9b334a45a8ff	791	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
bogdanm	0:9b334a45a8ff	792	#define ETH_MMCTGFCR ((uint32_t)0x00000168)
bogdanm	0:9b334a45a8ff	793	#define ETH_MMCRFCECR ((uint32_t)0x00000194)
bogdanm	0:9b334a45a8ff	794	#define ETH_MMCRFAECR ((uint32_t)0x00000198)
bogdanm	0:9b334a45a8ff	795	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/**
bogdanm	0:9b334a45a8ff	798	* @}
bogdanm	0:9b334a45a8ff	799	*/
bogdanm	0:9b334a45a8ff	800
bogdanm	0:9b334a45a8ff	801	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	802	* @{
bogdanm	0:9b334a45a8ff	803	*/
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	/**
bogdanm	0:9b334a45a8ff	806	* @}
bogdanm	0:9b334a45a8ff	807	*/
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	812	* @{
bogdanm	0:9b334a45a8ff	813	*/
bogdanm	0:9b334a45a8ff	814	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
bogdanm	0:9b334a45a8ff	815	/**
bogdanm	0:9b334a45a8ff	816	* @}
bogdanm	0:9b334a45a8ff	817	*/
bogdanm	0:9b334a45a8ff	818
bogdanm	0:9b334a45a8ff	819	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	820	* @{
bogdanm	0:9b334a45a8ff	821	*/
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
bogdanm	0:9b334a45a8ff	824	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
bogdanm	0:9b334a45a8ff	825	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
bogdanm	0:9b334a45a8ff	826	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/HASH Algorithm Selection/
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
bogdanm	0:9b334a45a8ff	831	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
bogdanm	0:9b334a45a8ff	832	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
bogdanm	0:9b334a45a8ff	833	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
bogdanm	0:9b334a45a8ff	836	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
bogdanm	0:9b334a45a8ff	839	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
bogdanm	0:9b334a45a8ff	840	/**
bogdanm	0:9b334a45a8ff	841	* @}
bogdanm	0:9b334a45a8ff	842	*/
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	845	* @{
bogdanm	0:9b334a45a8ff	846	*/
bogdanm	0:9b334a45a8ff	847	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
bogdanm	0:9b334a45a8ff	848	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
bogdanm	0:9b334a45a8ff	849	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
bogdanm	0:9b334a45a8ff	850	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
bogdanm	0:9b334a45a8ff	851	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
bogdanm	0:9b334a45a8ff	852	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
bogdanm	0:9b334a45a8ff	853	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
bogdanm	0:9b334a45a8ff	854	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
bogdanm	0:9b334a45a8ff	855	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
bogdanm	0:9b334a45a8ff	856	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
bogdanm	0:9b334a45a8ff	857	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
bogdanm	0:9b334a45a8ff	858	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
bogdanm	0:9b334a45a8ff	859	/**
bogdanm	0:9b334a45a8ff	860	* @}
bogdanm	0:9b334a45a8ff	861	*/
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	864	* @{
bogdanm	0:9b334a45a8ff	865	*/
bogdanm	0:9b334a45a8ff	866	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
bogdanm	0:9b334a45a8ff	867	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
bogdanm	0:9b334a45a8ff	868	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
bogdanm	0:9b334a45a8ff	869	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
bogdanm	0:9b334a45a8ff	870	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
bogdanm	0:9b334a45a8ff	871	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
bogdanm	0:9b334a45a8ff	872	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	/**
bogdanm	0:9b334a45a8ff	875	* @}
bogdanm	0:9b334a45a8ff	876	*/
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	879	* @{
bogdanm	0:9b334a45a8ff	880	*/
bogdanm	0:9b334a45a8ff	881	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
bogdanm	0:9b334a45a8ff	882	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
bogdanm	0:9b334a45a8ff	885	/**
bogdanm	0:9b334a45a8ff	886	* @}
bogdanm	0:9b334a45a8ff	887	*/
bogdanm	0:9b334a45a8ff	888
bogdanm	0:9b334a45a8ff	889	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
bogdanm	0:9b334a45a8ff	890	* @{
bogdanm	0:9b334a45a8ff	891	*/
bogdanm	0:9b334a45a8ff	892	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
bogdanm	0:9b334a45a8ff	893	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
bogdanm	0:9b334a45a8ff	894	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
bogdanm	0:9b334a45a8ff	895	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
bogdanm	0:9b334a45a8ff	896	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
bogdanm	0:9b334a45a8ff	897	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
bogdanm	0:9b334a45a8ff	898	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
bogdanm	0:9b334a45a8ff	899	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
bogdanm	0:9b334a45a8ff	900	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
bogdanm	0:9b334a45a8ff	901	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
bogdanm	0:9b334a45a8ff	902	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
bogdanm	0:9b334a45a8ff	903	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
bogdanm	0:9b334a45a8ff	904	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
bogdanm	0:9b334a45a8ff	905	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
bogdanm	0:9b334a45a8ff	906	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
bogdanm	0:9b334a45a8ff	907	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
bogdanm	0:9b334a45a8ff	910	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
bogdanm	0:9b334a45a8ff	911	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
bogdanm	0:9b334a45a8ff	912	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
bogdanm	0:9b334a45a8ff	913	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
bogdanm	0:9b334a45a8ff	914	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
bogdanm	0:9b334a45a8ff	915	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
bogdanm	0:9b334a45a8ff	918	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	#define DBP_BitNumber DBP_BIT_NUMBER
bogdanm	0:9b334a45a8ff	921	#define PVDE_BitNumber PVDE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	922	#define PMODE_BitNumber PMODE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	923	#define EWUP_BitNumber EWUP_BIT_NUMBER
bogdanm	0:9b334a45a8ff	924	#define FPDS_BitNumber FPDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	925	#define ODEN_BitNumber ODEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	926	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	927	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	928	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	929	#define BRE_BitNumber BRE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	/**
bogdanm	0:9b334a45a8ff	934	* @}
bogdanm	0:9b334a45a8ff	935	*/
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	938	* @{
bogdanm	0:9b334a45a8ff	939	*/
bogdanm	0:9b334a45a8ff	940	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
bogdanm	0:9b334a45a8ff	941	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
bogdanm	0:9b334a45a8ff	942	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
bogdanm	0:9b334a45a8ff	943	/**
bogdanm	0:9b334a45a8ff	944	* @}
bogdanm	0:9b334a45a8ff	945	*/
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	948	* @{
bogdanm	0:9b334a45a8ff	949	*/
bogdanm	0:9b334a45a8ff	950	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
bogdanm	0:9b334a45a8ff	951	/**
bogdanm	0:9b334a45a8ff	952	* @}
bogdanm	0:9b334a45a8ff	953	*/
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	956	* @{
bogdanm	0:9b334a45a8ff	957	*/
bogdanm	0:9b334a45a8ff	958	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
bogdanm	0:9b334a45a8ff	959	#define HAL_TIM_DMAError TIM_DMAError
bogdanm	0:9b334a45a8ff	960	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
bogdanm	0:9b334a45a8ff	961	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
bogdanm	0:9b334a45a8ff	962	/**
bogdanm	0:9b334a45a8ff	963	* @}
bogdanm	0:9b334a45a8ff	964	*/
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	967	* @{
bogdanm	0:9b334a45a8ff	968	*/
bogdanm	0:9b334a45a8ff	969	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
bogdanm	0:9b334a45a8ff	970	/**
bogdanm	0:9b334a45a8ff	971	* @}
bogdanm	0:9b334a45a8ff	972	*/
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	975	* @{
bogdanm	0:9b334a45a8ff	976	*/
bogdanm	0:9b334a45a8ff	977	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
bogdanm	0:9b334a45a8ff	978	/**
bogdanm	0:9b334a45a8ff	979	* @}
bogdanm	0:9b334a45a8ff	980	*/
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	984	* @{
bogdanm	0:9b334a45a8ff	985	*/
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	/**
bogdanm	0:9b334a45a8ff	988	* @}
bogdanm	0:9b334a45a8ff	989	*/
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/* Exported macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	994	* @{
bogdanm	0:9b334a45a8ff	995	*/
bogdanm	0:9b334a45a8ff	996	#define AES_IT_CC CRYP_IT_CC
bogdanm	0:9b334a45a8ff	997	#define AES_IT_ERR CRYP_IT_ERR
bogdanm	0:9b334a45a8ff	998	#define AES_FLAG_CCF CRYP_FLAG_CCF
bogdanm	0:9b334a45a8ff	999	/**
bogdanm	0:9b334a45a8ff	1000	* @}
bogdanm	0:9b334a45a8ff	1001	*/
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1004	* @{
bogdanm	0:9b334a45a8ff	1005	*/
bogdanm	0:9b334a45a8ff	1006	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
bogdanm	0:9b334a45a8ff	1007	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
bogdanm	0:9b334a45a8ff	1008	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
bogdanm	0:9b334a45a8ff	1009	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
bogdanm	0:9b334a45a8ff	1010	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
bogdanm	0:9b334a45a8ff	1011	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
bogdanm	0:9b334a45a8ff	1012	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
bogdanm	0:9b334a45a8ff	1013	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
bogdanm	0:9b334a45a8ff	1014	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
bogdanm	0:9b334a45a8ff	1015	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
bogdanm	0:9b334a45a8ff	1016	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	1017	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
bogdanm	0:9b334a45a8ff	1018	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
bogdanm	0:9b334a45a8ff	1021	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
bogdanm	0:9b334a45a8ff	1022	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
bogdanm	0:9b334a45a8ff	1023	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1024	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/**
bogdanm	0:9b334a45a8ff	1027	* @}
bogdanm	0:9b334a45a8ff	1028	*/
bogdanm	0:9b334a45a8ff	1029
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1032	* @{
bogdanm	0:9b334a45a8ff	1033	*/
bogdanm	0:9b334a45a8ff	1034	#define __ADC_ENABLE __HAL_ADC_ENABLE
bogdanm	0:9b334a45a8ff	1035	#define __ADC_DISABLE __HAL_ADC_DISABLE
bogdanm	0:9b334a45a8ff	1036	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
bogdanm	0:9b334a45a8ff	1037	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
bogdanm	0:9b334a45a8ff	1038	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
bogdanm	0:9b334a45a8ff	1039	#define __ADC_IS_ENABLED ADC_IS_ENABLE
bogdanm	0:9b334a45a8ff	1040	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
bogdanm	0:9b334a45a8ff	1041	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
bogdanm	0:9b334a45a8ff	1042	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
bogdanm	0:9b334a45a8ff	1043	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
bogdanm	0:9b334a45a8ff	1044	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
bogdanm	0:9b334a45a8ff	1045	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
bogdanm	0:9b334a45a8ff	1046	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
bogdanm	0:9b334a45a8ff	1049	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
bogdanm	0:9b334a45a8ff	1050	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
bogdanm	0:9b334a45a8ff	1051	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
bogdanm	0:9b334a45a8ff	1052	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
bogdanm	0:9b334a45a8ff	1053	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
bogdanm	0:9b334a45a8ff	1054	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	1055	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	1056	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
bogdanm	0:9b334a45a8ff	1057	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
bogdanm	0:9b334a45a8ff	1058	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
bogdanm	0:9b334a45a8ff	1059	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
bogdanm	0:9b334a45a8ff	1060	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
bogdanm	0:9b334a45a8ff	1061	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
bogdanm	0:9b334a45a8ff	1062	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
bogdanm	0:9b334a45a8ff	1063	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
bogdanm	0:9b334a45a8ff	1064	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
bogdanm	0:9b334a45a8ff	1065	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
bogdanm	0:9b334a45a8ff	1066	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
bogdanm	0:9b334a45a8ff	1067	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	1070	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	1071	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	1072	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
bogdanm	0:9b334a45a8ff	1073	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
bogdanm	0:9b334a45a8ff	1074	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
bogdanm	0:9b334a45a8ff	1075	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
bogdanm	0:9b334a45a8ff	1076	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
bogdanm	0:9b334a45a8ff	1077	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
bogdanm	0:9b334a45a8ff	1078	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
bogdanm	0:9b334a45a8ff	1081	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
bogdanm	0:9b334a45a8ff	1082	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
bogdanm	0:9b334a45a8ff	1083	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
bogdanm	0:9b334a45a8ff	1084	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
bogdanm	0:9b334a45a8ff	1085	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
bogdanm	0:9b334a45a8ff	1086	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
bogdanm	0:9b334a45a8ff	1087	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	#define __HAL_ADC_SQR1 ADC_SQR1
bogdanm	0:9b334a45a8ff	1090	#define __HAL_ADC_SMPR1 ADC_SMPR1
bogdanm	0:9b334a45a8ff	1091	#define __HAL_ADC_SMPR2 ADC_SMPR2
bogdanm	0:9b334a45a8ff	1092	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
bogdanm	0:9b334a45a8ff	1093	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
bogdanm	0:9b334a45a8ff	1094	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
bogdanm	0:9b334a45a8ff	1095	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
bogdanm	0:9b334a45a8ff	1096	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
bogdanm	0:9b334a45a8ff	1097	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
bogdanm	0:9b334a45a8ff	1098	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
bogdanm	0:9b334a45a8ff	1099	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
bogdanm	0:9b334a45a8ff	1100	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
bogdanm	0:9b334a45a8ff	1101	#define __HAL_ADC_JSQR ADC_JSQR
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
bogdanm	0:9b334a45a8ff	1104	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	1105	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
bogdanm	0:9b334a45a8ff	1106	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
bogdanm	0:9b334a45a8ff	1107	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
bogdanm	0:9b334a45a8ff	1108	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
bogdanm	0:9b334a45a8ff	1109	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
bogdanm	0:9b334a45a8ff	1110	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	/**
bogdanm	0:9b334a45a8ff	1113	* @}
bogdanm	0:9b334a45a8ff	1114	*/
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1117	* @{
bogdanm	0:9b334a45a8ff	1118	*/
bogdanm	0:9b334a45a8ff	1119	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
bogdanm	0:9b334a45a8ff	1120	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
bogdanm	0:9b334a45a8ff	1121	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
bogdanm	0:9b334a45a8ff	1122	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	/**
bogdanm	0:9b334a45a8ff	1125	* @}
bogdanm	0:9b334a45a8ff	1126	*/
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1129	* @{
bogdanm	0:9b334a45a8ff	1130	*/
bogdanm	0:9b334a45a8ff	1131	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
bogdanm	0:9b334a45a8ff	1132	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
bogdanm	0:9b334a45a8ff	1133	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
bogdanm	0:9b334a45a8ff	1134	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
bogdanm	0:9b334a45a8ff	1135	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
bogdanm	0:9b334a45a8ff	1136	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
bogdanm	0:9b334a45a8ff	1137	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
bogdanm	0:9b334a45a8ff	1138	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
bogdanm	0:9b334a45a8ff	1139	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
bogdanm	0:9b334a45a8ff	1140	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
bogdanm	0:9b334a45a8ff	1141	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
bogdanm	0:9b334a45a8ff	1142	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
bogdanm	0:9b334a45a8ff	1143	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
bogdanm	0:9b334a45a8ff	1144	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
bogdanm	0:9b334a45a8ff	1145	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
bogdanm	0:9b334a45a8ff	1146	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
bogdanm	0:9b334a45a8ff	1149	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
bogdanm	0:9b334a45a8ff	1150	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
bogdanm	0:9b334a45a8ff	1151	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
bogdanm	0:9b334a45a8ff	1152	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
bogdanm	0:9b334a45a8ff	1153	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
bogdanm	0:9b334a45a8ff	1154	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
bogdanm	0:9b334a45a8ff	1155	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
bogdanm	0:9b334a45a8ff	1156	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
bogdanm	0:9b334a45a8ff	1157	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
bogdanm	0:9b334a45a8ff	1158	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
bogdanm	0:9b334a45a8ff	1159	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
bogdanm	0:9b334a45a8ff	1160	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
bogdanm	0:9b334a45a8ff	1161	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
bogdanm	0:9b334a45a8ff	1165	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
bogdanm	0:9b334a45a8ff	1166	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
bogdanm	0:9b334a45a8ff	1167	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
bogdanm	0:9b334a45a8ff	1168	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
bogdanm	0:9b334a45a8ff	1169	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
bogdanm	0:9b334a45a8ff	1170	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
bogdanm	0:9b334a45a8ff	1171	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
bogdanm	0:9b334a45a8ff	1172	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
bogdanm	0:9b334a45a8ff	1173	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
bogdanm	0:9b334a45a8ff	1174	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
bogdanm	0:9b334a45a8ff	1175	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
bogdanm	0:9b334a45a8ff	1176	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
bogdanm	0:9b334a45a8ff	1177	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
bogdanm	0:9b334a45a8ff	1178	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
bogdanm	0:9b334a45a8ff	1179	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
bogdanm	0:9b334a45a8ff	1180	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
bogdanm	0:9b334a45a8ff	1181	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
bogdanm	0:9b334a45a8ff	1182	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
bogdanm	0:9b334a45a8ff	1183	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
bogdanm	0:9b334a45a8ff	1184	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
bogdanm	0:9b334a45a8ff	1185	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
bogdanm	0:9b334a45a8ff	1186	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
bogdanm	0:9b334a45a8ff	1187	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	/**
bogdanm	0:9b334a45a8ff	1190	* @}
bogdanm	0:9b334a45a8ff	1191	*/
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1194	* @{
bogdanm	0:9b334a45a8ff	1195	*/
bogdanm	0:9b334a45a8ff	1196
bogdanm	0:9b334a45a8ff	1197	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
bogdanm	0:9b334a45a8ff	1198	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
bogdanm	0:9b334a45a8ff	1199	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
bogdanm	0:9b334a45a8ff	1200	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
bogdanm	0:9b334a45a8ff	1201	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
bogdanm	0:9b334a45a8ff	1202	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
bogdanm	0:9b334a45a8ff	1203	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
bogdanm	0:9b334a45a8ff	1204	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
bogdanm	0:9b334a45a8ff	1205	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
bogdanm	0:9b334a45a8ff	1206	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
bogdanm	0:9b334a45a8ff	1207	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
bogdanm	0:9b334a45a8ff	1208	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
bogdanm	0:9b334a45a8ff	1209	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
bogdanm	0:9b334a45a8ff	1210	__HAL_COMP_COMP2_EXTI_GET_FLAG())
bogdanm	0:9b334a45a8ff	1211	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
bogdanm	0:9b334a45a8ff	1212	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
bogdanm	0:9b334a45a8ff	1213	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	/**
bogdanm	0:9b334a45a8ff	1216	* @}
bogdanm	0:9b334a45a8ff	1217	*/
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1220	* @{
bogdanm	0:9b334a45a8ff	1221	*/
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1224	((WAVE) == DAC_WAVE_NOISE)\|\| \
bogdanm	0:9b334a45a8ff	1225	((WAVE) == DAC_WAVE_TRIANGLE))
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/**
bogdanm	0:9b334a45a8ff	1228	* @}
bogdanm	0:9b334a45a8ff	1229	*/
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1232	* @{
bogdanm	0:9b334a45a8ff	1233	*/
bogdanm	0:9b334a45a8ff	1234
bogdanm	0:9b334a45a8ff	1235	#define IS_WRPAREA IS_OB_WRPAREA
bogdanm	0:9b334a45a8ff	1236	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
bogdanm	0:9b334a45a8ff	1237	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
bogdanm	0:9b334a45a8ff	1238	#define IS_TYPEERASE IS_FLASH_TYPEERASE
bogdanm	0:9b334a45a8ff	1239	#define IS_NBSECTORS IS_FLASH_NBSECTORS
bogdanm	0:9b334a45a8ff	1240	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	/**
bogdanm	0:9b334a45a8ff	1243	* @}
bogdanm	0:9b334a45a8ff	1244	*/
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1247	* @{
bogdanm	0:9b334a45a8ff	1248	*/
bogdanm	0:9b334a45a8ff	1249
bogdanm	0:9b334a45a8ff	1250	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
bogdanm	0:9b334a45a8ff	1251	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
bogdanm	0:9b334a45a8ff	1252	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
bogdanm	0:9b334a45a8ff	1253	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
bogdanm	0:9b334a45a8ff	1254	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
bogdanm	0:9b334a45a8ff	1255	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
bogdanm	0:9b334a45a8ff	1256	#define __HAL_I2C_SPEED I2C_SPEED
bogdanm	0:9b334a45a8ff	1257	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
bogdanm	0:9b334a45a8ff	1258	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
bogdanm	0:9b334a45a8ff	1259	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
bogdanm	0:9b334a45a8ff	1260	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
bogdanm	0:9b334a45a8ff	1261	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
bogdanm	0:9b334a45a8ff	1262	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
bogdanm	0:9b334a45a8ff	1263	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
bogdanm	0:9b334a45a8ff	1264	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
bogdanm	0:9b334a45a8ff	1265	/**
bogdanm	0:9b334a45a8ff	1266	* @}
bogdanm	0:9b334a45a8ff	1267	*/
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1270	* @{
bogdanm	0:9b334a45a8ff	1271	*/
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
bogdanm	0:9b334a45a8ff	1274	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/**
bogdanm	0:9b334a45a8ff	1277	* @}
bogdanm	0:9b334a45a8ff	1278	*/
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1281	* @{
bogdanm	0:9b334a45a8ff	1282	*/
bogdanm	0:9b334a45a8ff	1283
bogdanm	0:9b334a45a8ff	1284	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
bogdanm	0:9b334a45a8ff	1285	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1288	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	1289	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1290	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	1293
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	/**
bogdanm	0:9b334a45a8ff	1296	* @}
bogdanm	0:9b334a45a8ff	1297	*/
bogdanm	0:9b334a45a8ff	1298
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1301	* @{
bogdanm	0:9b334a45a8ff	1302	*/
bogdanm	0:9b334a45a8ff	1303	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
bogdanm	0:9b334a45a8ff	1304	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
bogdanm	0:9b334a45a8ff	1305	/**
bogdanm	0:9b334a45a8ff	1306	* @}
bogdanm	0:9b334a45a8ff	1307	*/
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309
bogdanm	0:9b334a45a8ff	1310	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1311	* @{
bogdanm	0:9b334a45a8ff	1312	*/
bogdanm	0:9b334a45a8ff	1313
bogdanm	0:9b334a45a8ff	1314	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
bogdanm	0:9b334a45a8ff	1315	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
bogdanm	0:9b334a45a8ff	1316	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/**
bogdanm	0:9b334a45a8ff	1319	* @}
bogdanm	0:9b334a45a8ff	1320	*/
bogdanm	0:9b334a45a8ff	1321
bogdanm	0:9b334a45a8ff	1322
bogdanm	0:9b334a45a8ff	1323	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1324	* @{
bogdanm	0:9b334a45a8ff	1325	*/
bogdanm	0:9b334a45a8ff	1326	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
bogdanm	0:9b334a45a8ff	1327	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
bogdanm	0:9b334a45a8ff	1328	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
bogdanm	0:9b334a45a8ff	1329	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
bogdanm	0:9b334a45a8ff	1330	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
bogdanm	0:9b334a45a8ff	1331	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
bogdanm	0:9b334a45a8ff	1332	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
bogdanm	0:9b334a45a8ff	1333	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
bogdanm	0:9b334a45a8ff	1334	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
bogdanm	0:9b334a45a8ff	1335	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
bogdanm	0:9b334a45a8ff	1336	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
bogdanm	0:9b334a45a8ff	1337	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
bogdanm	0:9b334a45a8ff	1338	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	/**
bogdanm	0:9b334a45a8ff	1341	* @}
bogdanm	0:9b334a45a8ff	1342	*/
bogdanm	0:9b334a45a8ff	1343
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1346	* @{
bogdanm	0:9b334a45a8ff	1347	*/
bogdanm	0:9b334a45a8ff	1348	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
bogdanm	0:9b334a45a8ff	1349	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
bogdanm	0:9b334a45a8ff	1350	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1351	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1352	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1353	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1354	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
bogdanm	0:9b334a45a8ff	1355	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
bogdanm	0:9b334a45a8ff	1356	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
bogdanm	0:9b334a45a8ff	1357	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
bogdanm	0:9b334a45a8ff	1358	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
bogdanm	0:9b334a45a8ff	1359	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
bogdanm	0:9b334a45a8ff	1360	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
bogdanm	0:9b334a45a8ff	1361	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
bogdanm	0:9b334a45a8ff	1362	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
bogdanm	0:9b334a45a8ff	1363	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
bogdanm	0:9b334a45a8ff	1364	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
bogdanm	0:9b334a45a8ff	1365	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
bogdanm	0:9b334a45a8ff	1366	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
bogdanm	0:9b334a45a8ff	1367	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1368	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1369	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1370	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1371	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1372	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1373	#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
bogdanm	0:9b334a45a8ff	1374	#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
bogdanm	0:9b334a45a8ff	1375	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
bogdanm	0:9b334a45a8ff	1376	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
bogdanm	0:9b334a45a8ff	1377	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
bogdanm	0:9b334a45a8ff	1378	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
bogdanm	0:9b334a45a8ff	1379	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1380	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1381	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
bogdanm	0:9b334a45a8ff	1382	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	#if defined (STM32F4)
bogdanm	0:9b334a45a8ff	1385	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
bogdanm	0:9b334a45a8ff	1386	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
bogdanm	0:9b334a45a8ff	1387	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
bogdanm	0:9b334a45a8ff	1388	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
bogdanm	0:9b334a45a8ff	1389	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
bogdanm	0:9b334a45a8ff	1390	#else
bogdanm	0:9b334a45a8ff	1391	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	1392	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	1393	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	1394	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	1395	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	1396	#endif /* STM32F4 */
bogdanm	0:9b334a45a8ff	1397	/**
bogdanm	0:9b334a45a8ff	1398	* @}
bogdanm	0:9b334a45a8ff	1399	*/
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1403	* @{
bogdanm	0:9b334a45a8ff	1404	*/
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
bogdanm	0:9b334a45a8ff	1407	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
bogdanm	0:9b334a45a8ff	1410	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1413	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1414	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1415	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1416	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1417	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1418	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1419	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1420	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1421	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1422	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1423	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1424	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1425	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1426	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1427	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1428	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1429	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1430	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1431	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1432	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1433	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1434	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1435	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1436	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
bogdanm	0:9b334a45a8ff	1437	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1438	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1439	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1440	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1441	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1442	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1443	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1444	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1445	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1446	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
bogdanm	0:9b334a45a8ff	1447	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1448	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
bogdanm	0:9b334a45a8ff	1449	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1450	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1451	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1452	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1453	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1454	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1455	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1456	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1457	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1458	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1459	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1460	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1461	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1462	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1463	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1464	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1465	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1466	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1467	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1468	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1469	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1470	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1471	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1472	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1473	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1474	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1475	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1476	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1477	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1478	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1479	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1480	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1481	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1482	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1483	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1484	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1485	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1486	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1487	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1488	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1489	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1490	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1491	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1492	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1493	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1494	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1495	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1496	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1497	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1498	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1499	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1500	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1501	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1502	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1503	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1504	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1505	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1506	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
bogdanm	0:9b334a45a8ff	1507	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1508	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1509	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1510	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1511	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1512	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
bogdanm	0:9b334a45a8ff	1513	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1514	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1515	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1516	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1517	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1518	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1519	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1520	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1521	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1522	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1523	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1524	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1525	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1526	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1527	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1528	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1529	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1530	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1531	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1532	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1533	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1534	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1535	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1536	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1537	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1538	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1539	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1540	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
bogdanm	0:9b334a45a8ff	1541	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1542	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1543	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1544	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
bogdanm	0:9b334a45a8ff	1545	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1546	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1547	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1548	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1549	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1550	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1551	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1552	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1553	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1554	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1555	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1556	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1557	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1558	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1559	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1560	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
bogdanm	0:9b334a45a8ff	1561	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1562	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1563	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1564	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1565	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1566	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
bogdanm	0:9b334a45a8ff	1567	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1568	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1569	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1570	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1571	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1572	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1573	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1574	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1575	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1576	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1577	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1578	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
bogdanm	0:9b334a45a8ff	1579	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1580	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1581	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1582	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1583	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1584	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
bogdanm	0:9b334a45a8ff	1585	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1586	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1587	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1588	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1589	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1590	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
bogdanm	0:9b334a45a8ff	1591	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1592	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1593	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1594	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1595	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1596	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1597	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1598	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1599	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1600	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1601	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1602	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
bogdanm	0:9b334a45a8ff	1603	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1604	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1605	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1606	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1607	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1608	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1609	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1610	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1611	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1612	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1613	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1614	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1615	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1616	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1617	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1618	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1619	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1620	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1621	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1622	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1623	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1624	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1625	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1626	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
bogdanm	0:9b334a45a8ff	1627	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1628	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1629	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1630	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1631	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1632	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1633	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1634	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1635	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1636	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1637	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1638	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1639	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1640	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1641	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1642	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1643	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1644	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1645	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1646	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1647	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1648	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1649	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1650	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1651	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1652	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1653	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1654	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1655	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1656	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
bogdanm	0:9b334a45a8ff	1657	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1658	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1659	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1660	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1661	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1662	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
bogdanm	0:9b334a45a8ff	1663	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1664	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1665	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1666	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1667	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1668	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
bogdanm	0:9b334a45a8ff	1669	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1670	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1671	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1672	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1673	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1674	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1675	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1676	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1677	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1678	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1679	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1680	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1681	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1682	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1683	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1684	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1685	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1686	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1687	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1688	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1689	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1690	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1691	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1692	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1693	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1694	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1695	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1696	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1697	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1698	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1699	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1700	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1701	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1702	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1703	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1704	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1705	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1706	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1707	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1708	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1709	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1710	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1711	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1712	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1713	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1714	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1715	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1716	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1717	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1718	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1719	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1720	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1721	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1722	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1723	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1724	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1725	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1726	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1727	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1728	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1729	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1730	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1731	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1732	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1733	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1734	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1735	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1736	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1737	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1738	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1739	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1740	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
bogdanm	0:9b334a45a8ff	1741	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1742	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1743	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1744	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
bogdanm	0:9b334a45a8ff	1745	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1746	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1747	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1748	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
bogdanm	0:9b334a45a8ff	1749	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1750	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1751	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1752	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
bogdanm	0:9b334a45a8ff	1753	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1754	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1755	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1756	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
bogdanm	0:9b334a45a8ff	1757	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1758	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1759	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1760	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1761	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1762	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
bogdanm	0:9b334a45a8ff	1763	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1764	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1765	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1766	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1767	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1768	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
bogdanm	0:9b334a45a8ff	1769	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1770	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1771	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1772	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1773	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1774	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
bogdanm	0:9b334a45a8ff	1775	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1776	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1777	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1778	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1779	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1780	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1781	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1782	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1783	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1784	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1785	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1786	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1787	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1788	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1789	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1790	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1791	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1792	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
bogdanm	0:9b334a45a8ff	1793	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1794	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1795	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1796	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1797	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1798	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
bogdanm	0:9b334a45a8ff	1799	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1800	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1801	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1802	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1803	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1804	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
bogdanm	0:9b334a45a8ff	1805	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1806	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1807	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1808	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1809	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1810	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
bogdanm	0:9b334a45a8ff	1811	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1812	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1813	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1814	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1815	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1816	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
bogdanm	0:9b334a45a8ff	1817	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1818	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1819	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1820	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
bogdanm	0:9b334a45a8ff	1821	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1822	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1823	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1824	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1825	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1826	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1827	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1828	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1829	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1830	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1831	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1832	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
bogdanm	0:9b334a45a8ff	1833	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1834	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1835	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1836	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1837	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1838	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
bogdanm	0:9b334a45a8ff	1839	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1840	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1841	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1842	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1843	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1844	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1845	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1846	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1847	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1848	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1849	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1850	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1851	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1852	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1853	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1854	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1855	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1856	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1857	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1858	#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1859	#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1860	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1861	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1862	#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
bogdanm	0:9b334a45a8ff	1863	#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1864	#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1865	#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1866	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1867	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1868	#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
bogdanm	0:9b334a45a8ff	1869	#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1870	#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1871	#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1872	#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
bogdanm	0:9b334a45a8ff	1873	#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1874	#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1875	#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1876	#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
bogdanm	0:9b334a45a8ff	1877	#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1878	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1879	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1880	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
bogdanm	0:9b334a45a8ff	1881	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1882	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1883	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1884	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1885	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1886	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1887	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1888	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1889	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1890	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1891	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1892	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1893	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1894	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
bogdanm	0:9b334a45a8ff	1895	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1896	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1897	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1898	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1899	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1900	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
bogdanm	0:9b334a45a8ff	1901	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1902	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1903	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1904	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1905	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1906	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1907	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1908	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
bogdanm	0:9b334a45a8ff	1909	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1910	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
bogdanm	0:9b334a45a8ff	1911	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
bogdanm	0:9b334a45a8ff	1912
bogdanm	0:9b334a45a8ff	1913	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
bogdanm	0:9b334a45a8ff	1914	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1915	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1916	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1917	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1918	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1919	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1920	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1921	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1922	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1923	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1924	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1925	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1926	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1927	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1928	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1929	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1930	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1931	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1932	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
bogdanm	0:9b334a45a8ff	1933	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1934	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1935	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1936	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1937	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1938	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1939	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
bogdanm	0:9b334a45a8ff	1940	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1941	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1942	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1943	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1944	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1945	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
bogdanm	0:9b334a45a8ff	1946	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1947	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1948	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1949	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1950	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1951	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1952	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1953	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1954	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1955	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1956	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1957	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1958	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1959	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1960	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1961	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1962	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1963	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1964	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1965	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1966	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1967	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1968	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1969	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1970	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1971	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1972	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1973	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1974	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
bogdanm	0:9b334a45a8ff	1975	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1976	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1977	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1978	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1979	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1980	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
bogdanm	0:9b334a45a8ff	1981	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1982	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1983	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1984	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1985	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1986	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
bogdanm	0:9b334a45a8ff	1987	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1988	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1989	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1990	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1991	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1992	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
bogdanm	0:9b334a45a8ff	1993	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1994	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1995	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1996	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1997	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1998	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1999	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2000	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2001	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2002	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2003	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2004	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2005	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
bogdanm	0:9b334a45a8ff	2006	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2007	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2008	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2009	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2010	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2011	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2012	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
bogdanm	0:9b334a45a8ff	2013	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2014	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2015	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2016	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2017	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
bogdanm	0:9b334a45a8ff	2018	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2019	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2020	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2021	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2022	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2023	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
bogdanm	0:9b334a45a8ff	2024	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2025	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2026	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2027	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2028	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2029	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
bogdanm	0:9b334a45a8ff	2030	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
bogdanm	0:9b334a45a8ff	2031	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
bogdanm	0:9b334a45a8ff	2032	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
mbed_official	19:112740acecfa	2033	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2034	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
mbed_official	19:112740acecfa	2035	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
bogdanm	0:9b334a45a8ff	2036	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
mbed_official	19:112740acecfa	2037	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
mbed_official	19:112740acecfa	2038	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2039	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2040	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
mbed_official	19:112740acecfa	2041	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2042	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
mbed_official	19:112740acecfa	2043	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2044	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
mbed_official	19:112740acecfa	2045	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2046	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
mbed_official	19:112740acecfa	2047	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
mbed_official	19:112740acecfa	2048	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
mbed_official	19:112740acecfa	2049	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2050	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
mbed_official	19:112740acecfa	2051	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
mbed_official	19:112740acecfa	2052	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
mbed_official	19:112740acecfa	2053	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
mbed_official	19:112740acecfa	2054	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2055	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
mbed_official	19:112740acecfa	2056	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
mbed_official	19:112740acecfa	2057	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
bogdanm	0:9b334a45a8ff	2058	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
mbed_official	19:112740acecfa	2059	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
mbed_official	19:112740acecfa	2060	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2061
bogdanm	0:9b334a45a8ff	2062	/* alias define maintained for legacy */
bogdanm	0:9b334a45a8ff	2063	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
bogdanm	0:9b334a45a8ff	2064	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2065
mbed_official	19:112740acecfa	2066	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
mbed_official	19:112740acecfa	2067	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
mbed_official	19:112740acecfa	2068	#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
mbed_official	19:112740acecfa	2069	#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
mbed_official	19:112740acecfa	2070	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
mbed_official	19:112740acecfa	2071	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
mbed_official	19:112740acecfa	2072	#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
mbed_official	19:112740acecfa	2073	#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
mbed_official	19:112740acecfa	2074	#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
mbed_official	19:112740acecfa	2075	#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
mbed_official	19:112740acecfa	2076	#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
mbed_official	19:112740acecfa	2077	#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
mbed_official	19:112740acecfa	2078	#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
mbed_official	19:112740acecfa	2079	#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
mbed_official	19:112740acecfa	2080	#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
mbed_official	19:112740acecfa	2081	#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
mbed_official	19:112740acecfa	2082	#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
mbed_official	19:112740acecfa	2083	#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
mbed_official	19:112740acecfa	2084	#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
mbed_official	19:112740acecfa	2085	#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
mbed_official	19:112740acecfa	2086	#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
mbed_official	19:112740acecfa	2087	#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
mbed_official	19:112740acecfa	2088
mbed_official	19:112740acecfa	2089	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
mbed_official	19:112740acecfa	2090	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
mbed_official	19:112740acecfa	2091	#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
mbed_official	19:112740acecfa	2092	#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
mbed_official	19:112740acecfa	2093	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
mbed_official	19:112740acecfa	2094	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
mbed_official	19:112740acecfa	2095	#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
mbed_official	19:112740acecfa	2096	#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
mbed_official	19:112740acecfa	2097	#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
mbed_official	19:112740acecfa	2098	#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
mbed_official	19:112740acecfa	2099	#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
mbed_official	19:112740acecfa	2100	#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
mbed_official	19:112740acecfa	2101	#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
mbed_official	19:112740acecfa	2102	#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
mbed_official	19:112740acecfa	2103	#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
mbed_official	19:112740acecfa	2104	#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
mbed_official	19:112740acecfa	2105	#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
mbed_official	19:112740acecfa	2106	#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
mbed_official	19:112740acecfa	2107	#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
mbed_official	19:112740acecfa	2108	#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
mbed_official	19:112740acecfa	2109	#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
mbed_official	19:112740acecfa	2110	#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
mbed_official	19:112740acecfa	2111
mbed_official	19:112740acecfa	2112	#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2113	#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2114	#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2115	#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2116	#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2117	#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2118	#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2119	#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2120	#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2121	#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2122	#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2123	#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2124	#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2125	#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2126	#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2127	#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2128	#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2129	#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2130	#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2131	#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2132	#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2133	#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2134	#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2135	#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2136	#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2137	#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2138	#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2139	#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2140	#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2141	#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2142	#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2143	#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2144	#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2145	#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2146	#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2147	#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2148	#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2149	#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2150	#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2151	#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2152	#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2153	#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2154	#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2155	#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2156	#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2157	#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2158	#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2159	#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2160	#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2161	#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2162	#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2163	#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2164	#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2165	#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2166	#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2167	#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2168	#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2169	#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2170	#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2171	#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2172	#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2173	#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2174	#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2175	#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2176	#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2177	#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2178	#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2179	#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2180	#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2181	#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2182	#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2183	#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2184	#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2185	#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2186	#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2187	#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2188	#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2189	#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2190	#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2191	#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2192	#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2193	#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2194	#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2195	#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2196	#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2197	#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2198	#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2199	#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2200	#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2201	#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2202	#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2203	#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2204	#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2205	#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2206	#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2207	#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2208	#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2209	#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2210	#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2211	#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2212	#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2213	#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2214	#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2215	#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2216	#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2217	#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2218	#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2219	#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2220	#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2221	#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2222	#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2223	#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2224	#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2225	#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2226	#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
mbed_official	19:112740acecfa	2227	#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
mbed_official	19:112740acecfa	2228
bogdanm	0:9b334a45a8ff	2229	#if defined(STM32F4)
bogdanm	0:9b334a45a8ff	2230	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2231	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
bogdanm	0:9b334a45a8ff	2232	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2233	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2234	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2235	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2236	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2237	#define Sdmmc1ClockSelection SdioClockSelection
bogdanm	0:9b334a45a8ff	2238	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
bogdanm	0:9b334a45a8ff	2239	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
bogdanm	0:9b334a45a8ff	2240	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
bogdanm	0:9b334a45a8ff	2241	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
bogdanm	0:9b334a45a8ff	2242	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
bogdanm	0:9b334a45a8ff	2243	#endif
bogdanm	0:9b334a45a8ff	2244
bogdanm	0:9b334a45a8ff	2245	#if defined(STM32F7) \|\| defined(STM32L4)
bogdanm	0:9b334a45a8ff	2246	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2247	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
bogdanm	0:9b334a45a8ff	2248	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2249	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2250	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2251	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2252	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2253	#define SdioClockSelection Sdmmc1ClockSelection
bogdanm	0:9b334a45a8ff	2254	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
bogdanm	0:9b334a45a8ff	2255	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
bogdanm	0:9b334a45a8ff	2256	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
bogdanm	0:9b334a45a8ff	2257	#endif
bogdanm	0:9b334a45a8ff	2258
bogdanm	0:9b334a45a8ff	2259	#if defined(STM32F7)
bogdanm	0:9b334a45a8ff	2260	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
bogdanm	0:9b334a45a8ff	2261	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
bogdanm	0:9b334a45a8ff	2262	#endif
bogdanm	0:9b334a45a8ff	2263
bogdanm	0:9b334a45a8ff	2264	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
bogdanm	0:9b334a45a8ff	2265	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
bogdanm	0:9b334a45a8ff	2266
mbed_official	19:112740acecfa	2267	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
mbed_official	19:112740acecfa	2268
mbed_official	19:112740acecfa	2269	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
mbed_official	19:112740acecfa	2270	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
mbed_official	19:112740acecfa	2271	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
mbed_official	19:112740acecfa	2272	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
mbed_official	19:112740acecfa	2273
mbed_official	19:112740acecfa	2274	#define RCC_IT_HSI14 RCC_IT_HSI14RDY
bogdanm	0:9b334a45a8ff	2275
mbed_official	19:112740acecfa	2276	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
mbed_official	19:112740acecfa	2277	#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
mbed_official	19:112740acecfa	2278	#define RCC_MCO_NODIV RCC_MCODIV_1
mbed_official	19:112740acecfa	2279	#define RCC_MCO_DIV1 RCC_MCODIV_1
mbed_official	19:112740acecfa	2280	#define RCC_MCO_DIV2 RCC_MCODIV_2
mbed_official	19:112740acecfa	2281	#define RCC_MCO_DIV4 RCC_MCODIV_4
mbed_official	19:112740acecfa	2282	#define RCC_MCO_DIV8 RCC_MCODIV_8
mbed_official	19:112740acecfa	2283	#define RCC_MCO_DIV16 RCC_MCODIV_16
mbed_official	19:112740acecfa	2284	#define RCC_MCO_DIV32 RCC_MCODIV_32
mbed_official	19:112740acecfa	2285	#define RCC_MCO_DIV64 RCC_MCODIV_64
mbed_official	19:112740acecfa	2286	#define RCC_MCO_DIV128 RCC_MCODIV_128
mbed_official	19:112740acecfa	2287	#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
mbed_official	19:112740acecfa	2288	#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
mbed_official	19:112740acecfa	2289	#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
mbed_official	19:112740acecfa	2290	#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
mbed_official	19:112740acecfa	2291	#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
mbed_official	19:112740acecfa	2292	#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
mbed_official	19:112740acecfa	2293	#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
mbed_official	19:112740acecfa	2294	#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
mbed_official	19:112740acecfa	2295	#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
mbed_official	19:112740acecfa	2296	#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
mbed_official	19:112740acecfa	2297	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
bogdanm	0:9b334a45a8ff	2298
mbed_official	19:112740acecfa	2299	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
mbed_official	19:112740acecfa	2300
mbed_official	19:112740acecfa	2301	#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
mbed_official	19:112740acecfa	2302	#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
mbed_official	19:112740acecfa	2303	#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
mbed_official	19:112740acecfa	2304	#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
mbed_official	19:112740acecfa	2305	#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
mbed_official	19:112740acecfa	2306	#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
mbed_official	19:112740acecfa	2307	#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
mbed_official	19:112740acecfa	2308	#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
bogdanm	0:9b334a45a8ff	2309
bogdanm	0:9b334a45a8ff	2310	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
mbed_official	19:112740acecfa	2311	#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
mbed_official	19:112740acecfa	2312	#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
mbed_official	19:112740acecfa	2313	#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
mbed_official	19:112740acecfa	2314	#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2315	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
mbed_official	19:112740acecfa	2316	#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2317	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
mbed_official	19:112740acecfa	2318	#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2319	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2320	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2321	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
mbed_official	19:112740acecfa	2322	#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2323	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
mbed_official	19:112740acecfa	2324	#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
mbed_official	19:112740acecfa	2325	#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2326	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
mbed_official	19:112740acecfa	2327	#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
mbed_official	19:112740acecfa	2328	#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
mbed_official	19:112740acecfa	2329	#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
mbed_official	19:112740acecfa	2330	#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2331	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2332	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
mbed_official	19:112740acecfa	2333	#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
mbed_official	19:112740acecfa	2334	#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
mbed_official	19:112740acecfa	2335	#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2336	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
bogdanm	0:9b334a45a8ff	2337	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
bogdanm	0:9b334a45a8ff	2338	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
bogdanm	0:9b334a45a8ff	2339	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
bogdanm	0:9b334a45a8ff	2340	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	2341	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	2342
bogdanm	0:9b334a45a8ff	2343	#define CR_HSION_BB RCC_CR_HSION_BB
bogdanm	0:9b334a45a8ff	2344	#define CR_CSSON_BB RCC_CR_CSSON_BB
bogdanm	0:9b334a45a8ff	2345	#define CR_PLLON_BB RCC_CR_PLLON_BB
bogdanm	0:9b334a45a8ff	2346	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
bogdanm	0:9b334a45a8ff	2347	#define CR_MSION_BB RCC_CR_MSION_BB
bogdanm	0:9b334a45a8ff	2348	#define CSR_LSION_BB RCC_CSR_LSION_BB
bogdanm	0:9b334a45a8ff	2349	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
bogdanm	0:9b334a45a8ff	2350	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
bogdanm	0:9b334a45a8ff	2351	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
bogdanm	0:9b334a45a8ff	2352	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
bogdanm	0:9b334a45a8ff	2353	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
bogdanm	0:9b334a45a8ff	2354	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
bogdanm	0:9b334a45a8ff	2355	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
mbed_official	19:112740acecfa	2356	#define CR_HSEON_BB RCC_CR_HSEON_BB
mbed_official	19:112740acecfa	2357	#define CSR_RMVF_BB RCC_CSR_RMVF_BB
bogdanm	0:9b334a45a8ff	2358	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
bogdanm	0:9b334a45a8ff	2359	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
bogdanm	0:9b334a45a8ff	2360
bogdanm	0:9b334a45a8ff	2361	/**
bogdanm	0:9b334a45a8ff	2362	* @}
bogdanm	0:9b334a45a8ff	2363	*/
bogdanm	0:9b334a45a8ff	2364
bogdanm	0:9b334a45a8ff	2365	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2366	* @{
bogdanm	0:9b334a45a8ff	2367	*/
bogdanm	0:9b334a45a8ff	2368	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
bogdanm	0:9b334a45a8ff	2369
bogdanm	0:9b334a45a8ff	2370	/**
bogdanm	0:9b334a45a8ff	2371	* @}
bogdanm	0:9b334a45a8ff	2372	*/
bogdanm	0:9b334a45a8ff	2373
bogdanm	0:9b334a45a8ff	2374	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2375	* @{
bogdanm	0:9b334a45a8ff	2376	*/
bogdanm	0:9b334a45a8ff	2377
bogdanm	0:9b334a45a8ff	2378	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2379	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2380	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2381
bogdanm	0:9b334a45a8ff	2382	#if defined (STM32F1)
bogdanm	0:9b334a45a8ff	2383	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
bogdanm	0:9b334a45a8ff	2384
bogdanm	0:9b334a45a8ff	2385	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
bogdanm	0:9b334a45a8ff	2386
bogdanm	0:9b334a45a8ff	2387	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
bogdanm	0:9b334a45a8ff	2388
bogdanm	0:9b334a45a8ff	2389	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
bogdanm	0:9b334a45a8ff	2390
bogdanm	0:9b334a45a8ff	2391	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
bogdanm	0:9b334a45a8ff	2392	#else
bogdanm	0:9b334a45a8ff	2393	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
bogdanm	0:9b334a45a8ff	2394	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
bogdanm	0:9b334a45a8ff	2395	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
bogdanm	0:9b334a45a8ff	2396	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
bogdanm	0:9b334a45a8ff	2397	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
bogdanm	0:9b334a45a8ff	2398	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
bogdanm	0:9b334a45a8ff	2399	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
bogdanm	0:9b334a45a8ff	2400	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
bogdanm	0:9b334a45a8ff	2401	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
bogdanm	0:9b334a45a8ff	2402	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
bogdanm	0:9b334a45a8ff	2403	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
bogdanm	0:9b334a45a8ff	2404	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
bogdanm	0:9b334a45a8ff	2405	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
bogdanm	0:9b334a45a8ff	2406	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
bogdanm	0:9b334a45a8ff	2407	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
bogdanm	0:9b334a45a8ff	2408	#endif /* STM32F1 */
bogdanm	0:9b334a45a8ff	2409
bogdanm	0:9b334a45a8ff	2410	#define IS_ALARM IS_RTC_ALARM
bogdanm	0:9b334a45a8ff	2411	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
bogdanm	0:9b334a45a8ff	2412	#define IS_TAMPER IS_RTC_TAMPER
bogdanm	0:9b334a45a8ff	2413	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
bogdanm	0:9b334a45a8ff	2414	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
bogdanm	0:9b334a45a8ff	2415	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
bogdanm	0:9b334a45a8ff	2416	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
bogdanm	0:9b334a45a8ff	2417	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
bogdanm	0:9b334a45a8ff	2418	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
bogdanm	0:9b334a45a8ff	2419	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
bogdanm	0:9b334a45a8ff	2420	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
bogdanm	0:9b334a45a8ff	2421	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
bogdanm	0:9b334a45a8ff	2422	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
bogdanm	0:9b334a45a8ff	2423	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
bogdanm	0:9b334a45a8ff	2424
bogdanm	0:9b334a45a8ff	2425	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
bogdanm	0:9b334a45a8ff	2426	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
bogdanm	0:9b334a45a8ff	2427
bogdanm	0:9b334a45a8ff	2428	/**
bogdanm	0:9b334a45a8ff	2429	* @}
bogdanm	0:9b334a45a8ff	2430	*/
bogdanm	0:9b334a45a8ff	2431
bogdanm	0:9b334a45a8ff	2432	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2433	* @{
bogdanm	0:9b334a45a8ff	2434	*/
bogdanm	0:9b334a45a8ff	2435
bogdanm	0:9b334a45a8ff	2436	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
bogdanm	0:9b334a45a8ff	2437	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
bogdanm	0:9b334a45a8ff	2438
bogdanm	0:9b334a45a8ff	2439	#if defined(STM32F4)
bogdanm	0:9b334a45a8ff	2440	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
bogdanm	0:9b334a45a8ff	2441	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
bogdanm	0:9b334a45a8ff	2442	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
bogdanm	0:9b334a45a8ff	2443	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
bogdanm	0:9b334a45a8ff	2444	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
bogdanm	0:9b334a45a8ff	2445	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
bogdanm	0:9b334a45a8ff	2446	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
bogdanm	0:9b334a45a8ff	2447	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
bogdanm	0:9b334a45a8ff	2448	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
bogdanm	0:9b334a45a8ff	2449	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
bogdanm	0:9b334a45a8ff	2450	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
bogdanm	0:9b334a45a8ff	2451	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
bogdanm	0:9b334a45a8ff	2452	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
bogdanm	0:9b334a45a8ff	2453	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
bogdanm	0:9b334a45a8ff	2454	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2455	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
bogdanm	0:9b334a45a8ff	2456	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
bogdanm	0:9b334a45a8ff	2457	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
bogdanm	0:9b334a45a8ff	2458	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
bogdanm	0:9b334a45a8ff	2459	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
bogdanm	0:9b334a45a8ff	2460	/* alias CMSIS */
bogdanm	0:9b334a45a8ff	2461	#define SDMMC1_IRQn SDIO_IRQn
bogdanm	0:9b334a45a8ff	2462	#define SDMMC1_IRQHandler SDIO_IRQHandler
bogdanm	0:9b334a45a8ff	2463	#endif
bogdanm	0:9b334a45a8ff	2464
bogdanm	0:9b334a45a8ff	2465	#if defined(STM32F7) \|\| defined(STM32L4)
bogdanm	0:9b334a45a8ff	2466	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
bogdanm	0:9b334a45a8ff	2467	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
bogdanm	0:9b334a45a8ff	2468	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
bogdanm	0:9b334a45a8ff	2469	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
bogdanm	0:9b334a45a8ff	2470	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
bogdanm	0:9b334a45a8ff	2471	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
bogdanm	0:9b334a45a8ff	2472	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
bogdanm	0:9b334a45a8ff	2473	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
bogdanm	0:9b334a45a8ff	2474	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
bogdanm	0:9b334a45a8ff	2475	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
bogdanm	0:9b334a45a8ff	2476	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
bogdanm	0:9b334a45a8ff	2477	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
bogdanm	0:9b334a45a8ff	2478	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
bogdanm	0:9b334a45a8ff	2479	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
bogdanm	0:9b334a45a8ff	2480	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2481	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
bogdanm	0:9b334a45a8ff	2482	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
bogdanm	0:9b334a45a8ff	2483	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
bogdanm	0:9b334a45a8ff	2484	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
bogdanm	0:9b334a45a8ff	2485	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
bogdanm	0:9b334a45a8ff	2486	/* alias CMSIS for compatibilities */
bogdanm	0:9b334a45a8ff	2487	#define SDIO_IRQn SDMMC1_IRQn
bogdanm	0:9b334a45a8ff	2488	#define SDIO_IRQHandler SDMMC1_IRQHandler
bogdanm	0:9b334a45a8ff	2489	#endif
bogdanm	0:9b334a45a8ff	2490	/**
bogdanm	0:9b334a45a8ff	2491	* @}
bogdanm	0:9b334a45a8ff	2492	*/
bogdanm	0:9b334a45a8ff	2493
bogdanm	0:9b334a45a8ff	2494	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2495	* @{
bogdanm	0:9b334a45a8ff	2496	*/
bogdanm	0:9b334a45a8ff	2497
bogdanm	0:9b334a45a8ff	2498	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
bogdanm	0:9b334a45a8ff	2499	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
bogdanm	0:9b334a45a8ff	2500	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
bogdanm	0:9b334a45a8ff	2501	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
bogdanm	0:9b334a45a8ff	2502	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
bogdanm	0:9b334a45a8ff	2503	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
bogdanm	0:9b334a45a8ff	2504
bogdanm	0:9b334a45a8ff	2505	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2506	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2507
bogdanm	0:9b334a45a8ff	2508	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	2509
bogdanm	0:9b334a45a8ff	2510	/**
bogdanm	0:9b334a45a8ff	2511	* @}
bogdanm	0:9b334a45a8ff	2512	*/
bogdanm	0:9b334a45a8ff	2513
bogdanm	0:9b334a45a8ff	2514	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2515	* @{
bogdanm	0:9b334a45a8ff	2516	*/
bogdanm	0:9b334a45a8ff	2517	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
bogdanm	0:9b334a45a8ff	2518	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
bogdanm	0:9b334a45a8ff	2519	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
bogdanm	0:9b334a45a8ff	2520	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
bogdanm	0:9b334a45a8ff	2521	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
bogdanm	0:9b334a45a8ff	2522	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
bogdanm	0:9b334a45a8ff	2523	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
bogdanm	0:9b334a45a8ff	2524	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
bogdanm	0:9b334a45a8ff	2525	/**
bogdanm	0:9b334a45a8ff	2526	* @}
bogdanm	0:9b334a45a8ff	2527	*/
bogdanm	0:9b334a45a8ff	2528
bogdanm	0:9b334a45a8ff	2529	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2530	* @{
bogdanm	0:9b334a45a8ff	2531	*/
bogdanm	0:9b334a45a8ff	2532
bogdanm	0:9b334a45a8ff	2533	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
bogdanm	0:9b334a45a8ff	2534	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
bogdanm	0:9b334a45a8ff	2535	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
bogdanm	0:9b334a45a8ff	2536
bogdanm	0:9b334a45a8ff	2537	/**
bogdanm	0:9b334a45a8ff	2538	* @}
bogdanm	0:9b334a45a8ff	2539	*/
bogdanm	0:9b334a45a8ff	2540
bogdanm	0:9b334a45a8ff	2541	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2542	* @{
bogdanm	0:9b334a45a8ff	2543	*/
bogdanm	0:9b334a45a8ff	2544
bogdanm	0:9b334a45a8ff	2545	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2546	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	2547	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2548	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	2549
bogdanm	0:9b334a45a8ff	2550	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
bogdanm	0:9b334a45a8ff	2551
bogdanm	0:9b334a45a8ff	2552	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	2553	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	2554
bogdanm	0:9b334a45a8ff	2555	/**
bogdanm	0:9b334a45a8ff	2556	* @}
bogdanm	0:9b334a45a8ff	2557	*/
bogdanm	0:9b334a45a8ff	2558
bogdanm	0:9b334a45a8ff	2559
bogdanm	0:9b334a45a8ff	2560	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2561	* @{
bogdanm	0:9b334a45a8ff	2562	*/
bogdanm	0:9b334a45a8ff	2563
bogdanm	0:9b334a45a8ff	2564	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
bogdanm	0:9b334a45a8ff	2565	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
bogdanm	0:9b334a45a8ff	2566	#define __USART_ENABLE __HAL_USART_ENABLE
bogdanm	0:9b334a45a8ff	2567	#define __USART_DISABLE __HAL_USART_DISABLE
bogdanm	0:9b334a45a8ff	2568
bogdanm	0:9b334a45a8ff	2569	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2570	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2571
bogdanm	0:9b334a45a8ff	2572	/**
bogdanm	0:9b334a45a8ff	2573	* @}
bogdanm	0:9b334a45a8ff	2574	*/
bogdanm	0:9b334a45a8ff	2575
bogdanm	0:9b334a45a8ff	2576	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2577	* @{
bogdanm	0:9b334a45a8ff	2578	*/
bogdanm	0:9b334a45a8ff	2579	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2580
bogdanm	0:9b334a45a8ff	2581	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
bogdanm	0:9b334a45a8ff	2582	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2583	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2584	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2585
bogdanm	0:9b334a45a8ff	2586	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
bogdanm	0:9b334a45a8ff	2587	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2588	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2589	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2590
bogdanm	0:9b334a45a8ff	2591	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2592	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2593	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2594	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2595	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	2596	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2597	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2598
bogdanm	0:9b334a45a8ff	2599	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2600	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2601	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2602	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2603	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	2604	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2605	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2606	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	2607
bogdanm	0:9b334a45a8ff	2608	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2609	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2610	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2611	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2612	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	2613	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2614	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2615	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	2616
bogdanm	0:9b334a45a8ff	2617	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
bogdanm	0:9b334a45a8ff	2618	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
bogdanm	0:9b334a45a8ff	2619
bogdanm	0:9b334a45a8ff	2620	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
bogdanm	0:9b334a45a8ff	2621	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
bogdanm	0:9b334a45a8ff	2622	/**
bogdanm	0:9b334a45a8ff	2623	* @}
bogdanm	0:9b334a45a8ff	2624	*/
bogdanm	0:9b334a45a8ff	2625
bogdanm	0:9b334a45a8ff	2626	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2627	* @{
bogdanm	0:9b334a45a8ff	2628	*/
bogdanm	0:9b334a45a8ff	2629	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
bogdanm	0:9b334a45a8ff	2630	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
bogdanm	0:9b334a45a8ff	2631
bogdanm	0:9b334a45a8ff	2632	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
bogdanm	0:9b334a45a8ff	2633	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
bogdanm	0:9b334a45a8ff	2634
bogdanm	0:9b334a45a8ff	2635	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
bogdanm	0:9b334a45a8ff	2636
bogdanm	0:9b334a45a8ff	2637	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
bogdanm	0:9b334a45a8ff	2638	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
bogdanm	0:9b334a45a8ff	2639	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
bogdanm	0:9b334a45a8ff	2640	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
bogdanm	0:9b334a45a8ff	2641	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
bogdanm	0:9b334a45a8ff	2642	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
bogdanm	0:9b334a45a8ff	2643	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
bogdanm	0:9b334a45a8ff	2644	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
bogdanm	0:9b334a45a8ff	2645	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
bogdanm	0:9b334a45a8ff	2646	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
bogdanm	0:9b334a45a8ff	2647	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
bogdanm	0:9b334a45a8ff	2648	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
bogdanm	0:9b334a45a8ff	2649
bogdanm	0:9b334a45a8ff	2650	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	2651	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	2652	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	0:9b334a45a8ff	2653	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	0:9b334a45a8ff	2654	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	2655	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	2656	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	2657	((SELECTION) == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	2658
bogdanm	0:9b334a45a8ff	2659	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	2660	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	2661	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	2662	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	2663
bogdanm	0:9b334a45a8ff	2664	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	2665	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	0:9b334a45a8ff	2666
bogdanm	0:9b334a45a8ff	2667	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	2668	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm	0:9b334a45a8ff	2669
bogdanm	0:9b334a45a8ff	2670	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	2671	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	0:9b334a45a8ff	2672
bogdanm	0:9b334a45a8ff	2673	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	2674	((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm	0:9b334a45a8ff	2675	/**
bogdanm	0:9b334a45a8ff	2676	* @}
bogdanm	0:9b334a45a8ff	2677	*/
bogdanm	0:9b334a45a8ff	2678
bogdanm	0:9b334a45a8ff	2679	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2680	* @{
bogdanm	0:9b334a45a8ff	2681	*/
bogdanm	0:9b334a45a8ff	2682
bogdanm	0:9b334a45a8ff	2683	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2684	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2685	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2686	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2687	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
bogdanm	0:9b334a45a8ff	2688	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
bogdanm	0:9b334a45a8ff	2689	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
bogdanm	0:9b334a45a8ff	2690
bogdanm	0:9b334a45a8ff	2691	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
bogdanm	0:9b334a45a8ff	2692	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
bogdanm	0:9b334a45a8ff	2693	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
bogdanm	0:9b334a45a8ff	2694	/**
bogdanm	0:9b334a45a8ff	2695	* @}
bogdanm	0:9b334a45a8ff	2696	*/
bogdanm	0:9b334a45a8ff	2697
bogdanm	0:9b334a45a8ff	2698	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2699	* @{
bogdanm	0:9b334a45a8ff	2700	*/
bogdanm	0:9b334a45a8ff	2701	#define __HAL_LTDC_LAYER LTDC_LAYER
bogdanm	0:9b334a45a8ff	2702	/**
bogdanm	0:9b334a45a8ff	2703	* @}
bogdanm	0:9b334a45a8ff	2704	*/
bogdanm	0:9b334a45a8ff	2705
bogdanm	0:9b334a45a8ff	2706	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2707	* @{
bogdanm	0:9b334a45a8ff	2708	*/
bogdanm	0:9b334a45a8ff	2709	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
bogdanm	0:9b334a45a8ff	2710	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
bogdanm	0:9b334a45a8ff	2711	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
bogdanm	0:9b334a45a8ff	2712	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
bogdanm	0:9b334a45a8ff	2713	#define SAI_STREOMODE SAI_STEREOMODE
bogdanm	0:9b334a45a8ff	2714	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
bogdanm	0:9b334a45a8ff	2715	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
bogdanm	0:9b334a45a8ff	2716	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
bogdanm	0:9b334a45a8ff	2717	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
bogdanm	0:9b334a45a8ff	2718	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
bogdanm	0:9b334a45a8ff	2719	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
bogdanm	0:9b334a45a8ff	2720	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
bogdanm	0:9b334a45a8ff	2721
bogdanm	0:9b334a45a8ff	2722	/**
bogdanm	0:9b334a45a8ff	2723	* @}
bogdanm	0:9b334a45a8ff	2724	*/
bogdanm	0:9b334a45a8ff	2725
bogdanm	0:9b334a45a8ff	2726
bogdanm	0:9b334a45a8ff	2727	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2728	* @{
bogdanm	0:9b334a45a8ff	2729	*/
bogdanm	0:9b334a45a8ff	2730
bogdanm	0:9b334a45a8ff	2731	/**
bogdanm	0:9b334a45a8ff	2732	* @}
bogdanm	0:9b334a45a8ff	2733	*/
bogdanm	0:9b334a45a8ff	2734
bogdanm	0:9b334a45a8ff	2735	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	2736	}
bogdanm	0:9b334a45a8ff	2737	#endif
bogdanm	0:9b334a45a8ff	2738
bogdanm	0:9b334a45a8ff	2739	#endif /* ___STM32_HAL_LEGACY */
bogdanm	0:9b334a45a8ff	2740
bogdanm	0:9b334a45a8ff	2741	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	2742

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h@19:112740acecfa, 2015-11-10 (annotated)

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