mattia griotti
Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial
Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed
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stm32f4xx_rcc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_rcc.h 00004 * @author MCD Application Team 00005 * @version V1.0.0 00006 * @date 30-September-2011 00007 * @brief This file contains all the functions prototypes for the RCC firmware library. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00012 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00013 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00014 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00015 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00016 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00017 * 00018 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00019 ****************************************************************************** 00020 */ 00021 00022 /* Define to prevent recursive inclusion -------------------------------------*/ 00023 #ifndef __STM32F4xx_RCC_H 00024 #define __STM32F4xx_RCC_H 00025 00026 #ifdef __cplusplus 00027 extern "C" { 00028 #endif 00029 00030 /* Includes ------------------------------------------------------------------*/ 00031 #include "stm32f4xx.h" 00032 00033 /** @addtogroup STM32F4xx_StdPeriph_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup RCC 00038 * @{ 00039 */ 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 typedef struct 00043 { 00044 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ 00045 uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ 00046 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ 00047 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ 00048 }RCC_ClocksTypeDef; 00049 00050 /* Exported constants --------------------------------------------------------*/ 00051 00052 /** @defgroup RCC_Exported_Constants 00053 * @{ 00054 */ 00055 00056 /** @defgroup RCC_HSE_configuration 00057 * @{ 00058 */ 00059 #define RCC_HSE_OFF ((uint8_t)0x00) 00060 #define RCC_HSE_ON ((uint8_t)0x01) 00061 #define RCC_HSE_Bypass ((uint8_t)0x05) 00062 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 00063 ((HSE) == RCC_HSE_Bypass)) 00064 /** 00065 * @} 00066 */ 00067 00068 /** @defgroup RCC_PLL_Clock_Source 00069 * @{ 00070 */ 00071 #define RCC_PLLSource_HSI ((uint32_t)0x00000000) 00072 #define RCC_PLLSource_HSE ((uint32_t)0x00400000) 00073 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ 00074 ((SOURCE) == RCC_PLLSource_HSE)) 00075 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) 00076 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) 00077 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 00078 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) 00079 00080 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) 00081 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 00082 /** 00083 * @} 00084 */ 00085 00086 /** @defgroup RCC_System_Clock_Source 00087 * @{ 00088 */ 00089 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 00090 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 00091 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 00092 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 00093 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 00094 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 00095 /** 00096 * @} 00097 */ 00098 00099 /** @defgroup RCC_AHB_Clock_Source 00100 * @{ 00101 */ 00102 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 00103 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 00104 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 00105 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 00106 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 00107 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 00108 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 00109 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 00110 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 00111 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 00112 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 00113 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 00114 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 00115 ((HCLK) == RCC_SYSCLK_Div512)) 00116 /** 00117 * @} 00118 */ 00119 00120 /** @defgroup RCC_APB1_APB2_Clock_Source 00121 * @{ 00122 */ 00123 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 00124 #define RCC_HCLK_Div2 ((uint32_t)0x00001000) 00125 #define RCC_HCLK_Div4 ((uint32_t)0x00001400) 00126 #define RCC_HCLK_Div8 ((uint32_t)0x00001800) 00127 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) 00128 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 00129 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 00130 ((PCLK) == RCC_HCLK_Div16)) 00131 /** 00132 * @} 00133 */ 00134 00135 /** @defgroup RCC_Interrupt_Source 00136 * @{ 00137 */ 00138 #define RCC_IT_LSIRDY ((uint8_t)0x01) 00139 #define RCC_IT_LSERDY ((uint8_t)0x02) 00140 #define RCC_IT_HSIRDY ((uint8_t)0x04) 00141 #define RCC_IT_HSERDY ((uint8_t)0x08) 00142 #define RCC_IT_PLLRDY ((uint8_t)0x10) 00143 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 00144 #define RCC_IT_CSS ((uint8_t)0x80) 00145 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) 00146 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 00147 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 00148 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ 00149 ((IT) == RCC_IT_PLLI2SRDY)) 00150 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) 00151 /** 00152 * @} 00153 */ 00154 00155 /** @defgroup RCC_LSE_Configuration 00156 * @{ 00157 */ 00158 #define RCC_LSE_OFF ((uint8_t)0x00) 00159 #define RCC_LSE_ON ((uint8_t)0x01) 00160 #define RCC_LSE_Bypass ((uint8_t)0x04) 00161 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 00162 ((LSE) == RCC_LSE_Bypass)) 00163 /** 00164 * @} 00165 */ 00166 00167 /** @defgroup RCC_RTC_Clock_Source 00168 * @{ 00169 */ 00170 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 00171 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 00172 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) 00173 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) 00174 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) 00175 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) 00176 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) 00177 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) 00178 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) 00179 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) 00180 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) 00181 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) 00182 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) 00183 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) 00184 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) 00185 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) 00186 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) 00187 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) 00188 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) 00189 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) 00190 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) 00191 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) 00192 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) 00193 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) 00194 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) 00195 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) 00196 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) 00197 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) 00198 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) 00199 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) 00200 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) 00201 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) 00202 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 00203 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 00204 ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ 00205 ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ 00206 ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ 00207 ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ 00208 ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ 00209 ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ 00210 ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ 00211 ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ 00212 ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ 00213 ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ 00214 ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ 00215 ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ 00216 ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ 00217 ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ 00218 ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ 00219 ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ 00220 ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ 00221 ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ 00222 ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ 00223 ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ 00224 ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ 00225 ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ 00226 ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ 00227 ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ 00228 ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ 00229 ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ 00230 ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ 00231 ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ 00232 ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ 00233 ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) 00234 /** 00235 * @} 00236 */ 00237 00238 /** @defgroup RCC_I2S_Clock_Source 00239 * @{ 00240 */ 00241 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) 00242 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) 00243 00244 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) 00245 /** 00246 * @} 00247 */ 00248 00249 /** @defgroup RCC_AHB1_Peripherals 00250 * @{ 00251 */ 00252 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) 00253 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) 00254 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) 00255 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) 00256 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) 00257 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) 00258 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) 00259 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) 00260 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) 00261 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) 00262 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) 00263 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) 00264 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) 00265 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) 00266 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) 00267 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) 00268 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) 00269 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) 00270 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) 00271 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) 00272 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) 00273 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) 00274 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) 00275 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00)) 00276 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) 00277 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) 00278 /** 00279 * @} 00280 */ 00281 00282 /** @defgroup RCC_AHB2_Peripherals 00283 * @{ 00284 */ 00285 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) 00286 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) 00287 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) 00288 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) 00289 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) 00290 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) 00291 /** 00292 * @} 00293 */ 00294 00295 /** @defgroup RCC_AHB3_Peripherals 00296 * @{ 00297 */ 00298 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) 00299 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 00300 /** 00301 * @} 00302 */ 00303 00304 /** @defgroup RCC_APB1_Peripherals 00305 * @{ 00306 */ 00307 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 00308 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 00309 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 00310 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 00311 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 00312 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 00313 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) 00314 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) 00315 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) 00316 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 00317 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 00318 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 00319 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 00320 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 00321 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 00322 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 00323 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 00324 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 00325 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) 00326 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 00327 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) 00328 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 00329 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 00330 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) 00331 /** 00332 * @} 00333 */ 00334 00335 /** @defgroup RCC_APB2_Peripherals 00336 * @{ 00337 */ 00338 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) 00339 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) 00340 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) 00341 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) 00342 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) 00343 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) 00344 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) 00345 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) 00346 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) 00347 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 00348 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) 00349 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) 00350 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) 00351 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) 00352 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) 00353 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup RCC_MCO1_Clock_Source_Prescaler 00359 * @{ 00360 */ 00361 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) 00362 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) 00363 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) 00364 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) 00365 #define RCC_MCO1Div_1 ((uint32_t)0x00000000) 00366 #define RCC_MCO1Div_2 ((uint32_t)0x04000000) 00367 #define RCC_MCO1Div_3 ((uint32_t)0x05000000) 00368 #define RCC_MCO1Div_4 ((uint32_t)0x06000000) 00369 #define RCC_MCO1Div_5 ((uint32_t)0x07000000) 00370 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ 00371 ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) 00372 00373 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ 00374 ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ 00375 ((DIV) == RCC_MCO1Div_5)) 00376 /** 00377 * @} 00378 */ 00379 00380 /** @defgroup RCC_MCO2_Clock_Source_Prescaler 00381 * @{ 00382 */ 00383 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) 00384 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) 00385 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) 00386 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) 00387 #define RCC_MCO2Div_1 ((uint32_t)0x00000000) 00388 #define RCC_MCO2Div_2 ((uint32_t)0x20000000) 00389 #define RCC_MCO2Div_3 ((uint32_t)0x28000000) 00390 #define RCC_MCO2Div_4 ((uint32_t)0x30000000) 00391 #define RCC_MCO2Div_5 ((uint32_t)0x38000000) 00392 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ 00393 ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) 00394 00395 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ 00396 ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ 00397 ((DIV) == RCC_MCO2Div_5)) 00398 /** 00399 * @} 00400 */ 00401 00402 /** @defgroup RCC_Flag 00403 * @{ 00404 */ 00405 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 00406 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 00407 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 00408 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 00409 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 00410 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 00411 #define RCC_FLAG_BORRST ((uint8_t)0x79) 00412 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 00413 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 00414 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 00415 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 00416 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 00417 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 00418 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 00419 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 00420 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ 00421 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 00422 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ 00423 ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ 00424 ((FLAG) == RCC_FLAG_PLLI2SRDY)) 00425 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 00426 /** 00427 * @} 00428 */ 00429 00430 /** 00431 * @} 00432 */ 00433 00434 /* Exported macro ------------------------------------------------------------*/ 00435 /* Exported functions --------------------------------------------------------*/ 00436 00437 /* Function used to set the RCC clock configuration to the default reset state */ 00438 void RCC_DeInit(void); 00439 00440 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ 00441 void RCC_HSEConfig(uint8_t RCC_HSE); 00442 ErrorStatus RCC_WaitForHSEStartUp(void); 00443 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 00444 void RCC_HSICmd(FunctionalState NewState); 00445 void RCC_LSEConfig(uint8_t RCC_LSE); 00446 void RCC_LSICmd(FunctionalState NewState); 00447 00448 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); 00449 void RCC_PLLCmd(FunctionalState NewState); 00450 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); 00451 void RCC_PLLI2SCmd(FunctionalState NewState); 00452 00453 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 00454 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); 00455 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); 00456 00457 /* System, AHB and APB busses clocks configuration functions ******************/ 00458 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 00459 uint8_t RCC_GetSYSCLKSource(void); 00460 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 00461 void RCC_PCLK1Config(uint32_t RCC_HCLK); 00462 void RCC_PCLK2Config(uint32_t RCC_HCLK); 00463 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 00464 00465 /* Peripheral clocks configuration functions **********************************/ 00466 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 00467 void RCC_RTCCLKCmd(FunctionalState NewState); 00468 void RCC_BackupResetCmd(FunctionalState NewState); 00469 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 00470 00471 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 00472 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 00473 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 00474 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 00475 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 00476 00477 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 00478 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 00479 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 00480 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 00481 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 00482 00483 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 00484 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 00485 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 00486 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 00487 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 00488 00489 /* Interrupts and flags management functions **********************************/ 00490 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 00491 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 00492 void RCC_ClearFlag(void); 00493 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 00494 void RCC_ClearITPendingBit(uint8_t RCC_IT); 00495 00496 #ifdef __cplusplus 00497 } 00498 #endif 00499 00500 #endif /* __STM32F4xx_RCC_H */ 00501 00502 /** 00503 * @} 00504 */ 00505 00506 /** 00507 * @} 00508 */ 00509 00510 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 00511
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