HelloWorld_IKS01A1 - Simple "hello world" style program for X-NUCLEO-I…

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mattia griotti / Mbed 2 deprecated HelloWorld_IKS01A1

Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial

Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed

stm32f4xx.h@8:1c6281289d67, 2015-11-15 (annotated)

Committer:: n0tform3
Date:: Sun Nov 15 09:00:40 2015 +0000
Revision:: 8:1c6281289d67

test with led

Who changed what in which revision?

User	Revision	Line number	New contents of line
n0tform3	8:1c6281289d67	1	/**
n0tform3	8:1c6281289d67	2	******************************************************************************
n0tform3	8:1c6281289d67	3	* @file stm32f4xx.h
n0tform3	8:1c6281289d67	4	* @author MCD Application Team
n0tform3	8:1c6281289d67	5	* @version V1.0.0
n0tform3	8:1c6281289d67	6	* @date 30-September-2011
n0tform3	8:1c6281289d67	7	* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
n0tform3	8:1c6281289d67	8	* This file contains all the peripheral register's definitions, bits
n0tform3	8:1c6281289d67	9	* definitions and memory mapping for STM32F4xx devices.
n0tform3	8:1c6281289d67	10	*
n0tform3	8:1c6281289d67	11	* The file is the unique include file that the application programmer
n0tform3	8:1c6281289d67	12	* is using in the C source code, usually in main.c. This file contains:
n0tform3	8:1c6281289d67	13	* - Configuration section that allows to select:
n0tform3	8:1c6281289d67	14	* - The device used in the target application
n0tform3	8:1c6281289d67	15	* - To use or not the peripherals drivers in application code(i.e.
n0tform3	8:1c6281289d67	16	* code will be based on direct access to peripherals registers
n0tform3	8:1c6281289d67	17	* rather than drivers API), this option is controlled by
n0tform3	8:1c6281289d67	18	* "#define USE_STDPERIPH_DRIVER"
n0tform3	8:1c6281289d67	19	* - To change few application-specific parameters such as the HSE
n0tform3	8:1c6281289d67	20	* crystal frequency
n0tform3	8:1c6281289d67	21	* - Data structures and the address mapping for all peripherals
n0tform3	8:1c6281289d67	22	* - Peripheral's registers declarations and bits definition
n0tform3	8:1c6281289d67	23	* - Macros to access peripherals registers hardware
n0tform3	8:1c6281289d67	24	*
n0tform3	8:1c6281289d67	25	******************************************************************************
n0tform3	8:1c6281289d67	26	* @attention
n0tform3	8:1c6281289d67	27	*
n0tform3	8:1c6281289d67	28	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
n0tform3	8:1c6281289d67	29	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
n0tform3	8:1c6281289d67	30	* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
n0tform3	8:1c6281289d67	31	* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
n0tform3	8:1c6281289d67	32	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
n0tform3	8:1c6281289d67	33	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
n0tform3	8:1c6281289d67	34	*
n0tform3	8:1c6281289d67	35	* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
n0tform3	8:1c6281289d67	36	******************************************************************************
n0tform3	8:1c6281289d67	37	*/
n0tform3	8:1c6281289d67	38
n0tform3	8:1c6281289d67	39	/** @addtogroup CMSIS
n0tform3	8:1c6281289d67	40	* @{
n0tform3	8:1c6281289d67	41	*/
n0tform3	8:1c6281289d67	42
n0tform3	8:1c6281289d67	43	/** @addtogroup stm32f4xx
n0tform3	8:1c6281289d67	44	* @{
n0tform3	8:1c6281289d67	45	*/
n0tform3	8:1c6281289d67	46
n0tform3	8:1c6281289d67	47	#ifndef __STM32F4xx_H
n0tform3	8:1c6281289d67	48	#define __STM32F4xx_H
n0tform3	8:1c6281289d67	49
n0tform3	8:1c6281289d67	50	#ifdef __cplusplus
n0tform3	8:1c6281289d67	51	extern "C" {
n0tform3	8:1c6281289d67	52	#endif /* __cplusplus */
n0tform3	8:1c6281289d67	53
n0tform3	8:1c6281289d67	54	/** @addtogroup Library_configuration_section
n0tform3	8:1c6281289d67	55	* @{
n0tform3	8:1c6281289d67	56	*/
n0tform3	8:1c6281289d67	57
n0tform3	8:1c6281289d67	58	/* Uncomment the line below according to the target STM32 device used in your
n0tform3	8:1c6281289d67	59	application
n0tform3	8:1c6281289d67	60	*/
n0tform3	8:1c6281289d67	61
n0tform3	8:1c6281289d67	62	#if !defined (STM32F4XX)
n0tform3	8:1c6281289d67	63	#define STM32F4XX
n0tform3	8:1c6281289d67	64	#endif
n0tform3	8:1c6281289d67	65
n0tform3	8:1c6281289d67	66	/* Tip: To avoid modifying this file each time you need to switch between these
n0tform3	8:1c6281289d67	67	devices, you can define the device in your toolchain compiler preprocessor.
n0tform3	8:1c6281289d67	68	*/
n0tform3	8:1c6281289d67	69
n0tform3	8:1c6281289d67	70	#if !defined (STM32F4XX)
n0tform3	8:1c6281289d67	71	#error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)"
n0tform3	8:1c6281289d67	72	#endif
n0tform3	8:1c6281289d67	73
n0tform3	8:1c6281289d67	74	#if !defined (USE_STDPERIPH_DRIVER)
n0tform3	8:1c6281289d67	75	/**
n0tform3	8:1c6281289d67	76	* @brief Comment the line below if you will not use the peripherals drivers.
n0tform3	8:1c6281289d67	77	In this case, these drivers will not be included and the application code will
n0tform3	8:1c6281289d67	78	be based on direct access to peripherals registers
n0tform3	8:1c6281289d67	79	*/
n0tform3	8:1c6281289d67	80	/#define USE_STDPERIPH_DRIVER/
n0tform3	8:1c6281289d67	81	#endif /* USE_STDPERIPH_DRIVER */
n0tform3	8:1c6281289d67	82
n0tform3	8:1c6281289d67	83	/**
n0tform3	8:1c6281289d67	84	* @brief In the following line adjust the value of External High Speed oscillator (HSE)
n0tform3	8:1c6281289d67	85	used in your application
n0tform3	8:1c6281289d67	86
n0tform3	8:1c6281289d67	87	Tip: To avoid modifying this file each time you need to use different HSE, you
n0tform3	8:1c6281289d67	88	can define the HSE value in your toolchain compiler preprocessor.
n0tform3	8:1c6281289d67	89	*/
n0tform3	8:1c6281289d67	90
n0tform3	8:1c6281289d67	91	#if !defined (HSE_VALUE)
n0tform3	8:1c6281289d67	92	#define HSE_VALUE ((uint32_t)25000000) /!< Value of the External oscillator in Hz /
n0tform3	8:1c6281289d67	93	#endif /* HSE_VALUE */
n0tform3	8:1c6281289d67	94
n0tform3	8:1c6281289d67	95	/**
n0tform3	8:1c6281289d67	96	* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
n0tform3	8:1c6281289d67	97	Timeout value
n0tform3	8:1c6281289d67	98	*/
n0tform3	8:1c6281289d67	99	#if !defined (HSE_STARTUP_TIMEOUT)
n0tform3	8:1c6281289d67	100	#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /!< Time out for HSE start up /
n0tform3	8:1c6281289d67	101	#endif /* HSE_STARTUP_TIMEOUT */
n0tform3	8:1c6281289d67	102
n0tform3	8:1c6281289d67	103	#if !defined (HSI_VALUE)
n0tform3	8:1c6281289d67	104	#define HSI_VALUE ((uint32_t)16000000) /!< Value of the Internal oscillator in Hz/
n0tform3	8:1c6281289d67	105	#endif /* HSI_VALUE */
n0tform3	8:1c6281289d67	106
n0tform3	8:1c6281289d67	107	/**
n0tform3	8:1c6281289d67	108	* @brief STM32F4XX Standard Peripherals Library version number V1.0.0
n0tform3	8:1c6281289d67	109	*/
n0tform3	8:1c6281289d67	110	#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /!< [31:24] main version /
n0tform3	8:1c6281289d67	111	#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /!< [23:16] sub1 version /
n0tform3	8:1c6281289d67	112	#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /!< [15:8] sub2 version /
n0tform3	8:1c6281289d67	113	#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /!< [7:0] release candidate /
n0tform3	8:1c6281289d67	114	#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
n0tform3	8:1c6281289d67	115	\|(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
n0tform3	8:1c6281289d67	116	\|(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
n0tform3	8:1c6281289d67	117	\|(__STM32F4XX_STDPERIPH_VERSION_RC))
n0tform3	8:1c6281289d67	118
n0tform3	8:1c6281289d67	119	/**
n0tform3	8:1c6281289d67	120	* @}
n0tform3	8:1c6281289d67	121	*/
n0tform3	8:1c6281289d67	122
n0tform3	8:1c6281289d67	123	/** @addtogroup Configuration_section_for_CMSIS
n0tform3	8:1c6281289d67	124	* @{
n0tform3	8:1c6281289d67	125	*/
n0tform3	8:1c6281289d67	126
n0tform3	8:1c6281289d67	127	/**
n0tform3	8:1c6281289d67	128	* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
n0tform3	8:1c6281289d67	129	*/
n0tform3	8:1c6281289d67	130	#define __CM4_REV 0x0001 /!< Core revision r0p1 /
n0tform3	8:1c6281289d67	131	#define __MPU_PRESENT 1 /!< STM32F4XX provides an MPU /
n0tform3	8:1c6281289d67	132	#define __NVIC_PRIO_BITS 4 /!< STM32F4XX uses 4 Bits for the Priority Levels /
n0tform3	8:1c6281289d67	133	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
n0tform3	8:1c6281289d67	134	#define __FPU_PRESENT 1 /!< FPU present /
n0tform3	8:1c6281289d67	135
n0tform3	8:1c6281289d67	136	/**
n0tform3	8:1c6281289d67	137	* @brief STM32F4XX Interrupt Number Definition, according to the selected device
n0tform3	8:1c6281289d67	138	* in @ref Library_configuration_section
n0tform3	8:1c6281289d67	139	*/
n0tform3	8:1c6281289d67	140	typedef enum IRQn
n0tform3	8:1c6281289d67	141	{
n0tform3	8:1c6281289d67	142	/**** Cortex-M4 Processor Exceptions Numbers **************************************************************/
n0tform3	8:1c6281289d67	143	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
n0tform3	8:1c6281289d67	144	MemoryManagement_IRQn = -12, /!< 4 Cortex-M4 Memory Management Interrupt /
n0tform3	8:1c6281289d67	145	BusFault_IRQn = -11, /!< 5 Cortex-M4 Bus Fault Interrupt /
n0tform3	8:1c6281289d67	146	UsageFault_IRQn = -10, /!< 6 Cortex-M4 Usage Fault Interrupt /
n0tform3	8:1c6281289d67	147	SVCall_IRQn = -5, /!< 11 Cortex-M4 SV Call Interrupt /
n0tform3	8:1c6281289d67	148	DebugMonitor_IRQn = -4, /!< 12 Cortex-M4 Debug Monitor Interrupt /
n0tform3	8:1c6281289d67	149	PendSV_IRQn = -2, /!< 14 Cortex-M4 Pend SV Interrupt /
n0tform3	8:1c6281289d67	150	SysTick_IRQn = -1, /!< 15 Cortex-M4 System Tick Interrupt /
n0tform3	8:1c6281289d67	151	/**** STM32 specific Interrupt Numbers ********************************************************************/
n0tform3	8:1c6281289d67	152	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
n0tform3	8:1c6281289d67	153	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
n0tform3	8:1c6281289d67	154	TAMP_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
n0tform3	8:1c6281289d67	155	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI line /
n0tform3	8:1c6281289d67	156	FLASH_IRQn = 4, /!< FLASH global Interrupt /
n0tform3	8:1c6281289d67	157	RCC_IRQn = 5, /!< RCC global Interrupt /
n0tform3	8:1c6281289d67	158	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
n0tform3	8:1c6281289d67	159	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
n0tform3	8:1c6281289d67	160	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
n0tform3	8:1c6281289d67	161	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
n0tform3	8:1c6281289d67	162	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
n0tform3	8:1c6281289d67	163	DMA1_Stream0_IRQn = 11, /!< DMA1 Stream 0 global Interrupt /
n0tform3	8:1c6281289d67	164	DMA1_Stream1_IRQn = 12, /!< DMA1 Stream 1 global Interrupt /
n0tform3	8:1c6281289d67	165	DMA1_Stream2_IRQn = 13, /!< DMA1 Stream 2 global Interrupt /
n0tform3	8:1c6281289d67	166	DMA1_Stream3_IRQn = 14, /!< DMA1 Stream 3 global Interrupt /
n0tform3	8:1c6281289d67	167	DMA1_Stream4_IRQn = 15, /!< DMA1 Stream 4 global Interrupt /
n0tform3	8:1c6281289d67	168	DMA1_Stream5_IRQn = 16, /!< DMA1 Stream 5 global Interrupt /
n0tform3	8:1c6281289d67	169	DMA1_Stream6_IRQn = 17, /!< DMA1 Stream 6 global Interrupt /
n0tform3	8:1c6281289d67	170	ADC_IRQn = 18, /!< ADC1, ADC2 and ADC3 global Interrupts /
n0tform3	8:1c6281289d67	171	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupt /
n0tform3	8:1c6281289d67	172	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupt /
n0tform3	8:1c6281289d67	173	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
n0tform3	8:1c6281289d67	174	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
n0tform3	8:1c6281289d67	175	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
n0tform3	8:1c6281289d67	176	TIM1_BRK_TIM9_IRQn = 24, /!< TIM1 Break interrupt and TIM9 global interrupt /
n0tform3	8:1c6281289d67	177	TIM1_UP_TIM10_IRQn = 25, /!< TIM1 Update Interrupt and TIM10 global interrupt /
n0tform3	8:1c6281289d67	178	TIM1_TRG_COM_TIM11_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt /
n0tform3	8:1c6281289d67	179	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
n0tform3	8:1c6281289d67	180	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
n0tform3	8:1c6281289d67	181	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
n0tform3	8:1c6281289d67	182	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
n0tform3	8:1c6281289d67	183	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
n0tform3	8:1c6281289d67	184	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
n0tform3	8:1c6281289d67	185	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
n0tform3	8:1c6281289d67	186	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
n0tform3	8:1c6281289d67	187	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
n0tform3	8:1c6281289d67	188	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
n0tform3	8:1c6281289d67	189	USART1_IRQn = 37, /!< USART1 global Interrupt /
n0tform3	8:1c6281289d67	190	USART2_IRQn = 38, /!< USART2 global Interrupt /
n0tform3	8:1c6281289d67	191	USART3_IRQn = 39, /!< USART3 global Interrupt /
n0tform3	8:1c6281289d67	192	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
n0tform3	8:1c6281289d67	193	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
n0tform3	8:1c6281289d67	194	OTG_FS_WKUP_IRQn = 42, /!< USB OTG FS Wakeup through EXTI line interrupt /
n0tform3	8:1c6281289d67	195	TIM8_BRK_TIM12_IRQn = 43, /!< TIM8 Break Interrupt and TIM12 global interrupt /
n0tform3	8:1c6281289d67	196	TIM8_UP_TIM13_IRQn = 44, /!< TIM8 Update Interrupt and TIM13 global interrupt /
n0tform3	8:1c6281289d67	197	TIM8_TRG_COM_TIM14_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt /
n0tform3	8:1c6281289d67	198	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
n0tform3	8:1c6281289d67	199	DMA1_Stream7_IRQn = 47, /!< DMA1 Stream7 Interrupt /
n0tform3	8:1c6281289d67	200	FSMC_IRQn = 48, /!< FSMC global Interrupt /
n0tform3	8:1c6281289d67	201	SDIO_IRQn = 49, /!< SDIO global Interrupt /
n0tform3	8:1c6281289d67	202	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
n0tform3	8:1c6281289d67	203	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
n0tform3	8:1c6281289d67	204	UART4_IRQn = 52, /!< UART4 global Interrupt /
n0tform3	8:1c6281289d67	205	UART5_IRQn = 53, /!< UART5 global Interrupt /
n0tform3	8:1c6281289d67	206	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
n0tform3	8:1c6281289d67	207	TIM7_IRQn = 55, /!< TIM7 global interrupt /
n0tform3	8:1c6281289d67	208	DMA2_Stream0_IRQn = 56, /!< DMA2 Stream 0 global Interrupt /
n0tform3	8:1c6281289d67	209	DMA2_Stream1_IRQn = 57, /!< DMA2 Stream 1 global Interrupt /
n0tform3	8:1c6281289d67	210	DMA2_Stream2_IRQn = 58, /!< DMA2 Stream 2 global Interrupt /
n0tform3	8:1c6281289d67	211	DMA2_Stream3_IRQn = 59, /!< DMA2 Stream 3 global Interrupt /
n0tform3	8:1c6281289d67	212	DMA2_Stream4_IRQn = 60, /!< DMA2 Stream 4 global Interrupt /
n0tform3	8:1c6281289d67	213	ETH_IRQn = 61, /!< Ethernet global Interrupt /
n0tform3	8:1c6281289d67	214	ETH_WKUP_IRQn = 62, /!< Ethernet Wakeup through EXTI line Interrupt /
n0tform3	8:1c6281289d67	215	CAN2_TX_IRQn = 63, /!< CAN2 TX Interrupt /
n0tform3	8:1c6281289d67	216	CAN2_RX0_IRQn = 64, /!< CAN2 RX0 Interrupt /
n0tform3	8:1c6281289d67	217	CAN2_RX1_IRQn = 65, /!< CAN2 RX1 Interrupt /
n0tform3	8:1c6281289d67	218	CAN2_SCE_IRQn = 66, /!< CAN2 SCE Interrupt /
n0tform3	8:1c6281289d67	219	OTG_FS_IRQn = 67, /!< USB OTG FS global Interrupt /
n0tform3	8:1c6281289d67	220	DMA2_Stream5_IRQn = 68, /!< DMA2 Stream 5 global interrupt /
n0tform3	8:1c6281289d67	221	DMA2_Stream6_IRQn = 69, /!< DMA2 Stream 6 global interrupt /
n0tform3	8:1c6281289d67	222	DMA2_Stream7_IRQn = 70, /!< DMA2 Stream 7 global interrupt /
n0tform3	8:1c6281289d67	223	USART6_IRQn = 71, /!< USART6 global interrupt /
n0tform3	8:1c6281289d67	224	I2C3_EV_IRQn = 72, /!< I2C3 event interrupt /
n0tform3	8:1c6281289d67	225	I2C3_ER_IRQn = 73, /!< I2C3 error interrupt /
n0tform3	8:1c6281289d67	226	OTG_HS_EP1_OUT_IRQn = 74, /!< USB OTG HS End Point 1 Out global interrupt /
n0tform3	8:1c6281289d67	227	OTG_HS_EP1_IN_IRQn = 75, /!< USB OTG HS End Point 1 In global interrupt /
n0tform3	8:1c6281289d67	228	OTG_HS_WKUP_IRQn = 76, /!< USB OTG HS Wakeup through EXTI interrupt /
n0tform3	8:1c6281289d67	229	OTG_HS_IRQn = 77, /!< USB OTG HS global interrupt /
n0tform3	8:1c6281289d67	230	DCMI_IRQn = 78, /!< DCMI global interrupt /
n0tform3	8:1c6281289d67	231	CRYP_IRQn = 79, /!< CRYP crypto global interrupt /
n0tform3	8:1c6281289d67	232	HASH_RNG_IRQn = 80, /!< Hash and Rng global interrupt /
n0tform3	8:1c6281289d67	233	FPU_IRQn = 81 /!< FPU global interrupt /
n0tform3	8:1c6281289d67	234	} IRQn_Type;
n0tform3	8:1c6281289d67	235
n0tform3	8:1c6281289d67	236	/**
n0tform3	8:1c6281289d67	237	* @}
n0tform3	8:1c6281289d67	238	*/
n0tform3	8:1c6281289d67	239
n0tform3	8:1c6281289d67	240	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
n0tform3	8:1c6281289d67	241	#include "system_stm32f4xx.h"
n0tform3	8:1c6281289d67	242	#include <stdint.h>
n0tform3	8:1c6281289d67	243
n0tform3	8:1c6281289d67	244	/** @addtogroup Exported_types
n0tform3	8:1c6281289d67	245	* @{
n0tform3	8:1c6281289d67	246	*/
n0tform3	8:1c6281289d67	247	/!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) /
n0tform3	8:1c6281289d67	248	typedef int32_t s32;
n0tform3	8:1c6281289d67	249	typedef int16_t s16;
n0tform3	8:1c6281289d67	250	typedef int8_t s8;
n0tform3	8:1c6281289d67	251
n0tform3	8:1c6281289d67	252	typedef const int32_t sc32; /!< Read Only /
n0tform3	8:1c6281289d67	253	typedef const int16_t sc16; /!< Read Only /
n0tform3	8:1c6281289d67	254	typedef const int8_t sc8; /!< Read Only /
n0tform3	8:1c6281289d67	255
n0tform3	8:1c6281289d67	256	typedef __IO int32_t vs32;
n0tform3	8:1c6281289d67	257	typedef __IO int16_t vs16;
n0tform3	8:1c6281289d67	258	typedef __IO int8_t vs8;
n0tform3	8:1c6281289d67	259
n0tform3	8:1c6281289d67	260	typedef __I int32_t vsc32; /!< Read Only /
n0tform3	8:1c6281289d67	261	typedef __I int16_t vsc16; /!< Read Only /
n0tform3	8:1c6281289d67	262	typedef __I int8_t vsc8; /!< Read Only /
n0tform3	8:1c6281289d67	263
n0tform3	8:1c6281289d67	264	typedef uint32_t u32;
n0tform3	8:1c6281289d67	265	typedef uint16_t u16;
n0tform3	8:1c6281289d67	266	typedef uint8_t u8;
n0tform3	8:1c6281289d67	267
n0tform3	8:1c6281289d67	268	typedef const uint32_t uc32; /!< Read Only /
n0tform3	8:1c6281289d67	269	typedef const uint16_t uc16; /!< Read Only /
n0tform3	8:1c6281289d67	270	typedef const uint8_t uc8; /!< Read Only /
n0tform3	8:1c6281289d67	271
n0tform3	8:1c6281289d67	272	typedef __IO uint32_t vu32;
n0tform3	8:1c6281289d67	273	typedef __IO uint16_t vu16;
n0tform3	8:1c6281289d67	274	typedef __IO uint8_t vu8;
n0tform3	8:1c6281289d67	275
n0tform3	8:1c6281289d67	276	typedef __I uint32_t vuc32; /!< Read Only /
n0tform3	8:1c6281289d67	277	typedef __I uint16_t vuc16; /!< Read Only /
n0tform3	8:1c6281289d67	278	typedef __I uint8_t vuc8; /!< Read Only /
n0tform3	8:1c6281289d67	279
n0tform3	8:1c6281289d67	280	typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
n0tform3	8:1c6281289d67	281
n0tform3	8:1c6281289d67	282	typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
n0tform3	8:1c6281289d67	283	#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) \|\| ((STATE) == ENABLE))
n0tform3	8:1c6281289d67	284
n0tform3	8:1c6281289d67	285	typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
n0tform3	8:1c6281289d67	286
n0tform3	8:1c6281289d67	287	/**
n0tform3	8:1c6281289d67	288	* @}
n0tform3	8:1c6281289d67	289	*/
n0tform3	8:1c6281289d67	290
n0tform3	8:1c6281289d67	291	/** @addtogroup Peripheral_registers_structures
n0tform3	8:1c6281289d67	292	* @{
n0tform3	8:1c6281289d67	293	*/
n0tform3	8:1c6281289d67	294
n0tform3	8:1c6281289d67	295	/**
n0tform3	8:1c6281289d67	296	* @brief Analog to Digital Converter
n0tform3	8:1c6281289d67	297	*/
n0tform3	8:1c6281289d67	298
n0tform3	8:1c6281289d67	299	typedef struct
n0tform3	8:1c6281289d67	300	{
n0tform3	8:1c6281289d67	301	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	302	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
n0tform3	8:1c6281289d67	303	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
n0tform3	8:1c6281289d67	304	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
n0tform3	8:1c6281289d67	305	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
n0tform3	8:1c6281289d67	306	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
n0tform3	8:1c6281289d67	307	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
n0tform3	8:1c6281289d67	308	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
n0tform3	8:1c6281289d67	309	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
n0tform3	8:1c6281289d67	310	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
n0tform3	8:1c6281289d67	311	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
n0tform3	8:1c6281289d67	312	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
n0tform3	8:1c6281289d67	313	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
n0tform3	8:1c6281289d67	314	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
n0tform3	8:1c6281289d67	315	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
n0tform3	8:1c6281289d67	316	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
n0tform3	8:1c6281289d67	317	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
n0tform3	8:1c6281289d67	318	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
n0tform3	8:1c6281289d67	319	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
n0tform3	8:1c6281289d67	320	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
n0tform3	8:1c6281289d67	321	} ADC_TypeDef;
n0tform3	8:1c6281289d67	322
n0tform3	8:1c6281289d67	323	typedef struct
n0tform3	8:1c6281289d67	324	{
n0tform3	8:1c6281289d67	325	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
n0tform3	8:1c6281289d67	326	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
n0tform3	8:1c6281289d67	327	__IO uint32_t CDR; /*!< ADC common regular data register for dual
n0tform3	8:1c6281289d67	328	AND triple modes, Address offset: ADC1 base address + 0x308 */
n0tform3	8:1c6281289d67	329	} ADC_Common_TypeDef;
n0tform3	8:1c6281289d67	330
n0tform3	8:1c6281289d67	331
n0tform3	8:1c6281289d67	332	/**
n0tform3	8:1c6281289d67	333	* @brief Controller Area Network TxMailBox
n0tform3	8:1c6281289d67	334	*/
n0tform3	8:1c6281289d67	335
n0tform3	8:1c6281289d67	336	typedef struct
n0tform3	8:1c6281289d67	337	{
n0tform3	8:1c6281289d67	338	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
n0tform3	8:1c6281289d67	339	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
n0tform3	8:1c6281289d67	340	__IO uint32_t TDLR; /!< CAN mailbox data low register /
n0tform3	8:1c6281289d67	341	__IO uint32_t TDHR; /!< CAN mailbox data high register /
n0tform3	8:1c6281289d67	342	} CAN_TxMailBox_TypeDef;
n0tform3	8:1c6281289d67	343
n0tform3	8:1c6281289d67	344	/**
n0tform3	8:1c6281289d67	345	* @brief Controller Area Network FIFOMailBox
n0tform3	8:1c6281289d67	346	*/
n0tform3	8:1c6281289d67	347
n0tform3	8:1c6281289d67	348	typedef struct
n0tform3	8:1c6281289d67	349	{
n0tform3	8:1c6281289d67	350	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
n0tform3	8:1c6281289d67	351	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
n0tform3	8:1c6281289d67	352	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
n0tform3	8:1c6281289d67	353	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
n0tform3	8:1c6281289d67	354	} CAN_FIFOMailBox_TypeDef;
n0tform3	8:1c6281289d67	355
n0tform3	8:1c6281289d67	356	/**
n0tform3	8:1c6281289d67	357	* @brief Controller Area Network FilterRegister
n0tform3	8:1c6281289d67	358	*/
n0tform3	8:1c6281289d67	359
n0tform3	8:1c6281289d67	360	typedef struct
n0tform3	8:1c6281289d67	361	{
n0tform3	8:1c6281289d67	362	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
n0tform3	8:1c6281289d67	363	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
n0tform3	8:1c6281289d67	364	} CAN_FilterRegister_TypeDef;
n0tform3	8:1c6281289d67	365
n0tform3	8:1c6281289d67	366	/**
n0tform3	8:1c6281289d67	367	* @brief Controller Area Network
n0tform3	8:1c6281289d67	368	*/
n0tform3	8:1c6281289d67	369
n0tform3	8:1c6281289d67	370	typedef struct
n0tform3	8:1c6281289d67	371	{
n0tform3	8:1c6281289d67	372	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	373	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	374	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	375	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	376	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	377	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	378	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	379	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	380	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
n0tform3	8:1c6281289d67	381	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
n0tform3	8:1c6281289d67	382	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
n0tform3	8:1c6281289d67	383	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
n0tform3	8:1c6281289d67	384	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
n0tform3	8:1c6281289d67	385	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
n0tform3	8:1c6281289d67	386	uint32_t RESERVED2; /!< Reserved, 0x208 /
n0tform3	8:1c6281289d67	387	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
n0tform3	8:1c6281289d67	388	uint32_t RESERVED3; /!< Reserved, 0x210 /
n0tform3	8:1c6281289d67	389	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
n0tform3	8:1c6281289d67	390	uint32_t RESERVED4; /!< Reserved, 0x218 /
n0tform3	8:1c6281289d67	391	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
n0tform3	8:1c6281289d67	392	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
n0tform3	8:1c6281289d67	393	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
n0tform3	8:1c6281289d67	394	} CAN_TypeDef;
n0tform3	8:1c6281289d67	395
n0tform3	8:1c6281289d67	396	/**
n0tform3	8:1c6281289d67	397	* @brief CRC calculation unit
n0tform3	8:1c6281289d67	398	*/
n0tform3	8:1c6281289d67	399
n0tform3	8:1c6281289d67	400	typedef struct
n0tform3	8:1c6281289d67	401	{
n0tform3	8:1c6281289d67	402	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	403	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	404	uint8_t RESERVED0; /!< Reserved, 0x05 /
n0tform3	8:1c6281289d67	405	uint16_t RESERVED1; /!< Reserved, 0x06 /
n0tform3	8:1c6281289d67	406	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	407	} CRC_TypeDef;
n0tform3	8:1c6281289d67	408
n0tform3	8:1c6281289d67	409	/**
n0tform3	8:1c6281289d67	410	* @brief Digital to Analog Converter
n0tform3	8:1c6281289d67	411	*/
n0tform3	8:1c6281289d67	412
n0tform3	8:1c6281289d67	413	typedef struct
n0tform3	8:1c6281289d67	414	{
n0tform3	8:1c6281289d67	415	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	416	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	417	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	418	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	419	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	420	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	421	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	422	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	423	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	424	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
n0tform3	8:1c6281289d67	425	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
n0tform3	8:1c6281289d67	426	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
n0tform3	8:1c6281289d67	427	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
n0tform3	8:1c6281289d67	428	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
n0tform3	8:1c6281289d67	429	} DAC_TypeDef;
n0tform3	8:1c6281289d67	430
n0tform3	8:1c6281289d67	431	/**
n0tform3	8:1c6281289d67	432	* @brief Debug MCU
n0tform3	8:1c6281289d67	433	*/
n0tform3	8:1c6281289d67	434
n0tform3	8:1c6281289d67	435	typedef struct
n0tform3	8:1c6281289d67	436	{
n0tform3	8:1c6281289d67	437	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
n0tform3	8:1c6281289d67	438	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	439	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	440	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	441	}DBGMCU_TypeDef;
n0tform3	8:1c6281289d67	442
n0tform3	8:1c6281289d67	443	/**
n0tform3	8:1c6281289d67	444	* @brief DCMI
n0tform3	8:1c6281289d67	445	*/
n0tform3	8:1c6281289d67	446
n0tform3	8:1c6281289d67	447	typedef struct
n0tform3	8:1c6281289d67	448	{
n0tform3	8:1c6281289d67	449	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
n0tform3	8:1c6281289d67	450	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	451	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	452	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	453	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	454	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	455	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	456	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	457	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
n0tform3	8:1c6281289d67	458	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
n0tform3	8:1c6281289d67	459	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
n0tform3	8:1c6281289d67	460	} DCMI_TypeDef;
n0tform3	8:1c6281289d67	461
n0tform3	8:1c6281289d67	462	/**
n0tform3	8:1c6281289d67	463	* @brief DMA Controller
n0tform3	8:1c6281289d67	464	*/
n0tform3	8:1c6281289d67	465
n0tform3	8:1c6281289d67	466	typedef struct
n0tform3	8:1c6281289d67	467	{
n0tform3	8:1c6281289d67	468	__IO uint32_t CR; /!< DMA stream x configuration register /
n0tform3	8:1c6281289d67	469	__IO uint32_t NDTR; /!< DMA stream x number of data register /
n0tform3	8:1c6281289d67	470	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
n0tform3	8:1c6281289d67	471	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
n0tform3	8:1c6281289d67	472	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
n0tform3	8:1c6281289d67	473	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
n0tform3	8:1c6281289d67	474	} DMA_Stream_TypeDef;
n0tform3	8:1c6281289d67	475
n0tform3	8:1c6281289d67	476	typedef struct
n0tform3	8:1c6281289d67	477	{
n0tform3	8:1c6281289d67	478	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	479	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	480	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	481	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	482	} DMA_TypeDef;
n0tform3	8:1c6281289d67	483
n0tform3	8:1c6281289d67	484	/**
n0tform3	8:1c6281289d67	485	* @brief Ethernet MAC
n0tform3	8:1c6281289d67	486	*/
n0tform3	8:1c6281289d67	487
n0tform3	8:1c6281289d67	488	typedef struct
n0tform3	8:1c6281289d67	489	{
n0tform3	8:1c6281289d67	490	__IO uint32_t MACCR;
n0tform3	8:1c6281289d67	491	__IO uint32_t MACFFR;
n0tform3	8:1c6281289d67	492	__IO uint32_t MACHTHR;
n0tform3	8:1c6281289d67	493	__IO uint32_t MACHTLR;
n0tform3	8:1c6281289d67	494	__IO uint32_t MACMIIAR;
n0tform3	8:1c6281289d67	495	__IO uint32_t MACMIIDR;
n0tform3	8:1c6281289d67	496	__IO uint32_t MACFCR;
n0tform3	8:1c6281289d67	497	__IO uint32_t MACVLANTR; /* 8 */
n0tform3	8:1c6281289d67	498	uint32_t RESERVED0[2];
n0tform3	8:1c6281289d67	499	__IO uint32_t MACRWUFFR; /* 11 */
n0tform3	8:1c6281289d67	500	__IO uint32_t MACPMTCSR;
n0tform3	8:1c6281289d67	501	uint32_t RESERVED1[2];
n0tform3	8:1c6281289d67	502	__IO uint32_t MACSR; /* 15 */
n0tform3	8:1c6281289d67	503	__IO uint32_t MACIMR;
n0tform3	8:1c6281289d67	504	__IO uint32_t MACA0HR;
n0tform3	8:1c6281289d67	505	__IO uint32_t MACA0LR;
n0tform3	8:1c6281289d67	506	__IO uint32_t MACA1HR;
n0tform3	8:1c6281289d67	507	__IO uint32_t MACA1LR;
n0tform3	8:1c6281289d67	508	__IO uint32_t MACA2HR;
n0tform3	8:1c6281289d67	509	__IO uint32_t MACA2LR;
n0tform3	8:1c6281289d67	510	__IO uint32_t MACA3HR;
n0tform3	8:1c6281289d67	511	__IO uint32_t MACA3LR; /* 24 */
n0tform3	8:1c6281289d67	512	uint32_t RESERVED2[40];
n0tform3	8:1c6281289d67	513	__IO uint32_t MMCCR; /* 65 */
n0tform3	8:1c6281289d67	514	__IO uint32_t MMCRIR;
n0tform3	8:1c6281289d67	515	__IO uint32_t MMCTIR;
n0tform3	8:1c6281289d67	516	__IO uint32_t MMCRIMR;
n0tform3	8:1c6281289d67	517	__IO uint32_t MMCTIMR; /* 69 */
n0tform3	8:1c6281289d67	518	uint32_t RESERVED3[14];
n0tform3	8:1c6281289d67	519	__IO uint32_t MMCTGFSCCR; /* 84 */
n0tform3	8:1c6281289d67	520	__IO uint32_t MMCTGFMSCCR;
n0tform3	8:1c6281289d67	521	uint32_t RESERVED4[5];
n0tform3	8:1c6281289d67	522	__IO uint32_t MMCTGFCR;
n0tform3	8:1c6281289d67	523	uint32_t RESERVED5[10];
n0tform3	8:1c6281289d67	524	__IO uint32_t MMCRFCECR;
n0tform3	8:1c6281289d67	525	__IO uint32_t MMCRFAECR;
n0tform3	8:1c6281289d67	526	uint32_t RESERVED6[10];
n0tform3	8:1c6281289d67	527	__IO uint32_t MMCRGUFCR;
n0tform3	8:1c6281289d67	528	uint32_t RESERVED7[334];
n0tform3	8:1c6281289d67	529	__IO uint32_t PTPTSCR;
n0tform3	8:1c6281289d67	530	__IO uint32_t PTPSSIR;
n0tform3	8:1c6281289d67	531	__IO uint32_t PTPTSHR;
n0tform3	8:1c6281289d67	532	__IO uint32_t PTPTSLR;
n0tform3	8:1c6281289d67	533	__IO uint32_t PTPTSHUR;
n0tform3	8:1c6281289d67	534	__IO uint32_t PTPTSLUR;
n0tform3	8:1c6281289d67	535	__IO uint32_t PTPTSAR;
n0tform3	8:1c6281289d67	536	__IO uint32_t PTPTTHR;
n0tform3	8:1c6281289d67	537	__IO uint32_t PTPTTLR;
n0tform3	8:1c6281289d67	538	__IO uint32_t RESERVED8;
n0tform3	8:1c6281289d67	539	__IO uint32_t PTPTSSR;
n0tform3	8:1c6281289d67	540	uint32_t RESERVED9[565];
n0tform3	8:1c6281289d67	541	__IO uint32_t DMABMR;
n0tform3	8:1c6281289d67	542	__IO uint32_t DMATPDR;
n0tform3	8:1c6281289d67	543	__IO uint32_t DMARPDR;
n0tform3	8:1c6281289d67	544	__IO uint32_t DMARDLAR;
n0tform3	8:1c6281289d67	545	__IO uint32_t DMATDLAR;
n0tform3	8:1c6281289d67	546	__IO uint32_t DMASR;
n0tform3	8:1c6281289d67	547	__IO uint32_t DMAOMR;
n0tform3	8:1c6281289d67	548	__IO uint32_t DMAIER;
n0tform3	8:1c6281289d67	549	__IO uint32_t DMAMFBOCR;
n0tform3	8:1c6281289d67	550	__IO uint32_t DMARSWTR;
n0tform3	8:1c6281289d67	551	uint32_t RESERVED10[8];
n0tform3	8:1c6281289d67	552	__IO uint32_t DMACHTDR;
n0tform3	8:1c6281289d67	553	__IO uint32_t DMACHRDR;
n0tform3	8:1c6281289d67	554	__IO uint32_t DMACHTBAR;
n0tform3	8:1c6281289d67	555	__IO uint32_t DMACHRBAR;
n0tform3	8:1c6281289d67	556	} ETH_TypeDef;
n0tform3	8:1c6281289d67	557
n0tform3	8:1c6281289d67	558	/**
n0tform3	8:1c6281289d67	559	* @brief External Interrupt/Event Controller
n0tform3	8:1c6281289d67	560	*/
n0tform3	8:1c6281289d67	561
n0tform3	8:1c6281289d67	562	typedef struct
n0tform3	8:1c6281289d67	563	{
n0tform3	8:1c6281289d67	564	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	565	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	566	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	567	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	568	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	569	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	570	} EXTI_TypeDef;
n0tform3	8:1c6281289d67	571
n0tform3	8:1c6281289d67	572	/**
n0tform3	8:1c6281289d67	573	* @brief FLASH Registers
n0tform3	8:1c6281289d67	574	*/
n0tform3	8:1c6281289d67	575
n0tform3	8:1c6281289d67	576	typedef struct
n0tform3	8:1c6281289d67	577	{
n0tform3	8:1c6281289d67	578	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	579	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	580	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	581	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	582	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	583	__IO uint32_t OPTCR; /!< FLASH option control register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	584	} FLASH_TypeDef;
n0tform3	8:1c6281289d67	585
n0tform3	8:1c6281289d67	586	/**
n0tform3	8:1c6281289d67	587	* @brief Flexible Static Memory Controller
n0tform3	8:1c6281289d67	588	*/
n0tform3	8:1c6281289d67	589
n0tform3	8:1c6281289d67	590	typedef struct
n0tform3	8:1c6281289d67	591	{
n0tform3	8:1c6281289d67	592	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
n0tform3	8:1c6281289d67	593	} FSMC_Bank1_TypeDef;
n0tform3	8:1c6281289d67	594
n0tform3	8:1c6281289d67	595	/**
n0tform3	8:1c6281289d67	596	* @brief Flexible Static Memory Controller Bank1E
n0tform3	8:1c6281289d67	597	*/
n0tform3	8:1c6281289d67	598
n0tform3	8:1c6281289d67	599	typedef struct
n0tform3	8:1c6281289d67	600	{
n0tform3	8:1c6281289d67	601	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
n0tform3	8:1c6281289d67	602	} FSMC_Bank1E_TypeDef;
n0tform3	8:1c6281289d67	603
n0tform3	8:1c6281289d67	604	/**
n0tform3	8:1c6281289d67	605	* @brief Flexible Static Memory Controller Bank2
n0tform3	8:1c6281289d67	606	*/
n0tform3	8:1c6281289d67	607
n0tform3	8:1c6281289d67	608	typedef struct
n0tform3	8:1c6281289d67	609	{
n0tform3	8:1c6281289d67	610	__IO uint32_t PCR2; /!< NAND Flash control register 2, Address offset: 0x60 /
n0tform3	8:1c6281289d67	611	__IO uint32_t SR2; /!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 /
n0tform3	8:1c6281289d67	612	__IO uint32_t PMEM2; /!< NAND Flash Common memory space timing register 2, Address offset: 0x68 /
n0tform3	8:1c6281289d67	613	__IO uint32_t PATT2; /!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C /
n0tform3	8:1c6281289d67	614	uint32_t RESERVED0; /!< Reserved, 0x70 /
n0tform3	8:1c6281289d67	615	__IO uint32_t ECCR2; /!< NAND Flash ECC result registers 2, Address offset: 0x74 /
n0tform3	8:1c6281289d67	616	} FSMC_Bank2_TypeDef;
n0tform3	8:1c6281289d67	617
n0tform3	8:1c6281289d67	618	/**
n0tform3	8:1c6281289d67	619	* @brief Flexible Static Memory Controller Bank3
n0tform3	8:1c6281289d67	620	*/
n0tform3	8:1c6281289d67	621
n0tform3	8:1c6281289d67	622	typedef struct
n0tform3	8:1c6281289d67	623	{
n0tform3	8:1c6281289d67	624	__IO uint32_t PCR3; /!< NAND Flash control register 3, Address offset: 0x80 /
n0tform3	8:1c6281289d67	625	__IO uint32_t SR3; /!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 /
n0tform3	8:1c6281289d67	626	__IO uint32_t PMEM3; /!< NAND Flash Common memory space timing register 3, Address offset: 0x88 /
n0tform3	8:1c6281289d67	627	__IO uint32_t PATT3; /!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C /
n0tform3	8:1c6281289d67	628	uint32_t RESERVED0; /!< Reserved, 0x90 /
n0tform3	8:1c6281289d67	629	__IO uint32_t ECCR3; /!< NAND Flash ECC result registers 3, Address offset: 0x94 /
n0tform3	8:1c6281289d67	630	} FSMC_Bank3_TypeDef;
n0tform3	8:1c6281289d67	631
n0tform3	8:1c6281289d67	632	/**
n0tform3	8:1c6281289d67	633	* @brief Flexible Static Memory Controller Bank4
n0tform3	8:1c6281289d67	634	*/
n0tform3	8:1c6281289d67	635
n0tform3	8:1c6281289d67	636	typedef struct
n0tform3	8:1c6281289d67	637	{
n0tform3	8:1c6281289d67	638	__IO uint32_t PCR4; /!< PC Card control register 4, Address offset: 0xA0 /
n0tform3	8:1c6281289d67	639	__IO uint32_t SR4; /!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 /
n0tform3	8:1c6281289d67	640	__IO uint32_t PMEM4; /!< PC Card Common memory space timing register 4, Address offset: 0xA8 /
n0tform3	8:1c6281289d67	641	__IO uint32_t PATT4; /!< PC Card Attribute memory space timing register 4, Address offset: 0xAC /
n0tform3	8:1c6281289d67	642	__IO uint32_t PIO4; /!< PC Card I/O space timing register 4, Address offset: 0xB0 /
n0tform3	8:1c6281289d67	643	} FSMC_Bank4_TypeDef;
n0tform3	8:1c6281289d67	644
n0tform3	8:1c6281289d67	645	/**
n0tform3	8:1c6281289d67	646	* @brief General Purpose I/O
n0tform3	8:1c6281289d67	647	*/
n0tform3	8:1c6281289d67	648
n0tform3	8:1c6281289d67	649	typedef struct
n0tform3	8:1c6281289d67	650	{
n0tform3	8:1c6281289d67	651	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	652	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	653	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	654	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	655	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	656	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	657	__IO uint16_t BSRRL; /!< GPIO port bit set/reset low register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	658	__IO uint16_t BSRRH; /!< GPIO port bit set/reset high register, Address offset: 0x1A /
n0tform3	8:1c6281289d67	659	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	660	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
n0tform3	8:1c6281289d67	661	} GPIO_TypeDef;
n0tform3	8:1c6281289d67	662
n0tform3	8:1c6281289d67	663	/**
n0tform3	8:1c6281289d67	664	* @brief System configuration controller
n0tform3	8:1c6281289d67	665	*/
n0tform3	8:1c6281289d67	666
n0tform3	8:1c6281289d67	667	typedef struct
n0tform3	8:1c6281289d67	668	{
n0tform3	8:1c6281289d67	669	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	670	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	671	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
n0tform3	8:1c6281289d67	672	uint32_t RESERVED[2]; /!< Reserved, 0x18-0x1C /
n0tform3	8:1c6281289d67	673	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	674	} SYSCFG_TypeDef;
n0tform3	8:1c6281289d67	675
n0tform3	8:1c6281289d67	676	/**
n0tform3	8:1c6281289d67	677	* @brief Inter-integrated Circuit Interface
n0tform3	8:1c6281289d67	678	*/
n0tform3	8:1c6281289d67	679
n0tform3	8:1c6281289d67	680	typedef struct
n0tform3	8:1c6281289d67	681	{
n0tform3	8:1c6281289d67	682	__IO uint16_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
n0tform3	8:1c6281289d67	683	uint16_t RESERVED0; /!< Reserved, 0x02 /
n0tform3	8:1c6281289d67	684	__IO uint16_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
n0tform3	8:1c6281289d67	685	uint16_t RESERVED1; /!< Reserved, 0x06 /
n0tform3	8:1c6281289d67	686	__IO uint16_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
n0tform3	8:1c6281289d67	687	uint16_t RESERVED2; /!< Reserved, 0x0A /
n0tform3	8:1c6281289d67	688	__IO uint16_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
n0tform3	8:1c6281289d67	689	uint16_t RESERVED3; /!< Reserved, 0x0E /
n0tform3	8:1c6281289d67	690	__IO uint16_t DR; /!< I2C Data register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	691	uint16_t RESERVED4; /!< Reserved, 0x12 /
n0tform3	8:1c6281289d67	692	__IO uint16_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
n0tform3	8:1c6281289d67	693	uint16_t RESERVED5; /!< Reserved, 0x16 /
n0tform3	8:1c6281289d67	694	__IO uint16_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
n0tform3	8:1c6281289d67	695	uint16_t RESERVED6; /!< Reserved, 0x1A /
n0tform3	8:1c6281289d67	696	__IO uint16_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	697	uint16_t RESERVED7; /!< Reserved, 0x1E /
n0tform3	8:1c6281289d67	698	__IO uint16_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	699	uint16_t RESERVED8; /!< Reserved, 0x22 /
n0tform3	8:1c6281289d67	700	} I2C_TypeDef;
n0tform3	8:1c6281289d67	701
n0tform3	8:1c6281289d67	702	/**
n0tform3	8:1c6281289d67	703	* @brief Independent WATCHDOG
n0tform3	8:1c6281289d67	704	*/
n0tform3	8:1c6281289d67	705
n0tform3	8:1c6281289d67	706	typedef struct
n0tform3	8:1c6281289d67	707	{
n0tform3	8:1c6281289d67	708	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	709	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	710	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	711	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	712	} IWDG_TypeDef;
n0tform3	8:1c6281289d67	713
n0tform3	8:1c6281289d67	714	/**
n0tform3	8:1c6281289d67	715	* @brief Power Control
n0tform3	8:1c6281289d67	716	*/
n0tform3	8:1c6281289d67	717
n0tform3	8:1c6281289d67	718	typedef struct
n0tform3	8:1c6281289d67	719	{
n0tform3	8:1c6281289d67	720	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	721	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	722	} PWR_TypeDef;
n0tform3	8:1c6281289d67	723
n0tform3	8:1c6281289d67	724	/**
n0tform3	8:1c6281289d67	725	* @brief Reset and Clock Control
n0tform3	8:1c6281289d67	726	*/
n0tform3	8:1c6281289d67	727
n0tform3	8:1c6281289d67	728	typedef struct
n0tform3	8:1c6281289d67	729	{
n0tform3	8:1c6281289d67	730	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	731	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	732	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	733	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	734	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	735	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	736	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	737	uint32_t RESERVED0; /!< Reserved, 0x1C /
n0tform3	8:1c6281289d67	738	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	739	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
n0tform3	8:1c6281289d67	740	uint32_t RESERVED1[2]; /!< Reserved, 0x28-0x2C /
n0tform3	8:1c6281289d67	741	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
n0tform3	8:1c6281289d67	742	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
n0tform3	8:1c6281289d67	743	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
n0tform3	8:1c6281289d67	744	uint32_t RESERVED2; /!< Reserved, 0x3C /
n0tform3	8:1c6281289d67	745	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
n0tform3	8:1c6281289d67	746	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
n0tform3	8:1c6281289d67	747	uint32_t RESERVED3[2]; /!< Reserved, 0x48-0x4C /
n0tform3	8:1c6281289d67	748	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
n0tform3	8:1c6281289d67	749	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
n0tform3	8:1c6281289d67	750	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
n0tform3	8:1c6281289d67	751	uint32_t RESERVED4; /!< Reserved, 0x5C /
n0tform3	8:1c6281289d67	752	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
n0tform3	8:1c6281289d67	753	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
n0tform3	8:1c6281289d67	754	uint32_t RESERVED5[2]; /!< Reserved, 0x68-0x6C /
n0tform3	8:1c6281289d67	755	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
n0tform3	8:1c6281289d67	756	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
n0tform3	8:1c6281289d67	757	uint32_t RESERVED6[2]; /!< Reserved, 0x78-0x7C /
n0tform3	8:1c6281289d67	758	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
n0tform3	8:1c6281289d67	759	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
n0tform3	8:1c6281289d67	760	} RCC_TypeDef;
n0tform3	8:1c6281289d67	761
n0tform3	8:1c6281289d67	762	/**
n0tform3	8:1c6281289d67	763	* @brief Real-Time Clock
n0tform3	8:1c6281289d67	764	*/
n0tform3	8:1c6281289d67	765
n0tform3	8:1c6281289d67	766	typedef struct
n0tform3	8:1c6281289d67	767	{
n0tform3	8:1c6281289d67	768	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	769	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	770	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	771	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	772	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	773	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	774	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	775	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	776	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	777	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
n0tform3	8:1c6281289d67	778	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
n0tform3	8:1c6281289d67	779	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
n0tform3	8:1c6281289d67	780	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
n0tform3	8:1c6281289d67	781	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
n0tform3	8:1c6281289d67	782	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
n0tform3	8:1c6281289d67	783	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
n0tform3	8:1c6281289d67	784	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
n0tform3	8:1c6281289d67	785	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
n0tform3	8:1c6281289d67	786	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
n0tform3	8:1c6281289d67	787	uint32_t RESERVED7; /!< Reserved, 0x4C /
n0tform3	8:1c6281289d67	788	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
n0tform3	8:1c6281289d67	789	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
n0tform3	8:1c6281289d67	790	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
n0tform3	8:1c6281289d67	791	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
n0tform3	8:1c6281289d67	792	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
n0tform3	8:1c6281289d67	793	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
n0tform3	8:1c6281289d67	794	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
n0tform3	8:1c6281289d67	795	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
n0tform3	8:1c6281289d67	796	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
n0tform3	8:1c6281289d67	797	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
n0tform3	8:1c6281289d67	798	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
n0tform3	8:1c6281289d67	799	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
n0tform3	8:1c6281289d67	800	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
n0tform3	8:1c6281289d67	801	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
n0tform3	8:1c6281289d67	802	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
n0tform3	8:1c6281289d67	803	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
n0tform3	8:1c6281289d67	804	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
n0tform3	8:1c6281289d67	805	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
n0tform3	8:1c6281289d67	806	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
n0tform3	8:1c6281289d67	807	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
n0tform3	8:1c6281289d67	808	} RTC_TypeDef;
n0tform3	8:1c6281289d67	809
n0tform3	8:1c6281289d67	810	/**
n0tform3	8:1c6281289d67	811	* @brief SD host Interface
n0tform3	8:1c6281289d67	812	*/
n0tform3	8:1c6281289d67	813
n0tform3	8:1c6281289d67	814	typedef struct
n0tform3	8:1c6281289d67	815	{
n0tform3	8:1c6281289d67	816	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	817	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	818	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	819	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	820	__I uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	821	__I uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	822	__I uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	823	__I uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	824	__I uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	825	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
n0tform3	8:1c6281289d67	826	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
n0tform3	8:1c6281289d67	827	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
n0tform3	8:1c6281289d67	828	__I uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
n0tform3	8:1c6281289d67	829	__I uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
n0tform3	8:1c6281289d67	830	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
n0tform3	8:1c6281289d67	831	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
n0tform3	8:1c6281289d67	832	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
n0tform3	8:1c6281289d67	833	__I uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
n0tform3	8:1c6281289d67	834	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
n0tform3	8:1c6281289d67	835	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
n0tform3	8:1c6281289d67	836	} SDIO_TypeDef;
n0tform3	8:1c6281289d67	837
n0tform3	8:1c6281289d67	838	/**
n0tform3	8:1c6281289d67	839	* @brief Serial Peripheral Interface
n0tform3	8:1c6281289d67	840	*/
n0tform3	8:1c6281289d67	841
n0tform3	8:1c6281289d67	842	typedef struct
n0tform3	8:1c6281289d67	843	{
n0tform3	8:1c6281289d67	844	__IO uint16_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
n0tform3	8:1c6281289d67	845	uint16_t RESERVED0; /!< Reserved, 0x02 /
n0tform3	8:1c6281289d67	846	__IO uint16_t CR2; /!< SPI control register 2, Address offset: 0x04 /
n0tform3	8:1c6281289d67	847	uint16_t RESERVED1; /!< Reserved, 0x06 /
n0tform3	8:1c6281289d67	848	__IO uint16_t SR; /!< SPI status register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	849	uint16_t RESERVED2; /!< Reserved, 0x0A /
n0tform3	8:1c6281289d67	850	__IO uint16_t DR; /!< SPI data register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	851	uint16_t RESERVED3; /!< Reserved, 0x0E /
n0tform3	8:1c6281289d67	852	__IO uint16_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
n0tform3	8:1c6281289d67	853	uint16_t RESERVED4; /!< Reserved, 0x12 /
n0tform3	8:1c6281289d67	854	__IO uint16_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
n0tform3	8:1c6281289d67	855	uint16_t RESERVED5; /!< Reserved, 0x16 /
n0tform3	8:1c6281289d67	856	__IO uint16_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
n0tform3	8:1c6281289d67	857	uint16_t RESERVED6; /!< Reserved, 0x1A /
n0tform3	8:1c6281289d67	858	__IO uint16_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	859	uint16_t RESERVED7; /!< Reserved, 0x1E /
n0tform3	8:1c6281289d67	860	__IO uint16_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	861	uint16_t RESERVED8; /!< Reserved, 0x22 /
n0tform3	8:1c6281289d67	862	} SPI_TypeDef;
n0tform3	8:1c6281289d67	863
n0tform3	8:1c6281289d67	864	/**
n0tform3	8:1c6281289d67	865	* @brief TIM
n0tform3	8:1c6281289d67	866	*/
n0tform3	8:1c6281289d67	867
n0tform3	8:1c6281289d67	868	typedef struct
n0tform3	8:1c6281289d67	869	{
n0tform3	8:1c6281289d67	870	__IO uint16_t CR1; /!< TIM control register 1, Address offset: 0x00 /
n0tform3	8:1c6281289d67	871	uint16_t RESERVED0; /!< Reserved, 0x02 /
n0tform3	8:1c6281289d67	872	__IO uint16_t CR2; /!< TIM control register 2, Address offset: 0x04 /
n0tform3	8:1c6281289d67	873	uint16_t RESERVED1; /!< Reserved, 0x06 /
n0tform3	8:1c6281289d67	874	__IO uint16_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	875	uint16_t RESERVED2; /!< Reserved, 0x0A /
n0tform3	8:1c6281289d67	876	__IO uint16_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	877	uint16_t RESERVED3; /!< Reserved, 0x0E /
n0tform3	8:1c6281289d67	878	__IO uint16_t SR; /!< TIM status register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	879	uint16_t RESERVED4; /!< Reserved, 0x12 /
n0tform3	8:1c6281289d67	880	__IO uint16_t EGR; /!< TIM event generation register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	881	uint16_t RESERVED5; /!< Reserved, 0x16 /
n0tform3	8:1c6281289d67	882	__IO uint16_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
n0tform3	8:1c6281289d67	883	uint16_t RESERVED6; /!< Reserved, 0x1A /
n0tform3	8:1c6281289d67	884	__IO uint16_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
n0tform3	8:1c6281289d67	885	uint16_t RESERVED7; /!< Reserved, 0x1E /
n0tform3	8:1c6281289d67	886	__IO uint16_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	887	uint16_t RESERVED8; /!< Reserved, 0x22 /
n0tform3	8:1c6281289d67	888	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
n0tform3	8:1c6281289d67	889	__IO uint16_t PSC; /!< TIM prescaler, Address offset: 0x28 /
n0tform3	8:1c6281289d67	890	uint16_t RESERVED9; /!< Reserved, 0x2A /
n0tform3	8:1c6281289d67	891	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
n0tform3	8:1c6281289d67	892	__IO uint16_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
n0tform3	8:1c6281289d67	893	uint16_t RESERVED10; /!< Reserved, 0x32 /
n0tform3	8:1c6281289d67	894	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
n0tform3	8:1c6281289d67	895	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
n0tform3	8:1c6281289d67	896	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
n0tform3	8:1c6281289d67	897	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
n0tform3	8:1c6281289d67	898	__IO uint16_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
n0tform3	8:1c6281289d67	899	uint16_t RESERVED11; /!< Reserved, 0x46 /
n0tform3	8:1c6281289d67	900	__IO uint16_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
n0tform3	8:1c6281289d67	901	uint16_t RESERVED12; /!< Reserved, 0x4A /
n0tform3	8:1c6281289d67	902	__IO uint16_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
n0tform3	8:1c6281289d67	903	uint16_t RESERVED13; /!< Reserved, 0x4E /
n0tform3	8:1c6281289d67	904	__IO uint16_t OR; /!< TIM option register, Address offset: 0x50 /
n0tform3	8:1c6281289d67	905	uint16_t RESERVED14; /!< Reserved, 0x52 /
n0tform3	8:1c6281289d67	906	} TIM_TypeDef;
n0tform3	8:1c6281289d67	907
n0tform3	8:1c6281289d67	908	/**
n0tform3	8:1c6281289d67	909	* @brief Universal Synchronous Asynchronous Receiver Transmitter
n0tform3	8:1c6281289d67	910	*/
n0tform3	8:1c6281289d67	911
n0tform3	8:1c6281289d67	912	typedef struct
n0tform3	8:1c6281289d67	913	{
n0tform3	8:1c6281289d67	914	__IO uint16_t SR; /!< USART Status register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	915	uint16_t RESERVED0; /!< Reserved, 0x02 /
n0tform3	8:1c6281289d67	916	__IO uint16_t DR; /!< USART Data register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	917	uint16_t RESERVED1; /!< Reserved, 0x06 /
n0tform3	8:1c6281289d67	918	__IO uint16_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	919	uint16_t RESERVED2; /!< Reserved, 0x0A /
n0tform3	8:1c6281289d67	920	__IO uint16_t CR1; /!< USART Control register 1, Address offset: 0x0C /
n0tform3	8:1c6281289d67	921	uint16_t RESERVED3; /!< Reserved, 0x0E /
n0tform3	8:1c6281289d67	922	__IO uint16_t CR2; /!< USART Control register 2, Address offset: 0x10 /
n0tform3	8:1c6281289d67	923	uint16_t RESERVED4; /!< Reserved, 0x12 /
n0tform3	8:1c6281289d67	924	__IO uint16_t CR3; /!< USART Control register 3, Address offset: 0x14 /
n0tform3	8:1c6281289d67	925	uint16_t RESERVED5; /!< Reserved, 0x16 /
n0tform3	8:1c6281289d67	926	__IO uint16_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	927	uint16_t RESERVED6; /!< Reserved, 0x1A /
n0tform3	8:1c6281289d67	928	} USART_TypeDef;
n0tform3	8:1c6281289d67	929
n0tform3	8:1c6281289d67	930	/**
n0tform3	8:1c6281289d67	931	* @brief Window WATCHDOG
n0tform3	8:1c6281289d67	932	*/
n0tform3	8:1c6281289d67	933
n0tform3	8:1c6281289d67	934	typedef struct
n0tform3	8:1c6281289d67	935	{
n0tform3	8:1c6281289d67	936	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	937	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	938	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	939	} WWDG_TypeDef;
n0tform3	8:1c6281289d67	940
n0tform3	8:1c6281289d67	941	/**
n0tform3	8:1c6281289d67	942	* @brief Crypto Processor
n0tform3	8:1c6281289d67	943	*/
n0tform3	8:1c6281289d67	944
n0tform3	8:1c6281289d67	945	typedef struct
n0tform3	8:1c6281289d67	946	{
n0tform3	8:1c6281289d67	947	__IO uint32_t CR; /!< CRYP control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	948	__IO uint32_t SR; /!< CRYP status register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	949	__IO uint32_t DR; /!< CRYP data input register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	950	__IO uint32_t DOUT; /!< CRYP data output register, Address offset: 0x0C /
n0tform3	8:1c6281289d67	951	__IO uint32_t DMACR; /!< CRYP DMA control register, Address offset: 0x10 /
n0tform3	8:1c6281289d67	952	__IO uint32_t IMSCR; /!< CRYP interrupt mask set/clear register, Address offset: 0x14 /
n0tform3	8:1c6281289d67	953	__IO uint32_t RISR; /!< CRYP raw interrupt status register, Address offset: 0x18 /
n0tform3	8:1c6281289d67	954	__IO uint32_t MISR; /!< CRYP masked interrupt status register, Address offset: 0x1C /
n0tform3	8:1c6281289d67	955	__IO uint32_t K0LR; /!< CRYP key left register 0, Address offset: 0x20 /
n0tform3	8:1c6281289d67	956	__IO uint32_t K0RR; /!< CRYP key right register 0, Address offset: 0x24 /
n0tform3	8:1c6281289d67	957	__IO uint32_t K1LR; /!< CRYP key left register 1, Address offset: 0x28 /
n0tform3	8:1c6281289d67	958	__IO uint32_t K1RR; /!< CRYP key right register 1, Address offset: 0x2C /
n0tform3	8:1c6281289d67	959	__IO uint32_t K2LR; /!< CRYP key left register 2, Address offset: 0x30 /
n0tform3	8:1c6281289d67	960	__IO uint32_t K2RR; /!< CRYP key right register 2, Address offset: 0x34 /
n0tform3	8:1c6281289d67	961	__IO uint32_t K3LR; /!< CRYP key left register 3, Address offset: 0x38 /
n0tform3	8:1c6281289d67	962	__IO uint32_t K3RR; /!< CRYP key right register 3, Address offset: 0x3C /
n0tform3	8:1c6281289d67	963	__IO uint32_t IV0LR; /!< CRYP initialization vector left-word register 0, Address offset: 0x40 /
n0tform3	8:1c6281289d67	964	__IO uint32_t IV0RR; /!< CRYP initialization vector right-word register 0, Address offset: 0x44 /
n0tform3	8:1c6281289d67	965	__IO uint32_t IV1LR; /!< CRYP initialization vector left-word register 1, Address offset: 0x48 /
n0tform3	8:1c6281289d67	966	__IO uint32_t IV1RR; /!< CRYP initialization vector right-word register 1, Address offset: 0x4C /
n0tform3	8:1c6281289d67	967	} CRYP_TypeDef;
n0tform3	8:1c6281289d67	968
n0tform3	8:1c6281289d67	969	/**
n0tform3	8:1c6281289d67	970	* @brief HASH
n0tform3	8:1c6281289d67	971	*/
n0tform3	8:1c6281289d67	972
n0tform3	8:1c6281289d67	973	typedef struct
n0tform3	8:1c6281289d67	974	{
n0tform3	8:1c6281289d67	975	__IO uint32_t CR; /!< HASH control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	976	__IO uint32_t DIN; /!< HASH data input register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	977	__IO uint32_t STR; /!< HASH start register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	978	__IO uint32_t HR[5]; /!< HASH digest registers, Address offset: 0x0C-0x1C /
n0tform3	8:1c6281289d67	979	__IO uint32_t IMR; /!< HASH interrupt enable register, Address offset: 0x20 /
n0tform3	8:1c6281289d67	980	__IO uint32_t SR; /!< HASH status register, Address offset: 0x24 /
n0tform3	8:1c6281289d67	981	uint32_t RESERVED[52]; /!< Reserved, 0x28-0xF4 /
n0tform3	8:1c6281289d67	982	__IO uint32_t CSR[51]; /!< HASH context swap registers, Address offset: 0x0F8-0x1C0 /
n0tform3	8:1c6281289d67	983	} HASH_TypeDef;
n0tform3	8:1c6281289d67	984
n0tform3	8:1c6281289d67	985	/**
n0tform3	8:1c6281289d67	986	* @brief HASH
n0tform3	8:1c6281289d67	987	*/
n0tform3	8:1c6281289d67	988
n0tform3	8:1c6281289d67	989	typedef struct
n0tform3	8:1c6281289d67	990	{
n0tform3	8:1c6281289d67	991	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
n0tform3	8:1c6281289d67	992	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
n0tform3	8:1c6281289d67	993	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
n0tform3	8:1c6281289d67	994	} RNG_TypeDef;
n0tform3	8:1c6281289d67	995
n0tform3	8:1c6281289d67	996	/**
n0tform3	8:1c6281289d67	997	* @}
n0tform3	8:1c6281289d67	998	*/
n0tform3	8:1c6281289d67	999
n0tform3	8:1c6281289d67	1000	/** @addtogroup Peripheral_memory_map
n0tform3	8:1c6281289d67	1001	* @{
n0tform3	8:1c6281289d67	1002	*/
n0tform3	8:1c6281289d67	1003	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH(up to 1 MB) base address in the alias region /
n0tform3	8:1c6281289d67	1004	#define CCMDATARAM_BASE ((uint32_t)0x10000000) /!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region /
n0tform3	8:1c6281289d67	1005	#define SRAM1_BASE ((uint32_t)0x20000000) /!< SRAM1(112 KB) base address in the alias region /
n0tform3	8:1c6281289d67	1006	#define SRAM2_BASE ((uint32_t)0x2001C000) /!< SRAM2(16 KB) base address in the alias region /
n0tform3	8:1c6281289d67	1007	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
n0tform3	8:1c6281289d67	1008	#define BKPSRAM_BASE ((uint32_t)0x40024000) /!< Backup SRAM(4 KB) base address in the alias region /
n0tform3	8:1c6281289d67	1009	#define FSMC_R_BASE ((uint32_t)0xA0000000) /!< FSMC registers base address /
n0tform3	8:1c6281289d67	1010
n0tform3	8:1c6281289d67	1011	#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region /
n0tform3	8:1c6281289d67	1012	#define SRAM1_BB_BASE ((uint32_t)0x22000000) /!< SRAM1(112 KB) base address in the bit-band region /
n0tform3	8:1c6281289d67	1013	#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /!< SRAM2(16 KB) base address in the bit-band region /
n0tform3	8:1c6281289d67	1014	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
n0tform3	8:1c6281289d67	1015	#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /!< Backup SRAM(4 KB) base address in the bit-band region /
n0tform3	8:1c6281289d67	1016
n0tform3	8:1c6281289d67	1017	/* Legacy defines */
n0tform3	8:1c6281289d67	1018	#define SRAM_BASE SRAM1_BASE
n0tform3	8:1c6281289d67	1019	#define SRAM_BB_BASE SRAM1_BB_BASE
n0tform3	8:1c6281289d67	1020
n0tform3	8:1c6281289d67	1021
n0tform3	8:1c6281289d67	1022	/!< Peripheral memory map /
n0tform3	8:1c6281289d67	1023	#define APB1PERIPH_BASE PERIPH_BASE
n0tform3	8:1c6281289d67	1024	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
n0tform3	8:1c6281289d67	1025	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
n0tform3	8:1c6281289d67	1026	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
n0tform3	8:1c6281289d67	1027
n0tform3	8:1c6281289d67	1028	/!< APB1 peripherals /
n0tform3	8:1c6281289d67	1029	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
n0tform3	8:1c6281289d67	1030	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
n0tform3	8:1c6281289d67	1031	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
n0tform3	8:1c6281289d67	1032	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
n0tform3	8:1c6281289d67	1033	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
n0tform3	8:1c6281289d67	1034	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
n0tform3	8:1c6281289d67	1035	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
n0tform3	8:1c6281289d67	1036	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
n0tform3	8:1c6281289d67	1037	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
n0tform3	8:1c6281289d67	1038	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
n0tform3	8:1c6281289d67	1039	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
n0tform3	8:1c6281289d67	1040	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
n0tform3	8:1c6281289d67	1041	#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
n0tform3	8:1c6281289d67	1042	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
n0tform3	8:1c6281289d67	1043	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
n0tform3	8:1c6281289d67	1044	#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
n0tform3	8:1c6281289d67	1045	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
n0tform3	8:1c6281289d67	1046	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
n0tform3	8:1c6281289d67	1047	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
n0tform3	8:1c6281289d67	1048	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
n0tform3	8:1c6281289d67	1049	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
n0tform3	8:1c6281289d67	1050	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
n0tform3	8:1c6281289d67	1051	#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
n0tform3	8:1c6281289d67	1052	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
n0tform3	8:1c6281289d67	1053	#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
n0tform3	8:1c6281289d67	1054	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
n0tform3	8:1c6281289d67	1055	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
n0tform3	8:1c6281289d67	1056
n0tform3	8:1c6281289d67	1057	/!< APB2 peripherals /
n0tform3	8:1c6281289d67	1058	#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
n0tform3	8:1c6281289d67	1059	#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
n0tform3	8:1c6281289d67	1060	#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
n0tform3	8:1c6281289d67	1061	#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
n0tform3	8:1c6281289d67	1062	#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
n0tform3	8:1c6281289d67	1063	#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
n0tform3	8:1c6281289d67	1064	#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
n0tform3	8:1c6281289d67	1065	#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
n0tform3	8:1c6281289d67	1066	#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
n0tform3	8:1c6281289d67	1067	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
n0tform3	8:1c6281289d67	1068	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
n0tform3	8:1c6281289d67	1069	#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
n0tform3	8:1c6281289d67	1070	#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
n0tform3	8:1c6281289d67	1071	#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
n0tform3	8:1c6281289d67	1072	#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
n0tform3	8:1c6281289d67	1073
n0tform3	8:1c6281289d67	1074	/!< AHB1 peripherals /
n0tform3	8:1c6281289d67	1075	#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
n0tform3	8:1c6281289d67	1076	#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
n0tform3	8:1c6281289d67	1077	#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
n0tform3	8:1c6281289d67	1078	#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
n0tform3	8:1c6281289d67	1079	#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
n0tform3	8:1c6281289d67	1080	#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
n0tform3	8:1c6281289d67	1081	#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
n0tform3	8:1c6281289d67	1082	#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
n0tform3	8:1c6281289d67	1083	#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
n0tform3	8:1c6281289d67	1084	#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
n0tform3	8:1c6281289d67	1085	#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
n0tform3	8:1c6281289d67	1086	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
n0tform3	8:1c6281289d67	1087	#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
n0tform3	8:1c6281289d67	1088	#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
n0tform3	8:1c6281289d67	1089	#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
n0tform3	8:1c6281289d67	1090	#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
n0tform3	8:1c6281289d67	1091	#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
n0tform3	8:1c6281289d67	1092	#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
n0tform3	8:1c6281289d67	1093	#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
n0tform3	8:1c6281289d67	1094	#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
n0tform3	8:1c6281289d67	1095	#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
n0tform3	8:1c6281289d67	1096	#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
n0tform3	8:1c6281289d67	1097	#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
n0tform3	8:1c6281289d67	1098	#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
n0tform3	8:1c6281289d67	1099	#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
n0tform3	8:1c6281289d67	1100	#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
n0tform3	8:1c6281289d67	1101	#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
n0tform3	8:1c6281289d67	1102	#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
n0tform3	8:1c6281289d67	1103	#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
n0tform3	8:1c6281289d67	1104	#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
n0tform3	8:1c6281289d67	1105	#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
n0tform3	8:1c6281289d67	1106	#define ETH_MAC_BASE (ETH_BASE)
n0tform3	8:1c6281289d67	1107	#define ETH_MMC_BASE (ETH_BASE + 0x0100)
n0tform3	8:1c6281289d67	1108	#define ETH_PTP_BASE (ETH_BASE + 0x0700)
n0tform3	8:1c6281289d67	1109	#define ETH_DMA_BASE (ETH_BASE + 0x1000)
n0tform3	8:1c6281289d67	1110
n0tform3	8:1c6281289d67	1111	/!< AHB2 peripherals /
n0tform3	8:1c6281289d67	1112	#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
n0tform3	8:1c6281289d67	1113	#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
n0tform3	8:1c6281289d67	1114	#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
n0tform3	8:1c6281289d67	1115	#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
n0tform3	8:1c6281289d67	1116
n0tform3	8:1c6281289d67	1117	/!< FSMC Bankx registers base address /
n0tform3	8:1c6281289d67	1118	#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
n0tform3	8:1c6281289d67	1119	#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
n0tform3	8:1c6281289d67	1120	#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
n0tform3	8:1c6281289d67	1121	#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
n0tform3	8:1c6281289d67	1122	#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
n0tform3	8:1c6281289d67	1123
n0tform3	8:1c6281289d67	1124	/* Debug MCU registers base address */
n0tform3	8:1c6281289d67	1125	#define DBGMCU_BASE ((uint32_t )0xE0042000)
n0tform3	8:1c6281289d67	1126
n0tform3	8:1c6281289d67	1127	/**
n0tform3	8:1c6281289d67	1128	* @}
n0tform3	8:1c6281289d67	1129	*/
n0tform3	8:1c6281289d67	1130
n0tform3	8:1c6281289d67	1131	/** @addtogroup Peripheral_declaration
n0tform3	8:1c6281289d67	1132	* @{
n0tform3	8:1c6281289d67	1133	*/
n0tform3	8:1c6281289d67	1134	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
n0tform3	8:1c6281289d67	1135	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
n0tform3	8:1c6281289d67	1136	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
n0tform3	8:1c6281289d67	1137	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
n0tform3	8:1c6281289d67	1138	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
n0tform3	8:1c6281289d67	1139	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
n0tform3	8:1c6281289d67	1140	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
n0tform3	8:1c6281289d67	1141	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
n0tform3	8:1c6281289d67	1142	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
n0tform3	8:1c6281289d67	1143	#define RTC ((RTC_TypeDef *) RTC_BASE)
n0tform3	8:1c6281289d67	1144	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
n0tform3	8:1c6281289d67	1145	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
n0tform3	8:1c6281289d67	1146	#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
n0tform3	8:1c6281289d67	1147	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
n0tform3	8:1c6281289d67	1148	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
n0tform3	8:1c6281289d67	1149	#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
n0tform3	8:1c6281289d67	1150	#define USART2 ((USART_TypeDef *) USART2_BASE)
n0tform3	8:1c6281289d67	1151	#define USART3 ((USART_TypeDef *) USART3_BASE)
n0tform3	8:1c6281289d67	1152	#define UART4 ((USART_TypeDef *) UART4_BASE)
n0tform3	8:1c6281289d67	1153	#define UART5 ((USART_TypeDef *) UART5_BASE)
n0tform3	8:1c6281289d67	1154	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
n0tform3	8:1c6281289d67	1155	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
n0tform3	8:1c6281289d67	1156	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
n0tform3	8:1c6281289d67	1157	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
n0tform3	8:1c6281289d67	1158	#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
n0tform3	8:1c6281289d67	1159	#define PWR ((PWR_TypeDef *) PWR_BASE)
n0tform3	8:1c6281289d67	1160	#define DAC ((DAC_TypeDef *) DAC_BASE)
n0tform3	8:1c6281289d67	1161	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
n0tform3	8:1c6281289d67	1162	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
n0tform3	8:1c6281289d67	1163	#define USART1 ((USART_TypeDef *) USART1_BASE)
n0tform3	8:1c6281289d67	1164	#define USART6 ((USART_TypeDef *) USART6_BASE)
n0tform3	8:1c6281289d67	1165	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
n0tform3	8:1c6281289d67	1166	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
n0tform3	8:1c6281289d67	1167	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
n0tform3	8:1c6281289d67	1168	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
n0tform3	8:1c6281289d67	1169	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
n0tform3	8:1c6281289d67	1170	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
n0tform3	8:1c6281289d67	1171	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
n0tform3	8:1c6281289d67	1172	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
n0tform3	8:1c6281289d67	1173	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
n0tform3	8:1c6281289d67	1174	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
n0tform3	8:1c6281289d67	1175	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
n0tform3	8:1c6281289d67	1176	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
n0tform3	8:1c6281289d67	1177	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
n0tform3	8:1c6281289d67	1178	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
n0tform3	8:1c6281289d67	1179	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
n0tform3	8:1c6281289d67	1180	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
n0tform3	8:1c6281289d67	1181	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
n0tform3	8:1c6281289d67	1182	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
n0tform3	8:1c6281289d67	1183	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
n0tform3	8:1c6281289d67	1184	#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
n0tform3	8:1c6281289d67	1185	#define CRC ((CRC_TypeDef *) CRC_BASE)
n0tform3	8:1c6281289d67	1186	#define RCC ((RCC_TypeDef *) RCC_BASE)
n0tform3	8:1c6281289d67	1187	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
n0tform3	8:1c6281289d67	1188	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
n0tform3	8:1c6281289d67	1189	#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
n0tform3	8:1c6281289d67	1190	#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
n0tform3	8:1c6281289d67	1191	#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
n0tform3	8:1c6281289d67	1192	#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
n0tform3	8:1c6281289d67	1193	#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
n0tform3	8:1c6281289d67	1194	#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
n0tform3	8:1c6281289d67	1195	#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
n0tform3	8:1c6281289d67	1196	#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
n0tform3	8:1c6281289d67	1197	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
n0tform3	8:1c6281289d67	1198	#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
n0tform3	8:1c6281289d67	1199	#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
n0tform3	8:1c6281289d67	1200	#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
n0tform3	8:1c6281289d67	1201	#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
n0tform3	8:1c6281289d67	1202	#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
n0tform3	8:1c6281289d67	1203	#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
n0tform3	8:1c6281289d67	1204	#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
n0tform3	8:1c6281289d67	1205	#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
n0tform3	8:1c6281289d67	1206	#define ETH ((ETH_TypeDef *) ETH_BASE)
n0tform3	8:1c6281289d67	1207	#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
n0tform3	8:1c6281289d67	1208	#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
n0tform3	8:1c6281289d67	1209	#define HASH ((HASH_TypeDef *) HASH_BASE)
n0tform3	8:1c6281289d67	1210	#define RNG ((RNG_TypeDef *) RNG_BASE)
n0tform3	8:1c6281289d67	1211	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
n0tform3	8:1c6281289d67	1212	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
n0tform3	8:1c6281289d67	1213	#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
n0tform3	8:1c6281289d67	1214	#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
n0tform3	8:1c6281289d67	1215	#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
n0tform3	8:1c6281289d67	1216	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
n0tform3	8:1c6281289d67	1217
n0tform3	8:1c6281289d67	1218	/**
n0tform3	8:1c6281289d67	1219	* @}
n0tform3	8:1c6281289d67	1220	*/
n0tform3	8:1c6281289d67	1221
n0tform3	8:1c6281289d67	1222	/** @addtogroup Exported_constants
n0tform3	8:1c6281289d67	1223	* @{
n0tform3	8:1c6281289d67	1224	*/
n0tform3	8:1c6281289d67	1225
n0tform3	8:1c6281289d67	1226	/** @addtogroup Peripheral_Registers_Bits_Definition
n0tform3	8:1c6281289d67	1227	* @{
n0tform3	8:1c6281289d67	1228	*/
n0tform3	8:1c6281289d67	1229
n0tform3	8:1c6281289d67	1230	/******************************************************************************/
n0tform3	8:1c6281289d67	1231	/* Peripheral Registers_Bits_Definition */
n0tform3	8:1c6281289d67	1232	/******************************************************************************/
n0tform3	8:1c6281289d67	1233
n0tform3	8:1c6281289d67	1234	/******************************************************************************/
n0tform3	8:1c6281289d67	1235	/* */
n0tform3	8:1c6281289d67	1236	/* Analog to Digital Converter */
n0tform3	8:1c6281289d67	1237	/* */
n0tform3	8:1c6281289d67	1238	/******************************************************************************/
n0tform3	8:1c6281289d67	1239	/****************** Bit definition for ADC_SR register ******************/
n0tform3	8:1c6281289d67	1240	#define ADC_SR_AWD ((uint8_t)0x01) /!<Analog watchdog flag /
n0tform3	8:1c6281289d67	1241	#define ADC_SR_EOC ((uint8_t)0x02) /!<End of conversion /
n0tform3	8:1c6281289d67	1242	#define ADC_SR_JEOC ((uint8_t)0x04) /!<Injected channel end of conversion /
n0tform3	8:1c6281289d67	1243	#define ADC_SR_JSTRT ((uint8_t)0x08) /!<Injected channel Start flag /
n0tform3	8:1c6281289d67	1244	#define ADC_SR_STRT ((uint8_t)0x10) /!<Regular channel Start flag /
n0tform3	8:1c6281289d67	1245	#define ADC_SR_OVR ((uint8_t)0x20) /!<Overrun flag /
n0tform3	8:1c6281289d67	1246
n0tform3	8:1c6281289d67	1247	/***************** Bit definition for ADC_CR1 register ******************/
n0tform3	8:1c6281289d67	1248	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!<AWDCH[4:0] bits (Analog watchdog channel select bits) /
n0tform3	8:1c6281289d67	1249	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	1250	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	1251	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	1252	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	1253	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	1254	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!<Interrupt enable for EOC /
n0tform3	8:1c6281289d67	1255	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!<AAnalog Watchdog interrupt enable /
n0tform3	8:1c6281289d67	1256	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!<Interrupt enable for injected channels /
n0tform3	8:1c6281289d67	1257	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!<Scan mode /
n0tform3	8:1c6281289d67	1258	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!<Enable the watchdog on a single channel in scan mode /
n0tform3	8:1c6281289d67	1259	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!<Automatic injected group conversion /
n0tform3	8:1c6281289d67	1260	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!<Discontinuous mode on regular channels /
n0tform3	8:1c6281289d67	1261	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!<Discontinuous mode on injected channels /
n0tform3	8:1c6281289d67	1262	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!<DISCNUM[2:0] bits (Discontinuous mode channel count) /
n0tform3	8:1c6281289d67	1263	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1264	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1265	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1266	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!<Analog watchdog enable on injected channels /
n0tform3	8:1c6281289d67	1267	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!<Analog watchdog enable on regular channels /
n0tform3	8:1c6281289d67	1268	#define ADC_CR1_RES ((uint32_t)0x03000000) /!<RES[2:0] bits (Resolution) /
n0tform3	8:1c6281289d67	1269	#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1270	#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1271	#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /!<overrun interrupt enable /
n0tform3	8:1c6281289d67	1272
n0tform3	8:1c6281289d67	1273	/***************** Bit definition for ADC_CR2 register ******************/
n0tform3	8:1c6281289d67	1274	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!<A/D Converter ON / OFF /
n0tform3	8:1c6281289d67	1275	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!<Continuous Conversion /
n0tform3	8:1c6281289d67	1276	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!<Direct Memory access mode /
n0tform3	8:1c6281289d67	1277	#define ADC_CR2_DDS ((uint32_t)0x00000200) /!<DMA disable selection (Single ADC) /
n0tform3	8:1c6281289d67	1278	#define ADC_CR2_EOCS ((uint32_t)0x00000400) /!<End of conversion selection /
n0tform3	8:1c6281289d67	1279	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!<Data Alignment /
n0tform3	8:1c6281289d67	1280	#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /!<JEXTSEL[3:0] bits (External event select for injected group) /
n0tform3	8:1c6281289d67	1281	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1282	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1283	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1284	#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1285	#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) /
n0tform3	8:1c6281289d67	1286	#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1287	#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1288	#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /!<Start Conversion of injected channels /
n0tform3	8:1c6281289d67	1289	#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /!<EXTSEL[3:0] bits (External Event Select for regular group) /
n0tform3	8:1c6281289d67	1290	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1291	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1292	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1293	#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1294	#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) /
n0tform3	8:1c6281289d67	1295	#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1296	#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1297	#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /!<Start Conversion of regular channels /
n0tform3	8:1c6281289d67	1298
n0tform3	8:1c6281289d67	1299	/**************** Bit definition for ADC_SMPR1 register *****************/
n0tform3	8:1c6281289d67	1300	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!<SMP10[2:0] bits (Channel 10 Sample time selection) /
n0tform3	8:1c6281289d67	1301	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	1302	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	1303	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	1304	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!<SMP11[2:0] bits (Channel 11 Sample time selection) /
n0tform3	8:1c6281289d67	1305	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!<Bit 0 /
n0tform3	8:1c6281289d67	1306	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!<Bit 1 /
n0tform3	8:1c6281289d67	1307	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!<Bit 2 /
n0tform3	8:1c6281289d67	1308	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!<SMP12[2:0] bits (Channel 12 Sample time selection) /
n0tform3	8:1c6281289d67	1309	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!<Bit 0 /
n0tform3	8:1c6281289d67	1310	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!<Bit 1 /
n0tform3	8:1c6281289d67	1311	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!<Bit 2 /
n0tform3	8:1c6281289d67	1312	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!<SMP13[2:0] bits (Channel 13 Sample time selection) /
n0tform3	8:1c6281289d67	1313	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!<Bit 0 /
n0tform3	8:1c6281289d67	1314	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!<Bit 1 /
n0tform3	8:1c6281289d67	1315	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!<Bit 2 /
n0tform3	8:1c6281289d67	1316	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!<SMP14[2:0] bits (Channel 14 Sample time selection) /
n0tform3	8:1c6281289d67	1317	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1318	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1319	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1320	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!<SMP15[2:0] bits (Channel 15 Sample time selection) /
n0tform3	8:1c6281289d67	1321	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1322	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1323	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1324	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!<SMP16[2:0] bits (Channel 16 Sample time selection) /
n0tform3	8:1c6281289d67	1325	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1326	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1327	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1328	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!<SMP17[2:0] bits (Channel 17 Sample time selection) /
n0tform3	8:1c6281289d67	1329	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1330	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1331	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1332	#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /!<SMP18[2:0] bits (Channel 18 Sample time selection) /
n0tform3	8:1c6281289d67	1333	#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1334	#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1335	#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1336
n0tform3	8:1c6281289d67	1337	/**************** Bit definition for ADC_SMPR2 register *****************/
n0tform3	8:1c6281289d67	1338	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!<SMP0[2:0] bits (Channel 0 Sample time selection) /
n0tform3	8:1c6281289d67	1339	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	1340	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	1341	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	1342	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!<SMP1[2:0] bits (Channel 1 Sample time selection) /
n0tform3	8:1c6281289d67	1343	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!<Bit 0 /
n0tform3	8:1c6281289d67	1344	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!<Bit 1 /
n0tform3	8:1c6281289d67	1345	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!<Bit 2 /
n0tform3	8:1c6281289d67	1346	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!<SMP2[2:0] bits (Channel 2 Sample time selection) /
n0tform3	8:1c6281289d67	1347	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!<Bit 0 /
n0tform3	8:1c6281289d67	1348	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!<Bit 1 /
n0tform3	8:1c6281289d67	1349	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!<Bit 2 /
n0tform3	8:1c6281289d67	1350	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!<SMP3[2:0] bits (Channel 3 Sample time selection) /
n0tform3	8:1c6281289d67	1351	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!<Bit 0 /
n0tform3	8:1c6281289d67	1352	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!<Bit 1 /
n0tform3	8:1c6281289d67	1353	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!<Bit 2 /
n0tform3	8:1c6281289d67	1354	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!<SMP4[2:0] bits (Channel 4 Sample time selection) /
n0tform3	8:1c6281289d67	1355	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1356	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1357	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1358	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!<SMP5[2:0] bits (Channel 5 Sample time selection) /
n0tform3	8:1c6281289d67	1359	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1360	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1361	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1362	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!<SMP6[2:0] bits (Channel 6 Sample time selection) /
n0tform3	8:1c6281289d67	1363	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1364	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1365	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1366	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!<SMP7[2:0] bits (Channel 7 Sample time selection) /
n0tform3	8:1c6281289d67	1367	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1368	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1369	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1370	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!<SMP8[2:0] bits (Channel 8 Sample time selection) /
n0tform3	8:1c6281289d67	1371	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1372	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1373	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1374	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!<SMP9[2:0] bits (Channel 9 Sample time selection) /
n0tform3	8:1c6281289d67	1375	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1376	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1377	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1378
n0tform3	8:1c6281289d67	1379	/**************** Bit definition for ADC_JOFR1 register *****************/
n0tform3	8:1c6281289d67	1380	#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /!<Data offset for injected channel 1 /
n0tform3	8:1c6281289d67	1381
n0tform3	8:1c6281289d67	1382	/**************** Bit definition for ADC_JOFR2 register *****************/
n0tform3	8:1c6281289d67	1383	#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /!<Data offset for injected channel 2 /
n0tform3	8:1c6281289d67	1384
n0tform3	8:1c6281289d67	1385	/**************** Bit definition for ADC_JOFR3 register *****************/
n0tform3	8:1c6281289d67	1386	#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /!<Data offset for injected channel 3 /
n0tform3	8:1c6281289d67	1387
n0tform3	8:1c6281289d67	1388	/**************** Bit definition for ADC_JOFR4 register *****************/
n0tform3	8:1c6281289d67	1389	#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /!<Data offset for injected channel 4 /
n0tform3	8:1c6281289d67	1390
n0tform3	8:1c6281289d67	1391	/***************** Bit definition for ADC_HTR register ******************/
n0tform3	8:1c6281289d67	1392	#define ADC_HTR_HT ((uint16_t)0x0FFF) /!<Analog watchdog high threshold /
n0tform3	8:1c6281289d67	1393
n0tform3	8:1c6281289d67	1394	/***************** Bit definition for ADC_LTR register ******************/
n0tform3	8:1c6281289d67	1395	#define ADC_LTR_LT ((uint16_t)0x0FFF) /!<Analog watchdog low threshold /
n0tform3	8:1c6281289d67	1396
n0tform3	8:1c6281289d67	1397	/***************** Bit definition for ADC_SQR1 register *****************/
n0tform3	8:1c6281289d67	1398	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!<SQ13[4:0] bits (13th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1399	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	1400	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	1401	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	1402	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	1403	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	1404	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!<SQ14[4:0] bits (14th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1405	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!<Bit 0 /
n0tform3	8:1c6281289d67	1406	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!<Bit 1 /
n0tform3	8:1c6281289d67	1407	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!<Bit 2 /
n0tform3	8:1c6281289d67	1408	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!<Bit 3 /
n0tform3	8:1c6281289d67	1409	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!<Bit 4 /
n0tform3	8:1c6281289d67	1410	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!<SQ15[4:0] bits (15th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1411	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!<Bit 0 /
n0tform3	8:1c6281289d67	1412	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!<Bit 1 /
n0tform3	8:1c6281289d67	1413	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1414	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1415	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1416	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!<SQ16[4:0] bits (16th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1417	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1418	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1419	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1420	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1421	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1422	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!<L[3:0] bits (Regular channel sequence length) /
n0tform3	8:1c6281289d67	1423	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1424	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1425	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1426	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1427
n0tform3	8:1c6281289d67	1428	/***************** Bit definition for ADC_SQR2 register *****************/
n0tform3	8:1c6281289d67	1429	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!<SQ7[4:0] bits (7th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1430	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	1431	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	1432	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	1433	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	1434	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	1435	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!<SQ8[4:0] bits (8th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1436	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!<Bit 0 /
n0tform3	8:1c6281289d67	1437	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!<Bit 1 /
n0tform3	8:1c6281289d67	1438	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!<Bit 2 /
n0tform3	8:1c6281289d67	1439	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!<Bit 3 /
n0tform3	8:1c6281289d67	1440	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!<Bit 4 /
n0tform3	8:1c6281289d67	1441	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!<SQ9[4:0] bits (9th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1442	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!<Bit 0 /
n0tform3	8:1c6281289d67	1443	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!<Bit 1 /
n0tform3	8:1c6281289d67	1444	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1445	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1446	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1447	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!<SQ10[4:0] bits (10th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1448	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1449	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1450	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1451	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1452	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1453	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!<SQ11[4:0] bits (11th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1454	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1455	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1456	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1457	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1458	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1459	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!<SQ12[4:0] bits (12th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1460	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1461	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1462	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1463	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1464	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1465
n0tform3	8:1c6281289d67	1466	/***************** Bit definition for ADC_SQR3 register *****************/
n0tform3	8:1c6281289d67	1467	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!<SQ1[4:0] bits (1st conversion in regular sequence) /
n0tform3	8:1c6281289d67	1468	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	1469	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	1470	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	1471	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	1472	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	1473	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!<SQ2[4:0] bits (2nd conversion in regular sequence) /
n0tform3	8:1c6281289d67	1474	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!<Bit 0 /
n0tform3	8:1c6281289d67	1475	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!<Bit 1 /
n0tform3	8:1c6281289d67	1476	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!<Bit 2 /
n0tform3	8:1c6281289d67	1477	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!<Bit 3 /
n0tform3	8:1c6281289d67	1478	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!<Bit 4 /
n0tform3	8:1c6281289d67	1479	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!<SQ3[4:0] bits (3rd conversion in regular sequence) /
n0tform3	8:1c6281289d67	1480	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!<Bit 0 /
n0tform3	8:1c6281289d67	1481	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!<Bit 1 /
n0tform3	8:1c6281289d67	1482	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1483	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1484	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1485	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!<SQ4[4:0] bits (4th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1486	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1487	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1488	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1489	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1490	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1491	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!<SQ5[4:0] bits (5th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1492	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1493	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1494	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1495	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1496	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1497	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!<SQ6[4:0] bits (6th conversion in regular sequence) /
n0tform3	8:1c6281289d67	1498	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1499	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1500	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1501	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1502	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1503
n0tform3	8:1c6281289d67	1504	/***************** Bit definition for ADC_JSQR register *****************/
n0tform3	8:1c6281289d67	1505	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!<JSQ1[4:0] bits (1st conversion in injected sequence) /
n0tform3	8:1c6281289d67	1506	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	1507	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	1508	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	1509	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	1510	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	1511	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!<JSQ2[4:0] bits (2nd conversion in injected sequence) /
n0tform3	8:1c6281289d67	1512	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!<Bit 0 /
n0tform3	8:1c6281289d67	1513	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!<Bit 1 /
n0tform3	8:1c6281289d67	1514	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!<Bit 2 /
n0tform3	8:1c6281289d67	1515	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!<Bit 3 /
n0tform3	8:1c6281289d67	1516	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!<Bit 4 /
n0tform3	8:1c6281289d67	1517	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!<JSQ3[4:0] bits (3rd conversion in injected sequence) /
n0tform3	8:1c6281289d67	1518	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!<Bit 0 /
n0tform3	8:1c6281289d67	1519	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!<Bit 1 /
n0tform3	8:1c6281289d67	1520	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1521	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1522	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1523	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!<JSQ4[4:0] bits (4th conversion in injected sequence) /
n0tform3	8:1c6281289d67	1524	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1525	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1526	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!<Bit 2 /
n0tform3	8:1c6281289d67	1527	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!<Bit 3 /
n0tform3	8:1c6281289d67	1528	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!<Bit 4 /
n0tform3	8:1c6281289d67	1529	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!<JL[1:0] bits (Injected Sequence length) /
n0tform3	8:1c6281289d67	1530	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1531	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1532
n0tform3	8:1c6281289d67	1533	/***************** Bit definition for ADC_JDR1 register *****************/
n0tform3	8:1c6281289d67	1534	#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /!<Injected data /
n0tform3	8:1c6281289d67	1535
n0tform3	8:1c6281289d67	1536	/***************** Bit definition for ADC_JDR2 register *****************/
n0tform3	8:1c6281289d67	1537	#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /!<Injected data /
n0tform3	8:1c6281289d67	1538
n0tform3	8:1c6281289d67	1539	/***************** Bit definition for ADC_JDR3 register *****************/
n0tform3	8:1c6281289d67	1540	#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /!<Injected data /
n0tform3	8:1c6281289d67	1541
n0tform3	8:1c6281289d67	1542	/***************** Bit definition for ADC_JDR4 register *****************/
n0tform3	8:1c6281289d67	1543	#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /!<Injected data /
n0tform3	8:1c6281289d67	1544
n0tform3	8:1c6281289d67	1545	/****************** Bit definition for ADC_DR register ******************/
n0tform3	8:1c6281289d67	1546	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!<Regular data /
n0tform3	8:1c6281289d67	1547	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!<ADC2 data /
n0tform3	8:1c6281289d67	1548
n0tform3	8:1c6281289d67	1549	/***************** Bit definition for ADC_CSR register ******************/
n0tform3	8:1c6281289d67	1550	#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /!<ADC1 Analog watchdog flag /
n0tform3	8:1c6281289d67	1551	#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /!<ADC1 End of conversion /
n0tform3	8:1c6281289d67	1552	#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /!<ADC1 Injected channel end of conversion /
n0tform3	8:1c6281289d67	1553	#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /!<ADC1 Injected channel Start flag /
n0tform3	8:1c6281289d67	1554	#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /!<ADC1 Regular channel Start flag /
n0tform3	8:1c6281289d67	1555	#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /!<ADC1 DMA overrun flag /
n0tform3	8:1c6281289d67	1556	#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /!<ADC2 Analog watchdog flag /
n0tform3	8:1c6281289d67	1557	#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /!<ADC2 End of conversion /
n0tform3	8:1c6281289d67	1558	#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /!<ADC2 Injected channel end of conversion /
n0tform3	8:1c6281289d67	1559	#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /!<ADC2 Injected channel Start flag /
n0tform3	8:1c6281289d67	1560	#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /!<ADC2 Regular channel Start flag /
n0tform3	8:1c6281289d67	1561	#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /!<ADC2 DMA overrun flag /
n0tform3	8:1c6281289d67	1562	#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /!<ADC3 Analog watchdog flag /
n0tform3	8:1c6281289d67	1563	#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /!<ADC3 End of conversion /
n0tform3	8:1c6281289d67	1564	#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /!<ADC3 Injected channel end of conversion /
n0tform3	8:1c6281289d67	1565	#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /!<ADC3 Injected channel Start flag /
n0tform3	8:1c6281289d67	1566	#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /!<ADC3 Regular channel Start flag /
n0tform3	8:1c6281289d67	1567	#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /!<ADC3 DMA overrun flag /
n0tform3	8:1c6281289d67	1568
n0tform3	8:1c6281289d67	1569	/***************** Bit definition for ADC_CCR register ******************/
n0tform3	8:1c6281289d67	1570	#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /!<MULTI[4:0] bits (Multi-ADC mode selection) /
n0tform3	8:1c6281289d67	1571	#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	1572	#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	1573	#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	1574	#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	1575	#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	1576	#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /!<DELAY[3:0] bits (Delay between 2 sampling phases) /
n0tform3	8:1c6281289d67	1577	#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	1578	#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	1579	#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	1580	#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	1581	#define ADC_CCR_DDS ((uint32_t)0x00002000) /!<DMA disable selection (Multi-ADC mode) /
n0tform3	8:1c6281289d67	1582	#define ADC_CCR_DMA ((uint32_t)0x0000C000) /!<DMA[1:0] bits (Direct Memory Access mode for multimode) /
n0tform3	8:1c6281289d67	1583	#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1584	#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1585	#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /!<ADCPRE[1:0] bits (ADC prescaler) /
n0tform3	8:1c6281289d67	1586	#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	1587	#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	1588	#define ADC_CCR_VBATE ((uint32_t)0x00400000) /!<VBAT Enable /
n0tform3	8:1c6281289d67	1589	#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /!<Temperature Sensor and VREFINT Enable /
n0tform3	8:1c6281289d67	1590
n0tform3	8:1c6281289d67	1591	/***************** Bit definition for ADC_CDR register ******************/
n0tform3	8:1c6281289d67	1592	#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /!<1st data of a pair of regular conversions /
n0tform3	8:1c6281289d67	1593	#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /!<2nd data of a pair of regular conversions /
n0tform3	8:1c6281289d67	1594
n0tform3	8:1c6281289d67	1595	/******************************************************************************/
n0tform3	8:1c6281289d67	1596	/* */
n0tform3	8:1c6281289d67	1597	/* Controller Area Network */
n0tform3	8:1c6281289d67	1598	/* */
n0tform3	8:1c6281289d67	1599	/******************************************************************************/
n0tform3	8:1c6281289d67	1600	/!<CAN control and status registers /
n0tform3	8:1c6281289d67	1601	/***************** Bit definition for CAN_MCR register ******************/
n0tform3	8:1c6281289d67	1602	#define CAN_MCR_INRQ ((uint16_t)0x0001) /!<Initialization Request /
n0tform3	8:1c6281289d67	1603	#define CAN_MCR_SLEEP ((uint16_t)0x0002) /!<Sleep Mode Request /
n0tform3	8:1c6281289d67	1604	#define CAN_MCR_TXFP ((uint16_t)0x0004) /!<Transmit FIFO Priority /
n0tform3	8:1c6281289d67	1605	#define CAN_MCR_RFLM ((uint16_t)0x0008) /!<Receive FIFO Locked Mode /
n0tform3	8:1c6281289d67	1606	#define CAN_MCR_NART ((uint16_t)0x0010) /!<No Automatic Retransmission /
n0tform3	8:1c6281289d67	1607	#define CAN_MCR_AWUM ((uint16_t)0x0020) /!<Automatic Wakeup Mode /
n0tform3	8:1c6281289d67	1608	#define CAN_MCR_ABOM ((uint16_t)0x0040) /!<Automatic Bus-Off Management /
n0tform3	8:1c6281289d67	1609	#define CAN_MCR_TTCM ((uint16_t)0x0080) /!<Time Triggered Communication Mode /
n0tform3	8:1c6281289d67	1610	#define CAN_MCR_RESET ((uint16_t)0x8000) /!<bxCAN software master reset /
n0tform3	8:1c6281289d67	1611
n0tform3	8:1c6281289d67	1612	/***************** Bit definition for CAN_MSR register ******************/
n0tform3	8:1c6281289d67	1613	#define CAN_MSR_INAK ((uint16_t)0x0001) /!<Initialization Acknowledge /
n0tform3	8:1c6281289d67	1614	#define CAN_MSR_SLAK ((uint16_t)0x0002) /!<Sleep Acknowledge /
n0tform3	8:1c6281289d67	1615	#define CAN_MSR_ERRI ((uint16_t)0x0004) /!<Error Interrupt /
n0tform3	8:1c6281289d67	1616	#define CAN_MSR_WKUI ((uint16_t)0x0008) /!<Wakeup Interrupt /
n0tform3	8:1c6281289d67	1617	#define CAN_MSR_SLAKI ((uint16_t)0x0010) /!<Sleep Acknowledge Interrupt /
n0tform3	8:1c6281289d67	1618	#define CAN_MSR_TXM ((uint16_t)0x0100) /!<Transmit Mode /
n0tform3	8:1c6281289d67	1619	#define CAN_MSR_RXM ((uint16_t)0x0200) /!<Receive Mode /
n0tform3	8:1c6281289d67	1620	#define CAN_MSR_SAMP ((uint16_t)0x0400) /!<Last Sample Point /
n0tform3	8:1c6281289d67	1621	#define CAN_MSR_RX ((uint16_t)0x0800) /!<CAN Rx Signal /
n0tform3	8:1c6281289d67	1622
n0tform3	8:1c6281289d67	1623	/***************** Bit definition for CAN_TSR register ******************/
n0tform3	8:1c6281289d67	1624	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
n0tform3	8:1c6281289d67	1625	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
n0tform3	8:1c6281289d67	1626	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
n0tform3	8:1c6281289d67	1627	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
n0tform3	8:1c6281289d67	1628	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
n0tform3	8:1c6281289d67	1629	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
n0tform3	8:1c6281289d67	1630	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
n0tform3	8:1c6281289d67	1631	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
n0tform3	8:1c6281289d67	1632	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
n0tform3	8:1c6281289d67	1633	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
n0tform3	8:1c6281289d67	1634	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
n0tform3	8:1c6281289d67	1635	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
n0tform3	8:1c6281289d67	1636	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
n0tform3	8:1c6281289d67	1637	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
n0tform3	8:1c6281289d67	1638	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
n0tform3	8:1c6281289d67	1639	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
n0tform3	8:1c6281289d67	1640
n0tform3	8:1c6281289d67	1641	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
n0tform3	8:1c6281289d67	1642	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
n0tform3	8:1c6281289d67	1643	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
n0tform3	8:1c6281289d67	1644	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
n0tform3	8:1c6281289d67	1645
n0tform3	8:1c6281289d67	1646	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
n0tform3	8:1c6281289d67	1647	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
n0tform3	8:1c6281289d67	1648	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
n0tform3	8:1c6281289d67	1649	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
n0tform3	8:1c6281289d67	1650
n0tform3	8:1c6281289d67	1651	/***************** Bit definition for CAN_RF0R register *****************/
n0tform3	8:1c6281289d67	1652	#define CAN_RF0R_FMP0 ((uint8_t)0x03) /!<FIFO 0 Message Pending /
n0tform3	8:1c6281289d67	1653	#define CAN_RF0R_FULL0 ((uint8_t)0x08) /!<FIFO 0 Full /
n0tform3	8:1c6281289d67	1654	#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /!<FIFO 0 Overrun /
n0tform3	8:1c6281289d67	1655	#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /!<Release FIFO 0 Output Mailbox /
n0tform3	8:1c6281289d67	1656
n0tform3	8:1c6281289d67	1657	/***************** Bit definition for CAN_RF1R register *****************/
n0tform3	8:1c6281289d67	1658	#define CAN_RF1R_FMP1 ((uint8_t)0x03) /!<FIFO 1 Message Pending /
n0tform3	8:1c6281289d67	1659	#define CAN_RF1R_FULL1 ((uint8_t)0x08) /!<FIFO 1 Full /
n0tform3	8:1c6281289d67	1660	#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /!<FIFO 1 Overrun /
n0tform3	8:1c6281289d67	1661	#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /!<Release FIFO 1 Output Mailbox /
n0tform3	8:1c6281289d67	1662
n0tform3	8:1c6281289d67	1663	/****************** Bit definition for CAN_IER register *****************/
n0tform3	8:1c6281289d67	1664	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
n0tform3	8:1c6281289d67	1665	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
n0tform3	8:1c6281289d67	1666	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
n0tform3	8:1c6281289d67	1667	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
n0tform3	8:1c6281289d67	1668	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
n0tform3	8:1c6281289d67	1669	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
n0tform3	8:1c6281289d67	1670	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
n0tform3	8:1c6281289d67	1671	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
n0tform3	8:1c6281289d67	1672	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
n0tform3	8:1c6281289d67	1673	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
n0tform3	8:1c6281289d67	1674	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
n0tform3	8:1c6281289d67	1675	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
n0tform3	8:1c6281289d67	1676	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
n0tform3	8:1c6281289d67	1677	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
n0tform3	8:1c6281289d67	1678
n0tform3	8:1c6281289d67	1679	/****************** Bit definition for CAN_ESR register *****************/
n0tform3	8:1c6281289d67	1680	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
n0tform3	8:1c6281289d67	1681	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
n0tform3	8:1c6281289d67	1682	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
n0tform3	8:1c6281289d67	1683
n0tform3	8:1c6281289d67	1684	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
n0tform3	8:1c6281289d67	1685	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	1686	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	1687	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	1688
n0tform3	8:1c6281289d67	1689	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
n0tform3	8:1c6281289d67	1690	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
n0tform3	8:1c6281289d67	1691
n0tform3	8:1c6281289d67	1692	/***************** Bit definition for CAN_BTR register ******************/
n0tform3	8:1c6281289d67	1693	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
n0tform3	8:1c6281289d67	1694	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
n0tform3	8:1c6281289d67	1695	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
n0tform3	8:1c6281289d67	1696	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
n0tform3	8:1c6281289d67	1697	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
n0tform3	8:1c6281289d67	1698	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
n0tform3	8:1c6281289d67	1699
n0tform3	8:1c6281289d67	1700	/!<Mailbox registers /
n0tform3	8:1c6281289d67	1701	/**************** Bit definition for CAN_TI0R register ******************/
n0tform3	8:1c6281289d67	1702	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
n0tform3	8:1c6281289d67	1703	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
n0tform3	8:1c6281289d67	1704	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
n0tform3	8:1c6281289d67	1705	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
n0tform3	8:1c6281289d67	1706	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
n0tform3	8:1c6281289d67	1707
n0tform3	8:1c6281289d67	1708	/**************** Bit definition for CAN_TDT0R register *****************/
n0tform3	8:1c6281289d67	1709	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
n0tform3	8:1c6281289d67	1710	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
n0tform3	8:1c6281289d67	1711	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
n0tform3	8:1c6281289d67	1712
n0tform3	8:1c6281289d67	1713	/**************** Bit definition for CAN_TDL0R register *****************/
n0tform3	8:1c6281289d67	1714	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
n0tform3	8:1c6281289d67	1715	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
n0tform3	8:1c6281289d67	1716	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
n0tform3	8:1c6281289d67	1717	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
n0tform3	8:1c6281289d67	1718
n0tform3	8:1c6281289d67	1719	/**************** Bit definition for CAN_TDH0R register *****************/
n0tform3	8:1c6281289d67	1720	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
n0tform3	8:1c6281289d67	1721	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
n0tform3	8:1c6281289d67	1722	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
n0tform3	8:1c6281289d67	1723	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
n0tform3	8:1c6281289d67	1724
n0tform3	8:1c6281289d67	1725	/***************** Bit definition for CAN_TI1R register *****************/
n0tform3	8:1c6281289d67	1726	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
n0tform3	8:1c6281289d67	1727	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
n0tform3	8:1c6281289d67	1728	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
n0tform3	8:1c6281289d67	1729	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
n0tform3	8:1c6281289d67	1730	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
n0tform3	8:1c6281289d67	1731
n0tform3	8:1c6281289d67	1732	/***************** Bit definition for CAN_TDT1R register ****************/
n0tform3	8:1c6281289d67	1733	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
n0tform3	8:1c6281289d67	1734	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
n0tform3	8:1c6281289d67	1735	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
n0tform3	8:1c6281289d67	1736
n0tform3	8:1c6281289d67	1737	/***************** Bit definition for CAN_TDL1R register ****************/
n0tform3	8:1c6281289d67	1738	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
n0tform3	8:1c6281289d67	1739	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
n0tform3	8:1c6281289d67	1740	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
n0tform3	8:1c6281289d67	1741	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
n0tform3	8:1c6281289d67	1742
n0tform3	8:1c6281289d67	1743	/***************** Bit definition for CAN_TDH1R register ****************/
n0tform3	8:1c6281289d67	1744	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
n0tform3	8:1c6281289d67	1745	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
n0tform3	8:1c6281289d67	1746	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
n0tform3	8:1c6281289d67	1747	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
n0tform3	8:1c6281289d67	1748
n0tform3	8:1c6281289d67	1749	/***************** Bit definition for CAN_TI2R register *****************/
n0tform3	8:1c6281289d67	1750	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
n0tform3	8:1c6281289d67	1751	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
n0tform3	8:1c6281289d67	1752	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
n0tform3	8:1c6281289d67	1753	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
n0tform3	8:1c6281289d67	1754	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
n0tform3	8:1c6281289d67	1755
n0tform3	8:1c6281289d67	1756	/***************** Bit definition for CAN_TDT2R register ****************/
n0tform3	8:1c6281289d67	1757	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
n0tform3	8:1c6281289d67	1758	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
n0tform3	8:1c6281289d67	1759	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
n0tform3	8:1c6281289d67	1760
n0tform3	8:1c6281289d67	1761	/***************** Bit definition for CAN_TDL2R register ****************/
n0tform3	8:1c6281289d67	1762	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
n0tform3	8:1c6281289d67	1763	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
n0tform3	8:1c6281289d67	1764	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
n0tform3	8:1c6281289d67	1765	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
n0tform3	8:1c6281289d67	1766
n0tform3	8:1c6281289d67	1767	/***************** Bit definition for CAN_TDH2R register ****************/
n0tform3	8:1c6281289d67	1768	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
n0tform3	8:1c6281289d67	1769	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
n0tform3	8:1c6281289d67	1770	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
n0tform3	8:1c6281289d67	1771	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
n0tform3	8:1c6281289d67	1772
n0tform3	8:1c6281289d67	1773	/***************** Bit definition for CAN_RI0R register *****************/
n0tform3	8:1c6281289d67	1774	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
n0tform3	8:1c6281289d67	1775	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
n0tform3	8:1c6281289d67	1776	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
n0tform3	8:1c6281289d67	1777	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
n0tform3	8:1c6281289d67	1778
n0tform3	8:1c6281289d67	1779	/***************** Bit definition for CAN_RDT0R register ****************/
n0tform3	8:1c6281289d67	1780	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
n0tform3	8:1c6281289d67	1781	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
n0tform3	8:1c6281289d67	1782	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
n0tform3	8:1c6281289d67	1783
n0tform3	8:1c6281289d67	1784	/***************** Bit definition for CAN_RDL0R register ****************/
n0tform3	8:1c6281289d67	1785	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
n0tform3	8:1c6281289d67	1786	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
n0tform3	8:1c6281289d67	1787	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
n0tform3	8:1c6281289d67	1788	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
n0tform3	8:1c6281289d67	1789
n0tform3	8:1c6281289d67	1790	/***************** Bit definition for CAN_RDH0R register ****************/
n0tform3	8:1c6281289d67	1791	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
n0tform3	8:1c6281289d67	1792	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
n0tform3	8:1c6281289d67	1793	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
n0tform3	8:1c6281289d67	1794	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
n0tform3	8:1c6281289d67	1795
n0tform3	8:1c6281289d67	1796	/***************** Bit definition for CAN_RI1R register *****************/
n0tform3	8:1c6281289d67	1797	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
n0tform3	8:1c6281289d67	1798	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
n0tform3	8:1c6281289d67	1799	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
n0tform3	8:1c6281289d67	1800	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
n0tform3	8:1c6281289d67	1801
n0tform3	8:1c6281289d67	1802	/***************** Bit definition for CAN_RDT1R register ****************/
n0tform3	8:1c6281289d67	1803	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
n0tform3	8:1c6281289d67	1804	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
n0tform3	8:1c6281289d67	1805	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
n0tform3	8:1c6281289d67	1806
n0tform3	8:1c6281289d67	1807	/***************** Bit definition for CAN_RDL1R register ****************/
n0tform3	8:1c6281289d67	1808	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
n0tform3	8:1c6281289d67	1809	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
n0tform3	8:1c6281289d67	1810	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
n0tform3	8:1c6281289d67	1811	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
n0tform3	8:1c6281289d67	1812
n0tform3	8:1c6281289d67	1813	/***************** Bit definition for CAN_RDH1R register ****************/
n0tform3	8:1c6281289d67	1814	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
n0tform3	8:1c6281289d67	1815	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
n0tform3	8:1c6281289d67	1816	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
n0tform3	8:1c6281289d67	1817	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
n0tform3	8:1c6281289d67	1818
n0tform3	8:1c6281289d67	1819	/!<CAN filter registers /
n0tform3	8:1c6281289d67	1820	/***************** Bit definition for CAN_FMR register ******************/
n0tform3	8:1c6281289d67	1821	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
n0tform3	8:1c6281289d67	1822
n0tform3	8:1c6281289d67	1823	/***************** Bit definition for CAN_FM1R register *****************/
n0tform3	8:1c6281289d67	1824	#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /!<Filter Mode /
n0tform3	8:1c6281289d67	1825	#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /!<Filter Init Mode bit 0 /
n0tform3	8:1c6281289d67	1826	#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /!<Filter Init Mode bit 1 /
n0tform3	8:1c6281289d67	1827	#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /!<Filter Init Mode bit 2 /
n0tform3	8:1c6281289d67	1828	#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /!<Filter Init Mode bit 3 /
n0tform3	8:1c6281289d67	1829	#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /!<Filter Init Mode bit 4 /
n0tform3	8:1c6281289d67	1830	#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /!<Filter Init Mode bit 5 /
n0tform3	8:1c6281289d67	1831	#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /!<Filter Init Mode bit 6 /
n0tform3	8:1c6281289d67	1832	#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /!<Filter Init Mode bit 7 /
n0tform3	8:1c6281289d67	1833	#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /!<Filter Init Mode bit 8 /
n0tform3	8:1c6281289d67	1834	#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /!<Filter Init Mode bit 9 /
n0tform3	8:1c6281289d67	1835	#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /!<Filter Init Mode bit 10 /
n0tform3	8:1c6281289d67	1836	#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /!<Filter Init Mode bit 11 /
n0tform3	8:1c6281289d67	1837	#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /!<Filter Init Mode bit 12 /
n0tform3	8:1c6281289d67	1838	#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /!<Filter Init Mode bit 13 /
n0tform3	8:1c6281289d67	1839
n0tform3	8:1c6281289d67	1840	/***************** Bit definition for CAN_FS1R register *****************/
n0tform3	8:1c6281289d67	1841	#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /!<Filter Scale Configuration /
n0tform3	8:1c6281289d67	1842	#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /!<Filter Scale Configuration bit 0 /
n0tform3	8:1c6281289d67	1843	#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /!<Filter Scale Configuration bit 1 /
n0tform3	8:1c6281289d67	1844	#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /!<Filter Scale Configuration bit 2 /
n0tform3	8:1c6281289d67	1845	#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /!<Filter Scale Configuration bit 3 /
n0tform3	8:1c6281289d67	1846	#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /!<Filter Scale Configuration bit 4 /
n0tform3	8:1c6281289d67	1847	#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /!<Filter Scale Configuration bit 5 /
n0tform3	8:1c6281289d67	1848	#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /!<Filter Scale Configuration bit 6 /
n0tform3	8:1c6281289d67	1849	#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /!<Filter Scale Configuration bit 7 /
n0tform3	8:1c6281289d67	1850	#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /!<Filter Scale Configuration bit 8 /
n0tform3	8:1c6281289d67	1851	#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /!<Filter Scale Configuration bit 9 /
n0tform3	8:1c6281289d67	1852	#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /!<Filter Scale Configuration bit 10 /
n0tform3	8:1c6281289d67	1853	#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /!<Filter Scale Configuration bit 11 /
n0tform3	8:1c6281289d67	1854	#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /!<Filter Scale Configuration bit 12 /
n0tform3	8:1c6281289d67	1855	#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /!<Filter Scale Configuration bit 13 /
n0tform3	8:1c6281289d67	1856
n0tform3	8:1c6281289d67	1857	/**************** Bit definition for CAN_FFA1R register *****************/
n0tform3	8:1c6281289d67	1858	#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /!<Filter FIFO Assignment /
n0tform3	8:1c6281289d67	1859	#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /!<Filter FIFO Assignment for Filter 0 /
n0tform3	8:1c6281289d67	1860	#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /!<Filter FIFO Assignment for Filter 1 /
n0tform3	8:1c6281289d67	1861	#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /!<Filter FIFO Assignment for Filter 2 /
n0tform3	8:1c6281289d67	1862	#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /!<Filter FIFO Assignment for Filter 3 /
n0tform3	8:1c6281289d67	1863	#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /!<Filter FIFO Assignment for Filter 4 /
n0tform3	8:1c6281289d67	1864	#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /!<Filter FIFO Assignment for Filter 5 /
n0tform3	8:1c6281289d67	1865	#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /!<Filter FIFO Assignment for Filter 6 /
n0tform3	8:1c6281289d67	1866	#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /!<Filter FIFO Assignment for Filter 7 /
n0tform3	8:1c6281289d67	1867	#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /!<Filter FIFO Assignment for Filter 8 /
n0tform3	8:1c6281289d67	1868	#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /!<Filter FIFO Assignment for Filter 9 /
n0tform3	8:1c6281289d67	1869	#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /!<Filter FIFO Assignment for Filter 10 /
n0tform3	8:1c6281289d67	1870	#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /!<Filter FIFO Assignment for Filter 11 /
n0tform3	8:1c6281289d67	1871	#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /!<Filter FIFO Assignment for Filter 12 /
n0tform3	8:1c6281289d67	1872	#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /!<Filter FIFO Assignment for Filter 13 /
n0tform3	8:1c6281289d67	1873
n0tform3	8:1c6281289d67	1874	/***************** Bit definition for CAN_FA1R register *****************/
n0tform3	8:1c6281289d67	1875	#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /!<Filter Active /
n0tform3	8:1c6281289d67	1876	#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /!<Filter 0 Active /
n0tform3	8:1c6281289d67	1877	#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /!<Filter 1 Active /
n0tform3	8:1c6281289d67	1878	#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /!<Filter 2 Active /
n0tform3	8:1c6281289d67	1879	#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /!<Filter 3 Active /
n0tform3	8:1c6281289d67	1880	#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /!<Filter 4 Active /
n0tform3	8:1c6281289d67	1881	#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /!<Filter 5 Active /
n0tform3	8:1c6281289d67	1882	#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /!<Filter 6 Active /
n0tform3	8:1c6281289d67	1883	#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /!<Filter 7 Active /
n0tform3	8:1c6281289d67	1884	#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /!<Filter 8 Active /
n0tform3	8:1c6281289d67	1885	#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /!<Filter 9 Active /
n0tform3	8:1c6281289d67	1886	#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /!<Filter 10 Active /
n0tform3	8:1c6281289d67	1887	#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /!<Filter 11 Active /
n0tform3	8:1c6281289d67	1888	#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /!<Filter 12 Active /
n0tform3	8:1c6281289d67	1889	#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /!<Filter 13 Active /
n0tform3	8:1c6281289d67	1890
n0tform3	8:1c6281289d67	1891	/***************** Bit definition for CAN_F0R1 register *****************/
n0tform3	8:1c6281289d67	1892	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	1893	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	1894	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	1895	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	1896	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	1897	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	1898	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	1899	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	1900	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	1901	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	1902	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	1903	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	1904	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	1905	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	1906	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	1907	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	1908	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	1909	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	1910	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	1911	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	1912	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	1913	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	1914	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	1915	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	1916	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	1917	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	1918	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	1919	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	1920	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	1921	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	1922	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	1923	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	1924
n0tform3	8:1c6281289d67	1925	/***************** Bit definition for CAN_F1R1 register *****************/
n0tform3	8:1c6281289d67	1926	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	1927	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	1928	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	1929	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	1930	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	1931	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	1932	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	1933	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	1934	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	1935	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	1936	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	1937	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	1938	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	1939	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	1940	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	1941	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	1942	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	1943	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	1944	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	1945	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	1946	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	1947	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	1948	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	1949	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	1950	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	1951	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	1952	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	1953	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	1954	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	1955	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	1956	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	1957	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	1958
n0tform3	8:1c6281289d67	1959	/***************** Bit definition for CAN_F2R1 register *****************/
n0tform3	8:1c6281289d67	1960	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	1961	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	1962	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	1963	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	1964	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	1965	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	1966	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	1967	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	1968	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	1969	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	1970	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	1971	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	1972	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	1973	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	1974	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	1975	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	1976	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	1977	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	1978	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	1979	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	1980	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	1981	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	1982	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	1983	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	1984	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	1985	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	1986	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	1987	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	1988	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	1989	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	1990	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	1991	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	1992
n0tform3	8:1c6281289d67	1993	/***************** Bit definition for CAN_F3R1 register *****************/
n0tform3	8:1c6281289d67	1994	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	1995	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	1996	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	1997	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	1998	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	1999	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2000	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2001	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2002	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2003	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2004	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2005	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2006	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2007	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2008	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2009	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2010	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2011	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2012	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2013	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2014	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2015	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2016	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2017	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2018	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2019	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2020	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2021	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2022	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2023	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2024	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2025	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2026
n0tform3	8:1c6281289d67	2027	/***************** Bit definition for CAN_F4R1 register *****************/
n0tform3	8:1c6281289d67	2028	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2029	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2030	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2031	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2032	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2033	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2034	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2035	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2036	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2037	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2038	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2039	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2040	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2041	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2042	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2043	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2044	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2045	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2046	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2047	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2048	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2049	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2050	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2051	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2052	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2053	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2054	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2055	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2056	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2057	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2058	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2059	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2060
n0tform3	8:1c6281289d67	2061	/***************** Bit definition for CAN_F5R1 register *****************/
n0tform3	8:1c6281289d67	2062	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2063	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2064	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2065	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2066	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2067	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2068	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2069	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2070	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2071	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2072	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2073	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2074	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2075	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2076	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2077	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2078	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2079	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2080	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2081	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2082	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2083	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2084	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2085	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2086	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2087	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2088	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2089	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2090	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2091	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2092	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2093	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2094
n0tform3	8:1c6281289d67	2095	/***************** Bit definition for CAN_F6R1 register *****************/
n0tform3	8:1c6281289d67	2096	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2097	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2098	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2099	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2100	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2101	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2102	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2103	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2104	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2105	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2106	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2107	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2108	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2109	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2110	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2111	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2112	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2113	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2114	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2115	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2116	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2117	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2118	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2119	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2120	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2121	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2122	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2123	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2124	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2125	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2126	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2127	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2128
n0tform3	8:1c6281289d67	2129	/***************** Bit definition for CAN_F7R1 register *****************/
n0tform3	8:1c6281289d67	2130	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2131	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2132	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2133	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2134	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2135	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2136	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2137	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2138	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2139	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2140	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2141	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2142	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2143	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2144	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2145	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2146	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2147	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2148	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2149	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2150	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2151	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2152	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2153	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2154	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2155	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2156	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2157	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2158	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2159	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2160	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2161	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2162
n0tform3	8:1c6281289d67	2163	/***************** Bit definition for CAN_F8R1 register *****************/
n0tform3	8:1c6281289d67	2164	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2165	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2166	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2167	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2168	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2169	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2170	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2171	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2172	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2173	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2174	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2175	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2176	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2177	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2178	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2179	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2180	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2181	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2182	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2183	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2184	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2185	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2186	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2187	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2188	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2189	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2190	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2191	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2192	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2193	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2194	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2195	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2196
n0tform3	8:1c6281289d67	2197	/***************** Bit definition for CAN_F9R1 register *****************/
n0tform3	8:1c6281289d67	2198	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2199	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2200	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2201	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2202	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2203	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2204	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2205	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2206	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2207	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2208	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2209	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2210	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2211	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2212	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2213	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2214	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2215	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2216	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2217	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2218	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2219	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2220	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2221	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2222	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2223	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2224	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2225	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2226	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2227	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2228	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2229	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2230
n0tform3	8:1c6281289d67	2231	/***************** Bit definition for CAN_F10R1 register ****************/
n0tform3	8:1c6281289d67	2232	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2233	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2234	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2235	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2236	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2237	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2238	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2239	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2240	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2241	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2242	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2243	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2244	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2245	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2246	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2247	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2248	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2249	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2250	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2251	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2252	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2253	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2254	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2255	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2256	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2257	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2258	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2259	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2260	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2261	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2262	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2263	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2264
n0tform3	8:1c6281289d67	2265	/***************** Bit definition for CAN_F11R1 register ****************/
n0tform3	8:1c6281289d67	2266	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2267	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2268	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2269	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2270	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2271	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2272	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2273	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2274	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2275	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2276	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2277	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2278	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2279	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2280	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2281	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2282	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2283	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2284	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2285	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2286	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2287	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2288	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2289	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2290	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2291	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2292	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2293	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2294	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2295	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2296	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2297	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2298
n0tform3	8:1c6281289d67	2299	/***************** Bit definition for CAN_F12R1 register ****************/
n0tform3	8:1c6281289d67	2300	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2301	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2302	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2303	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2304	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2305	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2306	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2307	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2308	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2309	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2310	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2311	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2312	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2313	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2314	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2315	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2316	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2317	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2318	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2319	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2320	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2321	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2322	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2323	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2324	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2325	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2326	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2327	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2328	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2329	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2330	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2331	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2332
n0tform3	8:1c6281289d67	2333	/***************** Bit definition for CAN_F13R1 register ****************/
n0tform3	8:1c6281289d67	2334	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2335	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2336	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2337	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2338	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2339	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2340	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2341	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2342	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2343	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2344	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2345	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2346	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2347	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2348	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2349	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2350	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2351	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2352	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2353	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2354	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2355	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2356	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2357	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2358	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2359	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2360	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2361	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2362	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2363	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2364	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2365	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2366
n0tform3	8:1c6281289d67	2367	/***************** Bit definition for CAN_F0R2 register *****************/
n0tform3	8:1c6281289d67	2368	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2369	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2370	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2371	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2372	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2373	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2374	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2375	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2376	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2377	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2378	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2379	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2380	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2381	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2382	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2383	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2384	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2385	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2386	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2387	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2388	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2389	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2390	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2391	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2392	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2393	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2394	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2395	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2396	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2397	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2398	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2399	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2400
n0tform3	8:1c6281289d67	2401	/***************** Bit definition for CAN_F1R2 register *****************/
n0tform3	8:1c6281289d67	2402	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2403	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2404	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2405	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2406	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2407	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2408	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2409	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2410	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2411	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2412	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2413	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2414	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2415	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2416	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2417	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2418	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2419	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2420	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2421	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2422	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2423	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2424	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2425	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2426	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2427	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2428	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2429	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2430	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2431	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2432	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2433	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2434
n0tform3	8:1c6281289d67	2435	/***************** Bit definition for CAN_F2R2 register *****************/
n0tform3	8:1c6281289d67	2436	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2437	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2438	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2439	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2440	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2441	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2442	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2443	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2444	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2445	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2446	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2447	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2448	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2449	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2450	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2451	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2452	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2453	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2454	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2455	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2456	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2457	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2458	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2459	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2460	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2461	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2462	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2463	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2464	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2465	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2466	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2467	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2468
n0tform3	8:1c6281289d67	2469	/***************** Bit definition for CAN_F3R2 register *****************/
n0tform3	8:1c6281289d67	2470	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2471	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2472	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2473	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2474	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2475	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2476	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2477	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2478	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2479	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2480	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2481	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2482	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2483	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2484	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2485	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2486	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2487	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2488	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2489	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2490	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2491	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2492	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2493	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2494	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2495	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2496	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2497	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2498	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2499	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2500	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2501	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2502
n0tform3	8:1c6281289d67	2503	/***************** Bit definition for CAN_F4R2 register *****************/
n0tform3	8:1c6281289d67	2504	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2505	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2506	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2507	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2508	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2509	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2510	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2511	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2512	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2513	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2514	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2515	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2516	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2517	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2518	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2519	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2520	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2521	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2522	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2523	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2524	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2525	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2526	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2527	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2528	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2529	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2530	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2531	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2532	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2533	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2534	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2535	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2536
n0tform3	8:1c6281289d67	2537	/***************** Bit definition for CAN_F5R2 register *****************/
n0tform3	8:1c6281289d67	2538	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2539	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2540	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2541	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2542	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2543	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2544	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2545	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2546	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2547	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2548	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2549	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2550	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2551	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2552	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2553	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2554	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2555	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2556	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2557	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2558	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2559	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2560	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2561	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2562	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2563	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2564	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2565	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2566	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2567	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2568	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2569	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2570
n0tform3	8:1c6281289d67	2571	/***************** Bit definition for CAN_F6R2 register *****************/
n0tform3	8:1c6281289d67	2572	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2573	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2574	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2575	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2576	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2577	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2578	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2579	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2580	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2581	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2582	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2583	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2584	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2585	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2586	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2587	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2588	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2589	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2590	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2591	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2592	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2593	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2594	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2595	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2596	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2597	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2598	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2599	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2600	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2601	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2602	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2603	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2604
n0tform3	8:1c6281289d67	2605	/***************** Bit definition for CAN_F7R2 register *****************/
n0tform3	8:1c6281289d67	2606	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2607	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2608	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2609	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2610	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2611	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2612	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2613	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2614	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2615	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2616	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2617	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2618	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2619	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2620	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2621	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2622	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2623	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2624	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2625	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2626	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2627	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2628	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2629	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2630	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2631	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2632	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2633	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2634	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2635	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2636	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2637	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2638
n0tform3	8:1c6281289d67	2639	/***************** Bit definition for CAN_F8R2 register *****************/
n0tform3	8:1c6281289d67	2640	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2641	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2642	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2643	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2644	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2645	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2646	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2647	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2648	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2649	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2650	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2651	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2652	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2653	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2654	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2655	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2656	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2657	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2658	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2659	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2660	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2661	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2662	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2663	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2664	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2665	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2666	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2667	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2668	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2669	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2670	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2671	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2672
n0tform3	8:1c6281289d67	2673	/***************** Bit definition for CAN_F9R2 register *****************/
n0tform3	8:1c6281289d67	2674	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2675	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2676	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2677	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2678	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2679	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2680	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2681	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2682	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2683	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2684	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2685	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2686	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2687	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2688	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2689	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2690	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2691	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2692	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2693	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2694	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2695	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2696	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2697	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2698	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2699	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2700	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2701	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2702	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2703	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2704	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2705	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2706
n0tform3	8:1c6281289d67	2707	/***************** Bit definition for CAN_F10R2 register ****************/
n0tform3	8:1c6281289d67	2708	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2709	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2710	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2711	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2712	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2713	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2714	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2715	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2716	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2717	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2718	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2719	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2720	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2721	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2722	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2723	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2724	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2725	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2726	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2727	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2728	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2729	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2730	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2731	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2732	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2733	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2734	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2735	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2736	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2737	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2738	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2739	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2740
n0tform3	8:1c6281289d67	2741	/***************** Bit definition for CAN_F11R2 register ****************/
n0tform3	8:1c6281289d67	2742	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2743	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2744	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2745	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2746	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2747	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2748	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2749	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2750	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2751	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2752	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2753	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2754	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2755	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2756	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2757	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2758	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2759	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2760	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2761	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2762	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2763	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2764	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2765	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2766	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2767	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2768	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2769	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2770	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2771	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2772	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2773	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2774
n0tform3	8:1c6281289d67	2775	/***************** Bit definition for CAN_F12R2 register ****************/
n0tform3	8:1c6281289d67	2776	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2777	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2778	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2779	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2780	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2781	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2782	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2783	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2784	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2785	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2786	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2787	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2788	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2789	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2790	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2791	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2792	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2793	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2794	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2795	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2796	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2797	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2798	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2799	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2800	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2801	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2802	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2803	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2804	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2805	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2806	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2807	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2808
n0tform3	8:1c6281289d67	2809	/***************** Bit definition for CAN_F13R2 register ****************/
n0tform3	8:1c6281289d67	2810	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
n0tform3	8:1c6281289d67	2811	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
n0tform3	8:1c6281289d67	2812	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
n0tform3	8:1c6281289d67	2813	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
n0tform3	8:1c6281289d67	2814	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
n0tform3	8:1c6281289d67	2815	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
n0tform3	8:1c6281289d67	2816	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
n0tform3	8:1c6281289d67	2817	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
n0tform3	8:1c6281289d67	2818	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
n0tform3	8:1c6281289d67	2819	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
n0tform3	8:1c6281289d67	2820	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
n0tform3	8:1c6281289d67	2821	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
n0tform3	8:1c6281289d67	2822	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
n0tform3	8:1c6281289d67	2823	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
n0tform3	8:1c6281289d67	2824	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
n0tform3	8:1c6281289d67	2825	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
n0tform3	8:1c6281289d67	2826	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
n0tform3	8:1c6281289d67	2827	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
n0tform3	8:1c6281289d67	2828	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
n0tform3	8:1c6281289d67	2829	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
n0tform3	8:1c6281289d67	2830	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
n0tform3	8:1c6281289d67	2831	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
n0tform3	8:1c6281289d67	2832	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
n0tform3	8:1c6281289d67	2833	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
n0tform3	8:1c6281289d67	2834	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
n0tform3	8:1c6281289d67	2835	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
n0tform3	8:1c6281289d67	2836	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
n0tform3	8:1c6281289d67	2837	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
n0tform3	8:1c6281289d67	2838	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
n0tform3	8:1c6281289d67	2839	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
n0tform3	8:1c6281289d67	2840	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
n0tform3	8:1c6281289d67	2841	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
n0tform3	8:1c6281289d67	2842
n0tform3	8:1c6281289d67	2843	/******************************************************************************/
n0tform3	8:1c6281289d67	2844	/* */
n0tform3	8:1c6281289d67	2845	/* CRC calculation unit */
n0tform3	8:1c6281289d67	2846	/* */
n0tform3	8:1c6281289d67	2847	/******************************************************************************/
n0tform3	8:1c6281289d67	2848	/***************** Bit definition for CRC_DR register *******************/
n0tform3	8:1c6281289d67	2849	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
n0tform3	8:1c6281289d67	2850
n0tform3	8:1c6281289d67	2851
n0tform3	8:1c6281289d67	2852	/***************** Bit definition for CRC_IDR register ******************/
n0tform3	8:1c6281289d67	2853	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
n0tform3	8:1c6281289d67	2854
n0tform3	8:1c6281289d67	2855
n0tform3	8:1c6281289d67	2856	/****************** Bit definition for CRC_CR register ******************/
n0tform3	8:1c6281289d67	2857	#define CRC_CR_RESET ((uint8_t)0x01) /!< RESET bit /
n0tform3	8:1c6281289d67	2858
n0tform3	8:1c6281289d67	2859	/******************************************************************************/
n0tform3	8:1c6281289d67	2860	/* */
n0tform3	8:1c6281289d67	2861	/* Crypto Processor */
n0tform3	8:1c6281289d67	2862	/* */
n0tform3	8:1c6281289d67	2863	/******************************************************************************/
n0tform3	8:1c6281289d67	2864	/***************** Bits definition for CRYP_CR register ******************/
n0tform3	8:1c6281289d67	2865	#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	2866
n0tform3	8:1c6281289d67	2867	#define CRYP_CR_ALGOMODE ((uint32_t)0x00000038)
n0tform3	8:1c6281289d67	2868	#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	2869	#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	2870	#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	2871	#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
n0tform3	8:1c6281289d67	2872	#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	2873	#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	2874	#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
n0tform3	8:1c6281289d67	2875	#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	2876	#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
n0tform3	8:1c6281289d67	2877	#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
n0tform3	8:1c6281289d67	2878	#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
n0tform3	8:1c6281289d67	2879
n0tform3	8:1c6281289d67	2880	#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
n0tform3	8:1c6281289d67	2881	#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	2882	#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	2883	#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
n0tform3	8:1c6281289d67	2884	#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	2885	#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	2886	#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	2887	#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	2888	/**************** Bits definition for CRYP_SR register *******************/
n0tform3	8:1c6281289d67	2889	#define CRYP_SR_IFEM ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	2890	#define CRYP_SR_IFNF ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	2891	#define CRYP_SR_OFNE ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	2892	#define CRYP_SR_OFFU ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	2893	#define CRYP_SR_BUSY ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	2894	/**************** Bits definition for CRYP_DMACR register ****************/
n0tform3	8:1c6281289d67	2895	#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	2896	#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	2897	/*************** Bits definition for CRYP_IMSCR register ****************/
n0tform3	8:1c6281289d67	2898	#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	2899	#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	2900	/**************** Bits definition for CRYP_RISR register *****************/
n0tform3	8:1c6281289d67	2901	#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	2902	#define CRYP_RISR_INRIS ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	2903	/**************** Bits definition for CRYP_MISR register *****************/
n0tform3	8:1c6281289d67	2904	#define CRYP_MISR_INMIS ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	2905	#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	2906
n0tform3	8:1c6281289d67	2907	/******************************************************************************/
n0tform3	8:1c6281289d67	2908	/* */
n0tform3	8:1c6281289d67	2909	/* Digital to Analog Converter */
n0tform3	8:1c6281289d67	2910	/* */
n0tform3	8:1c6281289d67	2911	/******************************************************************************/
n0tform3	8:1c6281289d67	2912	/****************** Bit definition for DAC_CR register ******************/
n0tform3	8:1c6281289d67	2913	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
n0tform3	8:1c6281289d67	2914	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!<DAC channel1 output buffer disable /
n0tform3	8:1c6281289d67	2915	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
n0tform3	8:1c6281289d67	2916
n0tform3	8:1c6281289d67	2917	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
n0tform3	8:1c6281289d67	2918	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
n0tform3	8:1c6281289d67	2919	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
n0tform3	8:1c6281289d67	2920	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
n0tform3	8:1c6281289d67	2921
n0tform3	8:1c6281289d67	2922	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
n0tform3	8:1c6281289d67	2923	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
n0tform3	8:1c6281289d67	2924	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
n0tform3	8:1c6281289d67	2925
n0tform3	8:1c6281289d67	2926	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
n0tform3	8:1c6281289d67	2927	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	2928	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	2929	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	2930	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	2931
n0tform3	8:1c6281289d67	2932	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
n0tform3	8:1c6281289d67	2933	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
n0tform3	8:1c6281289d67	2934	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!<DAC channel2 output buffer disable /
n0tform3	8:1c6281289d67	2935	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
n0tform3	8:1c6281289d67	2936
n0tform3	8:1c6281289d67	2937	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
n0tform3	8:1c6281289d67	2938	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
n0tform3	8:1c6281289d67	2939	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
n0tform3	8:1c6281289d67	2940	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
n0tform3	8:1c6281289d67	2941
n0tform3	8:1c6281289d67	2942	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
n0tform3	8:1c6281289d67	2943	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
n0tform3	8:1c6281289d67	2944	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
n0tform3	8:1c6281289d67	2945
n0tform3	8:1c6281289d67	2946	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
n0tform3	8:1c6281289d67	2947	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	2948	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	2949	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	2950	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	2951
n0tform3	8:1c6281289d67	2952	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
n0tform3	8:1c6281289d67	2953
n0tform3	8:1c6281289d67	2954	/*************** Bit definition for DAC_SWTRIGR register ****************/
n0tform3	8:1c6281289d67	2955	#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /!<DAC channel1 software trigger /
n0tform3	8:1c6281289d67	2956	#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /!<DAC channel2 software trigger /
n0tform3	8:1c6281289d67	2957
n0tform3	8:1c6281289d67	2958	/*************** Bit definition for DAC_DHR12R1 register ****************/
n0tform3	8:1c6281289d67	2959	#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /!<DAC channel1 12-bit Right aligned data /
n0tform3	8:1c6281289d67	2960
n0tform3	8:1c6281289d67	2961	/*************** Bit definition for DAC_DHR12L1 register ****************/
n0tform3	8:1c6281289d67	2962	#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /!<DAC channel1 12-bit Left aligned data /
n0tform3	8:1c6281289d67	2963
n0tform3	8:1c6281289d67	2964	/**************** Bit definition for DAC_DHR8R1 register ****************/
n0tform3	8:1c6281289d67	2965	#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /!<DAC channel1 8-bit Right aligned data /
n0tform3	8:1c6281289d67	2966
n0tform3	8:1c6281289d67	2967	/*************** Bit definition for DAC_DHR12R2 register ****************/
n0tform3	8:1c6281289d67	2968	#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /!<DAC channel2 12-bit Right aligned data /
n0tform3	8:1c6281289d67	2969
n0tform3	8:1c6281289d67	2970	/*************** Bit definition for DAC_DHR12L2 register ****************/
n0tform3	8:1c6281289d67	2971	#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /!<DAC channel2 12-bit Left aligned data /
n0tform3	8:1c6281289d67	2972
n0tform3	8:1c6281289d67	2973	/**************** Bit definition for DAC_DHR8R2 register ****************/
n0tform3	8:1c6281289d67	2974	#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /!<DAC channel2 8-bit Right aligned data /
n0tform3	8:1c6281289d67	2975
n0tform3	8:1c6281289d67	2976	/*************** Bit definition for DAC_DHR12RD register ****************/
n0tform3	8:1c6281289d67	2977	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
n0tform3	8:1c6281289d67	2978	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
n0tform3	8:1c6281289d67	2979
n0tform3	8:1c6281289d67	2980	/*************** Bit definition for DAC_DHR12LD register ****************/
n0tform3	8:1c6281289d67	2981	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
n0tform3	8:1c6281289d67	2982	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
n0tform3	8:1c6281289d67	2983
n0tform3	8:1c6281289d67	2984	/**************** Bit definition for DAC_DHR8RD register ****************/
n0tform3	8:1c6281289d67	2985	#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /!<DAC channel1 8-bit Right aligned data /
n0tform3	8:1c6281289d67	2986	#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /!<DAC channel2 8-bit Right aligned data /
n0tform3	8:1c6281289d67	2987
n0tform3	8:1c6281289d67	2988	/***************** Bit definition for DAC_DOR1 register *****************/
n0tform3	8:1c6281289d67	2989	#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /!<DAC channel1 data output /
n0tform3	8:1c6281289d67	2990
n0tform3	8:1c6281289d67	2991	/***************** Bit definition for DAC_DOR2 register *****************/
n0tform3	8:1c6281289d67	2992	#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /!<DAC channel2 data output /
n0tform3	8:1c6281289d67	2993
n0tform3	8:1c6281289d67	2994	/****************** Bit definition for DAC_SR register ******************/
n0tform3	8:1c6281289d67	2995	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
n0tform3	8:1c6281289d67	2996	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
n0tform3	8:1c6281289d67	2997
n0tform3	8:1c6281289d67	2998	/******************************************************************************/
n0tform3	8:1c6281289d67	2999	/* */
n0tform3	8:1c6281289d67	3000	/* Debug MCU */
n0tform3	8:1c6281289d67	3001	/* */
n0tform3	8:1c6281289d67	3002	/******************************************************************************/
n0tform3	8:1c6281289d67	3003
n0tform3	8:1c6281289d67	3004	/******************************************************************************/
n0tform3	8:1c6281289d67	3005	/* */
n0tform3	8:1c6281289d67	3006	/* DCMI */
n0tform3	8:1c6281289d67	3007	/* */
n0tform3	8:1c6281289d67	3008	/******************************************************************************/
n0tform3	8:1c6281289d67	3009	/****************** Bits definition for DCMI_CR register ****************/
n0tform3	8:1c6281289d67	3010	#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3011	#define DCMI_CR_CM ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3012	#define DCMI_CR_CROP ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3013	#define DCMI_CR_JPEG ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3014	#define DCMI_CR_ESS ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3015	#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3016	#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3017	#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	3018	#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3019	#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3020	#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3021	#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3022	#define DCMI_CR_CRE ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	3023	#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	3024
n0tform3	8:1c6281289d67	3025	/****************** Bits definition for DCMI_SR register ****************/
n0tform3	8:1c6281289d67	3026	#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3027	#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3028	#define DCMI_SR_FNE ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3029
n0tform3	8:1c6281289d67	3030	/****************** Bits definition for DCMI_RISR register **************/
n0tform3	8:1c6281289d67	3031	#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3032	#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3033	#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3034	#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3035	#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3036
n0tform3	8:1c6281289d67	3037	/****************** Bits definition for DCMI_IER register ***************/
n0tform3	8:1c6281289d67	3038	#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3039	#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3040	#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3041	#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3042	#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3043
n0tform3	8:1c6281289d67	3044	/****************** Bits definition for DCMI_MISR register **************/
n0tform3	8:1c6281289d67	3045	#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3046	#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3047	#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3048	#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3049	#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3050
n0tform3	8:1c6281289d67	3051	/****************** Bits definition for DCMI_ICR register ***************/
n0tform3	8:1c6281289d67	3052	#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3053	#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3054	#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3055	#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3056	#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3057
n0tform3	8:1c6281289d67	3058	/******************************************************************************/
n0tform3	8:1c6281289d67	3059	/* */
n0tform3	8:1c6281289d67	3060	/* DMA Controller */
n0tform3	8:1c6281289d67	3061	/* */
n0tform3	8:1c6281289d67	3062	/******************************************************************************/
n0tform3	8:1c6281289d67	3063	/****************** Bits definition for DMA_SxCR register ***************/
n0tform3	8:1c6281289d67	3064	#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
n0tform3	8:1c6281289d67	3065	#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	3066	#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	3067	#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	3068	#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
n0tform3	8:1c6281289d67	3069	#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	3070	#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	3071	#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
n0tform3	8:1c6281289d67	3072	#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	3073	#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	3074	#define DMA_SxCR_ACK ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	3075	#define DMA_SxCR_CT ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	3076	#define DMA_SxCR_DBM ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	3077	#define DMA_SxCR_PL ((uint32_t)0x00030000)
n0tform3	8:1c6281289d67	3078	#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	3079	#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	3080	#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	3081	#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
n0tform3	8:1c6281289d67	3082	#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	3083	#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	3084	#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
n0tform3	8:1c6281289d67	3085	#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3086	#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	3087	#define DMA_SxCR_MINC ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3088	#define DMA_SxCR_PINC ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3089	#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3090	#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
n0tform3	8:1c6281289d67	3091	#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3092	#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	3093	#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3094	#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3095	#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3096	#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3097	#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3098	#define DMA_SxCR_EN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3099
n0tform3	8:1c6281289d67	3100	/****************** Bits definition for DMA_SxCNDTR register ************/
n0tform3	8:1c6281289d67	3101	#define DMA_SxNDT ((uint32_t)0x0000FFFF)
n0tform3	8:1c6281289d67	3102	#define DMA_SxNDT_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3103	#define DMA_SxNDT_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3104	#define DMA_SxNDT_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3105	#define DMA_SxNDT_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3106	#define DMA_SxNDT_4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3107	#define DMA_SxNDT_5 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3108	#define DMA_SxNDT_6 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3109	#define DMA_SxNDT_7 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	3110	#define DMA_SxNDT_8 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3111	#define DMA_SxNDT_9 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3112	#define DMA_SxNDT_10 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3113	#define DMA_SxNDT_11 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3114	#define DMA_SxNDT_12 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	3115	#define DMA_SxNDT_13 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	3116	#define DMA_SxNDT_14 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	3117	#define DMA_SxNDT_15 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	3118
n0tform3	8:1c6281289d67	3119	/****************** Bits definition for DMA_SxFCR register **************/
n0tform3	8:1c6281289d67	3120	#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	3121	#define DMA_SxFCR_FS ((uint32_t)0x00000038)
n0tform3	8:1c6281289d67	3122	#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3123	#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3124	#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3125	#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3126	#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
n0tform3	8:1c6281289d67	3127	#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3128	#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3129
n0tform3	8:1c6281289d67	3130	/****************** Bits definition for DMA_LISR register ***************/
n0tform3	8:1c6281289d67	3131	#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	3132	#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	3133	#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	3134	#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	3135	#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	3136	#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	3137	#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	3138	#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	3139	#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	3140	#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	3141	#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3142	#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3143	#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3144	#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3145	#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3146	#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3147	#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3148	#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3149	#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3150	#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3151
n0tform3	8:1c6281289d67	3152	/****************** Bits definition for DMA_HISR register ***************/
n0tform3	8:1c6281289d67	3153	#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	3154	#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	3155	#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	3156	#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	3157	#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	3158	#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	3159	#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	3160	#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	3161	#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	3162	#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	3163	#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3164	#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3165	#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3166	#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3167	#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3168	#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3169	#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3170	#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3171	#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3172	#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3173
n0tform3	8:1c6281289d67	3174	/****************** Bits definition for DMA_LIFCR register **************/
n0tform3	8:1c6281289d67	3175	#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	3176	#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	3177	#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	3178	#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	3179	#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	3180	#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	3181	#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	3182	#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	3183	#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	3184	#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	3185	#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3186	#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3187	#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3188	#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3189	#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3190	#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3191	#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3192	#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3193	#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3194	#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3195
n0tform3	8:1c6281289d67	3196	/****************** Bits definition for DMA_HIFCR register **************/
n0tform3	8:1c6281289d67	3197	#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	3198	#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	3199	#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	3200	#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	3201	#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	3202	#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	3203	#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	3204	#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	3205	#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	3206	#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	3207	#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3208	#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3209	#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3210	#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3211	#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3212	#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3213	#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3214	#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3215	#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3216	#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3217
n0tform3	8:1c6281289d67	3218	/******************************************************************************/
n0tform3	8:1c6281289d67	3219	/* */
n0tform3	8:1c6281289d67	3220	/* External Interrupt/Event Controller */
n0tform3	8:1c6281289d67	3221	/* */
n0tform3	8:1c6281289d67	3222	/******************************************************************************/
n0tform3	8:1c6281289d67	3223	/***************** Bit definition for EXTI_IMR register *****************/
n0tform3	8:1c6281289d67	3224	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
n0tform3	8:1c6281289d67	3225	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
n0tform3	8:1c6281289d67	3226	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
n0tform3	8:1c6281289d67	3227	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
n0tform3	8:1c6281289d67	3228	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
n0tform3	8:1c6281289d67	3229	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
n0tform3	8:1c6281289d67	3230	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
n0tform3	8:1c6281289d67	3231	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
n0tform3	8:1c6281289d67	3232	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
n0tform3	8:1c6281289d67	3233	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
n0tform3	8:1c6281289d67	3234	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
n0tform3	8:1c6281289d67	3235	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
n0tform3	8:1c6281289d67	3236	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
n0tform3	8:1c6281289d67	3237	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
n0tform3	8:1c6281289d67	3238	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
n0tform3	8:1c6281289d67	3239	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
n0tform3	8:1c6281289d67	3240	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
n0tform3	8:1c6281289d67	3241	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
n0tform3	8:1c6281289d67	3242	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
n0tform3	8:1c6281289d67	3243	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
n0tform3	8:1c6281289d67	3244
n0tform3	8:1c6281289d67	3245	/***************** Bit definition for EXTI_EMR register *****************/
n0tform3	8:1c6281289d67	3246	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
n0tform3	8:1c6281289d67	3247	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
n0tform3	8:1c6281289d67	3248	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
n0tform3	8:1c6281289d67	3249	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
n0tform3	8:1c6281289d67	3250	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
n0tform3	8:1c6281289d67	3251	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
n0tform3	8:1c6281289d67	3252	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
n0tform3	8:1c6281289d67	3253	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
n0tform3	8:1c6281289d67	3254	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
n0tform3	8:1c6281289d67	3255	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
n0tform3	8:1c6281289d67	3256	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
n0tform3	8:1c6281289d67	3257	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
n0tform3	8:1c6281289d67	3258	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
n0tform3	8:1c6281289d67	3259	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
n0tform3	8:1c6281289d67	3260	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
n0tform3	8:1c6281289d67	3261	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
n0tform3	8:1c6281289d67	3262	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
n0tform3	8:1c6281289d67	3263	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
n0tform3	8:1c6281289d67	3264	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
n0tform3	8:1c6281289d67	3265	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
n0tform3	8:1c6281289d67	3266
n0tform3	8:1c6281289d67	3267	/**************** Bit definition for EXTI_RTSR register *****************/
n0tform3	8:1c6281289d67	3268	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
n0tform3	8:1c6281289d67	3269	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
n0tform3	8:1c6281289d67	3270	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
n0tform3	8:1c6281289d67	3271	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
n0tform3	8:1c6281289d67	3272	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
n0tform3	8:1c6281289d67	3273	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
n0tform3	8:1c6281289d67	3274	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
n0tform3	8:1c6281289d67	3275	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
n0tform3	8:1c6281289d67	3276	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
n0tform3	8:1c6281289d67	3277	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
n0tform3	8:1c6281289d67	3278	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
n0tform3	8:1c6281289d67	3279	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
n0tform3	8:1c6281289d67	3280	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
n0tform3	8:1c6281289d67	3281	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
n0tform3	8:1c6281289d67	3282	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
n0tform3	8:1c6281289d67	3283	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
n0tform3	8:1c6281289d67	3284	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
n0tform3	8:1c6281289d67	3285	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
n0tform3	8:1c6281289d67	3286	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
n0tform3	8:1c6281289d67	3287	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
n0tform3	8:1c6281289d67	3288
n0tform3	8:1c6281289d67	3289	/**************** Bit definition for EXTI_FTSR register *****************/
n0tform3	8:1c6281289d67	3290	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
n0tform3	8:1c6281289d67	3291	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
n0tform3	8:1c6281289d67	3292	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
n0tform3	8:1c6281289d67	3293	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
n0tform3	8:1c6281289d67	3294	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
n0tform3	8:1c6281289d67	3295	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
n0tform3	8:1c6281289d67	3296	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
n0tform3	8:1c6281289d67	3297	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
n0tform3	8:1c6281289d67	3298	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
n0tform3	8:1c6281289d67	3299	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
n0tform3	8:1c6281289d67	3300	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
n0tform3	8:1c6281289d67	3301	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
n0tform3	8:1c6281289d67	3302	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
n0tform3	8:1c6281289d67	3303	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
n0tform3	8:1c6281289d67	3304	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
n0tform3	8:1c6281289d67	3305	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
n0tform3	8:1c6281289d67	3306	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
n0tform3	8:1c6281289d67	3307	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
n0tform3	8:1c6281289d67	3308	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
n0tform3	8:1c6281289d67	3309	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
n0tform3	8:1c6281289d67	3310
n0tform3	8:1c6281289d67	3311	/**************** Bit definition for EXTI_SWIER register ****************/
n0tform3	8:1c6281289d67	3312	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
n0tform3	8:1c6281289d67	3313	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
n0tform3	8:1c6281289d67	3314	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
n0tform3	8:1c6281289d67	3315	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
n0tform3	8:1c6281289d67	3316	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
n0tform3	8:1c6281289d67	3317	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
n0tform3	8:1c6281289d67	3318	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
n0tform3	8:1c6281289d67	3319	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
n0tform3	8:1c6281289d67	3320	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
n0tform3	8:1c6281289d67	3321	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
n0tform3	8:1c6281289d67	3322	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
n0tform3	8:1c6281289d67	3323	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
n0tform3	8:1c6281289d67	3324	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
n0tform3	8:1c6281289d67	3325	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
n0tform3	8:1c6281289d67	3326	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
n0tform3	8:1c6281289d67	3327	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
n0tform3	8:1c6281289d67	3328	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
n0tform3	8:1c6281289d67	3329	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
n0tform3	8:1c6281289d67	3330	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
n0tform3	8:1c6281289d67	3331	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
n0tform3	8:1c6281289d67	3332
n0tform3	8:1c6281289d67	3333	/***************** Bit definition for EXTI_PR register ******************/
n0tform3	8:1c6281289d67	3334	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
n0tform3	8:1c6281289d67	3335	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
n0tform3	8:1c6281289d67	3336	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
n0tform3	8:1c6281289d67	3337	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
n0tform3	8:1c6281289d67	3338	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
n0tform3	8:1c6281289d67	3339	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
n0tform3	8:1c6281289d67	3340	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
n0tform3	8:1c6281289d67	3341	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
n0tform3	8:1c6281289d67	3342	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
n0tform3	8:1c6281289d67	3343	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
n0tform3	8:1c6281289d67	3344	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
n0tform3	8:1c6281289d67	3345	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
n0tform3	8:1c6281289d67	3346	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
n0tform3	8:1c6281289d67	3347	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
n0tform3	8:1c6281289d67	3348	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
n0tform3	8:1c6281289d67	3349	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
n0tform3	8:1c6281289d67	3350	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
n0tform3	8:1c6281289d67	3351	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
n0tform3	8:1c6281289d67	3352	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
n0tform3	8:1c6281289d67	3353	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
n0tform3	8:1c6281289d67	3354
n0tform3	8:1c6281289d67	3355	/******************************************************************************/
n0tform3	8:1c6281289d67	3356	/* */
n0tform3	8:1c6281289d67	3357	/* FLASH */
n0tform3	8:1c6281289d67	3358	/* */
n0tform3	8:1c6281289d67	3359	/******************************************************************************/
n0tform3	8:1c6281289d67	3360	/***************** Bits definition for FLASH_ACR register ***************/
n0tform3	8:1c6281289d67	3361	#define FLASH_ACR_LATENCY ((uint32_t)0x00000007)
n0tform3	8:1c6281289d67	3362	#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
n0tform3	8:1c6281289d67	3363	#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3364	#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3365	#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
n0tform3	8:1c6281289d67	3366	#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3367	#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
n0tform3	8:1c6281289d67	3368	#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
n0tform3	8:1c6281289d67	3369	#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
n0tform3	8:1c6281289d67	3370
n0tform3	8:1c6281289d67	3371	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3372	#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3373	#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3374	#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3375	#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	3376	#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
n0tform3	8:1c6281289d67	3377	#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
n0tform3	8:1c6281289d67	3378
n0tform3	8:1c6281289d67	3379	/***************** Bits definition for FLASH_SR register ****************/
n0tform3	8:1c6281289d67	3380	#define FLASH_SR_EOP ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3381	#define FLASH_SR_SOP ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3382	#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3383	#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3384	#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3385	#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	3386	#define FLASH_SR_BSY ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	3387
n0tform3	8:1c6281289d67	3388	/***************** Bits definition for FLASH_CR register ****************/
n0tform3	8:1c6281289d67	3389	#define FLASH_CR_PG ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3390	#define FLASH_CR_SER ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3391	#define FLASH_CR_MER ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3392	#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3393	#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	3394	#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3395	#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3396	#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3397	#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3398	#define FLASH_CR_STRT ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	3399	#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	3400	#define FLASH_CR_LOCK ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	3401
n0tform3	8:1c6281289d67	3402	/***************** Bits definition for FLASH_OPTCR register *************/
n0tform3	8:1c6281289d67	3403	#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	3404	#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	3405	#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	3406	#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	3407	#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
n0tform3	8:1c6281289d67	3408	#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	3409	#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	3410	#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	3411	#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	3412	#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	3413	#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	3414	#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	3415	#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	3416	#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	3417	#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	3418	#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	3419	#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	3420	#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	3421	#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	3422	#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	3423	#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	3424	#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	3425	#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	3426	#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	3427	#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	3428	#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	3429	#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	3430	#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	3431
n0tform3	8:1c6281289d67	3432	/******************************************************************************/
n0tform3	8:1c6281289d67	3433	/* */
n0tform3	8:1c6281289d67	3434	/* Flexible Static Memory Controller */
n0tform3	8:1c6281289d67	3435	/* */
n0tform3	8:1c6281289d67	3436	/******************************************************************************/
n0tform3	8:1c6281289d67	3437	/**************** Bit definition for FSMC_BCR1 register *****************/
n0tform3	8:1c6281289d67	3438	#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
n0tform3	8:1c6281289d67	3439	#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
n0tform3	8:1c6281289d67	3440
n0tform3	8:1c6281289d67	3441	#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
n0tform3	8:1c6281289d67	3442	#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
n0tform3	8:1c6281289d67	3443	#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
n0tform3	8:1c6281289d67	3444
n0tform3	8:1c6281289d67	3445	#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
n0tform3	8:1c6281289d67	3446	#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3447	#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3448
n0tform3	8:1c6281289d67	3449	#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
n0tform3	8:1c6281289d67	3450	#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
n0tform3	8:1c6281289d67	3451	#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
n0tform3	8:1c6281289d67	3452	#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
n0tform3	8:1c6281289d67	3453	#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
n0tform3	8:1c6281289d67	3454	#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /!<Write enable bit /
n0tform3	8:1c6281289d67	3455	#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
n0tform3	8:1c6281289d67	3456	#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
n0tform3	8:1c6281289d67	3457	#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
n0tform3	8:1c6281289d67	3458	#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
n0tform3	8:1c6281289d67	3459
n0tform3	8:1c6281289d67	3460	/**************** Bit definition for FSMC_BCR2 register *****************/
n0tform3	8:1c6281289d67	3461	#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
n0tform3	8:1c6281289d67	3462	#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
n0tform3	8:1c6281289d67	3463
n0tform3	8:1c6281289d67	3464	#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
n0tform3	8:1c6281289d67	3465	#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
n0tform3	8:1c6281289d67	3466	#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
n0tform3	8:1c6281289d67	3467
n0tform3	8:1c6281289d67	3468	#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
n0tform3	8:1c6281289d67	3469	#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3470	#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3471
n0tform3	8:1c6281289d67	3472	#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
n0tform3	8:1c6281289d67	3473	#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
n0tform3	8:1c6281289d67	3474	#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
n0tform3	8:1c6281289d67	3475	#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
n0tform3	8:1c6281289d67	3476	#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
n0tform3	8:1c6281289d67	3477	#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /!<Write enable bit /
n0tform3	8:1c6281289d67	3478	#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
n0tform3	8:1c6281289d67	3479	#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
n0tform3	8:1c6281289d67	3480	#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
n0tform3	8:1c6281289d67	3481	#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
n0tform3	8:1c6281289d67	3482
n0tform3	8:1c6281289d67	3483	/**************** Bit definition for FSMC_BCR3 register *****************/
n0tform3	8:1c6281289d67	3484	#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
n0tform3	8:1c6281289d67	3485	#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
n0tform3	8:1c6281289d67	3486
n0tform3	8:1c6281289d67	3487	#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
n0tform3	8:1c6281289d67	3488	#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
n0tform3	8:1c6281289d67	3489	#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
n0tform3	8:1c6281289d67	3490
n0tform3	8:1c6281289d67	3491	#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
n0tform3	8:1c6281289d67	3492	#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3493	#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3494
n0tform3	8:1c6281289d67	3495	#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
n0tform3	8:1c6281289d67	3496	#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
n0tform3	8:1c6281289d67	3497	#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit. /
n0tform3	8:1c6281289d67	3498	#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
n0tform3	8:1c6281289d67	3499	#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
n0tform3	8:1c6281289d67	3500	#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /!<Write enable bit /
n0tform3	8:1c6281289d67	3501	#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
n0tform3	8:1c6281289d67	3502	#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
n0tform3	8:1c6281289d67	3503	#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
n0tform3	8:1c6281289d67	3504	#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
n0tform3	8:1c6281289d67	3505
n0tform3	8:1c6281289d67	3506	/**************** Bit definition for FSMC_BCR4 register *****************/
n0tform3	8:1c6281289d67	3507	#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
n0tform3	8:1c6281289d67	3508	#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
n0tform3	8:1c6281289d67	3509
n0tform3	8:1c6281289d67	3510	#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
n0tform3	8:1c6281289d67	3511	#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
n0tform3	8:1c6281289d67	3512	#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
n0tform3	8:1c6281289d67	3513
n0tform3	8:1c6281289d67	3514	#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
n0tform3	8:1c6281289d67	3515	#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3516	#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3517
n0tform3	8:1c6281289d67	3518	#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
n0tform3	8:1c6281289d67	3519	#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
n0tform3	8:1c6281289d67	3520	#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
n0tform3	8:1c6281289d67	3521	#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
n0tform3	8:1c6281289d67	3522	#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
n0tform3	8:1c6281289d67	3523	#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /!<Write enable bit /
n0tform3	8:1c6281289d67	3524	#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
n0tform3	8:1c6281289d67	3525	#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
n0tform3	8:1c6281289d67	3526	#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
n0tform3	8:1c6281289d67	3527	#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
n0tform3	8:1c6281289d67	3528
n0tform3	8:1c6281289d67	3529	/**************** Bit definition for FSMC_BTR1 register ****************/
n0tform3	8:1c6281289d67	3530	#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
n0tform3	8:1c6281289d67	3531	#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3532	#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3533	#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3534	#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3535
n0tform3	8:1c6281289d67	3536	#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
n0tform3	8:1c6281289d67	3537	#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3538	#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3539	#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	3540	#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
n0tform3	8:1c6281289d67	3541
n0tform3	8:1c6281289d67	3542	#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
n0tform3	8:1c6281289d67	3543	#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3544	#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3545	#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3546	#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3547
n0tform3	8:1c6281289d67	3548	#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
n0tform3	8:1c6281289d67	3549	#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3550	#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3551	#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3552	#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3553
n0tform3	8:1c6281289d67	3554	#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
n0tform3	8:1c6281289d67	3555	#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3556	#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3557	#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3558	#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3559
n0tform3	8:1c6281289d67	3560	#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
n0tform3	8:1c6281289d67	3561	#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3562	#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3563	#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3564	#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3565
n0tform3	8:1c6281289d67	3566	#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
n0tform3	8:1c6281289d67	3567	#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3568	#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3569
n0tform3	8:1c6281289d67	3570	/**************** Bit definition for FSMC_BTR2 register *****************/
n0tform3	8:1c6281289d67	3571	#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
n0tform3	8:1c6281289d67	3572	#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3573	#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3574	#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3575	#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3576
n0tform3	8:1c6281289d67	3577	#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
n0tform3	8:1c6281289d67	3578	#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3579	#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3580	#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	3581	#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
n0tform3	8:1c6281289d67	3582
n0tform3	8:1c6281289d67	3583	#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
n0tform3	8:1c6281289d67	3584	#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3585	#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3586	#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3587	#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3588
n0tform3	8:1c6281289d67	3589	#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
n0tform3	8:1c6281289d67	3590	#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3591	#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3592	#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3593	#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3594
n0tform3	8:1c6281289d67	3595	#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
n0tform3	8:1c6281289d67	3596	#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3597	#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3598	#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3599	#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3600
n0tform3	8:1c6281289d67	3601	#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
n0tform3	8:1c6281289d67	3602	#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3603	#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3604	#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3605	#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3606
n0tform3	8:1c6281289d67	3607	#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
n0tform3	8:1c6281289d67	3608	#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3609	#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3610
n0tform3	8:1c6281289d67	3611	/***************** Bit definition for FSMC_BTR3 register *****************/
n0tform3	8:1c6281289d67	3612	#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
n0tform3	8:1c6281289d67	3613	#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3614	#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3615	#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3616	#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3617
n0tform3	8:1c6281289d67	3618	#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
n0tform3	8:1c6281289d67	3619	#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3620	#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3621	#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	3622	#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
n0tform3	8:1c6281289d67	3623
n0tform3	8:1c6281289d67	3624	#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
n0tform3	8:1c6281289d67	3625	#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3626	#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3627	#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3628	#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3629
n0tform3	8:1c6281289d67	3630	#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
n0tform3	8:1c6281289d67	3631	#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3632	#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3633	#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3634	#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3635
n0tform3	8:1c6281289d67	3636	#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
n0tform3	8:1c6281289d67	3637	#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3638	#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3639	#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3640	#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3641
n0tform3	8:1c6281289d67	3642	#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
n0tform3	8:1c6281289d67	3643	#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3644	#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3645	#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3646	#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3647
n0tform3	8:1c6281289d67	3648	#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
n0tform3	8:1c6281289d67	3649	#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3650	#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3651
n0tform3	8:1c6281289d67	3652	/**************** Bit definition for FSMC_BTR4 register *****************/
n0tform3	8:1c6281289d67	3653	#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
n0tform3	8:1c6281289d67	3654	#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3655	#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3656	#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3657	#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3658
n0tform3	8:1c6281289d67	3659	#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
n0tform3	8:1c6281289d67	3660	#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3661	#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3662	#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	3663	#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
n0tform3	8:1c6281289d67	3664
n0tform3	8:1c6281289d67	3665	#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
n0tform3	8:1c6281289d67	3666	#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3667	#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3668	#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3669	#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3670
n0tform3	8:1c6281289d67	3671	#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
n0tform3	8:1c6281289d67	3672	#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3673	#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3674	#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3675	#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3676
n0tform3	8:1c6281289d67	3677	#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
n0tform3	8:1c6281289d67	3678	#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3679	#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3680	#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3681	#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3682
n0tform3	8:1c6281289d67	3683	#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
n0tform3	8:1c6281289d67	3684	#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3685	#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3686	#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3687	#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3688
n0tform3	8:1c6281289d67	3689	#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
n0tform3	8:1c6281289d67	3690	#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3691	#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3692
n0tform3	8:1c6281289d67	3693	/**************** Bit definition for FSMC_BWTR1 register ****************/
n0tform3	8:1c6281289d67	3694	#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
n0tform3	8:1c6281289d67	3695	#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3696	#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3697	#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3698	#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3699
n0tform3	8:1c6281289d67	3700	#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
n0tform3	8:1c6281289d67	3701	#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3702	#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3703	#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	3704	#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
n0tform3	8:1c6281289d67	3705
n0tform3	8:1c6281289d67	3706	#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
n0tform3	8:1c6281289d67	3707	#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3708	#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3709	#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3710	#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3711
n0tform3	8:1c6281289d67	3712	#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
n0tform3	8:1c6281289d67	3713	#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3714	#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3715	#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3716	#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3717
n0tform3	8:1c6281289d67	3718	#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
n0tform3	8:1c6281289d67	3719	#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3720	#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3721	#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3722	#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3723
n0tform3	8:1c6281289d67	3724	#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
n0tform3	8:1c6281289d67	3725	#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3726	#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3727
n0tform3	8:1c6281289d67	3728	/**************** Bit definition for FSMC_BWTR2 register ****************/
n0tform3	8:1c6281289d67	3729	#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
n0tform3	8:1c6281289d67	3730	#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3731	#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3732	#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3733	#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3734
n0tform3	8:1c6281289d67	3735	#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
n0tform3	8:1c6281289d67	3736	#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3737	#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3738	#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	3739	#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
n0tform3	8:1c6281289d67	3740
n0tform3	8:1c6281289d67	3741	#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
n0tform3	8:1c6281289d67	3742	#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3743	#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3744	#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3745	#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3746
n0tform3	8:1c6281289d67	3747	#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
n0tform3	8:1c6281289d67	3748	#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3749	#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1/
n0tform3	8:1c6281289d67	3750	#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3751	#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3752
n0tform3	8:1c6281289d67	3753	#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
n0tform3	8:1c6281289d67	3754	#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3755	#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3756	#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3757	#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3758
n0tform3	8:1c6281289d67	3759	#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
n0tform3	8:1c6281289d67	3760	#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3761	#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3762
n0tform3	8:1c6281289d67	3763	/**************** Bit definition for FSMC_BWTR3 register ****************/
n0tform3	8:1c6281289d67	3764	#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
n0tform3	8:1c6281289d67	3765	#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3766	#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3767	#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3768	#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3769
n0tform3	8:1c6281289d67	3770	#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
n0tform3	8:1c6281289d67	3771	#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3772	#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3773	#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	3774	#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
n0tform3	8:1c6281289d67	3775
n0tform3	8:1c6281289d67	3776	#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
n0tform3	8:1c6281289d67	3777	#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3778	#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3779	#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3780	#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3781
n0tform3	8:1c6281289d67	3782	#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
n0tform3	8:1c6281289d67	3783	#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3784	#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3785	#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3786	#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3787
n0tform3	8:1c6281289d67	3788	#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
n0tform3	8:1c6281289d67	3789	#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3790	#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3791	#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3792	#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3793
n0tform3	8:1c6281289d67	3794	#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
n0tform3	8:1c6281289d67	3795	#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3796	#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3797
n0tform3	8:1c6281289d67	3798	/**************** Bit definition for FSMC_BWTR4 register ****************/
n0tform3	8:1c6281289d67	3799	#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
n0tform3	8:1c6281289d67	3800	#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3801	#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3802	#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3803	#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3804
n0tform3	8:1c6281289d67	3805	#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
n0tform3	8:1c6281289d67	3806	#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3807	#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3808	#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
n0tform3	8:1c6281289d67	3809	#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
n0tform3	8:1c6281289d67	3810
n0tform3	8:1c6281289d67	3811	#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
n0tform3	8:1c6281289d67	3812	#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3813	#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3814	#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3815	#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3816
n0tform3	8:1c6281289d67	3817	#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
n0tform3	8:1c6281289d67	3818	#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3819	#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3820	#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3821	#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3822
n0tform3	8:1c6281289d67	3823	#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
n0tform3	8:1c6281289d67	3824	#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3825	#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3826	#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3827	#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3828
n0tform3	8:1c6281289d67	3829	#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
n0tform3	8:1c6281289d67	3830	#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3831	#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3832
n0tform3	8:1c6281289d67	3833	/**************** Bit definition for FSMC_PCR2 register *****************/
n0tform3	8:1c6281289d67	3834	#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
n0tform3	8:1c6281289d67	3835	#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /!<PC Card/NAND Flash memory bank enable bit /
n0tform3	8:1c6281289d67	3836	#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /!<Memory type /
n0tform3	8:1c6281289d67	3837
n0tform3	8:1c6281289d67	3838	#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
n0tform3	8:1c6281289d67	3839	#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3840	#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3841
n0tform3	8:1c6281289d67	3842	#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
n0tform3	8:1c6281289d67	3843
n0tform3	8:1c6281289d67	3844	#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
n0tform3	8:1c6281289d67	3845	#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
n0tform3	8:1c6281289d67	3846	#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
n0tform3	8:1c6281289d67	3847	#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
n0tform3	8:1c6281289d67	3848	#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3849
n0tform3	8:1c6281289d67	3850	#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
n0tform3	8:1c6281289d67	3851	#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3852	#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3853	#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3854	#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3855
n0tform3	8:1c6281289d67	3856	#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[1:0] bits (ECC page size) /
n0tform3	8:1c6281289d67	3857	#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3858	#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3859	#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3860
n0tform3	8:1c6281289d67	3861	/**************** Bit definition for FSMC_PCR3 register *****************/
n0tform3	8:1c6281289d67	3862	#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
n0tform3	8:1c6281289d67	3863	#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /!<PC Card/NAND Flash memory bank enable bit /
n0tform3	8:1c6281289d67	3864	#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /!<Memory type /
n0tform3	8:1c6281289d67	3865
n0tform3	8:1c6281289d67	3866	#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
n0tform3	8:1c6281289d67	3867	#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3868	#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3869
n0tform3	8:1c6281289d67	3870	#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
n0tform3	8:1c6281289d67	3871
n0tform3	8:1c6281289d67	3872	#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
n0tform3	8:1c6281289d67	3873	#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
n0tform3	8:1c6281289d67	3874	#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
n0tform3	8:1c6281289d67	3875	#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
n0tform3	8:1c6281289d67	3876	#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3877
n0tform3	8:1c6281289d67	3878	#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
n0tform3	8:1c6281289d67	3879	#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3880	#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3881	#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3882	#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3883
n0tform3	8:1c6281289d67	3884	#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[2:0] bits (ECC page size) /
n0tform3	8:1c6281289d67	3885	#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3886	#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3887	#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3888
n0tform3	8:1c6281289d67	3889	/**************** Bit definition for FSMC_PCR4 register *****************/
n0tform3	8:1c6281289d67	3890	#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
n0tform3	8:1c6281289d67	3891	#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /!<PC Card/NAND Flash memory bank enable bit /
n0tform3	8:1c6281289d67	3892	#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /!<Memory type /
n0tform3	8:1c6281289d67	3893
n0tform3	8:1c6281289d67	3894	#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
n0tform3	8:1c6281289d67	3895	#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
n0tform3	8:1c6281289d67	3896	#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
n0tform3	8:1c6281289d67	3897
n0tform3	8:1c6281289d67	3898	#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
n0tform3	8:1c6281289d67	3899
n0tform3	8:1c6281289d67	3900	#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
n0tform3	8:1c6281289d67	3901	#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
n0tform3	8:1c6281289d67	3902	#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
n0tform3	8:1c6281289d67	3903	#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
n0tform3	8:1c6281289d67	3904	#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3905
n0tform3	8:1c6281289d67	3906	#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
n0tform3	8:1c6281289d67	3907	#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3908	#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3909	#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3910	#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3911
n0tform3	8:1c6281289d67	3912	#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[2:0] bits (ECC page size) /
n0tform3	8:1c6281289d67	3913	#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3914	#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3915	#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3916
n0tform3	8:1c6281289d67	3917	/***************** Bit definition for FSMC_SR2 register *****************/
n0tform3	8:1c6281289d67	3918	#define FSMC_SR2_IRS ((uint8_t)0x01) /!<Interrupt Rising Edge status /
n0tform3	8:1c6281289d67	3919	#define FSMC_SR2_ILS ((uint8_t)0x02) /!<Interrupt Level status /
n0tform3	8:1c6281289d67	3920	#define FSMC_SR2_IFS ((uint8_t)0x04) /!<Interrupt Falling Edge status /
n0tform3	8:1c6281289d67	3921	#define FSMC_SR2_IREN ((uint8_t)0x08) /!<Interrupt Rising Edge detection Enable bit /
n0tform3	8:1c6281289d67	3922	#define FSMC_SR2_ILEN ((uint8_t)0x10) /!<Interrupt Level detection Enable bit /
n0tform3	8:1c6281289d67	3923	#define FSMC_SR2_IFEN ((uint8_t)0x20) /!<Interrupt Falling Edge detection Enable bit /
n0tform3	8:1c6281289d67	3924	#define FSMC_SR2_FEMPT ((uint8_t)0x40) /!<FIFO empty /
n0tform3	8:1c6281289d67	3925
n0tform3	8:1c6281289d67	3926	/***************** Bit definition for FSMC_SR3 register *****************/
n0tform3	8:1c6281289d67	3927	#define FSMC_SR3_IRS ((uint8_t)0x01) /!<Interrupt Rising Edge status /
n0tform3	8:1c6281289d67	3928	#define FSMC_SR3_ILS ((uint8_t)0x02) /!<Interrupt Level status /
n0tform3	8:1c6281289d67	3929	#define FSMC_SR3_IFS ((uint8_t)0x04) /!<Interrupt Falling Edge status /
n0tform3	8:1c6281289d67	3930	#define FSMC_SR3_IREN ((uint8_t)0x08) /!<Interrupt Rising Edge detection Enable bit /
n0tform3	8:1c6281289d67	3931	#define FSMC_SR3_ILEN ((uint8_t)0x10) /!<Interrupt Level detection Enable bit /
n0tform3	8:1c6281289d67	3932	#define FSMC_SR3_IFEN ((uint8_t)0x20) /!<Interrupt Falling Edge detection Enable bit /
n0tform3	8:1c6281289d67	3933	#define FSMC_SR3_FEMPT ((uint8_t)0x40) /!<FIFO empty /
n0tform3	8:1c6281289d67	3934
n0tform3	8:1c6281289d67	3935	/***************** Bit definition for FSMC_SR4 register *****************/
n0tform3	8:1c6281289d67	3936	#define FSMC_SR4_IRS ((uint8_t)0x01) /!<Interrupt Rising Edge status /
n0tform3	8:1c6281289d67	3937	#define FSMC_SR4_ILS ((uint8_t)0x02) /!<Interrupt Level status /
n0tform3	8:1c6281289d67	3938	#define FSMC_SR4_IFS ((uint8_t)0x04) /!<Interrupt Falling Edge status /
n0tform3	8:1c6281289d67	3939	#define FSMC_SR4_IREN ((uint8_t)0x08) /!<Interrupt Rising Edge detection Enable bit /
n0tform3	8:1c6281289d67	3940	#define FSMC_SR4_ILEN ((uint8_t)0x10) /!<Interrupt Level detection Enable bit /
n0tform3	8:1c6281289d67	3941	#define FSMC_SR4_IFEN ((uint8_t)0x20) /!<Interrupt Falling Edge detection Enable bit /
n0tform3	8:1c6281289d67	3942	#define FSMC_SR4_FEMPT ((uint8_t)0x40) /!<FIFO empty /
n0tform3	8:1c6281289d67	3943
n0tform3	8:1c6281289d67	3944	/**************** Bit definition for FSMC_PMEM2 register ****************/
n0tform3	8:1c6281289d67	3945	#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /!<MEMSET2[7:0] bits (Common memory 2 setup time) /
n0tform3	8:1c6281289d67	3946	#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3947	#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3948	#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3949	#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3950	#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	3951	#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /!<Bit 5 /
n0tform3	8:1c6281289d67	3952	#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /!<Bit 6 /
n0tform3	8:1c6281289d67	3953	#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /!<Bit 7 /
n0tform3	8:1c6281289d67	3954
n0tform3	8:1c6281289d67	3955	#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /!<MEMWAIT2[7:0] bits (Common memory 2 wait time) /
n0tform3	8:1c6281289d67	3956	#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3957	#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3958	#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	3959	#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	3960	#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /!<Bit 4 /
n0tform3	8:1c6281289d67	3961	#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /!<Bit 5 /
n0tform3	8:1c6281289d67	3962	#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /!<Bit 6 /
n0tform3	8:1c6281289d67	3963	#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /!<Bit 7 /
n0tform3	8:1c6281289d67	3964
n0tform3	8:1c6281289d67	3965	#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /!<MEMHOLD2[7:0] bits (Common memory 2 hold time) /
n0tform3	8:1c6281289d67	3966	#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3967	#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3968	#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3969	#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3970	#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /!<Bit 4 /
n0tform3	8:1c6281289d67	3971	#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /!<Bit 5 /
n0tform3	8:1c6281289d67	3972	#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /!<Bit 6 /
n0tform3	8:1c6281289d67	3973	#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /!<Bit 7 /
n0tform3	8:1c6281289d67	3974
n0tform3	8:1c6281289d67	3975	#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) /
n0tform3	8:1c6281289d67	3976	#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	3977	#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	3978	#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	3979	#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	3980	#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	3981	#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /!<Bit 5 /
n0tform3	8:1c6281289d67	3982	#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /!<Bit 6 /
n0tform3	8:1c6281289d67	3983	#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /!<Bit 7 /
n0tform3	8:1c6281289d67	3984
n0tform3	8:1c6281289d67	3985	/**************** Bit definition for FSMC_PMEM3 register ****************/
n0tform3	8:1c6281289d67	3986	#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /!<MEMSET3[7:0] bits (Common memory 3 setup time) /
n0tform3	8:1c6281289d67	3987	#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	3988	#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	3989	#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	3990	#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	3991	#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	3992	#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /!<Bit 5 /
n0tform3	8:1c6281289d67	3993	#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /!<Bit 6 /
n0tform3	8:1c6281289d67	3994	#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /!<Bit 7 /
n0tform3	8:1c6281289d67	3995
n0tform3	8:1c6281289d67	3996	#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /!<MEMWAIT3[7:0] bits (Common memory 3 wait time) /
n0tform3	8:1c6281289d67	3997	#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	3998	#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	3999	#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	4000	#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	4001	#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4002	#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4003	#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4004	#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4005
n0tform3	8:1c6281289d67	4006	#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /!<MEMHOLD3[7:0] bits (Common memory 3 hold time) /
n0tform3	8:1c6281289d67	4007	#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4008	#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4009	#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4010	#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4011	#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4012	#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4013	#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4014	#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4015
n0tform3	8:1c6281289d67	4016	#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) /
n0tform3	8:1c6281289d67	4017	#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4018	#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4019	#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4020	#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4021	#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4022	#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4023	#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4024	#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4025
n0tform3	8:1c6281289d67	4026	/**************** Bit definition for FSMC_PMEM4 register ****************/
n0tform3	8:1c6281289d67	4027	#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /!<MEMSET4[7:0] bits (Common memory 4 setup time) /
n0tform3	8:1c6281289d67	4028	#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	4029	#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	4030	#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	4031	#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	4032	#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	4033	#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /!<Bit 5 /
n0tform3	8:1c6281289d67	4034	#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /!<Bit 6 /
n0tform3	8:1c6281289d67	4035	#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /!<Bit 7 /
n0tform3	8:1c6281289d67	4036
n0tform3	8:1c6281289d67	4037	#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /!<MEMWAIT4[7:0] bits (Common memory 4 wait time) /
n0tform3	8:1c6281289d67	4038	#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	4039	#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	4040	#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	4041	#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	4042	#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4043	#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4044	#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4045	#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4046
n0tform3	8:1c6281289d67	4047	#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /!<MEMHOLD4[7:0] bits (Common memory 4 hold time) /
n0tform3	8:1c6281289d67	4048	#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4049	#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4050	#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4051	#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4052	#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4053	#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4054	#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4055	#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4056
n0tform3	8:1c6281289d67	4057	#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) /
n0tform3	8:1c6281289d67	4058	#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4059	#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4060	#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4061	#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4062	#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4063	#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4064	#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4065	#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4066
n0tform3	8:1c6281289d67	4067	/**************** Bit definition for FSMC_PATT2 register ****************/
n0tform3	8:1c6281289d67	4068	#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /!<ATTSET2[7:0] bits (Attribute memory 2 setup time) /
n0tform3	8:1c6281289d67	4069	#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	4070	#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	4071	#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	4072	#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	4073	#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	4074	#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /!<Bit 5 /
n0tform3	8:1c6281289d67	4075	#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /!<Bit 6 /
n0tform3	8:1c6281289d67	4076	#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /!<Bit 7 /
n0tform3	8:1c6281289d67	4077
n0tform3	8:1c6281289d67	4078	#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) /
n0tform3	8:1c6281289d67	4079	#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	4080	#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	4081	#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	4082	#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	4083	#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4084	#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4085	#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4086	#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4087
n0tform3	8:1c6281289d67	4088	#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) /
n0tform3	8:1c6281289d67	4089	#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4090	#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4091	#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4092	#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4093	#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4094	#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4095	#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4096	#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4097
n0tform3	8:1c6281289d67	4098	#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) /
n0tform3	8:1c6281289d67	4099	#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4100	#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4101	#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4102	#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4103	#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4104	#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4105	#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4106	#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4107
n0tform3	8:1c6281289d67	4108	/**************** Bit definition for FSMC_PATT3 register ****************/
n0tform3	8:1c6281289d67	4109	#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /!<ATTSET3[7:0] bits (Attribute memory 3 setup time) /
n0tform3	8:1c6281289d67	4110	#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	4111	#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	4112	#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	4113	#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	4114	#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	4115	#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /!<Bit 5 /
n0tform3	8:1c6281289d67	4116	#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /!<Bit 6 /
n0tform3	8:1c6281289d67	4117	#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /!<Bit 7 /
n0tform3	8:1c6281289d67	4118
n0tform3	8:1c6281289d67	4119	#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) /
n0tform3	8:1c6281289d67	4120	#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	4121	#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	4122	#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	4123	#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	4124	#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4125	#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4126	#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4127	#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4128
n0tform3	8:1c6281289d67	4129	#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) /
n0tform3	8:1c6281289d67	4130	#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4131	#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4132	#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4133	#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4134	#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4135	#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4136	#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4137	#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4138
n0tform3	8:1c6281289d67	4139	#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) /
n0tform3	8:1c6281289d67	4140	#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4141	#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4142	#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4143	#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4144	#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4145	#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4146	#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4147	#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4148
n0tform3	8:1c6281289d67	4149	/**************** Bit definition for FSMC_PATT4 register ****************/
n0tform3	8:1c6281289d67	4150	#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /!<ATTSET4[7:0] bits (Attribute memory 4 setup time) /
n0tform3	8:1c6281289d67	4151	#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	4152	#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	4153	#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	4154	#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	4155	#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	4156	#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /!<Bit 5 /
n0tform3	8:1c6281289d67	4157	#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /!<Bit 6 /
n0tform3	8:1c6281289d67	4158	#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /!<Bit 7 /
n0tform3	8:1c6281289d67	4159
n0tform3	8:1c6281289d67	4160	#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) /
n0tform3	8:1c6281289d67	4161	#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	4162	#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	4163	#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	4164	#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	4165	#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4166	#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4167	#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4168	#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4169
n0tform3	8:1c6281289d67	4170	#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) /
n0tform3	8:1c6281289d67	4171	#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4172	#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4173	#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4174	#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4175	#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4176	#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4177	#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4178	#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4179
n0tform3	8:1c6281289d67	4180	#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) /
n0tform3	8:1c6281289d67	4181	#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4182	#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4183	#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4184	#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4185	#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4186	#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4187	#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4188	#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4189
n0tform3	8:1c6281289d67	4190	/**************** Bit definition for FSMC_PIO4 register *****************/
n0tform3	8:1c6281289d67	4191	#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /!<IOSET4[7:0] bits (I/O 4 setup time) /
n0tform3	8:1c6281289d67	4192	#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /!<Bit 0 /
n0tform3	8:1c6281289d67	4193	#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /!<Bit 1 /
n0tform3	8:1c6281289d67	4194	#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /!<Bit 2 /
n0tform3	8:1c6281289d67	4195	#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /!<Bit 3 /
n0tform3	8:1c6281289d67	4196	#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /!<Bit 4 /
n0tform3	8:1c6281289d67	4197	#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /!<Bit 5 /
n0tform3	8:1c6281289d67	4198	#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /!<Bit 6 /
n0tform3	8:1c6281289d67	4199	#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /!<Bit 7 /
n0tform3	8:1c6281289d67	4200
n0tform3	8:1c6281289d67	4201	#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /!<IOWAIT4[7:0] bits (I/O 4 wait time) /
n0tform3	8:1c6281289d67	4202	#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /!<Bit 0 /
n0tform3	8:1c6281289d67	4203	#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /!<Bit 1 /
n0tform3	8:1c6281289d67	4204	#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /!<Bit 2 /
n0tform3	8:1c6281289d67	4205	#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /!<Bit 3 /
n0tform3	8:1c6281289d67	4206	#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4207	#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4208	#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4209	#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4210
n0tform3	8:1c6281289d67	4211	#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /!<IOHOLD4[7:0] bits (I/O 4 hold time) /
n0tform3	8:1c6281289d67	4212	#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4213	#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4214	#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4215	#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4216	#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4217	#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4218	#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4219	#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4220
n0tform3	8:1c6281289d67	4221	#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) /
n0tform3	8:1c6281289d67	4222	#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /!<Bit 0 /
n0tform3	8:1c6281289d67	4223	#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /!<Bit 1 /
n0tform3	8:1c6281289d67	4224	#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /!<Bit 2 /
n0tform3	8:1c6281289d67	4225	#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /!<Bit 3 /
n0tform3	8:1c6281289d67	4226	#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /!<Bit 4 /
n0tform3	8:1c6281289d67	4227	#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /!<Bit 5 /
n0tform3	8:1c6281289d67	4228	#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /!<Bit 6 /
n0tform3	8:1c6281289d67	4229	#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /!<Bit 7 /
n0tform3	8:1c6281289d67	4230
n0tform3	8:1c6281289d67	4231	/**************** Bit definition for FSMC_ECCR2 register ****************/
n0tform3	8:1c6281289d67	4232	#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /!<ECC result /
n0tform3	8:1c6281289d67	4233
n0tform3	8:1c6281289d67	4234	/**************** Bit definition for FSMC_ECCR3 register ****************/
n0tform3	8:1c6281289d67	4235	#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /!<ECC result /
n0tform3	8:1c6281289d67	4236
n0tform3	8:1c6281289d67	4237	/******************************************************************************/
n0tform3	8:1c6281289d67	4238	/* */
n0tform3	8:1c6281289d67	4239	/* General Purpose I/O */
n0tform3	8:1c6281289d67	4240	/* */
n0tform3	8:1c6281289d67	4241	/******************************************************************************/
n0tform3	8:1c6281289d67	4242	/**************** Bits definition for GPIO_MODER register ***************/
n0tform3	8:1c6281289d67	4243	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
n0tform3	8:1c6281289d67	4244	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4245	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4246
n0tform3	8:1c6281289d67	4247	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
n0tform3	8:1c6281289d67	4248	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4249	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4250
n0tform3	8:1c6281289d67	4251	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
n0tform3	8:1c6281289d67	4252	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4253	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4254
n0tform3	8:1c6281289d67	4255	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
n0tform3	8:1c6281289d67	4256	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4257	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4258
n0tform3	8:1c6281289d67	4259	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
n0tform3	8:1c6281289d67	4260	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4261	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4262
n0tform3	8:1c6281289d67	4263	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
n0tform3	8:1c6281289d67	4264	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4265	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4266
n0tform3	8:1c6281289d67	4267	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
n0tform3	8:1c6281289d67	4268	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4269	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4270
n0tform3	8:1c6281289d67	4271	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
n0tform3	8:1c6281289d67	4272	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4273	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	4274
n0tform3	8:1c6281289d67	4275	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
n0tform3	8:1c6281289d67	4276	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4277	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4278
n0tform3	8:1c6281289d67	4279	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
n0tform3	8:1c6281289d67	4280	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	4281	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	4282
n0tform3	8:1c6281289d67	4283	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
n0tform3	8:1c6281289d67	4284	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	4285	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	4286
n0tform3	8:1c6281289d67	4287	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
n0tform3	8:1c6281289d67	4288	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4289	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	4290
n0tform3	8:1c6281289d67	4291	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
n0tform3	8:1c6281289d67	4292	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	4293	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4294
n0tform3	8:1c6281289d67	4295	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
n0tform3	8:1c6281289d67	4296	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	4297	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	4298
n0tform3	8:1c6281289d67	4299	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
n0tform3	8:1c6281289d67	4300	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	4301	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	4302
n0tform3	8:1c6281289d67	4303	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
n0tform3	8:1c6281289d67	4304	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	4305	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	4306
n0tform3	8:1c6281289d67	4307	/**************** Bits definition for GPIO_OTYPER register **************/
n0tform3	8:1c6281289d67	4308	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4309	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4310	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4311	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4312	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4313	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4314	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4315	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4316	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4317	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4318	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4319	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4320	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4321	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4322	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4323	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	4324
n0tform3	8:1c6281289d67	4325	/**************** Bits definition for GPIO_OSPEEDR register *************/
n0tform3	8:1c6281289d67	4326	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
n0tform3	8:1c6281289d67	4327	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4328	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4329
n0tform3	8:1c6281289d67	4330	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
n0tform3	8:1c6281289d67	4331	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4332	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4333
n0tform3	8:1c6281289d67	4334	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
n0tform3	8:1c6281289d67	4335	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4336	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4337
n0tform3	8:1c6281289d67	4338	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
n0tform3	8:1c6281289d67	4339	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4340	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4341
n0tform3	8:1c6281289d67	4342	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
n0tform3	8:1c6281289d67	4343	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4344	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4345
n0tform3	8:1c6281289d67	4346	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
n0tform3	8:1c6281289d67	4347	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4348	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4349
n0tform3	8:1c6281289d67	4350	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
n0tform3	8:1c6281289d67	4351	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4352	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4353
n0tform3	8:1c6281289d67	4354	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
n0tform3	8:1c6281289d67	4355	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4356	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	4357
n0tform3	8:1c6281289d67	4358	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
n0tform3	8:1c6281289d67	4359	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4360	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4361
n0tform3	8:1c6281289d67	4362	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
n0tform3	8:1c6281289d67	4363	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	4364	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	4365
n0tform3	8:1c6281289d67	4366	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
n0tform3	8:1c6281289d67	4367	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	4368	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	4369
n0tform3	8:1c6281289d67	4370	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
n0tform3	8:1c6281289d67	4371	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4372	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	4373
n0tform3	8:1c6281289d67	4374	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
n0tform3	8:1c6281289d67	4375	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	4376	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4377
n0tform3	8:1c6281289d67	4378	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
n0tform3	8:1c6281289d67	4379	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	4380	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	4381
n0tform3	8:1c6281289d67	4382	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
n0tform3	8:1c6281289d67	4383	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	4384	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	4385
n0tform3	8:1c6281289d67	4386	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
n0tform3	8:1c6281289d67	4387	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	4388	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	4389
n0tform3	8:1c6281289d67	4390	/**************** Bits definition for GPIO_PUPDR register ***************/
n0tform3	8:1c6281289d67	4391	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
n0tform3	8:1c6281289d67	4392	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4393	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4394
n0tform3	8:1c6281289d67	4395	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
n0tform3	8:1c6281289d67	4396	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4397	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4398
n0tform3	8:1c6281289d67	4399	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
n0tform3	8:1c6281289d67	4400	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4401	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4402
n0tform3	8:1c6281289d67	4403	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
n0tform3	8:1c6281289d67	4404	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4405	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4406
n0tform3	8:1c6281289d67	4407	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
n0tform3	8:1c6281289d67	4408	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4409	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4410
n0tform3	8:1c6281289d67	4411	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
n0tform3	8:1c6281289d67	4412	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4413	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4414
n0tform3	8:1c6281289d67	4415	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
n0tform3	8:1c6281289d67	4416	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4417	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4418
n0tform3	8:1c6281289d67	4419	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
n0tform3	8:1c6281289d67	4420	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4421	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	4422
n0tform3	8:1c6281289d67	4423	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
n0tform3	8:1c6281289d67	4424	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4425	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4426
n0tform3	8:1c6281289d67	4427	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
n0tform3	8:1c6281289d67	4428	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	4429	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	4430
n0tform3	8:1c6281289d67	4431	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
n0tform3	8:1c6281289d67	4432	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	4433	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	4434
n0tform3	8:1c6281289d67	4435	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
n0tform3	8:1c6281289d67	4436	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4437	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	4438
n0tform3	8:1c6281289d67	4439	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
n0tform3	8:1c6281289d67	4440	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	4441	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4442
n0tform3	8:1c6281289d67	4443	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
n0tform3	8:1c6281289d67	4444	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	4445	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	4446
n0tform3	8:1c6281289d67	4447	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
n0tform3	8:1c6281289d67	4448	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	4449	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	4450
n0tform3	8:1c6281289d67	4451	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
n0tform3	8:1c6281289d67	4452	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	4453	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	4454
n0tform3	8:1c6281289d67	4455	/**************** Bits definition for GPIO_IDR register *****************/
n0tform3	8:1c6281289d67	4456	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4457	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4458	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4459	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4460	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4461	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4462	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4463	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4464	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4465	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4466	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4467	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4468	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4469	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4470	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4471	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	4472	/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
n0tform3	8:1c6281289d67	4473	#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
n0tform3	8:1c6281289d67	4474	#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
n0tform3	8:1c6281289d67	4475	#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
n0tform3	8:1c6281289d67	4476	#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
n0tform3	8:1c6281289d67	4477	#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
n0tform3	8:1c6281289d67	4478	#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
n0tform3	8:1c6281289d67	4479	#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
n0tform3	8:1c6281289d67	4480	#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
n0tform3	8:1c6281289d67	4481	#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
n0tform3	8:1c6281289d67	4482	#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
n0tform3	8:1c6281289d67	4483	#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
n0tform3	8:1c6281289d67	4484	#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
n0tform3	8:1c6281289d67	4485	#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
n0tform3	8:1c6281289d67	4486	#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
n0tform3	8:1c6281289d67	4487	#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
n0tform3	8:1c6281289d67	4488	#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
n0tform3	8:1c6281289d67	4489
n0tform3	8:1c6281289d67	4490	/**************** Bits definition for GPIO_ODR register *****************/
n0tform3	8:1c6281289d67	4491	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4492	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4493	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4494	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4495	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4496	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4497	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4498	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4499	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4500	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4501	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4502	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4503	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4504	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4505	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4506	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	4507	/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
n0tform3	8:1c6281289d67	4508	#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
n0tform3	8:1c6281289d67	4509	#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
n0tform3	8:1c6281289d67	4510	#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
n0tform3	8:1c6281289d67	4511	#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
n0tform3	8:1c6281289d67	4512	#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
n0tform3	8:1c6281289d67	4513	#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
n0tform3	8:1c6281289d67	4514	#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
n0tform3	8:1c6281289d67	4515	#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
n0tform3	8:1c6281289d67	4516	#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
n0tform3	8:1c6281289d67	4517	#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
n0tform3	8:1c6281289d67	4518	#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
n0tform3	8:1c6281289d67	4519	#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
n0tform3	8:1c6281289d67	4520	#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
n0tform3	8:1c6281289d67	4521	#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
n0tform3	8:1c6281289d67	4522	#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
n0tform3	8:1c6281289d67	4523	#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
n0tform3	8:1c6281289d67	4524
n0tform3	8:1c6281289d67	4525	/**************** Bits definition for GPIO_BSRR register ****************/
n0tform3	8:1c6281289d67	4526	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4527	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4528	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4529	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4530	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4531	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4532	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4533	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4534	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4535	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4536	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4537	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4538	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4539	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4540	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4541	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	4542	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4543	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4544	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	4545	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	4546	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	4547	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	4548	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4549	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	4550	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	4551	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4552	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	4553	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	4554	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	4555	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	4556	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	4557	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	4558
n0tform3	8:1c6281289d67	4559	/******************************************************************************/
n0tform3	8:1c6281289d67	4560	/* */
n0tform3	8:1c6281289d67	4561	/* HASH */
n0tform3	8:1c6281289d67	4562	/* */
n0tform3	8:1c6281289d67	4563	/******************************************************************************/
n0tform3	8:1c6281289d67	4564	/**************** Bits definition for HASH_CR register ******************/
n0tform3	8:1c6281289d67	4565	#define HASH_CR_INIT ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4566	#define HASH_CR_DMAE ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4567	#define HASH_CR_DATATYPE ((uint32_t)0x00000030)
n0tform3	8:1c6281289d67	4568	#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4569	#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4570	#define HASH_CR_MODE ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4571	#define HASH_CR_ALGO ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4572	#define HASH_CR_NBW ((uint32_t)0x00000F00)
n0tform3	8:1c6281289d67	4573	#define HASH_CR_NBW_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4574	#define HASH_CR_NBW_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4575	#define HASH_CR_NBW_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4576	#define HASH_CR_NBW_3 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4577	#define HASH_CR_DINNE ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4578	#define HASH_CR_LKEY ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4579
n0tform3	8:1c6281289d67	4580	/**************** Bits definition for HASH_STR register *****************/
n0tform3	8:1c6281289d67	4581	#define HASH_STR_NBW ((uint32_t)0x0000001F)
n0tform3	8:1c6281289d67	4582	#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4583	#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4584	#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4585	#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4586	#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4587	#define HASH_STR_DCAL ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4588
n0tform3	8:1c6281289d67	4589	/**************** Bits definition for HASH_IMR register *****************/
n0tform3	8:1c6281289d67	4590	#define HASH_IMR_DINIM ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4591	#define HASH_IMR_DCIM ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4592
n0tform3	8:1c6281289d67	4593	/**************** Bits definition for HASH_SR register ******************/
n0tform3	8:1c6281289d67	4594	#define HASH_SR_DINIS ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4595	#define HASH_SR_DCIS ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4596	#define HASH_SR_DMAS ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4597	#define HASH_SR_BUSY ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4598
n0tform3	8:1c6281289d67	4599	/******************************************************************************/
n0tform3	8:1c6281289d67	4600	/* */
n0tform3	8:1c6281289d67	4601	/* Inter-integrated Circuit Interface */
n0tform3	8:1c6281289d67	4602	/* */
n0tform3	8:1c6281289d67	4603	/******************************************************************************/
n0tform3	8:1c6281289d67	4604	/***************** Bit definition for I2C_CR1 register ******************/
n0tform3	8:1c6281289d67	4605	#define I2C_CR1_PE ((uint16_t)0x0001) /!<Peripheral Enable /
n0tform3	8:1c6281289d67	4606	#define I2C_CR1_SMBUS ((uint16_t)0x0002) /!<SMBus Mode /
n0tform3	8:1c6281289d67	4607	#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /!<SMBus Type /
n0tform3	8:1c6281289d67	4608	#define I2C_CR1_ENARP ((uint16_t)0x0010) /!<ARP Enable /
n0tform3	8:1c6281289d67	4609	#define I2C_CR1_ENPEC ((uint16_t)0x0020) /!<PEC Enable /
n0tform3	8:1c6281289d67	4610	#define I2C_CR1_ENGC ((uint16_t)0x0040) /!<General Call Enable /
n0tform3	8:1c6281289d67	4611	#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /!<Clock Stretching Disable (Slave mode) /
n0tform3	8:1c6281289d67	4612	#define I2C_CR1_START ((uint16_t)0x0100) /!<Start Generation /
n0tform3	8:1c6281289d67	4613	#define I2C_CR1_STOP ((uint16_t)0x0200) /!<Stop Generation /
n0tform3	8:1c6281289d67	4614	#define I2C_CR1_ACK ((uint16_t)0x0400) /!<Acknowledge Enable /
n0tform3	8:1c6281289d67	4615	#define I2C_CR1_POS ((uint16_t)0x0800) /!<Acknowledge/PEC Position (for data reception) /
n0tform3	8:1c6281289d67	4616	#define I2C_CR1_PEC ((uint16_t)0x1000) /!<Packet Error Checking /
n0tform3	8:1c6281289d67	4617	#define I2C_CR1_ALERT ((uint16_t)0x2000) /!<SMBus Alert /
n0tform3	8:1c6281289d67	4618	#define I2C_CR1_SWRST ((uint16_t)0x8000) /!<Software Reset /
n0tform3	8:1c6281289d67	4619
n0tform3	8:1c6281289d67	4620	/***************** Bit definition for I2C_CR2 register ******************/
n0tform3	8:1c6281289d67	4621	#define I2C_CR2_FREQ ((uint16_t)0x003F) /!<FREQ[5:0] bits (Peripheral Clock Frequency) /
n0tform3	8:1c6281289d67	4622	#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	4623	#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	4624	#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /!<Bit 2 /
n0tform3	8:1c6281289d67	4625	#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /!<Bit 3 /
n0tform3	8:1c6281289d67	4626	#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /!<Bit 4 /
n0tform3	8:1c6281289d67	4627	#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /!<Bit 5 /
n0tform3	8:1c6281289d67	4628
n0tform3	8:1c6281289d67	4629	#define I2C_CR2_ITERREN ((uint16_t)0x0100) /!<Error Interrupt Enable /
n0tform3	8:1c6281289d67	4630	#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /!<Event Interrupt Enable /
n0tform3	8:1c6281289d67	4631	#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /!<Buffer Interrupt Enable /
n0tform3	8:1c6281289d67	4632	#define I2C_CR2_DMAEN ((uint16_t)0x0800) /!<DMA Requests Enable /
n0tform3	8:1c6281289d67	4633	#define I2C_CR2_LAST ((uint16_t)0x1000) /!<DMA Last Transfer /
n0tform3	8:1c6281289d67	4634
n0tform3	8:1c6281289d67	4635	/***************** Bit definition for I2C_OAR1 register *****************/
n0tform3	8:1c6281289d67	4636	#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /!<Interface Address /
n0tform3	8:1c6281289d67	4637	#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /!<Interface Address /
n0tform3	8:1c6281289d67	4638
n0tform3	8:1c6281289d67	4639	#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	4640	#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	4641	#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /!<Bit 2 /
n0tform3	8:1c6281289d67	4642	#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /!<Bit 3 /
n0tform3	8:1c6281289d67	4643	#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /!<Bit 4 /
n0tform3	8:1c6281289d67	4644	#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /!<Bit 5 /
n0tform3	8:1c6281289d67	4645	#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /!<Bit 6 /
n0tform3	8:1c6281289d67	4646	#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /!<Bit 7 /
n0tform3	8:1c6281289d67	4647	#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /!<Bit 8 /
n0tform3	8:1c6281289d67	4648	#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /!<Bit 9 /
n0tform3	8:1c6281289d67	4649
n0tform3	8:1c6281289d67	4650	#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /!<Addressing Mode (Slave mode) /
n0tform3	8:1c6281289d67	4651
n0tform3	8:1c6281289d67	4652	/***************** Bit definition for I2C_OAR2 register *****************/
n0tform3	8:1c6281289d67	4653	#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /!<Dual addressing mode enable /
n0tform3	8:1c6281289d67	4654	#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /!<Interface address /
n0tform3	8:1c6281289d67	4655
n0tform3	8:1c6281289d67	4656	/****************** Bit definition for I2C_DR register ******************/
n0tform3	8:1c6281289d67	4657	#define I2C_DR_DR ((uint8_t)0xFF) /!<8-bit Data Register /
n0tform3	8:1c6281289d67	4658
n0tform3	8:1c6281289d67	4659	/***************** Bit definition for I2C_SR1 register ******************/
n0tform3	8:1c6281289d67	4660	#define I2C_SR1_SB ((uint16_t)0x0001) /!<Start Bit (Master mode) /
n0tform3	8:1c6281289d67	4661	#define I2C_SR1_ADDR ((uint16_t)0x0002) /!<Address sent (master mode)/matched (slave mode) /
n0tform3	8:1c6281289d67	4662	#define I2C_SR1_BTF ((uint16_t)0x0004) /!<Byte Transfer Finished /
n0tform3	8:1c6281289d67	4663	#define I2C_SR1_ADD10 ((uint16_t)0x0008) /!<10-bit header sent (Master mode) /
n0tform3	8:1c6281289d67	4664	#define I2C_SR1_STOPF ((uint16_t)0x0010) /!<Stop detection (Slave mode) /
n0tform3	8:1c6281289d67	4665	#define I2C_SR1_RXNE ((uint16_t)0x0040) /!<Data Register not Empty (receivers) /
n0tform3	8:1c6281289d67	4666	#define I2C_SR1_TXE ((uint16_t)0x0080) /!<Data Register Empty (transmitters) /
n0tform3	8:1c6281289d67	4667	#define I2C_SR1_BERR ((uint16_t)0x0100) /!<Bus Error /
n0tform3	8:1c6281289d67	4668	#define I2C_SR1_ARLO ((uint16_t)0x0200) /!<Arbitration Lost (master mode) /
n0tform3	8:1c6281289d67	4669	#define I2C_SR1_AF ((uint16_t)0x0400) /!<Acknowledge Failure /
n0tform3	8:1c6281289d67	4670	#define I2C_SR1_OVR ((uint16_t)0x0800) /!<Overrun/Underrun /
n0tform3	8:1c6281289d67	4671	#define I2C_SR1_PECERR ((uint16_t)0x1000) /!<PEC Error in reception /
n0tform3	8:1c6281289d67	4672	#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /!<Timeout or Tlow Error /
n0tform3	8:1c6281289d67	4673	#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /!<SMBus Alert /
n0tform3	8:1c6281289d67	4674
n0tform3	8:1c6281289d67	4675	/***************** Bit definition for I2C_SR2 register ******************/
n0tform3	8:1c6281289d67	4676	#define I2C_SR2_MSL ((uint16_t)0x0001) /!<Master/Slave /
n0tform3	8:1c6281289d67	4677	#define I2C_SR2_BUSY ((uint16_t)0x0002) /!<Bus Busy /
n0tform3	8:1c6281289d67	4678	#define I2C_SR2_TRA ((uint16_t)0x0004) /!<Transmitter/Receiver /
n0tform3	8:1c6281289d67	4679	#define I2C_SR2_GENCALL ((uint16_t)0x0010) /!<General Call Address (Slave mode) /
n0tform3	8:1c6281289d67	4680	#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /!<SMBus Device Default Address (Slave mode) /
n0tform3	8:1c6281289d67	4681	#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /!<SMBus Host Header (Slave mode) /
n0tform3	8:1c6281289d67	4682	#define I2C_SR2_DUALF ((uint16_t)0x0080) /!<Dual Flag (Slave mode) /
n0tform3	8:1c6281289d67	4683	#define I2C_SR2_PEC ((uint16_t)0xFF00) /!<Packet Error Checking Register /
n0tform3	8:1c6281289d67	4684
n0tform3	8:1c6281289d67	4685	/***************** Bit definition for I2C_CCR register ******************/
n0tform3	8:1c6281289d67	4686	#define I2C_CCR_CCR ((uint16_t)0x0FFF) /!<Clock Control Register in Fast/Standard mode (Master mode) /
n0tform3	8:1c6281289d67	4687	#define I2C_CCR_DUTY ((uint16_t)0x4000) /!<Fast Mode Duty Cycle /
n0tform3	8:1c6281289d67	4688	#define I2C_CCR_FS ((uint16_t)0x8000) /!<I2C Master Mode Selection /
n0tform3	8:1c6281289d67	4689
n0tform3	8:1c6281289d67	4690	/**************** Bit definition for I2C_TRISE register *****************/
n0tform3	8:1c6281289d67	4691	#define I2C_TRISE_TRISE ((uint8_t)0x3F) /!<Maximum Rise Time in Fast/Standard mode (Master mode) /
n0tform3	8:1c6281289d67	4692
n0tform3	8:1c6281289d67	4693	/******************************************************************************/
n0tform3	8:1c6281289d67	4694	/* */
n0tform3	8:1c6281289d67	4695	/* Independent WATCHDOG */
n0tform3	8:1c6281289d67	4696	/* */
n0tform3	8:1c6281289d67	4697	/******************************************************************************/
n0tform3	8:1c6281289d67	4698	/***************** Bit definition for IWDG_KR register ******************/
n0tform3	8:1c6281289d67	4699	#define IWDG_KR_KEY ((uint16_t)0xFFFF) /!<Key value (write only, read 0000h) /
n0tform3	8:1c6281289d67	4700
n0tform3	8:1c6281289d67	4701	/***************** Bit definition for IWDG_PR register ******************/
n0tform3	8:1c6281289d67	4702	#define IWDG_PR_PR ((uint8_t)0x07) /!<PR[2:0] (Prescaler divider) /
n0tform3	8:1c6281289d67	4703	#define IWDG_PR_PR_0 ((uint8_t)0x01) /!<Bit 0 /
n0tform3	8:1c6281289d67	4704	#define IWDG_PR_PR_1 ((uint8_t)0x02) /!<Bit 1 /
n0tform3	8:1c6281289d67	4705	#define IWDG_PR_PR_2 ((uint8_t)0x04) /!<Bit 2 /
n0tform3	8:1c6281289d67	4706
n0tform3	8:1c6281289d67	4707	/***************** Bit definition for IWDG_RLR register *****************/
n0tform3	8:1c6281289d67	4708	#define IWDG_RLR_RL ((uint16_t)0x0FFF) /!<Watchdog counter reload value /
n0tform3	8:1c6281289d67	4709
n0tform3	8:1c6281289d67	4710	/***************** Bit definition for IWDG_SR register ******************/
n0tform3	8:1c6281289d67	4711	#define IWDG_SR_PVU ((uint8_t)0x01) /!<Watchdog prescaler value update /
n0tform3	8:1c6281289d67	4712	#define IWDG_SR_RVU ((uint8_t)0x02) /!<Watchdog counter reload value update /
n0tform3	8:1c6281289d67	4713
n0tform3	8:1c6281289d67	4714	/******************************************************************************/
n0tform3	8:1c6281289d67	4715	/* */
n0tform3	8:1c6281289d67	4716	/* Power Control */
n0tform3	8:1c6281289d67	4717	/* */
n0tform3	8:1c6281289d67	4718	/******************************************************************************/
n0tform3	8:1c6281289d67	4719	/****************** Bit definition for PWR_CR register ******************/
n0tform3	8:1c6281289d67	4720	#define PWR_CR_LPDS ((uint16_t)0x0001) /!< Low-Power Deepsleep /
n0tform3	8:1c6281289d67	4721	#define PWR_CR_PDDS ((uint16_t)0x0002) /!< Power Down Deepsleep /
n0tform3	8:1c6281289d67	4722	#define PWR_CR_CWUF ((uint16_t)0x0004) /!< Clear Wakeup Flag /
n0tform3	8:1c6281289d67	4723	#define PWR_CR_CSBF ((uint16_t)0x0008) /!< Clear Standby Flag /
n0tform3	8:1c6281289d67	4724	#define PWR_CR_PVDE ((uint16_t)0x0010) /!< Power Voltage Detector Enable /
n0tform3	8:1c6281289d67	4725
n0tform3	8:1c6281289d67	4726	#define PWR_CR_PLS ((uint16_t)0x00E0) /!< PLS[2:0] bits (PVD Level Selection) /
n0tform3	8:1c6281289d67	4727	#define PWR_CR_PLS_0 ((uint16_t)0x0020) /!< Bit 0 /
n0tform3	8:1c6281289d67	4728	#define PWR_CR_PLS_1 ((uint16_t)0x0040) /!< Bit 1 /
n0tform3	8:1c6281289d67	4729	#define PWR_CR_PLS_2 ((uint16_t)0x0080) /!< Bit 2 /
n0tform3	8:1c6281289d67	4730
n0tform3	8:1c6281289d67	4731
n0tform3	8:1c6281289d67	4732	/!< PVD level configuration /
n0tform3	8:1c6281289d67	4733	#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /!< PVD level 0 /
n0tform3	8:1c6281289d67	4734	#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /!< PVD level 1 /
n0tform3	8:1c6281289d67	4735	#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /!< PVD level 2 /
n0tform3	8:1c6281289d67	4736	#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /!< PVD level 3 /
n0tform3	8:1c6281289d67	4737	#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /!< PVD level 4 /
n0tform3	8:1c6281289d67	4738	#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /!< PVD level 5 /
n0tform3	8:1c6281289d67	4739	#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /!< PVD level 6 /
n0tform3	8:1c6281289d67	4740	#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /!< PVD level 7 /
n0tform3	8:1c6281289d67	4741
n0tform3	8:1c6281289d67	4742	#define PWR_CR_DBP ((uint16_t)0x0100) /!< Disable Backup Domain write protection /
n0tform3	8:1c6281289d67	4743	#define PWR_CR_FPDS ((uint16_t)0x0200) /!< Flash power down in Stop mode /
n0tform3	8:1c6281289d67	4744	#define PWR_CR_VOS ((uint16_t)0x4000) /!< Regulator voltage scaling output selection /
n0tform3	8:1c6281289d67	4745	/* Legacy define */
n0tform3	8:1c6281289d67	4746	#define PWR_CR_PMODE PWR_CR_VOS
n0tform3	8:1c6281289d67	4747
n0tform3	8:1c6281289d67	4748	/***************** Bit definition for PWR_CSR register ******************/
n0tform3	8:1c6281289d67	4749	#define PWR_CSR_WUF ((uint16_t)0x0001) /!< Wakeup Flag /
n0tform3	8:1c6281289d67	4750	#define PWR_CSR_SBF ((uint16_t)0x0002) /!< Standby Flag /
n0tform3	8:1c6281289d67	4751	#define PWR_CSR_PVDO ((uint16_t)0x0004) /!< PVD Output /
n0tform3	8:1c6281289d67	4752	#define PWR_CSR_BRR ((uint16_t)0x0008) /!< Backup regulator ready /
n0tform3	8:1c6281289d67	4753	#define PWR_CSR_EWUP ((uint16_t)0x0100) /!< Enable WKUP pin /
n0tform3	8:1c6281289d67	4754	#define PWR_CSR_BRE ((uint16_t)0x0200) /!< Backup regulator enable /
n0tform3	8:1c6281289d67	4755	#define PWR_CSR_VOSRDY ((uint16_t)0x4000) /!< Regulator voltage scaling output selection ready /
n0tform3	8:1c6281289d67	4756	/* Legacy define */
n0tform3	8:1c6281289d67	4757	#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
n0tform3	8:1c6281289d67	4758
n0tform3	8:1c6281289d67	4759	/******************************************************************************/
n0tform3	8:1c6281289d67	4760	/* */
n0tform3	8:1c6281289d67	4761	/* Reset and Clock Control */
n0tform3	8:1c6281289d67	4762	/* */
n0tform3	8:1c6281289d67	4763	/******************************************************************************/
n0tform3	8:1c6281289d67	4764	/****************** Bit definition for RCC_CR register ******************/
n0tform3	8:1c6281289d67	4765	#define RCC_CR_HSION ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4766	#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4767
n0tform3	8:1c6281289d67	4768	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
n0tform3	8:1c6281289d67	4769	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/!<Bit 0 /
n0tform3	8:1c6281289d67	4770	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/!<Bit 1 /
n0tform3	8:1c6281289d67	4771	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/!<Bit 2 /
n0tform3	8:1c6281289d67	4772	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/!<Bit 3 /
n0tform3	8:1c6281289d67	4773	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/!<Bit 4 /
n0tform3	8:1c6281289d67	4774
n0tform3	8:1c6281289d67	4775	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
n0tform3	8:1c6281289d67	4776	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/!<Bit 0 /
n0tform3	8:1c6281289d67	4777	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/!<Bit 1 /
n0tform3	8:1c6281289d67	4778	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/!<Bit 2 /
n0tform3	8:1c6281289d67	4779	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/!<Bit 3 /
n0tform3	8:1c6281289d67	4780	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/!<Bit 4 /
n0tform3	8:1c6281289d67	4781	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/!<Bit 5 /
n0tform3	8:1c6281289d67	4782	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/!<Bit 6 /
n0tform3	8:1c6281289d67	4783	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/!<Bit 7 /
n0tform3	8:1c6281289d67	4784
n0tform3	8:1c6281289d67	4785	#define RCC_CR_HSEON ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4786	#define RCC_CR_HSERDY ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4787	#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	4788	#define RCC_CR_CSSON ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	4789	#define RCC_CR_PLLON ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	4790	#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4791	#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	4792	#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	4793
n0tform3	8:1c6281289d67	4794	/****************** Bit definition for RCC_PLLCFGR register *************/
n0tform3	8:1c6281289d67	4795	#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
n0tform3	8:1c6281289d67	4796	#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4797	#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4798	#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4799	#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4800	#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4801	#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4802
n0tform3	8:1c6281289d67	4803	#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
n0tform3	8:1c6281289d67	4804	#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4805	#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4806	#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4807	#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4808	#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4809	#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4810	#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4811	#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4812	#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4813
n0tform3	8:1c6281289d67	4814	#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
n0tform3	8:1c6281289d67	4815	#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4816	#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4817
n0tform3	8:1c6281289d67	4818	#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4819	#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4820	#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
n0tform3	8:1c6281289d67	4821
n0tform3	8:1c6281289d67	4822	#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
n0tform3	8:1c6281289d67	4823	#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	4824	#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4825	#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	4826	#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	4827
n0tform3	8:1c6281289d67	4828	/****************** Bit definition for RCC_CFGR register ****************/
n0tform3	8:1c6281289d67	4829	/!< SW configuration /
n0tform3	8:1c6281289d67	4830	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
n0tform3	8:1c6281289d67	4831	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
n0tform3	8:1c6281289d67	4832	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
n0tform3	8:1c6281289d67	4833
n0tform3	8:1c6281289d67	4834	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
n0tform3	8:1c6281289d67	4835	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
n0tform3	8:1c6281289d67	4836	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
n0tform3	8:1c6281289d67	4837
n0tform3	8:1c6281289d67	4838	/!< SWS configuration /
n0tform3	8:1c6281289d67	4839	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
n0tform3	8:1c6281289d67	4840	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
n0tform3	8:1c6281289d67	4841	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
n0tform3	8:1c6281289d67	4842
n0tform3	8:1c6281289d67	4843	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
n0tform3	8:1c6281289d67	4844	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
n0tform3	8:1c6281289d67	4845	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
n0tform3	8:1c6281289d67	4846
n0tform3	8:1c6281289d67	4847	/!< HPRE configuration /
n0tform3	8:1c6281289d67	4848	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
n0tform3	8:1c6281289d67	4849	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
n0tform3	8:1c6281289d67	4850	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
n0tform3	8:1c6281289d67	4851	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
n0tform3	8:1c6281289d67	4852	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
n0tform3	8:1c6281289d67	4853
n0tform3	8:1c6281289d67	4854	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
n0tform3	8:1c6281289d67	4855	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
n0tform3	8:1c6281289d67	4856	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
n0tform3	8:1c6281289d67	4857	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
n0tform3	8:1c6281289d67	4858	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
n0tform3	8:1c6281289d67	4859	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
n0tform3	8:1c6281289d67	4860	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
n0tform3	8:1c6281289d67	4861	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
n0tform3	8:1c6281289d67	4862	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
n0tform3	8:1c6281289d67	4863
n0tform3	8:1c6281289d67	4864	/!< PPRE1 configuration /
n0tform3	8:1c6281289d67	4865	#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /!< PRE1[2:0] bits (APB1 prescaler) /
n0tform3	8:1c6281289d67	4866	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /!< Bit 0 /
n0tform3	8:1c6281289d67	4867	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /!< Bit 1 /
n0tform3	8:1c6281289d67	4868	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /!< Bit 2 /
n0tform3	8:1c6281289d67	4869
n0tform3	8:1c6281289d67	4870	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
n0tform3	8:1c6281289d67	4871	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /!< HCLK divided by 2 /
n0tform3	8:1c6281289d67	4872	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /!< HCLK divided by 4 /
n0tform3	8:1c6281289d67	4873	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /!< HCLK divided by 8 /
n0tform3	8:1c6281289d67	4874	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /!< HCLK divided by 16 /
n0tform3	8:1c6281289d67	4875
n0tform3	8:1c6281289d67	4876	/!< PPRE2 configuration /
n0tform3	8:1c6281289d67	4877	#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /!< PRE2[2:0] bits (APB2 prescaler) /
n0tform3	8:1c6281289d67	4878	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /!< Bit 0 /
n0tform3	8:1c6281289d67	4879	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /!< Bit 1 /
n0tform3	8:1c6281289d67	4880	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /!< Bit 2 /
n0tform3	8:1c6281289d67	4881
n0tform3	8:1c6281289d67	4882	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
n0tform3	8:1c6281289d67	4883	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /!< HCLK divided by 2 /
n0tform3	8:1c6281289d67	4884	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /!< HCLK divided by 4 /
n0tform3	8:1c6281289d67	4885	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /!< HCLK divided by 8 /
n0tform3	8:1c6281289d67	4886	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /!< HCLK divided by 16 /
n0tform3	8:1c6281289d67	4887
n0tform3	8:1c6281289d67	4888	/!< RTCPRE configuration /
n0tform3	8:1c6281289d67	4889	#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
n0tform3	8:1c6281289d67	4890	#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4891	#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4892	#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	4893	#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	4894	#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	4895
n0tform3	8:1c6281289d67	4896	/!< MCO1 configuration /
n0tform3	8:1c6281289d67	4897	#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
n0tform3	8:1c6281289d67	4898	#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	4899	#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4900
n0tform3	8:1c6281289d67	4901	#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	4902
n0tform3	8:1c6281289d67	4903	#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
n0tform3	8:1c6281289d67	4904	#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	4905	#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4906	#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	4907
n0tform3	8:1c6281289d67	4908	#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
n0tform3	8:1c6281289d67	4909	#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	4910	#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	4911	#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	4912
n0tform3	8:1c6281289d67	4913	#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
n0tform3	8:1c6281289d67	4914	#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	4915	#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	4916
n0tform3	8:1c6281289d67	4917	/****************** Bit definition for RCC_CIR register *****************/
n0tform3	8:1c6281289d67	4918	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4919	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4920	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4921	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4922	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4923	#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4924	#define RCC_CIR_CSSF ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4925	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4926	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	4927	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	4928	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4929	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4930	#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	4931	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4932	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4933	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	4934	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	4935	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	4936	#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	4937	#define RCC_CIR_CSSC ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	4938
n0tform3	8:1c6281289d67	4939	/****************** Bit definition for RCC_AHB1RSTR register ************/
n0tform3	8:1c6281289d67	4940	#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4941	#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4942	#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4943	#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4944	#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4945	#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4946	#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4947	#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4948	#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4949	#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4950	#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	4951	#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4952	#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4953	#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	4954
n0tform3	8:1c6281289d67	4955	/****************** Bit definition for RCC_AHB2RSTR register ************/
n0tform3	8:1c6281289d67	4956	#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4957	#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4958	#define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4959	#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4960	#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4961
n0tform3	8:1c6281289d67	4962	/****************** Bit definition for RCC_AHB3RSTR register ************/
n0tform3	8:1c6281289d67	4963	#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4964
n0tform3	8:1c6281289d67	4965	/****************** Bit definition for RCC_APB1RSTR register ************/
n0tform3	8:1c6281289d67	4966	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4967	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4968	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	4969	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	4970	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4971	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4972	#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	4973	#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	4974	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4975	#define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4976	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	4977	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	4978	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	4979	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	4980	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	4981	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	4982	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	4983	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	4984	#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	4985	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	4986	#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	4987	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	4988	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	4989
n0tform3	8:1c6281289d67	4990	/****************** Bit definition for RCC_APB2RSTR register ************/
n0tform3	8:1c6281289d67	4991	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	4992	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	4993	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	4994	#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	4995	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	4996	#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	4997	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	4998	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	4999	#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5000	#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5001	#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5002	/* Old SPI1RST bit definition, maintained for legacy purpose */
n0tform3	8:1c6281289d67	5003	#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
n0tform3	8:1c6281289d67	5004
n0tform3	8:1c6281289d67	5005	/****************** Bit definition for RCC_AHB1ENR register *************/
n0tform3	8:1c6281289d67	5006	#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5007	#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5008	#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5009	#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5010	#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5011	#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5012	#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5013	#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5014	#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5015	#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5016	#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5017	#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5018	#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5019	#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5020	#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5021	#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5022	#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	5023	#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	5024	#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	5025	#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	5026
n0tform3	8:1c6281289d67	5027	/****************** Bit definition for RCC_AHB2ENR register *************/
n0tform3	8:1c6281289d67	5028	#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5029	#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5030	#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5031	#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5032	#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5033
n0tform3	8:1c6281289d67	5034	/****************** Bit definition for RCC_AHB3ENR register *************/
n0tform3	8:1c6281289d67	5035	#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5036
n0tform3	8:1c6281289d67	5037	/****************** Bit definition for RCC_APB1ENR register *************/
n0tform3	8:1c6281289d67	5038	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5039	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5040	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5041	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5042	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5043	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5044	#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5045	#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5046	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5047	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5048	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5049	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5050	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5051	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5052	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	5053	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5054	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5055	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5056	#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	5057	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5058	#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5059	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	5060	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	5061
n0tform3	8:1c6281289d67	5062	/****************** Bit definition for RCC_APB2ENR register *************/
n0tform3	8:1c6281289d67	5063	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5064	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5065	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5066	#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5067	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5068	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5069	#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5070	#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5071	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5072	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5073	#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5074	#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5075	#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5076
n0tform3	8:1c6281289d67	5077	/****************** Bit definition for RCC_AHB1LPENR register ***********/
n0tform3	8:1c6281289d67	5078	#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5079	#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5080	#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5081	#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5082	#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5083	#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5084	#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5085	#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5086	#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5087	#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5088	#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5089	#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5090	#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5091	#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5092	#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5093	#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5094	#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5095	#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5096	#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	5097	#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	5098	#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	5099	#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	5100
n0tform3	8:1c6281289d67	5101	/****************** Bit definition for RCC_AHB2LPENR register ***********/
n0tform3	8:1c6281289d67	5102	#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5103	#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5104	#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5105	#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5106	#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5107
n0tform3	8:1c6281289d67	5108	/****************** Bit definition for RCC_AHB3LPENR register ***********/
n0tform3	8:1c6281289d67	5109	#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5110
n0tform3	8:1c6281289d67	5111	/****************** Bit definition for RCC_APB1LPENR register ***********/
n0tform3	8:1c6281289d67	5112	#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5113	#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5114	#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5115	#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5116	#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5117	#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5118	#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5119	#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5120	#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5121	#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5122	#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5123	#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5124	#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5125	#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5126	#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	5127	#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5128	#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5129	#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5130	#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	5131	#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5132	#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5133	#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	5134	#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	5135
n0tform3	8:1c6281289d67	5136	/****************** Bit definition for RCC_APB2LPENR register ***********/
n0tform3	8:1c6281289d67	5137	#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5138	#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5139	#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5140	#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5141	#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5142	#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5143	#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5144	#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5145	#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5146	#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5147	#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5148	#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5149	#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5150
n0tform3	8:1c6281289d67	5151	/****************** Bit definition for RCC_BDCR register ****************/
n0tform3	8:1c6281289d67	5152	#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5153	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5154	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5155
n0tform3	8:1c6281289d67	5156	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
n0tform3	8:1c6281289d67	5157	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5158	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5159
n0tform3	8:1c6281289d67	5160	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5161	#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5162
n0tform3	8:1c6281289d67	5163	/****************** Bit definition for RCC_CSR register *****************/
n0tform3	8:1c6281289d67	5164	#define RCC_CSR_LSION ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5165	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5166	#define RCC_CSR_RMVF ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	5167	#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5168	#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5169	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	5170	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	5171	#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	5172	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	5173	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	5174
n0tform3	8:1c6281289d67	5175	/****************** Bit definition for RCC_SSCGR register ***************/
n0tform3	8:1c6281289d67	5176	#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
n0tform3	8:1c6281289d67	5177	#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
n0tform3	8:1c6281289d67	5178	#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	5179	#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	5180
n0tform3	8:1c6281289d67	5181	/****************** Bit definition for RCC_PLLI2SCFGR register **********/
n0tform3	8:1c6281289d67	5182	#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
n0tform3	8:1c6281289d67	5183	#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
n0tform3	8:1c6281289d67	5184
n0tform3	8:1c6281289d67	5185	/******************************************************************************/
n0tform3	8:1c6281289d67	5186	/* */
n0tform3	8:1c6281289d67	5187	/* RNG */
n0tform3	8:1c6281289d67	5188	/* */
n0tform3	8:1c6281289d67	5189	/******************************************************************************/
n0tform3	8:1c6281289d67	5190	/****************** Bits definition for RNG_CR register *****************/
n0tform3	8:1c6281289d67	5191	#define RNG_CR_RNGEN ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5192	#define RNG_CR_IE ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5193
n0tform3	8:1c6281289d67	5194	/****************** Bits definition for RNG_SR register *****************/
n0tform3	8:1c6281289d67	5195	#define RNG_SR_DRDY ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5196	#define RNG_SR_CECS ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5197	#define RNG_SR_SECS ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5198	#define RNG_SR_CEIS ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5199	#define RNG_SR_SEIS ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5200
n0tform3	8:1c6281289d67	5201	/******************************************************************************/
n0tform3	8:1c6281289d67	5202	/* */
n0tform3	8:1c6281289d67	5203	/* Real-Time Clock (RTC) */
n0tform3	8:1c6281289d67	5204	/* */
n0tform3	8:1c6281289d67	5205	/******************************************************************************/
n0tform3	8:1c6281289d67	5206	/****************** Bits definition for RTC_TR register *****************/
n0tform3	8:1c6281289d67	5207	#define RTC_TR_PM ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5208	#define RTC_TR_HT ((uint32_t)0x00300000)
n0tform3	8:1c6281289d67	5209	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5210	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5211	#define RTC_TR_HU ((uint32_t)0x000F0000)
n0tform3	8:1c6281289d67	5212	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5213	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5214	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5215	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	5216	#define RTC_TR_MNT ((uint32_t)0x00007000)
n0tform3	8:1c6281289d67	5217	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5218	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5219	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5220	#define RTC_TR_MNU ((uint32_t)0x00000F00)
n0tform3	8:1c6281289d67	5221	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5222	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5223	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5224	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5225	#define RTC_TR_ST ((uint32_t)0x00000070)
n0tform3	8:1c6281289d67	5226	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5227	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5228	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5229	#define RTC_TR_SU ((uint32_t)0x0000000F)
n0tform3	8:1c6281289d67	5230	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5231	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5232	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5233	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5234
n0tform3	8:1c6281289d67	5235	/****************** Bits definition for RTC_DR register *****************/
n0tform3	8:1c6281289d67	5236	#define RTC_DR_YT ((uint32_t)0x00F00000)
n0tform3	8:1c6281289d67	5237	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5238	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5239	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5240	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	5241	#define RTC_DR_YU ((uint32_t)0x000F0000)
n0tform3	8:1c6281289d67	5242	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5243	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5244	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5245	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	5246	#define RTC_DR_WDU ((uint32_t)0x0000E000)
n0tform3	8:1c6281289d67	5247	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5248	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5249	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5250	#define RTC_DR_MT ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5251	#define RTC_DR_MU ((uint32_t)0x00000F00)
n0tform3	8:1c6281289d67	5252	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5253	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5254	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5255	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5256	#define RTC_DR_DT ((uint32_t)0x00000030)
n0tform3	8:1c6281289d67	5257	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5258	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5259	#define RTC_DR_DU ((uint32_t)0x0000000F)
n0tform3	8:1c6281289d67	5260	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5261	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5262	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5263	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5264
n0tform3	8:1c6281289d67	5265	/****************** Bits definition for RTC_CR register *****************/
n0tform3	8:1c6281289d67	5266	#define RTC_CR_COE ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	5267	#define RTC_CR_OSEL ((uint32_t)0x00600000)
n0tform3	8:1c6281289d67	5268	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5269	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5270	#define RTC_CR_POL ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5271	#define RTC_CR_COSEL ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	5272	#define RTC_CR_BCK ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5273	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5274	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5275	#define RTC_CR_TSIE ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5276	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5277	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5278	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5279	#define RTC_CR_TSE ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5280	#define RTC_CR_WUTE ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5281	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5282	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5283	#define RTC_CR_DCE ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5284	#define RTC_CR_FMT ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5285	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5286	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5287	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5288	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
n0tform3	8:1c6281289d67	5289	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5290	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5291	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5292
n0tform3	8:1c6281289d67	5293	/****************** Bits definition for RTC_ISR register ****************/
n0tform3	8:1c6281289d67	5294	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5295	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5296	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5297	#define RTC_ISR_TSF ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5298	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5299	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5300	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5301	#define RTC_ISR_INIT ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5302	#define RTC_ISR_INITF ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5303	#define RTC_ISR_RSF ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5304	#define RTC_ISR_INITS ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5305	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5306	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5307	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5308	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5309
n0tform3	8:1c6281289d67	5310	/****************** Bits definition for RTC_PRER register ***************/
n0tform3	8:1c6281289d67	5311	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
n0tform3	8:1c6281289d67	5312	#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
n0tform3	8:1c6281289d67	5313
n0tform3	8:1c6281289d67	5314	/****************** Bits definition for RTC_WUTR register ***************/
n0tform3	8:1c6281289d67	5315	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
n0tform3	8:1c6281289d67	5316
n0tform3	8:1c6281289d67	5317	/****************** Bits definition for RTC_CALIBR register *************/
n0tform3	8:1c6281289d67	5318	#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5319	#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
n0tform3	8:1c6281289d67	5320
n0tform3	8:1c6281289d67	5321	/****************** Bits definition for RTC_ALRMAR register *************/
n0tform3	8:1c6281289d67	5322	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	5323	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	5324	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
n0tform3	8:1c6281289d67	5325	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	5326	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	5327	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
n0tform3	8:1c6281289d67	5328	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	5329	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5330	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5331	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	5332	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	5333	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5334	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
n0tform3	8:1c6281289d67	5335	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5336	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5337	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
n0tform3	8:1c6281289d67	5338	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5339	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5340	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5341	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	5342	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5343	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
n0tform3	8:1c6281289d67	5344	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5345	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5346	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5347	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
n0tform3	8:1c6281289d67	5348	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5349	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5350	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5351	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5352	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5353	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
n0tform3	8:1c6281289d67	5354	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5355	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5356	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5357	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
n0tform3	8:1c6281289d67	5358	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5359	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5360	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5361	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5362
n0tform3	8:1c6281289d67	5363	/****************** Bits definition for RTC_ALRMBR register *************/
n0tform3	8:1c6281289d67	5364	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	5365	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
n0tform3	8:1c6281289d67	5366	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
n0tform3	8:1c6281289d67	5367	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
n0tform3	8:1c6281289d67	5368	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
n0tform3	8:1c6281289d67	5369	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
n0tform3	8:1c6281289d67	5370	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	5371	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5372	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5373	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	5374	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	5375	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5376	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
n0tform3	8:1c6281289d67	5377	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5378	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5379	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
n0tform3	8:1c6281289d67	5380	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5381	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5382	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5383	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	5384	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5385	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
n0tform3	8:1c6281289d67	5386	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5387	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5388	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5389	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
n0tform3	8:1c6281289d67	5390	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5391	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5392	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5393	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5394	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5395	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
n0tform3	8:1c6281289d67	5396	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5397	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5398	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5399	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
n0tform3	8:1c6281289d67	5400	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5401	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5402	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5403	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5404
n0tform3	8:1c6281289d67	5405	/****************** Bits definition for RTC_WPR register ****************/
n0tform3	8:1c6281289d67	5406	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
n0tform3	8:1c6281289d67	5407
n0tform3	8:1c6281289d67	5408	/****************** Bits definition for RTC_SSR register ****************/
n0tform3	8:1c6281289d67	5409	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
n0tform3	8:1c6281289d67	5410
n0tform3	8:1c6281289d67	5411	/****************** Bits definition for RTC_SHIFTR register *************/
n0tform3	8:1c6281289d67	5412	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
n0tform3	8:1c6281289d67	5413	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
n0tform3	8:1c6281289d67	5414
n0tform3	8:1c6281289d67	5415	/****************** Bits definition for RTC_TSTR register ***************/
n0tform3	8:1c6281289d67	5416	#define RTC_TSTR_PM ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	5417	#define RTC_TSTR_HT ((uint32_t)0x00300000)
n0tform3	8:1c6281289d67	5418	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
n0tform3	8:1c6281289d67	5419	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	5420	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
n0tform3	8:1c6281289d67	5421	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5422	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5423	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5424	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
n0tform3	8:1c6281289d67	5425	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
n0tform3	8:1c6281289d67	5426	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5427	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5428	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5429	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
n0tform3	8:1c6281289d67	5430	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5431	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5432	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5433	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5434	#define RTC_TSTR_ST ((uint32_t)0x00000070)
n0tform3	8:1c6281289d67	5435	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5436	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5437	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5438	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
n0tform3	8:1c6281289d67	5439	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5440	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5441	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5442	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5443
n0tform3	8:1c6281289d67	5444	/****************** Bits definition for RTC_TSDR register ***************/
n0tform3	8:1c6281289d67	5445	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
n0tform3	8:1c6281289d67	5446	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5447	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5448	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5449	#define RTC_TSDR_MT ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5450	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
n0tform3	8:1c6281289d67	5451	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5452	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5453	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5454	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5455	#define RTC_TSDR_DT ((uint32_t)0x00000030)
n0tform3	8:1c6281289d67	5456	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5457	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5458	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
n0tform3	8:1c6281289d67	5459	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5460	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5461	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5462	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5463
n0tform3	8:1c6281289d67	5464	/****************** Bits definition for RTC_TSSSR register **************/
n0tform3	8:1c6281289d67	5465	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
n0tform3	8:1c6281289d67	5466
n0tform3	8:1c6281289d67	5467	/****************** Bits definition for RTC_CAL register ***************/
n0tform3	8:1c6281289d67	5468	#define RTC_CALR_CALP ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5469	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5470	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5471	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
n0tform3	8:1c6281289d67	5472	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5473	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5474	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5475	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	5476	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	5477	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	5478	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	5479	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5480	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5481
n0tform3	8:1c6281289d67	5482	/****************** Bits definition for RTC_TAFCR register **************/
n0tform3	8:1c6281289d67	5483	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	5484	#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	5485	#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	5486	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
n0tform3	8:1c6281289d67	5487	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
n0tform3	8:1c6281289d67	5488	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
n0tform3	8:1c6281289d67	5489	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
n0tform3	8:1c6281289d67	5490	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
n0tform3	8:1c6281289d67	5491	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	5492	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	5493	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
n0tform3	8:1c6281289d67	5494	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	5495	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
n0tform3	8:1c6281289d67	5496	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	5497	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	5498	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	5499	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5500	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5501
n0tform3	8:1c6281289d67	5502	/****************** Bits definition for RTC_ALRMASSR register ***********/
n0tform3	8:1c6281289d67	5503	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
n0tform3	8:1c6281289d67	5504	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	5505	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5506	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5507	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	5508	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
n0tform3	8:1c6281289d67	5509
n0tform3	8:1c6281289d67	5510	/****************** Bits definition for RTC_ALRMBSSR register ***********/
n0tform3	8:1c6281289d67	5511	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
n0tform3	8:1c6281289d67	5512	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
n0tform3	8:1c6281289d67	5513	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	5514	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	5515	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
n0tform3	8:1c6281289d67	5516	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
n0tform3	8:1c6281289d67	5517
n0tform3	8:1c6281289d67	5518	/****************** Bits definition for RTC_BKP0R register **************/
n0tform3	8:1c6281289d67	5519	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5520
n0tform3	8:1c6281289d67	5521	/****************** Bits definition for RTC_BKP1R register **************/
n0tform3	8:1c6281289d67	5522	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5523
n0tform3	8:1c6281289d67	5524	/****************** Bits definition for RTC_BKP2R register **************/
n0tform3	8:1c6281289d67	5525	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5526
n0tform3	8:1c6281289d67	5527	/****************** Bits definition for RTC_BKP3R register **************/
n0tform3	8:1c6281289d67	5528	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5529
n0tform3	8:1c6281289d67	5530	/****************** Bits definition for RTC_BKP4R register **************/
n0tform3	8:1c6281289d67	5531	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5532
n0tform3	8:1c6281289d67	5533	/****************** Bits definition for RTC_BKP5R register **************/
n0tform3	8:1c6281289d67	5534	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5535
n0tform3	8:1c6281289d67	5536	/****************** Bits definition for RTC_BKP6R register **************/
n0tform3	8:1c6281289d67	5537	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5538
n0tform3	8:1c6281289d67	5539	/****************** Bits definition for RTC_BKP7R register **************/
n0tform3	8:1c6281289d67	5540	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5541
n0tform3	8:1c6281289d67	5542	/****************** Bits definition for RTC_BKP8R register **************/
n0tform3	8:1c6281289d67	5543	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5544
n0tform3	8:1c6281289d67	5545	/****************** Bits definition for RTC_BKP9R register **************/
n0tform3	8:1c6281289d67	5546	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5547
n0tform3	8:1c6281289d67	5548	/****************** Bits definition for RTC_BKP10R register *************/
n0tform3	8:1c6281289d67	5549	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5550
n0tform3	8:1c6281289d67	5551	/****************** Bits definition for RTC_BKP11R register *************/
n0tform3	8:1c6281289d67	5552	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5553
n0tform3	8:1c6281289d67	5554	/****************** Bits definition for RTC_BKP12R register *************/
n0tform3	8:1c6281289d67	5555	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5556
n0tform3	8:1c6281289d67	5557	/****************** Bits definition for RTC_BKP13R register *************/
n0tform3	8:1c6281289d67	5558	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5559
n0tform3	8:1c6281289d67	5560	/****************** Bits definition for RTC_BKP14R register *************/
n0tform3	8:1c6281289d67	5561	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5562
n0tform3	8:1c6281289d67	5563	/****************** Bits definition for RTC_BKP15R register *************/
n0tform3	8:1c6281289d67	5564	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5565
n0tform3	8:1c6281289d67	5566	/****************** Bits definition for RTC_BKP16R register *************/
n0tform3	8:1c6281289d67	5567	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5568
n0tform3	8:1c6281289d67	5569	/****************** Bits definition for RTC_BKP17R register *************/
n0tform3	8:1c6281289d67	5570	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5571
n0tform3	8:1c6281289d67	5572	/****************** Bits definition for RTC_BKP18R register *************/
n0tform3	8:1c6281289d67	5573	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5574
n0tform3	8:1c6281289d67	5575	/****************** Bits definition for RTC_BKP19R register *************/
n0tform3	8:1c6281289d67	5576	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
n0tform3	8:1c6281289d67	5577
n0tform3	8:1c6281289d67	5578	/******************************************************************************/
n0tform3	8:1c6281289d67	5579	/* */
n0tform3	8:1c6281289d67	5580	/* SD host Interface */
n0tform3	8:1c6281289d67	5581	/* */
n0tform3	8:1c6281289d67	5582	/******************************************************************************/
n0tform3	8:1c6281289d67	5583	/**************** Bit definition for SDIO_POWER register ****************/
n0tform3	8:1c6281289d67	5584	#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /!<PWRCTRL[1:0] bits (Power supply control bits) /
n0tform3	8:1c6281289d67	5585	#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /!<Bit 0 /
n0tform3	8:1c6281289d67	5586	#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /!<Bit 1 /
n0tform3	8:1c6281289d67	5587
n0tform3	8:1c6281289d67	5588	/**************** Bit definition for SDIO_CLKCR register ****************/
n0tform3	8:1c6281289d67	5589	#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /!<Clock divide factor /
n0tform3	8:1c6281289d67	5590	#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /!<Clock enable bit /
n0tform3	8:1c6281289d67	5591	#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /!<Power saving configuration bit /
n0tform3	8:1c6281289d67	5592	#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /!<Clock divider bypass enable bit /
n0tform3	8:1c6281289d67	5593
n0tform3	8:1c6281289d67	5594	#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /!<WIDBUS[1:0] bits (Wide bus mode enable bit) /
n0tform3	8:1c6281289d67	5595	#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /!<Bit 0 /
n0tform3	8:1c6281289d67	5596	#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /!<Bit 1 /
n0tform3	8:1c6281289d67	5597
n0tform3	8:1c6281289d67	5598	#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /!<SDIO_CK dephasing selection bit /
n0tform3	8:1c6281289d67	5599	#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /!<HW Flow Control enable /
n0tform3	8:1c6281289d67	5600
n0tform3	8:1c6281289d67	5601	/***************** Bit definition for SDIO_ARG register *****************/
n0tform3	8:1c6281289d67	5602	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!<Command argument /
n0tform3	8:1c6281289d67	5603
n0tform3	8:1c6281289d67	5604	/***************** Bit definition for SDIO_CMD register *****************/
n0tform3	8:1c6281289d67	5605	#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /!<Command Index /
n0tform3	8:1c6281289d67	5606
n0tform3	8:1c6281289d67	5607	#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /!<WAITRESP[1:0] bits (Wait for response bits) /
n0tform3	8:1c6281289d67	5608	#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /!< Bit 0 /
n0tform3	8:1c6281289d67	5609	#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /!< Bit 1 /
n0tform3	8:1c6281289d67	5610
n0tform3	8:1c6281289d67	5611	#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /!<CPSM Waits for Interrupt Request /
n0tform3	8:1c6281289d67	5612	#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /!<CPSM Waits for ends of data transfer (CmdPend internal signal) /
n0tform3	8:1c6281289d67	5613	#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /!<Command path state machine (CPSM) Enable bit /
n0tform3	8:1c6281289d67	5614	#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /!<SD I/O suspend command /
n0tform3	8:1c6281289d67	5615	#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /!<Enable CMD completion /
n0tform3	8:1c6281289d67	5616	#define SDIO_CMD_NIEN ((uint16_t)0x2000) /!<Not Interrupt Enable /
n0tform3	8:1c6281289d67	5617	#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /!<CE-ATA command /
n0tform3	8:1c6281289d67	5618
n0tform3	8:1c6281289d67	5619	/*************** Bit definition for SDIO_RESPCMD register ***************/
n0tform3	8:1c6281289d67	5620	#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /!<Response command index /
n0tform3	8:1c6281289d67	5621
n0tform3	8:1c6281289d67	5622	/**************** Bit definition for SDIO_RESP0 register ****************/
n0tform3	8:1c6281289d67	5623	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!<Card Status /
n0tform3	8:1c6281289d67	5624
n0tform3	8:1c6281289d67	5625	/**************** Bit definition for SDIO_RESP1 register ****************/
n0tform3	8:1c6281289d67	5626	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!<Card Status /
n0tform3	8:1c6281289d67	5627
n0tform3	8:1c6281289d67	5628	/**************** Bit definition for SDIO_RESP2 register ****************/
n0tform3	8:1c6281289d67	5629	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!<Card Status /
n0tform3	8:1c6281289d67	5630
n0tform3	8:1c6281289d67	5631	/**************** Bit definition for SDIO_RESP3 register ****************/
n0tform3	8:1c6281289d67	5632	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!<Card Status /
n0tform3	8:1c6281289d67	5633
n0tform3	8:1c6281289d67	5634	/**************** Bit definition for SDIO_RESP4 register ****************/
n0tform3	8:1c6281289d67	5635	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!<Card Status /
n0tform3	8:1c6281289d67	5636
n0tform3	8:1c6281289d67	5637	/**************** Bit definition for SDIO_DTIMER register ***************/
n0tform3	8:1c6281289d67	5638	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!<Data timeout period. /
n0tform3	8:1c6281289d67	5639
n0tform3	8:1c6281289d67	5640	/**************** Bit definition for SDIO_DLEN register *****************/
n0tform3	8:1c6281289d67	5641	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!<Data length value /
n0tform3	8:1c6281289d67	5642
n0tform3	8:1c6281289d67	5643	/**************** Bit definition for SDIO_DCTRL register ****************/
n0tform3	8:1c6281289d67	5644	#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /!<Data transfer enabled bit /
n0tform3	8:1c6281289d67	5645	#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /!<Data transfer direction selection /
n0tform3	8:1c6281289d67	5646	#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /!<Data transfer mode selection /
n0tform3	8:1c6281289d67	5647	#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /!<DMA enabled bit /
n0tform3	8:1c6281289d67	5648
n0tform3	8:1c6281289d67	5649	#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /!<DBLOCKSIZE[3:0] bits (Data block size) /
n0tform3	8:1c6281289d67	5650	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /!<Bit 0 /
n0tform3	8:1c6281289d67	5651	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /!<Bit 1 /
n0tform3	8:1c6281289d67	5652	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /!<Bit 2 /
n0tform3	8:1c6281289d67	5653	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /!<Bit 3 /
n0tform3	8:1c6281289d67	5654
n0tform3	8:1c6281289d67	5655	#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /!<Read wait start /
n0tform3	8:1c6281289d67	5656	#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /!<Read wait stop /
n0tform3	8:1c6281289d67	5657	#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /!<Read wait mode /
n0tform3	8:1c6281289d67	5658	#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /!<SD I/O enable functions /
n0tform3	8:1c6281289d67	5659
n0tform3	8:1c6281289d67	5660	/**************** Bit definition for SDIO_DCOUNT register ***************/
n0tform3	8:1c6281289d67	5661	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!<Data count value /
n0tform3	8:1c6281289d67	5662
n0tform3	8:1c6281289d67	5663	/**************** Bit definition for SDIO_STA register ******************/
n0tform3	8:1c6281289d67	5664	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!<Command response received (CRC check failed) /
n0tform3	8:1c6281289d67	5665	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!<Data block sent/received (CRC check failed) /
n0tform3	8:1c6281289d67	5666	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!<Command response timeout /
n0tform3	8:1c6281289d67	5667	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!<Data timeout /
n0tform3	8:1c6281289d67	5668	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!<Transmit FIFO underrun error /
n0tform3	8:1c6281289d67	5669	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!<Received FIFO overrun error /
n0tform3	8:1c6281289d67	5670	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!<Command response received (CRC check passed) /
n0tform3	8:1c6281289d67	5671	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!<Command sent (no response required) /
n0tform3	8:1c6281289d67	5672	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!<Data end (data counter, SDIDCOUNT, is zero) /
n0tform3	8:1c6281289d67	5673	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!<Start bit not detected on all data signals in wide bus mode /
n0tform3	8:1c6281289d67	5674	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!<Data block sent/received (CRC check passed) /
n0tform3	8:1c6281289d67	5675	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!<Command transfer in progress /
n0tform3	8:1c6281289d67	5676	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!<Data transmit in progress /
n0tform3	8:1c6281289d67	5677	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!<Data receive in progress /
n0tform3	8:1c6281289d67	5678	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
n0tform3	8:1c6281289d67	5679	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!<Receive FIFO Half Full: there are at least 8 words in the FIFO /
n0tform3	8:1c6281289d67	5680	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!<Transmit FIFO full /
n0tform3	8:1c6281289d67	5681	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!<Receive FIFO full /
n0tform3	8:1c6281289d67	5682	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!<Transmit FIFO empty /
n0tform3	8:1c6281289d67	5683	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!<Receive FIFO empty /
n0tform3	8:1c6281289d67	5684	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!<Data available in transmit FIFO /
n0tform3	8:1c6281289d67	5685	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!<Data available in receive FIFO /
n0tform3	8:1c6281289d67	5686	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!<SDIO interrupt received /
n0tform3	8:1c6281289d67	5687	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!<CE-ATA command completion signal received for CMD61 /
n0tform3	8:1c6281289d67	5688
n0tform3	8:1c6281289d67	5689	/***************** Bit definition for SDIO_ICR register *****************/
n0tform3	8:1c6281289d67	5690	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!<CCRCFAIL flag clear bit /
n0tform3	8:1c6281289d67	5691	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!<DCRCFAIL flag clear bit /
n0tform3	8:1c6281289d67	5692	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!<CTIMEOUT flag clear bit /
n0tform3	8:1c6281289d67	5693	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!<DTIMEOUT flag clear bit /
n0tform3	8:1c6281289d67	5694	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!<TXUNDERR flag clear bit /
n0tform3	8:1c6281289d67	5695	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!<RXOVERR flag clear bit /
n0tform3	8:1c6281289d67	5696	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!<CMDREND flag clear bit /
n0tform3	8:1c6281289d67	5697	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!<CMDSENT flag clear bit /
n0tform3	8:1c6281289d67	5698	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!<DATAEND flag clear bit /
n0tform3	8:1c6281289d67	5699	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!<STBITERR flag clear bit /
n0tform3	8:1c6281289d67	5700	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!<DBCKEND flag clear bit /
n0tform3	8:1c6281289d67	5701	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!<SDIOIT flag clear bit /
n0tform3	8:1c6281289d67	5702	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!<CEATAEND flag clear bit /
n0tform3	8:1c6281289d67	5703
n0tform3	8:1c6281289d67	5704	/**************** Bit definition for SDIO_MASK register *****************/
n0tform3	8:1c6281289d67	5705	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!<Command CRC Fail Interrupt Enable /
n0tform3	8:1c6281289d67	5706	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!<Data CRC Fail Interrupt Enable /
n0tform3	8:1c6281289d67	5707	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!<Command TimeOut Interrupt Enable /
n0tform3	8:1c6281289d67	5708	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!<Data TimeOut Interrupt Enable /
n0tform3	8:1c6281289d67	5709	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!<Tx FIFO UnderRun Error Interrupt Enable /
n0tform3	8:1c6281289d67	5710	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!<Rx FIFO OverRun Error Interrupt Enable /
n0tform3	8:1c6281289d67	5711	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!<Command Response Received Interrupt Enable /
n0tform3	8:1c6281289d67	5712	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!<Command Sent Interrupt Enable /
n0tform3	8:1c6281289d67	5713	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!<Data End Interrupt Enable /
n0tform3	8:1c6281289d67	5714	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!<Start Bit Error Interrupt Enable /
n0tform3	8:1c6281289d67	5715	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!<Data Block End Interrupt Enable /
n0tform3	8:1c6281289d67	5716	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!<CCommand Acting Interrupt Enable /
n0tform3	8:1c6281289d67	5717	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!<Data Transmit Acting Interrupt Enable /
n0tform3	8:1c6281289d67	5718	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!<Data receive acting interrupt enabled /
n0tform3	8:1c6281289d67	5719	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!<Tx FIFO Half Empty interrupt Enable /
n0tform3	8:1c6281289d67	5720	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!<Rx FIFO Half Full interrupt Enable /
n0tform3	8:1c6281289d67	5721	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!<Tx FIFO Full interrupt Enable /
n0tform3	8:1c6281289d67	5722	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!<Rx FIFO Full interrupt Enable /
n0tform3	8:1c6281289d67	5723	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!<Tx FIFO Empty interrupt Enable /
n0tform3	8:1c6281289d67	5724	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!<Rx FIFO Empty interrupt Enable /
n0tform3	8:1c6281289d67	5725	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!<Data available in Tx FIFO interrupt Enable /
n0tform3	8:1c6281289d67	5726	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!<Data available in Rx FIFO interrupt Enable /
n0tform3	8:1c6281289d67	5727	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!<SDIO Mode Interrupt Received interrupt Enable /
n0tform3	8:1c6281289d67	5728	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!<CE-ATA command completion signal received Interrupt Enable /
n0tform3	8:1c6281289d67	5729
n0tform3	8:1c6281289d67	5730	/*************** Bit definition for SDIO_FIFOCNT register ***************/
n0tform3	8:1c6281289d67	5731	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!<Remaining number of words to be written to or read from the FIFO /
n0tform3	8:1c6281289d67	5732
n0tform3	8:1c6281289d67	5733	/**************** Bit definition for SDIO_FIFO register *****************/
n0tform3	8:1c6281289d67	5734	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!<Receive and transmit FIFO data /
n0tform3	8:1c6281289d67	5735
n0tform3	8:1c6281289d67	5736	/******************************************************************************/
n0tform3	8:1c6281289d67	5737	/* */
n0tform3	8:1c6281289d67	5738	/* Serial Peripheral Interface */
n0tform3	8:1c6281289d67	5739	/* */
n0tform3	8:1c6281289d67	5740	/******************************************************************************/
n0tform3	8:1c6281289d67	5741	/***************** Bit definition for SPI_CR1 register ******************/
n0tform3	8:1c6281289d67	5742	#define SPI_CR1_CPHA ((uint16_t)0x0001) /!<Clock Phase /
n0tform3	8:1c6281289d67	5743	#define SPI_CR1_CPOL ((uint16_t)0x0002) /!<Clock Polarity /
n0tform3	8:1c6281289d67	5744	#define SPI_CR1_MSTR ((uint16_t)0x0004) /!<Master Selection /
n0tform3	8:1c6281289d67	5745
n0tform3	8:1c6281289d67	5746	#define SPI_CR1_BR ((uint16_t)0x0038) /!<BR[2:0] bits (Baud Rate Control) /
n0tform3	8:1c6281289d67	5747	#define SPI_CR1_BR_0 ((uint16_t)0x0008) /!<Bit 0 /
n0tform3	8:1c6281289d67	5748	#define SPI_CR1_BR_1 ((uint16_t)0x0010) /!<Bit 1 /
n0tform3	8:1c6281289d67	5749	#define SPI_CR1_BR_2 ((uint16_t)0x0020) /!<Bit 2 /
n0tform3	8:1c6281289d67	5750
n0tform3	8:1c6281289d67	5751	#define SPI_CR1_SPE ((uint16_t)0x0040) /!<SPI Enable /
n0tform3	8:1c6281289d67	5752	#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /!<Frame Format /
n0tform3	8:1c6281289d67	5753	#define SPI_CR1_SSI ((uint16_t)0x0100) /!<Internal slave select /
n0tform3	8:1c6281289d67	5754	#define SPI_CR1_SSM ((uint16_t)0x0200) /!<Software slave management /
n0tform3	8:1c6281289d67	5755	#define SPI_CR1_RXONLY ((uint16_t)0x0400) /!<Receive only /
n0tform3	8:1c6281289d67	5756	#define SPI_CR1_DFF ((uint16_t)0x0800) /!<Data Frame Format /
n0tform3	8:1c6281289d67	5757	#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /!<Transmit CRC next /
n0tform3	8:1c6281289d67	5758	#define SPI_CR1_CRCEN ((uint16_t)0x2000) /!<Hardware CRC calculation enable /
n0tform3	8:1c6281289d67	5759	#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /!<Output enable in bidirectional mode /
n0tform3	8:1c6281289d67	5760	#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /!<Bidirectional data mode enable /
n0tform3	8:1c6281289d67	5761
n0tform3	8:1c6281289d67	5762	/***************** Bit definition for SPI_CR2 register ******************/
n0tform3	8:1c6281289d67	5763	#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /!<Rx Buffer DMA Enable /
n0tform3	8:1c6281289d67	5764	#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /!<Tx Buffer DMA Enable /
n0tform3	8:1c6281289d67	5765	#define SPI_CR2_SSOE ((uint8_t)0x04) /!<SS Output Enable /
n0tform3	8:1c6281289d67	5766	#define SPI_CR2_ERRIE ((uint8_t)0x20) /!<Error Interrupt Enable /
n0tform3	8:1c6281289d67	5767	#define SPI_CR2_RXNEIE ((uint8_t)0x40) /!<RX buffer Not Empty Interrupt Enable /
n0tform3	8:1c6281289d67	5768	#define SPI_CR2_TXEIE ((uint8_t)0x80) /!<Tx buffer Empty Interrupt Enable /
n0tform3	8:1c6281289d67	5769
n0tform3	8:1c6281289d67	5770	/****************** Bit definition for SPI_SR register ******************/
n0tform3	8:1c6281289d67	5771	#define SPI_SR_RXNE ((uint8_t)0x01) /!<Receive buffer Not Empty /
n0tform3	8:1c6281289d67	5772	#define SPI_SR_TXE ((uint8_t)0x02) /!<Transmit buffer Empty /
n0tform3	8:1c6281289d67	5773	#define SPI_SR_CHSIDE ((uint8_t)0x04) /!<Channel side /
n0tform3	8:1c6281289d67	5774	#define SPI_SR_UDR ((uint8_t)0x08) /!<Underrun flag /
n0tform3	8:1c6281289d67	5775	#define SPI_SR_CRCERR ((uint8_t)0x10) /!<CRC Error flag /
n0tform3	8:1c6281289d67	5776	#define SPI_SR_MODF ((uint8_t)0x20) /!<Mode fault /
n0tform3	8:1c6281289d67	5777	#define SPI_SR_OVR ((uint8_t)0x40) /!<Overrun flag /
n0tform3	8:1c6281289d67	5778	#define SPI_SR_BSY ((uint8_t)0x80) /!<Busy flag /
n0tform3	8:1c6281289d67	5779
n0tform3	8:1c6281289d67	5780	/****************** Bit definition for SPI_DR register ******************/
n0tform3	8:1c6281289d67	5781	#define SPI_DR_DR ((uint16_t)0xFFFF) /!<Data Register /
n0tform3	8:1c6281289d67	5782
n0tform3	8:1c6281289d67	5783	/***************** Bit definition for SPI_CRCPR register ****************/
n0tform3	8:1c6281289d67	5784	#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /!<CRC polynomial register /
n0tform3	8:1c6281289d67	5785
n0tform3	8:1c6281289d67	5786	/**************** Bit definition for SPI_RXCRCR register ****************/
n0tform3	8:1c6281289d67	5787	#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /!<Rx CRC Register /
n0tform3	8:1c6281289d67	5788
n0tform3	8:1c6281289d67	5789	/**************** Bit definition for SPI_TXCRCR register ****************/
n0tform3	8:1c6281289d67	5790	#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /!<Tx CRC Register /
n0tform3	8:1c6281289d67	5791
n0tform3	8:1c6281289d67	5792	/**************** Bit definition for SPI_I2SCFGR register ***************/
n0tform3	8:1c6281289d67	5793	#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /!<Channel length (number of bits per audio channel) /
n0tform3	8:1c6281289d67	5794
n0tform3	8:1c6281289d67	5795	#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /!<DATLEN[1:0] bits (Data length to be transferred) /
n0tform3	8:1c6281289d67	5796	#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /!<Bit 0 /
n0tform3	8:1c6281289d67	5797	#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /!<Bit 1 /
n0tform3	8:1c6281289d67	5798
n0tform3	8:1c6281289d67	5799	#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /!<steady state clock polarity /
n0tform3	8:1c6281289d67	5800
n0tform3	8:1c6281289d67	5801	#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /!<I2SSTD[1:0] bits (I2S standard selection) /
n0tform3	8:1c6281289d67	5802	#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /!<Bit 0 /
n0tform3	8:1c6281289d67	5803	#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /!<Bit 1 /
n0tform3	8:1c6281289d67	5804
n0tform3	8:1c6281289d67	5805	#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /!<PCM frame synchronization /
n0tform3	8:1c6281289d67	5806
n0tform3	8:1c6281289d67	5807	#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
n0tform3	8:1c6281289d67	5808	#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /!<Bit 0 /
n0tform3	8:1c6281289d67	5809	#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /!<Bit 1 /
n0tform3	8:1c6281289d67	5810
n0tform3	8:1c6281289d67	5811	#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /!<I2S Enable /
n0tform3	8:1c6281289d67	5812	#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /!<I2S mode selection /
n0tform3	8:1c6281289d67	5813
n0tform3	8:1c6281289d67	5814	/**************** Bit definition for SPI_I2SPR register *****************/
n0tform3	8:1c6281289d67	5815	#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /!<I2S Linear prescaler /
n0tform3	8:1c6281289d67	5816	#define SPI_I2SPR_ODD ((uint16_t)0x0100) /!<Odd factor for the prescaler /
n0tform3	8:1c6281289d67	5817	#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /!<Master Clock Output Enable /
n0tform3	8:1c6281289d67	5818
n0tform3	8:1c6281289d67	5819	/******************************************************************************/
n0tform3	8:1c6281289d67	5820	/* */
n0tform3	8:1c6281289d67	5821	/* SYSCFG */
n0tform3	8:1c6281289d67	5822	/* */
n0tform3	8:1c6281289d67	5823	/******************************************************************************/
n0tform3	8:1c6281289d67	5824	/**************** Bit definition for SYSCFG_MEMRMP register *************/
n0tform3	8:1c6281289d67	5825	#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /!<SYSCFG_Memory Remap Config /
n0tform3	8:1c6281289d67	5826	#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	5827	#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	5828
n0tform3	8:1c6281289d67	5829	/**************** Bit definition for SYSCFG_PMC register ****************/
n0tform3	8:1c6281289d67	5830	#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /!<Ethernet PHY interface selection /
n0tform3	8:1c6281289d67	5831	/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
n0tform3	8:1c6281289d67	5832	#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
n0tform3	8:1c6281289d67	5833
n0tform3	8:1c6281289d67	5834	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
n0tform3	8:1c6281289d67	5835	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!<EXTI 0 configuration /
n0tform3	8:1c6281289d67	5836	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!<EXTI 1 configuration /
n0tform3	8:1c6281289d67	5837	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!<EXTI 2 configuration /
n0tform3	8:1c6281289d67	5838	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!<EXTI 3 configuration /
n0tform3	8:1c6281289d67	5839	/**
n0tform3	8:1c6281289d67	5840	* @brief EXTI0 configuration
n0tform3	8:1c6281289d67	5841	*/
n0tform3	8:1c6281289d67	5842	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!<PA[0] pin /
n0tform3	8:1c6281289d67	5843	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!<PB[0] pin /
n0tform3	8:1c6281289d67	5844	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!<PC[0] pin /
n0tform3	8:1c6281289d67	5845	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!<PD[0] pin /
n0tform3	8:1c6281289d67	5846	#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!<PE[0] pin /
n0tform3	8:1c6281289d67	5847	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!<PF[0] pin /
n0tform3	8:1c6281289d67	5848	#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /!<PG[0] pin /
n0tform3	8:1c6281289d67	5849	#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /!<PH[0] pin /
n0tform3	8:1c6281289d67	5850	#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /!<PI[0] pin /
n0tform3	8:1c6281289d67	5851	/**
n0tform3	8:1c6281289d67	5852	* @brief EXTI1 configuration
n0tform3	8:1c6281289d67	5853	*/
n0tform3	8:1c6281289d67	5854	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!<PA[1] pin /
n0tform3	8:1c6281289d67	5855	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!<PB[1] pin /
n0tform3	8:1c6281289d67	5856	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!<PC[1] pin /
n0tform3	8:1c6281289d67	5857	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!<PD[1] pin /
n0tform3	8:1c6281289d67	5858	#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!<PE[1] pin /
n0tform3	8:1c6281289d67	5859	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!<PF[1] pin /
n0tform3	8:1c6281289d67	5860	#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /!<PG[1] pin /
n0tform3	8:1c6281289d67	5861	#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /!<PH[1] pin /
n0tform3	8:1c6281289d67	5862	#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /!<PI[1] pin /
n0tform3	8:1c6281289d67	5863	/**
n0tform3	8:1c6281289d67	5864	* @brief EXTI2 configuration
n0tform3	8:1c6281289d67	5865	*/
n0tform3	8:1c6281289d67	5866	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!<PA[2] pin /
n0tform3	8:1c6281289d67	5867	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!<PB[2] pin /
n0tform3	8:1c6281289d67	5868	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!<PC[2] pin /
n0tform3	8:1c6281289d67	5869	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!<PD[2] pin /
n0tform3	8:1c6281289d67	5870	#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!<PE[2] pin /
n0tform3	8:1c6281289d67	5871	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!<PF[2] pin /
n0tform3	8:1c6281289d67	5872	#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /!<PG[2] pin /
n0tform3	8:1c6281289d67	5873	#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /!<PH[2] pin /
n0tform3	8:1c6281289d67	5874	#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /!<PI[2] pin /
n0tform3	8:1c6281289d67	5875	/**
n0tform3	8:1c6281289d67	5876	* @brief EXTI3 configuration
n0tform3	8:1c6281289d67	5877	*/
n0tform3	8:1c6281289d67	5878	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!<PA[3] pin /
n0tform3	8:1c6281289d67	5879	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!<PB[3] pin /
n0tform3	8:1c6281289d67	5880	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!<PC[3] pin /
n0tform3	8:1c6281289d67	5881	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!<PD[3] pin /
n0tform3	8:1c6281289d67	5882	#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!<PE[3] pin /
n0tform3	8:1c6281289d67	5883	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!<PF[3] pin /
n0tform3	8:1c6281289d67	5884	#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /!<PG[3] pin /
n0tform3	8:1c6281289d67	5885	#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /!<PH[3] pin /
n0tform3	8:1c6281289d67	5886	#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /!<PI[3] pin /
n0tform3	8:1c6281289d67	5887
n0tform3	8:1c6281289d67	5888	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
n0tform3	8:1c6281289d67	5889	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!<EXTI 4 configuration /
n0tform3	8:1c6281289d67	5890	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!<EXTI 5 configuration /
n0tform3	8:1c6281289d67	5891	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!<EXTI 6 configuration /
n0tform3	8:1c6281289d67	5892	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!<EXTI 7 configuration /
n0tform3	8:1c6281289d67	5893	/**
n0tform3	8:1c6281289d67	5894	* @brief EXTI4 configuration
n0tform3	8:1c6281289d67	5895	*/
n0tform3	8:1c6281289d67	5896	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!<PA[4] pin /
n0tform3	8:1c6281289d67	5897	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!<PB[4] pin /
n0tform3	8:1c6281289d67	5898	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!<PC[4] pin /
n0tform3	8:1c6281289d67	5899	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!<PD[4] pin /
n0tform3	8:1c6281289d67	5900	#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /!<PE[4] pin /
n0tform3	8:1c6281289d67	5901	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!<PF[4] pin /
n0tform3	8:1c6281289d67	5902	#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /!<PG[4] pin /
n0tform3	8:1c6281289d67	5903	#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /!<PH[4] pin /
n0tform3	8:1c6281289d67	5904	#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /!<PI[4] pin /
n0tform3	8:1c6281289d67	5905	/**
n0tform3	8:1c6281289d67	5906	* @brief EXTI5 configuration
n0tform3	8:1c6281289d67	5907	*/
n0tform3	8:1c6281289d67	5908	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!<PA[5] pin /
n0tform3	8:1c6281289d67	5909	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!<PB[5] pin /
n0tform3	8:1c6281289d67	5910	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!<PC[5] pin /
n0tform3	8:1c6281289d67	5911	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!<PD[5] pin /
n0tform3	8:1c6281289d67	5912	#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /!<PE[5] pin /
n0tform3	8:1c6281289d67	5913	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!<PF[5] pin /
n0tform3	8:1c6281289d67	5914	#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /!<PG[5] pin /
n0tform3	8:1c6281289d67	5915	#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /!<PH[5] pin /
n0tform3	8:1c6281289d67	5916	#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /!<PI[5] pin /
n0tform3	8:1c6281289d67	5917	/**
n0tform3	8:1c6281289d67	5918	* @brief EXTI6 configuration
n0tform3	8:1c6281289d67	5919	*/
n0tform3	8:1c6281289d67	5920	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!<PA[6] pin /
n0tform3	8:1c6281289d67	5921	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!<PB[6] pin /
n0tform3	8:1c6281289d67	5922	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!<PC[6] pin /
n0tform3	8:1c6281289d67	5923	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!<PD[6] pin /
n0tform3	8:1c6281289d67	5924	#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /!<PE[6] pin /
n0tform3	8:1c6281289d67	5925	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!<PF[6] pin /
n0tform3	8:1c6281289d67	5926	#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /!<PG[6] pin /
n0tform3	8:1c6281289d67	5927	#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /!<PH[6] pin /
n0tform3	8:1c6281289d67	5928	#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /!<PI[6] pin /
n0tform3	8:1c6281289d67	5929	/**
n0tform3	8:1c6281289d67	5930	* @brief EXTI7 configuration
n0tform3	8:1c6281289d67	5931	*/
n0tform3	8:1c6281289d67	5932	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!<PA[7] pin /
n0tform3	8:1c6281289d67	5933	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!<PB[7] pin /
n0tform3	8:1c6281289d67	5934	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!<PC[7] pin /
n0tform3	8:1c6281289d67	5935	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!<PD[7] pin /
n0tform3	8:1c6281289d67	5936	#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /!<PE[7] pin /
n0tform3	8:1c6281289d67	5937	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!<PF[7] pin /
n0tform3	8:1c6281289d67	5938	#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /!<PG[7] pin /
n0tform3	8:1c6281289d67	5939	#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /!<PH[7] pin /
n0tform3	8:1c6281289d67	5940	#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /!<PI[7] pin /
n0tform3	8:1c6281289d67	5941
n0tform3	8:1c6281289d67	5942	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
n0tform3	8:1c6281289d67	5943	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!<EXTI 8 configuration /
n0tform3	8:1c6281289d67	5944	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!<EXTI 9 configuration /
n0tform3	8:1c6281289d67	5945	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!<EXTI 10 configuration /
n0tform3	8:1c6281289d67	5946	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!<EXTI 11 configuration /
n0tform3	8:1c6281289d67	5947
n0tform3	8:1c6281289d67	5948	/**
n0tform3	8:1c6281289d67	5949	* @brief EXTI8 configuration
n0tform3	8:1c6281289d67	5950	*/
n0tform3	8:1c6281289d67	5951	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!<PA[8] pin /
n0tform3	8:1c6281289d67	5952	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!<PB[8] pin /
n0tform3	8:1c6281289d67	5953	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!<PC[8] pin /
n0tform3	8:1c6281289d67	5954	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!<PD[8] pin /
n0tform3	8:1c6281289d67	5955	#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!<PE[8] pin /
n0tform3	8:1c6281289d67	5956	#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /!<PF[8] pin /
n0tform3	8:1c6281289d67	5957	#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /!<PG[8] pin /
n0tform3	8:1c6281289d67	5958	#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /!<PH[8] pin /
n0tform3	8:1c6281289d67	5959	#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /!<PI[8] pin /
n0tform3	8:1c6281289d67	5960	/**
n0tform3	8:1c6281289d67	5961	* @brief EXTI9 configuration
n0tform3	8:1c6281289d67	5962	*/
n0tform3	8:1c6281289d67	5963	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!<PA[9] pin /
n0tform3	8:1c6281289d67	5964	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!<PB[9] pin /
n0tform3	8:1c6281289d67	5965	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!<PC[9] pin /
n0tform3	8:1c6281289d67	5966	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!<PD[9] pin /
n0tform3	8:1c6281289d67	5967	#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!<PE[9] pin /
n0tform3	8:1c6281289d67	5968	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!<PF[9] pin /
n0tform3	8:1c6281289d67	5969	#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /!<PG[9] pin /
n0tform3	8:1c6281289d67	5970	#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /!<PH[9] pin /
n0tform3	8:1c6281289d67	5971	#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /!<PI[9] pin /
n0tform3	8:1c6281289d67	5972	/**
n0tform3	8:1c6281289d67	5973	* @brief EXTI10 configuration
n0tform3	8:1c6281289d67	5974	*/
n0tform3	8:1c6281289d67	5975	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!<PA[10] pin /
n0tform3	8:1c6281289d67	5976	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!<PB[10] pin /
n0tform3	8:1c6281289d67	5977	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!<PC[10] pin /
n0tform3	8:1c6281289d67	5978	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!<PD[10] pin /
n0tform3	8:1c6281289d67	5979	#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!<PE[10] pin /
n0tform3	8:1c6281289d67	5980	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!<PF[10] pin /
n0tform3	8:1c6281289d67	5981	#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /!<PG[10] pin /
n0tform3	8:1c6281289d67	5982	#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /!<PH[10] pin /
n0tform3	8:1c6281289d67	5983	#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /!<PI[10] pin /
n0tform3	8:1c6281289d67	5984	/**
n0tform3	8:1c6281289d67	5985	* @brief EXTI11 configuration
n0tform3	8:1c6281289d67	5986	*/
n0tform3	8:1c6281289d67	5987	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!<PA[11] pin /
n0tform3	8:1c6281289d67	5988	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!<PB[11] pin /
n0tform3	8:1c6281289d67	5989	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!<PC[11] pin /
n0tform3	8:1c6281289d67	5990	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!<PD[11] pin /
n0tform3	8:1c6281289d67	5991	#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!<PE[11] pin /
n0tform3	8:1c6281289d67	5992	#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /!<PF[11] pin /
n0tform3	8:1c6281289d67	5993	#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /!<PG[11] pin /
n0tform3	8:1c6281289d67	5994	#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /!<PH[11] pin /
n0tform3	8:1c6281289d67	5995	#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /!<PI[11] pin /
n0tform3	8:1c6281289d67	5996
n0tform3	8:1c6281289d67	5997	/*************** Bit definition for SYSCFG_EXTICR4 register *************/
n0tform3	8:1c6281289d67	5998	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!<EXTI 12 configuration /
n0tform3	8:1c6281289d67	5999	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!<EXTI 13 configuration /
n0tform3	8:1c6281289d67	6000	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!<EXTI 14 configuration /
n0tform3	8:1c6281289d67	6001	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!<EXTI 15 configuration /
n0tform3	8:1c6281289d67	6002	/**
n0tform3	8:1c6281289d67	6003	* @brief EXTI12 configuration
n0tform3	8:1c6281289d67	6004	*/
n0tform3	8:1c6281289d67	6005	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!<PA[12] pin /
n0tform3	8:1c6281289d67	6006	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!<PB[12] pin /
n0tform3	8:1c6281289d67	6007	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!<PC[12] pin /
n0tform3	8:1c6281289d67	6008	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!<PD[12] pin /
n0tform3	8:1c6281289d67	6009	#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!<PE[12] pin /
n0tform3	8:1c6281289d67	6010	#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /!<PF[12] pin /
n0tform3	8:1c6281289d67	6011	#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /!<PG[12] pin /
n0tform3	8:1c6281289d67	6012	#define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) /!<PH[12] pin /
n0tform3	8:1c6281289d67	6013	/**
n0tform3	8:1c6281289d67	6014	* @brief EXTI13 configuration
n0tform3	8:1c6281289d67	6015	*/
n0tform3	8:1c6281289d67	6016	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!<PA[13] pin /
n0tform3	8:1c6281289d67	6017	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!<PB[13] pin /
n0tform3	8:1c6281289d67	6018	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!<PC[13] pin /
n0tform3	8:1c6281289d67	6019	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!<PD[13] pin /
n0tform3	8:1c6281289d67	6020	#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!<PE[13] pin /
n0tform3	8:1c6281289d67	6021	#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /!<PF[13] pin /
n0tform3	8:1c6281289d67	6022	#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /!<PG[13] pin /
n0tform3	8:1c6281289d67	6023	#define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) /!<PH[13] pin /
n0tform3	8:1c6281289d67	6024	/**
n0tform3	8:1c6281289d67	6025	* @brief EXTI14 configuration
n0tform3	8:1c6281289d67	6026	*/
n0tform3	8:1c6281289d67	6027	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!<PA[14] pin /
n0tform3	8:1c6281289d67	6028	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!<PB[14] pin /
n0tform3	8:1c6281289d67	6029	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!<PC[14] pin /
n0tform3	8:1c6281289d67	6030	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!<PD[14] pin /
n0tform3	8:1c6281289d67	6031	#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!<PE[14] pin /
n0tform3	8:1c6281289d67	6032	#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /!<PF[14] pin /
n0tform3	8:1c6281289d67	6033	#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /!<PG[14] pin /
n0tform3	8:1c6281289d67	6034	#define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) /!<PH[14] pin /
n0tform3	8:1c6281289d67	6035	/**
n0tform3	8:1c6281289d67	6036	* @brief EXTI15 configuration
n0tform3	8:1c6281289d67	6037	*/
n0tform3	8:1c6281289d67	6038	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!<PA[15] pin /
n0tform3	8:1c6281289d67	6039	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!<PB[15] pin /
n0tform3	8:1c6281289d67	6040	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!<PC[15] pin /
n0tform3	8:1c6281289d67	6041	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!<PD[15] pin /
n0tform3	8:1c6281289d67	6042	#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!<PE[15] pin /
n0tform3	8:1c6281289d67	6043	#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /!<PF[15] pin /
n0tform3	8:1c6281289d67	6044	#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /!<PG[15] pin /
n0tform3	8:1c6281289d67	6045	#define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) /!<PH[15] pin /
n0tform3	8:1c6281289d67	6046
n0tform3	8:1c6281289d67	6047	/**************** Bit definition for SYSCFG_CMPCR register **************/
n0tform3	8:1c6281289d67	6048	#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /!<Compensation cell ready flag /
n0tform3	8:1c6281289d67	6049	#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /!<Compensation cell power-down /
n0tform3	8:1c6281289d67	6050
n0tform3	8:1c6281289d67	6051	/******************************************************************************/
n0tform3	8:1c6281289d67	6052	/* */
n0tform3	8:1c6281289d67	6053	/* TIM */
n0tform3	8:1c6281289d67	6054	/* */
n0tform3	8:1c6281289d67	6055	/******************************************************************************/
n0tform3	8:1c6281289d67	6056	/***************** Bit definition for TIM_CR1 register ******************/
n0tform3	8:1c6281289d67	6057	#define TIM_CR1_CEN ((uint16_t)0x0001) /!<Counter enable /
n0tform3	8:1c6281289d67	6058	#define TIM_CR1_UDIS ((uint16_t)0x0002) /!<Update disable /
n0tform3	8:1c6281289d67	6059	#define TIM_CR1_URS ((uint16_t)0x0004) /!<Update request source /
n0tform3	8:1c6281289d67	6060	#define TIM_CR1_OPM ((uint16_t)0x0008) /!<One pulse mode /
n0tform3	8:1c6281289d67	6061	#define TIM_CR1_DIR ((uint16_t)0x0010) /!<Direction /
n0tform3	8:1c6281289d67	6062
n0tform3	8:1c6281289d67	6063	#define TIM_CR1_CMS ((uint16_t)0x0060) /!<CMS[1:0] bits (Center-aligned mode selection) /
n0tform3	8:1c6281289d67	6064	#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /!<Bit 0 /
n0tform3	8:1c6281289d67	6065	#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /!<Bit 1 /
n0tform3	8:1c6281289d67	6066
n0tform3	8:1c6281289d67	6067	#define TIM_CR1_ARPE ((uint16_t)0x0080) /!<Auto-reload preload enable /
n0tform3	8:1c6281289d67	6068
n0tform3	8:1c6281289d67	6069	#define TIM_CR1_CKD ((uint16_t)0x0300) /!<CKD[1:0] bits (clock division) /
n0tform3	8:1c6281289d67	6070	#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /!<Bit 0 /
n0tform3	8:1c6281289d67	6071	#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /!<Bit 1 /
n0tform3	8:1c6281289d67	6072
n0tform3	8:1c6281289d67	6073	/***************** Bit definition for TIM_CR2 register ******************/
n0tform3	8:1c6281289d67	6074	#define TIM_CR2_CCPC ((uint16_t)0x0001) /!<Capture/Compare Preloaded Control /
n0tform3	8:1c6281289d67	6075	#define TIM_CR2_CCUS ((uint16_t)0x0004) /!<Capture/Compare Control Update Selection /
n0tform3	8:1c6281289d67	6076	#define TIM_CR2_CCDS ((uint16_t)0x0008) /!<Capture/Compare DMA Selection /
n0tform3	8:1c6281289d67	6077
n0tform3	8:1c6281289d67	6078	#define TIM_CR2_MMS ((uint16_t)0x0070) /!<MMS[2:0] bits (Master Mode Selection) /
n0tform3	8:1c6281289d67	6079	#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /!<Bit 0 /
n0tform3	8:1c6281289d67	6080	#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /!<Bit 1 /
n0tform3	8:1c6281289d67	6081	#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /!<Bit 2 /
n0tform3	8:1c6281289d67	6082
n0tform3	8:1c6281289d67	6083	#define TIM_CR2_TI1S ((uint16_t)0x0080) /!<TI1 Selection /
n0tform3	8:1c6281289d67	6084	#define TIM_CR2_OIS1 ((uint16_t)0x0100) /!<Output Idle state 1 (OC1 output) /
n0tform3	8:1c6281289d67	6085	#define TIM_CR2_OIS1N ((uint16_t)0x0200) /!<Output Idle state 1 (OC1N output) /
n0tform3	8:1c6281289d67	6086	#define TIM_CR2_OIS2 ((uint16_t)0x0400) /!<Output Idle state 2 (OC2 output) /
n0tform3	8:1c6281289d67	6087	#define TIM_CR2_OIS2N ((uint16_t)0x0800) /!<Output Idle state 2 (OC2N output) /
n0tform3	8:1c6281289d67	6088	#define TIM_CR2_OIS3 ((uint16_t)0x1000) /!<Output Idle state 3 (OC3 output) /
n0tform3	8:1c6281289d67	6089	#define TIM_CR2_OIS3N ((uint16_t)0x2000) /!<Output Idle state 3 (OC3N output) /
n0tform3	8:1c6281289d67	6090	#define TIM_CR2_OIS4 ((uint16_t)0x4000) /!<Output Idle state 4 (OC4 output) /
n0tform3	8:1c6281289d67	6091
n0tform3	8:1c6281289d67	6092	/***************** Bit definition for TIM_SMCR register *****************/
n0tform3	8:1c6281289d67	6093	#define TIM_SMCR_SMS ((uint16_t)0x0007) /!<SMS[2:0] bits (Slave mode selection) /
n0tform3	8:1c6281289d67	6094	#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	6095	#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	6096	#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /!<Bit 2 /
n0tform3	8:1c6281289d67	6097
n0tform3	8:1c6281289d67	6098	#define TIM_SMCR_TS ((uint16_t)0x0070) /!<TS[2:0] bits (Trigger selection) /
n0tform3	8:1c6281289d67	6099	#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /!<Bit 0 /
n0tform3	8:1c6281289d67	6100	#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /!<Bit 1 /
n0tform3	8:1c6281289d67	6101	#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /!<Bit 2 /
n0tform3	8:1c6281289d67	6102
n0tform3	8:1c6281289d67	6103	#define TIM_SMCR_MSM ((uint16_t)0x0080) /!<Master/slave mode /
n0tform3	8:1c6281289d67	6104
n0tform3	8:1c6281289d67	6105	#define TIM_SMCR_ETF ((uint16_t)0x0F00) /!<ETF[3:0] bits (External trigger filter) /
n0tform3	8:1c6281289d67	6106	#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /!<Bit 0 /
n0tform3	8:1c6281289d67	6107	#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /!<Bit 1 /
n0tform3	8:1c6281289d67	6108	#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /!<Bit 2 /
n0tform3	8:1c6281289d67	6109	#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /!<Bit 3 /
n0tform3	8:1c6281289d67	6110
n0tform3	8:1c6281289d67	6111	#define TIM_SMCR_ETPS ((uint16_t)0x3000) /!<ETPS[1:0] bits (External trigger prescaler) /
n0tform3	8:1c6281289d67	6112	#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /!<Bit 0 /
n0tform3	8:1c6281289d67	6113	#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /!<Bit 1 /
n0tform3	8:1c6281289d67	6114
n0tform3	8:1c6281289d67	6115	#define TIM_SMCR_ECE ((uint16_t)0x4000) /!<External clock enable /
n0tform3	8:1c6281289d67	6116	#define TIM_SMCR_ETP ((uint16_t)0x8000) /!<External trigger polarity /
n0tform3	8:1c6281289d67	6117
n0tform3	8:1c6281289d67	6118	/***************** Bit definition for TIM_DIER register *****************/
n0tform3	8:1c6281289d67	6119	#define TIM_DIER_UIE ((uint16_t)0x0001) /!<Update interrupt enable /
n0tform3	8:1c6281289d67	6120	#define TIM_DIER_CC1IE ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt enable /
n0tform3	8:1c6281289d67	6121	#define TIM_DIER_CC2IE ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt enable /
n0tform3	8:1c6281289d67	6122	#define TIM_DIER_CC3IE ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt enable /
n0tform3	8:1c6281289d67	6123	#define TIM_DIER_CC4IE ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt enable /
n0tform3	8:1c6281289d67	6124	#define TIM_DIER_COMIE ((uint16_t)0x0020) /!<COM interrupt enable /
n0tform3	8:1c6281289d67	6125	#define TIM_DIER_TIE ((uint16_t)0x0040) /!<Trigger interrupt enable /
n0tform3	8:1c6281289d67	6126	#define TIM_DIER_BIE ((uint16_t)0x0080) /!<Break interrupt enable /
n0tform3	8:1c6281289d67	6127	#define TIM_DIER_UDE ((uint16_t)0x0100) /!<Update DMA request enable /
n0tform3	8:1c6281289d67	6128	#define TIM_DIER_CC1DE ((uint16_t)0x0200) /!<Capture/Compare 1 DMA request enable /
n0tform3	8:1c6281289d67	6129	#define TIM_DIER_CC2DE ((uint16_t)0x0400) /!<Capture/Compare 2 DMA request enable /
n0tform3	8:1c6281289d67	6130	#define TIM_DIER_CC3DE ((uint16_t)0x0800) /!<Capture/Compare 3 DMA request enable /
n0tform3	8:1c6281289d67	6131	#define TIM_DIER_CC4DE ((uint16_t)0x1000) /!<Capture/Compare 4 DMA request enable /
n0tform3	8:1c6281289d67	6132	#define TIM_DIER_COMDE ((uint16_t)0x2000) /!<COM DMA request enable /
n0tform3	8:1c6281289d67	6133	#define TIM_DIER_TDE ((uint16_t)0x4000) /!<Trigger DMA request enable /
n0tform3	8:1c6281289d67	6134
n0tform3	8:1c6281289d67	6135	/****************** Bit definition for TIM_SR register ******************/
n0tform3	8:1c6281289d67	6136	#define TIM_SR_UIF ((uint16_t)0x0001) /!<Update interrupt Flag /
n0tform3	8:1c6281289d67	6137	#define TIM_SR_CC1IF ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt Flag /
n0tform3	8:1c6281289d67	6138	#define TIM_SR_CC2IF ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt Flag /
n0tform3	8:1c6281289d67	6139	#define TIM_SR_CC3IF ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt Flag /
n0tform3	8:1c6281289d67	6140	#define TIM_SR_CC4IF ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt Flag /
n0tform3	8:1c6281289d67	6141	#define TIM_SR_COMIF ((uint16_t)0x0020) /!<COM interrupt Flag /
n0tform3	8:1c6281289d67	6142	#define TIM_SR_TIF ((uint16_t)0x0040) /!<Trigger interrupt Flag /
n0tform3	8:1c6281289d67	6143	#define TIM_SR_BIF ((uint16_t)0x0080) /!<Break interrupt Flag /
n0tform3	8:1c6281289d67	6144	#define TIM_SR_CC1OF ((uint16_t)0x0200) /!<Capture/Compare 1 Overcapture Flag /
n0tform3	8:1c6281289d67	6145	#define TIM_SR_CC2OF ((uint16_t)0x0400) /!<Capture/Compare 2 Overcapture Flag /
n0tform3	8:1c6281289d67	6146	#define TIM_SR_CC3OF ((uint16_t)0x0800) /!<Capture/Compare 3 Overcapture Flag /
n0tform3	8:1c6281289d67	6147	#define TIM_SR_CC4OF ((uint16_t)0x1000) /!<Capture/Compare 4 Overcapture Flag /
n0tform3	8:1c6281289d67	6148
n0tform3	8:1c6281289d67	6149	/***************** Bit definition for TIM_EGR register ******************/
n0tform3	8:1c6281289d67	6150	#define TIM_EGR_UG ((uint8_t)0x01) /!<Update Generation /
n0tform3	8:1c6281289d67	6151	#define TIM_EGR_CC1G ((uint8_t)0x02) /!<Capture/Compare 1 Generation /
n0tform3	8:1c6281289d67	6152	#define TIM_EGR_CC2G ((uint8_t)0x04) /!<Capture/Compare 2 Generation /
n0tform3	8:1c6281289d67	6153	#define TIM_EGR_CC3G ((uint8_t)0x08) /!<Capture/Compare 3 Generation /
n0tform3	8:1c6281289d67	6154	#define TIM_EGR_CC4G ((uint8_t)0x10) /!<Capture/Compare 4 Generation /
n0tform3	8:1c6281289d67	6155	#define TIM_EGR_COMG ((uint8_t)0x20) /!<Capture/Compare Control Update Generation /
n0tform3	8:1c6281289d67	6156	#define TIM_EGR_TG ((uint8_t)0x40) /!<Trigger Generation /
n0tform3	8:1c6281289d67	6157	#define TIM_EGR_BG ((uint8_t)0x80) /!<Break Generation /
n0tform3	8:1c6281289d67	6158
n0tform3	8:1c6281289d67	6159	/**************** Bit definition for TIM_CCMR1 register *****************/
n0tform3	8:1c6281289d67	6160	#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
n0tform3	8:1c6281289d67	6161	#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	6162	#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	6163
n0tform3	8:1c6281289d67	6164	#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /!<Output Compare 1 Fast enable /
n0tform3	8:1c6281289d67	6165	#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /!<Output Compare 1 Preload enable /
n0tform3	8:1c6281289d67	6166
n0tform3	8:1c6281289d67	6167	#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
n0tform3	8:1c6281289d67	6168	#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /!<Bit 0 /
n0tform3	8:1c6281289d67	6169	#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /!<Bit 1 /
n0tform3	8:1c6281289d67	6170	#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /!<Bit 2 /
n0tform3	8:1c6281289d67	6171
n0tform3	8:1c6281289d67	6172	#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /!<Output Compare 1Clear Enable /
n0tform3	8:1c6281289d67	6173
n0tform3	8:1c6281289d67	6174	#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
n0tform3	8:1c6281289d67	6175	#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /!<Bit 0 /
n0tform3	8:1c6281289d67	6176	#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /!<Bit 1 /
n0tform3	8:1c6281289d67	6177
n0tform3	8:1c6281289d67	6178	#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /!<Output Compare 2 Fast enable /
n0tform3	8:1c6281289d67	6179	#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /!<Output Compare 2 Preload enable /
n0tform3	8:1c6281289d67	6180
n0tform3	8:1c6281289d67	6181	#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
n0tform3	8:1c6281289d67	6182	#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /!<Bit 0 /
n0tform3	8:1c6281289d67	6183	#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /!<Bit 1 /
n0tform3	8:1c6281289d67	6184	#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /!<Bit 2 /
n0tform3	8:1c6281289d67	6185
n0tform3	8:1c6281289d67	6186	#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /!<Output Compare 2 Clear Enable /
n0tform3	8:1c6281289d67	6187
n0tform3	8:1c6281289d67	6188	/----------------------------------------------------------------------------/
n0tform3	8:1c6281289d67	6189
n0tform3	8:1c6281289d67	6190	#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
n0tform3	8:1c6281289d67	6191	#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /!<Bit 0 /
n0tform3	8:1c6281289d67	6192	#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /!<Bit 1 /
n0tform3	8:1c6281289d67	6193
n0tform3	8:1c6281289d67	6194	#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
n0tform3	8:1c6281289d67	6195	#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /!<Bit 0 /
n0tform3	8:1c6281289d67	6196	#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /!<Bit 1 /
n0tform3	8:1c6281289d67	6197	#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /!<Bit 2 /
n0tform3	8:1c6281289d67	6198	#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /!<Bit 3 /
n0tform3	8:1c6281289d67	6199
n0tform3	8:1c6281289d67	6200	#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
n0tform3	8:1c6281289d67	6201	#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /!<Bit 0 /
n0tform3	8:1c6281289d67	6202	#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /!<Bit 1 /
n0tform3	8:1c6281289d67	6203
n0tform3	8:1c6281289d67	6204	#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
n0tform3	8:1c6281289d67	6205	#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /!<Bit 0 /
n0tform3	8:1c6281289d67	6206	#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /!<Bit 1 /
n0tform3	8:1c6281289d67	6207	#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /!<Bit 2 /
n0tform3	8:1c6281289d67	6208	#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /!<Bit 3 /
n0tform3	8:1c6281289d67	6209
n0tform3	8:1c6281289d67	6210	/**************** Bit definition for TIM_CCMR2 register *****************/
n0tform3	8:1c6281289d67	6211	#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
n0tform3	8:1c6281289d67	6212	#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	6213	#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	6214
n0tform3	8:1c6281289d67	6215	#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /!<Output Compare 3 Fast enable /
n0tform3	8:1c6281289d67	6216	#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /!<Output Compare 3 Preload enable /
n0tform3	8:1c6281289d67	6217
n0tform3	8:1c6281289d67	6218	#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
n0tform3	8:1c6281289d67	6219	#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /!<Bit 0 /
n0tform3	8:1c6281289d67	6220	#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /!<Bit 1 /
n0tform3	8:1c6281289d67	6221	#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /!<Bit 2 /
n0tform3	8:1c6281289d67	6222
n0tform3	8:1c6281289d67	6223	#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /!<Output Compare 3 Clear Enable /
n0tform3	8:1c6281289d67	6224
n0tform3	8:1c6281289d67	6225	#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
n0tform3	8:1c6281289d67	6226	#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /!<Bit 0 /
n0tform3	8:1c6281289d67	6227	#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /!<Bit 1 /
n0tform3	8:1c6281289d67	6228
n0tform3	8:1c6281289d67	6229	#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /!<Output Compare 4 Fast enable /
n0tform3	8:1c6281289d67	6230	#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /!<Output Compare 4 Preload enable /
n0tform3	8:1c6281289d67	6231
n0tform3	8:1c6281289d67	6232	#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
n0tform3	8:1c6281289d67	6233	#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /!<Bit 0 /
n0tform3	8:1c6281289d67	6234	#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /!<Bit 1 /
n0tform3	8:1c6281289d67	6235	#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /!<Bit 2 /
n0tform3	8:1c6281289d67	6236
n0tform3	8:1c6281289d67	6237	#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /!<Output Compare 4 Clear Enable /
n0tform3	8:1c6281289d67	6238
n0tform3	8:1c6281289d67	6239	/----------------------------------------------------------------------------/
n0tform3	8:1c6281289d67	6240
n0tform3	8:1c6281289d67	6241	#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
n0tform3	8:1c6281289d67	6242	#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /!<Bit 0 /
n0tform3	8:1c6281289d67	6243	#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /!<Bit 1 /
n0tform3	8:1c6281289d67	6244
n0tform3	8:1c6281289d67	6245	#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
n0tform3	8:1c6281289d67	6246	#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /!<Bit 0 /
n0tform3	8:1c6281289d67	6247	#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /!<Bit 1 /
n0tform3	8:1c6281289d67	6248	#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /!<Bit 2 /
n0tform3	8:1c6281289d67	6249	#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /!<Bit 3 /
n0tform3	8:1c6281289d67	6250
n0tform3	8:1c6281289d67	6251	#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
n0tform3	8:1c6281289d67	6252	#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /!<Bit 0 /
n0tform3	8:1c6281289d67	6253	#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /!<Bit 1 /
n0tform3	8:1c6281289d67	6254
n0tform3	8:1c6281289d67	6255	#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
n0tform3	8:1c6281289d67	6256	#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /!<Bit 0 /
n0tform3	8:1c6281289d67	6257	#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /!<Bit 1 /
n0tform3	8:1c6281289d67	6258	#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /!<Bit 2 /
n0tform3	8:1c6281289d67	6259	#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /!<Bit 3 /
n0tform3	8:1c6281289d67	6260
n0tform3	8:1c6281289d67	6261	/***************** Bit definition for TIM_CCER register *****************/
n0tform3	8:1c6281289d67	6262	#define TIM_CCER_CC1E ((uint16_t)0x0001) /!<Capture/Compare 1 output enable /
n0tform3	8:1c6281289d67	6263	#define TIM_CCER_CC1P ((uint16_t)0x0002) /!<Capture/Compare 1 output Polarity /
n0tform3	8:1c6281289d67	6264	#define TIM_CCER_CC1NE ((uint16_t)0x0004) /!<Capture/Compare 1 Complementary output enable /
n0tform3	8:1c6281289d67	6265	#define TIM_CCER_CC1NP ((uint16_t)0x0008) /!<Capture/Compare 1 Complementary output Polarity /
n0tform3	8:1c6281289d67	6266	#define TIM_CCER_CC2E ((uint16_t)0x0010) /!<Capture/Compare 2 output enable /
n0tform3	8:1c6281289d67	6267	#define TIM_CCER_CC2P ((uint16_t)0x0020) /!<Capture/Compare 2 output Polarity /
n0tform3	8:1c6281289d67	6268	#define TIM_CCER_CC2NE ((uint16_t)0x0040) /!<Capture/Compare 2 Complementary output enable /
n0tform3	8:1c6281289d67	6269	#define TIM_CCER_CC2NP ((uint16_t)0x0080) /!<Capture/Compare 2 Complementary output Polarity /
n0tform3	8:1c6281289d67	6270	#define TIM_CCER_CC3E ((uint16_t)0x0100) /!<Capture/Compare 3 output enable /
n0tform3	8:1c6281289d67	6271	#define TIM_CCER_CC3P ((uint16_t)0x0200) /!<Capture/Compare 3 output Polarity /
n0tform3	8:1c6281289d67	6272	#define TIM_CCER_CC3NE ((uint16_t)0x0400) /!<Capture/Compare 3 Complementary output enable /
n0tform3	8:1c6281289d67	6273	#define TIM_CCER_CC3NP ((uint16_t)0x0800) /!<Capture/Compare 3 Complementary output Polarity /
n0tform3	8:1c6281289d67	6274	#define TIM_CCER_CC4E ((uint16_t)0x1000) /!<Capture/Compare 4 output enable /
n0tform3	8:1c6281289d67	6275	#define TIM_CCER_CC4P ((uint16_t)0x2000) /!<Capture/Compare 4 output Polarity /
n0tform3	8:1c6281289d67	6276	#define TIM_CCER_CC4NP ((uint16_t)0x8000) /!<Capture/Compare 4 Complementary output Polarity /
n0tform3	8:1c6281289d67	6277
n0tform3	8:1c6281289d67	6278	/***************** Bit definition for TIM_CNT register ******************/
n0tform3	8:1c6281289d67	6279	#define TIM_CNT_CNT ((uint16_t)0xFFFF) /!<Counter Value /
n0tform3	8:1c6281289d67	6280
n0tform3	8:1c6281289d67	6281	/***************** Bit definition for TIM_PSC register ******************/
n0tform3	8:1c6281289d67	6282	#define TIM_PSC_PSC ((uint16_t)0xFFFF) /!<Prescaler Value /
n0tform3	8:1c6281289d67	6283
n0tform3	8:1c6281289d67	6284	/***************** Bit definition for TIM_ARR register ******************/
n0tform3	8:1c6281289d67	6285	#define TIM_ARR_ARR ((uint16_t)0xFFFF) /!<actual auto-reload Value /
n0tform3	8:1c6281289d67	6286
n0tform3	8:1c6281289d67	6287	/***************** Bit definition for TIM_RCR register ******************/
n0tform3	8:1c6281289d67	6288	#define TIM_RCR_REP ((uint8_t)0xFF) /!<Repetition Counter Value /
n0tform3	8:1c6281289d67	6289
n0tform3	8:1c6281289d67	6290	/***************** Bit definition for TIM_CCR1 register *****************/
n0tform3	8:1c6281289d67	6291	#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /!<Capture/Compare 1 Value /
n0tform3	8:1c6281289d67	6292
n0tform3	8:1c6281289d67	6293	/***************** Bit definition for TIM_CCR2 register *****************/
n0tform3	8:1c6281289d67	6294	#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /!<Capture/Compare 2 Value /
n0tform3	8:1c6281289d67	6295
n0tform3	8:1c6281289d67	6296	/***************** Bit definition for TIM_CCR3 register *****************/
n0tform3	8:1c6281289d67	6297	#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /!<Capture/Compare 3 Value /
n0tform3	8:1c6281289d67	6298
n0tform3	8:1c6281289d67	6299	/***************** Bit definition for TIM_CCR4 register *****************/
n0tform3	8:1c6281289d67	6300	#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /!<Capture/Compare 4 Value /
n0tform3	8:1c6281289d67	6301
n0tform3	8:1c6281289d67	6302	/***************** Bit definition for TIM_BDTR register *****************/
n0tform3	8:1c6281289d67	6303	#define TIM_BDTR_DTG ((uint16_t)0x00FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
n0tform3	8:1c6281289d67	6304	#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	6305	#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	6306	#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /!<Bit 2 /
n0tform3	8:1c6281289d67	6307	#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /!<Bit 3 /
n0tform3	8:1c6281289d67	6308	#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /!<Bit 4 /
n0tform3	8:1c6281289d67	6309	#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /!<Bit 5 /
n0tform3	8:1c6281289d67	6310	#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /!<Bit 6 /
n0tform3	8:1c6281289d67	6311	#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /!<Bit 7 /
n0tform3	8:1c6281289d67	6312
n0tform3	8:1c6281289d67	6313	#define TIM_BDTR_LOCK ((uint16_t)0x0300) /!<LOCK[1:0] bits (Lock Configuration) /
n0tform3	8:1c6281289d67	6314	#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /!<Bit 0 /
n0tform3	8:1c6281289d67	6315	#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /!<Bit 1 /
n0tform3	8:1c6281289d67	6316
n0tform3	8:1c6281289d67	6317	#define TIM_BDTR_OSSI ((uint16_t)0x0400) /!<Off-State Selection for Idle mode /
n0tform3	8:1c6281289d67	6318	#define TIM_BDTR_OSSR ((uint16_t)0x0800) /!<Off-State Selection for Run mode /
n0tform3	8:1c6281289d67	6319	#define TIM_BDTR_BKE ((uint16_t)0x1000) /!<Break enable /
n0tform3	8:1c6281289d67	6320	#define TIM_BDTR_BKP ((uint16_t)0x2000) /!<Break Polarity /
n0tform3	8:1c6281289d67	6321	#define TIM_BDTR_AOE ((uint16_t)0x4000) /!<Automatic Output enable /
n0tform3	8:1c6281289d67	6322	#define TIM_BDTR_MOE ((uint16_t)0x8000) /!<Main Output enable /
n0tform3	8:1c6281289d67	6323
n0tform3	8:1c6281289d67	6324	/***************** Bit definition for TIM_DCR register ******************/
n0tform3	8:1c6281289d67	6325	#define TIM_DCR_DBA ((uint16_t)0x001F) /!<DBA[4:0] bits (DMA Base Address) /
n0tform3	8:1c6281289d67	6326	#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	6327	#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	6328	#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /!<Bit 2 /
n0tform3	8:1c6281289d67	6329	#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /!<Bit 3 /
n0tform3	8:1c6281289d67	6330	#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /!<Bit 4 /
n0tform3	8:1c6281289d67	6331
n0tform3	8:1c6281289d67	6332	#define TIM_DCR_DBL ((uint16_t)0x1F00) /!<DBL[4:0] bits (DMA Burst Length) /
n0tform3	8:1c6281289d67	6333	#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /!<Bit 0 /
n0tform3	8:1c6281289d67	6334	#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /!<Bit 1 /
n0tform3	8:1c6281289d67	6335	#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /!<Bit 2 /
n0tform3	8:1c6281289d67	6336	#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /!<Bit 3 /
n0tform3	8:1c6281289d67	6337	#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /!<Bit 4 /
n0tform3	8:1c6281289d67	6338
n0tform3	8:1c6281289d67	6339	/***************** Bit definition for TIM_DMAR register *****************/
n0tform3	8:1c6281289d67	6340	#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /!<DMA register for burst accesses /
n0tform3	8:1c6281289d67	6341
n0tform3	8:1c6281289d67	6342	/***************** Bit definition for TIM_OR register *******************/
n0tform3	8:1c6281289d67	6343	#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) /
n0tform3	8:1c6281289d67	6344	#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /!<Bit 0 /
n0tform3	8:1c6281289d67	6345	#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /!<Bit 1 /
n0tform3	8:1c6281289d67	6346	#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) /
n0tform3	8:1c6281289d67	6347	#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /!<Bit 0 /
n0tform3	8:1c6281289d67	6348	#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /!<Bit 1 /
n0tform3	8:1c6281289d67	6349
n0tform3	8:1c6281289d67	6350
n0tform3	8:1c6281289d67	6351	/******************************************************************************/
n0tform3	8:1c6281289d67	6352	/* */
n0tform3	8:1c6281289d67	6353	/* Universal Synchronous Asynchronous Receiver Transmitter */
n0tform3	8:1c6281289d67	6354	/* */
n0tform3	8:1c6281289d67	6355	/******************************************************************************/
n0tform3	8:1c6281289d67	6356	/***************** Bit definition for USART_SR register *****************/
n0tform3	8:1c6281289d67	6357	#define USART_SR_PE ((uint16_t)0x0001) /!<Parity Error /
n0tform3	8:1c6281289d67	6358	#define USART_SR_FE ((uint16_t)0x0002) /!<Framing Error /
n0tform3	8:1c6281289d67	6359	#define USART_SR_NE ((uint16_t)0x0004) /!<Noise Error Flag /
n0tform3	8:1c6281289d67	6360	#define USART_SR_ORE ((uint16_t)0x0008) /!<OverRun Error /
n0tform3	8:1c6281289d67	6361	#define USART_SR_IDLE ((uint16_t)0x0010) /!<IDLE line detected /
n0tform3	8:1c6281289d67	6362	#define USART_SR_RXNE ((uint16_t)0x0020) /!<Read Data Register Not Empty /
n0tform3	8:1c6281289d67	6363	#define USART_SR_TC ((uint16_t)0x0040) /!<Transmission Complete /
n0tform3	8:1c6281289d67	6364	#define USART_SR_TXE ((uint16_t)0x0080) /!<Transmit Data Register Empty /
n0tform3	8:1c6281289d67	6365	#define USART_SR_LBD ((uint16_t)0x0100) /!<LIN Break Detection Flag /
n0tform3	8:1c6281289d67	6366	#define USART_SR_CTS ((uint16_t)0x0200) /!<CTS Flag /
n0tform3	8:1c6281289d67	6367
n0tform3	8:1c6281289d67	6368	/***************** Bit definition for USART_DR register *****************/
n0tform3	8:1c6281289d67	6369	#define USART_DR_DR ((uint16_t)0x01FF) /!<Data value /
n0tform3	8:1c6281289d67	6370
n0tform3	8:1c6281289d67	6371	/**************** Bit definition for USART_BRR register *****************/
n0tform3	8:1c6281289d67	6372	#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /!<Fraction of USARTDIV /
n0tform3	8:1c6281289d67	6373	#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /!<Mantissa of USARTDIV /
n0tform3	8:1c6281289d67	6374
n0tform3	8:1c6281289d67	6375	/**************** Bit definition for USART_CR1 register *****************/
n0tform3	8:1c6281289d67	6376	#define USART_CR1_SBK ((uint16_t)0x0001) /!<Send Break /
n0tform3	8:1c6281289d67	6377	#define USART_CR1_RWU ((uint16_t)0x0002) /!<Receiver wakeup /
n0tform3	8:1c6281289d67	6378	#define USART_CR1_RE ((uint16_t)0x0004) /!<Receiver Enable /
n0tform3	8:1c6281289d67	6379	#define USART_CR1_TE ((uint16_t)0x0008) /!<Transmitter Enable /
n0tform3	8:1c6281289d67	6380	#define USART_CR1_IDLEIE ((uint16_t)0x0010) /!<IDLE Interrupt Enable /
n0tform3	8:1c6281289d67	6381	#define USART_CR1_RXNEIE ((uint16_t)0x0020) /!<RXNE Interrupt Enable /
n0tform3	8:1c6281289d67	6382	#define USART_CR1_TCIE ((uint16_t)0x0040) /!<Transmission Complete Interrupt Enable /
n0tform3	8:1c6281289d67	6383	#define USART_CR1_TXEIE ((uint16_t)0x0080) /!<PE Interrupt Enable /
n0tform3	8:1c6281289d67	6384	#define USART_CR1_PEIE ((uint16_t)0x0100) /!<PE Interrupt Enable /
n0tform3	8:1c6281289d67	6385	#define USART_CR1_PS ((uint16_t)0x0200) /!<Parity Selection /
n0tform3	8:1c6281289d67	6386	#define USART_CR1_PCE ((uint16_t)0x0400) /!<Parity Control Enable /
n0tform3	8:1c6281289d67	6387	#define USART_CR1_WAKE ((uint16_t)0x0800) /!<Wakeup method /
n0tform3	8:1c6281289d67	6388	#define USART_CR1_M ((uint16_t)0x1000) /!<Word length /
n0tform3	8:1c6281289d67	6389	#define USART_CR1_UE ((uint16_t)0x2000) /!<USART Enable /
n0tform3	8:1c6281289d67	6390	#define USART_CR1_OVER8 ((uint16_t)0x8000) /!<USART Oversampling by 8 enable /
n0tform3	8:1c6281289d67	6391
n0tform3	8:1c6281289d67	6392	/**************** Bit definition for USART_CR2 register *****************/
n0tform3	8:1c6281289d67	6393	#define USART_CR2_ADD ((uint16_t)0x000F) /!<Address of the USART node /
n0tform3	8:1c6281289d67	6394	#define USART_CR2_LBDL ((uint16_t)0x0020) /!<LIN Break Detection Length /
n0tform3	8:1c6281289d67	6395	#define USART_CR2_LBDIE ((uint16_t)0x0040) /!<LIN Break Detection Interrupt Enable /
n0tform3	8:1c6281289d67	6396	#define USART_CR2_LBCL ((uint16_t)0x0100) /!<Last Bit Clock pulse /
n0tform3	8:1c6281289d67	6397	#define USART_CR2_CPHA ((uint16_t)0x0200) /!<Clock Phase /
n0tform3	8:1c6281289d67	6398	#define USART_CR2_CPOL ((uint16_t)0x0400) /!<Clock Polarity /
n0tform3	8:1c6281289d67	6399	#define USART_CR2_CLKEN ((uint16_t)0x0800) /!<Clock Enable /
n0tform3	8:1c6281289d67	6400
n0tform3	8:1c6281289d67	6401	#define USART_CR2_STOP ((uint16_t)0x3000) /!<STOP[1:0] bits (STOP bits) /
n0tform3	8:1c6281289d67	6402	#define USART_CR2_STOP_0 ((uint16_t)0x1000) /!<Bit 0 /
n0tform3	8:1c6281289d67	6403	#define USART_CR2_STOP_1 ((uint16_t)0x2000) /!<Bit 1 /
n0tform3	8:1c6281289d67	6404
n0tform3	8:1c6281289d67	6405	#define USART_CR2_LINEN ((uint16_t)0x4000) /!<LIN mode enable /
n0tform3	8:1c6281289d67	6406
n0tform3	8:1c6281289d67	6407	/**************** Bit definition for USART_CR3 register *****************/
n0tform3	8:1c6281289d67	6408	#define USART_CR3_EIE ((uint16_t)0x0001) /!<Error Interrupt Enable /
n0tform3	8:1c6281289d67	6409	#define USART_CR3_IREN ((uint16_t)0x0002) /!<IrDA mode Enable /
n0tform3	8:1c6281289d67	6410	#define USART_CR3_IRLP ((uint16_t)0x0004) /!<IrDA Low-Power /
n0tform3	8:1c6281289d67	6411	#define USART_CR3_HDSEL ((uint16_t)0x0008) /!<Half-Duplex Selection /
n0tform3	8:1c6281289d67	6412	#define USART_CR3_NACK ((uint16_t)0x0010) /!<Smartcard NACK enable /
n0tform3	8:1c6281289d67	6413	#define USART_CR3_SCEN ((uint16_t)0x0020) /!<Smartcard mode enable /
n0tform3	8:1c6281289d67	6414	#define USART_CR3_DMAR ((uint16_t)0x0040) /!<DMA Enable Receiver /
n0tform3	8:1c6281289d67	6415	#define USART_CR3_DMAT ((uint16_t)0x0080) /!<DMA Enable Transmitter /
n0tform3	8:1c6281289d67	6416	#define USART_CR3_RTSE ((uint16_t)0x0100) /!<RTS Enable /
n0tform3	8:1c6281289d67	6417	#define USART_CR3_CTSE ((uint16_t)0x0200) /!<CTS Enable /
n0tform3	8:1c6281289d67	6418	#define USART_CR3_CTSIE ((uint16_t)0x0400) /!<CTS Interrupt Enable /
n0tform3	8:1c6281289d67	6419	#define USART_CR3_ONEBIT ((uint16_t)0x0800) /!<USART One bit method enable /
n0tform3	8:1c6281289d67	6420
n0tform3	8:1c6281289d67	6421	/**************** Bit definition for USART_GTPR register ****************/
n0tform3	8:1c6281289d67	6422	#define USART_GTPR_PSC ((uint16_t)0x00FF) /!<PSC[7:0] bits (Prescaler value) /
n0tform3	8:1c6281289d67	6423	#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	6424	#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	6425	#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /!<Bit 2 /
n0tform3	8:1c6281289d67	6426	#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /!<Bit 3 /
n0tform3	8:1c6281289d67	6427	#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /!<Bit 4 /
n0tform3	8:1c6281289d67	6428	#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /!<Bit 5 /
n0tform3	8:1c6281289d67	6429	#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /!<Bit 6 /
n0tform3	8:1c6281289d67	6430	#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /!<Bit 7 /
n0tform3	8:1c6281289d67	6431
n0tform3	8:1c6281289d67	6432	#define USART_GTPR_GT ((uint16_t)0xFF00) /!<Guard time value /
n0tform3	8:1c6281289d67	6433
n0tform3	8:1c6281289d67	6434	/******************************************************************************/
n0tform3	8:1c6281289d67	6435	/* */
n0tform3	8:1c6281289d67	6436	/* Window WATCHDOG */
n0tform3	8:1c6281289d67	6437	/* */
n0tform3	8:1c6281289d67	6438	/******************************************************************************/
n0tform3	8:1c6281289d67	6439	/***************** Bit definition for WWDG_CR register ******************/
n0tform3	8:1c6281289d67	6440	#define WWDG_CR_T ((uint8_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
n0tform3	8:1c6281289d67	6441	#define WWDG_CR_T0 ((uint8_t)0x01) /!<Bit 0 /
n0tform3	8:1c6281289d67	6442	#define WWDG_CR_T1 ((uint8_t)0x02) /!<Bit 1 /
n0tform3	8:1c6281289d67	6443	#define WWDG_CR_T2 ((uint8_t)0x04) /!<Bit 2 /
n0tform3	8:1c6281289d67	6444	#define WWDG_CR_T3 ((uint8_t)0x08) /!<Bit 3 /
n0tform3	8:1c6281289d67	6445	#define WWDG_CR_T4 ((uint8_t)0x10) /!<Bit 4 /
n0tform3	8:1c6281289d67	6446	#define WWDG_CR_T5 ((uint8_t)0x20) /!<Bit 5 /
n0tform3	8:1c6281289d67	6447	#define WWDG_CR_T6 ((uint8_t)0x40) /!<Bit 6 /
n0tform3	8:1c6281289d67	6448
n0tform3	8:1c6281289d67	6449	#define WWDG_CR_WDGA ((uint8_t)0x80) /!<Activation bit /
n0tform3	8:1c6281289d67	6450
n0tform3	8:1c6281289d67	6451	/***************** Bit definition for WWDG_CFR register *****************/
n0tform3	8:1c6281289d67	6452	#define WWDG_CFR_W ((uint16_t)0x007F) /!<W[6:0] bits (7-bit window value) /
n0tform3	8:1c6281289d67	6453	#define WWDG_CFR_W0 ((uint16_t)0x0001) /!<Bit 0 /
n0tform3	8:1c6281289d67	6454	#define WWDG_CFR_W1 ((uint16_t)0x0002) /!<Bit 1 /
n0tform3	8:1c6281289d67	6455	#define WWDG_CFR_W2 ((uint16_t)0x0004) /!<Bit 2 /
n0tform3	8:1c6281289d67	6456	#define WWDG_CFR_W3 ((uint16_t)0x0008) /!<Bit 3 /
n0tform3	8:1c6281289d67	6457	#define WWDG_CFR_W4 ((uint16_t)0x0010) /!<Bit 4 /
n0tform3	8:1c6281289d67	6458	#define WWDG_CFR_W5 ((uint16_t)0x0020) /!<Bit 5 /
n0tform3	8:1c6281289d67	6459	#define WWDG_CFR_W6 ((uint16_t)0x0040) /!<Bit 6 /
n0tform3	8:1c6281289d67	6460
n0tform3	8:1c6281289d67	6461	#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
n0tform3	8:1c6281289d67	6462	#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /!<Bit 0 /
n0tform3	8:1c6281289d67	6463	#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /!<Bit 1 /
n0tform3	8:1c6281289d67	6464
n0tform3	8:1c6281289d67	6465	#define WWDG_CFR_EWI ((uint16_t)0x0200) /!<Early Wakeup Interrupt /
n0tform3	8:1c6281289d67	6466
n0tform3	8:1c6281289d67	6467	/***************** Bit definition for WWDG_SR register ******************/
n0tform3	8:1c6281289d67	6468	#define WWDG_SR_EWIF ((uint8_t)0x01) /!<Early Wakeup Interrupt Flag /
n0tform3	8:1c6281289d67	6469
n0tform3	8:1c6281289d67	6470
n0tform3	8:1c6281289d67	6471	/******************************************************************************/
n0tform3	8:1c6281289d67	6472	/* */
n0tform3	8:1c6281289d67	6473	/* DBG */
n0tform3	8:1c6281289d67	6474	/* */
n0tform3	8:1c6281289d67	6475	/******************************************************************************/
n0tform3	8:1c6281289d67	6476	/****************** Bit definition for DBGMCU_IDCODE register ***********/
n0tform3	8:1c6281289d67	6477	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
n0tform3	8:1c6281289d67	6478	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
n0tform3	8:1c6281289d67	6479
n0tform3	8:1c6281289d67	6480	/****************** Bit definition for DBGMCU_CR register ***************/
n0tform3	8:1c6281289d67	6481	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	6482	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	6483	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	6484	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	6485
n0tform3	8:1c6281289d67	6486	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
n0tform3	8:1c6281289d67	6487	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/!<Bit 0 /
n0tform3	8:1c6281289d67	6488	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/!<Bit 1 /
n0tform3	8:1c6281289d67	6489
n0tform3	8:1c6281289d67	6490	/****************** Bit definition for DBGMCU_APB1_FZ register **********/
n0tform3	8:1c6281289d67	6491	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	6492	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	6493	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
n0tform3	8:1c6281289d67	6494	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
n0tform3	8:1c6281289d67	6495	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
n0tform3	8:1c6281289d67	6496	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
n0tform3	8:1c6281289d67	6497	#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
n0tform3	8:1c6281289d67	6498	#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
n0tform3	8:1c6281289d67	6499	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
n0tform3	8:1c6281289d67	6500	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
n0tform3	8:1c6281289d67	6501	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
n0tform3	8:1c6281289d67	6502	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
n0tform3	8:1c6281289d67	6503	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
n0tform3	8:1c6281289d67	6504	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
n0tform3	8:1c6281289d67	6505	#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
n0tform3	8:1c6281289d67	6506	#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
n0tform3	8:1c6281289d67	6507	#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
n0tform3	8:1c6281289d67	6508	/* Old IWDGSTOP bit definition, maintained for legacy purpose */
n0tform3	8:1c6281289d67	6509	#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
n0tform3	8:1c6281289d67	6510
n0tform3	8:1c6281289d67	6511	/****************** Bit definition for DBGMCU_APB2_FZ register **********/
n0tform3	8:1c6281289d67	6512	#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
n0tform3	8:1c6281289d67	6513	#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
n0tform3	8:1c6281289d67	6514	#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
n0tform3	8:1c6281289d67	6515	#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
n0tform3	8:1c6281289d67	6516	#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
n0tform3	8:1c6281289d67	6517
n0tform3	8:1c6281289d67	6518	/******************************************************************************/
n0tform3	8:1c6281289d67	6519	/* */
n0tform3	8:1c6281289d67	6520	/* Ethernet MAC Registers bits definitions */
n0tform3	8:1c6281289d67	6521	/* */
n0tform3	8:1c6281289d67	6522	/******************************************************************************/
n0tform3	8:1c6281289d67	6523	/* Bit definition for Ethernet MAC Control Register register */
n0tform3	8:1c6281289d67	6524	#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
n0tform3	8:1c6281289d67	6525	#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
n0tform3	8:1c6281289d67	6526	#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
n0tform3	8:1c6281289d67	6527	#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
n0tform3	8:1c6281289d67	6528	#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
n0tform3	8:1c6281289d67	6529	#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
n0tform3	8:1c6281289d67	6530	#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
n0tform3	8:1c6281289d67	6531	#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
n0tform3	8:1c6281289d67	6532	#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
n0tform3	8:1c6281289d67	6533	#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
n0tform3	8:1c6281289d67	6534	#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
n0tform3	8:1c6281289d67	6535	#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
n0tform3	8:1c6281289d67	6536	#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
n0tform3	8:1c6281289d67	6537	#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
n0tform3	8:1c6281289d67	6538	#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
n0tform3	8:1c6281289d67	6539	#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
n0tform3	8:1c6281289d67	6540	#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
n0tform3	8:1c6281289d67	6541	#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
n0tform3	8:1c6281289d67	6542	#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
n0tform3	8:1c6281289d67	6543	#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
n0tform3	8:1c6281289d67	6544	a transmission attempt during retries after a collision: 0 =< r <2^k */
n0tform3	8:1c6281289d67	6545	#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
n0tform3	8:1c6281289d67	6546	#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
n0tform3	8:1c6281289d67	6547	#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
n0tform3	8:1c6281289d67	6548	#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
n0tform3	8:1c6281289d67	6549	#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
n0tform3	8:1c6281289d67	6550	#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
n0tform3	8:1c6281289d67	6551	#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
n0tform3	8:1c6281289d67	6552
n0tform3	8:1c6281289d67	6553	/* Bit definition for Ethernet MAC Frame Filter Register */
n0tform3	8:1c6281289d67	6554	#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
n0tform3	8:1c6281289d67	6555	#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
n0tform3	8:1c6281289d67	6556	#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
n0tform3	8:1c6281289d67	6557	#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
n0tform3	8:1c6281289d67	6558	#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
n0tform3	8:1c6281289d67	6559	#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
n0tform3	8:1c6281289d67	6560	#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
n0tform3	8:1c6281289d67	6561	#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
n0tform3	8:1c6281289d67	6562	#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
n0tform3	8:1c6281289d67	6563	#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
n0tform3	8:1c6281289d67	6564	#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
n0tform3	8:1c6281289d67	6565	#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
n0tform3	8:1c6281289d67	6566	#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
n0tform3	8:1c6281289d67	6567	#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
n0tform3	8:1c6281289d67	6568
n0tform3	8:1c6281289d67	6569	/* Bit definition for Ethernet MAC Hash Table High Register */
n0tform3	8:1c6281289d67	6570	#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
n0tform3	8:1c6281289d67	6571
n0tform3	8:1c6281289d67	6572	/* Bit definition for Ethernet MAC Hash Table Low Register */
n0tform3	8:1c6281289d67	6573	#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
n0tform3	8:1c6281289d67	6574
n0tform3	8:1c6281289d67	6575	/* Bit definition for Ethernet MAC MII Address Register */
n0tform3	8:1c6281289d67	6576	#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
n0tform3	8:1c6281289d67	6577	#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
n0tform3	8:1c6281289d67	6578	#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
n0tform3	8:1c6281289d67	6579	#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
n0tform3	8:1c6281289d67	6580	#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
n0tform3	8:1c6281289d67	6581	#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
n0tform3	8:1c6281289d67	6582	#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
n0tform3	8:1c6281289d67	6583	#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
n0tform3	8:1c6281289d67	6584	#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
n0tform3	8:1c6281289d67	6585	#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
n0tform3	8:1c6281289d67	6586
n0tform3	8:1c6281289d67	6587	/* Bit definition for Ethernet MAC MII Data Register */
n0tform3	8:1c6281289d67	6588	#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
n0tform3	8:1c6281289d67	6589
n0tform3	8:1c6281289d67	6590	/* Bit definition for Ethernet MAC Flow Control Register */
n0tform3	8:1c6281289d67	6591	#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
n0tform3	8:1c6281289d67	6592	#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
n0tform3	8:1c6281289d67	6593	#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
n0tform3	8:1c6281289d67	6594	#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
n0tform3	8:1c6281289d67	6595	#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
n0tform3	8:1c6281289d67	6596	#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
n0tform3	8:1c6281289d67	6597	#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
n0tform3	8:1c6281289d67	6598	#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
n0tform3	8:1c6281289d67	6599	#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
n0tform3	8:1c6281289d67	6600	#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
n0tform3	8:1c6281289d67	6601	#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
n0tform3	8:1c6281289d67	6602
n0tform3	8:1c6281289d67	6603	/* Bit definition for Ethernet MAC VLAN Tag Register */
n0tform3	8:1c6281289d67	6604	#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
n0tform3	8:1c6281289d67	6605	#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
n0tform3	8:1c6281289d67	6606
n0tform3	8:1c6281289d67	6607	/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
n0tform3	8:1c6281289d67	6608	#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
n0tform3	8:1c6281289d67	6609	/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
n0tform3	8:1c6281289d67	6610	Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
n0tform3	8:1c6281289d67	6611	/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
n0tform3	8:1c6281289d67	6612	Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
n0tform3	8:1c6281289d67	6613	Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
n0tform3	8:1c6281289d67	6614	Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
n0tform3	8:1c6281289d67	6615	Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
n0tform3	8:1c6281289d67	6616	RSVD - Filter1 Command - RSVD - Filter0 Command
n0tform3	8:1c6281289d67	6617	Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
n0tform3	8:1c6281289d67	6618	Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
n0tform3	8:1c6281289d67	6619	Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
n0tform3	8:1c6281289d67	6620
n0tform3	8:1c6281289d67	6621	/* Bit definition for Ethernet MAC PMT Control and Status Register */
n0tform3	8:1c6281289d67	6622	#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
n0tform3	8:1c6281289d67	6623	#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
n0tform3	8:1c6281289d67	6624	#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
n0tform3	8:1c6281289d67	6625	#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
n0tform3	8:1c6281289d67	6626	#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
n0tform3	8:1c6281289d67	6627	#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
n0tform3	8:1c6281289d67	6628	#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
n0tform3	8:1c6281289d67	6629
n0tform3	8:1c6281289d67	6630	/* Bit definition for Ethernet MAC Status Register */
n0tform3	8:1c6281289d67	6631	#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
n0tform3	8:1c6281289d67	6632	#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
n0tform3	8:1c6281289d67	6633	#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
n0tform3	8:1c6281289d67	6634	#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
n0tform3	8:1c6281289d67	6635	#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
n0tform3	8:1c6281289d67	6636
n0tform3	8:1c6281289d67	6637	/* Bit definition for Ethernet MAC Interrupt Mask Register */
n0tform3	8:1c6281289d67	6638	#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
n0tform3	8:1c6281289d67	6639	#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
n0tform3	8:1c6281289d67	6640
n0tform3	8:1c6281289d67	6641	/* Bit definition for Ethernet MAC Address0 High Register */
n0tform3	8:1c6281289d67	6642	#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
n0tform3	8:1c6281289d67	6643
n0tform3	8:1c6281289d67	6644	/* Bit definition for Ethernet MAC Address0 Low Register */
n0tform3	8:1c6281289d67	6645	#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
n0tform3	8:1c6281289d67	6646
n0tform3	8:1c6281289d67	6647	/* Bit definition for Ethernet MAC Address1 High Register */
n0tform3	8:1c6281289d67	6648	#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
n0tform3	8:1c6281289d67	6649	#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
n0tform3	8:1c6281289d67	6650	#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
n0tform3	8:1c6281289d67	6651	#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
n0tform3	8:1c6281289d67	6652	#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
n0tform3	8:1c6281289d67	6653	#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
n0tform3	8:1c6281289d67	6654	#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
n0tform3	8:1c6281289d67	6655	#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
n0tform3	8:1c6281289d67	6656	#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
n0tform3	8:1c6281289d67	6657	#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
n0tform3	8:1c6281289d67	6658
n0tform3	8:1c6281289d67	6659	/* Bit definition for Ethernet MAC Address1 Low Register */
n0tform3	8:1c6281289d67	6660	#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
n0tform3	8:1c6281289d67	6661
n0tform3	8:1c6281289d67	6662	/* Bit definition for Ethernet MAC Address2 High Register */
n0tform3	8:1c6281289d67	6663	#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
n0tform3	8:1c6281289d67	6664	#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
n0tform3	8:1c6281289d67	6665	#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
n0tform3	8:1c6281289d67	6666	#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
n0tform3	8:1c6281289d67	6667	#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
n0tform3	8:1c6281289d67	6668	#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
n0tform3	8:1c6281289d67	6669	#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
n0tform3	8:1c6281289d67	6670	#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
n0tform3	8:1c6281289d67	6671	#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
n0tform3	8:1c6281289d67	6672	#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
n0tform3	8:1c6281289d67	6673
n0tform3	8:1c6281289d67	6674	/* Bit definition for Ethernet MAC Address2 Low Register */
n0tform3	8:1c6281289d67	6675	#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
n0tform3	8:1c6281289d67	6676
n0tform3	8:1c6281289d67	6677	/* Bit definition for Ethernet MAC Address3 High Register */
n0tform3	8:1c6281289d67	6678	#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
n0tform3	8:1c6281289d67	6679	#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
n0tform3	8:1c6281289d67	6680	#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
n0tform3	8:1c6281289d67	6681	#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
n0tform3	8:1c6281289d67	6682	#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
n0tform3	8:1c6281289d67	6683	#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
n0tform3	8:1c6281289d67	6684	#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
n0tform3	8:1c6281289d67	6685	#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
n0tform3	8:1c6281289d67	6686	#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
n0tform3	8:1c6281289d67	6687	#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
n0tform3	8:1c6281289d67	6688
n0tform3	8:1c6281289d67	6689	/* Bit definition for Ethernet MAC Address3 Low Register */
n0tform3	8:1c6281289d67	6690	#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
n0tform3	8:1c6281289d67	6691
n0tform3	8:1c6281289d67	6692	/******************************************************************************/
n0tform3	8:1c6281289d67	6693	/* Ethernet MMC Registers bits definition */
n0tform3	8:1c6281289d67	6694	/******************************************************************************/
n0tform3	8:1c6281289d67	6695
n0tform3	8:1c6281289d67	6696	/* Bit definition for Ethernet MMC Contol Register */
n0tform3	8:1c6281289d67	6697	#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
n0tform3	8:1c6281289d67	6698	#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
n0tform3	8:1c6281289d67	6699	#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
n0tform3	8:1c6281289d67	6700	#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
n0tform3	8:1c6281289d67	6701	#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
n0tform3	8:1c6281289d67	6702	#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
n0tform3	8:1c6281289d67	6703
n0tform3	8:1c6281289d67	6704	/* Bit definition for Ethernet MMC Receive Interrupt Register */
n0tform3	8:1c6281289d67	6705	#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6706	#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6707	#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6708
n0tform3	8:1c6281289d67	6709	/* Bit definition for Ethernet MMC Transmit Interrupt Register */
n0tform3	8:1c6281289d67	6710	#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6711	#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6712	#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6713
n0tform3	8:1c6281289d67	6714	/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
n0tform3	8:1c6281289d67	6715	#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6716	#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6717	#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6718
n0tform3	8:1c6281289d67	6719	/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
n0tform3	8:1c6281289d67	6720	#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6721	#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6722	#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
n0tform3	8:1c6281289d67	6723
n0tform3	8:1c6281289d67	6724	/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
n0tform3	8:1c6281289d67	6725	#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
n0tform3	8:1c6281289d67	6726
n0tform3	8:1c6281289d67	6727	/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
n0tform3	8:1c6281289d67	6728	#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
n0tform3	8:1c6281289d67	6729
n0tform3	8:1c6281289d67	6730	/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
n0tform3	8:1c6281289d67	6731	#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
n0tform3	8:1c6281289d67	6732
n0tform3	8:1c6281289d67	6733	/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
n0tform3	8:1c6281289d67	6734	#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
n0tform3	8:1c6281289d67	6735
n0tform3	8:1c6281289d67	6736	/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
n0tform3	8:1c6281289d67	6737	#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
n0tform3	8:1c6281289d67	6738
n0tform3	8:1c6281289d67	6739	/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
n0tform3	8:1c6281289d67	6740	#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
n0tform3	8:1c6281289d67	6741
n0tform3	8:1c6281289d67	6742	/******************************************************************************/
n0tform3	8:1c6281289d67	6743	/* Ethernet PTP Registers bits definition */
n0tform3	8:1c6281289d67	6744	/******************************************************************************/
n0tform3	8:1c6281289d67	6745
n0tform3	8:1c6281289d67	6746	/* Bit definition for Ethernet PTP Time Stamp Contol Register */
n0tform3	8:1c6281289d67	6747	#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
n0tform3	8:1c6281289d67	6748	#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
n0tform3	8:1c6281289d67	6749	#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
n0tform3	8:1c6281289d67	6750	#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
n0tform3	8:1c6281289d67	6751	#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
n0tform3	8:1c6281289d67	6752	#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
n0tform3	8:1c6281289d67	6753	#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
n0tform3	8:1c6281289d67	6754	#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
n0tform3	8:1c6281289d67	6755	#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
n0tform3	8:1c6281289d67	6756
n0tform3	8:1c6281289d67	6757	#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
n0tform3	8:1c6281289d67	6758	#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
n0tform3	8:1c6281289d67	6759	#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
n0tform3	8:1c6281289d67	6760	#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
n0tform3	8:1c6281289d67	6761	#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
n0tform3	8:1c6281289d67	6762	#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
n0tform3	8:1c6281289d67	6763
n0tform3	8:1c6281289d67	6764	/* Bit definition for Ethernet PTP Sub-Second Increment Register */
n0tform3	8:1c6281289d67	6765	#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
n0tform3	8:1c6281289d67	6766
n0tform3	8:1c6281289d67	6767	/* Bit definition for Ethernet PTP Time Stamp High Register */
n0tform3	8:1c6281289d67	6768	#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
n0tform3	8:1c6281289d67	6769
n0tform3	8:1c6281289d67	6770	/* Bit definition for Ethernet PTP Time Stamp Low Register */
n0tform3	8:1c6281289d67	6771	#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
n0tform3	8:1c6281289d67	6772	#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
n0tform3	8:1c6281289d67	6773
n0tform3	8:1c6281289d67	6774	/* Bit definition for Ethernet PTP Time Stamp High Update Register */
n0tform3	8:1c6281289d67	6775	#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
n0tform3	8:1c6281289d67	6776
n0tform3	8:1c6281289d67	6777	/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
n0tform3	8:1c6281289d67	6778	#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
n0tform3	8:1c6281289d67	6779	#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
n0tform3	8:1c6281289d67	6780
n0tform3	8:1c6281289d67	6781	/* Bit definition for Ethernet PTP Time Stamp Addend Register */
n0tform3	8:1c6281289d67	6782	#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
n0tform3	8:1c6281289d67	6783
n0tform3	8:1c6281289d67	6784	/* Bit definition for Ethernet PTP Target Time High Register */
n0tform3	8:1c6281289d67	6785	#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
n0tform3	8:1c6281289d67	6786
n0tform3	8:1c6281289d67	6787	/* Bit definition for Ethernet PTP Target Time Low Register */
n0tform3	8:1c6281289d67	6788	#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
n0tform3	8:1c6281289d67	6789
n0tform3	8:1c6281289d67	6790	/* Bit definition for Ethernet PTP Time Stamp Status Register */
n0tform3	8:1c6281289d67	6791	#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
n0tform3	8:1c6281289d67	6792	#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
n0tform3	8:1c6281289d67	6793
n0tform3	8:1c6281289d67	6794	/******************************************************************************/
n0tform3	8:1c6281289d67	6795	/* Ethernet DMA Registers bits definition */
n0tform3	8:1c6281289d67	6796	/******************************************************************************/
n0tform3	8:1c6281289d67	6797
n0tform3	8:1c6281289d67	6798	/* Bit definition for Ethernet DMA Bus Mode Register */
n0tform3	8:1c6281289d67	6799	#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
n0tform3	8:1c6281289d67	6800	#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
n0tform3	8:1c6281289d67	6801	#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
n0tform3	8:1c6281289d67	6802	#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
n0tform3	8:1c6281289d67	6803	#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
n0tform3	8:1c6281289d67	6804	#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
n0tform3	8:1c6281289d67	6805	#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
n0tform3	8:1c6281289d67	6806	#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
n0tform3	8:1c6281289d67	6807	#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
n0tform3	8:1c6281289d67	6808	#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
n0tform3	8:1c6281289d67	6809	#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
n0tform3	8:1c6281289d67	6810	#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
n0tform3	8:1c6281289d67	6811	#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
n0tform3	8:1c6281289d67	6812	#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
n0tform3	8:1c6281289d67	6813	#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
n0tform3	8:1c6281289d67	6814	#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
n0tform3	8:1c6281289d67	6815	#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
n0tform3	8:1c6281289d67	6816	#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
n0tform3	8:1c6281289d67	6817	#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
n0tform3	8:1c6281289d67	6818	#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
n0tform3	8:1c6281289d67	6819	#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
n0tform3	8:1c6281289d67	6820	#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
n0tform3	8:1c6281289d67	6821	#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
n0tform3	8:1c6281289d67	6822	#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
n0tform3	8:1c6281289d67	6823	#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
n0tform3	8:1c6281289d67	6824	#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
n0tform3	8:1c6281289d67	6825	#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
n0tform3	8:1c6281289d67	6826	#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
n0tform3	8:1c6281289d67	6827	#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
n0tform3	8:1c6281289d67	6828	#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
n0tform3	8:1c6281289d67	6829	#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
n0tform3	8:1c6281289d67	6830	#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
n0tform3	8:1c6281289d67	6831	#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
n0tform3	8:1c6281289d67	6832	#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
n0tform3	8:1c6281289d67	6833	#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
n0tform3	8:1c6281289d67	6834	#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
n0tform3	8:1c6281289d67	6835	#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
n0tform3	8:1c6281289d67	6836	#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
n0tform3	8:1c6281289d67	6837	#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
n0tform3	8:1c6281289d67	6838
n0tform3	8:1c6281289d67	6839	/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
n0tform3	8:1c6281289d67	6840	#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
n0tform3	8:1c6281289d67	6841
n0tform3	8:1c6281289d67	6842	/* Bit definition for Ethernet DMA Receive Poll Demand Register */
n0tform3	8:1c6281289d67	6843	#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
n0tform3	8:1c6281289d67	6844
n0tform3	8:1c6281289d67	6845	/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
n0tform3	8:1c6281289d67	6846	#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
n0tform3	8:1c6281289d67	6847
n0tform3	8:1c6281289d67	6848	/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
n0tform3	8:1c6281289d67	6849	#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
n0tform3	8:1c6281289d67	6850
n0tform3	8:1c6281289d67	6851	/* Bit definition for Ethernet DMA Status Register */
n0tform3	8:1c6281289d67	6852	#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
n0tform3	8:1c6281289d67	6853	#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
n0tform3	8:1c6281289d67	6854	#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
n0tform3	8:1c6281289d67	6855	#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
n0tform3	8:1c6281289d67	6856	/* combination with EBS[2:0] for GetFlagStatus function */
n0tform3	8:1c6281289d67	6857	#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
n0tform3	8:1c6281289d67	6858	#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
n0tform3	8:1c6281289d67	6859	#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
n0tform3	8:1c6281289d67	6860	#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
n0tform3	8:1c6281289d67	6861	#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
n0tform3	8:1c6281289d67	6862	#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
n0tform3	8:1c6281289d67	6863	#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
n0tform3	8:1c6281289d67	6864	#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
n0tform3	8:1c6281289d67	6865	#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
n0tform3	8:1c6281289d67	6866	#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
n0tform3	8:1c6281289d67	6867	#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
n0tform3	8:1c6281289d67	6868	#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
n0tform3	8:1c6281289d67	6869	#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
n0tform3	8:1c6281289d67	6870	#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
n0tform3	8:1c6281289d67	6871	#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
n0tform3	8:1c6281289d67	6872	#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
n0tform3	8:1c6281289d67	6873	#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
n0tform3	8:1c6281289d67	6874	#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
n0tform3	8:1c6281289d67	6875	#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
n0tform3	8:1c6281289d67	6876	#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
n0tform3	8:1c6281289d67	6877	#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
n0tform3	8:1c6281289d67	6878	#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
n0tform3	8:1c6281289d67	6879	#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
n0tform3	8:1c6281289d67	6880	#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
n0tform3	8:1c6281289d67	6881	#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
n0tform3	8:1c6281289d67	6882	#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
n0tform3	8:1c6281289d67	6883	#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
n0tform3	8:1c6281289d67	6884	#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
n0tform3	8:1c6281289d67	6885	#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
n0tform3	8:1c6281289d67	6886	#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
n0tform3	8:1c6281289d67	6887	#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
n0tform3	8:1c6281289d67	6888	#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
n0tform3	8:1c6281289d67	6889
n0tform3	8:1c6281289d67	6890	/* Bit definition for Ethernet DMA Operation Mode Register */
n0tform3	8:1c6281289d67	6891	#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
n0tform3	8:1c6281289d67	6892	#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
n0tform3	8:1c6281289d67	6893	#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
n0tform3	8:1c6281289d67	6894	#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
n0tform3	8:1c6281289d67	6895	#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
n0tform3	8:1c6281289d67	6896	#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
n0tform3	8:1c6281289d67	6897	#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
n0tform3	8:1c6281289d67	6898	#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
n0tform3	8:1c6281289d67	6899	#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
n0tform3	8:1c6281289d67	6900	#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
n0tform3	8:1c6281289d67	6901	#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
n0tform3	8:1c6281289d67	6902	#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
n0tform3	8:1c6281289d67	6903	#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
n0tform3	8:1c6281289d67	6904	#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
n0tform3	8:1c6281289d67	6905	#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
n0tform3	8:1c6281289d67	6906	#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
n0tform3	8:1c6281289d67	6907	#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
n0tform3	8:1c6281289d67	6908	#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
n0tform3	8:1c6281289d67	6909	#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
n0tform3	8:1c6281289d67	6910	#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
n0tform3	8:1c6281289d67	6911	#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
n0tform3	8:1c6281289d67	6912	#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
n0tform3	8:1c6281289d67	6913	#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
n0tform3	8:1c6281289d67	6914	#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
n0tform3	8:1c6281289d67	6915
n0tform3	8:1c6281289d67	6916	/* Bit definition for Ethernet DMA Interrupt Enable Register */
n0tform3	8:1c6281289d67	6917	#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
n0tform3	8:1c6281289d67	6918	#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
n0tform3	8:1c6281289d67	6919	#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
n0tform3	8:1c6281289d67	6920	#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
n0tform3	8:1c6281289d67	6921	#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
n0tform3	8:1c6281289d67	6922	#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
n0tform3	8:1c6281289d67	6923	#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
n0tform3	8:1c6281289d67	6924	#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
n0tform3	8:1c6281289d67	6925	#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
n0tform3	8:1c6281289d67	6926	#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
n0tform3	8:1c6281289d67	6927	#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
n0tform3	8:1c6281289d67	6928	#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
n0tform3	8:1c6281289d67	6929	#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
n0tform3	8:1c6281289d67	6930	#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
n0tform3	8:1c6281289d67	6931	#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
n0tform3	8:1c6281289d67	6932
n0tform3	8:1c6281289d67	6933	/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
n0tform3	8:1c6281289d67	6934	#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
n0tform3	8:1c6281289d67	6935	#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
n0tform3	8:1c6281289d67	6936	#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
n0tform3	8:1c6281289d67	6937	#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
n0tform3	8:1c6281289d67	6938
n0tform3	8:1c6281289d67	6939	/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
n0tform3	8:1c6281289d67	6940	#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
n0tform3	8:1c6281289d67	6941
n0tform3	8:1c6281289d67	6942	/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
n0tform3	8:1c6281289d67	6943	#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
n0tform3	8:1c6281289d67	6944
n0tform3	8:1c6281289d67	6945	/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
n0tform3	8:1c6281289d67	6946	#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
n0tform3	8:1c6281289d67	6947
n0tform3	8:1c6281289d67	6948	/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
n0tform3	8:1c6281289d67	6949	#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
n0tform3	8:1c6281289d67	6950
n0tform3	8:1c6281289d67	6951	/**
n0tform3	8:1c6281289d67	6952	* @}
n0tform3	8:1c6281289d67	6953	*/
n0tform3	8:1c6281289d67	6954
n0tform3	8:1c6281289d67	6955	/**
n0tform3	8:1c6281289d67	6956	* @}
n0tform3	8:1c6281289d67	6957	*/
n0tform3	8:1c6281289d67	6958
n0tform3	8:1c6281289d67	6959	#ifdef USE_STDPERIPH_DRIVER
n0tform3	8:1c6281289d67	6960	#include "stm32f4xx_conf.h"
n0tform3	8:1c6281289d67	6961	#endif /* USE_STDPERIPH_DRIVER */
n0tform3	8:1c6281289d67	6962
n0tform3	8:1c6281289d67	6963	/** @addtogroup Exported_macro
n0tform3	8:1c6281289d67	6964	* @{
n0tform3	8:1c6281289d67	6965	*/
n0tform3	8:1c6281289d67	6966
n0tform3	8:1c6281289d67	6967	#define SET_BIT(REG, BIT) ((REG) \|= (BIT))
n0tform3	8:1c6281289d67	6968
n0tform3	8:1c6281289d67	6969	#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
n0tform3	8:1c6281289d67	6970
n0tform3	8:1c6281289d67	6971	#define READ_BIT(REG, BIT) ((REG) & (BIT))
n0tform3	8:1c6281289d67	6972
n0tform3	8:1c6281289d67	6973	#define CLEAR_REG(REG) ((REG) = (0x0))
n0tform3	8:1c6281289d67	6974
n0tform3	8:1c6281289d67	6975	#define WRITE_REG(REG, VAL) ((REG) = (VAL))
n0tform3	8:1c6281289d67	6976
n0tform3	8:1c6281289d67	6977	#define READ_REG(REG) ((REG))
n0tform3	8:1c6281289d67	6978
n0tform3	8:1c6281289d67	6979	#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) \| (SETMASK)))
n0tform3	8:1c6281289d67	6980
n0tform3	8:1c6281289d67	6981	/**
n0tform3	8:1c6281289d67	6982	* @}
n0tform3	8:1c6281289d67	6983	*/
n0tform3	8:1c6281289d67	6984
n0tform3	8:1c6281289d67	6985	#ifdef __cplusplus
n0tform3	8:1c6281289d67	6986	}
n0tform3	8:1c6281289d67	6987	#endif /* __cplusplus */
n0tform3	8:1c6281289d67	6988
n0tform3	8:1c6281289d67	6989	#endif /* __STM32F4xx_H */
n0tform3	8:1c6281289d67	6990
n0tform3	8:1c6281289d67	6991	/**
n0tform3	8:1c6281289d67	6992	* @}
n0tform3	8:1c6281289d67	6993	*/
n0tform3	8:1c6281289d67	6994
n0tform3	8:1c6281289d67	6995	/**
n0tform3	8:1c6281289d67	6996	* @}
n0tform3	8:1c6281289d67	6997	*/
n0tform3	8:1c6281289d67	6998
n0tform3	8:1c6281289d67	6999	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/
n0tform3	8:1c6281289d67	7000

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	15 Nov 2015
Imports:	67
Forks:	0
Commits:	9
Dependents:	0
Dependencies:	4
Followers:	1

stm32f4xx.h@8:1c6281289d67, 2015-11-15 (annotated)

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