mattia griotti
Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial
Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed
Fork of
HelloWorld_IKS01A1
by 
ST
stm32f4xx_usart.h@8:1c6281289d67, 2015-11-15 (annotated)
- Committer:
- n0tform3
- Date:
- Sun Nov 15 09:00:40 2015 +0000
- Revision:
- 8:1c6281289d67
test with led
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| n0tform3 | 8:1c6281289d67 | 1 | /** |
| n0tform3 | 8:1c6281289d67 | 2 | ****************************************************************************** |
| n0tform3 | 8:1c6281289d67 | 3 | * @file stm32f4xx_usart.h |
| n0tform3 | 8:1c6281289d67 | 4 | * @author MCD Application Team |
| n0tform3 | 8:1c6281289d67 | 5 | * @version V1.0.0 |
| n0tform3 | 8:1c6281289d67 | 6 | * @date 30-September-2011 |
| n0tform3 | 8:1c6281289d67 | 7 | * @brief This file contains all the functions prototypes for the USART |
| n0tform3 | 8:1c6281289d67 | 8 | * firmware library. |
| n0tform3 | 8:1c6281289d67 | 9 | ****************************************************************************** |
| n0tform3 | 8:1c6281289d67 | 10 | * @attention |
| n0tform3 | 8:1c6281289d67 | 11 | * |
| n0tform3 | 8:1c6281289d67 | 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
| n0tform3 | 8:1c6281289d67 | 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
| n0tform3 | 8:1c6281289d67 | 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
| n0tform3 | 8:1c6281289d67 | 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
| n0tform3 | 8:1c6281289d67 | 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
| n0tform3 | 8:1c6281289d67 | 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
| n0tform3 | 8:1c6281289d67 | 18 | * |
| n0tform3 | 8:1c6281289d67 | 19 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
| n0tform3 | 8:1c6281289d67 | 20 | ****************************************************************************** |
| n0tform3 | 8:1c6281289d67 | 21 | */ |
| n0tform3 | 8:1c6281289d67 | 22 | |
| n0tform3 | 8:1c6281289d67 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 24 | #ifndef __STM32F4xx_USART_H |
| n0tform3 | 8:1c6281289d67 | 25 | #define __STM32F4xx_USART_H |
| n0tform3 | 8:1c6281289d67 | 26 | |
| n0tform3 | 8:1c6281289d67 | 27 | #ifdef __cplusplus |
| n0tform3 | 8:1c6281289d67 | 28 | extern "C" { |
| n0tform3 | 8:1c6281289d67 | 29 | #endif |
| n0tform3 | 8:1c6281289d67 | 30 | |
| n0tform3 | 8:1c6281289d67 | 31 | /* Includes ------------------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 32 | #include "stm32f4xx.h" |
| n0tform3 | 8:1c6281289d67 | 33 | |
| n0tform3 | 8:1c6281289d67 | 34 | /** @addtogroup STM32F4xx_StdPeriph_Driver |
| n0tform3 | 8:1c6281289d67 | 35 | * @{ |
| n0tform3 | 8:1c6281289d67 | 36 | */ |
| n0tform3 | 8:1c6281289d67 | 37 | |
| n0tform3 | 8:1c6281289d67 | 38 | /** @addtogroup USART |
| n0tform3 | 8:1c6281289d67 | 39 | * @{ |
| n0tform3 | 8:1c6281289d67 | 40 | */ |
| n0tform3 | 8:1c6281289d67 | 41 | |
| n0tform3 | 8:1c6281289d67 | 42 | /* Exported types ------------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 43 | |
| n0tform3 | 8:1c6281289d67 | 44 | /** |
| n0tform3 | 8:1c6281289d67 | 45 | * @brief USART Init Structure definition |
| n0tform3 | 8:1c6281289d67 | 46 | */ |
| n0tform3 | 8:1c6281289d67 | 47 | |
| n0tform3 | 8:1c6281289d67 | 48 | typedef struct |
| n0tform3 | 8:1c6281289d67 | 49 | { |
| n0tform3 | 8:1c6281289d67 | 50 | uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. |
| n0tform3 | 8:1c6281289d67 | 51 | The baud rate is computed using the following formula: |
| n0tform3 | 8:1c6281289d67 | 52 | - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) |
| n0tform3 | 8:1c6281289d67 | 53 | - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 |
| n0tform3 | 8:1c6281289d67 | 54 | Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ |
| n0tform3 | 8:1c6281289d67 | 55 | |
| n0tform3 | 8:1c6281289d67 | 56 | uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. |
| n0tform3 | 8:1c6281289d67 | 57 | This parameter can be a value of @ref USART_Word_Length */ |
| n0tform3 | 8:1c6281289d67 | 58 | |
| n0tform3 | 8:1c6281289d67 | 59 | uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. |
| n0tform3 | 8:1c6281289d67 | 60 | This parameter can be a value of @ref USART_Stop_Bits */ |
| n0tform3 | 8:1c6281289d67 | 61 | |
| n0tform3 | 8:1c6281289d67 | 62 | uint16_t USART_Parity; /*!< Specifies the parity mode. |
| n0tform3 | 8:1c6281289d67 | 63 | This parameter can be a value of @ref USART_Parity |
| n0tform3 | 8:1c6281289d67 | 64 | @note When parity is enabled, the computed parity is inserted |
| n0tform3 | 8:1c6281289d67 | 65 | at the MSB position of the transmitted data (9th bit when |
| n0tform3 | 8:1c6281289d67 | 66 | the word length is set to 9 data bits; 8th bit when the |
| n0tform3 | 8:1c6281289d67 | 67 | word length is set to 8 data bits). */ |
| n0tform3 | 8:1c6281289d67 | 68 | |
| n0tform3 | 8:1c6281289d67 | 69 | uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. |
| n0tform3 | 8:1c6281289d67 | 70 | This parameter can be a value of @ref USART_Mode */ |
| n0tform3 | 8:1c6281289d67 | 71 | |
| n0tform3 | 8:1c6281289d67 | 72 | uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled |
| n0tform3 | 8:1c6281289d67 | 73 | or disabled. |
| n0tform3 | 8:1c6281289d67 | 74 | This parameter can be a value of @ref USART_Hardware_Flow_Control */ |
| n0tform3 | 8:1c6281289d67 | 75 | } USART_InitTypeDef; |
| n0tform3 | 8:1c6281289d67 | 76 | |
| n0tform3 | 8:1c6281289d67 | 77 | /** |
| n0tform3 | 8:1c6281289d67 | 78 | * @brief USART Clock Init Structure definition |
| n0tform3 | 8:1c6281289d67 | 79 | */ |
| n0tform3 | 8:1c6281289d67 | 80 | |
| n0tform3 | 8:1c6281289d67 | 81 | typedef struct |
| n0tform3 | 8:1c6281289d67 | 82 | { |
| n0tform3 | 8:1c6281289d67 | 83 | |
| n0tform3 | 8:1c6281289d67 | 84 | uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. |
| n0tform3 | 8:1c6281289d67 | 85 | This parameter can be a value of @ref USART_Clock */ |
| n0tform3 | 8:1c6281289d67 | 86 | |
| n0tform3 | 8:1c6281289d67 | 87 | uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. |
| n0tform3 | 8:1c6281289d67 | 88 | This parameter can be a value of @ref USART_Clock_Polarity */ |
| n0tform3 | 8:1c6281289d67 | 89 | |
| n0tform3 | 8:1c6281289d67 | 90 | uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. |
| n0tform3 | 8:1c6281289d67 | 91 | This parameter can be a value of @ref USART_Clock_Phase */ |
| n0tform3 | 8:1c6281289d67 | 92 | |
| n0tform3 | 8:1c6281289d67 | 93 | uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted |
| n0tform3 | 8:1c6281289d67 | 94 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. |
| n0tform3 | 8:1c6281289d67 | 95 | This parameter can be a value of @ref USART_Last_Bit */ |
| n0tform3 | 8:1c6281289d67 | 96 | } USART_ClockInitTypeDef; |
| n0tform3 | 8:1c6281289d67 | 97 | |
| n0tform3 | 8:1c6281289d67 | 98 | /* Exported constants --------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 99 | |
| n0tform3 | 8:1c6281289d67 | 100 | /** @defgroup USART_Exported_Constants |
| n0tform3 | 8:1c6281289d67 | 101 | * @{ |
| n0tform3 | 8:1c6281289d67 | 102 | */ |
| n0tform3 | 8:1c6281289d67 | 103 | |
| n0tform3 | 8:1c6281289d67 | 104 | #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ |
| n0tform3 | 8:1c6281289d67 | 105 | ((PERIPH) == USART2) || \ |
| n0tform3 | 8:1c6281289d67 | 106 | ((PERIPH) == USART3) || \ |
| n0tform3 | 8:1c6281289d67 | 107 | ((PERIPH) == UART4) || \ |
| n0tform3 | 8:1c6281289d67 | 108 | ((PERIPH) == UART5) || \ |
| n0tform3 | 8:1c6281289d67 | 109 | ((PERIPH) == USART6)) |
| n0tform3 | 8:1c6281289d67 | 110 | |
| n0tform3 | 8:1c6281289d67 | 111 | #define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ |
| n0tform3 | 8:1c6281289d67 | 112 | ((PERIPH) == USART2) || \ |
| n0tform3 | 8:1c6281289d67 | 113 | ((PERIPH) == USART3) || \ |
| n0tform3 | 8:1c6281289d67 | 114 | ((PERIPH) == USART6)) |
| n0tform3 | 8:1c6281289d67 | 115 | |
| n0tform3 | 8:1c6281289d67 | 116 | /** @defgroup USART_Word_Length |
| n0tform3 | 8:1c6281289d67 | 117 | * @{ |
| n0tform3 | 8:1c6281289d67 | 118 | */ |
| n0tform3 | 8:1c6281289d67 | 119 | |
| n0tform3 | 8:1c6281289d67 | 120 | #define USART_WordLength_8b ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 121 | #define USART_WordLength_9b ((uint16_t)0x1000) |
| n0tform3 | 8:1c6281289d67 | 122 | |
| n0tform3 | 8:1c6281289d67 | 123 | #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ |
| n0tform3 | 8:1c6281289d67 | 124 | ((LENGTH) == USART_WordLength_9b)) |
| n0tform3 | 8:1c6281289d67 | 125 | /** |
| n0tform3 | 8:1c6281289d67 | 126 | * @} |
| n0tform3 | 8:1c6281289d67 | 127 | */ |
| n0tform3 | 8:1c6281289d67 | 128 | |
| n0tform3 | 8:1c6281289d67 | 129 | /** @defgroup USART_Stop_Bits |
| n0tform3 | 8:1c6281289d67 | 130 | * @{ |
| n0tform3 | 8:1c6281289d67 | 131 | */ |
| n0tform3 | 8:1c6281289d67 | 132 | |
| n0tform3 | 8:1c6281289d67 | 133 | #define USART_StopBits_1 ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 134 | #define USART_StopBits_0_5 ((uint16_t)0x1000) |
| n0tform3 | 8:1c6281289d67 | 135 | #define USART_StopBits_2 ((uint16_t)0x2000) |
| n0tform3 | 8:1c6281289d67 | 136 | #define USART_StopBits_1_5 ((uint16_t)0x3000) |
| n0tform3 | 8:1c6281289d67 | 137 | #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ |
| n0tform3 | 8:1c6281289d67 | 138 | ((STOPBITS) == USART_StopBits_0_5) || \ |
| n0tform3 | 8:1c6281289d67 | 139 | ((STOPBITS) == USART_StopBits_2) || \ |
| n0tform3 | 8:1c6281289d67 | 140 | ((STOPBITS) == USART_StopBits_1_5)) |
| n0tform3 | 8:1c6281289d67 | 141 | /** |
| n0tform3 | 8:1c6281289d67 | 142 | * @} |
| n0tform3 | 8:1c6281289d67 | 143 | */ |
| n0tform3 | 8:1c6281289d67 | 144 | |
| n0tform3 | 8:1c6281289d67 | 145 | /** @defgroup USART_Parity |
| n0tform3 | 8:1c6281289d67 | 146 | * @{ |
| n0tform3 | 8:1c6281289d67 | 147 | */ |
| n0tform3 | 8:1c6281289d67 | 148 | |
| n0tform3 | 8:1c6281289d67 | 149 | #define USART_Parity_No ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 150 | #define USART_Parity_Even ((uint16_t)0x0400) |
| n0tform3 | 8:1c6281289d67 | 151 | #define USART_Parity_Odd ((uint16_t)0x0600) |
| n0tform3 | 8:1c6281289d67 | 152 | #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ |
| n0tform3 | 8:1c6281289d67 | 153 | ((PARITY) == USART_Parity_Even) || \ |
| n0tform3 | 8:1c6281289d67 | 154 | ((PARITY) == USART_Parity_Odd)) |
| n0tform3 | 8:1c6281289d67 | 155 | /** |
| n0tform3 | 8:1c6281289d67 | 156 | * @} |
| n0tform3 | 8:1c6281289d67 | 157 | */ |
| n0tform3 | 8:1c6281289d67 | 158 | |
| n0tform3 | 8:1c6281289d67 | 159 | /** @defgroup USART_Mode |
| n0tform3 | 8:1c6281289d67 | 160 | * @{ |
| n0tform3 | 8:1c6281289d67 | 161 | */ |
| n0tform3 | 8:1c6281289d67 | 162 | |
| n0tform3 | 8:1c6281289d67 | 163 | #define USART_Mode_Rx ((uint16_t)0x0004) |
| n0tform3 | 8:1c6281289d67 | 164 | #define USART_Mode_Tx ((uint16_t)0x0008) |
| n0tform3 | 8:1c6281289d67 | 165 | #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) |
| n0tform3 | 8:1c6281289d67 | 166 | /** |
| n0tform3 | 8:1c6281289d67 | 167 | * @} |
| n0tform3 | 8:1c6281289d67 | 168 | */ |
| n0tform3 | 8:1c6281289d67 | 169 | |
| n0tform3 | 8:1c6281289d67 | 170 | /** @defgroup USART_Hardware_Flow_Control |
| n0tform3 | 8:1c6281289d67 | 171 | * @{ |
| n0tform3 | 8:1c6281289d67 | 172 | */ |
| n0tform3 | 8:1c6281289d67 | 173 | #define USART_HardwareFlowControl_None ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 174 | #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) |
| n0tform3 | 8:1c6281289d67 | 175 | #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) |
| n0tform3 | 8:1c6281289d67 | 176 | #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) |
| n0tform3 | 8:1c6281289d67 | 177 | #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ |
| n0tform3 | 8:1c6281289d67 | 178 | (((CONTROL) == USART_HardwareFlowControl_None) || \ |
| n0tform3 | 8:1c6281289d67 | 179 | ((CONTROL) == USART_HardwareFlowControl_RTS) || \ |
| n0tform3 | 8:1c6281289d67 | 180 | ((CONTROL) == USART_HardwareFlowControl_CTS) || \ |
| n0tform3 | 8:1c6281289d67 | 181 | ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) |
| n0tform3 | 8:1c6281289d67 | 182 | /** |
| n0tform3 | 8:1c6281289d67 | 183 | * @} |
| n0tform3 | 8:1c6281289d67 | 184 | */ |
| n0tform3 | 8:1c6281289d67 | 185 | |
| n0tform3 | 8:1c6281289d67 | 186 | /** @defgroup USART_Clock |
| n0tform3 | 8:1c6281289d67 | 187 | * @{ |
| n0tform3 | 8:1c6281289d67 | 188 | */ |
| n0tform3 | 8:1c6281289d67 | 189 | #define USART_Clock_Disable ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 190 | #define USART_Clock_Enable ((uint16_t)0x0800) |
| n0tform3 | 8:1c6281289d67 | 191 | #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ |
| n0tform3 | 8:1c6281289d67 | 192 | ((CLOCK) == USART_Clock_Enable)) |
| n0tform3 | 8:1c6281289d67 | 193 | /** |
| n0tform3 | 8:1c6281289d67 | 194 | * @} |
| n0tform3 | 8:1c6281289d67 | 195 | */ |
| n0tform3 | 8:1c6281289d67 | 196 | |
| n0tform3 | 8:1c6281289d67 | 197 | /** @defgroup USART_Clock_Polarity |
| n0tform3 | 8:1c6281289d67 | 198 | * @{ |
| n0tform3 | 8:1c6281289d67 | 199 | */ |
| n0tform3 | 8:1c6281289d67 | 200 | |
| n0tform3 | 8:1c6281289d67 | 201 | #define USART_CPOL_Low ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 202 | #define USART_CPOL_High ((uint16_t)0x0400) |
| n0tform3 | 8:1c6281289d67 | 203 | #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) |
| n0tform3 | 8:1c6281289d67 | 204 | |
| n0tform3 | 8:1c6281289d67 | 205 | /** |
| n0tform3 | 8:1c6281289d67 | 206 | * @} |
| n0tform3 | 8:1c6281289d67 | 207 | */ |
| n0tform3 | 8:1c6281289d67 | 208 | |
| n0tform3 | 8:1c6281289d67 | 209 | /** @defgroup USART_Clock_Phase |
| n0tform3 | 8:1c6281289d67 | 210 | * @{ |
| n0tform3 | 8:1c6281289d67 | 211 | */ |
| n0tform3 | 8:1c6281289d67 | 212 | |
| n0tform3 | 8:1c6281289d67 | 213 | #define USART_CPHA_1Edge ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 214 | #define USART_CPHA_2Edge ((uint16_t)0x0200) |
| n0tform3 | 8:1c6281289d67 | 215 | #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) |
| n0tform3 | 8:1c6281289d67 | 216 | |
| n0tform3 | 8:1c6281289d67 | 217 | /** |
| n0tform3 | 8:1c6281289d67 | 218 | * @} |
| n0tform3 | 8:1c6281289d67 | 219 | */ |
| n0tform3 | 8:1c6281289d67 | 220 | |
| n0tform3 | 8:1c6281289d67 | 221 | /** @defgroup USART_Last_Bit |
| n0tform3 | 8:1c6281289d67 | 222 | * @{ |
| n0tform3 | 8:1c6281289d67 | 223 | */ |
| n0tform3 | 8:1c6281289d67 | 224 | |
| n0tform3 | 8:1c6281289d67 | 225 | #define USART_LastBit_Disable ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 226 | #define USART_LastBit_Enable ((uint16_t)0x0100) |
| n0tform3 | 8:1c6281289d67 | 227 | #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ |
| n0tform3 | 8:1c6281289d67 | 228 | ((LASTBIT) == USART_LastBit_Enable)) |
| n0tform3 | 8:1c6281289d67 | 229 | /** |
| n0tform3 | 8:1c6281289d67 | 230 | * @} |
| n0tform3 | 8:1c6281289d67 | 231 | */ |
| n0tform3 | 8:1c6281289d67 | 232 | |
| n0tform3 | 8:1c6281289d67 | 233 | /** @defgroup USART_Interrupt_definition |
| n0tform3 | 8:1c6281289d67 | 234 | * @{ |
| n0tform3 | 8:1c6281289d67 | 235 | */ |
| n0tform3 | 8:1c6281289d67 | 236 | |
| n0tform3 | 8:1c6281289d67 | 237 | #define USART_IT_PE ((uint16_t)0x0028) |
| n0tform3 | 8:1c6281289d67 | 238 | #define USART_IT_TXE ((uint16_t)0x0727) |
| n0tform3 | 8:1c6281289d67 | 239 | #define USART_IT_TC ((uint16_t)0x0626) |
| n0tform3 | 8:1c6281289d67 | 240 | #define USART_IT_RXNE ((uint16_t)0x0525) |
| n0tform3 | 8:1c6281289d67 | 241 | #define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ |
| n0tform3 | 8:1c6281289d67 | 242 | #define USART_IT_IDLE ((uint16_t)0x0424) |
| n0tform3 | 8:1c6281289d67 | 243 | #define USART_IT_LBD ((uint16_t)0x0846) |
| n0tform3 | 8:1c6281289d67 | 244 | #define USART_IT_CTS ((uint16_t)0x096A) |
| n0tform3 | 8:1c6281289d67 | 245 | #define USART_IT_ERR ((uint16_t)0x0060) |
| n0tform3 | 8:1c6281289d67 | 246 | #define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ |
| n0tform3 | 8:1c6281289d67 | 247 | #define USART_IT_NE ((uint16_t)0x0260) |
| n0tform3 | 8:1c6281289d67 | 248 | #define USART_IT_FE ((uint16_t)0x0160) |
| n0tform3 | 8:1c6281289d67 | 249 | |
| n0tform3 | 8:1c6281289d67 | 250 | /** @defgroup USART_Legacy |
| n0tform3 | 8:1c6281289d67 | 251 | * @{ |
| n0tform3 | 8:1c6281289d67 | 252 | */ |
| n0tform3 | 8:1c6281289d67 | 253 | #define USART_IT_ORE USART_IT_ORE_ER |
| n0tform3 | 8:1c6281289d67 | 254 | /** |
| n0tform3 | 8:1c6281289d67 | 255 | * @} |
| n0tform3 | 8:1c6281289d67 | 256 | */ |
| n0tform3 | 8:1c6281289d67 | 257 | |
| n0tform3 | 8:1c6281289d67 | 258 | #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ |
| n0tform3 | 8:1c6281289d67 | 259 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ |
| n0tform3 | 8:1c6281289d67 | 260 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ |
| n0tform3 | 8:1c6281289d67 | 261 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) |
| n0tform3 | 8:1c6281289d67 | 262 | #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ |
| n0tform3 | 8:1c6281289d67 | 263 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ |
| n0tform3 | 8:1c6281289d67 | 264 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ |
| n0tform3 | 8:1c6281289d67 | 265 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ |
| n0tform3 | 8:1c6281289d67 | 266 | ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ |
| n0tform3 | 8:1c6281289d67 | 267 | ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) |
| n0tform3 | 8:1c6281289d67 | 268 | #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ |
| n0tform3 | 8:1c6281289d67 | 269 | ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) |
| n0tform3 | 8:1c6281289d67 | 270 | /** |
| n0tform3 | 8:1c6281289d67 | 271 | * @} |
| n0tform3 | 8:1c6281289d67 | 272 | */ |
| n0tform3 | 8:1c6281289d67 | 273 | |
| n0tform3 | 8:1c6281289d67 | 274 | /** @defgroup USART_DMA_Requests |
| n0tform3 | 8:1c6281289d67 | 275 | * @{ |
| n0tform3 | 8:1c6281289d67 | 276 | */ |
| n0tform3 | 8:1c6281289d67 | 277 | |
| n0tform3 | 8:1c6281289d67 | 278 | #define USART_DMAReq_Tx ((uint16_t)0x0080) |
| n0tform3 | 8:1c6281289d67 | 279 | #define USART_DMAReq_Rx ((uint16_t)0x0040) |
| n0tform3 | 8:1c6281289d67 | 280 | #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) |
| n0tform3 | 8:1c6281289d67 | 281 | |
| n0tform3 | 8:1c6281289d67 | 282 | /** |
| n0tform3 | 8:1c6281289d67 | 283 | * @} |
| n0tform3 | 8:1c6281289d67 | 284 | */ |
| n0tform3 | 8:1c6281289d67 | 285 | |
| n0tform3 | 8:1c6281289d67 | 286 | /** @defgroup USART_WakeUp_methods |
| n0tform3 | 8:1c6281289d67 | 287 | * @{ |
| n0tform3 | 8:1c6281289d67 | 288 | */ |
| n0tform3 | 8:1c6281289d67 | 289 | |
| n0tform3 | 8:1c6281289d67 | 290 | #define USART_WakeUp_IdleLine ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 291 | #define USART_WakeUp_AddressMark ((uint16_t)0x0800) |
| n0tform3 | 8:1c6281289d67 | 292 | #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ |
| n0tform3 | 8:1c6281289d67 | 293 | ((WAKEUP) == USART_WakeUp_AddressMark)) |
| n0tform3 | 8:1c6281289d67 | 294 | /** |
| n0tform3 | 8:1c6281289d67 | 295 | * @} |
| n0tform3 | 8:1c6281289d67 | 296 | */ |
| n0tform3 | 8:1c6281289d67 | 297 | |
| n0tform3 | 8:1c6281289d67 | 298 | /** @defgroup USART_LIN_Break_Detection_Length |
| n0tform3 | 8:1c6281289d67 | 299 | * @{ |
| n0tform3 | 8:1c6281289d67 | 300 | */ |
| n0tform3 | 8:1c6281289d67 | 301 | |
| n0tform3 | 8:1c6281289d67 | 302 | #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 303 | #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) |
| n0tform3 | 8:1c6281289d67 | 304 | #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ |
| n0tform3 | 8:1c6281289d67 | 305 | (((LENGTH) == USART_LINBreakDetectLength_10b) || \ |
| n0tform3 | 8:1c6281289d67 | 306 | ((LENGTH) == USART_LINBreakDetectLength_11b)) |
| n0tform3 | 8:1c6281289d67 | 307 | /** |
| n0tform3 | 8:1c6281289d67 | 308 | * @} |
| n0tform3 | 8:1c6281289d67 | 309 | */ |
| n0tform3 | 8:1c6281289d67 | 310 | |
| n0tform3 | 8:1c6281289d67 | 311 | /** @defgroup USART_IrDA_Low_Power |
| n0tform3 | 8:1c6281289d67 | 312 | * @{ |
| n0tform3 | 8:1c6281289d67 | 313 | */ |
| n0tform3 | 8:1c6281289d67 | 314 | |
| n0tform3 | 8:1c6281289d67 | 315 | #define USART_IrDAMode_LowPower ((uint16_t)0x0004) |
| n0tform3 | 8:1c6281289d67 | 316 | #define USART_IrDAMode_Normal ((uint16_t)0x0000) |
| n0tform3 | 8:1c6281289d67 | 317 | #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ |
| n0tform3 | 8:1c6281289d67 | 318 | ((MODE) == USART_IrDAMode_Normal)) |
| n0tform3 | 8:1c6281289d67 | 319 | /** |
| n0tform3 | 8:1c6281289d67 | 320 | * @} |
| n0tform3 | 8:1c6281289d67 | 321 | */ |
| n0tform3 | 8:1c6281289d67 | 322 | |
| n0tform3 | 8:1c6281289d67 | 323 | /** @defgroup USART_Flags |
| n0tform3 | 8:1c6281289d67 | 324 | * @{ |
| n0tform3 | 8:1c6281289d67 | 325 | */ |
| n0tform3 | 8:1c6281289d67 | 326 | |
| n0tform3 | 8:1c6281289d67 | 327 | #define USART_FLAG_CTS ((uint16_t)0x0200) |
| n0tform3 | 8:1c6281289d67 | 328 | #define USART_FLAG_LBD ((uint16_t)0x0100) |
| n0tform3 | 8:1c6281289d67 | 329 | #define USART_FLAG_TXE ((uint16_t)0x0080) |
| n0tform3 | 8:1c6281289d67 | 330 | #define USART_FLAG_TC ((uint16_t)0x0040) |
| n0tform3 | 8:1c6281289d67 | 331 | #define USART_FLAG_RXNE ((uint16_t)0x0020) |
| n0tform3 | 8:1c6281289d67 | 332 | #define USART_FLAG_IDLE ((uint16_t)0x0010) |
| n0tform3 | 8:1c6281289d67 | 333 | #define USART_FLAG_ORE ((uint16_t)0x0008) |
| n0tform3 | 8:1c6281289d67 | 334 | #define USART_FLAG_NE ((uint16_t)0x0004) |
| n0tform3 | 8:1c6281289d67 | 335 | #define USART_FLAG_FE ((uint16_t)0x0002) |
| n0tform3 | 8:1c6281289d67 | 336 | #define USART_FLAG_PE ((uint16_t)0x0001) |
| n0tform3 | 8:1c6281289d67 | 337 | #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ |
| n0tform3 | 8:1c6281289d67 | 338 | ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ |
| n0tform3 | 8:1c6281289d67 | 339 | ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ |
| n0tform3 | 8:1c6281289d67 | 340 | ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ |
| n0tform3 | 8:1c6281289d67 | 341 | ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) |
| n0tform3 | 8:1c6281289d67 | 342 | |
| n0tform3 | 8:1c6281289d67 | 343 | #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) |
| n0tform3 | 8:1c6281289d67 | 344 | |
| n0tform3 | 8:1c6281289d67 | 345 | #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) |
| n0tform3 | 8:1c6281289d67 | 346 | #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) |
| n0tform3 | 8:1c6281289d67 | 347 | #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) |
| n0tform3 | 8:1c6281289d67 | 348 | |
| n0tform3 | 8:1c6281289d67 | 349 | /** |
| n0tform3 | 8:1c6281289d67 | 350 | * @} |
| n0tform3 | 8:1c6281289d67 | 351 | */ |
| n0tform3 | 8:1c6281289d67 | 352 | |
| n0tform3 | 8:1c6281289d67 | 353 | /** |
| n0tform3 | 8:1c6281289d67 | 354 | * @} |
| n0tform3 | 8:1c6281289d67 | 355 | */ |
| n0tform3 | 8:1c6281289d67 | 356 | |
| n0tform3 | 8:1c6281289d67 | 357 | /* Exported macro ------------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 358 | /* Exported functions --------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 359 | |
| n0tform3 | 8:1c6281289d67 | 360 | /* Function used to set the USART configuration to the default reset state ***/ |
| n0tform3 | 8:1c6281289d67 | 361 | void USART_DeInit(USART_TypeDef* USARTx); |
| n0tform3 | 8:1c6281289d67 | 362 | |
| n0tform3 | 8:1c6281289d67 | 363 | /* Initialization and Configuration functions *********************************/ |
| n0tform3 | 8:1c6281289d67 | 364 | void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); |
| n0tform3 | 8:1c6281289d67 | 365 | void USART_StructInit(USART_InitTypeDef* USART_InitStruct); |
| n0tform3 | 8:1c6281289d67 | 366 | void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); |
| n0tform3 | 8:1c6281289d67 | 367 | void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); |
| n0tform3 | 8:1c6281289d67 | 368 | void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 369 | void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); |
| n0tform3 | 8:1c6281289d67 | 370 | void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 371 | void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 372 | |
| n0tform3 | 8:1c6281289d67 | 373 | /* Data transfers functions ***************************************************/ |
| n0tform3 | 8:1c6281289d67 | 374 | void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); |
| n0tform3 | 8:1c6281289d67 | 375 | uint16_t USART_ReceiveData(USART_TypeDef* USARTx); |
| n0tform3 | 8:1c6281289d67 | 376 | |
| n0tform3 | 8:1c6281289d67 | 377 | /* Multi-Processor Communication functions ************************************/ |
| n0tform3 | 8:1c6281289d67 | 378 | void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); |
| n0tform3 | 8:1c6281289d67 | 379 | void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); |
| n0tform3 | 8:1c6281289d67 | 380 | void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 381 | |
| n0tform3 | 8:1c6281289d67 | 382 | /* LIN mode functions *********************************************************/ |
| n0tform3 | 8:1c6281289d67 | 383 | void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); |
| n0tform3 | 8:1c6281289d67 | 384 | void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 385 | void USART_SendBreak(USART_TypeDef* USARTx); |
| n0tform3 | 8:1c6281289d67 | 386 | |
| n0tform3 | 8:1c6281289d67 | 387 | /* Half-duplex mode function **************************************************/ |
| n0tform3 | 8:1c6281289d67 | 388 | void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 389 | |
| n0tform3 | 8:1c6281289d67 | 390 | /* Smartcard mode functions ***************************************************/ |
| n0tform3 | 8:1c6281289d67 | 391 | void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 392 | void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 393 | void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); |
| n0tform3 | 8:1c6281289d67 | 394 | |
| n0tform3 | 8:1c6281289d67 | 395 | /* IrDA mode functions ********************************************************/ |
| n0tform3 | 8:1c6281289d67 | 396 | void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); |
| n0tform3 | 8:1c6281289d67 | 397 | void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 398 | |
| n0tform3 | 8:1c6281289d67 | 399 | /* DMA transfers management functions *****************************************/ |
| n0tform3 | 8:1c6281289d67 | 400 | void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 401 | |
| n0tform3 | 8:1c6281289d67 | 402 | /* Interrupts and flags management functions **********************************/ |
| n0tform3 | 8:1c6281289d67 | 403 | void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 404 | FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); |
| n0tform3 | 8:1c6281289d67 | 405 | void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); |
| n0tform3 | 8:1c6281289d67 | 406 | ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); |
| n0tform3 | 8:1c6281289d67 | 407 | void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); |
| n0tform3 | 8:1c6281289d67 | 408 | |
| n0tform3 | 8:1c6281289d67 | 409 | #ifdef __cplusplus |
| n0tform3 | 8:1c6281289d67 | 410 | } |
| n0tform3 | 8:1c6281289d67 | 411 | #endif |
| n0tform3 | 8:1c6281289d67 | 412 | |
| n0tform3 | 8:1c6281289d67 | 413 | #endif /* __STM32F4xx_USART_H */ |
| n0tform3 | 8:1c6281289d67 | 414 | |
| n0tform3 | 8:1c6281289d67 | 415 | /** |
| n0tform3 | 8:1c6281289d67 | 416 | * @} |
| n0tform3 | 8:1c6281289d67 | 417 | */ |
| n0tform3 | 8:1c6281289d67 | 418 | |
| n0tform3 | 8:1c6281289d67 | 419 | /** |
| n0tform3 | 8:1c6281289d67 | 420 | * @} |
| n0tform3 | 8:1c6281289d67 | 421 | */ |
| n0tform3 | 8:1c6281289d67 | 422 | |
| n0tform3 | 8:1c6281289d67 | 423 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
| n0tform3 | 8:1c6281289d67 | 424 |