mattia griotti
Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial
Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed
Fork of
HelloWorld_IKS01A1
by 
ST
stm32f4xx_rcc.h@8:1c6281289d67, 2015-11-15 (annotated)
- Committer:
- n0tform3
- Date:
- Sun Nov 15 09:00:40 2015 +0000
- Revision:
- 8:1c6281289d67
test with led
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| n0tform3 | 8:1c6281289d67 | 1 | /** |
| n0tform3 | 8:1c6281289d67 | 2 | ****************************************************************************** |
| n0tform3 | 8:1c6281289d67 | 3 | * @file stm32f4xx_rcc.h |
| n0tform3 | 8:1c6281289d67 | 4 | * @author MCD Application Team |
| n0tform3 | 8:1c6281289d67 | 5 | * @version V1.0.0 |
| n0tform3 | 8:1c6281289d67 | 6 | * @date 30-September-2011 |
| n0tform3 | 8:1c6281289d67 | 7 | * @brief This file contains all the functions prototypes for the RCC firmware library. |
| n0tform3 | 8:1c6281289d67 | 8 | ****************************************************************************** |
| n0tform3 | 8:1c6281289d67 | 9 | * @attention |
| n0tform3 | 8:1c6281289d67 | 10 | * |
| n0tform3 | 8:1c6281289d67 | 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
| n0tform3 | 8:1c6281289d67 | 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
| n0tform3 | 8:1c6281289d67 | 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
| n0tform3 | 8:1c6281289d67 | 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
| n0tform3 | 8:1c6281289d67 | 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
| n0tform3 | 8:1c6281289d67 | 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
| n0tform3 | 8:1c6281289d67 | 17 | * |
| n0tform3 | 8:1c6281289d67 | 18 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
| n0tform3 | 8:1c6281289d67 | 19 | ****************************************************************************** |
| n0tform3 | 8:1c6281289d67 | 20 | */ |
| n0tform3 | 8:1c6281289d67 | 21 | |
| n0tform3 | 8:1c6281289d67 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 23 | #ifndef __STM32F4xx_RCC_H |
| n0tform3 | 8:1c6281289d67 | 24 | #define __STM32F4xx_RCC_H |
| n0tform3 | 8:1c6281289d67 | 25 | |
| n0tform3 | 8:1c6281289d67 | 26 | #ifdef __cplusplus |
| n0tform3 | 8:1c6281289d67 | 27 | extern "C" { |
| n0tform3 | 8:1c6281289d67 | 28 | #endif |
| n0tform3 | 8:1c6281289d67 | 29 | |
| n0tform3 | 8:1c6281289d67 | 30 | /* Includes ------------------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 31 | #include "stm32f4xx.h" |
| n0tform3 | 8:1c6281289d67 | 32 | |
| n0tform3 | 8:1c6281289d67 | 33 | /** @addtogroup STM32F4xx_StdPeriph_Driver |
| n0tform3 | 8:1c6281289d67 | 34 | * @{ |
| n0tform3 | 8:1c6281289d67 | 35 | */ |
| n0tform3 | 8:1c6281289d67 | 36 | |
| n0tform3 | 8:1c6281289d67 | 37 | /** @addtogroup RCC |
| n0tform3 | 8:1c6281289d67 | 38 | * @{ |
| n0tform3 | 8:1c6281289d67 | 39 | */ |
| n0tform3 | 8:1c6281289d67 | 40 | |
| n0tform3 | 8:1c6281289d67 | 41 | /* Exported types ------------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 42 | typedef struct |
| n0tform3 | 8:1c6281289d67 | 43 | { |
| n0tform3 | 8:1c6281289d67 | 44 | uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ |
| n0tform3 | 8:1c6281289d67 | 45 | uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ |
| n0tform3 | 8:1c6281289d67 | 46 | uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ |
| n0tform3 | 8:1c6281289d67 | 47 | uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ |
| n0tform3 | 8:1c6281289d67 | 48 | }RCC_ClocksTypeDef; |
| n0tform3 | 8:1c6281289d67 | 49 | |
| n0tform3 | 8:1c6281289d67 | 50 | /* Exported constants --------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 51 | |
| n0tform3 | 8:1c6281289d67 | 52 | /** @defgroup RCC_Exported_Constants |
| n0tform3 | 8:1c6281289d67 | 53 | * @{ |
| n0tform3 | 8:1c6281289d67 | 54 | */ |
| n0tform3 | 8:1c6281289d67 | 55 | |
| n0tform3 | 8:1c6281289d67 | 56 | /** @defgroup RCC_HSE_configuration |
| n0tform3 | 8:1c6281289d67 | 57 | * @{ |
| n0tform3 | 8:1c6281289d67 | 58 | */ |
| n0tform3 | 8:1c6281289d67 | 59 | #define RCC_HSE_OFF ((uint8_t)0x00) |
| n0tform3 | 8:1c6281289d67 | 60 | #define RCC_HSE_ON ((uint8_t)0x01) |
| n0tform3 | 8:1c6281289d67 | 61 | #define RCC_HSE_Bypass ((uint8_t)0x05) |
| n0tform3 | 8:1c6281289d67 | 62 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
| n0tform3 | 8:1c6281289d67 | 63 | ((HSE) == RCC_HSE_Bypass)) |
| n0tform3 | 8:1c6281289d67 | 64 | /** |
| n0tform3 | 8:1c6281289d67 | 65 | * @} |
| n0tform3 | 8:1c6281289d67 | 66 | */ |
| n0tform3 | 8:1c6281289d67 | 67 | |
| n0tform3 | 8:1c6281289d67 | 68 | /** @defgroup RCC_PLL_Clock_Source |
| n0tform3 | 8:1c6281289d67 | 69 | * @{ |
| n0tform3 | 8:1c6281289d67 | 70 | */ |
| n0tform3 | 8:1c6281289d67 | 71 | #define RCC_PLLSource_HSI ((uint32_t)0x00000000) |
| n0tform3 | 8:1c6281289d67 | 72 | #define RCC_PLLSource_HSE ((uint32_t)0x00400000) |
| n0tform3 | 8:1c6281289d67 | 73 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ |
| n0tform3 | 8:1c6281289d67 | 74 | ((SOURCE) == RCC_PLLSource_HSE)) |
| n0tform3 | 8:1c6281289d67 | 75 | #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) |
| n0tform3 | 8:1c6281289d67 | 76 | #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
| n0tform3 | 8:1c6281289d67 | 77 | #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) |
| n0tform3 | 8:1c6281289d67 | 78 | #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) |
| n0tform3 | 8:1c6281289d67 | 79 | |
| n0tform3 | 8:1c6281289d67 | 80 | #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
| n0tform3 | 8:1c6281289d67 | 81 | #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
| n0tform3 | 8:1c6281289d67 | 82 | /** |
| n0tform3 | 8:1c6281289d67 | 83 | * @} |
| n0tform3 | 8:1c6281289d67 | 84 | */ |
| n0tform3 | 8:1c6281289d67 | 85 | |
| n0tform3 | 8:1c6281289d67 | 86 | /** @defgroup RCC_System_Clock_Source |
| n0tform3 | 8:1c6281289d67 | 87 | * @{ |
| n0tform3 | 8:1c6281289d67 | 88 | */ |
| n0tform3 | 8:1c6281289d67 | 89 | #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) |
| n0tform3 | 8:1c6281289d67 | 90 | #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) |
| n0tform3 | 8:1c6281289d67 | 91 | #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) |
| n0tform3 | 8:1c6281289d67 | 92 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ |
| n0tform3 | 8:1c6281289d67 | 93 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
| n0tform3 | 8:1c6281289d67 | 94 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
| n0tform3 | 8:1c6281289d67 | 95 | /** |
| n0tform3 | 8:1c6281289d67 | 96 | * @} |
| n0tform3 | 8:1c6281289d67 | 97 | */ |
| n0tform3 | 8:1c6281289d67 | 98 | |
| n0tform3 | 8:1c6281289d67 | 99 | /** @defgroup RCC_AHB_Clock_Source |
| n0tform3 | 8:1c6281289d67 | 100 | * @{ |
| n0tform3 | 8:1c6281289d67 | 101 | */ |
| n0tform3 | 8:1c6281289d67 | 102 | #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) |
| n0tform3 | 8:1c6281289d67 | 103 | #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) |
| n0tform3 | 8:1c6281289d67 | 104 | #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) |
| n0tform3 | 8:1c6281289d67 | 105 | #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) |
| n0tform3 | 8:1c6281289d67 | 106 | #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) |
| n0tform3 | 8:1c6281289d67 | 107 | #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) |
| n0tform3 | 8:1c6281289d67 | 108 | #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) |
| n0tform3 | 8:1c6281289d67 | 109 | #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) |
| n0tform3 | 8:1c6281289d67 | 110 | #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) |
| n0tform3 | 8:1c6281289d67 | 111 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ |
| n0tform3 | 8:1c6281289d67 | 112 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
| n0tform3 | 8:1c6281289d67 | 113 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
| n0tform3 | 8:1c6281289d67 | 114 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
| n0tform3 | 8:1c6281289d67 | 115 | ((HCLK) == RCC_SYSCLK_Div512)) |
| n0tform3 | 8:1c6281289d67 | 116 | /** |
| n0tform3 | 8:1c6281289d67 | 117 | * @} |
| n0tform3 | 8:1c6281289d67 | 118 | */ |
| n0tform3 | 8:1c6281289d67 | 119 | |
| n0tform3 | 8:1c6281289d67 | 120 | /** @defgroup RCC_APB1_APB2_Clock_Source |
| n0tform3 | 8:1c6281289d67 | 121 | * @{ |
| n0tform3 | 8:1c6281289d67 | 122 | */ |
| n0tform3 | 8:1c6281289d67 | 123 | #define RCC_HCLK_Div1 ((uint32_t)0x00000000) |
| n0tform3 | 8:1c6281289d67 | 124 | #define RCC_HCLK_Div2 ((uint32_t)0x00001000) |
| n0tform3 | 8:1c6281289d67 | 125 | #define RCC_HCLK_Div4 ((uint32_t)0x00001400) |
| n0tform3 | 8:1c6281289d67 | 126 | #define RCC_HCLK_Div8 ((uint32_t)0x00001800) |
| n0tform3 | 8:1c6281289d67 | 127 | #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) |
| n0tform3 | 8:1c6281289d67 | 128 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ |
| n0tform3 | 8:1c6281289d67 | 129 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
| n0tform3 | 8:1c6281289d67 | 130 | ((PCLK) == RCC_HCLK_Div16)) |
| n0tform3 | 8:1c6281289d67 | 131 | /** |
| n0tform3 | 8:1c6281289d67 | 132 | * @} |
| n0tform3 | 8:1c6281289d67 | 133 | */ |
| n0tform3 | 8:1c6281289d67 | 134 | |
| n0tform3 | 8:1c6281289d67 | 135 | /** @defgroup RCC_Interrupt_Source |
| n0tform3 | 8:1c6281289d67 | 136 | * @{ |
| n0tform3 | 8:1c6281289d67 | 137 | */ |
| n0tform3 | 8:1c6281289d67 | 138 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
| n0tform3 | 8:1c6281289d67 | 139 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
| n0tform3 | 8:1c6281289d67 | 140 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
| n0tform3 | 8:1c6281289d67 | 141 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
| n0tform3 | 8:1c6281289d67 | 142 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
| n0tform3 | 8:1c6281289d67 | 143 | #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) |
| n0tform3 | 8:1c6281289d67 | 144 | #define RCC_IT_CSS ((uint8_t)0x80) |
| n0tform3 | 8:1c6281289d67 | 145 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 146 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
| n0tform3 | 8:1c6281289d67 | 147 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
| n0tform3 | 8:1c6281289d67 | 148 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ |
| n0tform3 | 8:1c6281289d67 | 149 | ((IT) == RCC_IT_PLLI2SRDY)) |
| n0tform3 | 8:1c6281289d67 | 150 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 151 | /** |
| n0tform3 | 8:1c6281289d67 | 152 | * @} |
| n0tform3 | 8:1c6281289d67 | 153 | */ |
| n0tform3 | 8:1c6281289d67 | 154 | |
| n0tform3 | 8:1c6281289d67 | 155 | /** @defgroup RCC_LSE_Configuration |
| n0tform3 | 8:1c6281289d67 | 156 | * @{ |
| n0tform3 | 8:1c6281289d67 | 157 | */ |
| n0tform3 | 8:1c6281289d67 | 158 | #define RCC_LSE_OFF ((uint8_t)0x00) |
| n0tform3 | 8:1c6281289d67 | 159 | #define RCC_LSE_ON ((uint8_t)0x01) |
| n0tform3 | 8:1c6281289d67 | 160 | #define RCC_LSE_Bypass ((uint8_t)0x04) |
| n0tform3 | 8:1c6281289d67 | 161 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
| n0tform3 | 8:1c6281289d67 | 162 | ((LSE) == RCC_LSE_Bypass)) |
| n0tform3 | 8:1c6281289d67 | 163 | /** |
| n0tform3 | 8:1c6281289d67 | 164 | * @} |
| n0tform3 | 8:1c6281289d67 | 165 | */ |
| n0tform3 | 8:1c6281289d67 | 166 | |
| n0tform3 | 8:1c6281289d67 | 167 | /** @defgroup RCC_RTC_Clock_Source |
| n0tform3 | 8:1c6281289d67 | 168 | * @{ |
| n0tform3 | 8:1c6281289d67 | 169 | */ |
| n0tform3 | 8:1c6281289d67 | 170 | #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) |
| n0tform3 | 8:1c6281289d67 | 171 | #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) |
| n0tform3 | 8:1c6281289d67 | 172 | #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) |
| n0tform3 | 8:1c6281289d67 | 173 | #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) |
| n0tform3 | 8:1c6281289d67 | 174 | #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) |
| n0tform3 | 8:1c6281289d67 | 175 | #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) |
| n0tform3 | 8:1c6281289d67 | 176 | #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) |
| n0tform3 | 8:1c6281289d67 | 177 | #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) |
| n0tform3 | 8:1c6281289d67 | 178 | #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) |
| n0tform3 | 8:1c6281289d67 | 179 | #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) |
| n0tform3 | 8:1c6281289d67 | 180 | #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) |
| n0tform3 | 8:1c6281289d67 | 181 | #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) |
| n0tform3 | 8:1c6281289d67 | 182 | #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) |
| n0tform3 | 8:1c6281289d67 | 183 | #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) |
| n0tform3 | 8:1c6281289d67 | 184 | #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) |
| n0tform3 | 8:1c6281289d67 | 185 | #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) |
| n0tform3 | 8:1c6281289d67 | 186 | #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) |
| n0tform3 | 8:1c6281289d67 | 187 | #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) |
| n0tform3 | 8:1c6281289d67 | 188 | #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) |
| n0tform3 | 8:1c6281289d67 | 189 | #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) |
| n0tform3 | 8:1c6281289d67 | 190 | #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) |
| n0tform3 | 8:1c6281289d67 | 191 | #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) |
| n0tform3 | 8:1c6281289d67 | 192 | #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) |
| n0tform3 | 8:1c6281289d67 | 193 | #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) |
| n0tform3 | 8:1c6281289d67 | 194 | #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) |
| n0tform3 | 8:1c6281289d67 | 195 | #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) |
| n0tform3 | 8:1c6281289d67 | 196 | #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) |
| n0tform3 | 8:1c6281289d67 | 197 | #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) |
| n0tform3 | 8:1c6281289d67 | 198 | #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) |
| n0tform3 | 8:1c6281289d67 | 199 | #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) |
| n0tform3 | 8:1c6281289d67 | 200 | #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) |
| n0tform3 | 8:1c6281289d67 | 201 | #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) |
| n0tform3 | 8:1c6281289d67 | 202 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ |
| n0tform3 | 8:1c6281289d67 | 203 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
| n0tform3 | 8:1c6281289d67 | 204 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ |
| n0tform3 | 8:1c6281289d67 | 205 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ |
| n0tform3 | 8:1c6281289d67 | 206 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ |
| n0tform3 | 8:1c6281289d67 | 207 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ |
| n0tform3 | 8:1c6281289d67 | 208 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ |
| n0tform3 | 8:1c6281289d67 | 209 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ |
| n0tform3 | 8:1c6281289d67 | 210 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ |
| n0tform3 | 8:1c6281289d67 | 211 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ |
| n0tform3 | 8:1c6281289d67 | 212 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ |
| n0tform3 | 8:1c6281289d67 | 213 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ |
| n0tform3 | 8:1c6281289d67 | 214 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ |
| n0tform3 | 8:1c6281289d67 | 215 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ |
| n0tform3 | 8:1c6281289d67 | 216 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ |
| n0tform3 | 8:1c6281289d67 | 217 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ |
| n0tform3 | 8:1c6281289d67 | 218 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ |
| n0tform3 | 8:1c6281289d67 | 219 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ |
| n0tform3 | 8:1c6281289d67 | 220 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ |
| n0tform3 | 8:1c6281289d67 | 221 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ |
| n0tform3 | 8:1c6281289d67 | 222 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ |
| n0tform3 | 8:1c6281289d67 | 223 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ |
| n0tform3 | 8:1c6281289d67 | 224 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ |
| n0tform3 | 8:1c6281289d67 | 225 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ |
| n0tform3 | 8:1c6281289d67 | 226 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ |
| n0tform3 | 8:1c6281289d67 | 227 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ |
| n0tform3 | 8:1c6281289d67 | 228 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ |
| n0tform3 | 8:1c6281289d67 | 229 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ |
| n0tform3 | 8:1c6281289d67 | 230 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ |
| n0tform3 | 8:1c6281289d67 | 231 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ |
| n0tform3 | 8:1c6281289d67 | 232 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ |
| n0tform3 | 8:1c6281289d67 | 233 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) |
| n0tform3 | 8:1c6281289d67 | 234 | /** |
| n0tform3 | 8:1c6281289d67 | 235 | * @} |
| n0tform3 | 8:1c6281289d67 | 236 | */ |
| n0tform3 | 8:1c6281289d67 | 237 | |
| n0tform3 | 8:1c6281289d67 | 238 | /** @defgroup RCC_I2S_Clock_Source |
| n0tform3 | 8:1c6281289d67 | 239 | * @{ |
| n0tform3 | 8:1c6281289d67 | 240 | */ |
| n0tform3 | 8:1c6281289d67 | 241 | #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) |
| n0tform3 | 8:1c6281289d67 | 242 | #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) |
| n0tform3 | 8:1c6281289d67 | 243 | |
| n0tform3 | 8:1c6281289d67 | 244 | #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) |
| n0tform3 | 8:1c6281289d67 | 245 | /** |
| n0tform3 | 8:1c6281289d67 | 246 | * @} |
| n0tform3 | 8:1c6281289d67 | 247 | */ |
| n0tform3 | 8:1c6281289d67 | 248 | |
| n0tform3 | 8:1c6281289d67 | 249 | /** @defgroup RCC_AHB1_Peripherals |
| n0tform3 | 8:1c6281289d67 | 250 | * @{ |
| n0tform3 | 8:1c6281289d67 | 251 | */ |
| n0tform3 | 8:1c6281289d67 | 252 | #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) |
| n0tform3 | 8:1c6281289d67 | 253 | #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) |
| n0tform3 | 8:1c6281289d67 | 254 | #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) |
| n0tform3 | 8:1c6281289d67 | 255 | #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) |
| n0tform3 | 8:1c6281289d67 | 256 | #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) |
| n0tform3 | 8:1c6281289d67 | 257 | #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) |
| n0tform3 | 8:1c6281289d67 | 258 | #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) |
| n0tform3 | 8:1c6281289d67 | 259 | #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) |
| n0tform3 | 8:1c6281289d67 | 260 | #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) |
| n0tform3 | 8:1c6281289d67 | 261 | #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) |
| n0tform3 | 8:1c6281289d67 | 262 | #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) |
| n0tform3 | 8:1c6281289d67 | 263 | #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) |
| n0tform3 | 8:1c6281289d67 | 264 | #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) |
| n0tform3 | 8:1c6281289d67 | 265 | #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) |
| n0tform3 | 8:1c6281289d67 | 266 | #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) |
| n0tform3 | 8:1c6281289d67 | 267 | #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) |
| n0tform3 | 8:1c6281289d67 | 268 | #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) |
| n0tform3 | 8:1c6281289d67 | 269 | #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) |
| n0tform3 | 8:1c6281289d67 | 270 | #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) |
| n0tform3 | 8:1c6281289d67 | 271 | #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) |
| n0tform3 | 8:1c6281289d67 | 272 | #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) |
| n0tform3 | 8:1c6281289d67 | 273 | #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) |
| n0tform3 | 8:1c6281289d67 | 274 | #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) |
| n0tform3 | 8:1c6281289d67 | 275 | #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 276 | #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 277 | #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 278 | /** |
| n0tform3 | 8:1c6281289d67 | 279 | * @} |
| n0tform3 | 8:1c6281289d67 | 280 | */ |
| n0tform3 | 8:1c6281289d67 | 281 | |
| n0tform3 | 8:1c6281289d67 | 282 | /** @defgroup RCC_AHB2_Peripherals |
| n0tform3 | 8:1c6281289d67 | 283 | * @{ |
| n0tform3 | 8:1c6281289d67 | 284 | */ |
| n0tform3 | 8:1c6281289d67 | 285 | #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) |
| n0tform3 | 8:1c6281289d67 | 286 | #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) |
| n0tform3 | 8:1c6281289d67 | 287 | #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) |
| n0tform3 | 8:1c6281289d67 | 288 | #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) |
| n0tform3 | 8:1c6281289d67 | 289 | #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) |
| n0tform3 | 8:1c6281289d67 | 290 | #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 291 | /** |
| n0tform3 | 8:1c6281289d67 | 292 | * @} |
| n0tform3 | 8:1c6281289d67 | 293 | */ |
| n0tform3 | 8:1c6281289d67 | 294 | |
| n0tform3 | 8:1c6281289d67 | 295 | /** @defgroup RCC_AHB3_Peripherals |
| n0tform3 | 8:1c6281289d67 | 296 | * @{ |
| n0tform3 | 8:1c6281289d67 | 297 | */ |
| n0tform3 | 8:1c6281289d67 | 298 | #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) |
| n0tform3 | 8:1c6281289d67 | 299 | #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 300 | /** |
| n0tform3 | 8:1c6281289d67 | 301 | * @} |
| n0tform3 | 8:1c6281289d67 | 302 | */ |
| n0tform3 | 8:1c6281289d67 | 303 | |
| n0tform3 | 8:1c6281289d67 | 304 | /** @defgroup RCC_APB1_Peripherals |
| n0tform3 | 8:1c6281289d67 | 305 | * @{ |
| n0tform3 | 8:1c6281289d67 | 306 | */ |
| n0tform3 | 8:1c6281289d67 | 307 | #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) |
| n0tform3 | 8:1c6281289d67 | 308 | #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) |
| n0tform3 | 8:1c6281289d67 | 309 | #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) |
| n0tform3 | 8:1c6281289d67 | 310 | #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) |
| n0tform3 | 8:1c6281289d67 | 311 | #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) |
| n0tform3 | 8:1c6281289d67 | 312 | #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) |
| n0tform3 | 8:1c6281289d67 | 313 | #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) |
| n0tform3 | 8:1c6281289d67 | 314 | #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) |
| n0tform3 | 8:1c6281289d67 | 315 | #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) |
| n0tform3 | 8:1c6281289d67 | 316 | #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) |
| n0tform3 | 8:1c6281289d67 | 317 | #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) |
| n0tform3 | 8:1c6281289d67 | 318 | #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) |
| n0tform3 | 8:1c6281289d67 | 319 | #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) |
| n0tform3 | 8:1c6281289d67 | 320 | #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) |
| n0tform3 | 8:1c6281289d67 | 321 | #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) |
| n0tform3 | 8:1c6281289d67 | 322 | #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) |
| n0tform3 | 8:1c6281289d67 | 323 | #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) |
| n0tform3 | 8:1c6281289d67 | 324 | #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) |
| n0tform3 | 8:1c6281289d67 | 325 | #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) |
| n0tform3 | 8:1c6281289d67 | 326 | #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) |
| n0tform3 | 8:1c6281289d67 | 327 | #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) |
| n0tform3 | 8:1c6281289d67 | 328 | #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) |
| n0tform3 | 8:1c6281289d67 | 329 | #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) |
| n0tform3 | 8:1c6281289d67 | 330 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 331 | /** |
| n0tform3 | 8:1c6281289d67 | 332 | * @} |
| n0tform3 | 8:1c6281289d67 | 333 | */ |
| n0tform3 | 8:1c6281289d67 | 334 | |
| n0tform3 | 8:1c6281289d67 | 335 | /** @defgroup RCC_APB2_Peripherals |
| n0tform3 | 8:1c6281289d67 | 336 | * @{ |
| n0tform3 | 8:1c6281289d67 | 337 | */ |
| n0tform3 | 8:1c6281289d67 | 338 | #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) |
| n0tform3 | 8:1c6281289d67 | 339 | #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) |
| n0tform3 | 8:1c6281289d67 | 340 | #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) |
| n0tform3 | 8:1c6281289d67 | 341 | #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) |
| n0tform3 | 8:1c6281289d67 | 342 | #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) |
| n0tform3 | 8:1c6281289d67 | 343 | #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) |
| n0tform3 | 8:1c6281289d67 | 344 | #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) |
| n0tform3 | 8:1c6281289d67 | 345 | #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) |
| n0tform3 | 8:1c6281289d67 | 346 | #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) |
| n0tform3 | 8:1c6281289d67 | 347 | #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) |
| n0tform3 | 8:1c6281289d67 | 348 | #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) |
| n0tform3 | 8:1c6281289d67 | 349 | #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) |
| n0tform3 | 8:1c6281289d67 | 350 | #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) |
| n0tform3 | 8:1c6281289d67 | 351 | #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) |
| n0tform3 | 8:1c6281289d67 | 352 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 353 | #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) |
| n0tform3 | 8:1c6281289d67 | 354 | /** |
| n0tform3 | 8:1c6281289d67 | 355 | * @} |
| n0tform3 | 8:1c6281289d67 | 356 | */ |
| n0tform3 | 8:1c6281289d67 | 357 | |
| n0tform3 | 8:1c6281289d67 | 358 | /** @defgroup RCC_MCO1_Clock_Source_Prescaler |
| n0tform3 | 8:1c6281289d67 | 359 | * @{ |
| n0tform3 | 8:1c6281289d67 | 360 | */ |
| n0tform3 | 8:1c6281289d67 | 361 | #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) |
| n0tform3 | 8:1c6281289d67 | 362 | #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) |
| n0tform3 | 8:1c6281289d67 | 363 | #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) |
| n0tform3 | 8:1c6281289d67 | 364 | #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) |
| n0tform3 | 8:1c6281289d67 | 365 | #define RCC_MCO1Div_1 ((uint32_t)0x00000000) |
| n0tform3 | 8:1c6281289d67 | 366 | #define RCC_MCO1Div_2 ((uint32_t)0x04000000) |
| n0tform3 | 8:1c6281289d67 | 367 | #define RCC_MCO1Div_3 ((uint32_t)0x05000000) |
| n0tform3 | 8:1c6281289d67 | 368 | #define RCC_MCO1Div_4 ((uint32_t)0x06000000) |
| n0tform3 | 8:1c6281289d67 | 369 | #define RCC_MCO1Div_5 ((uint32_t)0x07000000) |
| n0tform3 | 8:1c6281289d67 | 370 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ |
| n0tform3 | 8:1c6281289d67 | 371 | ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) |
| n0tform3 | 8:1c6281289d67 | 372 | |
| n0tform3 | 8:1c6281289d67 | 373 | #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ |
| n0tform3 | 8:1c6281289d67 | 374 | ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ |
| n0tform3 | 8:1c6281289d67 | 375 | ((DIV) == RCC_MCO1Div_5)) |
| n0tform3 | 8:1c6281289d67 | 376 | /** |
| n0tform3 | 8:1c6281289d67 | 377 | * @} |
| n0tform3 | 8:1c6281289d67 | 378 | */ |
| n0tform3 | 8:1c6281289d67 | 379 | |
| n0tform3 | 8:1c6281289d67 | 380 | /** @defgroup RCC_MCO2_Clock_Source_Prescaler |
| n0tform3 | 8:1c6281289d67 | 381 | * @{ |
| n0tform3 | 8:1c6281289d67 | 382 | */ |
| n0tform3 | 8:1c6281289d67 | 383 | #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) |
| n0tform3 | 8:1c6281289d67 | 384 | #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) |
| n0tform3 | 8:1c6281289d67 | 385 | #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) |
| n0tform3 | 8:1c6281289d67 | 386 | #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) |
| n0tform3 | 8:1c6281289d67 | 387 | #define RCC_MCO2Div_1 ((uint32_t)0x00000000) |
| n0tform3 | 8:1c6281289d67 | 388 | #define RCC_MCO2Div_2 ((uint32_t)0x20000000) |
| n0tform3 | 8:1c6281289d67 | 389 | #define RCC_MCO2Div_3 ((uint32_t)0x28000000) |
| n0tform3 | 8:1c6281289d67 | 390 | #define RCC_MCO2Div_4 ((uint32_t)0x30000000) |
| n0tform3 | 8:1c6281289d67 | 391 | #define RCC_MCO2Div_5 ((uint32_t)0x38000000) |
| n0tform3 | 8:1c6281289d67 | 392 | #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ |
| n0tform3 | 8:1c6281289d67 | 393 | ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) |
| n0tform3 | 8:1c6281289d67 | 394 | |
| n0tform3 | 8:1c6281289d67 | 395 | #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ |
| n0tform3 | 8:1c6281289d67 | 396 | ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ |
| n0tform3 | 8:1c6281289d67 | 397 | ((DIV) == RCC_MCO2Div_5)) |
| n0tform3 | 8:1c6281289d67 | 398 | /** |
| n0tform3 | 8:1c6281289d67 | 399 | * @} |
| n0tform3 | 8:1c6281289d67 | 400 | */ |
| n0tform3 | 8:1c6281289d67 | 401 | |
| n0tform3 | 8:1c6281289d67 | 402 | /** @defgroup RCC_Flag |
| n0tform3 | 8:1c6281289d67 | 403 | * @{ |
| n0tform3 | 8:1c6281289d67 | 404 | */ |
| n0tform3 | 8:1c6281289d67 | 405 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21) |
| n0tform3 | 8:1c6281289d67 | 406 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) |
| n0tform3 | 8:1c6281289d67 | 407 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
| n0tform3 | 8:1c6281289d67 | 408 | #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) |
| n0tform3 | 8:1c6281289d67 | 409 | #define RCC_FLAG_LSERDY ((uint8_t)0x41) |
| n0tform3 | 8:1c6281289d67 | 410 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61) |
| n0tform3 | 8:1c6281289d67 | 411 | #define RCC_FLAG_BORRST ((uint8_t)0x79) |
| n0tform3 | 8:1c6281289d67 | 412 | #define RCC_FLAG_PINRST ((uint8_t)0x7A) |
| n0tform3 | 8:1c6281289d67 | 413 | #define RCC_FLAG_PORRST ((uint8_t)0x7B) |
| n0tform3 | 8:1c6281289d67 | 414 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C) |
| n0tform3 | 8:1c6281289d67 | 415 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
| n0tform3 | 8:1c6281289d67 | 416 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
| n0tform3 | 8:1c6281289d67 | 417 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
| n0tform3 | 8:1c6281289d67 | 418 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| n0tform3 | 8:1c6281289d67 | 419 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
| n0tform3 | 8:1c6281289d67 | 420 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ |
| n0tform3 | 8:1c6281289d67 | 421 | ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ |
| n0tform3 | 8:1c6281289d67 | 422 | ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ |
| n0tform3 | 8:1c6281289d67 | 423 | ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ |
| n0tform3 | 8:1c6281289d67 | 424 | ((FLAG) == RCC_FLAG_PLLI2SRDY)) |
| n0tform3 | 8:1c6281289d67 | 425 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
| n0tform3 | 8:1c6281289d67 | 426 | /** |
| n0tform3 | 8:1c6281289d67 | 427 | * @} |
| n0tform3 | 8:1c6281289d67 | 428 | */ |
| n0tform3 | 8:1c6281289d67 | 429 | |
| n0tform3 | 8:1c6281289d67 | 430 | /** |
| n0tform3 | 8:1c6281289d67 | 431 | * @} |
| n0tform3 | 8:1c6281289d67 | 432 | */ |
| n0tform3 | 8:1c6281289d67 | 433 | |
| n0tform3 | 8:1c6281289d67 | 434 | /* Exported macro ------------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 435 | /* Exported functions --------------------------------------------------------*/ |
| n0tform3 | 8:1c6281289d67 | 436 | |
| n0tform3 | 8:1c6281289d67 | 437 | /* Function used to set the RCC clock configuration to the default reset state */ |
| n0tform3 | 8:1c6281289d67 | 438 | void RCC_DeInit(void); |
| n0tform3 | 8:1c6281289d67 | 439 | |
| n0tform3 | 8:1c6281289d67 | 440 | /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ |
| n0tform3 | 8:1c6281289d67 | 441 | void RCC_HSEConfig(uint8_t RCC_HSE); |
| n0tform3 | 8:1c6281289d67 | 442 | ErrorStatus RCC_WaitForHSEStartUp(void); |
| n0tform3 | 8:1c6281289d67 | 443 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); |
| n0tform3 | 8:1c6281289d67 | 444 | void RCC_HSICmd(FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 445 | void RCC_LSEConfig(uint8_t RCC_LSE); |
| n0tform3 | 8:1c6281289d67 | 446 | void RCC_LSICmd(FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 447 | |
| n0tform3 | 8:1c6281289d67 | 448 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); |
| n0tform3 | 8:1c6281289d67 | 449 | void RCC_PLLCmd(FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 450 | void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); |
| n0tform3 | 8:1c6281289d67 | 451 | void RCC_PLLI2SCmd(FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 452 | |
| n0tform3 | 8:1c6281289d67 | 453 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 454 | void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); |
| n0tform3 | 8:1c6281289d67 | 455 | void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); |
| n0tform3 | 8:1c6281289d67 | 456 | |
| n0tform3 | 8:1c6281289d67 | 457 | /* System, AHB and APB busses clocks configuration functions ******************/ |
| n0tform3 | 8:1c6281289d67 | 458 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); |
| n0tform3 | 8:1c6281289d67 | 459 | uint8_t RCC_GetSYSCLKSource(void); |
| n0tform3 | 8:1c6281289d67 | 460 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK); |
| n0tform3 | 8:1c6281289d67 | 461 | void RCC_PCLK1Config(uint32_t RCC_HCLK); |
| n0tform3 | 8:1c6281289d67 | 462 | void RCC_PCLK2Config(uint32_t RCC_HCLK); |
| n0tform3 | 8:1c6281289d67 | 463 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); |
| n0tform3 | 8:1c6281289d67 | 464 | |
| n0tform3 | 8:1c6281289d67 | 465 | /* Peripheral clocks configuration functions **********************************/ |
| n0tform3 | 8:1c6281289d67 | 466 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); |
| n0tform3 | 8:1c6281289d67 | 467 | void RCC_RTCCLKCmd(FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 468 | void RCC_BackupResetCmd(FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 469 | void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); |
| n0tform3 | 8:1c6281289d67 | 470 | |
| n0tform3 | 8:1c6281289d67 | 471 | void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 472 | void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 473 | void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 474 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 475 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 476 | |
| n0tform3 | 8:1c6281289d67 | 477 | void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 478 | void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 479 | void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 480 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 481 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 482 | |
| n0tform3 | 8:1c6281289d67 | 483 | void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 484 | void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 485 | void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 486 | void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 487 | void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 488 | |
| n0tform3 | 8:1c6281289d67 | 489 | /* Interrupts and flags management functions **********************************/ |
| n0tform3 | 8:1c6281289d67 | 490 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); |
| n0tform3 | 8:1c6281289d67 | 491 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
| n0tform3 | 8:1c6281289d67 | 492 | void RCC_ClearFlag(void); |
| n0tform3 | 8:1c6281289d67 | 493 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
| n0tform3 | 8:1c6281289d67 | 494 | void RCC_ClearITPendingBit(uint8_t RCC_IT); |
| n0tform3 | 8:1c6281289d67 | 495 | |
| n0tform3 | 8:1c6281289d67 | 496 | #ifdef __cplusplus |
| n0tform3 | 8:1c6281289d67 | 497 | } |
| n0tform3 | 8:1c6281289d67 | 498 | #endif |
| n0tform3 | 8:1c6281289d67 | 499 | |
| n0tform3 | 8:1c6281289d67 | 500 | #endif /* __STM32F4xx_RCC_H */ |
| n0tform3 | 8:1c6281289d67 | 501 | |
| n0tform3 | 8:1c6281289d67 | 502 | /** |
| n0tform3 | 8:1c6281289d67 | 503 | * @} |
| n0tform3 | 8:1c6281289d67 | 504 | */ |
| n0tform3 | 8:1c6281289d67 | 505 | |
| n0tform3 | 8:1c6281289d67 | 506 | /** |
| n0tform3 | 8:1c6281289d67 | 507 | * @} |
| n0tform3 | 8:1c6281289d67 | 508 | */ |
| n0tform3 | 8:1c6281289d67 | 509 | |
| n0tform3 | 8:1c6281289d67 | 510 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
| n0tform3 | 8:1c6281289d67 | 511 |