Murilo Pontes
cc1101 driver library
Dependents: kl25z-tinyshell-demo
cc1101_regs.h@1:ee6686ffcad0, 2014-03-09 (annotated)
- Committer:
- murilopontes
- Date:
- Sun Mar 09 18:39:56 2014 +0000
- Revision:
- 1:ee6686ffcad0
update regs
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| murilopontes | 1:ee6686ffcad0 | 1 | /* |
| murilopontes | 1:ee6686ffcad0 | 2 | * CC1101_REGS.h |
| murilopontes | 1:ee6686ffcad0 | 3 | * |
| murilopontes | 1:ee6686ffcad0 | 4 | * Created on: 07/02/2014 |
| murilopontes | 1:ee6686ffcad0 | 5 | * Author: mpontes <murilopontes@gmail.com> |
| murilopontes | 1:ee6686ffcad0 | 6 | */ |
| murilopontes | 1:ee6686ffcad0 | 7 | |
| murilopontes | 1:ee6686ffcad0 | 8 | #ifndef CC1101_BOARD_REGS_H_ |
| murilopontes | 1:ee6686ffcad0 | 9 | #define CC1101_BOARD_REGS_H_ |
| murilopontes | 1:ee6686ffcad0 | 10 | |
| murilopontes | 1:ee6686ffcad0 | 11 | #define CC1101_DUMMY_BYTE 0xDB |
| murilopontes | 1:ee6686ffcad0 | 12 | |
| murilopontes | 1:ee6686ffcad0 | 13 | #define CC1101_WRITE_BYTE 0x00 |
| murilopontes | 1:ee6686ffcad0 | 14 | #define CC1101_WRITE_BURST 0x40 |
| murilopontes | 1:ee6686ffcad0 | 15 | #define CC1101_READ_BYTE 0x80 |
| murilopontes | 1:ee6686ffcad0 | 16 | #define CC1101_READ_BURST 0xC0 |
| murilopontes | 1:ee6686ffcad0 | 17 | |
| murilopontes | 1:ee6686ffcad0 | 18 | |
| murilopontes | 1:ee6686ffcad0 | 19 | /* configuration registers */ |
| murilopontes | 1:ee6686ffcad0 | 20 | #define CC1101_IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */ |
| murilopontes | 1:ee6686ffcad0 | 21 | #define CC1101_IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */ |
| murilopontes | 1:ee6686ffcad0 | 22 | #define CC1101_IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */ |
| murilopontes | 1:ee6686ffcad0 | 23 | #define CC1101_FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */ |
| murilopontes | 1:ee6686ffcad0 | 24 | #define CC1101_SYNC1 0x04 /* SYNC1 - Sync word, high byte */ |
| murilopontes | 1:ee6686ffcad0 | 25 | #define CC1101_SYNC0 0x05 /* SYNC0 - Sync word, low byte */ |
| murilopontes | 1:ee6686ffcad0 | 26 | #define CC1101_PKTLEN 0x06 /* PKTLEN - Packet length */ |
| murilopontes | 1:ee6686ffcad0 | 27 | #define CC1101_PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */ |
| murilopontes | 1:ee6686ffcad0 | 28 | #define CC1101_PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */ |
| murilopontes | 1:ee6686ffcad0 | 29 | #define CC1101_ADDR 0x09 /* ADDR - Device address */ |
| murilopontes | 1:ee6686ffcad0 | 30 | #define CC1101_CHANNR 0x0A /* CHANNR - Channel number */ |
| murilopontes | 1:ee6686ffcad0 | 31 | #define CC1101_FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */ |
| murilopontes | 1:ee6686ffcad0 | 32 | #define CC1101_FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */ |
| murilopontes | 1:ee6686ffcad0 | 33 | #define CC1101_FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */ |
| murilopontes | 1:ee6686ffcad0 | 34 | #define CC1101_FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */ |
| murilopontes | 1:ee6686ffcad0 | 35 | #define CC1101_FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */ |
| murilopontes | 1:ee6686ffcad0 | 36 | #define CC1101_MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */ |
| murilopontes | 1:ee6686ffcad0 | 37 | #define CC1101_MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */ |
| murilopontes | 1:ee6686ffcad0 | 38 | #define CC1101_MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */ |
| murilopontes | 1:ee6686ffcad0 | 39 | #define CC1101_MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */ |
| murilopontes | 1:ee6686ffcad0 | 40 | #define CC1101_MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */ |
| murilopontes | 1:ee6686ffcad0 | 41 | #define CC1101_DEVIATN 0x15 /* DEVIATN - Modem deviation setting */ |
| murilopontes | 1:ee6686ffcad0 | 42 | #define CC1101_MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */ |
| murilopontes | 1:ee6686ffcad0 | 43 | #define CC1101_MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */ |
| murilopontes | 1:ee6686ffcad0 | 44 | #define CC1101_MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */ |
| murilopontes | 1:ee6686ffcad0 | 45 | #define CC1101_FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */ |
| murilopontes | 1:ee6686ffcad0 | 46 | #define CC1101_BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */ |
| murilopontes | 1:ee6686ffcad0 | 47 | #define CC1101_AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */ |
| murilopontes | 1:ee6686ffcad0 | 48 | #define CC1101_AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */ |
| murilopontes | 1:ee6686ffcad0 | 49 | #define CC1101_AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */ |
| murilopontes | 1:ee6686ffcad0 | 50 | #define CC1101_WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */ |
| murilopontes | 1:ee6686ffcad0 | 51 | #define CC1101_WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */ |
| murilopontes | 1:ee6686ffcad0 | 52 | #define CC1101_WORCTRL 0x20 /* WORCTRL - Wake On Radio control */ |
| murilopontes | 1:ee6686ffcad0 | 53 | #define CC1101_FREND1 0x21 /* FREND1 - Front end RX configuration */ |
| murilopontes | 1:ee6686ffcad0 | 54 | #define CC1101_FREND0 0x22 /* FREDN0 - Front end TX configuration */ |
| murilopontes | 1:ee6686ffcad0 | 55 | #define CC1101_FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */ |
| murilopontes | 1:ee6686ffcad0 | 56 | #define CC1101_FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */ |
| murilopontes | 1:ee6686ffcad0 | 57 | #define CC1101_FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */ |
| murilopontes | 1:ee6686ffcad0 | 58 | #define CC1101_FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */ |
| murilopontes | 1:ee6686ffcad0 | 59 | #define CC1101_RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */ |
| murilopontes | 1:ee6686ffcad0 | 60 | #define CC1101_RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */ |
| murilopontes | 1:ee6686ffcad0 | 61 | #define CC1101_FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */ |
| murilopontes | 1:ee6686ffcad0 | 62 | #define CC1101_PTEST 0x2A /* PTEST - Production test */ |
| murilopontes | 1:ee6686ffcad0 | 63 | #define CC1101_AGCTEST 0x2B /* AGCTEST - AGC test */ |
| murilopontes | 1:ee6686ffcad0 | 64 | #define CC1101_TEST2 0x2C /* TEST2 - Various test settings */ |
| murilopontes | 1:ee6686ffcad0 | 65 | #define CC1101_TEST1 0x2D /* TEST1 - Various test settings */ |
| murilopontes | 1:ee6686ffcad0 | 66 | #define CC1101_TEST0 0x2E /* TEST0 - Various test settings */ |
| murilopontes | 1:ee6686ffcad0 | 67 | |
| murilopontes | 1:ee6686ffcad0 | 68 | /* command strobe registers */ |
| murilopontes | 1:ee6686ffcad0 | 69 | #define CC1101_SRES 0x30 /* SRES - Reset chip. */ |
| murilopontes | 1:ee6686ffcad0 | 70 | #define CC1101_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */ |
| murilopontes | 1:ee6686ffcad0 | 71 | #define CC1101_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */ |
| murilopontes | 1:ee6686ffcad0 | 72 | #define CC1101_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */ |
| murilopontes | 1:ee6686ffcad0 | 73 | #define CC1101_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */ |
| murilopontes | 1:ee6686ffcad0 | 74 | #define CC1101_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */ |
| murilopontes | 1:ee6686ffcad0 | 75 | #define CC1101_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */ |
| murilopontes | 1:ee6686ffcad0 | 76 | #define CC1101_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */ |
| murilopontes | 1:ee6686ffcad0 | 77 | #define CC1101_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */ |
| murilopontes | 1:ee6686ffcad0 | 78 | #define CC1101_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */ |
| murilopontes | 1:ee6686ffcad0 | 79 | #define CC1101_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */ |
| murilopontes | 1:ee6686ffcad0 | 80 | #define CC1101_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */ |
| murilopontes | 1:ee6686ffcad0 | 81 | #define CC1101_SWORRST 0x3C /* SWORRST - Reset real time clock. */ |
| murilopontes | 1:ee6686ffcad0 | 82 | #define CC1101_SNOP 0x3D /* SNOP - No operation. Returns status byte. */ |
| murilopontes | 1:ee6686ffcad0 | 83 | |
| murilopontes | 1:ee6686ffcad0 | 84 | /* status registers */ |
| murilopontes | 1:ee6686ffcad0 | 85 | #define CC1101_PARTNUM 0x30 /* PARTNUM - Chip ID */ |
| murilopontes | 1:ee6686ffcad0 | 86 | #define CC1101_VERSION 0x31 /* VERSION - Chip ID */ |
| murilopontes | 1:ee6686ffcad0 | 87 | #define CC1101_FREQEST 0x32 /* FREQEST – Frequency Offset Estimate from demodulator */ |
| murilopontes | 1:ee6686ffcad0 | 88 | #define CC1101_LQI 0x33 /* LQI – Demodulator estimate for Link Quality */ |
| murilopontes | 1:ee6686ffcad0 | 89 | #define CC1101_RSSI 0x34 /* RSSI – Received signal strength indication */ |
| murilopontes | 1:ee6686ffcad0 | 90 | #define CC1101_MARCSTATE 0x35 /* MARCSTATE – Main Radio Control State Machine state */ |
| murilopontes | 1:ee6686ffcad0 | 91 | #define CC1101_WORTIME1 0x36 /* WORTIME1 – High byte of WOR time */ |
| murilopontes | 1:ee6686ffcad0 | 92 | #define CC1101_WORTIME0 0x37 /* WORTIME0 – Low byte of WOR time */ |
| murilopontes | 1:ee6686ffcad0 | 93 | #define CC1101_PKTSTATUS 0x38 /* PKTSTATUS – Current GDOx status and packet status */ |
| murilopontes | 1:ee6686ffcad0 | 94 | #define CC1101_VCO_VC_DAC 0x39 /* VCO_VC_DAC – Current setting from PLL calibration module */ |
| murilopontes | 1:ee6686ffcad0 | 95 | #define CC1101_TXBYTES 0x3a /* TXBYTES – Underflow and number of bytes */ |
| murilopontes | 1:ee6686ffcad0 | 96 | #define CC1101_RXBYTES 0x3b /* RXBYTES – Overflow and number of bytes */ |
| murilopontes | 1:ee6686ffcad0 | 97 | #define CC1101_RCCTRL1_STATUS 0x3c /* RCCTRL1_STATUS – Last RC Oscillator Calibration Result */ |
| murilopontes | 1:ee6686ffcad0 | 98 | #define CC1101_RCCTRL0_STATUS 0x3d /* RCCTRL0_STATUS – Last RC Oscillator Calibration Result */ |
| murilopontes | 1:ee6686ffcad0 | 99 | |
| murilopontes | 1:ee6686ffcad0 | 100 | |
| murilopontes | 1:ee6686ffcad0 | 101 | /* burst write registers */ |
| murilopontes | 1:ee6686ffcad0 | 102 | #define CC1101_PA_TABLE0 0x3E /* PA_TABLE0 - PA control settings table */ |
| murilopontes | 1:ee6686ffcad0 | 103 | #define CC1101_TXFIFO 0x3F /* TXFIFO - Transmit FIFO */ |
| murilopontes | 1:ee6686ffcad0 | 104 | #define CC1101_RXFIFO 0x3F /* RXFIFO - Receive FIFO */ |
| murilopontes | 1:ee6686ffcad0 | 105 | |
| murilopontes | 1:ee6686ffcad0 | 106 | |
| murilopontes | 1:ee6686ffcad0 | 107 | |
| murilopontes | 1:ee6686ffcad0 | 108 | |
| murilopontes | 1:ee6686ffcad0 | 109 | |
| murilopontes | 1:ee6686ffcad0 | 110 | |
| murilopontes | 1:ee6686ffcad0 | 111 | |
| murilopontes | 1:ee6686ffcad0 | 112 | //----------------------------------------------------------------------------- |
| murilopontes | 1:ee6686ffcad0 | 113 | // CC1101 STATE MACHINE |
| murilopontes | 1:ee6686ffcad0 | 114 | //------------------------------------------------------------------------------ |
| murilopontes | 1:ee6686ffcad0 | 115 | #define CC1101_MARCSTATE_SLEEP 0x00 |
| murilopontes | 1:ee6686ffcad0 | 116 | #define CC1101_MARCSTATE_IDLE 0x01 |
| murilopontes | 1:ee6686ffcad0 | 117 | #define CC1101_MARCSTATE_XOFF 0x02 |
| murilopontes | 1:ee6686ffcad0 | 118 | #define CC1101_MARCSTATE_VCOON_MC 0x03 |
| murilopontes | 1:ee6686ffcad0 | 119 | #define CC1101_MARCSTATE_REGON_MC 0x04 |
| murilopontes | 1:ee6686ffcad0 | 120 | #define CC1101_MARCSTATE_MANCAL 0x05 |
| murilopontes | 1:ee6686ffcad0 | 121 | #define CC1101_MARCSTATE_VCOON 0x06 |
| murilopontes | 1:ee6686ffcad0 | 122 | #define CC1101_MARCSTATE_REGON 0x07 |
| murilopontes | 1:ee6686ffcad0 | 123 | #define CC1101_MARCSTATE_STARTCAL 0x08 |
| murilopontes | 1:ee6686ffcad0 | 124 | #define CC1101_MARCSTATE_BWBOOST 0x09 |
| murilopontes | 1:ee6686ffcad0 | 125 | #define CC1101_MARCSTATE_FS_LOCK 0x0a |
| murilopontes | 1:ee6686ffcad0 | 126 | #define CC1101_MARCSTATE_IFADCON 0x0b |
| murilopontes | 1:ee6686ffcad0 | 127 | #define CC1101_MARCSTATE_ENDCAL 0x0c |
| murilopontes | 1:ee6686ffcad0 | 128 | #define CC1101_MARCSTATE_RX 0x0d |
| murilopontes | 1:ee6686ffcad0 | 129 | #define CC1101_MARCSTATE_RX_END 0x0e |
| murilopontes | 1:ee6686ffcad0 | 130 | #define CC1101_MARCSTATE_RX_RST 0x0f |
| murilopontes | 1:ee6686ffcad0 | 131 | #define CC1101_MARCSTATE_TXRX_SWITCH 0x10 |
| murilopontes | 1:ee6686ffcad0 | 132 | #define CC1101_MARCSTATE_RXFIFO_OVERFLOW 0x11 |
| murilopontes | 1:ee6686ffcad0 | 133 | #define CC1101_MARCSTATE_FSTXON 0x12 |
| murilopontes | 1:ee6686ffcad0 | 134 | #define CC1101_MARCSTATE_TX 0x13 |
| murilopontes | 1:ee6686ffcad0 | 135 | #define CC1101_MARCSTATE_TX_END 0x14 |
| murilopontes | 1:ee6686ffcad0 | 136 | #define CC1101_MARCSTATE_RXTX_SWITCH 0x15 |
| murilopontes | 1:ee6686ffcad0 | 137 | #define CC1101_MARCSTATE_TXFIFO_UNDERFLOW 0x16 |
| murilopontes | 1:ee6686ffcad0 | 138 | |
| murilopontes | 1:ee6686ffcad0 | 139 | //-------------------------------------------- |
| murilopontes | 1:ee6686ffcad0 | 140 | // CC1101 GDO config |
| murilopontes | 1:ee6686ffcad0 | 141 | //-------------------------------------------- |
| murilopontes | 1:ee6686ffcad0 | 142 | |
| murilopontes | 1:ee6686ffcad0 | 143 | |
| murilopontes | 1:ee6686ffcad0 | 144 | #define CC1101_GDO_RX_ASSERT_WHEN_FILLED_OR_ABOVE_THRESHOLD 0x00 |
| murilopontes | 1:ee6686ffcad0 | 145 | #define CC1101_GDO_RX_ASSERT_WHEN_FILLED_OR_ABOVE_THRESHOLD_OR_END_PACKET 0x01 |
| murilopontes | 1:ee6686ffcad0 | 146 | #define CC1101_GDO_TX_ASSERT_WHEN_FILLED_OR_ABOVE_THRESHOLD 0x02 |
| murilopontes | 1:ee6686ffcad0 | 147 | #define CC1101_GDO_TX_ASSERT_WHEN_FULL 0x03 |
| murilopontes | 1:ee6686ffcad0 | 148 | #define CC1101_GDO_RX_ASSERT_ON_OVERFLOW 0x04 |
| murilopontes | 1:ee6686ffcad0 | 149 | #define CC1101_GDO_TX_ASSERT_ON_UNDERFLOW 0x05 |
| murilopontes | 1:ee6686ffcad0 | 150 | #define CC1101_GDO_ASSERT_ON_SYNC_WORD 0x06 |
| murilopontes | 1:ee6686ffcad0 | 151 | #define CC1101_GDO_ASSERT_ON_CRC_OK 0x07 |
| murilopontes | 1:ee6686ffcad0 | 152 | #define CC1101_GDO_ASSERT_ON_PQI_ABOVE_PQT 0x08 |
| murilopontes | 1:ee6686ffcad0 | 153 | #define CC1101_GDO_CCA_ASSERT_WHEN_RSSI_ABOVE_THRESHOLD 0x09 |
| murilopontes | 1:ee6686ffcad0 | 154 | #define CC1101_GDO_LOCK_DETECTOR_OUTPUT 0x0a |
| murilopontes | 1:ee6686ffcad0 | 155 | #define CC1101_GDO_SERIAL_CLOCK 0x0b |
| murilopontes | 1:ee6686ffcad0 | 156 | #define CC1101_GDO_SERIAL_SYNCHRONOUS_DATA_OUTPUT 0x0c |
| murilopontes | 1:ee6686ffcad0 | 157 | #define CC1101_GDO_SERIA_DATA_OUTPUT 0x0d |
| murilopontes | 1:ee6686ffcad0 | 158 | #define CC1101_GDO_CARRIER_SENSE_HIGH_IF_RSSI_ABOVE_THRESHOLD 0x0e |
| murilopontes | 1:ee6686ffcad0 | 159 | #define CC1101_GDO_CRC_OK 0x0f |
| murilopontes | 1:ee6686ffcad0 | 160 | #define CC1101_GDO_RX_HARD_DATA_1 0x16 |
| murilopontes | 1:ee6686ffcad0 | 161 | #define CC1101_GDO_RX_HARD_DATA_0 0x17 |
| murilopontes | 1:ee6686ffcad0 | 162 | #define CC1101_GDO_PA_PD 0x1b |
| murilopontes | 1:ee6686ffcad0 | 163 | #define CC1101_GDO_LNA_PD 0x1c |
| murilopontes | 1:ee6686ffcad0 | 164 | #define CC1101_GDO_RX_SYMBOL_TICK 0x1d |
| murilopontes | 1:ee6686ffcad0 | 165 | #define CC1101_GDO_WOR_1 0x24 |
| murilopontes | 1:ee6686ffcad0 | 166 | #define CC1101_GDO_WOR_0 0x25 |
| murilopontes | 1:ee6686ffcad0 | 167 | #define CC1101_GDO_CLK_32K 0x27 |
| murilopontes | 1:ee6686ffcad0 | 168 | #define CC1101_GDO_CHIP_RDYN 0x29 |
| murilopontes | 1:ee6686ffcad0 | 169 | #define CC1101_GDO_XOSC_STABLE 0x2b |
| murilopontes | 1:ee6686ffcad0 | 170 | #define CC1101_GDO_GDO0_Z_EN_N 0x2d |
| murilopontes | 1:ee6686ffcad0 | 171 | #define CC1101_GDO_HIGH_IMPEDANCE 0x2e |
| murilopontes | 1:ee6686ffcad0 | 172 | #define CC1101_GDO_HW_0 0x2f |
| murilopontes | 1:ee6686ffcad0 | 173 | #define CC1101_GDO_CLK_XOSC1 0x30 |
| murilopontes | 1:ee6686ffcad0 | 174 | #define CC1101_GDO_CLK_XOSC15 0x31 |
| murilopontes | 1:ee6686ffcad0 | 175 | #define CC1101_GDO_CLK_XOSC2 0x32 |
| murilopontes | 1:ee6686ffcad0 | 176 | #define CC1101_GDO_CLK_XOSC3 0x33 |
| murilopontes | 1:ee6686ffcad0 | 177 | #define CC1101_GDO_CLK_XOSC4 0x34 |
| murilopontes | 1:ee6686ffcad0 | 178 | #define CC1101_GDO_CLK_XOSC6 0x35 |
| murilopontes | 1:ee6686ffcad0 | 179 | #define CC1101_GDO_CLK_XOSC8 0x36 |
| murilopontes | 1:ee6686ffcad0 | 180 | #define CC1101_GDO_CLK_XOSC12 0x37 |
| murilopontes | 1:ee6686ffcad0 | 181 | #define CC1101_GDO_CLK_XOSC16 0x38 |
| murilopontes | 1:ee6686ffcad0 | 182 | #define CC1101_GDO_CLK_XOSC24 0x39 |
| murilopontes | 1:ee6686ffcad0 | 183 | #define CC1101_GDO_CLK_XOSC32 0x3a |
| murilopontes | 1:ee6686ffcad0 | 184 | #define CC1101_GDO_CLK_XOSC48 0x3b |
| murilopontes | 1:ee6686ffcad0 | 185 | #define CC1101_GDO_CLK_XOSC64 0x3c |
| murilopontes | 1:ee6686ffcad0 | 186 | #define CC1101_GDO_CLK_XOSC96 0x3d |
| murilopontes | 1:ee6686ffcad0 | 187 | #define CC1101_GDO_CLK_XOSC128 0x3e |
| murilopontes | 1:ee6686ffcad0 | 188 | #define CC1101_GDO_CLK_XOSC192 0x3f |
| murilopontes | 1:ee6686ffcad0 | 189 | |
| murilopontes | 1:ee6686ffcad0 | 190 | |
| murilopontes | 1:ee6686ffcad0 | 191 | |
| murilopontes | 1:ee6686ffcad0 | 192 | |
| murilopontes | 1:ee6686ffcad0 | 193 | #endif /* CC1101_BOARD_REGS_H_ */ |