Muhammad Imran Shahidan / Mbed 2 deprecated IBM_RFID

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependencies:   C12832 EthernetInterface IBMIoTClientEthernetExample LM75B MMA7660 MQTT iBMrfid mbed-rtos mbed

Fork of IBMIoTClientEthernetExample by IBM Watson IoT

EthernetInterface/lwip-eth/arch/TARGET_NXP/lpc17xx_emac.h@6:37b6d0d56190, 2014-08-20 (annotated)

Committer:
samdanbury
Date:
Wed Aug 20 12:45:14 2014 +0000
Revision:
6:37b6d0d56190
Code completely changed to improve the structure, flow and memory usage of the application

Who changed what in which revision?

UserRevisionLine numberNew contents of line
samdanbury 6:37b6d0d56190 1 /**********************************************************************
samdanbury 6:37b6d0d56190 2 * $Id$ lpc17xx_emac.h 2010-05-21
samdanbury 6:37b6d0d56190 3 *//**
samdanbury 6:37b6d0d56190 4 * @file lpc17xx_emac.h
samdanbury 6:37b6d0d56190 5 * @brief Contains all macro definitions and function prototypes
samdanbury 6:37b6d0d56190 6 * support for Ethernet MAC firmware library on LPC17xx
samdanbury 6:37b6d0d56190 7 * @version 2.0
samdanbury 6:37b6d0d56190 8 * @date 21. May. 2010
samdanbury 6:37b6d0d56190 9 * @author NXP MCU SW Application Team
samdanbury 6:37b6d0d56190 10 *
samdanbury 6:37b6d0d56190 11 * Copyright(C) 2010, NXP Semiconductor
samdanbury 6:37b6d0d56190 12 * All rights reserved.
samdanbury 6:37b6d0d56190 13 *
samdanbury 6:37b6d0d56190 14 ***********************************************************************
samdanbury 6:37b6d0d56190 15 * Software that is described herein is for illustrative purposes only
samdanbury 6:37b6d0d56190 16 * which provides customers with programming information regarding the
samdanbury 6:37b6d0d56190 17 * products. This software is supplied "AS IS" without any warranties.
samdanbury 6:37b6d0d56190 18 * NXP Semiconductors assumes no responsibility or liability for the
samdanbury 6:37b6d0d56190 19 * use of the software, conveys no license or title under any patent,
samdanbury 6:37b6d0d56190 20 * copyright, or mask work right to the product. NXP Semiconductors
samdanbury 6:37b6d0d56190 21 * reserves the right to make changes in the software without
samdanbury 6:37b6d0d56190 22 * notification. NXP Semiconductors also make no representation or
samdanbury 6:37b6d0d56190 23 * warranty that such application will be suitable for the specified
samdanbury 6:37b6d0d56190 24 * use without further testing or modification.
samdanbury 6:37b6d0d56190 25 **********************************************************************/
samdanbury 6:37b6d0d56190 26
samdanbury 6:37b6d0d56190 27 /* Peripheral group ----------------------------------------------------------- */
samdanbury 6:37b6d0d56190 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
samdanbury 6:37b6d0d56190 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
samdanbury 6:37b6d0d56190 30 * @{
samdanbury 6:37b6d0d56190 31 */
samdanbury 6:37b6d0d56190 32
samdanbury 6:37b6d0d56190 33 #ifndef LPC17XX_EMAC_H_
samdanbury 6:37b6d0d56190 34 #define LPC17XX_EMAC_H_
samdanbury 6:37b6d0d56190 35
samdanbury 6:37b6d0d56190 36 /* Includes ------------------------------------------------------------------- */
samdanbury 6:37b6d0d56190 37 #include "cmsis.h"
samdanbury 6:37b6d0d56190 38
samdanbury 6:37b6d0d56190 39 #ifdef __cplusplus
samdanbury 6:37b6d0d56190 40 extern "C"
samdanbury 6:37b6d0d56190 41 {
samdanbury 6:37b6d0d56190 42 #endif
samdanbury 6:37b6d0d56190 43
samdanbury 6:37b6d0d56190 44 #define MCB_LPC_1768
samdanbury 6:37b6d0d56190 45 //#define IAR_LPC_1768
samdanbury 6:37b6d0d56190 46
samdanbury 6:37b6d0d56190 47 /* Public Macros -------------------------------------------------------------- */
samdanbury 6:37b6d0d56190 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
samdanbury 6:37b6d0d56190 49 * @{
samdanbury 6:37b6d0d56190 50 */
samdanbury 6:37b6d0d56190 51
samdanbury 6:37b6d0d56190 52
samdanbury 6:37b6d0d56190 53 /* EMAC PHY status type definitions */
samdanbury 6:37b6d0d56190 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
samdanbury 6:37b6d0d56190 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
samdanbury 6:37b6d0d56190 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
samdanbury 6:37b6d0d56190 57
samdanbury 6:37b6d0d56190 58 /* EMAC PHY device Speed definitions */
samdanbury 6:37b6d0d56190 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
samdanbury 6:37b6d0d56190 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
samdanbury 6:37b6d0d56190 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
samdanbury 6:37b6d0d56190 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
samdanbury 6:37b6d0d56190 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
samdanbury 6:37b6d0d56190 64
samdanbury 6:37b6d0d56190 65 /**
samdanbury 6:37b6d0d56190 66 * @}
samdanbury 6:37b6d0d56190 67 */
samdanbury 6:37b6d0d56190 68 /* Private Macros ------------------------------------------------------------- */
samdanbury 6:37b6d0d56190 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
samdanbury 6:37b6d0d56190 70 * @{
samdanbury 6:37b6d0d56190 71 */
samdanbury 6:37b6d0d56190 72
samdanbury 6:37b6d0d56190 73
samdanbury 6:37b6d0d56190 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
samdanbury 6:37b6d0d56190 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
samdanbury 6:37b6d0d56190 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
samdanbury 6:37b6d0d56190 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
samdanbury 6:37b6d0d56190 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
samdanbury 6:37b6d0d56190 79
samdanbury 6:37b6d0d56190 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
samdanbury 6:37b6d0d56190 81 /*********************************************************************//**
samdanbury 6:37b6d0d56190 82 * Macro defines for MAC Configuration Register 1
samdanbury 6:37b6d0d56190 83 **********************************************************************/
samdanbury 6:37b6d0d56190 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
samdanbury 6:37b6d0d56190 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
samdanbury 6:37b6d0d56190 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
samdanbury 6:37b6d0d56190 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
samdanbury 6:37b6d0d56190 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
samdanbury 6:37b6d0d56190 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
samdanbury 6:37b6d0d56190 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
samdanbury 6:37b6d0d56190 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
samdanbury 6:37b6d0d56190 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
samdanbury 6:37b6d0d56190 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
samdanbury 6:37b6d0d56190 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
samdanbury 6:37b6d0d56190 95
samdanbury 6:37b6d0d56190 96 /*********************************************************************//**
samdanbury 6:37b6d0d56190 97 * Macro defines for MAC Configuration Register 2
samdanbury 6:37b6d0d56190 98 **********************************************************************/
samdanbury 6:37b6d0d56190 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
samdanbury 6:37b6d0d56190 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
samdanbury 6:37b6d0d56190 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
samdanbury 6:37b6d0d56190 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
samdanbury 6:37b6d0d56190 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
samdanbury 6:37b6d0d56190 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
samdanbury 6:37b6d0d56190 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
samdanbury 6:37b6d0d56190 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
samdanbury 6:37b6d0d56190 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
samdanbury 6:37b6d0d56190 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
samdanbury 6:37b6d0d56190 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
samdanbury 6:37b6d0d56190 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
samdanbury 6:37b6d0d56190 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
samdanbury 6:37b6d0d56190 112
samdanbury 6:37b6d0d56190 113 /*********************************************************************//**
samdanbury 6:37b6d0d56190 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
samdanbury 6:37b6d0d56190 115 **********************************************************************/
samdanbury 6:37b6d0d56190 116 /** Programmable field representing the nibble time offset of the minimum possible period
samdanbury 6:37b6d0d56190 117 * between the end of any transmitted packet to the beginning of the next */
samdanbury 6:37b6d0d56190 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
samdanbury 6:37b6d0d56190 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
samdanbury 6:37b6d0d56190 120 * offset of the minimum possible period between the end of any transmitted packet to the
samdanbury 6:37b6d0d56190 121 * beginning of the next */
samdanbury 6:37b6d0d56190 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
samdanbury 6:37b6d0d56190 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
samdanbury 6:37b6d0d56190 124 * offset of the minimum possible period between the end of any transmitted packet to the
samdanbury 6:37b6d0d56190 125 * beginning of the next */
samdanbury 6:37b6d0d56190 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
samdanbury 6:37b6d0d56190 127
samdanbury 6:37b6d0d56190 128 /*********************************************************************//**
samdanbury 6:37b6d0d56190 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
samdanbury 6:37b6d0d56190 130 **********************************************************************/
samdanbury 6:37b6d0d56190 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
samdanbury 6:37b6d0d56190 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
samdanbury 6:37b6d0d56190 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
samdanbury 6:37b6d0d56190 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
samdanbury 6:37b6d0d56190 135 /** Programmable field representing the optional carrierSense window referenced in
samdanbury 6:37b6d0d56190 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
samdanbury 6:37b6d0d56190 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
samdanbury 6:37b6d0d56190 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
samdanbury 6:37b6d0d56190 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
samdanbury 6:37b6d0d56190 140
samdanbury 6:37b6d0d56190 141 /*********************************************************************//**
samdanbury 6:37b6d0d56190 142 * Macro defines for Collision Window/Retry Register
samdanbury 6:37b6d0d56190 143 **********************************************************************/
samdanbury 6:37b6d0d56190 144 /** Programmable field specifying the number of retransmission attempts following a collision before
samdanbury 6:37b6d0d56190 145 * aborting the packet due to excessive collisions */
samdanbury 6:37b6d0d56190 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
samdanbury 6:37b6d0d56190 147 /** Programmable field representing the slot time or collision window during which collisions occur
samdanbury 6:37b6d0d56190 148 * in properly configured networks */
samdanbury 6:37b6d0d56190 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
samdanbury 6:37b6d0d56190 150 /** Default value for Collision Window / Retry register */
samdanbury 6:37b6d0d56190 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
samdanbury 6:37b6d0d56190 152
samdanbury 6:37b6d0d56190 153 /*********************************************************************//**
samdanbury 6:37b6d0d56190 154 * Macro defines for Maximum Frame Register
samdanbury 6:37b6d0d56190 155 **********************************************************************/
samdanbury 6:37b6d0d56190 156 /** Represents a maximum receive frame of 1536 octets */
samdanbury 6:37b6d0d56190 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
samdanbury 6:37b6d0d56190 158
samdanbury 6:37b6d0d56190 159 /*********************************************************************//**
samdanbury 6:37b6d0d56190 160 * Macro defines for PHY Support Register
samdanbury 6:37b6d0d56190 161 **********************************************************************/
samdanbury 6:37b6d0d56190 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
samdanbury 6:37b6d0d56190 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
samdanbury 6:37b6d0d56190 164
samdanbury 6:37b6d0d56190 165 /*********************************************************************//**
samdanbury 6:37b6d0d56190 166 * Macro defines for Test Register
samdanbury 6:37b6d0d56190 167 **********************************************************************/
samdanbury 6:37b6d0d56190 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
samdanbury 6:37b6d0d56190 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
samdanbury 6:37b6d0d56190 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
samdanbury 6:37b6d0d56190 171
samdanbury 6:37b6d0d56190 172 /*********************************************************************//**
samdanbury 6:37b6d0d56190 173 * Macro defines for MII Management Configuration Register
samdanbury 6:37b6d0d56190 174 **********************************************************************/
samdanbury 6:37b6d0d56190 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
samdanbury 6:37b6d0d56190 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
samdanbury 6:37b6d0d56190 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
samdanbury 6:37b6d0d56190 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
samdanbury 6:37b6d0d56190 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
samdanbury 6:37b6d0d56190 180
samdanbury 6:37b6d0d56190 181 /*********************************************************************//**
samdanbury 6:37b6d0d56190 182 * Macro defines for MII Management Command Register
samdanbury 6:37b6d0d56190 183 **********************************************************************/
samdanbury 6:37b6d0d56190 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
samdanbury 6:37b6d0d56190 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
samdanbury 6:37b6d0d56190 186
samdanbury 6:37b6d0d56190 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
samdanbury 6:37b6d0d56190 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
samdanbury 6:37b6d0d56190 189
samdanbury 6:37b6d0d56190 190 /*********************************************************************//**
samdanbury 6:37b6d0d56190 191 * Macro defines for MII Management Address Register
samdanbury 6:37b6d0d56190 192 **********************************************************************/
samdanbury 6:37b6d0d56190 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
samdanbury 6:37b6d0d56190 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
samdanbury 6:37b6d0d56190 195
samdanbury 6:37b6d0d56190 196 /*********************************************************************//**
samdanbury 6:37b6d0d56190 197 * Macro defines for MII Management Write Data Register
samdanbury 6:37b6d0d56190 198 **********************************************************************/
samdanbury 6:37b6d0d56190 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
samdanbury 6:37b6d0d56190 200
samdanbury 6:37b6d0d56190 201 /*********************************************************************//**
samdanbury 6:37b6d0d56190 202 * Macro defines for MII Management Read Data Register
samdanbury 6:37b6d0d56190 203 **********************************************************************/
samdanbury 6:37b6d0d56190 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
samdanbury 6:37b6d0d56190 205
samdanbury 6:37b6d0d56190 206 /*********************************************************************//**
samdanbury 6:37b6d0d56190 207 * Macro defines for MII Management Indicators Register
samdanbury 6:37b6d0d56190 208 **********************************************************************/
samdanbury 6:37b6d0d56190 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
samdanbury 6:37b6d0d56190 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
samdanbury 6:37b6d0d56190 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
samdanbury 6:37b6d0d56190 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
samdanbury 6:37b6d0d56190 213
samdanbury 6:37b6d0d56190 214 /* Station Address 0 Register */
samdanbury 6:37b6d0d56190 215 /* Station Address 1 Register */
samdanbury 6:37b6d0d56190 216 /* Station Address 2 Register */
samdanbury 6:37b6d0d56190 217
samdanbury 6:37b6d0d56190 218
samdanbury 6:37b6d0d56190 219 /* Control register definitions --------------------------------------------------------------------------- */
samdanbury 6:37b6d0d56190 220 /*********************************************************************//**
samdanbury 6:37b6d0d56190 221 * Macro defines for Command Register
samdanbury 6:37b6d0d56190 222 **********************************************************************/
samdanbury 6:37b6d0d56190 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
samdanbury 6:37b6d0d56190 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
samdanbury 6:37b6d0d56190 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
samdanbury 6:37b6d0d56190 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
samdanbury 6:37b6d0d56190 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
samdanbury 6:37b6d0d56190 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
samdanbury 6:37b6d0d56190 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
samdanbury 6:37b6d0d56190 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
samdanbury 6:37b6d0d56190 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
samdanbury 6:37b6d0d56190 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
samdanbury 6:37b6d0d56190 233
samdanbury 6:37b6d0d56190 234 /*********************************************************************//**
samdanbury 6:37b6d0d56190 235 * Macro defines for Status Register
samdanbury 6:37b6d0d56190 236 **********************************************************************/
samdanbury 6:37b6d0d56190 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
samdanbury 6:37b6d0d56190 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
samdanbury 6:37b6d0d56190 239
samdanbury 6:37b6d0d56190 240 /*********************************************************************//**
samdanbury 6:37b6d0d56190 241 * Macro defines for Transmit Status Vector 0 Register
samdanbury 6:37b6d0d56190 242 **********************************************************************/
samdanbury 6:37b6d0d56190 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
samdanbury 6:37b6d0d56190 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
samdanbury 6:37b6d0d56190 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
samdanbury 6:37b6d0d56190 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
samdanbury 6:37b6d0d56190 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
samdanbury 6:37b6d0d56190 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
samdanbury 6:37b6d0d56190 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
samdanbury 6:37b6d0d56190 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
samdanbury 6:37b6d0d56190 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
samdanbury 6:37b6d0d56190 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
samdanbury 6:37b6d0d56190 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
samdanbury 6:37b6d0d56190 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
samdanbury 6:37b6d0d56190 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
samdanbury 6:37b6d0d56190 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
samdanbury 6:37b6d0d56190 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
samdanbury 6:37b6d0d56190 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
samdanbury 6:37b6d0d56190 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
samdanbury 6:37b6d0d56190 260
samdanbury 6:37b6d0d56190 261 /*********************************************************************//**
samdanbury 6:37b6d0d56190 262 * Macro defines for Transmit Status Vector 1 Register
samdanbury 6:37b6d0d56190 263 **********************************************************************/
samdanbury 6:37b6d0d56190 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
samdanbury 6:37b6d0d56190 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
samdanbury 6:37b6d0d56190 266
samdanbury 6:37b6d0d56190 267 /*********************************************************************//**
samdanbury 6:37b6d0d56190 268 * Macro defines for Receive Status Vector Register
samdanbury 6:37b6d0d56190 269 **********************************************************************/
samdanbury 6:37b6d0d56190 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
samdanbury 6:37b6d0d56190 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
samdanbury 6:37b6d0d56190 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
samdanbury 6:37b6d0d56190 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
samdanbury 6:37b6d0d56190 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
samdanbury 6:37b6d0d56190 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
samdanbury 6:37b6d0d56190 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
samdanbury 6:37b6d0d56190 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
samdanbury 6:37b6d0d56190 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
samdanbury 6:37b6d0d56190 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
samdanbury 6:37b6d0d56190 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
samdanbury 6:37b6d0d56190 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
samdanbury 6:37b6d0d56190 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
samdanbury 6:37b6d0d56190 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
samdanbury 6:37b6d0d56190 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
samdanbury 6:37b6d0d56190 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
samdanbury 6:37b6d0d56190 286
samdanbury 6:37b6d0d56190 287 /*********************************************************************//**
samdanbury 6:37b6d0d56190 288 * Macro defines for Flow Control Counter Register
samdanbury 6:37b6d0d56190 289 **********************************************************************/
samdanbury 6:37b6d0d56190 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
samdanbury 6:37b6d0d56190 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
samdanbury 6:37b6d0d56190 292
samdanbury 6:37b6d0d56190 293 /*********************************************************************//**
samdanbury 6:37b6d0d56190 294 * Macro defines for Flow Control Status Register
samdanbury 6:37b6d0d56190 295 **********************************************************************/
samdanbury 6:37b6d0d56190 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
samdanbury 6:37b6d0d56190 297
samdanbury 6:37b6d0d56190 298
samdanbury 6:37b6d0d56190 299 /* Receive filter register definitions -------------------------------------------------------- */
samdanbury 6:37b6d0d56190 300 /*********************************************************************//**
samdanbury 6:37b6d0d56190 301 * Macro defines for Receive Filter Control Register
samdanbury 6:37b6d0d56190 302 **********************************************************************/
samdanbury 6:37b6d0d56190 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
samdanbury 6:37b6d0d56190 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
samdanbury 6:37b6d0d56190 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
samdanbury 6:37b6d0d56190 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
samdanbury 6:37b6d0d56190 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
samdanbury 6:37b6d0d56190 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
samdanbury 6:37b6d0d56190 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
samdanbury 6:37b6d0d56190 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
samdanbury 6:37b6d0d56190 311
samdanbury 6:37b6d0d56190 312 /*********************************************************************//**
samdanbury 6:37b6d0d56190 313 * Macro defines for Receive Filter WoL Status/Clear Registers
samdanbury 6:37b6d0d56190 314 **********************************************************************/
samdanbury 6:37b6d0d56190 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
samdanbury 6:37b6d0d56190 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
samdanbury 6:37b6d0d56190 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
samdanbury 6:37b6d0d56190 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
samdanbury 6:37b6d0d56190 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
samdanbury 6:37b6d0d56190 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
samdanbury 6:37b6d0d56190 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
samdanbury 6:37b6d0d56190 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
samdanbury 6:37b6d0d56190 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
samdanbury 6:37b6d0d56190 324
samdanbury 6:37b6d0d56190 325
samdanbury 6:37b6d0d56190 326 /* Module control register definitions ---------------------------------------------------- */
samdanbury 6:37b6d0d56190 327 /*********************************************************************//**
samdanbury 6:37b6d0d56190 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
samdanbury 6:37b6d0d56190 329 **********************************************************************/
samdanbury 6:37b6d0d56190 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
samdanbury 6:37b6d0d56190 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
samdanbury 6:37b6d0d56190 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
samdanbury 6:37b6d0d56190 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
samdanbury 6:37b6d0d56190 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
samdanbury 6:37b6d0d56190 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
samdanbury 6:37b6d0d56190 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
samdanbury 6:37b6d0d56190 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
samdanbury 6:37b6d0d56190 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
samdanbury 6:37b6d0d56190 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
samdanbury 6:37b6d0d56190 340
samdanbury 6:37b6d0d56190 341 /*********************************************************************//**
samdanbury 6:37b6d0d56190 342 * Macro defines for Power Down Register
samdanbury 6:37b6d0d56190 343 **********************************************************************/
samdanbury 6:37b6d0d56190 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
samdanbury 6:37b6d0d56190 345
samdanbury 6:37b6d0d56190 346 /* Descriptor and status formats ---------------------------------------------------- */
samdanbury 6:37b6d0d56190 347 /*********************************************************************//**
samdanbury 6:37b6d0d56190 348 * Macro defines for RX Descriptor Control Word
samdanbury 6:37b6d0d56190 349 **********************************************************************/
samdanbury 6:37b6d0d56190 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
samdanbury 6:37b6d0d56190 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
samdanbury 6:37b6d0d56190 352
samdanbury 6:37b6d0d56190 353 /*********************************************************************//**
samdanbury 6:37b6d0d56190 354 * Macro defines for RX Status Hash CRC Word
samdanbury 6:37b6d0d56190 355 **********************************************************************/
samdanbury 6:37b6d0d56190 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
samdanbury 6:37b6d0d56190 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
samdanbury 6:37b6d0d56190 358
samdanbury 6:37b6d0d56190 359 /*********************************************************************//**
samdanbury 6:37b6d0d56190 360 * Macro defines for RX Status Information Word
samdanbury 6:37b6d0d56190 361 **********************************************************************/
samdanbury 6:37b6d0d56190 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
samdanbury 6:37b6d0d56190 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
samdanbury 6:37b6d0d56190 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
samdanbury 6:37b6d0d56190 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
samdanbury 6:37b6d0d56190 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
samdanbury 6:37b6d0d56190 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
samdanbury 6:37b6d0d56190 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
samdanbury 6:37b6d0d56190 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
samdanbury 6:37b6d0d56190 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
samdanbury 6:37b6d0d56190 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
samdanbury 6:37b6d0d56190 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
samdanbury 6:37b6d0d56190 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
samdanbury 6:37b6d0d56190 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
samdanbury 6:37b6d0d56190 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
samdanbury 6:37b6d0d56190 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
samdanbury 6:37b6d0d56190 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
samdanbury 6:37b6d0d56190 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
samdanbury 6:37b6d0d56190 379
samdanbury 6:37b6d0d56190 380 /*********************************************************************//**
samdanbury 6:37b6d0d56190 381 * Macro defines for TX Descriptor Control Word
samdanbury 6:37b6d0d56190 382 **********************************************************************/
samdanbury 6:37b6d0d56190 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
samdanbury 6:37b6d0d56190 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
samdanbury 6:37b6d0d56190 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
samdanbury 6:37b6d0d56190 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
samdanbury 6:37b6d0d56190 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
samdanbury 6:37b6d0d56190 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
samdanbury 6:37b6d0d56190 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
samdanbury 6:37b6d0d56190 390
samdanbury 6:37b6d0d56190 391 /*********************************************************************//**
samdanbury 6:37b6d0d56190 392 * Macro defines for TX Status Information Word
samdanbury 6:37b6d0d56190 393 **********************************************************************/
samdanbury 6:37b6d0d56190 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
samdanbury 6:37b6d0d56190 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
samdanbury 6:37b6d0d56190 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
samdanbury 6:37b6d0d56190 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
samdanbury 6:37b6d0d56190 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
samdanbury 6:37b6d0d56190 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
samdanbury 6:37b6d0d56190 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
samdanbury 6:37b6d0d56190 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
samdanbury 6:37b6d0d56190 402
samdanbury 6:37b6d0d56190 403 #ifdef MCB_LPC_1768
samdanbury 6:37b6d0d56190 404 /* DP83848C PHY definition ------------------------------------------------------------ */
samdanbury 6:37b6d0d56190 405
samdanbury 6:37b6d0d56190 406 /** PHY device reset time out definition */
samdanbury 6:37b6d0d56190 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
samdanbury 6:37b6d0d56190 408
samdanbury 6:37b6d0d56190 409 /* ENET Device Revision ID */
samdanbury 6:37b6d0d56190 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
samdanbury 6:37b6d0d56190 411
samdanbury 6:37b6d0d56190 412 /*********************************************************************//**
samdanbury 6:37b6d0d56190 413 * Macro defines for DP83848C PHY Registers
samdanbury 6:37b6d0d56190 414 **********************************************************************/
samdanbury 6:37b6d0d56190 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
samdanbury 6:37b6d0d56190 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
samdanbury 6:37b6d0d56190 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
samdanbury 6:37b6d0d56190 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
samdanbury 6:37b6d0d56190 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
samdanbury 6:37b6d0d56190 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
samdanbury 6:37b6d0d56190 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
samdanbury 6:37b6d0d56190 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
samdanbury 6:37b6d0d56190 423 #define EMAC_PHY_REG_LPNPA 0x08
samdanbury 6:37b6d0d56190 424
samdanbury 6:37b6d0d56190 425 /*********************************************************************//**
samdanbury 6:37b6d0d56190 426 * Macro defines for PHY Extended Registers
samdanbury 6:37b6d0d56190 427 **********************************************************************/
samdanbury 6:37b6d0d56190 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
samdanbury 6:37b6d0d56190 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
samdanbury 6:37b6d0d56190 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
samdanbury 6:37b6d0d56190 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
samdanbury 6:37b6d0d56190 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
samdanbury 6:37b6d0d56190 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
samdanbury 6:37b6d0d56190 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
samdanbury 6:37b6d0d56190 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
samdanbury 6:37b6d0d56190 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
samdanbury 6:37b6d0d56190 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
samdanbury 6:37b6d0d56190 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
samdanbury 6:37b6d0d56190 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
samdanbury 6:37b6d0d56190 440
samdanbury 6:37b6d0d56190 441 /*********************************************************************//**
samdanbury 6:37b6d0d56190 442 * Macro defines for PHY Basic Mode Control Register
samdanbury 6:37b6d0d56190 443 **********************************************************************/
samdanbury 6:37b6d0d56190 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
samdanbury 6:37b6d0d56190 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
samdanbury 6:37b6d0d56190 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
samdanbury 6:37b6d0d56190 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
samdanbury 6:37b6d0d56190 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
samdanbury 6:37b6d0d56190 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
samdanbury 6:37b6d0d56190 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
samdanbury 6:37b6d0d56190 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
samdanbury 6:37b6d0d56190 452
samdanbury 6:37b6d0d56190 453 /*********************************************************************//**
samdanbury 6:37b6d0d56190 454 * Macro defines for PHY Basic Mode Status Status Register
samdanbury 6:37b6d0d56190 455 **********************************************************************/
samdanbury 6:37b6d0d56190 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
samdanbury 6:37b6d0d56190 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
samdanbury 6:37b6d0d56190 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
samdanbury 6:37b6d0d56190 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
samdanbury 6:37b6d0d56190 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
samdanbury 6:37b6d0d56190 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
samdanbury 6:37b6d0d56190 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
samdanbury 6:37b6d0d56190 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
samdanbury 6:37b6d0d56190 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
samdanbury 6:37b6d0d56190 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
samdanbury 6:37b6d0d56190 466
samdanbury 6:37b6d0d56190 467 /*********************************************************************//**
samdanbury 6:37b6d0d56190 468 * Macro defines for PHY Status Register
samdanbury 6:37b6d0d56190 469 **********************************************************************/
samdanbury 6:37b6d0d56190 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
samdanbury 6:37b6d0d56190 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
samdanbury 6:37b6d0d56190 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
samdanbury 6:37b6d0d56190 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
samdanbury 6:37b6d0d56190 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
samdanbury 6:37b6d0d56190 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
samdanbury 6:37b6d0d56190 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
samdanbury 6:37b6d0d56190 477
samdanbury 6:37b6d0d56190 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
samdanbury 6:37b6d0d56190 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
samdanbury 6:37b6d0d56190 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
samdanbury 6:37b6d0d56190 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
samdanbury 6:37b6d0d56190 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
samdanbury 6:37b6d0d56190 483
samdanbury 6:37b6d0d56190 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
samdanbury 6:37b6d0d56190 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
samdanbury 6:37b6d0d56190 486
samdanbury 6:37b6d0d56190 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
samdanbury 6:37b6d0d56190 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
samdanbury 6:37b6d0d56190 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
samdanbury 6:37b6d0d56190 490
samdanbury 6:37b6d0d56190 491 #elif defined(IAR_LPC_1768)
samdanbury 6:37b6d0d56190 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
samdanbury 6:37b6d0d56190 493 /** PHY device reset time out definition */
samdanbury 6:37b6d0d56190 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
samdanbury 6:37b6d0d56190 495
samdanbury 6:37b6d0d56190 496 /* ENET Device Revision ID */
samdanbury 6:37b6d0d56190 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
samdanbury 6:37b6d0d56190 498
samdanbury 6:37b6d0d56190 499 /*********************************************************************//**
samdanbury 6:37b6d0d56190 500 * Macro defines for KSZ8721BL PHY Registers
samdanbury 6:37b6d0d56190 501 **********************************************************************/
samdanbury 6:37b6d0d56190 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
samdanbury 6:37b6d0d56190 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
samdanbury 6:37b6d0d56190 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
samdanbury 6:37b6d0d56190 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
samdanbury 6:37b6d0d56190 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
samdanbury 6:37b6d0d56190 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
samdanbury 6:37b6d0d56190 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
samdanbury 6:37b6d0d56190 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
samdanbury 6:37b6d0d56190 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
samdanbury 6:37b6d0d56190 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
samdanbury 6:37b6d0d56190 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
samdanbury 6:37b6d0d56190 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
samdanbury 6:37b6d0d56190 514
samdanbury 6:37b6d0d56190 515 /*********************************************************************//**
samdanbury 6:37b6d0d56190 516 * Macro defines for PHY Basic Mode Control Register
samdanbury 6:37b6d0d56190 517 **********************************************************************/
samdanbury 6:37b6d0d56190 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
samdanbury 6:37b6d0d56190 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
samdanbury 6:37b6d0d56190 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
samdanbury 6:37b6d0d56190 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
samdanbury 6:37b6d0d56190 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
samdanbury 6:37b6d0d56190 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
samdanbury 6:37b6d0d56190 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
samdanbury 6:37b6d0d56190 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
samdanbury 6:37b6d0d56190 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
samdanbury 6:37b6d0d56190 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
samdanbury 6:37b6d0d56190 528
samdanbury 6:37b6d0d56190 529 /*********************************************************************//**
samdanbury 6:37b6d0d56190 530 * Macro defines for PHY Basic Mode Status Register
samdanbury 6:37b6d0d56190 531 **********************************************************************/
samdanbury 6:37b6d0d56190 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
samdanbury 6:37b6d0d56190 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
samdanbury 6:37b6d0d56190 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
samdanbury 6:37b6d0d56190 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
samdanbury 6:37b6d0d56190 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
samdanbury 6:37b6d0d56190 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
samdanbury 6:37b6d0d56190 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
samdanbury 6:37b6d0d56190 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
samdanbury 6:37b6d0d56190 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
samdanbury 6:37b6d0d56190 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
samdanbury 6:37b6d0d56190 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
samdanbury 6:37b6d0d56190 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
samdanbury 6:37b6d0d56190 544
samdanbury 6:37b6d0d56190 545 /*********************************************************************//**
samdanbury 6:37b6d0d56190 546 * Macro defines for PHY Identifier
samdanbury 6:37b6d0d56190 547 **********************************************************************/
samdanbury 6:37b6d0d56190 548 /* PHY Identifier 1 bitmap definitions */
samdanbury 6:37b6d0d56190 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
samdanbury 6:37b6d0d56190 550
samdanbury 6:37b6d0d56190 551 /* PHY Identifier 2 bitmap definitions */
samdanbury 6:37b6d0d56190 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
samdanbury 6:37b6d0d56190 553
samdanbury 6:37b6d0d56190 554 /*********************************************************************//**
samdanbury 6:37b6d0d56190 555 * Macro defines for Auto-Negotiation Advertisement
samdanbury 6:37b6d0d56190 556 **********************************************************************/
samdanbury 6:37b6d0d56190 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
samdanbury 6:37b6d0d56190 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
samdanbury 6:37b6d0d56190 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
samdanbury 6:37b6d0d56190 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
samdanbury 6:37b6d0d56190 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
samdanbury 6:37b6d0d56190 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
samdanbury 6:37b6d0d56190 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
samdanbury 6:37b6d0d56190 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
samdanbury 6:37b6d0d56190 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
samdanbury 6:37b6d0d56190 566
samdanbury 6:37b6d0d56190 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
samdanbury 6:37b6d0d56190 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
samdanbury 6:37b6d0d56190 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
samdanbury 6:37b6d0d56190 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
samdanbury 6:37b6d0d56190 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
samdanbury 6:37b6d0d56190 572
samdanbury 6:37b6d0d56190 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
samdanbury 6:37b6d0d56190 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
samdanbury 6:37b6d0d56190 575
samdanbury 6:37b6d0d56190 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
samdanbury 6:37b6d0d56190 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
samdanbury 6:37b6d0d56190 578 #endif
samdanbury 6:37b6d0d56190 579
samdanbury 6:37b6d0d56190 580 /**
samdanbury 6:37b6d0d56190 581 * @}
samdanbury 6:37b6d0d56190 582 */
samdanbury 6:37b6d0d56190 583
samdanbury 6:37b6d0d56190 584
samdanbury 6:37b6d0d56190 585 /* Public Types --------------------------------------------------------------- */
samdanbury 6:37b6d0d56190 586 /** @defgroup EMAC_Public_Types EMAC Public Types
samdanbury 6:37b6d0d56190 587 * @{
samdanbury 6:37b6d0d56190 588 */
samdanbury 6:37b6d0d56190 589
samdanbury 6:37b6d0d56190 590 /* Descriptor and status formats ---------------------------------------------- */
samdanbury 6:37b6d0d56190 591
samdanbury 6:37b6d0d56190 592 /**
samdanbury 6:37b6d0d56190 593 * @brief RX Descriptor structure type definition
samdanbury 6:37b6d0d56190 594 */
samdanbury 6:37b6d0d56190 595 typedef struct {
samdanbury 6:37b6d0d56190 596 uint32_t Packet; /**< Receive Packet Descriptor */
samdanbury 6:37b6d0d56190 597 uint32_t Ctrl; /**< Receive Control Descriptor */
samdanbury 6:37b6d0d56190 598 } RX_Desc;
samdanbury 6:37b6d0d56190 599
samdanbury 6:37b6d0d56190 600 /**
samdanbury 6:37b6d0d56190 601 * @brief RX Status structure type definition
samdanbury 6:37b6d0d56190 602 */
samdanbury 6:37b6d0d56190 603 typedef struct {
samdanbury 6:37b6d0d56190 604 uint32_t Info; /**< Receive Information Status */
samdanbury 6:37b6d0d56190 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
samdanbury 6:37b6d0d56190 606 } RX_Stat;
samdanbury 6:37b6d0d56190 607
samdanbury 6:37b6d0d56190 608 /**
samdanbury 6:37b6d0d56190 609 * @brief TX Descriptor structure type definition
samdanbury 6:37b6d0d56190 610 */
samdanbury 6:37b6d0d56190 611 typedef struct {
samdanbury 6:37b6d0d56190 612 uint32_t Packet; /**< Transmit Packet Descriptor */
samdanbury 6:37b6d0d56190 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
samdanbury 6:37b6d0d56190 614 } TX_Desc;
samdanbury 6:37b6d0d56190 615
samdanbury 6:37b6d0d56190 616 /**
samdanbury 6:37b6d0d56190 617 * @brief TX Status structure type definition
samdanbury 6:37b6d0d56190 618 */
samdanbury 6:37b6d0d56190 619 typedef struct {
samdanbury 6:37b6d0d56190 620 uint32_t Info; /**< Transmit Information Status */
samdanbury 6:37b6d0d56190 621 } TX_Stat;
samdanbury 6:37b6d0d56190 622
samdanbury 6:37b6d0d56190 623
samdanbury 6:37b6d0d56190 624 /**
samdanbury 6:37b6d0d56190 625 * @brief TX Data Buffer structure definition
samdanbury 6:37b6d0d56190 626 */
samdanbury 6:37b6d0d56190 627 typedef struct {
samdanbury 6:37b6d0d56190 628 uint32_t ulDataLen; /**< Data length */
samdanbury 6:37b6d0d56190 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
samdanbury 6:37b6d0d56190 630 } EMAC_PACKETBUF_Type;
samdanbury 6:37b6d0d56190 631
samdanbury 6:37b6d0d56190 632 /**
samdanbury 6:37b6d0d56190 633 * @brief EMAC configuration structure definition
samdanbury 6:37b6d0d56190 634 */
samdanbury 6:37b6d0d56190 635 typedef struct {
samdanbury 6:37b6d0d56190 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
samdanbury 6:37b6d0d56190 637 - EMAC_MODE_AUTO
samdanbury 6:37b6d0d56190 638 - EMAC_MODE_10M_FULL
samdanbury 6:37b6d0d56190 639 - EMAC_MODE_10M_HALF
samdanbury 6:37b6d0d56190 640 - EMAC_MODE_100M_FULL
samdanbury 6:37b6d0d56190 641 - EMAC_MODE_100M_HALF
samdanbury 6:37b6d0d56190 642 */
samdanbury 6:37b6d0d56190 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
samdanbury 6:37b6d0d56190 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
samdanbury 6:37b6d0d56190 645 */
samdanbury 6:37b6d0d56190 646 } EMAC_CFG_Type;
samdanbury 6:37b6d0d56190 647
samdanbury 6:37b6d0d56190 648 /** Ethernet block power/clock control bit*/
samdanbury 6:37b6d0d56190 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
samdanbury 6:37b6d0d56190 650
samdanbury 6:37b6d0d56190 651 #ifdef __cplusplus
samdanbury 6:37b6d0d56190 652 }
samdanbury 6:37b6d0d56190 653 #endif
samdanbury 6:37b6d0d56190 654
samdanbury 6:37b6d0d56190 655 #endif /* LPC17XX_EMAC_H_ */
samdanbury 6:37b6d0d56190 656
samdanbury 6:37b6d0d56190 657 /**
samdanbury 6:37b6d0d56190 658 * @}
samdanbury 6:37b6d0d56190 659 */
samdanbury 6:37b6d0d56190 660
samdanbury 6:37b6d0d56190 661 /* --------------------------------- End Of File ------------------------------ */