Mark Turner / mbed

mbed library for slider v2

Dependents:   kl46z_slider_v2

TARGET_KL46Z/core_cmSimd.h@0:b7116bd48af6, 2016-09-14 (annotated)

Committer:
mturner5
Date:
Wed Sep 14 07:04:27 2016 +0000
Revision:
0:b7116bd48af6
Tried to use the timer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:b7116bd48af6 1 /**************************************************************************//**
mturner5 0:b7116bd48af6 2 * @file core_cmSimd.h
mturner5 0:b7116bd48af6 3 * @brief CMSIS Cortex-M SIMD Header File
mturner5 0:b7116bd48af6 4 * @version V4.10
mturner5 0:b7116bd48af6 5 * @date 18. March 2015
mturner5 0:b7116bd48af6 6 *
mturner5 0:b7116bd48af6 7 * @note
mturner5 0:b7116bd48af6 8 *
mturner5 0:b7116bd48af6 9 ******************************************************************************/
mturner5 0:b7116bd48af6 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
mturner5 0:b7116bd48af6 11
mturner5 0:b7116bd48af6 12 All rights reserved.
mturner5 0:b7116bd48af6 13 Redistribution and use in source and binary forms, with or without
mturner5 0:b7116bd48af6 14 modification, are permitted provided that the following conditions are met:
mturner5 0:b7116bd48af6 15 - Redistributions of source code must retain the above copyright
mturner5 0:b7116bd48af6 16 notice, this list of conditions and the following disclaimer.
mturner5 0:b7116bd48af6 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:b7116bd48af6 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:b7116bd48af6 19 documentation and/or other materials provided with the distribution.
mturner5 0:b7116bd48af6 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:b7116bd48af6 21 to endorse or promote products derived from this software without
mturner5 0:b7116bd48af6 22 specific prior written permission.
mturner5 0:b7116bd48af6 23 *
mturner5 0:b7116bd48af6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:b7116bd48af6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:b7116bd48af6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:b7116bd48af6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:b7116bd48af6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:b7116bd48af6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:b7116bd48af6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:b7116bd48af6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:b7116bd48af6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:b7116bd48af6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:b7116bd48af6 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:b7116bd48af6 35 ---------------------------------------------------------------------------*/
mturner5 0:b7116bd48af6 36
mturner5 0:b7116bd48af6 37
mturner5 0:b7116bd48af6 38 #if defined ( __ICCARM__ )
mturner5 0:b7116bd48af6 39 #pragma system_include /* treat file as system include file for MISRA check */
mturner5 0:b7116bd48af6 40 #endif
mturner5 0:b7116bd48af6 41
mturner5 0:b7116bd48af6 42 #ifndef __CORE_CMSIMD_H
mturner5 0:b7116bd48af6 43 #define __CORE_CMSIMD_H
mturner5 0:b7116bd48af6 44
mturner5 0:b7116bd48af6 45 #ifdef __cplusplus
mturner5 0:b7116bd48af6 46 extern "C" {
mturner5 0:b7116bd48af6 47 #endif
mturner5 0:b7116bd48af6 48
mturner5 0:b7116bd48af6 49
mturner5 0:b7116bd48af6 50 /*******************************************************************************
mturner5 0:b7116bd48af6 51 * Hardware Abstraction Layer
mturner5 0:b7116bd48af6 52 ******************************************************************************/
mturner5 0:b7116bd48af6 53
mturner5 0:b7116bd48af6 54
mturner5 0:b7116bd48af6 55 /* ################### Compiler specific Intrinsics ########################### */
mturner5 0:b7116bd48af6 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
mturner5 0:b7116bd48af6 57 Access to dedicated SIMD instructions
mturner5 0:b7116bd48af6 58 @{
mturner5 0:b7116bd48af6 59 */
mturner5 0:b7116bd48af6 60
mturner5 0:b7116bd48af6 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mturner5 0:b7116bd48af6 62 /* ARM armcc specific functions */
mturner5 0:b7116bd48af6 63 #define __SADD8 __sadd8
mturner5 0:b7116bd48af6 64 #define __QADD8 __qadd8
mturner5 0:b7116bd48af6 65 #define __SHADD8 __shadd8
mturner5 0:b7116bd48af6 66 #define __UADD8 __uadd8
mturner5 0:b7116bd48af6 67 #define __UQADD8 __uqadd8
mturner5 0:b7116bd48af6 68 #define __UHADD8 __uhadd8
mturner5 0:b7116bd48af6 69 #define __SSUB8 __ssub8
mturner5 0:b7116bd48af6 70 #define __QSUB8 __qsub8
mturner5 0:b7116bd48af6 71 #define __SHSUB8 __shsub8
mturner5 0:b7116bd48af6 72 #define __USUB8 __usub8
mturner5 0:b7116bd48af6 73 #define __UQSUB8 __uqsub8
mturner5 0:b7116bd48af6 74 #define __UHSUB8 __uhsub8
mturner5 0:b7116bd48af6 75 #define __SADD16 __sadd16
mturner5 0:b7116bd48af6 76 #define __QADD16 __qadd16
mturner5 0:b7116bd48af6 77 #define __SHADD16 __shadd16
mturner5 0:b7116bd48af6 78 #define __UADD16 __uadd16
mturner5 0:b7116bd48af6 79 #define __UQADD16 __uqadd16
mturner5 0:b7116bd48af6 80 #define __UHADD16 __uhadd16
mturner5 0:b7116bd48af6 81 #define __SSUB16 __ssub16
mturner5 0:b7116bd48af6 82 #define __QSUB16 __qsub16
mturner5 0:b7116bd48af6 83 #define __SHSUB16 __shsub16
mturner5 0:b7116bd48af6 84 #define __USUB16 __usub16
mturner5 0:b7116bd48af6 85 #define __UQSUB16 __uqsub16
mturner5 0:b7116bd48af6 86 #define __UHSUB16 __uhsub16
mturner5 0:b7116bd48af6 87 #define __SASX __sasx
mturner5 0:b7116bd48af6 88 #define __QASX __qasx
mturner5 0:b7116bd48af6 89 #define __SHASX __shasx
mturner5 0:b7116bd48af6 90 #define __UASX __uasx
mturner5 0:b7116bd48af6 91 #define __UQASX __uqasx
mturner5 0:b7116bd48af6 92 #define __UHASX __uhasx
mturner5 0:b7116bd48af6 93 #define __SSAX __ssax
mturner5 0:b7116bd48af6 94 #define __QSAX __qsax
mturner5 0:b7116bd48af6 95 #define __SHSAX __shsax
mturner5 0:b7116bd48af6 96 #define __USAX __usax
mturner5 0:b7116bd48af6 97 #define __UQSAX __uqsax
mturner5 0:b7116bd48af6 98 #define __UHSAX __uhsax
mturner5 0:b7116bd48af6 99 #define __USAD8 __usad8
mturner5 0:b7116bd48af6 100 #define __USADA8 __usada8
mturner5 0:b7116bd48af6 101 #define __SSAT16 __ssat16
mturner5 0:b7116bd48af6 102 #define __USAT16 __usat16
mturner5 0:b7116bd48af6 103 #define __UXTB16 __uxtb16
mturner5 0:b7116bd48af6 104 #define __UXTAB16 __uxtab16
mturner5 0:b7116bd48af6 105 #define __SXTB16 __sxtb16
mturner5 0:b7116bd48af6 106 #define __SXTAB16 __sxtab16
mturner5 0:b7116bd48af6 107 #define __SMUAD __smuad
mturner5 0:b7116bd48af6 108 #define __SMUADX __smuadx
mturner5 0:b7116bd48af6 109 #define __SMLAD __smlad
mturner5 0:b7116bd48af6 110 #define __SMLADX __smladx
mturner5 0:b7116bd48af6 111 #define __SMLALD __smlald
mturner5 0:b7116bd48af6 112 #define __SMLALDX __smlaldx
mturner5 0:b7116bd48af6 113 #define __SMUSD __smusd
mturner5 0:b7116bd48af6 114 #define __SMUSDX __smusdx
mturner5 0:b7116bd48af6 115 #define __SMLSD __smlsd
mturner5 0:b7116bd48af6 116 #define __SMLSDX __smlsdx
mturner5 0:b7116bd48af6 117 #define __SMLSLD __smlsld
mturner5 0:b7116bd48af6 118 #define __SMLSLDX __smlsldx
mturner5 0:b7116bd48af6 119 #define __SEL __sel
mturner5 0:b7116bd48af6 120 #define __QADD __qadd
mturner5 0:b7116bd48af6 121 #define __QSUB __qsub
mturner5 0:b7116bd48af6 122
mturner5 0:b7116bd48af6 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
mturner5 0:b7116bd48af6 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
mturner5 0:b7116bd48af6 125
mturner5 0:b7116bd48af6 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
mturner5 0:b7116bd48af6 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
mturner5 0:b7116bd48af6 128
mturner5 0:b7116bd48af6 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
mturner5 0:b7116bd48af6 130 ((int64_t)(ARG3) << 32) ) >> 32))
mturner5 0:b7116bd48af6 131
mturner5 0:b7116bd48af6 132
mturner5 0:b7116bd48af6 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mturner5 0:b7116bd48af6 134 /* GNU gcc specific functions */
mturner5 0:b7116bd48af6 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 136 {
mturner5 0:b7116bd48af6 137 uint32_t result;
mturner5 0:b7116bd48af6 138
mturner5 0:b7116bd48af6 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 140 return(result);
mturner5 0:b7116bd48af6 141 }
mturner5 0:b7116bd48af6 142
mturner5 0:b7116bd48af6 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 144 {
mturner5 0:b7116bd48af6 145 uint32_t result;
mturner5 0:b7116bd48af6 146
mturner5 0:b7116bd48af6 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 148 return(result);
mturner5 0:b7116bd48af6 149 }
mturner5 0:b7116bd48af6 150
mturner5 0:b7116bd48af6 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 152 {
mturner5 0:b7116bd48af6 153 uint32_t result;
mturner5 0:b7116bd48af6 154
mturner5 0:b7116bd48af6 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 156 return(result);
mturner5 0:b7116bd48af6 157 }
mturner5 0:b7116bd48af6 158
mturner5 0:b7116bd48af6 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 160 {
mturner5 0:b7116bd48af6 161 uint32_t result;
mturner5 0:b7116bd48af6 162
mturner5 0:b7116bd48af6 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 164 return(result);
mturner5 0:b7116bd48af6 165 }
mturner5 0:b7116bd48af6 166
mturner5 0:b7116bd48af6 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 168 {
mturner5 0:b7116bd48af6 169 uint32_t result;
mturner5 0:b7116bd48af6 170
mturner5 0:b7116bd48af6 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 172 return(result);
mturner5 0:b7116bd48af6 173 }
mturner5 0:b7116bd48af6 174
mturner5 0:b7116bd48af6 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 176 {
mturner5 0:b7116bd48af6 177 uint32_t result;
mturner5 0:b7116bd48af6 178
mturner5 0:b7116bd48af6 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 180 return(result);
mturner5 0:b7116bd48af6 181 }
mturner5 0:b7116bd48af6 182
mturner5 0:b7116bd48af6 183
mturner5 0:b7116bd48af6 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 185 {
mturner5 0:b7116bd48af6 186 uint32_t result;
mturner5 0:b7116bd48af6 187
mturner5 0:b7116bd48af6 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 189 return(result);
mturner5 0:b7116bd48af6 190 }
mturner5 0:b7116bd48af6 191
mturner5 0:b7116bd48af6 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 193 {
mturner5 0:b7116bd48af6 194 uint32_t result;
mturner5 0:b7116bd48af6 195
mturner5 0:b7116bd48af6 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 197 return(result);
mturner5 0:b7116bd48af6 198 }
mturner5 0:b7116bd48af6 199
mturner5 0:b7116bd48af6 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 201 {
mturner5 0:b7116bd48af6 202 uint32_t result;
mturner5 0:b7116bd48af6 203
mturner5 0:b7116bd48af6 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 205 return(result);
mturner5 0:b7116bd48af6 206 }
mturner5 0:b7116bd48af6 207
mturner5 0:b7116bd48af6 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 209 {
mturner5 0:b7116bd48af6 210 uint32_t result;
mturner5 0:b7116bd48af6 211
mturner5 0:b7116bd48af6 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 213 return(result);
mturner5 0:b7116bd48af6 214 }
mturner5 0:b7116bd48af6 215
mturner5 0:b7116bd48af6 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 217 {
mturner5 0:b7116bd48af6 218 uint32_t result;
mturner5 0:b7116bd48af6 219
mturner5 0:b7116bd48af6 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 221 return(result);
mturner5 0:b7116bd48af6 222 }
mturner5 0:b7116bd48af6 223
mturner5 0:b7116bd48af6 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 225 {
mturner5 0:b7116bd48af6 226 uint32_t result;
mturner5 0:b7116bd48af6 227
mturner5 0:b7116bd48af6 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 229 return(result);
mturner5 0:b7116bd48af6 230 }
mturner5 0:b7116bd48af6 231
mturner5 0:b7116bd48af6 232
mturner5 0:b7116bd48af6 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 234 {
mturner5 0:b7116bd48af6 235 uint32_t result;
mturner5 0:b7116bd48af6 236
mturner5 0:b7116bd48af6 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 238 return(result);
mturner5 0:b7116bd48af6 239 }
mturner5 0:b7116bd48af6 240
mturner5 0:b7116bd48af6 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 242 {
mturner5 0:b7116bd48af6 243 uint32_t result;
mturner5 0:b7116bd48af6 244
mturner5 0:b7116bd48af6 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 246 return(result);
mturner5 0:b7116bd48af6 247 }
mturner5 0:b7116bd48af6 248
mturner5 0:b7116bd48af6 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 250 {
mturner5 0:b7116bd48af6 251 uint32_t result;
mturner5 0:b7116bd48af6 252
mturner5 0:b7116bd48af6 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 254 return(result);
mturner5 0:b7116bd48af6 255 }
mturner5 0:b7116bd48af6 256
mturner5 0:b7116bd48af6 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 258 {
mturner5 0:b7116bd48af6 259 uint32_t result;
mturner5 0:b7116bd48af6 260
mturner5 0:b7116bd48af6 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 262 return(result);
mturner5 0:b7116bd48af6 263 }
mturner5 0:b7116bd48af6 264
mturner5 0:b7116bd48af6 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 266 {
mturner5 0:b7116bd48af6 267 uint32_t result;
mturner5 0:b7116bd48af6 268
mturner5 0:b7116bd48af6 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 270 return(result);
mturner5 0:b7116bd48af6 271 }
mturner5 0:b7116bd48af6 272
mturner5 0:b7116bd48af6 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 274 {
mturner5 0:b7116bd48af6 275 uint32_t result;
mturner5 0:b7116bd48af6 276
mturner5 0:b7116bd48af6 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 278 return(result);
mturner5 0:b7116bd48af6 279 }
mturner5 0:b7116bd48af6 280
mturner5 0:b7116bd48af6 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 282 {
mturner5 0:b7116bd48af6 283 uint32_t result;
mturner5 0:b7116bd48af6 284
mturner5 0:b7116bd48af6 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 286 return(result);
mturner5 0:b7116bd48af6 287 }
mturner5 0:b7116bd48af6 288
mturner5 0:b7116bd48af6 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 290 {
mturner5 0:b7116bd48af6 291 uint32_t result;
mturner5 0:b7116bd48af6 292
mturner5 0:b7116bd48af6 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 294 return(result);
mturner5 0:b7116bd48af6 295 }
mturner5 0:b7116bd48af6 296
mturner5 0:b7116bd48af6 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 298 {
mturner5 0:b7116bd48af6 299 uint32_t result;
mturner5 0:b7116bd48af6 300
mturner5 0:b7116bd48af6 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 302 return(result);
mturner5 0:b7116bd48af6 303 }
mturner5 0:b7116bd48af6 304
mturner5 0:b7116bd48af6 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 306 {
mturner5 0:b7116bd48af6 307 uint32_t result;
mturner5 0:b7116bd48af6 308
mturner5 0:b7116bd48af6 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 310 return(result);
mturner5 0:b7116bd48af6 311 }
mturner5 0:b7116bd48af6 312
mturner5 0:b7116bd48af6 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 314 {
mturner5 0:b7116bd48af6 315 uint32_t result;
mturner5 0:b7116bd48af6 316
mturner5 0:b7116bd48af6 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 318 return(result);
mturner5 0:b7116bd48af6 319 }
mturner5 0:b7116bd48af6 320
mturner5 0:b7116bd48af6 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 322 {
mturner5 0:b7116bd48af6 323 uint32_t result;
mturner5 0:b7116bd48af6 324
mturner5 0:b7116bd48af6 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 326 return(result);
mturner5 0:b7116bd48af6 327 }
mturner5 0:b7116bd48af6 328
mturner5 0:b7116bd48af6 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 330 {
mturner5 0:b7116bd48af6 331 uint32_t result;
mturner5 0:b7116bd48af6 332
mturner5 0:b7116bd48af6 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 334 return(result);
mturner5 0:b7116bd48af6 335 }
mturner5 0:b7116bd48af6 336
mturner5 0:b7116bd48af6 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 338 {
mturner5 0:b7116bd48af6 339 uint32_t result;
mturner5 0:b7116bd48af6 340
mturner5 0:b7116bd48af6 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 342 return(result);
mturner5 0:b7116bd48af6 343 }
mturner5 0:b7116bd48af6 344
mturner5 0:b7116bd48af6 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 346 {
mturner5 0:b7116bd48af6 347 uint32_t result;
mturner5 0:b7116bd48af6 348
mturner5 0:b7116bd48af6 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 350 return(result);
mturner5 0:b7116bd48af6 351 }
mturner5 0:b7116bd48af6 352
mturner5 0:b7116bd48af6 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 354 {
mturner5 0:b7116bd48af6 355 uint32_t result;
mturner5 0:b7116bd48af6 356
mturner5 0:b7116bd48af6 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 358 return(result);
mturner5 0:b7116bd48af6 359 }
mturner5 0:b7116bd48af6 360
mturner5 0:b7116bd48af6 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 362 {
mturner5 0:b7116bd48af6 363 uint32_t result;
mturner5 0:b7116bd48af6 364
mturner5 0:b7116bd48af6 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 366 return(result);
mturner5 0:b7116bd48af6 367 }
mturner5 0:b7116bd48af6 368
mturner5 0:b7116bd48af6 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 370 {
mturner5 0:b7116bd48af6 371 uint32_t result;
mturner5 0:b7116bd48af6 372
mturner5 0:b7116bd48af6 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 374 return(result);
mturner5 0:b7116bd48af6 375 }
mturner5 0:b7116bd48af6 376
mturner5 0:b7116bd48af6 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 378 {
mturner5 0:b7116bd48af6 379 uint32_t result;
mturner5 0:b7116bd48af6 380
mturner5 0:b7116bd48af6 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 382 return(result);
mturner5 0:b7116bd48af6 383 }
mturner5 0:b7116bd48af6 384
mturner5 0:b7116bd48af6 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 386 {
mturner5 0:b7116bd48af6 387 uint32_t result;
mturner5 0:b7116bd48af6 388
mturner5 0:b7116bd48af6 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 390 return(result);
mturner5 0:b7116bd48af6 391 }
mturner5 0:b7116bd48af6 392
mturner5 0:b7116bd48af6 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 394 {
mturner5 0:b7116bd48af6 395 uint32_t result;
mturner5 0:b7116bd48af6 396
mturner5 0:b7116bd48af6 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 398 return(result);
mturner5 0:b7116bd48af6 399 }
mturner5 0:b7116bd48af6 400
mturner5 0:b7116bd48af6 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 402 {
mturner5 0:b7116bd48af6 403 uint32_t result;
mturner5 0:b7116bd48af6 404
mturner5 0:b7116bd48af6 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 406 return(result);
mturner5 0:b7116bd48af6 407 }
mturner5 0:b7116bd48af6 408
mturner5 0:b7116bd48af6 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 410 {
mturner5 0:b7116bd48af6 411 uint32_t result;
mturner5 0:b7116bd48af6 412
mturner5 0:b7116bd48af6 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 414 return(result);
mturner5 0:b7116bd48af6 415 }
mturner5 0:b7116bd48af6 416
mturner5 0:b7116bd48af6 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 418 {
mturner5 0:b7116bd48af6 419 uint32_t result;
mturner5 0:b7116bd48af6 420
mturner5 0:b7116bd48af6 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 422 return(result);
mturner5 0:b7116bd48af6 423 }
mturner5 0:b7116bd48af6 424
mturner5 0:b7116bd48af6 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 426 {
mturner5 0:b7116bd48af6 427 uint32_t result;
mturner5 0:b7116bd48af6 428
mturner5 0:b7116bd48af6 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 430 return(result);
mturner5 0:b7116bd48af6 431 }
mturner5 0:b7116bd48af6 432
mturner5 0:b7116bd48af6 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
mturner5 0:b7116bd48af6 434 {
mturner5 0:b7116bd48af6 435 uint32_t result;
mturner5 0:b7116bd48af6 436
mturner5 0:b7116bd48af6 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mturner5 0:b7116bd48af6 438 return(result);
mturner5 0:b7116bd48af6 439 }
mturner5 0:b7116bd48af6 440
mturner5 0:b7116bd48af6 441 #define __SSAT16(ARG1,ARG2) \
mturner5 0:b7116bd48af6 442 ({ \
mturner5 0:b7116bd48af6 443 uint32_t __RES, __ARG1 = (ARG1); \
mturner5 0:b7116bd48af6 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mturner5 0:b7116bd48af6 445 __RES; \
mturner5 0:b7116bd48af6 446 })
mturner5 0:b7116bd48af6 447
mturner5 0:b7116bd48af6 448 #define __USAT16(ARG1,ARG2) \
mturner5 0:b7116bd48af6 449 ({ \
mturner5 0:b7116bd48af6 450 uint32_t __RES, __ARG1 = (ARG1); \
mturner5 0:b7116bd48af6 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mturner5 0:b7116bd48af6 452 __RES; \
mturner5 0:b7116bd48af6 453 })
mturner5 0:b7116bd48af6 454
mturner5 0:b7116bd48af6 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
mturner5 0:b7116bd48af6 456 {
mturner5 0:b7116bd48af6 457 uint32_t result;
mturner5 0:b7116bd48af6 458
mturner5 0:b7116bd48af6 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
mturner5 0:b7116bd48af6 460 return(result);
mturner5 0:b7116bd48af6 461 }
mturner5 0:b7116bd48af6 462
mturner5 0:b7116bd48af6 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 464 {
mturner5 0:b7116bd48af6 465 uint32_t result;
mturner5 0:b7116bd48af6 466
mturner5 0:b7116bd48af6 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 468 return(result);
mturner5 0:b7116bd48af6 469 }
mturner5 0:b7116bd48af6 470
mturner5 0:b7116bd48af6 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
mturner5 0:b7116bd48af6 472 {
mturner5 0:b7116bd48af6 473 uint32_t result;
mturner5 0:b7116bd48af6 474
mturner5 0:b7116bd48af6 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
mturner5 0:b7116bd48af6 476 return(result);
mturner5 0:b7116bd48af6 477 }
mturner5 0:b7116bd48af6 478
mturner5 0:b7116bd48af6 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 480 {
mturner5 0:b7116bd48af6 481 uint32_t result;
mturner5 0:b7116bd48af6 482
mturner5 0:b7116bd48af6 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 484 return(result);
mturner5 0:b7116bd48af6 485 }
mturner5 0:b7116bd48af6 486
mturner5 0:b7116bd48af6 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 488 {
mturner5 0:b7116bd48af6 489 uint32_t result;
mturner5 0:b7116bd48af6 490
mturner5 0:b7116bd48af6 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 492 return(result);
mturner5 0:b7116bd48af6 493 }
mturner5 0:b7116bd48af6 494
mturner5 0:b7116bd48af6 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 496 {
mturner5 0:b7116bd48af6 497 uint32_t result;
mturner5 0:b7116bd48af6 498
mturner5 0:b7116bd48af6 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 500 return(result);
mturner5 0:b7116bd48af6 501 }
mturner5 0:b7116bd48af6 502
mturner5 0:b7116bd48af6 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
mturner5 0:b7116bd48af6 504 {
mturner5 0:b7116bd48af6 505 uint32_t result;
mturner5 0:b7116bd48af6 506
mturner5 0:b7116bd48af6 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mturner5 0:b7116bd48af6 508 return(result);
mturner5 0:b7116bd48af6 509 }
mturner5 0:b7116bd48af6 510
mturner5 0:b7116bd48af6 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
mturner5 0:b7116bd48af6 512 {
mturner5 0:b7116bd48af6 513 uint32_t result;
mturner5 0:b7116bd48af6 514
mturner5 0:b7116bd48af6 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mturner5 0:b7116bd48af6 516 return(result);
mturner5 0:b7116bd48af6 517 }
mturner5 0:b7116bd48af6 518
mturner5 0:b7116bd48af6 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
mturner5 0:b7116bd48af6 520 {
mturner5 0:b7116bd48af6 521 union llreg_u{
mturner5 0:b7116bd48af6 522 uint32_t w32[2];
mturner5 0:b7116bd48af6 523 uint64_t w64;
mturner5 0:b7116bd48af6 524 } llr;
mturner5 0:b7116bd48af6 525 llr.w64 = acc;
mturner5 0:b7116bd48af6 526
mturner5 0:b7116bd48af6 527 #ifndef __ARMEB__ // Little endian
mturner5 0:b7116bd48af6 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
mturner5 0:b7116bd48af6 529 #else // Big endian
mturner5 0:b7116bd48af6 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
mturner5 0:b7116bd48af6 531 #endif
mturner5 0:b7116bd48af6 532
mturner5 0:b7116bd48af6 533 return(llr.w64);
mturner5 0:b7116bd48af6 534 }
mturner5 0:b7116bd48af6 535
mturner5 0:b7116bd48af6 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
mturner5 0:b7116bd48af6 537 {
mturner5 0:b7116bd48af6 538 union llreg_u{
mturner5 0:b7116bd48af6 539 uint32_t w32[2];
mturner5 0:b7116bd48af6 540 uint64_t w64;
mturner5 0:b7116bd48af6 541 } llr;
mturner5 0:b7116bd48af6 542 llr.w64 = acc;
mturner5 0:b7116bd48af6 543
mturner5 0:b7116bd48af6 544 #ifndef __ARMEB__ // Little endian
mturner5 0:b7116bd48af6 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
mturner5 0:b7116bd48af6 546 #else // Big endian
mturner5 0:b7116bd48af6 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
mturner5 0:b7116bd48af6 548 #endif
mturner5 0:b7116bd48af6 549
mturner5 0:b7116bd48af6 550 return(llr.w64);
mturner5 0:b7116bd48af6 551 }
mturner5 0:b7116bd48af6 552
mturner5 0:b7116bd48af6 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 554 {
mturner5 0:b7116bd48af6 555 uint32_t result;
mturner5 0:b7116bd48af6 556
mturner5 0:b7116bd48af6 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 558 return(result);
mturner5 0:b7116bd48af6 559 }
mturner5 0:b7116bd48af6 560
mturner5 0:b7116bd48af6 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 562 {
mturner5 0:b7116bd48af6 563 uint32_t result;
mturner5 0:b7116bd48af6 564
mturner5 0:b7116bd48af6 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 566 return(result);
mturner5 0:b7116bd48af6 567 }
mturner5 0:b7116bd48af6 568
mturner5 0:b7116bd48af6 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
mturner5 0:b7116bd48af6 570 {
mturner5 0:b7116bd48af6 571 uint32_t result;
mturner5 0:b7116bd48af6 572
mturner5 0:b7116bd48af6 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mturner5 0:b7116bd48af6 574 return(result);
mturner5 0:b7116bd48af6 575 }
mturner5 0:b7116bd48af6 576
mturner5 0:b7116bd48af6 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
mturner5 0:b7116bd48af6 578 {
mturner5 0:b7116bd48af6 579 uint32_t result;
mturner5 0:b7116bd48af6 580
mturner5 0:b7116bd48af6 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mturner5 0:b7116bd48af6 582 return(result);
mturner5 0:b7116bd48af6 583 }
mturner5 0:b7116bd48af6 584
mturner5 0:b7116bd48af6 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
mturner5 0:b7116bd48af6 586 {
mturner5 0:b7116bd48af6 587 union llreg_u{
mturner5 0:b7116bd48af6 588 uint32_t w32[2];
mturner5 0:b7116bd48af6 589 uint64_t w64;
mturner5 0:b7116bd48af6 590 } llr;
mturner5 0:b7116bd48af6 591 llr.w64 = acc;
mturner5 0:b7116bd48af6 592
mturner5 0:b7116bd48af6 593 #ifndef __ARMEB__ // Little endian
mturner5 0:b7116bd48af6 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
mturner5 0:b7116bd48af6 595 #else // Big endian
mturner5 0:b7116bd48af6 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
mturner5 0:b7116bd48af6 597 #endif
mturner5 0:b7116bd48af6 598
mturner5 0:b7116bd48af6 599 return(llr.w64);
mturner5 0:b7116bd48af6 600 }
mturner5 0:b7116bd48af6 601
mturner5 0:b7116bd48af6 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
mturner5 0:b7116bd48af6 603 {
mturner5 0:b7116bd48af6 604 union llreg_u{
mturner5 0:b7116bd48af6 605 uint32_t w32[2];
mturner5 0:b7116bd48af6 606 uint64_t w64;
mturner5 0:b7116bd48af6 607 } llr;
mturner5 0:b7116bd48af6 608 llr.w64 = acc;
mturner5 0:b7116bd48af6 609
mturner5 0:b7116bd48af6 610 #ifndef __ARMEB__ // Little endian
mturner5 0:b7116bd48af6 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
mturner5 0:b7116bd48af6 612 #else // Big endian
mturner5 0:b7116bd48af6 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
mturner5 0:b7116bd48af6 614 #endif
mturner5 0:b7116bd48af6 615
mturner5 0:b7116bd48af6 616 return(llr.w64);
mturner5 0:b7116bd48af6 617 }
mturner5 0:b7116bd48af6 618
mturner5 0:b7116bd48af6 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 620 {
mturner5 0:b7116bd48af6 621 uint32_t result;
mturner5 0:b7116bd48af6 622
mturner5 0:b7116bd48af6 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 624 return(result);
mturner5 0:b7116bd48af6 625 }
mturner5 0:b7116bd48af6 626
mturner5 0:b7116bd48af6 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 628 {
mturner5 0:b7116bd48af6 629 uint32_t result;
mturner5 0:b7116bd48af6 630
mturner5 0:b7116bd48af6 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 632 return(result);
mturner5 0:b7116bd48af6 633 }
mturner5 0:b7116bd48af6 634
mturner5 0:b7116bd48af6 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 636 {
mturner5 0:b7116bd48af6 637 uint32_t result;
mturner5 0:b7116bd48af6 638
mturner5 0:b7116bd48af6 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mturner5 0:b7116bd48af6 640 return(result);
mturner5 0:b7116bd48af6 641 }
mturner5 0:b7116bd48af6 642
mturner5 0:b7116bd48af6 643 #define __PKHBT(ARG1,ARG2,ARG3) \
mturner5 0:b7116bd48af6 644 ({ \
mturner5 0:b7116bd48af6 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
mturner5 0:b7116bd48af6 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
mturner5 0:b7116bd48af6 647 __RES; \
mturner5 0:b7116bd48af6 648 })
mturner5 0:b7116bd48af6 649
mturner5 0:b7116bd48af6 650 #define __PKHTB(ARG1,ARG2,ARG3) \
mturner5 0:b7116bd48af6 651 ({ \
mturner5 0:b7116bd48af6 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
mturner5 0:b7116bd48af6 653 if (ARG3 == 0) \
mturner5 0:b7116bd48af6 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
mturner5 0:b7116bd48af6 655 else \
mturner5 0:b7116bd48af6 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
mturner5 0:b7116bd48af6 657 __RES; \
mturner5 0:b7116bd48af6 658 })
mturner5 0:b7116bd48af6 659
mturner5 0:b7116bd48af6 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
mturner5 0:b7116bd48af6 661 {
mturner5 0:b7116bd48af6 662 int32_t result;
mturner5 0:b7116bd48af6 663
mturner5 0:b7116bd48af6 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
mturner5 0:b7116bd48af6 665 return(result);
mturner5 0:b7116bd48af6 666 }
mturner5 0:b7116bd48af6 667
mturner5 0:b7116bd48af6 668
mturner5 0:b7116bd48af6 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mturner5 0:b7116bd48af6 670 /* IAR iccarm specific functions */
mturner5 0:b7116bd48af6 671 #include <cmsis_iar.h>
mturner5 0:b7116bd48af6 672
mturner5 0:b7116bd48af6 673
mturner5 0:b7116bd48af6 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mturner5 0:b7116bd48af6 675 /* TI CCS specific functions */
mturner5 0:b7116bd48af6 676 #include <cmsis_ccs.h>
mturner5 0:b7116bd48af6 677
mturner5 0:b7116bd48af6 678
mturner5 0:b7116bd48af6 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mturner5 0:b7116bd48af6 680 /* TASKING carm specific functions */
mturner5 0:b7116bd48af6 681 /* not yet supported */
mturner5 0:b7116bd48af6 682
mturner5 0:b7116bd48af6 683
mturner5 0:b7116bd48af6 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
mturner5 0:b7116bd48af6 685 /* Cosmic specific functions */
mturner5 0:b7116bd48af6 686 #include <cmsis_csm.h>
mturner5 0:b7116bd48af6 687
mturner5 0:b7116bd48af6 688 #endif
mturner5 0:b7116bd48af6 689
mturner5 0:b7116bd48af6 690 /*@} end of group CMSIS_SIMD_intrinsics */
mturner5 0:b7116bd48af6 691
mturner5 0:b7116bd48af6 692
mturner5 0:b7116bd48af6 693 #ifdef __cplusplus
mturner5 0:b7116bd48af6 694 }
mturner5 0:b7116bd48af6 695 #endif
mturner5 0:b7116bd48af6 696
mturner5 0:b7116bd48af6 697 #endif /* __CORE_CMSIMD_H */