Mark Turner / mbed

mbed library for slider v2

Dependents:   kl46z_slider_v2

TARGET_KL46Z/core_caFunc.h@0:b7116bd48af6, 2016-09-14 (annotated)

Committer:
mturner5
Date:
Wed Sep 14 07:04:27 2016 +0000
Revision:
0:b7116bd48af6
Tried to use the timer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:b7116bd48af6 1 /**************************************************************************//**
mturner5 0:b7116bd48af6 2 * @file core_caFunc.h
mturner5 0:b7116bd48af6 3 * @brief CMSIS Cortex-A Core Function Access Header File
mturner5 0:b7116bd48af6 4 * @version V3.10
mturner5 0:b7116bd48af6 5 * @date 30 Oct 2013
mturner5 0:b7116bd48af6 6 *
mturner5 0:b7116bd48af6 7 * @note
mturner5 0:b7116bd48af6 8 *
mturner5 0:b7116bd48af6 9 ******************************************************************************/
mturner5 0:b7116bd48af6 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mturner5 0:b7116bd48af6 11
mturner5 0:b7116bd48af6 12 All rights reserved.
mturner5 0:b7116bd48af6 13 Redistribution and use in source and binary forms, with or without
mturner5 0:b7116bd48af6 14 modification, are permitted provided that the following conditions are met:
mturner5 0:b7116bd48af6 15 - Redistributions of source code must retain the above copyright
mturner5 0:b7116bd48af6 16 notice, this list of conditions and the following disclaimer.
mturner5 0:b7116bd48af6 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:b7116bd48af6 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:b7116bd48af6 19 documentation and/or other materials provided with the distribution.
mturner5 0:b7116bd48af6 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:b7116bd48af6 21 to endorse or promote products derived from this software without
mturner5 0:b7116bd48af6 22 specific prior written permission.
mturner5 0:b7116bd48af6 23 *
mturner5 0:b7116bd48af6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:b7116bd48af6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:b7116bd48af6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:b7116bd48af6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:b7116bd48af6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:b7116bd48af6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:b7116bd48af6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:b7116bd48af6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:b7116bd48af6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:b7116bd48af6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:b7116bd48af6 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:b7116bd48af6 35 ---------------------------------------------------------------------------*/
mturner5 0:b7116bd48af6 36
mturner5 0:b7116bd48af6 37
mturner5 0:b7116bd48af6 38 #ifndef __CORE_CAFUNC_H__
mturner5 0:b7116bd48af6 39 #define __CORE_CAFUNC_H__
mturner5 0:b7116bd48af6 40
mturner5 0:b7116bd48af6 41
mturner5 0:b7116bd48af6 42 /* ########################### Core Function Access ########################### */
mturner5 0:b7116bd48af6 43 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:b7116bd48af6 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mturner5 0:b7116bd48af6 45 @{
mturner5 0:b7116bd48af6 46 */
mturner5 0:b7116bd48af6 47
mturner5 0:b7116bd48af6 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mturner5 0:b7116bd48af6 49 /* ARM armcc specific functions */
mturner5 0:b7116bd48af6 50
mturner5 0:b7116bd48af6 51 #if (__ARMCC_VERSION < 400677)
mturner5 0:b7116bd48af6 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mturner5 0:b7116bd48af6 53 #endif
mturner5 0:b7116bd48af6 54
mturner5 0:b7116bd48af6 55 #define MODE_USR 0x10
mturner5 0:b7116bd48af6 56 #define MODE_FIQ 0x11
mturner5 0:b7116bd48af6 57 #define MODE_IRQ 0x12
mturner5 0:b7116bd48af6 58 #define MODE_SVC 0x13
mturner5 0:b7116bd48af6 59 #define MODE_MON 0x16
mturner5 0:b7116bd48af6 60 #define MODE_ABT 0x17
mturner5 0:b7116bd48af6 61 #define MODE_HYP 0x1A
mturner5 0:b7116bd48af6 62 #define MODE_UND 0x1B
mturner5 0:b7116bd48af6 63 #define MODE_SYS 0x1F
mturner5 0:b7116bd48af6 64
mturner5 0:b7116bd48af6 65 /** \brief Get APSR Register
mturner5 0:b7116bd48af6 66
mturner5 0:b7116bd48af6 67 This function returns the content of the APSR Register.
mturner5 0:b7116bd48af6 68
mturner5 0:b7116bd48af6 69 \return APSR Register value
mturner5 0:b7116bd48af6 70 */
mturner5 0:b7116bd48af6 71 __STATIC_INLINE uint32_t __get_APSR(void)
mturner5 0:b7116bd48af6 72 {
mturner5 0:b7116bd48af6 73 register uint32_t __regAPSR __ASM("apsr");
mturner5 0:b7116bd48af6 74 return(__regAPSR);
mturner5 0:b7116bd48af6 75 }
mturner5 0:b7116bd48af6 76
mturner5 0:b7116bd48af6 77
mturner5 0:b7116bd48af6 78 /** \brief Get CPSR Register
mturner5 0:b7116bd48af6 79
mturner5 0:b7116bd48af6 80 This function returns the content of the CPSR Register.
mturner5 0:b7116bd48af6 81
mturner5 0:b7116bd48af6 82 \return CPSR Register value
mturner5 0:b7116bd48af6 83 */
mturner5 0:b7116bd48af6 84 __STATIC_INLINE uint32_t __get_CPSR(void)
mturner5 0:b7116bd48af6 85 {
mturner5 0:b7116bd48af6 86 register uint32_t __regCPSR __ASM("cpsr");
mturner5 0:b7116bd48af6 87 return(__regCPSR);
mturner5 0:b7116bd48af6 88 }
mturner5 0:b7116bd48af6 89
mturner5 0:b7116bd48af6 90 /** \brief Set Stack Pointer
mturner5 0:b7116bd48af6 91
mturner5 0:b7116bd48af6 92 This function assigns the given value to the current stack pointer.
mturner5 0:b7116bd48af6 93
mturner5 0:b7116bd48af6 94 \param [in] topOfStack Stack Pointer value to set
mturner5 0:b7116bd48af6 95 */
mturner5 0:b7116bd48af6 96 register uint32_t __regSP __ASM("sp");
mturner5 0:b7116bd48af6 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
mturner5 0:b7116bd48af6 98 {
mturner5 0:b7116bd48af6 99 __regSP = topOfStack;
mturner5 0:b7116bd48af6 100 }
mturner5 0:b7116bd48af6 101
mturner5 0:b7116bd48af6 102
mturner5 0:b7116bd48af6 103 /** \brief Get link register
mturner5 0:b7116bd48af6 104
mturner5 0:b7116bd48af6 105 This function returns the value of the link register
mturner5 0:b7116bd48af6 106
mturner5 0:b7116bd48af6 107 \return Value of link register
mturner5 0:b7116bd48af6 108 */
mturner5 0:b7116bd48af6 109 register uint32_t __reglr __ASM("lr");
mturner5 0:b7116bd48af6 110 __STATIC_INLINE uint32_t __get_LR(void)
mturner5 0:b7116bd48af6 111 {
mturner5 0:b7116bd48af6 112 return(__reglr);
mturner5 0:b7116bd48af6 113 }
mturner5 0:b7116bd48af6 114
mturner5 0:b7116bd48af6 115 /** \brief Set link register
mturner5 0:b7116bd48af6 116
mturner5 0:b7116bd48af6 117 This function sets the value of the link register
mturner5 0:b7116bd48af6 118
mturner5 0:b7116bd48af6 119 \param [in] lr LR value to set
mturner5 0:b7116bd48af6 120 */
mturner5 0:b7116bd48af6 121 __STATIC_INLINE void __set_LR(uint32_t lr)
mturner5 0:b7116bd48af6 122 {
mturner5 0:b7116bd48af6 123 __reglr = lr;
mturner5 0:b7116bd48af6 124 }
mturner5 0:b7116bd48af6 125
mturner5 0:b7116bd48af6 126 /** \brief Set Process Stack Pointer
mturner5 0:b7116bd48af6 127
mturner5 0:b7116bd48af6 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mturner5 0:b7116bd48af6 129
mturner5 0:b7116bd48af6 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mturner5 0:b7116bd48af6 131 */
mturner5 0:b7116bd48af6 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
mturner5 0:b7116bd48af6 133 {
mturner5 0:b7116bd48af6 134 ARM
mturner5 0:b7116bd48af6 135 PRESERVE8
mturner5 0:b7116bd48af6 136
mturner5 0:b7116bd48af6 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
mturner5 0:b7116bd48af6 138 MRS R1, CPSR
mturner5 0:b7116bd48af6 139 CPS #MODE_SYS ;no effect in USR mode
mturner5 0:b7116bd48af6 140 MOV SP, R0
mturner5 0:b7116bd48af6 141 MSR CPSR_c, R1 ;no effect in USR mode
mturner5 0:b7116bd48af6 142 ISB
mturner5 0:b7116bd48af6 143 BX LR
mturner5 0:b7116bd48af6 144
mturner5 0:b7116bd48af6 145 }
mturner5 0:b7116bd48af6 146
mturner5 0:b7116bd48af6 147 /** \brief Set User Mode
mturner5 0:b7116bd48af6 148
mturner5 0:b7116bd48af6 149 This function changes the processor state to User Mode
mturner5 0:b7116bd48af6 150 */
mturner5 0:b7116bd48af6 151 __STATIC_ASM void __set_CPS_USR(void)
mturner5 0:b7116bd48af6 152 {
mturner5 0:b7116bd48af6 153 ARM
mturner5 0:b7116bd48af6 154
mturner5 0:b7116bd48af6 155 CPS #MODE_USR
mturner5 0:b7116bd48af6 156 BX LR
mturner5 0:b7116bd48af6 157 }
mturner5 0:b7116bd48af6 158
mturner5 0:b7116bd48af6 159
mturner5 0:b7116bd48af6 160 /** \brief Enable FIQ
mturner5 0:b7116bd48af6 161
mturner5 0:b7116bd48af6 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mturner5 0:b7116bd48af6 163 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 164 */
mturner5 0:b7116bd48af6 165 #define __enable_fault_irq __enable_fiq
mturner5 0:b7116bd48af6 166
mturner5 0:b7116bd48af6 167
mturner5 0:b7116bd48af6 168 /** \brief Disable FIQ
mturner5 0:b7116bd48af6 169
mturner5 0:b7116bd48af6 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mturner5 0:b7116bd48af6 171 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 172 */
mturner5 0:b7116bd48af6 173 #define __disable_fault_irq __disable_fiq
mturner5 0:b7116bd48af6 174
mturner5 0:b7116bd48af6 175
mturner5 0:b7116bd48af6 176 /** \brief Get FPSCR
mturner5 0:b7116bd48af6 177
mturner5 0:b7116bd48af6 178 This function returns the current value of the Floating Point Status/Control register.
mturner5 0:b7116bd48af6 179
mturner5 0:b7116bd48af6 180 \return Floating Point Status/Control register value
mturner5 0:b7116bd48af6 181 */
mturner5 0:b7116bd48af6 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
mturner5 0:b7116bd48af6 183 {
mturner5 0:b7116bd48af6 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:b7116bd48af6 185 register uint32_t __regfpscr __ASM("fpscr");
mturner5 0:b7116bd48af6 186 return(__regfpscr);
mturner5 0:b7116bd48af6 187 #else
mturner5 0:b7116bd48af6 188 return(0);
mturner5 0:b7116bd48af6 189 #endif
mturner5 0:b7116bd48af6 190 }
mturner5 0:b7116bd48af6 191
mturner5 0:b7116bd48af6 192
mturner5 0:b7116bd48af6 193 /** \brief Set FPSCR
mturner5 0:b7116bd48af6 194
mturner5 0:b7116bd48af6 195 This function assigns the given value to the Floating Point Status/Control register.
mturner5 0:b7116bd48af6 196
mturner5 0:b7116bd48af6 197 \param [in] fpscr Floating Point Status/Control value to set
mturner5 0:b7116bd48af6 198 */
mturner5 0:b7116bd48af6 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mturner5 0:b7116bd48af6 200 {
mturner5 0:b7116bd48af6 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:b7116bd48af6 202 register uint32_t __regfpscr __ASM("fpscr");
mturner5 0:b7116bd48af6 203 __regfpscr = (fpscr);
mturner5 0:b7116bd48af6 204 #endif
mturner5 0:b7116bd48af6 205 }
mturner5 0:b7116bd48af6 206
mturner5 0:b7116bd48af6 207 /** \brief Get FPEXC
mturner5 0:b7116bd48af6 208
mturner5 0:b7116bd48af6 209 This function returns the current value of the Floating Point Exception Control register.
mturner5 0:b7116bd48af6 210
mturner5 0:b7116bd48af6 211 \return Floating Point Exception Control register value
mturner5 0:b7116bd48af6 212 */
mturner5 0:b7116bd48af6 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
mturner5 0:b7116bd48af6 214 {
mturner5 0:b7116bd48af6 215 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 216 register uint32_t __regfpexc __ASM("fpexc");
mturner5 0:b7116bd48af6 217 return(__regfpexc);
mturner5 0:b7116bd48af6 218 #else
mturner5 0:b7116bd48af6 219 return(0);
mturner5 0:b7116bd48af6 220 #endif
mturner5 0:b7116bd48af6 221 }
mturner5 0:b7116bd48af6 222
mturner5 0:b7116bd48af6 223
mturner5 0:b7116bd48af6 224 /** \brief Set FPEXC
mturner5 0:b7116bd48af6 225
mturner5 0:b7116bd48af6 226 This function assigns the given value to the Floating Point Exception Control register.
mturner5 0:b7116bd48af6 227
mturner5 0:b7116bd48af6 228 \param [in] fpscr Floating Point Exception Control value to set
mturner5 0:b7116bd48af6 229 */
mturner5 0:b7116bd48af6 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
mturner5 0:b7116bd48af6 231 {
mturner5 0:b7116bd48af6 232 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 233 register uint32_t __regfpexc __ASM("fpexc");
mturner5 0:b7116bd48af6 234 __regfpexc = (fpexc);
mturner5 0:b7116bd48af6 235 #endif
mturner5 0:b7116bd48af6 236 }
mturner5 0:b7116bd48af6 237
mturner5 0:b7116bd48af6 238 /** \brief Get CPACR
mturner5 0:b7116bd48af6 239
mturner5 0:b7116bd48af6 240 This function returns the current value of the Coprocessor Access Control register.
mturner5 0:b7116bd48af6 241
mturner5 0:b7116bd48af6 242 \return Coprocessor Access Control register value
mturner5 0:b7116bd48af6 243 */
mturner5 0:b7116bd48af6 244 __STATIC_INLINE uint32_t __get_CPACR(void)
mturner5 0:b7116bd48af6 245 {
mturner5 0:b7116bd48af6 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mturner5 0:b7116bd48af6 247 return __regCPACR;
mturner5 0:b7116bd48af6 248 }
mturner5 0:b7116bd48af6 249
mturner5 0:b7116bd48af6 250 /** \brief Set CPACR
mturner5 0:b7116bd48af6 251
mturner5 0:b7116bd48af6 252 This function assigns the given value to the Coprocessor Access Control register.
mturner5 0:b7116bd48af6 253
mturner5 0:b7116bd48af6 254 \param [in] cpacr Coprocessor Acccess Control value to set
mturner5 0:b7116bd48af6 255 */
mturner5 0:b7116bd48af6 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
mturner5 0:b7116bd48af6 257 {
mturner5 0:b7116bd48af6 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mturner5 0:b7116bd48af6 259 __regCPACR = cpacr;
mturner5 0:b7116bd48af6 260 __ISB();
mturner5 0:b7116bd48af6 261 }
mturner5 0:b7116bd48af6 262
mturner5 0:b7116bd48af6 263 /** \brief Get CBAR
mturner5 0:b7116bd48af6 264
mturner5 0:b7116bd48af6 265 This function returns the value of the Configuration Base Address register.
mturner5 0:b7116bd48af6 266
mturner5 0:b7116bd48af6 267 \return Configuration Base Address register value
mturner5 0:b7116bd48af6 268 */
mturner5 0:b7116bd48af6 269 __STATIC_INLINE uint32_t __get_CBAR() {
mturner5 0:b7116bd48af6 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
mturner5 0:b7116bd48af6 271 return(__regCBAR);
mturner5 0:b7116bd48af6 272 }
mturner5 0:b7116bd48af6 273
mturner5 0:b7116bd48af6 274 /** \brief Get TTBR0
mturner5 0:b7116bd48af6 275
mturner5 0:b7116bd48af6 276 This function returns the value of the Translation Table Base Register 0.
mturner5 0:b7116bd48af6 277
mturner5 0:b7116bd48af6 278 \return Translation Table Base Register 0 value
mturner5 0:b7116bd48af6 279 */
mturner5 0:b7116bd48af6 280 __STATIC_INLINE uint32_t __get_TTBR0() {
mturner5 0:b7116bd48af6 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mturner5 0:b7116bd48af6 282 return(__regTTBR0);
mturner5 0:b7116bd48af6 283 }
mturner5 0:b7116bd48af6 284
mturner5 0:b7116bd48af6 285 /** \brief Set TTBR0
mturner5 0:b7116bd48af6 286
mturner5 0:b7116bd48af6 287 This function assigns the given value to the Translation Table Base Register 0.
mturner5 0:b7116bd48af6 288
mturner5 0:b7116bd48af6 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
mturner5 0:b7116bd48af6 290 */
mturner5 0:b7116bd48af6 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mturner5 0:b7116bd48af6 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mturner5 0:b7116bd48af6 293 __regTTBR0 = ttbr0;
mturner5 0:b7116bd48af6 294 __ISB();
mturner5 0:b7116bd48af6 295 }
mturner5 0:b7116bd48af6 296
mturner5 0:b7116bd48af6 297 /** \brief Get DACR
mturner5 0:b7116bd48af6 298
mturner5 0:b7116bd48af6 299 This function returns the value of the Domain Access Control Register.
mturner5 0:b7116bd48af6 300
mturner5 0:b7116bd48af6 301 \return Domain Access Control Register value
mturner5 0:b7116bd48af6 302 */
mturner5 0:b7116bd48af6 303 __STATIC_INLINE uint32_t __get_DACR() {
mturner5 0:b7116bd48af6 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mturner5 0:b7116bd48af6 305 return(__regDACR);
mturner5 0:b7116bd48af6 306 }
mturner5 0:b7116bd48af6 307
mturner5 0:b7116bd48af6 308 /** \brief Set DACR
mturner5 0:b7116bd48af6 309
mturner5 0:b7116bd48af6 310 This function assigns the given value to the Domain Access Control Register.
mturner5 0:b7116bd48af6 311
mturner5 0:b7116bd48af6 312 \param [in] dacr Domain Access Control Register value to set
mturner5 0:b7116bd48af6 313 */
mturner5 0:b7116bd48af6 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mturner5 0:b7116bd48af6 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mturner5 0:b7116bd48af6 316 __regDACR = dacr;
mturner5 0:b7116bd48af6 317 __ISB();
mturner5 0:b7116bd48af6 318 }
mturner5 0:b7116bd48af6 319
mturner5 0:b7116bd48af6 320 /******************************** Cache and BTAC enable ****************************************************/
mturner5 0:b7116bd48af6 321
mturner5 0:b7116bd48af6 322 /** \brief Set SCTLR
mturner5 0:b7116bd48af6 323
mturner5 0:b7116bd48af6 324 This function assigns the given value to the System Control Register.
mturner5 0:b7116bd48af6 325
mturner5 0:b7116bd48af6 326 \param [in] sctlr System Control Register value to set
mturner5 0:b7116bd48af6 327 */
mturner5 0:b7116bd48af6 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
mturner5 0:b7116bd48af6 329 {
mturner5 0:b7116bd48af6 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mturner5 0:b7116bd48af6 331 __regSCTLR = sctlr;
mturner5 0:b7116bd48af6 332 }
mturner5 0:b7116bd48af6 333
mturner5 0:b7116bd48af6 334 /** \brief Get SCTLR
mturner5 0:b7116bd48af6 335
mturner5 0:b7116bd48af6 336 This function returns the value of the System Control Register.
mturner5 0:b7116bd48af6 337
mturner5 0:b7116bd48af6 338 \return System Control Register value
mturner5 0:b7116bd48af6 339 */
mturner5 0:b7116bd48af6 340 __STATIC_INLINE uint32_t __get_SCTLR() {
mturner5 0:b7116bd48af6 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mturner5 0:b7116bd48af6 342 return(__regSCTLR);
mturner5 0:b7116bd48af6 343 }
mturner5 0:b7116bd48af6 344
mturner5 0:b7116bd48af6 345 /** \brief Enable Caches
mturner5 0:b7116bd48af6 346
mturner5 0:b7116bd48af6 347 Enable Caches
mturner5 0:b7116bd48af6 348 */
mturner5 0:b7116bd48af6 349 __STATIC_INLINE void __enable_caches(void) {
mturner5 0:b7116bd48af6 350 // Set I bit 12 to enable I Cache
mturner5 0:b7116bd48af6 351 // Set C bit 2 to enable D Cache
mturner5 0:b7116bd48af6 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mturner5 0:b7116bd48af6 353 }
mturner5 0:b7116bd48af6 354
mturner5 0:b7116bd48af6 355 /** \brief Disable Caches
mturner5 0:b7116bd48af6 356
mturner5 0:b7116bd48af6 357 Disable Caches
mturner5 0:b7116bd48af6 358 */
mturner5 0:b7116bd48af6 359 __STATIC_INLINE void __disable_caches(void) {
mturner5 0:b7116bd48af6 360 // Clear I bit 12 to disable I Cache
mturner5 0:b7116bd48af6 361 // Clear C bit 2 to disable D Cache
mturner5 0:b7116bd48af6 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
mturner5 0:b7116bd48af6 363 __ISB();
mturner5 0:b7116bd48af6 364 }
mturner5 0:b7116bd48af6 365
mturner5 0:b7116bd48af6 366 /** \brief Enable BTAC
mturner5 0:b7116bd48af6 367
mturner5 0:b7116bd48af6 368 Enable BTAC
mturner5 0:b7116bd48af6 369 */
mturner5 0:b7116bd48af6 370 __STATIC_INLINE void __enable_btac(void) {
mturner5 0:b7116bd48af6 371 // Set Z bit 11 to enable branch prediction
mturner5 0:b7116bd48af6 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
mturner5 0:b7116bd48af6 373 __ISB();
mturner5 0:b7116bd48af6 374 }
mturner5 0:b7116bd48af6 375
mturner5 0:b7116bd48af6 376 /** \brief Disable BTAC
mturner5 0:b7116bd48af6 377
mturner5 0:b7116bd48af6 378 Disable BTAC
mturner5 0:b7116bd48af6 379 */
mturner5 0:b7116bd48af6 380 __STATIC_INLINE void __disable_btac(void) {
mturner5 0:b7116bd48af6 381 // Clear Z bit 11 to disable branch prediction
mturner5 0:b7116bd48af6 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
mturner5 0:b7116bd48af6 383 }
mturner5 0:b7116bd48af6 384
mturner5 0:b7116bd48af6 385
mturner5 0:b7116bd48af6 386 /** \brief Enable MMU
mturner5 0:b7116bd48af6 387
mturner5 0:b7116bd48af6 388 Enable MMU
mturner5 0:b7116bd48af6 389 */
mturner5 0:b7116bd48af6 390 __STATIC_INLINE void __enable_mmu(void) {
mturner5 0:b7116bd48af6 391 // Set M bit 0 to enable the MMU
mturner5 0:b7116bd48af6 392 // Set AFE bit to enable simplified access permissions model
mturner5 0:b7116bd48af6 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mturner5 0:b7116bd48af6 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mturner5 0:b7116bd48af6 395 __ISB();
mturner5 0:b7116bd48af6 396 }
mturner5 0:b7116bd48af6 397
mturner5 0:b7116bd48af6 398 /** \brief Disable MMU
mturner5 0:b7116bd48af6 399
mturner5 0:b7116bd48af6 400 Disable MMU
mturner5 0:b7116bd48af6 401 */
mturner5 0:b7116bd48af6 402 __STATIC_INLINE void __disable_mmu(void) {
mturner5 0:b7116bd48af6 403 // Clear M bit 0 to disable the MMU
mturner5 0:b7116bd48af6 404 __set_SCTLR( __get_SCTLR() & ~1);
mturner5 0:b7116bd48af6 405 __ISB();
mturner5 0:b7116bd48af6 406 }
mturner5 0:b7116bd48af6 407
mturner5 0:b7116bd48af6 408 /******************************** TLB maintenance operations ************************************************/
mturner5 0:b7116bd48af6 409 /** \brief Invalidate the whole tlb
mturner5 0:b7116bd48af6 410
mturner5 0:b7116bd48af6 411 TLBIALL. Invalidate the whole tlb
mturner5 0:b7116bd48af6 412 */
mturner5 0:b7116bd48af6 413
mturner5 0:b7116bd48af6 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mturner5 0:b7116bd48af6 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
mturner5 0:b7116bd48af6 416 __TLBIALL = 0;
mturner5 0:b7116bd48af6 417 __DSB();
mturner5 0:b7116bd48af6 418 __ISB();
mturner5 0:b7116bd48af6 419 }
mturner5 0:b7116bd48af6 420
mturner5 0:b7116bd48af6 421 /******************************** BTB maintenance operations ************************************************/
mturner5 0:b7116bd48af6 422 /** \brief Invalidate entire branch predictor array
mturner5 0:b7116bd48af6 423
mturner5 0:b7116bd48af6 424 BPIALL. Branch Predictor Invalidate All.
mturner5 0:b7116bd48af6 425 */
mturner5 0:b7116bd48af6 426
mturner5 0:b7116bd48af6 427 __STATIC_INLINE void __v7_inv_btac(void) {
mturner5 0:b7116bd48af6 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
mturner5 0:b7116bd48af6 429 __BPIALL = 0;
mturner5 0:b7116bd48af6 430 __DSB(); //ensure completion of the invalidation
mturner5 0:b7116bd48af6 431 __ISB(); //ensure instruction fetch path sees new state
mturner5 0:b7116bd48af6 432 }
mturner5 0:b7116bd48af6 433
mturner5 0:b7116bd48af6 434
mturner5 0:b7116bd48af6 435 /******************************** L1 cache operations ******************************************************/
mturner5 0:b7116bd48af6 436
mturner5 0:b7116bd48af6 437 /** \brief Invalidate the whole I$
mturner5 0:b7116bd48af6 438
mturner5 0:b7116bd48af6 439 ICIALLU. Instruction Cache Invalidate All to PoU
mturner5 0:b7116bd48af6 440 */
mturner5 0:b7116bd48af6 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
mturner5 0:b7116bd48af6 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
mturner5 0:b7116bd48af6 443 __ICIALLU = 0;
mturner5 0:b7116bd48af6 444 __DSB(); //ensure completion of the invalidation
mturner5 0:b7116bd48af6 445 __ISB(); //ensure instruction fetch path sees new I cache state
mturner5 0:b7116bd48af6 446 }
mturner5 0:b7116bd48af6 447
mturner5 0:b7116bd48af6 448 /** \brief Clean D$ by MVA
mturner5 0:b7116bd48af6 449
mturner5 0:b7116bd48af6 450 DCCMVAC. Data cache clean by MVA to PoC
mturner5 0:b7116bd48af6 451 */
mturner5 0:b7116bd48af6 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
mturner5 0:b7116bd48af6 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
mturner5 0:b7116bd48af6 454 __DCCMVAC = (uint32_t)va;
mturner5 0:b7116bd48af6 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mturner5 0:b7116bd48af6 456 }
mturner5 0:b7116bd48af6 457
mturner5 0:b7116bd48af6 458 /** \brief Invalidate D$ by MVA
mturner5 0:b7116bd48af6 459
mturner5 0:b7116bd48af6 460 DCIMVAC. Data cache invalidate by MVA to PoC
mturner5 0:b7116bd48af6 461 */
mturner5 0:b7116bd48af6 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
mturner5 0:b7116bd48af6 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
mturner5 0:b7116bd48af6 464 __DCIMVAC = (uint32_t)va;
mturner5 0:b7116bd48af6 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mturner5 0:b7116bd48af6 466 }
mturner5 0:b7116bd48af6 467
mturner5 0:b7116bd48af6 468 /** \brief Clean and Invalidate D$ by MVA
mturner5 0:b7116bd48af6 469
mturner5 0:b7116bd48af6 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mturner5 0:b7116bd48af6 471 */
mturner5 0:b7116bd48af6 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mturner5 0:b7116bd48af6 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
mturner5 0:b7116bd48af6 474 __DCCIMVAC = (uint32_t)va;
mturner5 0:b7116bd48af6 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mturner5 0:b7116bd48af6 476 }
mturner5 0:b7116bd48af6 477
mturner5 0:b7116bd48af6 478 /** \brief Clean and Invalidate the entire data or unified cache
mturner5 0:b7116bd48af6 479
mturner5 0:b7116bd48af6 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
mturner5 0:b7116bd48af6 481 */
mturner5 0:b7116bd48af6 482 #pragma push
mturner5 0:b7116bd48af6 483 #pragma arm
mturner5 0:b7116bd48af6 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
mturner5 0:b7116bd48af6 485 ARM
mturner5 0:b7116bd48af6 486
mturner5 0:b7116bd48af6 487 PUSH {R4-R11}
mturner5 0:b7116bd48af6 488
mturner5 0:b7116bd48af6 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
mturner5 0:b7116bd48af6 490 ANDS R3, R6, #0x07000000 // Extract coherency level
mturner5 0:b7116bd48af6 491 MOV R3, R3, LSR #23 // Total cache levels << 1
mturner5 0:b7116bd48af6 492 BEQ Finished // If 0, no need to clean
mturner5 0:b7116bd48af6 493
mturner5 0:b7116bd48af6 494 MOV R10, #0 // R10 holds current cache level << 1
mturner5 0:b7116bd48af6 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
mturner5 0:b7116bd48af6 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
mturner5 0:b7116bd48af6 497 AND R1, R1, #7 // Isolate those lower 3 bits
mturner5 0:b7116bd48af6 498 CMP R1, #2
mturner5 0:b7116bd48af6 499 BLT Skip // No cache or only instruction cache at this level
mturner5 0:b7116bd48af6 500
mturner5 0:b7116bd48af6 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
mturner5 0:b7116bd48af6 502 ISB // ISB to sync the change to the CacheSizeID reg
mturner5 0:b7116bd48af6 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
mturner5 0:b7116bd48af6 504 AND R2, R1, #7 // Extract the line length field
mturner5 0:b7116bd48af6 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
mturner5 0:b7116bd48af6 506 LDR R4, =0x3FF
mturner5 0:b7116bd48af6 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
mturner5 0:b7116bd48af6 508 CLZ R5, R4 // R5 is the bit position of the way size increment
mturner5 0:b7116bd48af6 509 LDR R7, =0x7FFF
mturner5 0:b7116bd48af6 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
mturner5 0:b7116bd48af6 511
mturner5 0:b7116bd48af6 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
mturner5 0:b7116bd48af6 513
mturner5 0:b7116bd48af6 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
mturner5 0:b7116bd48af6 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
mturner5 0:b7116bd48af6 516 CMP R0, #0
mturner5 0:b7116bd48af6 517 BNE Dccsw
mturner5 0:b7116bd48af6 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
mturner5 0:b7116bd48af6 519 B cont
mturner5 0:b7116bd48af6 520 Dccsw CMP R0, #1
mturner5 0:b7116bd48af6 521 BNE Dccisw
mturner5 0:b7116bd48af6 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
mturner5 0:b7116bd48af6 523 B cont
mturner5 0:b7116bd48af6 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
mturner5 0:b7116bd48af6 525 cont SUBS R9, R9, #1 // Decrement the Way number
mturner5 0:b7116bd48af6 526 BGE Loop3
mturner5 0:b7116bd48af6 527 SUBS R7, R7, #1 // Decrement the Set number
mturner5 0:b7116bd48af6 528 BGE Loop2
mturner5 0:b7116bd48af6 529 Skip ADD R10, R10, #2 // Increment the cache number
mturner5 0:b7116bd48af6 530 CMP R3, R10
mturner5 0:b7116bd48af6 531 BGT Loop1
mturner5 0:b7116bd48af6 532
mturner5 0:b7116bd48af6 533 Finished
mturner5 0:b7116bd48af6 534 DSB
mturner5 0:b7116bd48af6 535 POP {R4-R11}
mturner5 0:b7116bd48af6 536 BX lr
mturner5 0:b7116bd48af6 537
mturner5 0:b7116bd48af6 538 }
mturner5 0:b7116bd48af6 539 #pragma pop
mturner5 0:b7116bd48af6 540
mturner5 0:b7116bd48af6 541
mturner5 0:b7116bd48af6 542 /** \brief Invalidate the whole D$
mturner5 0:b7116bd48af6 543
mturner5 0:b7116bd48af6 544 DCISW. Invalidate by Set/Way
mturner5 0:b7116bd48af6 545 */
mturner5 0:b7116bd48af6 546
mturner5 0:b7116bd48af6 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
mturner5 0:b7116bd48af6 548 __v7_all_cache(0);
mturner5 0:b7116bd48af6 549 }
mturner5 0:b7116bd48af6 550
mturner5 0:b7116bd48af6 551 /** \brief Clean the whole D$
mturner5 0:b7116bd48af6 552
mturner5 0:b7116bd48af6 553 DCCSW. Clean by Set/Way
mturner5 0:b7116bd48af6 554 */
mturner5 0:b7116bd48af6 555
mturner5 0:b7116bd48af6 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
mturner5 0:b7116bd48af6 557 __v7_all_cache(1);
mturner5 0:b7116bd48af6 558 }
mturner5 0:b7116bd48af6 559
mturner5 0:b7116bd48af6 560 /** \brief Clean and invalidate the whole D$
mturner5 0:b7116bd48af6 561
mturner5 0:b7116bd48af6 562 DCCISW. Clean and Invalidate by Set/Way
mturner5 0:b7116bd48af6 563 */
mturner5 0:b7116bd48af6 564
mturner5 0:b7116bd48af6 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mturner5 0:b7116bd48af6 566 __v7_all_cache(2);
mturner5 0:b7116bd48af6 567 }
mturner5 0:b7116bd48af6 568
mturner5 0:b7116bd48af6 569 #include "core_ca_mmu.h"
mturner5 0:b7116bd48af6 570
mturner5 0:b7116bd48af6 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
mturner5 0:b7116bd48af6 572
mturner5 0:b7116bd48af6 573 #define __inline inline
mturner5 0:b7116bd48af6 574
mturner5 0:b7116bd48af6 575 inline static uint32_t __disable_irq_iar() {
mturner5 0:b7116bd48af6 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
mturner5 0:b7116bd48af6 577 __disable_irq();
mturner5 0:b7116bd48af6 578 return irq_dis;
mturner5 0:b7116bd48af6 579 }
mturner5 0:b7116bd48af6 580
mturner5 0:b7116bd48af6 581 #define MODE_USR 0x10
mturner5 0:b7116bd48af6 582 #define MODE_FIQ 0x11
mturner5 0:b7116bd48af6 583 #define MODE_IRQ 0x12
mturner5 0:b7116bd48af6 584 #define MODE_SVC 0x13
mturner5 0:b7116bd48af6 585 #define MODE_MON 0x16
mturner5 0:b7116bd48af6 586 #define MODE_ABT 0x17
mturner5 0:b7116bd48af6 587 #define MODE_HYP 0x1A
mturner5 0:b7116bd48af6 588 #define MODE_UND 0x1B
mturner5 0:b7116bd48af6 589 #define MODE_SYS 0x1F
mturner5 0:b7116bd48af6 590
mturner5 0:b7116bd48af6 591 /** \brief Set Process Stack Pointer
mturner5 0:b7116bd48af6 592
mturner5 0:b7116bd48af6 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mturner5 0:b7116bd48af6 594
mturner5 0:b7116bd48af6 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mturner5 0:b7116bd48af6 596 */
mturner5 0:b7116bd48af6 597 // from rt_CMSIS.c
mturner5 0:b7116bd48af6 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
mturner5 0:b7116bd48af6 599 __asm(
mturner5 0:b7116bd48af6 600 " ARM\n"
mturner5 0:b7116bd48af6 601 // " PRESERVE8\n"
mturner5 0:b7116bd48af6 602
mturner5 0:b7116bd48af6 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
mturner5 0:b7116bd48af6 604 " MRS R1, CPSR \n"
mturner5 0:b7116bd48af6 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
mturner5 0:b7116bd48af6 606 " MOV SP, R0 \n"
mturner5 0:b7116bd48af6 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
mturner5 0:b7116bd48af6 608 " ISB \n"
mturner5 0:b7116bd48af6 609 " BX LR \n");
mturner5 0:b7116bd48af6 610 }
mturner5 0:b7116bd48af6 611
mturner5 0:b7116bd48af6 612 /** \brief Set User Mode
mturner5 0:b7116bd48af6 613
mturner5 0:b7116bd48af6 614 This function changes the processor state to User Mode
mturner5 0:b7116bd48af6 615 */
mturner5 0:b7116bd48af6 616 // from rt_CMSIS.c
mturner5 0:b7116bd48af6 617 __arm static inline void __set_CPS_USR(void) {
mturner5 0:b7116bd48af6 618 __asm(
mturner5 0:b7116bd48af6 619 " ARM \n"
mturner5 0:b7116bd48af6 620
mturner5 0:b7116bd48af6 621 " CPS #0x10 \n" // MODE_USR
mturner5 0:b7116bd48af6 622 " BX LR\n");
mturner5 0:b7116bd48af6 623 }
mturner5 0:b7116bd48af6 624
mturner5 0:b7116bd48af6 625 /** \brief Set TTBR0
mturner5 0:b7116bd48af6 626
mturner5 0:b7116bd48af6 627 This function assigns the given value to the Translation Table Base Register 0.
mturner5 0:b7116bd48af6 628
mturner5 0:b7116bd48af6 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
mturner5 0:b7116bd48af6 630 */
mturner5 0:b7116bd48af6 631 // from mmu_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mturner5 0:b7116bd48af6 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
mturner5 0:b7116bd48af6 634 __ISB();
mturner5 0:b7116bd48af6 635 }
mturner5 0:b7116bd48af6 636
mturner5 0:b7116bd48af6 637 /** \brief Set DACR
mturner5 0:b7116bd48af6 638
mturner5 0:b7116bd48af6 639 This function assigns the given value to the Domain Access Control Register.
mturner5 0:b7116bd48af6 640
mturner5 0:b7116bd48af6 641 \param [in] dacr Domain Access Control Register value to set
mturner5 0:b7116bd48af6 642 */
mturner5 0:b7116bd48af6 643 // from mmu_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mturner5 0:b7116bd48af6 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
mturner5 0:b7116bd48af6 646 __ISB();
mturner5 0:b7116bd48af6 647 }
mturner5 0:b7116bd48af6 648
mturner5 0:b7116bd48af6 649
mturner5 0:b7116bd48af6 650 /******************************** Cache and BTAC enable ****************************************************/
mturner5 0:b7116bd48af6 651 /** \brief Set SCTLR
mturner5 0:b7116bd48af6 652
mturner5 0:b7116bd48af6 653 This function assigns the given value to the System Control Register.
mturner5 0:b7116bd48af6 654
mturner5 0:b7116bd48af6 655 \param [in] sctlr System Control Register value to set
mturner5 0:b7116bd48af6 656 */
mturner5 0:b7116bd48af6 657 // from __enable_mmu()
mturner5 0:b7116bd48af6 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
mturner5 0:b7116bd48af6 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
mturner5 0:b7116bd48af6 660 }
mturner5 0:b7116bd48af6 661
mturner5 0:b7116bd48af6 662 /** \brief Get SCTLR
mturner5 0:b7116bd48af6 663
mturner5 0:b7116bd48af6 664 This function returns the value of the System Control Register.
mturner5 0:b7116bd48af6 665
mturner5 0:b7116bd48af6 666 \return System Control Register value
mturner5 0:b7116bd48af6 667 */
mturner5 0:b7116bd48af6 668 // from __enable_mmu()
mturner5 0:b7116bd48af6 669 __STATIC_INLINE uint32_t __get_SCTLR() {
mturner5 0:b7116bd48af6 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
mturner5 0:b7116bd48af6 671 return __regSCTLR;
mturner5 0:b7116bd48af6 672 }
mturner5 0:b7116bd48af6 673
mturner5 0:b7116bd48af6 674 /** \brief Enable Caches
mturner5 0:b7116bd48af6 675
mturner5 0:b7116bd48af6 676 Enable Caches
mturner5 0:b7116bd48af6 677 */
mturner5 0:b7116bd48af6 678 // from system_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 679 __STATIC_INLINE void __enable_caches(void) {
mturner5 0:b7116bd48af6 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mturner5 0:b7116bd48af6 681 }
mturner5 0:b7116bd48af6 682
mturner5 0:b7116bd48af6 683 /** \brief Enable BTAC
mturner5 0:b7116bd48af6 684
mturner5 0:b7116bd48af6 685 Enable BTAC
mturner5 0:b7116bd48af6 686 */
mturner5 0:b7116bd48af6 687 // from system_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 688 __STATIC_INLINE void __enable_btac(void) {
mturner5 0:b7116bd48af6 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
mturner5 0:b7116bd48af6 690 __ISB();
mturner5 0:b7116bd48af6 691 }
mturner5 0:b7116bd48af6 692
mturner5 0:b7116bd48af6 693 /** \brief Enable MMU
mturner5 0:b7116bd48af6 694
mturner5 0:b7116bd48af6 695 Enable MMU
mturner5 0:b7116bd48af6 696 */
mturner5 0:b7116bd48af6 697 // from system_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 698 __STATIC_INLINE void __enable_mmu(void) {
mturner5 0:b7116bd48af6 699 // Set M bit 0 to enable the MMU
mturner5 0:b7116bd48af6 700 // Set AFE bit to enable simplified access permissions model
mturner5 0:b7116bd48af6 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mturner5 0:b7116bd48af6 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mturner5 0:b7116bd48af6 703 __ISB();
mturner5 0:b7116bd48af6 704 }
mturner5 0:b7116bd48af6 705
mturner5 0:b7116bd48af6 706 /******************************** TLB maintenance operations ************************************************/
mturner5 0:b7116bd48af6 707 /** \brief Invalidate the whole tlb
mturner5 0:b7116bd48af6 708
mturner5 0:b7116bd48af6 709 TLBIALL. Invalidate the whole tlb
mturner5 0:b7116bd48af6 710 */
mturner5 0:b7116bd48af6 711 // from system_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mturner5 0:b7116bd48af6 713 uint32_t val = 0;
mturner5 0:b7116bd48af6 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
mturner5 0:b7116bd48af6 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
mturner5 0:b7116bd48af6 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
mturner5 0:b7116bd48af6 717 __DSB();
mturner5 0:b7116bd48af6 718 __ISB();
mturner5 0:b7116bd48af6 719 }
mturner5 0:b7116bd48af6 720
mturner5 0:b7116bd48af6 721 /******************************** BTB maintenance operations ************************************************/
mturner5 0:b7116bd48af6 722 /** \brief Invalidate entire branch predictor array
mturner5 0:b7116bd48af6 723
mturner5 0:b7116bd48af6 724 BPIALL. Branch Predictor Invalidate All.
mturner5 0:b7116bd48af6 725 */
mturner5 0:b7116bd48af6 726 // from system_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 727 __STATIC_INLINE void __v7_inv_btac(void) {
mturner5 0:b7116bd48af6 728 uint32_t val = 0;
mturner5 0:b7116bd48af6 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
mturner5 0:b7116bd48af6 730 __DSB(); //ensure completion of the invalidation
mturner5 0:b7116bd48af6 731 __ISB(); //ensure instruction fetch path sees new state
mturner5 0:b7116bd48af6 732 }
mturner5 0:b7116bd48af6 733
mturner5 0:b7116bd48af6 734
mturner5 0:b7116bd48af6 735 /******************************** L1 cache operations ******************************************************/
mturner5 0:b7116bd48af6 736
mturner5 0:b7116bd48af6 737 /** \brief Invalidate the whole I$
mturner5 0:b7116bd48af6 738
mturner5 0:b7116bd48af6 739 ICIALLU. Instruction Cache Invalidate All to PoU
mturner5 0:b7116bd48af6 740 */
mturner5 0:b7116bd48af6 741 // from system_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
mturner5 0:b7116bd48af6 743 uint32_t val = 0;
mturner5 0:b7116bd48af6 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
mturner5 0:b7116bd48af6 745 __DSB(); //ensure completion of the invalidation
mturner5 0:b7116bd48af6 746 __ISB(); //ensure instruction fetch path sees new I cache state
mturner5 0:b7116bd48af6 747 }
mturner5 0:b7116bd48af6 748
mturner5 0:b7116bd48af6 749 // from __v7_inv_dcache_all()
mturner5 0:b7116bd48af6 750 __arm static inline void __v7_all_cache(uint32_t op) {
mturner5 0:b7116bd48af6 751 __asm(
mturner5 0:b7116bd48af6 752 " ARM \n"
mturner5 0:b7116bd48af6 753
mturner5 0:b7116bd48af6 754 " PUSH {R4-R11} \n"
mturner5 0:b7116bd48af6 755
mturner5 0:b7116bd48af6 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
mturner5 0:b7116bd48af6 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
mturner5 0:b7116bd48af6 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
mturner5 0:b7116bd48af6 759 " BEQ Finished\n" // If 0, no need to clean
mturner5 0:b7116bd48af6 760
mturner5 0:b7116bd48af6 761 " MOV R10, #0\n" // R10 holds current cache level << 1
mturner5 0:b7116bd48af6 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
mturner5 0:b7116bd48af6 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
mturner5 0:b7116bd48af6 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
mturner5 0:b7116bd48af6 765 " CMP R1, #2 \n"
mturner5 0:b7116bd48af6 766 " BLT Skip \n" // No cache or only instruction cache at this level
mturner5 0:b7116bd48af6 767
mturner5 0:b7116bd48af6 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
mturner5 0:b7116bd48af6 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
mturner5 0:b7116bd48af6 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
mturner5 0:b7116bd48af6 771 " AND R2, R1, #7 \n" // Extract the line length field
mturner5 0:b7116bd48af6 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
mturner5 0:b7116bd48af6 773 " movw R4, #0x3FF \n"
mturner5 0:b7116bd48af6 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
mturner5 0:b7116bd48af6 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
mturner5 0:b7116bd48af6 776 " movw R7, #0x7FFF \n"
mturner5 0:b7116bd48af6 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
mturner5 0:b7116bd48af6 778
mturner5 0:b7116bd48af6 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
mturner5 0:b7116bd48af6 780
mturner5 0:b7116bd48af6 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
mturner5 0:b7116bd48af6 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
mturner5 0:b7116bd48af6 783 " CMP R0, #0 \n"
mturner5 0:b7116bd48af6 784 " BNE Dccsw \n"
mturner5 0:b7116bd48af6 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
mturner5 0:b7116bd48af6 786 " B cont \n"
mturner5 0:b7116bd48af6 787 "Dccsw: CMP R0, #1 \n"
mturner5 0:b7116bd48af6 788 " BNE Dccisw \n"
mturner5 0:b7116bd48af6 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
mturner5 0:b7116bd48af6 790 " B cont \n"
mturner5 0:b7116bd48af6 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
mturner5 0:b7116bd48af6 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
mturner5 0:b7116bd48af6 793 " BGE Loop3 \n"
mturner5 0:b7116bd48af6 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
mturner5 0:b7116bd48af6 795 " BGE Loop2 \n"
mturner5 0:b7116bd48af6 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
mturner5 0:b7116bd48af6 797 " CMP R3, R10 \n"
mturner5 0:b7116bd48af6 798 " BGT Loop1 \n"
mturner5 0:b7116bd48af6 799
mturner5 0:b7116bd48af6 800 "Finished: \n"
mturner5 0:b7116bd48af6 801 " DSB \n"
mturner5 0:b7116bd48af6 802 " POP {R4-R11} \n"
mturner5 0:b7116bd48af6 803 " BX lr \n" );
mturner5 0:b7116bd48af6 804 }
mturner5 0:b7116bd48af6 805
mturner5 0:b7116bd48af6 806 /** \brief Invalidate the whole D$
mturner5 0:b7116bd48af6 807
mturner5 0:b7116bd48af6 808 DCISW. Invalidate by Set/Way
mturner5 0:b7116bd48af6 809 */
mturner5 0:b7116bd48af6 810 // from system_Renesas_RZ_A1.c
mturner5 0:b7116bd48af6 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
mturner5 0:b7116bd48af6 812 __v7_all_cache(0);
mturner5 0:b7116bd48af6 813 }
mturner5 0:b7116bd48af6 814 /** \brief Clean and Invalidate D$ by MVA
mturner5 0:b7116bd48af6 815
mturner5 0:b7116bd48af6 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mturner5 0:b7116bd48af6 817 */
mturner5 0:b7116bd48af6 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mturner5 0:b7116bd48af6 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
mturner5 0:b7116bd48af6 820 __DMB();
mturner5 0:b7116bd48af6 821 }
mturner5 0:b7116bd48af6 822
mturner5 0:b7116bd48af6 823 #include "core_ca_mmu.h"
mturner5 0:b7116bd48af6 824
mturner5 0:b7116bd48af6 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
mturner5 0:b7116bd48af6 826 /* GNU gcc specific functions */
mturner5 0:b7116bd48af6 827
mturner5 0:b7116bd48af6 828 #define MODE_USR 0x10
mturner5 0:b7116bd48af6 829 #define MODE_FIQ 0x11
mturner5 0:b7116bd48af6 830 #define MODE_IRQ 0x12
mturner5 0:b7116bd48af6 831 #define MODE_SVC 0x13
mturner5 0:b7116bd48af6 832 #define MODE_MON 0x16
mturner5 0:b7116bd48af6 833 #define MODE_ABT 0x17
mturner5 0:b7116bd48af6 834 #define MODE_HYP 0x1A
mturner5 0:b7116bd48af6 835 #define MODE_UND 0x1B
mturner5 0:b7116bd48af6 836 #define MODE_SYS 0x1F
mturner5 0:b7116bd48af6 837
mturner5 0:b7116bd48af6 838
mturner5 0:b7116bd48af6 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
mturner5 0:b7116bd48af6 840 {
mturner5 0:b7116bd48af6 841 __ASM volatile ("cpsie i");
mturner5 0:b7116bd48af6 842 }
mturner5 0:b7116bd48af6 843
mturner5 0:b7116bd48af6 844 /** \brief Disable IRQ Interrupts
mturner5 0:b7116bd48af6 845
mturner5 0:b7116bd48af6 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
mturner5 0:b7116bd48af6 847 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 848 */
mturner5 0:b7116bd48af6 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
mturner5 0:b7116bd48af6 850 {
mturner5 0:b7116bd48af6 851 uint32_t result;
mturner5 0:b7116bd48af6 852
mturner5 0:b7116bd48af6 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
mturner5 0:b7116bd48af6 854 __ASM volatile ("cpsid i");
mturner5 0:b7116bd48af6 855 return(result & 0x80);
mturner5 0:b7116bd48af6 856 }
mturner5 0:b7116bd48af6 857
mturner5 0:b7116bd48af6 858
mturner5 0:b7116bd48af6 859 /** \brief Get APSR Register
mturner5 0:b7116bd48af6 860
mturner5 0:b7116bd48af6 861 This function returns the content of the APSR Register.
mturner5 0:b7116bd48af6 862
mturner5 0:b7116bd48af6 863 \return APSR Register value
mturner5 0:b7116bd48af6 864 */
mturner5 0:b7116bd48af6 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
mturner5 0:b7116bd48af6 866 {
mturner5 0:b7116bd48af6 867 #if 1
mturner5 0:b7116bd48af6 868 register uint32_t __regAPSR;
mturner5 0:b7116bd48af6 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
mturner5 0:b7116bd48af6 870 #else
mturner5 0:b7116bd48af6 871 register uint32_t __regAPSR __ASM("apsr");
mturner5 0:b7116bd48af6 872 #endif
mturner5 0:b7116bd48af6 873 return(__regAPSR);
mturner5 0:b7116bd48af6 874 }
mturner5 0:b7116bd48af6 875
mturner5 0:b7116bd48af6 876
mturner5 0:b7116bd48af6 877 /** \brief Get CPSR Register
mturner5 0:b7116bd48af6 878
mturner5 0:b7116bd48af6 879 This function returns the content of the CPSR Register.
mturner5 0:b7116bd48af6 880
mturner5 0:b7116bd48af6 881 \return CPSR Register value
mturner5 0:b7116bd48af6 882 */
mturner5 0:b7116bd48af6 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
mturner5 0:b7116bd48af6 884 {
mturner5 0:b7116bd48af6 885 #if 1
mturner5 0:b7116bd48af6 886 register uint32_t __regCPSR;
mturner5 0:b7116bd48af6 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
mturner5 0:b7116bd48af6 888 #else
mturner5 0:b7116bd48af6 889 register uint32_t __regCPSR __ASM("cpsr");
mturner5 0:b7116bd48af6 890 #endif
mturner5 0:b7116bd48af6 891 return(__regCPSR);
mturner5 0:b7116bd48af6 892 }
mturner5 0:b7116bd48af6 893
mturner5 0:b7116bd48af6 894 #if 0
mturner5 0:b7116bd48af6 895 /** \brief Set Stack Pointer
mturner5 0:b7116bd48af6 896
mturner5 0:b7116bd48af6 897 This function assigns the given value to the current stack pointer.
mturner5 0:b7116bd48af6 898
mturner5 0:b7116bd48af6 899 \param [in] topOfStack Stack Pointer value to set
mturner5 0:b7116bd48af6 900 */
mturner5 0:b7116bd48af6 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
mturner5 0:b7116bd48af6 902 {
mturner5 0:b7116bd48af6 903 register uint32_t __regSP __ASM("sp");
mturner5 0:b7116bd48af6 904 __regSP = topOfStack;
mturner5 0:b7116bd48af6 905 }
mturner5 0:b7116bd48af6 906 #endif
mturner5 0:b7116bd48af6 907
mturner5 0:b7116bd48af6 908 /** \brief Get link register
mturner5 0:b7116bd48af6 909
mturner5 0:b7116bd48af6 910 This function returns the value of the link register
mturner5 0:b7116bd48af6 911
mturner5 0:b7116bd48af6 912 \return Value of link register
mturner5 0:b7116bd48af6 913 */
mturner5 0:b7116bd48af6 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
mturner5 0:b7116bd48af6 915 {
mturner5 0:b7116bd48af6 916 register uint32_t __reglr __ASM("lr");
mturner5 0:b7116bd48af6 917 return(__reglr);
mturner5 0:b7116bd48af6 918 }
mturner5 0:b7116bd48af6 919
mturner5 0:b7116bd48af6 920 #if 0
mturner5 0:b7116bd48af6 921 /** \brief Set link register
mturner5 0:b7116bd48af6 922
mturner5 0:b7116bd48af6 923 This function sets the value of the link register
mturner5 0:b7116bd48af6 924
mturner5 0:b7116bd48af6 925 \param [in] lr LR value to set
mturner5 0:b7116bd48af6 926 */
mturner5 0:b7116bd48af6 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
mturner5 0:b7116bd48af6 928 {
mturner5 0:b7116bd48af6 929 register uint32_t __reglr __ASM("lr");
mturner5 0:b7116bd48af6 930 __reglr = lr;
mturner5 0:b7116bd48af6 931 }
mturner5 0:b7116bd48af6 932 #endif
mturner5 0:b7116bd48af6 933
mturner5 0:b7116bd48af6 934 /** \brief Set Process Stack Pointer
mturner5 0:b7116bd48af6 935
mturner5 0:b7116bd48af6 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mturner5 0:b7116bd48af6 937
mturner5 0:b7116bd48af6 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mturner5 0:b7116bd48af6 939 */
mturner5 0:b7116bd48af6 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mturner5 0:b7116bd48af6 941 {
mturner5 0:b7116bd48af6 942 __asm__ volatile (
mturner5 0:b7116bd48af6 943 ".ARM;"
mturner5 0:b7116bd48af6 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
mturner5 0:b7116bd48af6 945
mturner5 0:b7116bd48af6 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
mturner5 0:b7116bd48af6 947 "MRS R1, CPSR;"
mturner5 0:b7116bd48af6 948 "CPS %0;" /* ;no effect in USR mode */
mturner5 0:b7116bd48af6 949 "MOV SP, R0;"
mturner5 0:b7116bd48af6 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
mturner5 0:b7116bd48af6 951 "ISB;"
mturner5 0:b7116bd48af6 952 //"BX LR;"
mturner5 0:b7116bd48af6 953 :
mturner5 0:b7116bd48af6 954 : "i"(MODE_SYS)
mturner5 0:b7116bd48af6 955 : "r0", "r1");
mturner5 0:b7116bd48af6 956 return;
mturner5 0:b7116bd48af6 957 }
mturner5 0:b7116bd48af6 958
mturner5 0:b7116bd48af6 959 /** \brief Set User Mode
mturner5 0:b7116bd48af6 960
mturner5 0:b7116bd48af6 961 This function changes the processor state to User Mode
mturner5 0:b7116bd48af6 962 */
mturner5 0:b7116bd48af6 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
mturner5 0:b7116bd48af6 964 {
mturner5 0:b7116bd48af6 965 __asm__ volatile (
mturner5 0:b7116bd48af6 966 ".ARM;"
mturner5 0:b7116bd48af6 967
mturner5 0:b7116bd48af6 968 "CPS %0;"
mturner5 0:b7116bd48af6 969 //"BX LR;"
mturner5 0:b7116bd48af6 970 :
mturner5 0:b7116bd48af6 971 : "i"(MODE_USR)
mturner5 0:b7116bd48af6 972 : );
mturner5 0:b7116bd48af6 973 return;
mturner5 0:b7116bd48af6 974 }
mturner5 0:b7116bd48af6 975
mturner5 0:b7116bd48af6 976
mturner5 0:b7116bd48af6 977 /** \brief Enable FIQ
mturner5 0:b7116bd48af6 978
mturner5 0:b7116bd48af6 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mturner5 0:b7116bd48af6 980 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 981 */
mturner5 0:b7116bd48af6 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
mturner5 0:b7116bd48af6 983
mturner5 0:b7116bd48af6 984
mturner5 0:b7116bd48af6 985 /** \brief Disable FIQ
mturner5 0:b7116bd48af6 986
mturner5 0:b7116bd48af6 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mturner5 0:b7116bd48af6 988 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 989 */
mturner5 0:b7116bd48af6 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
mturner5 0:b7116bd48af6 991
mturner5 0:b7116bd48af6 992
mturner5 0:b7116bd48af6 993 /** \brief Get FPSCR
mturner5 0:b7116bd48af6 994
mturner5 0:b7116bd48af6 995 This function returns the current value of the Floating Point Status/Control register.
mturner5 0:b7116bd48af6 996
mturner5 0:b7116bd48af6 997 \return Floating Point Status/Control register value
mturner5 0:b7116bd48af6 998 */
mturner5 0:b7116bd48af6 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
mturner5 0:b7116bd48af6 1000 {
mturner5 0:b7116bd48af6 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:b7116bd48af6 1002 #if 1
mturner5 0:b7116bd48af6 1003 uint32_t result;
mturner5 0:b7116bd48af6 1004
mturner5 0:b7116bd48af6 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
mturner5 0:b7116bd48af6 1006 return (result);
mturner5 0:b7116bd48af6 1007 #else
mturner5 0:b7116bd48af6 1008 register uint32_t __regfpscr __ASM("fpscr");
mturner5 0:b7116bd48af6 1009 return(__regfpscr);
mturner5 0:b7116bd48af6 1010 #endif
mturner5 0:b7116bd48af6 1011 #else
mturner5 0:b7116bd48af6 1012 return(0);
mturner5 0:b7116bd48af6 1013 #endif
mturner5 0:b7116bd48af6 1014 }
mturner5 0:b7116bd48af6 1015
mturner5 0:b7116bd48af6 1016
mturner5 0:b7116bd48af6 1017 /** \brief Set FPSCR
mturner5 0:b7116bd48af6 1018
mturner5 0:b7116bd48af6 1019 This function assigns the given value to the Floating Point Status/Control register.
mturner5 0:b7116bd48af6 1020
mturner5 0:b7116bd48af6 1021 \param [in] fpscr Floating Point Status/Control value to set
mturner5 0:b7116bd48af6 1022 */
mturner5 0:b7116bd48af6 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mturner5 0:b7116bd48af6 1024 {
mturner5 0:b7116bd48af6 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:b7116bd48af6 1026 #if 1
mturner5 0:b7116bd48af6 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
mturner5 0:b7116bd48af6 1028 #else
mturner5 0:b7116bd48af6 1029 register uint32_t __regfpscr __ASM("fpscr");
mturner5 0:b7116bd48af6 1030 __regfpscr = (fpscr);
mturner5 0:b7116bd48af6 1031 #endif
mturner5 0:b7116bd48af6 1032 #endif
mturner5 0:b7116bd48af6 1033 }
mturner5 0:b7116bd48af6 1034
mturner5 0:b7116bd48af6 1035 /** \brief Get FPEXC
mturner5 0:b7116bd48af6 1036
mturner5 0:b7116bd48af6 1037 This function returns the current value of the Floating Point Exception Control register.
mturner5 0:b7116bd48af6 1038
mturner5 0:b7116bd48af6 1039 \return Floating Point Exception Control register value
mturner5 0:b7116bd48af6 1040 */
mturner5 0:b7116bd48af6 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
mturner5 0:b7116bd48af6 1042 {
mturner5 0:b7116bd48af6 1043 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 1044 #if 1
mturner5 0:b7116bd48af6 1045 uint32_t result;
mturner5 0:b7116bd48af6 1046
mturner5 0:b7116bd48af6 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
mturner5 0:b7116bd48af6 1048 return (result);
mturner5 0:b7116bd48af6 1049 #else
mturner5 0:b7116bd48af6 1050 register uint32_t __regfpexc __ASM("fpexc");
mturner5 0:b7116bd48af6 1051 return(__regfpexc);
mturner5 0:b7116bd48af6 1052 #endif
mturner5 0:b7116bd48af6 1053 #else
mturner5 0:b7116bd48af6 1054 return(0);
mturner5 0:b7116bd48af6 1055 #endif
mturner5 0:b7116bd48af6 1056 }
mturner5 0:b7116bd48af6 1057
mturner5 0:b7116bd48af6 1058
mturner5 0:b7116bd48af6 1059 /** \brief Set FPEXC
mturner5 0:b7116bd48af6 1060
mturner5 0:b7116bd48af6 1061 This function assigns the given value to the Floating Point Exception Control register.
mturner5 0:b7116bd48af6 1062
mturner5 0:b7116bd48af6 1063 \param [in] fpscr Floating Point Exception Control value to set
mturner5 0:b7116bd48af6 1064 */
mturner5 0:b7116bd48af6 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
mturner5 0:b7116bd48af6 1066 {
mturner5 0:b7116bd48af6 1067 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 1068 #if 1
mturner5 0:b7116bd48af6 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
mturner5 0:b7116bd48af6 1070 #else
mturner5 0:b7116bd48af6 1071 register uint32_t __regfpexc __ASM("fpexc");
mturner5 0:b7116bd48af6 1072 __regfpexc = (fpexc);
mturner5 0:b7116bd48af6 1073 #endif
mturner5 0:b7116bd48af6 1074 #endif
mturner5 0:b7116bd48af6 1075 }
mturner5 0:b7116bd48af6 1076
mturner5 0:b7116bd48af6 1077 /** \brief Get CPACR
mturner5 0:b7116bd48af6 1078
mturner5 0:b7116bd48af6 1079 This function returns the current value of the Coprocessor Access Control register.
mturner5 0:b7116bd48af6 1080
mturner5 0:b7116bd48af6 1081 \return Coprocessor Access Control register value
mturner5 0:b7116bd48af6 1082 */
mturner5 0:b7116bd48af6 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
mturner5 0:b7116bd48af6 1084 {
mturner5 0:b7116bd48af6 1085 #if 1
mturner5 0:b7116bd48af6 1086 register uint32_t __regCPACR;
mturner5 0:b7116bd48af6 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
mturner5 0:b7116bd48af6 1088 #else
mturner5 0:b7116bd48af6 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mturner5 0:b7116bd48af6 1090 #endif
mturner5 0:b7116bd48af6 1091 return __regCPACR;
mturner5 0:b7116bd48af6 1092 }
mturner5 0:b7116bd48af6 1093
mturner5 0:b7116bd48af6 1094 /** \brief Set CPACR
mturner5 0:b7116bd48af6 1095
mturner5 0:b7116bd48af6 1096 This function assigns the given value to the Coprocessor Access Control register.
mturner5 0:b7116bd48af6 1097
mturner5 0:b7116bd48af6 1098 \param [in] cpacr Coprocessor Acccess Control value to set
mturner5 0:b7116bd48af6 1099 */
mturner5 0:b7116bd48af6 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
mturner5 0:b7116bd48af6 1101 {
mturner5 0:b7116bd48af6 1102 #if 1
mturner5 0:b7116bd48af6 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
mturner5 0:b7116bd48af6 1104 #else
mturner5 0:b7116bd48af6 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mturner5 0:b7116bd48af6 1106 __regCPACR = cpacr;
mturner5 0:b7116bd48af6 1107 #endif
mturner5 0:b7116bd48af6 1108 __ISB();
mturner5 0:b7116bd48af6 1109 }
mturner5 0:b7116bd48af6 1110
mturner5 0:b7116bd48af6 1111 /** \brief Get CBAR
mturner5 0:b7116bd48af6 1112
mturner5 0:b7116bd48af6 1113 This function returns the value of the Configuration Base Address register.
mturner5 0:b7116bd48af6 1114
mturner5 0:b7116bd48af6 1115 \return Configuration Base Address register value
mturner5 0:b7116bd48af6 1116 */
mturner5 0:b7116bd48af6 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
mturner5 0:b7116bd48af6 1118 #if 1
mturner5 0:b7116bd48af6 1119 register uint32_t __regCBAR;
mturner5 0:b7116bd48af6 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
mturner5 0:b7116bd48af6 1121 #else
mturner5 0:b7116bd48af6 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
mturner5 0:b7116bd48af6 1123 #endif
mturner5 0:b7116bd48af6 1124 return(__regCBAR);
mturner5 0:b7116bd48af6 1125 }
mturner5 0:b7116bd48af6 1126
mturner5 0:b7116bd48af6 1127 /** \brief Get TTBR0
mturner5 0:b7116bd48af6 1128
mturner5 0:b7116bd48af6 1129 This function returns the value of the Translation Table Base Register 0.
mturner5 0:b7116bd48af6 1130
mturner5 0:b7116bd48af6 1131 \return Translation Table Base Register 0 value
mturner5 0:b7116bd48af6 1132 */
mturner5 0:b7116bd48af6 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
mturner5 0:b7116bd48af6 1134 #if 1
mturner5 0:b7116bd48af6 1135 register uint32_t __regTTBR0;
mturner5 0:b7116bd48af6 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
mturner5 0:b7116bd48af6 1137 #else
mturner5 0:b7116bd48af6 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mturner5 0:b7116bd48af6 1139 #endif
mturner5 0:b7116bd48af6 1140 return(__regTTBR0);
mturner5 0:b7116bd48af6 1141 }
mturner5 0:b7116bd48af6 1142
mturner5 0:b7116bd48af6 1143 /** \brief Set TTBR0
mturner5 0:b7116bd48af6 1144
mturner5 0:b7116bd48af6 1145 This function assigns the given value to the Translation Table Base Register 0.
mturner5 0:b7116bd48af6 1146
mturner5 0:b7116bd48af6 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
mturner5 0:b7116bd48af6 1148 */
mturner5 0:b7116bd48af6 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mturner5 0:b7116bd48af6 1150 #if 1
mturner5 0:b7116bd48af6 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
mturner5 0:b7116bd48af6 1152 #else
mturner5 0:b7116bd48af6 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mturner5 0:b7116bd48af6 1154 __regTTBR0 = ttbr0;
mturner5 0:b7116bd48af6 1155 #endif
mturner5 0:b7116bd48af6 1156 __ISB();
mturner5 0:b7116bd48af6 1157 }
mturner5 0:b7116bd48af6 1158
mturner5 0:b7116bd48af6 1159 /** \brief Get DACR
mturner5 0:b7116bd48af6 1160
mturner5 0:b7116bd48af6 1161 This function returns the value of the Domain Access Control Register.
mturner5 0:b7116bd48af6 1162
mturner5 0:b7116bd48af6 1163 \return Domain Access Control Register value
mturner5 0:b7116bd48af6 1164 */
mturner5 0:b7116bd48af6 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
mturner5 0:b7116bd48af6 1166 #if 1
mturner5 0:b7116bd48af6 1167 register uint32_t __regDACR;
mturner5 0:b7116bd48af6 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
mturner5 0:b7116bd48af6 1169 #else
mturner5 0:b7116bd48af6 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mturner5 0:b7116bd48af6 1171 #endif
mturner5 0:b7116bd48af6 1172 return(__regDACR);
mturner5 0:b7116bd48af6 1173 }
mturner5 0:b7116bd48af6 1174
mturner5 0:b7116bd48af6 1175 /** \brief Set DACR
mturner5 0:b7116bd48af6 1176
mturner5 0:b7116bd48af6 1177 This function assigns the given value to the Domain Access Control Register.
mturner5 0:b7116bd48af6 1178
mturner5 0:b7116bd48af6 1179 \param [in] dacr Domain Access Control Register value to set
mturner5 0:b7116bd48af6 1180 */
mturner5 0:b7116bd48af6 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mturner5 0:b7116bd48af6 1182 #if 1
mturner5 0:b7116bd48af6 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
mturner5 0:b7116bd48af6 1184 #else
mturner5 0:b7116bd48af6 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mturner5 0:b7116bd48af6 1186 __regDACR = dacr;
mturner5 0:b7116bd48af6 1187 #endif
mturner5 0:b7116bd48af6 1188 __ISB();
mturner5 0:b7116bd48af6 1189 }
mturner5 0:b7116bd48af6 1190
mturner5 0:b7116bd48af6 1191 /******************************** Cache and BTAC enable ****************************************************/
mturner5 0:b7116bd48af6 1192
mturner5 0:b7116bd48af6 1193 /** \brief Set SCTLR
mturner5 0:b7116bd48af6 1194
mturner5 0:b7116bd48af6 1195 This function assigns the given value to the System Control Register.
mturner5 0:b7116bd48af6 1196
mturner5 0:b7116bd48af6 1197 \param [in] sctlr System Control Register value to set
mturner5 0:b7116bd48af6 1198 */
mturner5 0:b7116bd48af6 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
mturner5 0:b7116bd48af6 1200 {
mturner5 0:b7116bd48af6 1201 #if 1
mturner5 0:b7116bd48af6 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
mturner5 0:b7116bd48af6 1203 #else
mturner5 0:b7116bd48af6 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mturner5 0:b7116bd48af6 1205 __regSCTLR = sctlr;
mturner5 0:b7116bd48af6 1206 #endif
mturner5 0:b7116bd48af6 1207 }
mturner5 0:b7116bd48af6 1208
mturner5 0:b7116bd48af6 1209 /** \brief Get SCTLR
mturner5 0:b7116bd48af6 1210
mturner5 0:b7116bd48af6 1211 This function returns the value of the System Control Register.
mturner5 0:b7116bd48af6 1212
mturner5 0:b7116bd48af6 1213 \return System Control Register value
mturner5 0:b7116bd48af6 1214 */
mturner5 0:b7116bd48af6 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
mturner5 0:b7116bd48af6 1216 #if 1
mturner5 0:b7116bd48af6 1217 register uint32_t __regSCTLR;
mturner5 0:b7116bd48af6 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
mturner5 0:b7116bd48af6 1219 #else
mturner5 0:b7116bd48af6 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mturner5 0:b7116bd48af6 1221 #endif
mturner5 0:b7116bd48af6 1222 return(__regSCTLR);
mturner5 0:b7116bd48af6 1223 }
mturner5 0:b7116bd48af6 1224
mturner5 0:b7116bd48af6 1225 /** \brief Enable Caches
mturner5 0:b7116bd48af6 1226
mturner5 0:b7116bd48af6 1227 Enable Caches
mturner5 0:b7116bd48af6 1228 */
mturner5 0:b7116bd48af6 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
mturner5 0:b7116bd48af6 1230 // Set I bit 12 to enable I Cache
mturner5 0:b7116bd48af6 1231 // Set C bit 2 to enable D Cache
mturner5 0:b7116bd48af6 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mturner5 0:b7116bd48af6 1233 }
mturner5 0:b7116bd48af6 1234
mturner5 0:b7116bd48af6 1235 /** \brief Disable Caches
mturner5 0:b7116bd48af6 1236
mturner5 0:b7116bd48af6 1237 Disable Caches
mturner5 0:b7116bd48af6 1238 */
mturner5 0:b7116bd48af6 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
mturner5 0:b7116bd48af6 1240 // Clear I bit 12 to disable I Cache
mturner5 0:b7116bd48af6 1241 // Clear C bit 2 to disable D Cache
mturner5 0:b7116bd48af6 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
mturner5 0:b7116bd48af6 1243 __ISB();
mturner5 0:b7116bd48af6 1244 }
mturner5 0:b7116bd48af6 1245
mturner5 0:b7116bd48af6 1246 /** \brief Enable BTAC
mturner5 0:b7116bd48af6 1247
mturner5 0:b7116bd48af6 1248 Enable BTAC
mturner5 0:b7116bd48af6 1249 */
mturner5 0:b7116bd48af6 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
mturner5 0:b7116bd48af6 1251 // Set Z bit 11 to enable branch prediction
mturner5 0:b7116bd48af6 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
mturner5 0:b7116bd48af6 1253 __ISB();
mturner5 0:b7116bd48af6 1254 }
mturner5 0:b7116bd48af6 1255
mturner5 0:b7116bd48af6 1256 /** \brief Disable BTAC
mturner5 0:b7116bd48af6 1257
mturner5 0:b7116bd48af6 1258 Disable BTAC
mturner5 0:b7116bd48af6 1259 */
mturner5 0:b7116bd48af6 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
mturner5 0:b7116bd48af6 1261 // Clear Z bit 11 to disable branch prediction
mturner5 0:b7116bd48af6 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
mturner5 0:b7116bd48af6 1263 }
mturner5 0:b7116bd48af6 1264
mturner5 0:b7116bd48af6 1265
mturner5 0:b7116bd48af6 1266 /** \brief Enable MMU
mturner5 0:b7116bd48af6 1267
mturner5 0:b7116bd48af6 1268 Enable MMU
mturner5 0:b7116bd48af6 1269 */
mturner5 0:b7116bd48af6 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
mturner5 0:b7116bd48af6 1271 // Set M bit 0 to enable the MMU
mturner5 0:b7116bd48af6 1272 // Set AFE bit to enable simplified access permissions model
mturner5 0:b7116bd48af6 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mturner5 0:b7116bd48af6 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mturner5 0:b7116bd48af6 1275 __ISB();
mturner5 0:b7116bd48af6 1276 }
mturner5 0:b7116bd48af6 1277
mturner5 0:b7116bd48af6 1278 /** \brief Disable MMU
mturner5 0:b7116bd48af6 1279
mturner5 0:b7116bd48af6 1280 Disable MMU
mturner5 0:b7116bd48af6 1281 */
mturner5 0:b7116bd48af6 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
mturner5 0:b7116bd48af6 1283 // Clear M bit 0 to disable the MMU
mturner5 0:b7116bd48af6 1284 __set_SCTLR( __get_SCTLR() & ~1);
mturner5 0:b7116bd48af6 1285 __ISB();
mturner5 0:b7116bd48af6 1286 }
mturner5 0:b7116bd48af6 1287
mturner5 0:b7116bd48af6 1288 /******************************** TLB maintenance operations ************************************************/
mturner5 0:b7116bd48af6 1289 /** \brief Invalidate the whole tlb
mturner5 0:b7116bd48af6 1290
mturner5 0:b7116bd48af6 1291 TLBIALL. Invalidate the whole tlb
mturner5 0:b7116bd48af6 1292 */
mturner5 0:b7116bd48af6 1293
mturner5 0:b7116bd48af6 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mturner5 0:b7116bd48af6 1295 #if 1
mturner5 0:b7116bd48af6 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
mturner5 0:b7116bd48af6 1297 #else
mturner5 0:b7116bd48af6 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
mturner5 0:b7116bd48af6 1299 __TLBIALL = 0;
mturner5 0:b7116bd48af6 1300 #endif
mturner5 0:b7116bd48af6 1301 __DSB();
mturner5 0:b7116bd48af6 1302 __ISB();
mturner5 0:b7116bd48af6 1303 }
mturner5 0:b7116bd48af6 1304
mturner5 0:b7116bd48af6 1305 /******************************** BTB maintenance operations ************************************************/
mturner5 0:b7116bd48af6 1306 /** \brief Invalidate entire branch predictor array
mturner5 0:b7116bd48af6 1307
mturner5 0:b7116bd48af6 1308 BPIALL. Branch Predictor Invalidate All.
mturner5 0:b7116bd48af6 1309 */
mturner5 0:b7116bd48af6 1310
mturner5 0:b7116bd48af6 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
mturner5 0:b7116bd48af6 1312 #if 1
mturner5 0:b7116bd48af6 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
mturner5 0:b7116bd48af6 1314 #else
mturner5 0:b7116bd48af6 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
mturner5 0:b7116bd48af6 1316 __BPIALL = 0;
mturner5 0:b7116bd48af6 1317 #endif
mturner5 0:b7116bd48af6 1318 __DSB(); //ensure completion of the invalidation
mturner5 0:b7116bd48af6 1319 __ISB(); //ensure instruction fetch path sees new state
mturner5 0:b7116bd48af6 1320 }
mturner5 0:b7116bd48af6 1321
mturner5 0:b7116bd48af6 1322
mturner5 0:b7116bd48af6 1323 /******************************** L1 cache operations ******************************************************/
mturner5 0:b7116bd48af6 1324
mturner5 0:b7116bd48af6 1325 /** \brief Invalidate the whole I$
mturner5 0:b7116bd48af6 1326
mturner5 0:b7116bd48af6 1327 ICIALLU. Instruction Cache Invalidate All to PoU
mturner5 0:b7116bd48af6 1328 */
mturner5 0:b7116bd48af6 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
mturner5 0:b7116bd48af6 1330 #if 1
mturner5 0:b7116bd48af6 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
mturner5 0:b7116bd48af6 1332 #else
mturner5 0:b7116bd48af6 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
mturner5 0:b7116bd48af6 1334 __ICIALLU = 0;
mturner5 0:b7116bd48af6 1335 #endif
mturner5 0:b7116bd48af6 1336 __DSB(); //ensure completion of the invalidation
mturner5 0:b7116bd48af6 1337 __ISB(); //ensure instruction fetch path sees new I cache state
mturner5 0:b7116bd48af6 1338 }
mturner5 0:b7116bd48af6 1339
mturner5 0:b7116bd48af6 1340 /** \brief Clean D$ by MVA
mturner5 0:b7116bd48af6 1341
mturner5 0:b7116bd48af6 1342 DCCMVAC. Data cache clean by MVA to PoC
mturner5 0:b7116bd48af6 1343 */
mturner5 0:b7116bd48af6 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
mturner5 0:b7116bd48af6 1345 #if 1
mturner5 0:b7116bd48af6 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
mturner5 0:b7116bd48af6 1347 #else
mturner5 0:b7116bd48af6 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
mturner5 0:b7116bd48af6 1349 __DCCMVAC = (uint32_t)va;
mturner5 0:b7116bd48af6 1350 #endif
mturner5 0:b7116bd48af6 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mturner5 0:b7116bd48af6 1352 }
mturner5 0:b7116bd48af6 1353
mturner5 0:b7116bd48af6 1354 /** \brief Invalidate D$ by MVA
mturner5 0:b7116bd48af6 1355
mturner5 0:b7116bd48af6 1356 DCIMVAC. Data cache invalidate by MVA to PoC
mturner5 0:b7116bd48af6 1357 */
mturner5 0:b7116bd48af6 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
mturner5 0:b7116bd48af6 1359 #if 1
mturner5 0:b7116bd48af6 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
mturner5 0:b7116bd48af6 1361 #else
mturner5 0:b7116bd48af6 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
mturner5 0:b7116bd48af6 1363 __DCIMVAC = (uint32_t)va;
mturner5 0:b7116bd48af6 1364 #endif
mturner5 0:b7116bd48af6 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mturner5 0:b7116bd48af6 1366 }
mturner5 0:b7116bd48af6 1367
mturner5 0:b7116bd48af6 1368 /** \brief Clean and Invalidate D$ by MVA
mturner5 0:b7116bd48af6 1369
mturner5 0:b7116bd48af6 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mturner5 0:b7116bd48af6 1371 */
mturner5 0:b7116bd48af6 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mturner5 0:b7116bd48af6 1373 #if 1
mturner5 0:b7116bd48af6 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
mturner5 0:b7116bd48af6 1375 #else
mturner5 0:b7116bd48af6 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
mturner5 0:b7116bd48af6 1377 __DCCIMVAC = (uint32_t)va;
mturner5 0:b7116bd48af6 1378 #endif
mturner5 0:b7116bd48af6 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mturner5 0:b7116bd48af6 1380 }
mturner5 0:b7116bd48af6 1381
mturner5 0:b7116bd48af6 1382 /** \brief Clean and Invalidate the entire data or unified cache
mturner5 0:b7116bd48af6 1383
mturner5 0:b7116bd48af6 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
mturner5 0:b7116bd48af6 1385 */
mturner5 0:b7116bd48af6 1386 extern void __v7_all_cache(uint32_t op);
mturner5 0:b7116bd48af6 1387
mturner5 0:b7116bd48af6 1388
mturner5 0:b7116bd48af6 1389 /** \brief Invalidate the whole D$
mturner5 0:b7116bd48af6 1390
mturner5 0:b7116bd48af6 1391 DCISW. Invalidate by Set/Way
mturner5 0:b7116bd48af6 1392 */
mturner5 0:b7116bd48af6 1393
mturner5 0:b7116bd48af6 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
mturner5 0:b7116bd48af6 1395 __v7_all_cache(0);
mturner5 0:b7116bd48af6 1396 }
mturner5 0:b7116bd48af6 1397
mturner5 0:b7116bd48af6 1398 /** \brief Clean the whole D$
mturner5 0:b7116bd48af6 1399
mturner5 0:b7116bd48af6 1400 DCCSW. Clean by Set/Way
mturner5 0:b7116bd48af6 1401 */
mturner5 0:b7116bd48af6 1402
mturner5 0:b7116bd48af6 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
mturner5 0:b7116bd48af6 1404 __v7_all_cache(1);
mturner5 0:b7116bd48af6 1405 }
mturner5 0:b7116bd48af6 1406
mturner5 0:b7116bd48af6 1407 /** \brief Clean and invalidate the whole D$
mturner5 0:b7116bd48af6 1408
mturner5 0:b7116bd48af6 1409 DCCISW. Clean and Invalidate by Set/Way
mturner5 0:b7116bd48af6 1410 */
mturner5 0:b7116bd48af6 1411
mturner5 0:b7116bd48af6 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mturner5 0:b7116bd48af6 1413 __v7_all_cache(2);
mturner5 0:b7116bd48af6 1414 }
mturner5 0:b7116bd48af6 1415
mturner5 0:b7116bd48af6 1416 #include "core_ca_mmu.h"
mturner5 0:b7116bd48af6 1417
mturner5 0:b7116bd48af6 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
mturner5 0:b7116bd48af6 1419
mturner5 0:b7116bd48af6 1420 #error TASKING Compiler support not implemented for Cortex-A
mturner5 0:b7116bd48af6 1421
mturner5 0:b7116bd48af6 1422 #endif
mturner5 0:b7116bd48af6 1423
mturner5 0:b7116bd48af6 1424 /*@} end of CMSIS_Core_RegAccFunctions */
mturner5 0:b7116bd48af6 1425
mturner5 0:b7116bd48af6 1426
mturner5 0:b7116bd48af6 1427 #endif /* __CORE_CAFUNC_H__ */