Mark Turner / mbed

mbed library for slider v2

Dependents:   kl46z_slider_v2

TARGET_KL46Z/core_ca9.h@0:b7116bd48af6, 2016-09-14 (annotated)

Committer:
mturner5
Date:
Wed Sep 14 07:04:27 2016 +0000
Revision:
0:b7116bd48af6
Tried to use the timer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:b7116bd48af6 1 /**************************************************************************//**
mturner5 0:b7116bd48af6 2 * @file core_ca9.h
mturner5 0:b7116bd48af6 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
mturner5 0:b7116bd48af6 4 * @version
mturner5 0:b7116bd48af6 5 * @date 25 March 2013
mturner5 0:b7116bd48af6 6 *
mturner5 0:b7116bd48af6 7 * @note
mturner5 0:b7116bd48af6 8 *
mturner5 0:b7116bd48af6 9 ******************************************************************************/
mturner5 0:b7116bd48af6 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
mturner5 0:b7116bd48af6 11
mturner5 0:b7116bd48af6 12 All rights reserved.
mturner5 0:b7116bd48af6 13 Redistribution and use in source and binary forms, with or without
mturner5 0:b7116bd48af6 14 modification, are permitted provided that the following conditions are met:
mturner5 0:b7116bd48af6 15 - Redistributions of source code must retain the above copyright
mturner5 0:b7116bd48af6 16 notice, this list of conditions and the following disclaimer.
mturner5 0:b7116bd48af6 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:b7116bd48af6 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:b7116bd48af6 19 documentation and/or other materials provided with the distribution.
mturner5 0:b7116bd48af6 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:b7116bd48af6 21 to endorse or promote products derived from this software without
mturner5 0:b7116bd48af6 22 specific prior written permission.
mturner5 0:b7116bd48af6 23 *
mturner5 0:b7116bd48af6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:b7116bd48af6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:b7116bd48af6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:b7116bd48af6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:b7116bd48af6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:b7116bd48af6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:b7116bd48af6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:b7116bd48af6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:b7116bd48af6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:b7116bd48af6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:b7116bd48af6 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:b7116bd48af6 35 ---------------------------------------------------------------------------*/
mturner5 0:b7116bd48af6 36
mturner5 0:b7116bd48af6 37
mturner5 0:b7116bd48af6 38 #if defined ( __ICCARM__ )
mturner5 0:b7116bd48af6 39 #pragma system_include /* treat file as system include file for MISRA check */
mturner5 0:b7116bd48af6 40 #endif
mturner5 0:b7116bd48af6 41
mturner5 0:b7116bd48af6 42 #ifdef __cplusplus
mturner5 0:b7116bd48af6 43 extern "C" {
mturner5 0:b7116bd48af6 44 #endif
mturner5 0:b7116bd48af6 45
mturner5 0:b7116bd48af6 46 #ifndef __CORE_CA9_H_GENERIC
mturner5 0:b7116bd48af6 47 #define __CORE_CA9_H_GENERIC
mturner5 0:b7116bd48af6 48
mturner5 0:b7116bd48af6 49
mturner5 0:b7116bd48af6 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mturner5 0:b7116bd48af6 51 CMSIS violates the following MISRA-C:2004 rules:
mturner5 0:b7116bd48af6 52
mturner5 0:b7116bd48af6 53 \li Required Rule 8.5, object/function definition in header file.<br>
mturner5 0:b7116bd48af6 54 Function definitions in header files are used to allow 'inlining'.
mturner5 0:b7116bd48af6 55
mturner5 0:b7116bd48af6 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mturner5 0:b7116bd48af6 57 Unions are used for effective representation of core registers.
mturner5 0:b7116bd48af6 58
mturner5 0:b7116bd48af6 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
mturner5 0:b7116bd48af6 60 Function-like macros are used to allow more efficient code.
mturner5 0:b7116bd48af6 61 */
mturner5 0:b7116bd48af6 62
mturner5 0:b7116bd48af6 63
mturner5 0:b7116bd48af6 64 /*******************************************************************************
mturner5 0:b7116bd48af6 65 * CMSIS definitions
mturner5 0:b7116bd48af6 66 ******************************************************************************/
mturner5 0:b7116bd48af6 67 /** \ingroup Cortex_A9
mturner5 0:b7116bd48af6 68 @{
mturner5 0:b7116bd48af6 69 */
mturner5 0:b7116bd48af6 70
mturner5 0:b7116bd48af6 71 /* CMSIS CA9 definitions */
mturner5 0:b7116bd48af6 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mturner5 0:b7116bd48af6 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
mturner5 0:b7116bd48af6 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
mturner5 0:b7116bd48af6 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mturner5 0:b7116bd48af6 76
mturner5 0:b7116bd48af6 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
mturner5 0:b7116bd48af6 78
mturner5 0:b7116bd48af6 79
mturner5 0:b7116bd48af6 80 #if defined ( __CC_ARM )
mturner5 0:b7116bd48af6 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mturner5 0:b7116bd48af6 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mturner5 0:b7116bd48af6 83 #define __STATIC_INLINE static __inline
mturner5 0:b7116bd48af6 84 #define __STATIC_ASM static __asm
mturner5 0:b7116bd48af6 85
mturner5 0:b7116bd48af6 86 #elif defined ( __ICCARM__ )
mturner5 0:b7116bd48af6 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mturner5 0:b7116bd48af6 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mturner5 0:b7116bd48af6 89 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 90 #define __STATIC_ASM static __asm
mturner5 0:b7116bd48af6 91
mturner5 0:b7116bd48af6 92 #include <stdint.h>
mturner5 0:b7116bd48af6 93 inline uint32_t __get_PSR(void) {
mturner5 0:b7116bd48af6 94 __ASM("mrs r0, cpsr");
mturner5 0:b7116bd48af6 95 }
mturner5 0:b7116bd48af6 96
mturner5 0:b7116bd48af6 97 #elif defined ( __TMS470__ )
mturner5 0:b7116bd48af6 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mturner5 0:b7116bd48af6 99 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 100 #define __STATIC_ASM static __asm
mturner5 0:b7116bd48af6 101
mturner5 0:b7116bd48af6 102 #elif defined ( __GNUC__ )
mturner5 0:b7116bd48af6 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mturner5 0:b7116bd48af6 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mturner5 0:b7116bd48af6 105 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 106 #define __STATIC_ASM static __asm
mturner5 0:b7116bd48af6 107
mturner5 0:b7116bd48af6 108 #elif defined ( __TASKING__ )
mturner5 0:b7116bd48af6 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mturner5 0:b7116bd48af6 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mturner5 0:b7116bd48af6 111 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 112 #define __STATIC_ASM static __asm
mturner5 0:b7116bd48af6 113
mturner5 0:b7116bd48af6 114 #endif
mturner5 0:b7116bd48af6 115
mturner5 0:b7116bd48af6 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
mturner5 0:b7116bd48af6 117 */
mturner5 0:b7116bd48af6 118 #if defined ( __CC_ARM )
mturner5 0:b7116bd48af6 119 #if defined __TARGET_FPU_VFP
mturner5 0:b7116bd48af6 120 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 121 #define __FPU_USED 1
mturner5 0:b7116bd48af6 122 #else
mturner5 0:b7116bd48af6 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 124 #define __FPU_USED 0
mturner5 0:b7116bd48af6 125 #endif
mturner5 0:b7116bd48af6 126 #else
mturner5 0:b7116bd48af6 127 #define __FPU_USED 0
mturner5 0:b7116bd48af6 128 #endif
mturner5 0:b7116bd48af6 129
mturner5 0:b7116bd48af6 130 #elif defined ( __ICCARM__ )
mturner5 0:b7116bd48af6 131 #if defined __ARMVFP__
mturner5 0:b7116bd48af6 132 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 133 #define __FPU_USED 1
mturner5 0:b7116bd48af6 134 #else
mturner5 0:b7116bd48af6 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 136 #define __FPU_USED 0
mturner5 0:b7116bd48af6 137 #endif
mturner5 0:b7116bd48af6 138 #else
mturner5 0:b7116bd48af6 139 #define __FPU_USED 0
mturner5 0:b7116bd48af6 140 #endif
mturner5 0:b7116bd48af6 141
mturner5 0:b7116bd48af6 142 #elif defined ( __TMS470__ )
mturner5 0:b7116bd48af6 143 #if defined __TI_VFP_SUPPORT__
mturner5 0:b7116bd48af6 144 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 145 #define __FPU_USED 1
mturner5 0:b7116bd48af6 146 #else
mturner5 0:b7116bd48af6 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 148 #define __FPU_USED 0
mturner5 0:b7116bd48af6 149 #endif
mturner5 0:b7116bd48af6 150 #else
mturner5 0:b7116bd48af6 151 #define __FPU_USED 0
mturner5 0:b7116bd48af6 152 #endif
mturner5 0:b7116bd48af6 153
mturner5 0:b7116bd48af6 154 #elif defined ( __GNUC__ )
mturner5 0:b7116bd48af6 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mturner5 0:b7116bd48af6 156 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 157 #define __FPU_USED 1
mturner5 0:b7116bd48af6 158 #else
mturner5 0:b7116bd48af6 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 160 #define __FPU_USED 0
mturner5 0:b7116bd48af6 161 #endif
mturner5 0:b7116bd48af6 162 #else
mturner5 0:b7116bd48af6 163 #define __FPU_USED 0
mturner5 0:b7116bd48af6 164 #endif
mturner5 0:b7116bd48af6 165
mturner5 0:b7116bd48af6 166 #elif defined ( __TASKING__ )
mturner5 0:b7116bd48af6 167 #if defined __FPU_VFP__
mturner5 0:b7116bd48af6 168 #if (__FPU_PRESENT == 1)
mturner5 0:b7116bd48af6 169 #define __FPU_USED 1
mturner5 0:b7116bd48af6 170 #else
mturner5 0:b7116bd48af6 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 172 #define __FPU_USED 0
mturner5 0:b7116bd48af6 173 #endif
mturner5 0:b7116bd48af6 174 #else
mturner5 0:b7116bd48af6 175 #define __FPU_USED 0
mturner5 0:b7116bd48af6 176 #endif
mturner5 0:b7116bd48af6 177 #endif
mturner5 0:b7116bd48af6 178
mturner5 0:b7116bd48af6 179 #include <stdint.h> /*!< standard types definitions */
mturner5 0:b7116bd48af6 180 #include "core_caInstr.h" /*!< Core Instruction Access */
mturner5 0:b7116bd48af6 181 #include "core_caFunc.h" /*!< Core Function Access */
mturner5 0:b7116bd48af6 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
mturner5 0:b7116bd48af6 183
mturner5 0:b7116bd48af6 184 #endif /* __CORE_CA9_H_GENERIC */
mturner5 0:b7116bd48af6 185
mturner5 0:b7116bd48af6 186 #ifndef __CMSIS_GENERIC
mturner5 0:b7116bd48af6 187
mturner5 0:b7116bd48af6 188 #ifndef __CORE_CA9_H_DEPENDANT
mturner5 0:b7116bd48af6 189 #define __CORE_CA9_H_DEPENDANT
mturner5 0:b7116bd48af6 190
mturner5 0:b7116bd48af6 191 /* check device defines and use defaults */
mturner5 0:b7116bd48af6 192 #if defined __CHECK_DEVICE_DEFINES
mturner5 0:b7116bd48af6 193 #ifndef __CA9_REV
mturner5 0:b7116bd48af6 194 #define __CA9_REV 0x0000
mturner5 0:b7116bd48af6 195 #warning "__CA9_REV not defined in device header file; using default!"
mturner5 0:b7116bd48af6 196 #endif
mturner5 0:b7116bd48af6 197
mturner5 0:b7116bd48af6 198 #ifndef __FPU_PRESENT
mturner5 0:b7116bd48af6 199 #define __FPU_PRESENT 1
mturner5 0:b7116bd48af6 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
mturner5 0:b7116bd48af6 201 #endif
mturner5 0:b7116bd48af6 202
mturner5 0:b7116bd48af6 203 #ifndef __Vendor_SysTickConfig
mturner5 0:b7116bd48af6 204 #define __Vendor_SysTickConfig 1
mturner5 0:b7116bd48af6 205 #endif
mturner5 0:b7116bd48af6 206
mturner5 0:b7116bd48af6 207 #if __Vendor_SysTickConfig == 0
mturner5 0:b7116bd48af6 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
mturner5 0:b7116bd48af6 209 #endif
mturner5 0:b7116bd48af6 210 #endif
mturner5 0:b7116bd48af6 211
mturner5 0:b7116bd48af6 212 /* IO definitions (access restrictions to peripheral registers) */
mturner5 0:b7116bd48af6 213 /**
mturner5 0:b7116bd48af6 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
mturner5 0:b7116bd48af6 215
mturner5 0:b7116bd48af6 216 <strong>IO Type Qualifiers</strong> are used
mturner5 0:b7116bd48af6 217 \li to specify the access to peripheral variables.
mturner5 0:b7116bd48af6 218 \li for automatic generation of peripheral register debug information.
mturner5 0:b7116bd48af6 219 */
mturner5 0:b7116bd48af6 220 #ifdef __cplusplus
mturner5 0:b7116bd48af6 221 #define __I volatile /*!< Defines 'read only' permissions */
mturner5 0:b7116bd48af6 222 #else
mturner5 0:b7116bd48af6 223 #define __I volatile const /*!< Defines 'read only' permissions */
mturner5 0:b7116bd48af6 224 #endif
mturner5 0:b7116bd48af6 225 #define __O volatile /*!< Defines 'write only' permissions */
mturner5 0:b7116bd48af6 226 #define __IO volatile /*!< Defines 'read / write' permissions */
mturner5 0:b7116bd48af6 227
mturner5 0:b7116bd48af6 228 /*@} end of group Cortex_A9 */
mturner5 0:b7116bd48af6 229
mturner5 0:b7116bd48af6 230
mturner5 0:b7116bd48af6 231 /*******************************************************************************
mturner5 0:b7116bd48af6 232 * Register Abstraction
mturner5 0:b7116bd48af6 233 ******************************************************************************/
mturner5 0:b7116bd48af6 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
mturner5 0:b7116bd48af6 235 \brief Type definitions and defines for Cortex-A processor based devices.
mturner5 0:b7116bd48af6 236 */
mturner5 0:b7116bd48af6 237
mturner5 0:b7116bd48af6 238 /** \ingroup CMSIS_core_register
mturner5 0:b7116bd48af6 239 \defgroup CMSIS_CORE Status and Control Registers
mturner5 0:b7116bd48af6 240 \brief Core Register type definitions.
mturner5 0:b7116bd48af6 241 @{
mturner5 0:b7116bd48af6 242 */
mturner5 0:b7116bd48af6 243
mturner5 0:b7116bd48af6 244 /** \brief Union type to access the Application Program Status Register (APSR).
mturner5 0:b7116bd48af6 245 */
mturner5 0:b7116bd48af6 246 typedef union
mturner5 0:b7116bd48af6 247 {
mturner5 0:b7116bd48af6 248 struct
mturner5 0:b7116bd48af6 249 {
mturner5 0:b7116bd48af6 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mturner5 0:b7116bd48af6 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mturner5 0:b7116bd48af6 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
mturner5 0:b7116bd48af6 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mturner5 0:b7116bd48af6 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mturner5 0:b7116bd48af6 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mturner5 0:b7116bd48af6 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mturner5 0:b7116bd48af6 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mturner5 0:b7116bd48af6 258 } b; /*!< Structure used for bit access */
mturner5 0:b7116bd48af6 259 uint32_t w; /*!< Type used for word access */
mturner5 0:b7116bd48af6 260 } APSR_Type;
mturner5 0:b7116bd48af6 261
mturner5 0:b7116bd48af6 262
mturner5 0:b7116bd48af6 263 /*@} end of group CMSIS_CORE */
mturner5 0:b7116bd48af6 264
mturner5 0:b7116bd48af6 265 /*@} end of CMSIS_Core_FPUFunctions */
mturner5 0:b7116bd48af6 266
mturner5 0:b7116bd48af6 267
mturner5 0:b7116bd48af6 268 #endif /* __CORE_CA9_H_GENERIC */
mturner5 0:b7116bd48af6 269
mturner5 0:b7116bd48af6 270 #endif /* __CMSIS_GENERIC */
mturner5 0:b7116bd48af6 271
mturner5 0:b7116bd48af6 272 #ifdef __cplusplus
mturner5 0:b7116bd48af6 273 }
mturner5 0:b7116bd48af6 274
mturner5 0:b7116bd48af6 275
mturner5 0:b7116bd48af6 276 #endif