Mark Turner / MarksMbed

This is a repository for all my programs or modified programs.

TARGET_KL46Z/core_cmInstr.h@0:72480818e4a9, 2016-09-11 (annotated)

Committer:
mturner5
Date:
Sun Sep 11 23:48:09 2016 +0000
Revision:
0:72480818e4a9
Made delays for the LEDS and button presses

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:72480818e4a9 1 /**************************************************************************//**
mturner5 0:72480818e4a9 2 * @file core_cmInstr.h
mturner5 0:72480818e4a9 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
mturner5 0:72480818e4a9 4 * @version V3.20
mturner5 0:72480818e4a9 5 * @date 05. March 2013
mturner5 0:72480818e4a9 6 *
mturner5 0:72480818e4a9 7 * @note
mturner5 0:72480818e4a9 8 *
mturner5 0:72480818e4a9 9 ******************************************************************************/
mturner5 0:72480818e4a9 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mturner5 0:72480818e4a9 11
mturner5 0:72480818e4a9 12 All rights reserved.
mturner5 0:72480818e4a9 13 Redistribution and use in source and binary forms, with or without
mturner5 0:72480818e4a9 14 modification, are permitted provided that the following conditions are met:
mturner5 0:72480818e4a9 15 - Redistributions of source code must retain the above copyright
mturner5 0:72480818e4a9 16 notice, this list of conditions and the following disclaimer.
mturner5 0:72480818e4a9 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:72480818e4a9 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:72480818e4a9 19 documentation and/or other materials provided with the distribution.
mturner5 0:72480818e4a9 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:72480818e4a9 21 to endorse or promote products derived from this software without
mturner5 0:72480818e4a9 22 specific prior written permission.
mturner5 0:72480818e4a9 23 *
mturner5 0:72480818e4a9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:72480818e4a9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:72480818e4a9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:72480818e4a9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:72480818e4a9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:72480818e4a9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:72480818e4a9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:72480818e4a9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:72480818e4a9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:72480818e4a9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:72480818e4a9 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:72480818e4a9 35 ---------------------------------------------------------------------------*/
mturner5 0:72480818e4a9 36
mturner5 0:72480818e4a9 37
mturner5 0:72480818e4a9 38 #ifndef __CORE_CMINSTR_H
mturner5 0:72480818e4a9 39 #define __CORE_CMINSTR_H
mturner5 0:72480818e4a9 40
mturner5 0:72480818e4a9 41
mturner5 0:72480818e4a9 42 /* ########################## Core Instruction Access ######################### */
mturner5 0:72480818e4a9 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
mturner5 0:72480818e4a9 44 Access to dedicated instructions
mturner5 0:72480818e4a9 45 @{
mturner5 0:72480818e4a9 46 */
mturner5 0:72480818e4a9 47
mturner5 0:72480818e4a9 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mturner5 0:72480818e4a9 49 /* ARM armcc specific functions */
mturner5 0:72480818e4a9 50
mturner5 0:72480818e4a9 51 #if (__ARMCC_VERSION < 400677)
mturner5 0:72480818e4a9 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mturner5 0:72480818e4a9 53 #endif
mturner5 0:72480818e4a9 54
mturner5 0:72480818e4a9 55
mturner5 0:72480818e4a9 56 /** \brief No Operation
mturner5 0:72480818e4a9 57
mturner5 0:72480818e4a9 58 No Operation does nothing. This instruction can be used for code alignment purposes.
mturner5 0:72480818e4a9 59 */
mturner5 0:72480818e4a9 60 #define __NOP __nop
mturner5 0:72480818e4a9 61
mturner5 0:72480818e4a9 62
mturner5 0:72480818e4a9 63 /** \brief Wait For Interrupt
mturner5 0:72480818e4a9 64
mturner5 0:72480818e4a9 65 Wait For Interrupt is a hint instruction that suspends execution
mturner5 0:72480818e4a9 66 until one of a number of events occurs.
mturner5 0:72480818e4a9 67 */
mturner5 0:72480818e4a9 68 #define __WFI __wfi
mturner5 0:72480818e4a9 69
mturner5 0:72480818e4a9 70
mturner5 0:72480818e4a9 71 /** \brief Wait For Event
mturner5 0:72480818e4a9 72
mturner5 0:72480818e4a9 73 Wait For Event is a hint instruction that permits the processor to enter
mturner5 0:72480818e4a9 74 a low-power state until one of a number of events occurs.
mturner5 0:72480818e4a9 75 */
mturner5 0:72480818e4a9 76 #define __WFE __wfe
mturner5 0:72480818e4a9 77
mturner5 0:72480818e4a9 78
mturner5 0:72480818e4a9 79 /** \brief Send Event
mturner5 0:72480818e4a9 80
mturner5 0:72480818e4a9 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
mturner5 0:72480818e4a9 82 */
mturner5 0:72480818e4a9 83 #define __SEV __sev
mturner5 0:72480818e4a9 84
mturner5 0:72480818e4a9 85
mturner5 0:72480818e4a9 86 /** \brief Instruction Synchronization Barrier
mturner5 0:72480818e4a9 87
mturner5 0:72480818e4a9 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
mturner5 0:72480818e4a9 89 so that all instructions following the ISB are fetched from cache or
mturner5 0:72480818e4a9 90 memory, after the instruction has been completed.
mturner5 0:72480818e4a9 91 */
mturner5 0:72480818e4a9 92 #define __ISB() __isb(0xF)
mturner5 0:72480818e4a9 93
mturner5 0:72480818e4a9 94
mturner5 0:72480818e4a9 95 /** \brief Data Synchronization Barrier
mturner5 0:72480818e4a9 96
mturner5 0:72480818e4a9 97 This function acts as a special kind of Data Memory Barrier.
mturner5 0:72480818e4a9 98 It completes when all explicit memory accesses before this instruction complete.
mturner5 0:72480818e4a9 99 */
mturner5 0:72480818e4a9 100 #define __DSB() __dsb(0xF)
mturner5 0:72480818e4a9 101
mturner5 0:72480818e4a9 102
mturner5 0:72480818e4a9 103 /** \brief Data Memory Barrier
mturner5 0:72480818e4a9 104
mturner5 0:72480818e4a9 105 This function ensures the apparent order of the explicit memory operations before
mturner5 0:72480818e4a9 106 and after the instruction, without ensuring their completion.
mturner5 0:72480818e4a9 107 */
mturner5 0:72480818e4a9 108 #define __DMB() __dmb(0xF)
mturner5 0:72480818e4a9 109
mturner5 0:72480818e4a9 110
mturner5 0:72480818e4a9 111 /** \brief Reverse byte order (32 bit)
mturner5 0:72480818e4a9 112
mturner5 0:72480818e4a9 113 This function reverses the byte order in integer value.
mturner5 0:72480818e4a9 114
mturner5 0:72480818e4a9 115 \param [in] value Value to reverse
mturner5 0:72480818e4a9 116 \return Reversed value
mturner5 0:72480818e4a9 117 */
mturner5 0:72480818e4a9 118 #define __REV __rev
mturner5 0:72480818e4a9 119
mturner5 0:72480818e4a9 120
mturner5 0:72480818e4a9 121 /** \brief Reverse byte order (16 bit)
mturner5 0:72480818e4a9 122
mturner5 0:72480818e4a9 123 This function reverses the byte order in two unsigned short values.
mturner5 0:72480818e4a9 124
mturner5 0:72480818e4a9 125 \param [in] value Value to reverse
mturner5 0:72480818e4a9 126 \return Reversed value
mturner5 0:72480818e4a9 127 */
mturner5 0:72480818e4a9 128 #ifndef __NO_EMBEDDED_ASM
mturner5 0:72480818e4a9 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
mturner5 0:72480818e4a9 130 {
mturner5 0:72480818e4a9 131 rev16 r0, r0
mturner5 0:72480818e4a9 132 bx lr
mturner5 0:72480818e4a9 133 }
mturner5 0:72480818e4a9 134 #endif
mturner5 0:72480818e4a9 135
mturner5 0:72480818e4a9 136 /** \brief Reverse byte order in signed short value
mturner5 0:72480818e4a9 137
mturner5 0:72480818e4a9 138 This function reverses the byte order in a signed short value with sign extension to integer.
mturner5 0:72480818e4a9 139
mturner5 0:72480818e4a9 140 \param [in] value Value to reverse
mturner5 0:72480818e4a9 141 \return Reversed value
mturner5 0:72480818e4a9 142 */
mturner5 0:72480818e4a9 143 #ifndef __NO_EMBEDDED_ASM
mturner5 0:72480818e4a9 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
mturner5 0:72480818e4a9 145 {
mturner5 0:72480818e4a9 146 revsh r0, r0
mturner5 0:72480818e4a9 147 bx lr
mturner5 0:72480818e4a9 148 }
mturner5 0:72480818e4a9 149 #endif
mturner5 0:72480818e4a9 150
mturner5 0:72480818e4a9 151
mturner5 0:72480818e4a9 152 /** \brief Rotate Right in unsigned value (32 bit)
mturner5 0:72480818e4a9 153
mturner5 0:72480818e4a9 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
mturner5 0:72480818e4a9 155
mturner5 0:72480818e4a9 156 \param [in] value Value to rotate
mturner5 0:72480818e4a9 157 \param [in] value Number of Bits to rotate
mturner5 0:72480818e4a9 158 \return Rotated value
mturner5 0:72480818e4a9 159 */
mturner5 0:72480818e4a9 160 #define __ROR __ror
mturner5 0:72480818e4a9 161
mturner5 0:72480818e4a9 162
mturner5 0:72480818e4a9 163 /** \brief Breakpoint
mturner5 0:72480818e4a9 164
mturner5 0:72480818e4a9 165 This function causes the processor to enter Debug state.
mturner5 0:72480818e4a9 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
mturner5 0:72480818e4a9 167
mturner5 0:72480818e4a9 168 \param [in] value is ignored by the processor.
mturner5 0:72480818e4a9 169 If required, a debugger can use it to store additional information about the breakpoint.
mturner5 0:72480818e4a9 170 */
mturner5 0:72480818e4a9 171 #define __BKPT(value) __breakpoint(value)
mturner5 0:72480818e4a9 172
mturner5 0:72480818e4a9 173
mturner5 0:72480818e4a9 174 #if (__CORTEX_M >= 0x03)
mturner5 0:72480818e4a9 175
mturner5 0:72480818e4a9 176 /** \brief Reverse bit order of value
mturner5 0:72480818e4a9 177
mturner5 0:72480818e4a9 178 This function reverses the bit order of the given value.
mturner5 0:72480818e4a9 179
mturner5 0:72480818e4a9 180 \param [in] value Value to reverse
mturner5 0:72480818e4a9 181 \return Reversed value
mturner5 0:72480818e4a9 182 */
mturner5 0:72480818e4a9 183 #define __RBIT __rbit
mturner5 0:72480818e4a9 184
mturner5 0:72480818e4a9 185
mturner5 0:72480818e4a9 186 /** \brief LDR Exclusive (8 bit)
mturner5 0:72480818e4a9 187
mturner5 0:72480818e4a9 188 This function performs a exclusive LDR command for 8 bit value.
mturner5 0:72480818e4a9 189
mturner5 0:72480818e4a9 190 \param [in] ptr Pointer to data
mturner5 0:72480818e4a9 191 \return value of type uint8_t at (*ptr)
mturner5 0:72480818e4a9 192 */
mturner5 0:72480818e4a9 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
mturner5 0:72480818e4a9 194
mturner5 0:72480818e4a9 195
mturner5 0:72480818e4a9 196 /** \brief LDR Exclusive (16 bit)
mturner5 0:72480818e4a9 197
mturner5 0:72480818e4a9 198 This function performs a exclusive LDR command for 16 bit values.
mturner5 0:72480818e4a9 199
mturner5 0:72480818e4a9 200 \param [in] ptr Pointer to data
mturner5 0:72480818e4a9 201 \return value of type uint16_t at (*ptr)
mturner5 0:72480818e4a9 202 */
mturner5 0:72480818e4a9 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
mturner5 0:72480818e4a9 204
mturner5 0:72480818e4a9 205
mturner5 0:72480818e4a9 206 /** \brief LDR Exclusive (32 bit)
mturner5 0:72480818e4a9 207
mturner5 0:72480818e4a9 208 This function performs a exclusive LDR command for 32 bit values.
mturner5 0:72480818e4a9 209
mturner5 0:72480818e4a9 210 \param [in] ptr Pointer to data
mturner5 0:72480818e4a9 211 \return value of type uint32_t at (*ptr)
mturner5 0:72480818e4a9 212 */
mturner5 0:72480818e4a9 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
mturner5 0:72480818e4a9 214
mturner5 0:72480818e4a9 215
mturner5 0:72480818e4a9 216 /** \brief STR Exclusive (8 bit)
mturner5 0:72480818e4a9 217
mturner5 0:72480818e4a9 218 This function performs a exclusive STR command for 8 bit values.
mturner5 0:72480818e4a9 219
mturner5 0:72480818e4a9 220 \param [in] value Value to store
mturner5 0:72480818e4a9 221 \param [in] ptr Pointer to location
mturner5 0:72480818e4a9 222 \return 0 Function succeeded
mturner5 0:72480818e4a9 223 \return 1 Function failed
mturner5 0:72480818e4a9 224 */
mturner5 0:72480818e4a9 225 #define __STREXB(value, ptr) __strex(value, ptr)
mturner5 0:72480818e4a9 226
mturner5 0:72480818e4a9 227
mturner5 0:72480818e4a9 228 /** \brief STR Exclusive (16 bit)
mturner5 0:72480818e4a9 229
mturner5 0:72480818e4a9 230 This function performs a exclusive STR command for 16 bit values.
mturner5 0:72480818e4a9 231
mturner5 0:72480818e4a9 232 \param [in] value Value to store
mturner5 0:72480818e4a9 233 \param [in] ptr Pointer to location
mturner5 0:72480818e4a9 234 \return 0 Function succeeded
mturner5 0:72480818e4a9 235 \return 1 Function failed
mturner5 0:72480818e4a9 236 */
mturner5 0:72480818e4a9 237 #define __STREXH(value, ptr) __strex(value, ptr)
mturner5 0:72480818e4a9 238
mturner5 0:72480818e4a9 239
mturner5 0:72480818e4a9 240 /** \brief STR Exclusive (32 bit)
mturner5 0:72480818e4a9 241
mturner5 0:72480818e4a9 242 This function performs a exclusive STR command for 32 bit values.
mturner5 0:72480818e4a9 243
mturner5 0:72480818e4a9 244 \param [in] value Value to store
mturner5 0:72480818e4a9 245 \param [in] ptr Pointer to location
mturner5 0:72480818e4a9 246 \return 0 Function succeeded
mturner5 0:72480818e4a9 247 \return 1 Function failed
mturner5 0:72480818e4a9 248 */
mturner5 0:72480818e4a9 249 #define __STREXW(value, ptr) __strex(value, ptr)
mturner5 0:72480818e4a9 250
mturner5 0:72480818e4a9 251
mturner5 0:72480818e4a9 252 /** \brief Remove the exclusive lock
mturner5 0:72480818e4a9 253
mturner5 0:72480818e4a9 254 This function removes the exclusive lock which is created by LDREX.
mturner5 0:72480818e4a9 255
mturner5 0:72480818e4a9 256 */
mturner5 0:72480818e4a9 257 #define __CLREX __clrex
mturner5 0:72480818e4a9 258
mturner5 0:72480818e4a9 259
mturner5 0:72480818e4a9 260 /** \brief Signed Saturate
mturner5 0:72480818e4a9 261
mturner5 0:72480818e4a9 262 This function saturates a signed value.
mturner5 0:72480818e4a9 263
mturner5 0:72480818e4a9 264 \param [in] value Value to be saturated
mturner5 0:72480818e4a9 265 \param [in] sat Bit position to saturate to (1..32)
mturner5 0:72480818e4a9 266 \return Saturated value
mturner5 0:72480818e4a9 267 */
mturner5 0:72480818e4a9 268 #define __SSAT __ssat
mturner5 0:72480818e4a9 269
mturner5 0:72480818e4a9 270
mturner5 0:72480818e4a9 271 /** \brief Unsigned Saturate
mturner5 0:72480818e4a9 272
mturner5 0:72480818e4a9 273 This function saturates an unsigned value.
mturner5 0:72480818e4a9 274
mturner5 0:72480818e4a9 275 \param [in] value Value to be saturated
mturner5 0:72480818e4a9 276 \param [in] sat Bit position to saturate to (0..31)
mturner5 0:72480818e4a9 277 \return Saturated value
mturner5 0:72480818e4a9 278 */
mturner5 0:72480818e4a9 279 #define __USAT __usat
mturner5 0:72480818e4a9 280
mturner5 0:72480818e4a9 281
mturner5 0:72480818e4a9 282 /** \brief Count leading zeros
mturner5 0:72480818e4a9 283
mturner5 0:72480818e4a9 284 This function counts the number of leading zeros of a data value.
mturner5 0:72480818e4a9 285
mturner5 0:72480818e4a9 286 \param [in] value Value to count the leading zeros
mturner5 0:72480818e4a9 287 \return number of leading zeros in value
mturner5 0:72480818e4a9 288 */
mturner5 0:72480818e4a9 289 #define __CLZ __clz
mturner5 0:72480818e4a9 290
mturner5 0:72480818e4a9 291 #endif /* (__CORTEX_M >= 0x03) */
mturner5 0:72480818e4a9 292
mturner5 0:72480818e4a9 293
mturner5 0:72480818e4a9 294
mturner5 0:72480818e4a9 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mturner5 0:72480818e4a9 296 /* IAR iccarm specific functions */
mturner5 0:72480818e4a9 297
mturner5 0:72480818e4a9 298 #include <cmsis_iar.h>
mturner5 0:72480818e4a9 299
mturner5 0:72480818e4a9 300
mturner5 0:72480818e4a9 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mturner5 0:72480818e4a9 302 /* TI CCS specific functions */
mturner5 0:72480818e4a9 303
mturner5 0:72480818e4a9 304 #include <cmsis_ccs.h>
mturner5 0:72480818e4a9 305
mturner5 0:72480818e4a9 306
mturner5 0:72480818e4a9 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mturner5 0:72480818e4a9 308 /* GNU gcc specific functions */
mturner5 0:72480818e4a9 309
mturner5 0:72480818e4a9 310 /* Define macros for porting to both thumb1 and thumb2.
mturner5 0:72480818e4a9 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
mturner5 0:72480818e4a9 312 * Otherwise, use general registers, specified by constrant "r" */
mturner5 0:72480818e4a9 313 #if defined (__thumb__) && !defined (__thumb2__)
mturner5 0:72480818e4a9 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
mturner5 0:72480818e4a9 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
mturner5 0:72480818e4a9 316 #else
mturner5 0:72480818e4a9 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
mturner5 0:72480818e4a9 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
mturner5 0:72480818e4a9 319 #endif
mturner5 0:72480818e4a9 320
mturner5 0:72480818e4a9 321 /** \brief No Operation
mturner5 0:72480818e4a9 322
mturner5 0:72480818e4a9 323 No Operation does nothing. This instruction can be used for code alignment purposes.
mturner5 0:72480818e4a9 324 */
mturner5 0:72480818e4a9 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
mturner5 0:72480818e4a9 326 {
mturner5 0:72480818e4a9 327 __ASM volatile ("nop");
mturner5 0:72480818e4a9 328 }
mturner5 0:72480818e4a9 329
mturner5 0:72480818e4a9 330
mturner5 0:72480818e4a9 331 /** \brief Wait For Interrupt
mturner5 0:72480818e4a9 332
mturner5 0:72480818e4a9 333 Wait For Interrupt is a hint instruction that suspends execution
mturner5 0:72480818e4a9 334 until one of a number of events occurs.
mturner5 0:72480818e4a9 335 */
mturner5 0:72480818e4a9 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
mturner5 0:72480818e4a9 337 {
mturner5 0:72480818e4a9 338 __ASM volatile ("wfi");
mturner5 0:72480818e4a9 339 }
mturner5 0:72480818e4a9 340
mturner5 0:72480818e4a9 341
mturner5 0:72480818e4a9 342 /** \brief Wait For Event
mturner5 0:72480818e4a9 343
mturner5 0:72480818e4a9 344 Wait For Event is a hint instruction that permits the processor to enter
mturner5 0:72480818e4a9 345 a low-power state until one of a number of events occurs.
mturner5 0:72480818e4a9 346 */
mturner5 0:72480818e4a9 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
mturner5 0:72480818e4a9 348 {
mturner5 0:72480818e4a9 349 __ASM volatile ("wfe");
mturner5 0:72480818e4a9 350 }
mturner5 0:72480818e4a9 351
mturner5 0:72480818e4a9 352
mturner5 0:72480818e4a9 353 /** \brief Send Event
mturner5 0:72480818e4a9 354
mturner5 0:72480818e4a9 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
mturner5 0:72480818e4a9 356 */
mturner5 0:72480818e4a9 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
mturner5 0:72480818e4a9 358 {
mturner5 0:72480818e4a9 359 __ASM volatile ("sev");
mturner5 0:72480818e4a9 360 }
mturner5 0:72480818e4a9 361
mturner5 0:72480818e4a9 362
mturner5 0:72480818e4a9 363 /** \brief Instruction Synchronization Barrier
mturner5 0:72480818e4a9 364
mturner5 0:72480818e4a9 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
mturner5 0:72480818e4a9 366 so that all instructions following the ISB are fetched from cache or
mturner5 0:72480818e4a9 367 memory, after the instruction has been completed.
mturner5 0:72480818e4a9 368 */
mturner5 0:72480818e4a9 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
mturner5 0:72480818e4a9 370 {
mturner5 0:72480818e4a9 371 __ASM volatile ("isb");
mturner5 0:72480818e4a9 372 }
mturner5 0:72480818e4a9 373
mturner5 0:72480818e4a9 374
mturner5 0:72480818e4a9 375 /** \brief Data Synchronization Barrier
mturner5 0:72480818e4a9 376
mturner5 0:72480818e4a9 377 This function acts as a special kind of Data Memory Barrier.
mturner5 0:72480818e4a9 378 It completes when all explicit memory accesses before this instruction complete.
mturner5 0:72480818e4a9 379 */
mturner5 0:72480818e4a9 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
mturner5 0:72480818e4a9 381 {
mturner5 0:72480818e4a9 382 __ASM volatile ("dsb");
mturner5 0:72480818e4a9 383 }
mturner5 0:72480818e4a9 384
mturner5 0:72480818e4a9 385
mturner5 0:72480818e4a9 386 /** \brief Data Memory Barrier
mturner5 0:72480818e4a9 387
mturner5 0:72480818e4a9 388 This function ensures the apparent order of the explicit memory operations before
mturner5 0:72480818e4a9 389 and after the instruction, without ensuring their completion.
mturner5 0:72480818e4a9 390 */
mturner5 0:72480818e4a9 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
mturner5 0:72480818e4a9 392 {
mturner5 0:72480818e4a9 393 __ASM volatile ("dmb");
mturner5 0:72480818e4a9 394 }
mturner5 0:72480818e4a9 395
mturner5 0:72480818e4a9 396
mturner5 0:72480818e4a9 397 /** \brief Reverse byte order (32 bit)
mturner5 0:72480818e4a9 398
mturner5 0:72480818e4a9 399 This function reverses the byte order in integer value.
mturner5 0:72480818e4a9 400
mturner5 0:72480818e4a9 401 \param [in] value Value to reverse
mturner5 0:72480818e4a9 402 \return Reversed value
mturner5 0:72480818e4a9 403 */
mturner5 0:72480818e4a9 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
mturner5 0:72480818e4a9 405 {
mturner5 0:72480818e4a9 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
mturner5 0:72480818e4a9 407 return __builtin_bswap32(value);
mturner5 0:72480818e4a9 408 #else
mturner5 0:72480818e4a9 409 uint32_t result;
mturner5 0:72480818e4a9 410
mturner5 0:72480818e4a9 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mturner5 0:72480818e4a9 412 return(result);
mturner5 0:72480818e4a9 413 #endif
mturner5 0:72480818e4a9 414 }
mturner5 0:72480818e4a9 415
mturner5 0:72480818e4a9 416
mturner5 0:72480818e4a9 417 /** \brief Reverse byte order (16 bit)
mturner5 0:72480818e4a9 418
mturner5 0:72480818e4a9 419 This function reverses the byte order in two unsigned short values.
mturner5 0:72480818e4a9 420
mturner5 0:72480818e4a9 421 \param [in] value Value to reverse
mturner5 0:72480818e4a9 422 \return Reversed value
mturner5 0:72480818e4a9 423 */
mturner5 0:72480818e4a9 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
mturner5 0:72480818e4a9 425 {
mturner5 0:72480818e4a9 426 uint32_t result;
mturner5 0:72480818e4a9 427
mturner5 0:72480818e4a9 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mturner5 0:72480818e4a9 429 return(result);
mturner5 0:72480818e4a9 430 }
mturner5 0:72480818e4a9 431
mturner5 0:72480818e4a9 432
mturner5 0:72480818e4a9 433 /** \brief Reverse byte order in signed short value
mturner5 0:72480818e4a9 434
mturner5 0:72480818e4a9 435 This function reverses the byte order in a signed short value with sign extension to integer.
mturner5 0:72480818e4a9 436
mturner5 0:72480818e4a9 437 \param [in] value Value to reverse
mturner5 0:72480818e4a9 438 \return Reversed value
mturner5 0:72480818e4a9 439 */
mturner5 0:72480818e4a9 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
mturner5 0:72480818e4a9 441 {
mturner5 0:72480818e4a9 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mturner5 0:72480818e4a9 443 return (short)__builtin_bswap16(value);
mturner5 0:72480818e4a9 444 #else
mturner5 0:72480818e4a9 445 uint32_t result;
mturner5 0:72480818e4a9 446
mturner5 0:72480818e4a9 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mturner5 0:72480818e4a9 448 return(result);
mturner5 0:72480818e4a9 449 #endif
mturner5 0:72480818e4a9 450 }
mturner5 0:72480818e4a9 451
mturner5 0:72480818e4a9 452
mturner5 0:72480818e4a9 453 /** \brief Rotate Right in unsigned value (32 bit)
mturner5 0:72480818e4a9 454
mturner5 0:72480818e4a9 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
mturner5 0:72480818e4a9 456
mturner5 0:72480818e4a9 457 \param [in] value Value to rotate
mturner5 0:72480818e4a9 458 \param [in] value Number of Bits to rotate
mturner5 0:72480818e4a9 459 \return Rotated value
mturner5 0:72480818e4a9 460 */
mturner5 0:72480818e4a9 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
mturner5 0:72480818e4a9 462 {
mturner5 0:72480818e4a9 463 return (op1 >> op2) | (op1 << (32 - op2));
mturner5 0:72480818e4a9 464 }
mturner5 0:72480818e4a9 465
mturner5 0:72480818e4a9 466
mturner5 0:72480818e4a9 467 /** \brief Breakpoint
mturner5 0:72480818e4a9 468
mturner5 0:72480818e4a9 469 This function causes the processor to enter Debug state.
mturner5 0:72480818e4a9 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
mturner5 0:72480818e4a9 471
mturner5 0:72480818e4a9 472 \param [in] value is ignored by the processor.
mturner5 0:72480818e4a9 473 If required, a debugger can use it to store additional information about the breakpoint.
mturner5 0:72480818e4a9 474 */
mturner5 0:72480818e4a9 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
mturner5 0:72480818e4a9 476
mturner5 0:72480818e4a9 477
mturner5 0:72480818e4a9 478 #if (__CORTEX_M >= 0x03)
mturner5 0:72480818e4a9 479
mturner5 0:72480818e4a9 480 /** \brief Reverse bit order of value
mturner5 0:72480818e4a9 481
mturner5 0:72480818e4a9 482 This function reverses the bit order of the given value.
mturner5 0:72480818e4a9 483
mturner5 0:72480818e4a9 484 \param [in] value Value to reverse
mturner5 0:72480818e4a9 485 \return Reversed value
mturner5 0:72480818e4a9 486 */
mturner5 0:72480818e4a9 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
mturner5 0:72480818e4a9 488 {
mturner5 0:72480818e4a9 489 uint32_t result;
mturner5 0:72480818e4a9 490
mturner5 0:72480818e4a9 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
mturner5 0:72480818e4a9 492 return(result);
mturner5 0:72480818e4a9 493 }
mturner5 0:72480818e4a9 494
mturner5 0:72480818e4a9 495
mturner5 0:72480818e4a9 496 /** \brief LDR Exclusive (8 bit)
mturner5 0:72480818e4a9 497
mturner5 0:72480818e4a9 498 This function performs a exclusive LDR command for 8 bit value.
mturner5 0:72480818e4a9 499
mturner5 0:72480818e4a9 500 \param [in] ptr Pointer to data
mturner5 0:72480818e4a9 501 \return value of type uint8_t at (*ptr)
mturner5 0:72480818e4a9 502 */
mturner5 0:72480818e4a9 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
mturner5 0:72480818e4a9 504 {
mturner5 0:72480818e4a9 505 uint32_t result;
mturner5 0:72480818e4a9 506
mturner5 0:72480818e4a9 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mturner5 0:72480818e4a9 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:72480818e4a9 509 #else
mturner5 0:72480818e4a9 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mturner5 0:72480818e4a9 511 accepted by assembler. So has to use following less efficient pattern.
mturner5 0:72480818e4a9 512 */
mturner5 0:72480818e4a9 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mturner5 0:72480818e4a9 514 #endif
mturner5 0:72480818e4a9 515 return(result);
mturner5 0:72480818e4a9 516 }
mturner5 0:72480818e4a9 517
mturner5 0:72480818e4a9 518
mturner5 0:72480818e4a9 519 /** \brief LDR Exclusive (16 bit)
mturner5 0:72480818e4a9 520
mturner5 0:72480818e4a9 521 This function performs a exclusive LDR command for 16 bit values.
mturner5 0:72480818e4a9 522
mturner5 0:72480818e4a9 523 \param [in] ptr Pointer to data
mturner5 0:72480818e4a9 524 \return value of type uint16_t at (*ptr)
mturner5 0:72480818e4a9 525 */
mturner5 0:72480818e4a9 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
mturner5 0:72480818e4a9 527 {
mturner5 0:72480818e4a9 528 uint32_t result;
mturner5 0:72480818e4a9 529
mturner5 0:72480818e4a9 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mturner5 0:72480818e4a9 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:72480818e4a9 532 #else
mturner5 0:72480818e4a9 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mturner5 0:72480818e4a9 534 accepted by assembler. So has to use following less efficient pattern.
mturner5 0:72480818e4a9 535 */
mturner5 0:72480818e4a9 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mturner5 0:72480818e4a9 537 #endif
mturner5 0:72480818e4a9 538 return(result);
mturner5 0:72480818e4a9 539 }
mturner5 0:72480818e4a9 540
mturner5 0:72480818e4a9 541
mturner5 0:72480818e4a9 542 /** \brief LDR Exclusive (32 bit)
mturner5 0:72480818e4a9 543
mturner5 0:72480818e4a9 544 This function performs a exclusive LDR command for 32 bit values.
mturner5 0:72480818e4a9 545
mturner5 0:72480818e4a9 546 \param [in] ptr Pointer to data
mturner5 0:72480818e4a9 547 \return value of type uint32_t at (*ptr)
mturner5 0:72480818e4a9 548 */
mturner5 0:72480818e4a9 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
mturner5 0:72480818e4a9 550 {
mturner5 0:72480818e4a9 551 uint32_t result;
mturner5 0:72480818e4a9 552
mturner5 0:72480818e4a9 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:72480818e4a9 554 return(result);
mturner5 0:72480818e4a9 555 }
mturner5 0:72480818e4a9 556
mturner5 0:72480818e4a9 557
mturner5 0:72480818e4a9 558 /** \brief STR Exclusive (8 bit)
mturner5 0:72480818e4a9 559
mturner5 0:72480818e4a9 560 This function performs a exclusive STR command for 8 bit values.
mturner5 0:72480818e4a9 561
mturner5 0:72480818e4a9 562 \param [in] value Value to store
mturner5 0:72480818e4a9 563 \param [in] ptr Pointer to location
mturner5 0:72480818e4a9 564 \return 0 Function succeeded
mturner5 0:72480818e4a9 565 \return 1 Function failed
mturner5 0:72480818e4a9 566 */
mturner5 0:72480818e4a9 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
mturner5 0:72480818e4a9 568 {
mturner5 0:72480818e4a9 569 uint32_t result;
mturner5 0:72480818e4a9 570
mturner5 0:72480818e4a9 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
mturner5 0:72480818e4a9 572 return(result);
mturner5 0:72480818e4a9 573 }
mturner5 0:72480818e4a9 574
mturner5 0:72480818e4a9 575
mturner5 0:72480818e4a9 576 /** \brief STR Exclusive (16 bit)
mturner5 0:72480818e4a9 577
mturner5 0:72480818e4a9 578 This function performs a exclusive STR command for 16 bit values.
mturner5 0:72480818e4a9 579
mturner5 0:72480818e4a9 580 \param [in] value Value to store
mturner5 0:72480818e4a9 581 \param [in] ptr Pointer to location
mturner5 0:72480818e4a9 582 \return 0 Function succeeded
mturner5 0:72480818e4a9 583 \return 1 Function failed
mturner5 0:72480818e4a9 584 */
mturner5 0:72480818e4a9 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
mturner5 0:72480818e4a9 586 {
mturner5 0:72480818e4a9 587 uint32_t result;
mturner5 0:72480818e4a9 588
mturner5 0:72480818e4a9 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
mturner5 0:72480818e4a9 590 return(result);
mturner5 0:72480818e4a9 591 }
mturner5 0:72480818e4a9 592
mturner5 0:72480818e4a9 593
mturner5 0:72480818e4a9 594 /** \brief STR Exclusive (32 bit)
mturner5 0:72480818e4a9 595
mturner5 0:72480818e4a9 596 This function performs a exclusive STR command for 32 bit values.
mturner5 0:72480818e4a9 597
mturner5 0:72480818e4a9 598 \param [in] value Value to store
mturner5 0:72480818e4a9 599 \param [in] ptr Pointer to location
mturner5 0:72480818e4a9 600 \return 0 Function succeeded
mturner5 0:72480818e4a9 601 \return 1 Function failed
mturner5 0:72480818e4a9 602 */
mturner5 0:72480818e4a9 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
mturner5 0:72480818e4a9 604 {
mturner5 0:72480818e4a9 605 uint32_t result;
mturner5 0:72480818e4a9 606
mturner5 0:72480818e4a9 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
mturner5 0:72480818e4a9 608 return(result);
mturner5 0:72480818e4a9 609 }
mturner5 0:72480818e4a9 610
mturner5 0:72480818e4a9 611
mturner5 0:72480818e4a9 612 /** \brief Remove the exclusive lock
mturner5 0:72480818e4a9 613
mturner5 0:72480818e4a9 614 This function removes the exclusive lock which is created by LDREX.
mturner5 0:72480818e4a9 615
mturner5 0:72480818e4a9 616 */
mturner5 0:72480818e4a9 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
mturner5 0:72480818e4a9 618 {
mturner5 0:72480818e4a9 619 __ASM volatile ("clrex" ::: "memory");
mturner5 0:72480818e4a9 620 }
mturner5 0:72480818e4a9 621
mturner5 0:72480818e4a9 622
mturner5 0:72480818e4a9 623 /** \brief Signed Saturate
mturner5 0:72480818e4a9 624
mturner5 0:72480818e4a9 625 This function saturates a signed value.
mturner5 0:72480818e4a9 626
mturner5 0:72480818e4a9 627 \param [in] value Value to be saturated
mturner5 0:72480818e4a9 628 \param [in] sat Bit position to saturate to (1..32)
mturner5 0:72480818e4a9 629 \return Saturated value
mturner5 0:72480818e4a9 630 */
mturner5 0:72480818e4a9 631 #define __SSAT(ARG1,ARG2) \
mturner5 0:72480818e4a9 632 ({ \
mturner5 0:72480818e4a9 633 uint32_t __RES, __ARG1 = (ARG1); \
mturner5 0:72480818e4a9 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mturner5 0:72480818e4a9 635 __RES; \
mturner5 0:72480818e4a9 636 })
mturner5 0:72480818e4a9 637
mturner5 0:72480818e4a9 638
mturner5 0:72480818e4a9 639 /** \brief Unsigned Saturate
mturner5 0:72480818e4a9 640
mturner5 0:72480818e4a9 641 This function saturates an unsigned value.
mturner5 0:72480818e4a9 642
mturner5 0:72480818e4a9 643 \param [in] value Value to be saturated
mturner5 0:72480818e4a9 644 \param [in] sat Bit position to saturate to (0..31)
mturner5 0:72480818e4a9 645 \return Saturated value
mturner5 0:72480818e4a9 646 */
mturner5 0:72480818e4a9 647 #define __USAT(ARG1,ARG2) \
mturner5 0:72480818e4a9 648 ({ \
mturner5 0:72480818e4a9 649 uint32_t __RES, __ARG1 = (ARG1); \
mturner5 0:72480818e4a9 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mturner5 0:72480818e4a9 651 __RES; \
mturner5 0:72480818e4a9 652 })
mturner5 0:72480818e4a9 653
mturner5 0:72480818e4a9 654
mturner5 0:72480818e4a9 655 /** \brief Count leading zeros
mturner5 0:72480818e4a9 656
mturner5 0:72480818e4a9 657 This function counts the number of leading zeros of a data value.
mturner5 0:72480818e4a9 658
mturner5 0:72480818e4a9 659 \param [in] value Value to count the leading zeros
mturner5 0:72480818e4a9 660 \return number of leading zeros in value
mturner5 0:72480818e4a9 661 */
mturner5 0:72480818e4a9 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
mturner5 0:72480818e4a9 663 {
mturner5 0:72480818e4a9 664 uint32_t result;
mturner5 0:72480818e4a9 665
mturner5 0:72480818e4a9 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
mturner5 0:72480818e4a9 667 return(result);
mturner5 0:72480818e4a9 668 }
mturner5 0:72480818e4a9 669
mturner5 0:72480818e4a9 670 #endif /* (__CORTEX_M >= 0x03) */
mturner5 0:72480818e4a9 671
mturner5 0:72480818e4a9 672
mturner5 0:72480818e4a9 673
mturner5 0:72480818e4a9 674
mturner5 0:72480818e4a9 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mturner5 0:72480818e4a9 676 /* TASKING carm specific functions */
mturner5 0:72480818e4a9 677
mturner5 0:72480818e4a9 678 /*
mturner5 0:72480818e4a9 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
mturner5 0:72480818e4a9 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
mturner5 0:72480818e4a9 681 * Including the CMSIS ones.
mturner5 0:72480818e4a9 682 */
mturner5 0:72480818e4a9 683
mturner5 0:72480818e4a9 684 #endif
mturner5 0:72480818e4a9 685
mturner5 0:72480818e4a9 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
mturner5 0:72480818e4a9 687
mturner5 0:72480818e4a9 688 #endif /* __CORE_CMINSTR_H */