Mark Turner / MarksMbed

This is a repository for all my programs or modified programs.

TARGET_KL46Z/core_cmFunc.h@0:72480818e4a9, 2016-09-11 (annotated)

Committer:
mturner5
Date:
Sun Sep 11 23:48:09 2016 +0000
Revision:
0:72480818e4a9
Made delays for the LEDS and button presses

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:72480818e4a9 1 /**************************************************************************//**
mturner5 0:72480818e4a9 2 * @file core_cmFunc.h
mturner5 0:72480818e4a9 3 * @brief CMSIS Cortex-M Core Function Access Header File
mturner5 0:72480818e4a9 4 * @version V3.20
mturner5 0:72480818e4a9 5 * @date 25. February 2013
mturner5 0:72480818e4a9 6 *
mturner5 0:72480818e4a9 7 * @note
mturner5 0:72480818e4a9 8 *
mturner5 0:72480818e4a9 9 ******************************************************************************/
mturner5 0:72480818e4a9 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mturner5 0:72480818e4a9 11
mturner5 0:72480818e4a9 12 All rights reserved.
mturner5 0:72480818e4a9 13 Redistribution and use in source and binary forms, with or without
mturner5 0:72480818e4a9 14 modification, are permitted provided that the following conditions are met:
mturner5 0:72480818e4a9 15 - Redistributions of source code must retain the above copyright
mturner5 0:72480818e4a9 16 notice, this list of conditions and the following disclaimer.
mturner5 0:72480818e4a9 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:72480818e4a9 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:72480818e4a9 19 documentation and/or other materials provided with the distribution.
mturner5 0:72480818e4a9 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:72480818e4a9 21 to endorse or promote products derived from this software without
mturner5 0:72480818e4a9 22 specific prior written permission.
mturner5 0:72480818e4a9 23 *
mturner5 0:72480818e4a9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:72480818e4a9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:72480818e4a9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:72480818e4a9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:72480818e4a9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:72480818e4a9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:72480818e4a9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:72480818e4a9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:72480818e4a9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:72480818e4a9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:72480818e4a9 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:72480818e4a9 35 ---------------------------------------------------------------------------*/
mturner5 0:72480818e4a9 36
mturner5 0:72480818e4a9 37
mturner5 0:72480818e4a9 38 #ifndef __CORE_CMFUNC_H
mturner5 0:72480818e4a9 39 #define __CORE_CMFUNC_H
mturner5 0:72480818e4a9 40
mturner5 0:72480818e4a9 41
mturner5 0:72480818e4a9 42 /* ########################### Core Function Access ########################### */
mturner5 0:72480818e4a9 43 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:72480818e4a9 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mturner5 0:72480818e4a9 45 @{
mturner5 0:72480818e4a9 46 */
mturner5 0:72480818e4a9 47
mturner5 0:72480818e4a9 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mturner5 0:72480818e4a9 49 /* ARM armcc specific functions */
mturner5 0:72480818e4a9 50
mturner5 0:72480818e4a9 51 #if (__ARMCC_VERSION < 400677)
mturner5 0:72480818e4a9 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mturner5 0:72480818e4a9 53 #endif
mturner5 0:72480818e4a9 54
mturner5 0:72480818e4a9 55 /* intrinsic void __enable_irq(); */
mturner5 0:72480818e4a9 56 /* intrinsic void __disable_irq(); */
mturner5 0:72480818e4a9 57
mturner5 0:72480818e4a9 58 /** \brief Get Control Register
mturner5 0:72480818e4a9 59
mturner5 0:72480818e4a9 60 This function returns the content of the Control Register.
mturner5 0:72480818e4a9 61
mturner5 0:72480818e4a9 62 \return Control Register value
mturner5 0:72480818e4a9 63 */
mturner5 0:72480818e4a9 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
mturner5 0:72480818e4a9 65 {
mturner5 0:72480818e4a9 66 register uint32_t __regControl __ASM("control");
mturner5 0:72480818e4a9 67 return(__regControl);
mturner5 0:72480818e4a9 68 }
mturner5 0:72480818e4a9 69
mturner5 0:72480818e4a9 70
mturner5 0:72480818e4a9 71 /** \brief Set Control Register
mturner5 0:72480818e4a9 72
mturner5 0:72480818e4a9 73 This function writes the given value to the Control Register.
mturner5 0:72480818e4a9 74
mturner5 0:72480818e4a9 75 \param [in] control Control Register value to set
mturner5 0:72480818e4a9 76 */
mturner5 0:72480818e4a9 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
mturner5 0:72480818e4a9 78 {
mturner5 0:72480818e4a9 79 register uint32_t __regControl __ASM("control");
mturner5 0:72480818e4a9 80 __regControl = control;
mturner5 0:72480818e4a9 81 }
mturner5 0:72480818e4a9 82
mturner5 0:72480818e4a9 83
mturner5 0:72480818e4a9 84 /** \brief Get IPSR Register
mturner5 0:72480818e4a9 85
mturner5 0:72480818e4a9 86 This function returns the content of the IPSR Register.
mturner5 0:72480818e4a9 87
mturner5 0:72480818e4a9 88 \return IPSR Register value
mturner5 0:72480818e4a9 89 */
mturner5 0:72480818e4a9 90 __STATIC_INLINE uint32_t __get_IPSR(void)
mturner5 0:72480818e4a9 91 {
mturner5 0:72480818e4a9 92 register uint32_t __regIPSR __ASM("ipsr");
mturner5 0:72480818e4a9 93 return(__regIPSR);
mturner5 0:72480818e4a9 94 }
mturner5 0:72480818e4a9 95
mturner5 0:72480818e4a9 96
mturner5 0:72480818e4a9 97 /** \brief Get APSR Register
mturner5 0:72480818e4a9 98
mturner5 0:72480818e4a9 99 This function returns the content of the APSR Register.
mturner5 0:72480818e4a9 100
mturner5 0:72480818e4a9 101 \return APSR Register value
mturner5 0:72480818e4a9 102 */
mturner5 0:72480818e4a9 103 __STATIC_INLINE uint32_t __get_APSR(void)
mturner5 0:72480818e4a9 104 {
mturner5 0:72480818e4a9 105 register uint32_t __regAPSR __ASM("apsr");
mturner5 0:72480818e4a9 106 return(__regAPSR);
mturner5 0:72480818e4a9 107 }
mturner5 0:72480818e4a9 108
mturner5 0:72480818e4a9 109
mturner5 0:72480818e4a9 110 /** \brief Get xPSR Register
mturner5 0:72480818e4a9 111
mturner5 0:72480818e4a9 112 This function returns the content of the xPSR Register.
mturner5 0:72480818e4a9 113
mturner5 0:72480818e4a9 114 \return xPSR Register value
mturner5 0:72480818e4a9 115 */
mturner5 0:72480818e4a9 116 __STATIC_INLINE uint32_t __get_xPSR(void)
mturner5 0:72480818e4a9 117 {
mturner5 0:72480818e4a9 118 register uint32_t __regXPSR __ASM("xpsr");
mturner5 0:72480818e4a9 119 return(__regXPSR);
mturner5 0:72480818e4a9 120 }
mturner5 0:72480818e4a9 121
mturner5 0:72480818e4a9 122
mturner5 0:72480818e4a9 123 /** \brief Get Process Stack Pointer
mturner5 0:72480818e4a9 124
mturner5 0:72480818e4a9 125 This function returns the current value of the Process Stack Pointer (PSP).
mturner5 0:72480818e4a9 126
mturner5 0:72480818e4a9 127 \return PSP Register value
mturner5 0:72480818e4a9 128 */
mturner5 0:72480818e4a9 129 __STATIC_INLINE uint32_t __get_PSP(void)
mturner5 0:72480818e4a9 130 {
mturner5 0:72480818e4a9 131 register uint32_t __regProcessStackPointer __ASM("psp");
mturner5 0:72480818e4a9 132 return(__regProcessStackPointer);
mturner5 0:72480818e4a9 133 }
mturner5 0:72480818e4a9 134
mturner5 0:72480818e4a9 135
mturner5 0:72480818e4a9 136 /** \brief Set Process Stack Pointer
mturner5 0:72480818e4a9 137
mturner5 0:72480818e4a9 138 This function assigns the given value to the Process Stack Pointer (PSP).
mturner5 0:72480818e4a9 139
mturner5 0:72480818e4a9 140 \param [in] topOfProcStack Process Stack Pointer value to set
mturner5 0:72480818e4a9 141 */
mturner5 0:72480818e4a9 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mturner5 0:72480818e4a9 143 {
mturner5 0:72480818e4a9 144 register uint32_t __regProcessStackPointer __ASM("psp");
mturner5 0:72480818e4a9 145 __regProcessStackPointer = topOfProcStack;
mturner5 0:72480818e4a9 146 }
mturner5 0:72480818e4a9 147
mturner5 0:72480818e4a9 148
mturner5 0:72480818e4a9 149 /** \brief Get Main Stack Pointer
mturner5 0:72480818e4a9 150
mturner5 0:72480818e4a9 151 This function returns the current value of the Main Stack Pointer (MSP).
mturner5 0:72480818e4a9 152
mturner5 0:72480818e4a9 153 \return MSP Register value
mturner5 0:72480818e4a9 154 */
mturner5 0:72480818e4a9 155 __STATIC_INLINE uint32_t __get_MSP(void)
mturner5 0:72480818e4a9 156 {
mturner5 0:72480818e4a9 157 register uint32_t __regMainStackPointer __ASM("msp");
mturner5 0:72480818e4a9 158 return(__regMainStackPointer);
mturner5 0:72480818e4a9 159 }
mturner5 0:72480818e4a9 160
mturner5 0:72480818e4a9 161
mturner5 0:72480818e4a9 162 /** \brief Set Main Stack Pointer
mturner5 0:72480818e4a9 163
mturner5 0:72480818e4a9 164 This function assigns the given value to the Main Stack Pointer (MSP).
mturner5 0:72480818e4a9 165
mturner5 0:72480818e4a9 166 \param [in] topOfMainStack Main Stack Pointer value to set
mturner5 0:72480818e4a9 167 */
mturner5 0:72480818e4a9 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mturner5 0:72480818e4a9 169 {
mturner5 0:72480818e4a9 170 register uint32_t __regMainStackPointer __ASM("msp");
mturner5 0:72480818e4a9 171 __regMainStackPointer = topOfMainStack;
mturner5 0:72480818e4a9 172 }
mturner5 0:72480818e4a9 173
mturner5 0:72480818e4a9 174
mturner5 0:72480818e4a9 175 /** \brief Get Priority Mask
mturner5 0:72480818e4a9 176
mturner5 0:72480818e4a9 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
mturner5 0:72480818e4a9 178
mturner5 0:72480818e4a9 179 \return Priority Mask value
mturner5 0:72480818e4a9 180 */
mturner5 0:72480818e4a9 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
mturner5 0:72480818e4a9 182 {
mturner5 0:72480818e4a9 183 register uint32_t __regPriMask __ASM("primask");
mturner5 0:72480818e4a9 184 return(__regPriMask);
mturner5 0:72480818e4a9 185 }
mturner5 0:72480818e4a9 186
mturner5 0:72480818e4a9 187
mturner5 0:72480818e4a9 188 /** \brief Set Priority Mask
mturner5 0:72480818e4a9 189
mturner5 0:72480818e4a9 190 This function assigns the given value to the Priority Mask Register.
mturner5 0:72480818e4a9 191
mturner5 0:72480818e4a9 192 \param [in] priMask Priority Mask
mturner5 0:72480818e4a9 193 */
mturner5 0:72480818e4a9 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mturner5 0:72480818e4a9 195 {
mturner5 0:72480818e4a9 196 register uint32_t __regPriMask __ASM("primask");
mturner5 0:72480818e4a9 197 __regPriMask = (priMask);
mturner5 0:72480818e4a9 198 }
mturner5 0:72480818e4a9 199
mturner5 0:72480818e4a9 200
mturner5 0:72480818e4a9 201 #if (__CORTEX_M >= 0x03)
mturner5 0:72480818e4a9 202
mturner5 0:72480818e4a9 203 /** \brief Enable FIQ
mturner5 0:72480818e4a9 204
mturner5 0:72480818e4a9 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mturner5 0:72480818e4a9 206 Can only be executed in Privileged modes.
mturner5 0:72480818e4a9 207 */
mturner5 0:72480818e4a9 208 #define __enable_fault_irq __enable_fiq
mturner5 0:72480818e4a9 209
mturner5 0:72480818e4a9 210
mturner5 0:72480818e4a9 211 /** \brief Disable FIQ
mturner5 0:72480818e4a9 212
mturner5 0:72480818e4a9 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mturner5 0:72480818e4a9 214 Can only be executed in Privileged modes.
mturner5 0:72480818e4a9 215 */
mturner5 0:72480818e4a9 216 #define __disable_fault_irq __disable_fiq
mturner5 0:72480818e4a9 217
mturner5 0:72480818e4a9 218
mturner5 0:72480818e4a9 219 /** \brief Get Base Priority
mturner5 0:72480818e4a9 220
mturner5 0:72480818e4a9 221 This function returns the current value of the Base Priority register.
mturner5 0:72480818e4a9 222
mturner5 0:72480818e4a9 223 \return Base Priority register value
mturner5 0:72480818e4a9 224 */
mturner5 0:72480818e4a9 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
mturner5 0:72480818e4a9 226 {
mturner5 0:72480818e4a9 227 register uint32_t __regBasePri __ASM("basepri");
mturner5 0:72480818e4a9 228 return(__regBasePri);
mturner5 0:72480818e4a9 229 }
mturner5 0:72480818e4a9 230
mturner5 0:72480818e4a9 231
mturner5 0:72480818e4a9 232 /** \brief Set Base Priority
mturner5 0:72480818e4a9 233
mturner5 0:72480818e4a9 234 This function assigns the given value to the Base Priority register.
mturner5 0:72480818e4a9 235
mturner5 0:72480818e4a9 236 \param [in] basePri Base Priority value to set
mturner5 0:72480818e4a9 237 */
mturner5 0:72480818e4a9 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
mturner5 0:72480818e4a9 239 {
mturner5 0:72480818e4a9 240 register uint32_t __regBasePri __ASM("basepri");
mturner5 0:72480818e4a9 241 __regBasePri = (basePri & 0xff);
mturner5 0:72480818e4a9 242 }
mturner5 0:72480818e4a9 243
mturner5 0:72480818e4a9 244
mturner5 0:72480818e4a9 245 /** \brief Get Fault Mask
mturner5 0:72480818e4a9 246
mturner5 0:72480818e4a9 247 This function returns the current value of the Fault Mask register.
mturner5 0:72480818e4a9 248
mturner5 0:72480818e4a9 249 \return Fault Mask register value
mturner5 0:72480818e4a9 250 */
mturner5 0:72480818e4a9 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mturner5 0:72480818e4a9 252 {
mturner5 0:72480818e4a9 253 register uint32_t __regFaultMask __ASM("faultmask");
mturner5 0:72480818e4a9 254 return(__regFaultMask);
mturner5 0:72480818e4a9 255 }
mturner5 0:72480818e4a9 256
mturner5 0:72480818e4a9 257
mturner5 0:72480818e4a9 258 /** \brief Set Fault Mask
mturner5 0:72480818e4a9 259
mturner5 0:72480818e4a9 260 This function assigns the given value to the Fault Mask register.
mturner5 0:72480818e4a9 261
mturner5 0:72480818e4a9 262 \param [in] faultMask Fault Mask value to set
mturner5 0:72480818e4a9 263 */
mturner5 0:72480818e4a9 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mturner5 0:72480818e4a9 265 {
mturner5 0:72480818e4a9 266 register uint32_t __regFaultMask __ASM("faultmask");
mturner5 0:72480818e4a9 267 __regFaultMask = (faultMask & (uint32_t)1);
mturner5 0:72480818e4a9 268 }
mturner5 0:72480818e4a9 269
mturner5 0:72480818e4a9 270 #endif /* (__CORTEX_M >= 0x03) */
mturner5 0:72480818e4a9 271
mturner5 0:72480818e4a9 272
mturner5 0:72480818e4a9 273 #if (__CORTEX_M == 0x04)
mturner5 0:72480818e4a9 274
mturner5 0:72480818e4a9 275 /** \brief Get FPSCR
mturner5 0:72480818e4a9 276
mturner5 0:72480818e4a9 277 This function returns the current value of the Floating Point Status/Control register.
mturner5 0:72480818e4a9 278
mturner5 0:72480818e4a9 279 \return Floating Point Status/Control register value
mturner5 0:72480818e4a9 280 */
mturner5 0:72480818e4a9 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
mturner5 0:72480818e4a9 282 {
mturner5 0:72480818e4a9 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:72480818e4a9 284 register uint32_t __regfpscr __ASM("fpscr");
mturner5 0:72480818e4a9 285 return(__regfpscr);
mturner5 0:72480818e4a9 286 #else
mturner5 0:72480818e4a9 287 return(0);
mturner5 0:72480818e4a9 288 #endif
mturner5 0:72480818e4a9 289 }
mturner5 0:72480818e4a9 290
mturner5 0:72480818e4a9 291
mturner5 0:72480818e4a9 292 /** \brief Set FPSCR
mturner5 0:72480818e4a9 293
mturner5 0:72480818e4a9 294 This function assigns the given value to the Floating Point Status/Control register.
mturner5 0:72480818e4a9 295
mturner5 0:72480818e4a9 296 \param [in] fpscr Floating Point Status/Control value to set
mturner5 0:72480818e4a9 297 */
mturner5 0:72480818e4a9 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mturner5 0:72480818e4a9 299 {
mturner5 0:72480818e4a9 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:72480818e4a9 301 register uint32_t __regfpscr __ASM("fpscr");
mturner5 0:72480818e4a9 302 __regfpscr = (fpscr);
mturner5 0:72480818e4a9 303 #endif
mturner5 0:72480818e4a9 304 }
mturner5 0:72480818e4a9 305
mturner5 0:72480818e4a9 306 #endif /* (__CORTEX_M == 0x04) */
mturner5 0:72480818e4a9 307
mturner5 0:72480818e4a9 308
mturner5 0:72480818e4a9 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mturner5 0:72480818e4a9 310 /* IAR iccarm specific functions */
mturner5 0:72480818e4a9 311
mturner5 0:72480818e4a9 312 #include <cmsis_iar.h>
mturner5 0:72480818e4a9 313
mturner5 0:72480818e4a9 314
mturner5 0:72480818e4a9 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mturner5 0:72480818e4a9 316 /* TI CCS specific functions */
mturner5 0:72480818e4a9 317
mturner5 0:72480818e4a9 318 #include <cmsis_ccs.h>
mturner5 0:72480818e4a9 319
mturner5 0:72480818e4a9 320
mturner5 0:72480818e4a9 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mturner5 0:72480818e4a9 322 /* GNU gcc specific functions */
mturner5 0:72480818e4a9 323
mturner5 0:72480818e4a9 324 /** \brief Enable IRQ Interrupts
mturner5 0:72480818e4a9 325
mturner5 0:72480818e4a9 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
mturner5 0:72480818e4a9 327 Can only be executed in Privileged modes.
mturner5 0:72480818e4a9 328 */
mturner5 0:72480818e4a9 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
mturner5 0:72480818e4a9 330 {
mturner5 0:72480818e4a9 331 __ASM volatile ("cpsie i" : : : "memory");
mturner5 0:72480818e4a9 332 }
mturner5 0:72480818e4a9 333
mturner5 0:72480818e4a9 334
mturner5 0:72480818e4a9 335 /** \brief Disable IRQ Interrupts
mturner5 0:72480818e4a9 336
mturner5 0:72480818e4a9 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
mturner5 0:72480818e4a9 338 Can only be executed in Privileged modes.
mturner5 0:72480818e4a9 339 */
mturner5 0:72480818e4a9 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
mturner5 0:72480818e4a9 341 {
mturner5 0:72480818e4a9 342 __ASM volatile ("cpsid i" : : : "memory");
mturner5 0:72480818e4a9 343 }
mturner5 0:72480818e4a9 344
mturner5 0:72480818e4a9 345
mturner5 0:72480818e4a9 346 /** \brief Get Control Register
mturner5 0:72480818e4a9 347
mturner5 0:72480818e4a9 348 This function returns the content of the Control Register.
mturner5 0:72480818e4a9 349
mturner5 0:72480818e4a9 350 \return Control Register value
mturner5 0:72480818e4a9 351 */
mturner5 0:72480818e4a9 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
mturner5 0:72480818e4a9 353 {
mturner5 0:72480818e4a9 354 uint32_t result;
mturner5 0:72480818e4a9 355
mturner5 0:72480818e4a9 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
mturner5 0:72480818e4a9 357 return(result);
mturner5 0:72480818e4a9 358 }
mturner5 0:72480818e4a9 359
mturner5 0:72480818e4a9 360
mturner5 0:72480818e4a9 361 /** \brief Set Control Register
mturner5 0:72480818e4a9 362
mturner5 0:72480818e4a9 363 This function writes the given value to the Control Register.
mturner5 0:72480818e4a9 364
mturner5 0:72480818e4a9 365 \param [in] control Control Register value to set
mturner5 0:72480818e4a9 366 */
mturner5 0:72480818e4a9 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
mturner5 0:72480818e4a9 368 {
mturner5 0:72480818e4a9 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
mturner5 0:72480818e4a9 370 }
mturner5 0:72480818e4a9 371
mturner5 0:72480818e4a9 372
mturner5 0:72480818e4a9 373 /** \brief Get IPSR Register
mturner5 0:72480818e4a9 374
mturner5 0:72480818e4a9 375 This function returns the content of the IPSR Register.
mturner5 0:72480818e4a9 376
mturner5 0:72480818e4a9 377 \return IPSR Register value
mturner5 0:72480818e4a9 378 */
mturner5 0:72480818e4a9 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
mturner5 0:72480818e4a9 380 {
mturner5 0:72480818e4a9 381 uint32_t result;
mturner5 0:72480818e4a9 382
mturner5 0:72480818e4a9 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
mturner5 0:72480818e4a9 384 return(result);
mturner5 0:72480818e4a9 385 }
mturner5 0:72480818e4a9 386
mturner5 0:72480818e4a9 387
mturner5 0:72480818e4a9 388 /** \brief Get APSR Register
mturner5 0:72480818e4a9 389
mturner5 0:72480818e4a9 390 This function returns the content of the APSR Register.
mturner5 0:72480818e4a9 391
mturner5 0:72480818e4a9 392 \return APSR Register value
mturner5 0:72480818e4a9 393 */
mturner5 0:72480818e4a9 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
mturner5 0:72480818e4a9 395 {
mturner5 0:72480818e4a9 396 uint32_t result;
mturner5 0:72480818e4a9 397
mturner5 0:72480818e4a9 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
mturner5 0:72480818e4a9 399 return(result);
mturner5 0:72480818e4a9 400 }
mturner5 0:72480818e4a9 401
mturner5 0:72480818e4a9 402
mturner5 0:72480818e4a9 403 /** \brief Get xPSR Register
mturner5 0:72480818e4a9 404
mturner5 0:72480818e4a9 405 This function returns the content of the xPSR Register.
mturner5 0:72480818e4a9 406
mturner5 0:72480818e4a9 407 \return xPSR Register value
mturner5 0:72480818e4a9 408 */
mturner5 0:72480818e4a9 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
mturner5 0:72480818e4a9 410 {
mturner5 0:72480818e4a9 411 uint32_t result;
mturner5 0:72480818e4a9 412
mturner5 0:72480818e4a9 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
mturner5 0:72480818e4a9 414 return(result);
mturner5 0:72480818e4a9 415 }
mturner5 0:72480818e4a9 416
mturner5 0:72480818e4a9 417
mturner5 0:72480818e4a9 418 /** \brief Get Process Stack Pointer
mturner5 0:72480818e4a9 419
mturner5 0:72480818e4a9 420 This function returns the current value of the Process Stack Pointer (PSP).
mturner5 0:72480818e4a9 421
mturner5 0:72480818e4a9 422 \return PSP Register value
mturner5 0:72480818e4a9 423 */
mturner5 0:72480818e4a9 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
mturner5 0:72480818e4a9 425 {
mturner5 0:72480818e4a9 426 register uint32_t result;
mturner5 0:72480818e4a9 427
mturner5 0:72480818e4a9 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
mturner5 0:72480818e4a9 429 return(result);
mturner5 0:72480818e4a9 430 }
mturner5 0:72480818e4a9 431
mturner5 0:72480818e4a9 432
mturner5 0:72480818e4a9 433 /** \brief Set Process Stack Pointer
mturner5 0:72480818e4a9 434
mturner5 0:72480818e4a9 435 This function assigns the given value to the Process Stack Pointer (PSP).
mturner5 0:72480818e4a9 436
mturner5 0:72480818e4a9 437 \param [in] topOfProcStack Process Stack Pointer value to set
mturner5 0:72480818e4a9 438 */
mturner5 0:72480818e4a9 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mturner5 0:72480818e4a9 440 {
mturner5 0:72480818e4a9 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
mturner5 0:72480818e4a9 442 }
mturner5 0:72480818e4a9 443
mturner5 0:72480818e4a9 444
mturner5 0:72480818e4a9 445 /** \brief Get Main Stack Pointer
mturner5 0:72480818e4a9 446
mturner5 0:72480818e4a9 447 This function returns the current value of the Main Stack Pointer (MSP).
mturner5 0:72480818e4a9 448
mturner5 0:72480818e4a9 449 \return MSP Register value
mturner5 0:72480818e4a9 450 */
mturner5 0:72480818e4a9 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
mturner5 0:72480818e4a9 452 {
mturner5 0:72480818e4a9 453 register uint32_t result;
mturner5 0:72480818e4a9 454
mturner5 0:72480818e4a9 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
mturner5 0:72480818e4a9 456 return(result);
mturner5 0:72480818e4a9 457 }
mturner5 0:72480818e4a9 458
mturner5 0:72480818e4a9 459
mturner5 0:72480818e4a9 460 /** \brief Set Main Stack Pointer
mturner5 0:72480818e4a9 461
mturner5 0:72480818e4a9 462 This function assigns the given value to the Main Stack Pointer (MSP).
mturner5 0:72480818e4a9 463
mturner5 0:72480818e4a9 464 \param [in] topOfMainStack Main Stack Pointer value to set
mturner5 0:72480818e4a9 465 */
mturner5 0:72480818e4a9 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mturner5 0:72480818e4a9 467 {
mturner5 0:72480818e4a9 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
mturner5 0:72480818e4a9 469 }
mturner5 0:72480818e4a9 470
mturner5 0:72480818e4a9 471
mturner5 0:72480818e4a9 472 /** \brief Get Priority Mask
mturner5 0:72480818e4a9 473
mturner5 0:72480818e4a9 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
mturner5 0:72480818e4a9 475
mturner5 0:72480818e4a9 476 \return Priority Mask value
mturner5 0:72480818e4a9 477 */
mturner5 0:72480818e4a9 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
mturner5 0:72480818e4a9 479 {
mturner5 0:72480818e4a9 480 uint32_t result;
mturner5 0:72480818e4a9 481
mturner5 0:72480818e4a9 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
mturner5 0:72480818e4a9 483 return(result);
mturner5 0:72480818e4a9 484 }
mturner5 0:72480818e4a9 485
mturner5 0:72480818e4a9 486
mturner5 0:72480818e4a9 487 /** \brief Set Priority Mask
mturner5 0:72480818e4a9 488
mturner5 0:72480818e4a9 489 This function assigns the given value to the Priority Mask Register.
mturner5 0:72480818e4a9 490
mturner5 0:72480818e4a9 491 \param [in] priMask Priority Mask
mturner5 0:72480818e4a9 492 */
mturner5 0:72480818e4a9 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mturner5 0:72480818e4a9 494 {
mturner5 0:72480818e4a9 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
mturner5 0:72480818e4a9 496 }
mturner5 0:72480818e4a9 497
mturner5 0:72480818e4a9 498
mturner5 0:72480818e4a9 499 #if (__CORTEX_M >= 0x03)
mturner5 0:72480818e4a9 500
mturner5 0:72480818e4a9 501 /** \brief Enable FIQ
mturner5 0:72480818e4a9 502
mturner5 0:72480818e4a9 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mturner5 0:72480818e4a9 504 Can only be executed in Privileged modes.
mturner5 0:72480818e4a9 505 */
mturner5 0:72480818e4a9 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
mturner5 0:72480818e4a9 507 {
mturner5 0:72480818e4a9 508 __ASM volatile ("cpsie f" : : : "memory");
mturner5 0:72480818e4a9 509 }
mturner5 0:72480818e4a9 510
mturner5 0:72480818e4a9 511
mturner5 0:72480818e4a9 512 /** \brief Disable FIQ
mturner5 0:72480818e4a9 513
mturner5 0:72480818e4a9 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mturner5 0:72480818e4a9 515 Can only be executed in Privileged modes.
mturner5 0:72480818e4a9 516 */
mturner5 0:72480818e4a9 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
mturner5 0:72480818e4a9 518 {
mturner5 0:72480818e4a9 519 __ASM volatile ("cpsid f" : : : "memory");
mturner5 0:72480818e4a9 520 }
mturner5 0:72480818e4a9 521
mturner5 0:72480818e4a9 522
mturner5 0:72480818e4a9 523 /** \brief Get Base Priority
mturner5 0:72480818e4a9 524
mturner5 0:72480818e4a9 525 This function returns the current value of the Base Priority register.
mturner5 0:72480818e4a9 526
mturner5 0:72480818e4a9 527 \return Base Priority register value
mturner5 0:72480818e4a9 528 */
mturner5 0:72480818e4a9 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
mturner5 0:72480818e4a9 530 {
mturner5 0:72480818e4a9 531 uint32_t result;
mturner5 0:72480818e4a9 532
mturner5 0:72480818e4a9 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
mturner5 0:72480818e4a9 534 return(result);
mturner5 0:72480818e4a9 535 }
mturner5 0:72480818e4a9 536
mturner5 0:72480818e4a9 537
mturner5 0:72480818e4a9 538 /** \brief Set Base Priority
mturner5 0:72480818e4a9 539
mturner5 0:72480818e4a9 540 This function assigns the given value to the Base Priority register.
mturner5 0:72480818e4a9 541
mturner5 0:72480818e4a9 542 \param [in] basePri Base Priority value to set
mturner5 0:72480818e4a9 543 */
mturner5 0:72480818e4a9 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
mturner5 0:72480818e4a9 545 {
mturner5 0:72480818e4a9 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
mturner5 0:72480818e4a9 547 }
mturner5 0:72480818e4a9 548
mturner5 0:72480818e4a9 549
mturner5 0:72480818e4a9 550 /** \brief Get Fault Mask
mturner5 0:72480818e4a9 551
mturner5 0:72480818e4a9 552 This function returns the current value of the Fault Mask register.
mturner5 0:72480818e4a9 553
mturner5 0:72480818e4a9 554 \return Fault Mask register value
mturner5 0:72480818e4a9 555 */
mturner5 0:72480818e4a9 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mturner5 0:72480818e4a9 557 {
mturner5 0:72480818e4a9 558 uint32_t result;
mturner5 0:72480818e4a9 559
mturner5 0:72480818e4a9 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
mturner5 0:72480818e4a9 561 return(result);
mturner5 0:72480818e4a9 562 }
mturner5 0:72480818e4a9 563
mturner5 0:72480818e4a9 564
mturner5 0:72480818e4a9 565 /** \brief Set Fault Mask
mturner5 0:72480818e4a9 566
mturner5 0:72480818e4a9 567 This function assigns the given value to the Fault Mask register.
mturner5 0:72480818e4a9 568
mturner5 0:72480818e4a9 569 \param [in] faultMask Fault Mask value to set
mturner5 0:72480818e4a9 570 */
mturner5 0:72480818e4a9 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mturner5 0:72480818e4a9 572 {
mturner5 0:72480818e4a9 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
mturner5 0:72480818e4a9 574 }
mturner5 0:72480818e4a9 575
mturner5 0:72480818e4a9 576 #endif /* (__CORTEX_M >= 0x03) */
mturner5 0:72480818e4a9 577
mturner5 0:72480818e4a9 578
mturner5 0:72480818e4a9 579 #if (__CORTEX_M == 0x04)
mturner5 0:72480818e4a9 580
mturner5 0:72480818e4a9 581 /** \brief Get FPSCR
mturner5 0:72480818e4a9 582
mturner5 0:72480818e4a9 583 This function returns the current value of the Floating Point Status/Control register.
mturner5 0:72480818e4a9 584
mturner5 0:72480818e4a9 585 \return Floating Point Status/Control register value
mturner5 0:72480818e4a9 586 */
mturner5 0:72480818e4a9 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
mturner5 0:72480818e4a9 588 {
mturner5 0:72480818e4a9 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:72480818e4a9 590 uint32_t result;
mturner5 0:72480818e4a9 591
mturner5 0:72480818e4a9 592 /* Empty asm statement works as a scheduling barrier */
mturner5 0:72480818e4a9 593 __ASM volatile ("");
mturner5 0:72480818e4a9 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
mturner5 0:72480818e4a9 595 __ASM volatile ("");
mturner5 0:72480818e4a9 596 return(result);
mturner5 0:72480818e4a9 597 #else
mturner5 0:72480818e4a9 598 return(0);
mturner5 0:72480818e4a9 599 #endif
mturner5 0:72480818e4a9 600 }
mturner5 0:72480818e4a9 601
mturner5 0:72480818e4a9 602
mturner5 0:72480818e4a9 603 /** \brief Set FPSCR
mturner5 0:72480818e4a9 604
mturner5 0:72480818e4a9 605 This function assigns the given value to the Floating Point Status/Control register.
mturner5 0:72480818e4a9 606
mturner5 0:72480818e4a9 607 \param [in] fpscr Floating Point Status/Control value to set
mturner5 0:72480818e4a9 608 */
mturner5 0:72480818e4a9 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mturner5 0:72480818e4a9 610 {
mturner5 0:72480818e4a9 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:72480818e4a9 612 /* Empty asm statement works as a scheduling barrier */
mturner5 0:72480818e4a9 613 __ASM volatile ("");
mturner5 0:72480818e4a9 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
mturner5 0:72480818e4a9 615 __ASM volatile ("");
mturner5 0:72480818e4a9 616 #endif
mturner5 0:72480818e4a9 617 }
mturner5 0:72480818e4a9 618
mturner5 0:72480818e4a9 619 #endif /* (__CORTEX_M == 0x04) */
mturner5 0:72480818e4a9 620
mturner5 0:72480818e4a9 621
mturner5 0:72480818e4a9 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mturner5 0:72480818e4a9 623 /* TASKING carm specific functions */
mturner5 0:72480818e4a9 624
mturner5 0:72480818e4a9 625 /*
mturner5 0:72480818e4a9 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
mturner5 0:72480818e4a9 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
mturner5 0:72480818e4a9 628 * Including the CMSIS ones.
mturner5 0:72480818e4a9 629 */
mturner5 0:72480818e4a9 630
mturner5 0:72480818e4a9 631 #endif
mturner5 0:72480818e4a9 632
mturner5 0:72480818e4a9 633 /*@} end of CMSIS_Core_RegAccFunctions */
mturner5 0:72480818e4a9 634
mturner5 0:72480818e4a9 635
mturner5 0:72480818e4a9 636 #endif /* __CORE_CMFUNC_H */