Mark Turner / MarksMbed

This is a repository for all my programs or modified programs.

TARGET_KL46Z/core_cm4.h@0:72480818e4a9, 2016-09-11 (annotated)

Committer:
mturner5
Date:
Sun Sep 11 23:48:09 2016 +0000
Revision:
0:72480818e4a9
Made delays for the LEDS and button presses

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:72480818e4a9 1 /**************************************************************************//**
mturner5 0:72480818e4a9 2 * @file core_cm4.h
mturner5 0:72480818e4a9 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
mturner5 0:72480818e4a9 4 * @version V3.20
mturner5 0:72480818e4a9 5 * @date 25. February 2013
mturner5 0:72480818e4a9 6 *
mturner5 0:72480818e4a9 7 * @note
mturner5 0:72480818e4a9 8 *
mturner5 0:72480818e4a9 9 ******************************************************************************/
mturner5 0:72480818e4a9 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mturner5 0:72480818e4a9 11
mturner5 0:72480818e4a9 12 All rights reserved.
mturner5 0:72480818e4a9 13 Redistribution and use in source and binary forms, with or without
mturner5 0:72480818e4a9 14 modification, are permitted provided that the following conditions are met:
mturner5 0:72480818e4a9 15 - Redistributions of source code must retain the above copyright
mturner5 0:72480818e4a9 16 notice, this list of conditions and the following disclaimer.
mturner5 0:72480818e4a9 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:72480818e4a9 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:72480818e4a9 19 documentation and/or other materials provided with the distribution.
mturner5 0:72480818e4a9 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:72480818e4a9 21 to endorse or promote products derived from this software without
mturner5 0:72480818e4a9 22 specific prior written permission.
mturner5 0:72480818e4a9 23 *
mturner5 0:72480818e4a9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:72480818e4a9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:72480818e4a9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:72480818e4a9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:72480818e4a9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:72480818e4a9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:72480818e4a9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:72480818e4a9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:72480818e4a9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:72480818e4a9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:72480818e4a9 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:72480818e4a9 35 ---------------------------------------------------------------------------*/
mturner5 0:72480818e4a9 36
mturner5 0:72480818e4a9 37
mturner5 0:72480818e4a9 38 #if defined ( __ICCARM__ )
mturner5 0:72480818e4a9 39 #pragma system_include /* treat file as system include file for MISRA check */
mturner5 0:72480818e4a9 40 #endif
mturner5 0:72480818e4a9 41
mturner5 0:72480818e4a9 42 #ifdef __cplusplus
mturner5 0:72480818e4a9 43 extern "C" {
mturner5 0:72480818e4a9 44 #endif
mturner5 0:72480818e4a9 45
mturner5 0:72480818e4a9 46 #ifndef __CORE_CM4_H_GENERIC
mturner5 0:72480818e4a9 47 #define __CORE_CM4_H_GENERIC
mturner5 0:72480818e4a9 48
mturner5 0:72480818e4a9 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mturner5 0:72480818e4a9 50 CMSIS violates the following MISRA-C:2004 rules:
mturner5 0:72480818e4a9 51
mturner5 0:72480818e4a9 52 \li Required Rule 8.5, object/function definition in header file.<br>
mturner5 0:72480818e4a9 53 Function definitions in header files are used to allow 'inlining'.
mturner5 0:72480818e4a9 54
mturner5 0:72480818e4a9 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mturner5 0:72480818e4a9 56 Unions are used for effective representation of core registers.
mturner5 0:72480818e4a9 57
mturner5 0:72480818e4a9 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mturner5 0:72480818e4a9 59 Function-like macros are used to allow more efficient code.
mturner5 0:72480818e4a9 60 */
mturner5 0:72480818e4a9 61
mturner5 0:72480818e4a9 62
mturner5 0:72480818e4a9 63 /*******************************************************************************
mturner5 0:72480818e4a9 64 * CMSIS definitions
mturner5 0:72480818e4a9 65 ******************************************************************************/
mturner5 0:72480818e4a9 66 /** \ingroup Cortex_M4
mturner5 0:72480818e4a9 67 @{
mturner5 0:72480818e4a9 68 */
mturner5 0:72480818e4a9 69
mturner5 0:72480818e4a9 70 /* CMSIS CM4 definitions */
mturner5 0:72480818e4a9 71 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mturner5 0:72480818e4a9 72 #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
mturner5 0:72480818e4a9 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
mturner5 0:72480818e4a9 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mturner5 0:72480818e4a9 75
mturner5 0:72480818e4a9 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
mturner5 0:72480818e4a9 77
mturner5 0:72480818e4a9 78
mturner5 0:72480818e4a9 79 #if defined ( __CC_ARM )
mturner5 0:72480818e4a9 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mturner5 0:72480818e4a9 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mturner5 0:72480818e4a9 82 #define __STATIC_INLINE static __inline
mturner5 0:72480818e4a9 83
mturner5 0:72480818e4a9 84 #elif defined ( __ICCARM__ )
mturner5 0:72480818e4a9 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mturner5 0:72480818e4a9 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mturner5 0:72480818e4a9 87 #define __STATIC_INLINE static inline
mturner5 0:72480818e4a9 88
mturner5 0:72480818e4a9 89 #elif defined ( __TMS470__ )
mturner5 0:72480818e4a9 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mturner5 0:72480818e4a9 91 #define __STATIC_INLINE static inline
mturner5 0:72480818e4a9 92
mturner5 0:72480818e4a9 93 #elif defined ( __GNUC__ )
mturner5 0:72480818e4a9 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mturner5 0:72480818e4a9 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mturner5 0:72480818e4a9 96 #define __STATIC_INLINE static inline
mturner5 0:72480818e4a9 97
mturner5 0:72480818e4a9 98 #elif defined ( __TASKING__ )
mturner5 0:72480818e4a9 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mturner5 0:72480818e4a9 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mturner5 0:72480818e4a9 101 #define __STATIC_INLINE static inline
mturner5 0:72480818e4a9 102
mturner5 0:72480818e4a9 103 #endif
mturner5 0:72480818e4a9 104
mturner5 0:72480818e4a9 105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
mturner5 0:72480818e4a9 106 */
mturner5 0:72480818e4a9 107 #if defined ( __CC_ARM )
mturner5 0:72480818e4a9 108 #if defined __TARGET_FPU_VFP
mturner5 0:72480818e4a9 109 #if (__FPU_PRESENT == 1)
mturner5 0:72480818e4a9 110 #define __FPU_USED 1
mturner5 0:72480818e4a9 111 #else
mturner5 0:72480818e4a9 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 113 #define __FPU_USED 0
mturner5 0:72480818e4a9 114 #endif
mturner5 0:72480818e4a9 115 #else
mturner5 0:72480818e4a9 116 #define __FPU_USED 0
mturner5 0:72480818e4a9 117 #endif
mturner5 0:72480818e4a9 118
mturner5 0:72480818e4a9 119 #elif defined ( __ICCARM__ )
mturner5 0:72480818e4a9 120 #if defined __ARMVFP__
mturner5 0:72480818e4a9 121 #if (__FPU_PRESENT == 1)
mturner5 0:72480818e4a9 122 #define __FPU_USED 1
mturner5 0:72480818e4a9 123 #else
mturner5 0:72480818e4a9 124 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 125 #define __FPU_USED 0
mturner5 0:72480818e4a9 126 #endif
mturner5 0:72480818e4a9 127 #else
mturner5 0:72480818e4a9 128 #define __FPU_USED 0
mturner5 0:72480818e4a9 129 #endif
mturner5 0:72480818e4a9 130
mturner5 0:72480818e4a9 131 #elif defined ( __TMS470__ )
mturner5 0:72480818e4a9 132 #if defined __TI_VFP_SUPPORT__
mturner5 0:72480818e4a9 133 #if (__FPU_PRESENT == 1)
mturner5 0:72480818e4a9 134 #define __FPU_USED 1
mturner5 0:72480818e4a9 135 #else
mturner5 0:72480818e4a9 136 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 137 #define __FPU_USED 0
mturner5 0:72480818e4a9 138 #endif
mturner5 0:72480818e4a9 139 #else
mturner5 0:72480818e4a9 140 #define __FPU_USED 0
mturner5 0:72480818e4a9 141 #endif
mturner5 0:72480818e4a9 142
mturner5 0:72480818e4a9 143 #elif defined ( __GNUC__ )
mturner5 0:72480818e4a9 144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mturner5 0:72480818e4a9 145 #if (__FPU_PRESENT == 1)
mturner5 0:72480818e4a9 146 #define __FPU_USED 1
mturner5 0:72480818e4a9 147 #else
mturner5 0:72480818e4a9 148 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 149 #define __FPU_USED 0
mturner5 0:72480818e4a9 150 #endif
mturner5 0:72480818e4a9 151 #else
mturner5 0:72480818e4a9 152 #define __FPU_USED 0
mturner5 0:72480818e4a9 153 #endif
mturner5 0:72480818e4a9 154
mturner5 0:72480818e4a9 155 #elif defined ( __TASKING__ )
mturner5 0:72480818e4a9 156 #if defined __FPU_VFP__
mturner5 0:72480818e4a9 157 #if (__FPU_PRESENT == 1)
mturner5 0:72480818e4a9 158 #define __FPU_USED 1
mturner5 0:72480818e4a9 159 #else
mturner5 0:72480818e4a9 160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 161 #define __FPU_USED 0
mturner5 0:72480818e4a9 162 #endif
mturner5 0:72480818e4a9 163 #else
mturner5 0:72480818e4a9 164 #define __FPU_USED 0
mturner5 0:72480818e4a9 165 #endif
mturner5 0:72480818e4a9 166 #endif
mturner5 0:72480818e4a9 167
mturner5 0:72480818e4a9 168 #include <stdint.h> /* standard types definitions */
mturner5 0:72480818e4a9 169 #include <core_cmInstr.h> /* Core Instruction Access */
mturner5 0:72480818e4a9 170 #include <core_cmFunc.h> /* Core Function Access */
mturner5 0:72480818e4a9 171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
mturner5 0:72480818e4a9 172
mturner5 0:72480818e4a9 173 #endif /* __CORE_CM4_H_GENERIC */
mturner5 0:72480818e4a9 174
mturner5 0:72480818e4a9 175 #ifndef __CMSIS_GENERIC
mturner5 0:72480818e4a9 176
mturner5 0:72480818e4a9 177 #ifndef __CORE_CM4_H_DEPENDANT
mturner5 0:72480818e4a9 178 #define __CORE_CM4_H_DEPENDANT
mturner5 0:72480818e4a9 179
mturner5 0:72480818e4a9 180 /* check device defines and use defaults */
mturner5 0:72480818e4a9 181 #if defined __CHECK_DEVICE_DEFINES
mturner5 0:72480818e4a9 182 #ifndef __CM4_REV
mturner5 0:72480818e4a9 183 #define __CM4_REV 0x0000
mturner5 0:72480818e4a9 184 #warning "__CM4_REV not defined in device header file; using default!"
mturner5 0:72480818e4a9 185 #endif
mturner5 0:72480818e4a9 186
mturner5 0:72480818e4a9 187 #ifndef __FPU_PRESENT
mturner5 0:72480818e4a9 188 #define __FPU_PRESENT 0
mturner5 0:72480818e4a9 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
mturner5 0:72480818e4a9 190 #endif
mturner5 0:72480818e4a9 191
mturner5 0:72480818e4a9 192 #ifndef __MPU_PRESENT
mturner5 0:72480818e4a9 193 #define __MPU_PRESENT 0
mturner5 0:72480818e4a9 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
mturner5 0:72480818e4a9 195 #endif
mturner5 0:72480818e4a9 196
mturner5 0:72480818e4a9 197 #ifndef __NVIC_PRIO_BITS
mturner5 0:72480818e4a9 198 #define __NVIC_PRIO_BITS 4
mturner5 0:72480818e4a9 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mturner5 0:72480818e4a9 200 #endif
mturner5 0:72480818e4a9 201
mturner5 0:72480818e4a9 202 #ifndef __Vendor_SysTickConfig
mturner5 0:72480818e4a9 203 #define __Vendor_SysTickConfig 0
mturner5 0:72480818e4a9 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mturner5 0:72480818e4a9 205 #endif
mturner5 0:72480818e4a9 206 #endif
mturner5 0:72480818e4a9 207
mturner5 0:72480818e4a9 208 /* IO definitions (access restrictions to peripheral registers) */
mturner5 0:72480818e4a9 209 /**
mturner5 0:72480818e4a9 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
mturner5 0:72480818e4a9 211
mturner5 0:72480818e4a9 212 <strong>IO Type Qualifiers</strong> are used
mturner5 0:72480818e4a9 213 \li to specify the access to peripheral variables.
mturner5 0:72480818e4a9 214 \li for automatic generation of peripheral register debug information.
mturner5 0:72480818e4a9 215 */
mturner5 0:72480818e4a9 216 #ifdef __cplusplus
mturner5 0:72480818e4a9 217 #define __I volatile /*!< Defines 'read only' permissions */
mturner5 0:72480818e4a9 218 #else
mturner5 0:72480818e4a9 219 #define __I volatile const /*!< Defines 'read only' permissions */
mturner5 0:72480818e4a9 220 #endif
mturner5 0:72480818e4a9 221 #define __O volatile /*!< Defines 'write only' permissions */
mturner5 0:72480818e4a9 222 #define __IO volatile /*!< Defines 'read / write' permissions */
mturner5 0:72480818e4a9 223
mturner5 0:72480818e4a9 224 /*@} end of group Cortex_M4 */
mturner5 0:72480818e4a9 225
mturner5 0:72480818e4a9 226
mturner5 0:72480818e4a9 227
mturner5 0:72480818e4a9 228 /*******************************************************************************
mturner5 0:72480818e4a9 229 * Register Abstraction
mturner5 0:72480818e4a9 230 Core Register contain:
mturner5 0:72480818e4a9 231 - Core Register
mturner5 0:72480818e4a9 232 - Core NVIC Register
mturner5 0:72480818e4a9 233 - Core SCB Register
mturner5 0:72480818e4a9 234 - Core SysTick Register
mturner5 0:72480818e4a9 235 - Core Debug Register
mturner5 0:72480818e4a9 236 - Core MPU Register
mturner5 0:72480818e4a9 237 - Core FPU Register
mturner5 0:72480818e4a9 238 ******************************************************************************/
mturner5 0:72480818e4a9 239 /** \defgroup CMSIS_core_register Defines and Type Definitions
mturner5 0:72480818e4a9 240 \brief Type definitions and defines for Cortex-M processor based devices.
mturner5 0:72480818e4a9 241 */
mturner5 0:72480818e4a9 242
mturner5 0:72480818e4a9 243 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 244 \defgroup CMSIS_CORE Status and Control Registers
mturner5 0:72480818e4a9 245 \brief Core Register type definitions.
mturner5 0:72480818e4a9 246 @{
mturner5 0:72480818e4a9 247 */
mturner5 0:72480818e4a9 248
mturner5 0:72480818e4a9 249 /** \brief Union type to access the Application Program Status Register (APSR).
mturner5 0:72480818e4a9 250 */
mturner5 0:72480818e4a9 251 typedef union
mturner5 0:72480818e4a9 252 {
mturner5 0:72480818e4a9 253 struct
mturner5 0:72480818e4a9 254 {
mturner5 0:72480818e4a9 255 #if (__CORTEX_M != 0x04)
mturner5 0:72480818e4a9 256 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mturner5 0:72480818e4a9 257 #else
mturner5 0:72480818e4a9 258 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mturner5 0:72480818e4a9 259 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mturner5 0:72480818e4a9 260 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mturner5 0:72480818e4a9 261 #endif
mturner5 0:72480818e4a9 262 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mturner5 0:72480818e4a9 263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mturner5 0:72480818e4a9 264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mturner5 0:72480818e4a9 265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mturner5 0:72480818e4a9 266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mturner5 0:72480818e4a9 267 } b; /*!< Structure used for bit access */
mturner5 0:72480818e4a9 268 uint32_t w; /*!< Type used for word access */
mturner5 0:72480818e4a9 269 } APSR_Type;
mturner5 0:72480818e4a9 270
mturner5 0:72480818e4a9 271
mturner5 0:72480818e4a9 272 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mturner5 0:72480818e4a9 273 */
mturner5 0:72480818e4a9 274 typedef union
mturner5 0:72480818e4a9 275 {
mturner5 0:72480818e4a9 276 struct
mturner5 0:72480818e4a9 277 {
mturner5 0:72480818e4a9 278 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mturner5 0:72480818e4a9 279 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mturner5 0:72480818e4a9 280 } b; /*!< Structure used for bit access */
mturner5 0:72480818e4a9 281 uint32_t w; /*!< Type used for word access */
mturner5 0:72480818e4a9 282 } IPSR_Type;
mturner5 0:72480818e4a9 283
mturner5 0:72480818e4a9 284
mturner5 0:72480818e4a9 285 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mturner5 0:72480818e4a9 286 */
mturner5 0:72480818e4a9 287 typedef union
mturner5 0:72480818e4a9 288 {
mturner5 0:72480818e4a9 289 struct
mturner5 0:72480818e4a9 290 {
mturner5 0:72480818e4a9 291 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mturner5 0:72480818e4a9 292 #if (__CORTEX_M != 0x04)
mturner5 0:72480818e4a9 293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mturner5 0:72480818e4a9 294 #else
mturner5 0:72480818e4a9 295 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mturner5 0:72480818e4a9 296 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mturner5 0:72480818e4a9 297 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mturner5 0:72480818e4a9 298 #endif
mturner5 0:72480818e4a9 299 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mturner5 0:72480818e4a9 300 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mturner5 0:72480818e4a9 301 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mturner5 0:72480818e4a9 302 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mturner5 0:72480818e4a9 303 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mturner5 0:72480818e4a9 304 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mturner5 0:72480818e4a9 305 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mturner5 0:72480818e4a9 306 } b; /*!< Structure used for bit access */
mturner5 0:72480818e4a9 307 uint32_t w; /*!< Type used for word access */
mturner5 0:72480818e4a9 308 } xPSR_Type;
mturner5 0:72480818e4a9 309
mturner5 0:72480818e4a9 310
mturner5 0:72480818e4a9 311 /** \brief Union type to access the Control Registers (CONTROL).
mturner5 0:72480818e4a9 312 */
mturner5 0:72480818e4a9 313 typedef union
mturner5 0:72480818e4a9 314 {
mturner5 0:72480818e4a9 315 struct
mturner5 0:72480818e4a9 316 {
mturner5 0:72480818e4a9 317 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mturner5 0:72480818e4a9 318 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mturner5 0:72480818e4a9 319 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mturner5 0:72480818e4a9 320 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mturner5 0:72480818e4a9 321 } b; /*!< Structure used for bit access */
mturner5 0:72480818e4a9 322 uint32_t w; /*!< Type used for word access */
mturner5 0:72480818e4a9 323 } CONTROL_Type;
mturner5 0:72480818e4a9 324
mturner5 0:72480818e4a9 325 /*@} end of group CMSIS_CORE */
mturner5 0:72480818e4a9 326
mturner5 0:72480818e4a9 327
mturner5 0:72480818e4a9 328 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 329 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mturner5 0:72480818e4a9 330 \brief Type definitions for the NVIC Registers
mturner5 0:72480818e4a9 331 @{
mturner5 0:72480818e4a9 332 */
mturner5 0:72480818e4a9 333
mturner5 0:72480818e4a9 334 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mturner5 0:72480818e4a9 335 */
mturner5 0:72480818e4a9 336 typedef struct
mturner5 0:72480818e4a9 337 {
mturner5 0:72480818e4a9 338 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mturner5 0:72480818e4a9 339 uint32_t RESERVED0[24];
mturner5 0:72480818e4a9 340 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mturner5 0:72480818e4a9 341 uint32_t RSERVED1[24];
mturner5 0:72480818e4a9 342 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mturner5 0:72480818e4a9 343 uint32_t RESERVED2[24];
mturner5 0:72480818e4a9 344 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mturner5 0:72480818e4a9 345 uint32_t RESERVED3[24];
mturner5 0:72480818e4a9 346 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
mturner5 0:72480818e4a9 347 uint32_t RESERVED4[56];
mturner5 0:72480818e4a9 348 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
mturner5 0:72480818e4a9 349 uint32_t RESERVED5[644];
mturner5 0:72480818e4a9 350 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
mturner5 0:72480818e4a9 351 } NVIC_Type;
mturner5 0:72480818e4a9 352
mturner5 0:72480818e4a9 353 /* Software Triggered Interrupt Register Definitions */
mturner5 0:72480818e4a9 354 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
mturner5 0:72480818e4a9 355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
mturner5 0:72480818e4a9 356
mturner5 0:72480818e4a9 357 /*@} end of group CMSIS_NVIC */
mturner5 0:72480818e4a9 358
mturner5 0:72480818e4a9 359
mturner5 0:72480818e4a9 360 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 361 \defgroup CMSIS_SCB System Control Block (SCB)
mturner5 0:72480818e4a9 362 \brief Type definitions for the System Control Block Registers
mturner5 0:72480818e4a9 363 @{
mturner5 0:72480818e4a9 364 */
mturner5 0:72480818e4a9 365
mturner5 0:72480818e4a9 366 /** \brief Structure type to access the System Control Block (SCB).
mturner5 0:72480818e4a9 367 */
mturner5 0:72480818e4a9 368 typedef struct
mturner5 0:72480818e4a9 369 {
mturner5 0:72480818e4a9 370 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mturner5 0:72480818e4a9 371 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mturner5 0:72480818e4a9 372 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mturner5 0:72480818e4a9 373 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mturner5 0:72480818e4a9 374 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mturner5 0:72480818e4a9 375 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mturner5 0:72480818e4a9 376 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
mturner5 0:72480818e4a9 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mturner5 0:72480818e4a9 378 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
mturner5 0:72480818e4a9 379 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
mturner5 0:72480818e4a9 380 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
mturner5 0:72480818e4a9 381 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
mturner5 0:72480818e4a9 382 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
mturner5 0:72480818e4a9 383 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
mturner5 0:72480818e4a9 384 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
mturner5 0:72480818e4a9 385 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
mturner5 0:72480818e4a9 386 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
mturner5 0:72480818e4a9 387 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
mturner5 0:72480818e4a9 388 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
mturner5 0:72480818e4a9 389 uint32_t RESERVED0[5];
mturner5 0:72480818e4a9 390 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
mturner5 0:72480818e4a9 391 } SCB_Type;
mturner5 0:72480818e4a9 392
mturner5 0:72480818e4a9 393 /* SCB CPUID Register Definitions */
mturner5 0:72480818e4a9 394 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mturner5 0:72480818e4a9 395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mturner5 0:72480818e4a9 396
mturner5 0:72480818e4a9 397 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mturner5 0:72480818e4a9 398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mturner5 0:72480818e4a9 399
mturner5 0:72480818e4a9 400 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mturner5 0:72480818e4a9 401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mturner5 0:72480818e4a9 402
mturner5 0:72480818e4a9 403 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mturner5 0:72480818e4a9 404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mturner5 0:72480818e4a9 405
mturner5 0:72480818e4a9 406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mturner5 0:72480818e4a9 407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
mturner5 0:72480818e4a9 408
mturner5 0:72480818e4a9 409 /* SCB Interrupt Control State Register Definitions */
mturner5 0:72480818e4a9 410 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mturner5 0:72480818e4a9 411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mturner5 0:72480818e4a9 412
mturner5 0:72480818e4a9 413 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mturner5 0:72480818e4a9 414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mturner5 0:72480818e4a9 415
mturner5 0:72480818e4a9 416 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mturner5 0:72480818e4a9 417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mturner5 0:72480818e4a9 418
mturner5 0:72480818e4a9 419 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mturner5 0:72480818e4a9 420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mturner5 0:72480818e4a9 421
mturner5 0:72480818e4a9 422 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mturner5 0:72480818e4a9 423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mturner5 0:72480818e4a9 424
mturner5 0:72480818e4a9 425 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mturner5 0:72480818e4a9 426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mturner5 0:72480818e4a9 427
mturner5 0:72480818e4a9 428 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mturner5 0:72480818e4a9 429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mturner5 0:72480818e4a9 430
mturner5 0:72480818e4a9 431 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mturner5 0:72480818e4a9 432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mturner5 0:72480818e4a9 433
mturner5 0:72480818e4a9 434 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
mturner5 0:72480818e4a9 435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
mturner5 0:72480818e4a9 436
mturner5 0:72480818e4a9 437 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mturner5 0:72480818e4a9 438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
mturner5 0:72480818e4a9 439
mturner5 0:72480818e4a9 440 /* SCB Vector Table Offset Register Definitions */
mturner5 0:72480818e4a9 441 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
mturner5 0:72480818e4a9 442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mturner5 0:72480818e4a9 443
mturner5 0:72480818e4a9 444 /* SCB Application Interrupt and Reset Control Register Definitions */
mturner5 0:72480818e4a9 445 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mturner5 0:72480818e4a9 446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mturner5 0:72480818e4a9 447
mturner5 0:72480818e4a9 448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mturner5 0:72480818e4a9 449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mturner5 0:72480818e4a9 450
mturner5 0:72480818e4a9 451 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mturner5 0:72480818e4a9 452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mturner5 0:72480818e4a9 453
mturner5 0:72480818e4a9 454 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
mturner5 0:72480818e4a9 455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
mturner5 0:72480818e4a9 456
mturner5 0:72480818e4a9 457 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mturner5 0:72480818e4a9 458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mturner5 0:72480818e4a9 459
mturner5 0:72480818e4a9 460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mturner5 0:72480818e4a9 461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mturner5 0:72480818e4a9 462
mturner5 0:72480818e4a9 463 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
mturner5 0:72480818e4a9 464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
mturner5 0:72480818e4a9 465
mturner5 0:72480818e4a9 466 /* SCB System Control Register Definitions */
mturner5 0:72480818e4a9 467 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mturner5 0:72480818e4a9 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mturner5 0:72480818e4a9 469
mturner5 0:72480818e4a9 470 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mturner5 0:72480818e4a9 471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mturner5 0:72480818e4a9 472
mturner5 0:72480818e4a9 473 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mturner5 0:72480818e4a9 474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mturner5 0:72480818e4a9 475
mturner5 0:72480818e4a9 476 /* SCB Configuration Control Register Definitions */
mturner5 0:72480818e4a9 477 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mturner5 0:72480818e4a9 478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mturner5 0:72480818e4a9 479
mturner5 0:72480818e4a9 480 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
mturner5 0:72480818e4a9 481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
mturner5 0:72480818e4a9 482
mturner5 0:72480818e4a9 483 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
mturner5 0:72480818e4a9 484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
mturner5 0:72480818e4a9 485
mturner5 0:72480818e4a9 486 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mturner5 0:72480818e4a9 487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mturner5 0:72480818e4a9 488
mturner5 0:72480818e4a9 489 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
mturner5 0:72480818e4a9 490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
mturner5 0:72480818e4a9 491
mturner5 0:72480818e4a9 492 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
mturner5 0:72480818e4a9 493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
mturner5 0:72480818e4a9 494
mturner5 0:72480818e4a9 495 /* SCB System Handler Control and State Register Definitions */
mturner5 0:72480818e4a9 496 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
mturner5 0:72480818e4a9 497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
mturner5 0:72480818e4a9 498
mturner5 0:72480818e4a9 499 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
mturner5 0:72480818e4a9 500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
mturner5 0:72480818e4a9 501
mturner5 0:72480818e4a9 502 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
mturner5 0:72480818e4a9 503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
mturner5 0:72480818e4a9 504
mturner5 0:72480818e4a9 505 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mturner5 0:72480818e4a9 506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mturner5 0:72480818e4a9 507
mturner5 0:72480818e4a9 508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
mturner5 0:72480818e4a9 509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
mturner5 0:72480818e4a9 510
mturner5 0:72480818e4a9 511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
mturner5 0:72480818e4a9 512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
mturner5 0:72480818e4a9 513
mturner5 0:72480818e4a9 514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
mturner5 0:72480818e4a9 515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
mturner5 0:72480818e4a9 516
mturner5 0:72480818e4a9 517 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
mturner5 0:72480818e4a9 518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
mturner5 0:72480818e4a9 519
mturner5 0:72480818e4a9 520 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
mturner5 0:72480818e4a9 521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
mturner5 0:72480818e4a9 522
mturner5 0:72480818e4a9 523 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
mturner5 0:72480818e4a9 524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
mturner5 0:72480818e4a9 525
mturner5 0:72480818e4a9 526 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
mturner5 0:72480818e4a9 527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
mturner5 0:72480818e4a9 528
mturner5 0:72480818e4a9 529 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
mturner5 0:72480818e4a9 530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
mturner5 0:72480818e4a9 531
mturner5 0:72480818e4a9 532 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
mturner5 0:72480818e4a9 533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
mturner5 0:72480818e4a9 534
mturner5 0:72480818e4a9 535 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
mturner5 0:72480818e4a9 536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
mturner5 0:72480818e4a9 537
mturner5 0:72480818e4a9 538 /* SCB Configurable Fault Status Registers Definitions */
mturner5 0:72480818e4a9 539 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
mturner5 0:72480818e4a9 540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
mturner5 0:72480818e4a9 541
mturner5 0:72480818e4a9 542 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
mturner5 0:72480818e4a9 543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
mturner5 0:72480818e4a9 544
mturner5 0:72480818e4a9 545 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
mturner5 0:72480818e4a9 546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
mturner5 0:72480818e4a9 547
mturner5 0:72480818e4a9 548 /* SCB Hard Fault Status Registers Definitions */
mturner5 0:72480818e4a9 549 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
mturner5 0:72480818e4a9 550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
mturner5 0:72480818e4a9 551
mturner5 0:72480818e4a9 552 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
mturner5 0:72480818e4a9 553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
mturner5 0:72480818e4a9 554
mturner5 0:72480818e4a9 555 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
mturner5 0:72480818e4a9 556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
mturner5 0:72480818e4a9 557
mturner5 0:72480818e4a9 558 /* SCB Debug Fault Status Register Definitions */
mturner5 0:72480818e4a9 559 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
mturner5 0:72480818e4a9 560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
mturner5 0:72480818e4a9 561
mturner5 0:72480818e4a9 562 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
mturner5 0:72480818e4a9 563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
mturner5 0:72480818e4a9 564
mturner5 0:72480818e4a9 565 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
mturner5 0:72480818e4a9 566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
mturner5 0:72480818e4a9 567
mturner5 0:72480818e4a9 568 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
mturner5 0:72480818e4a9 569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
mturner5 0:72480818e4a9 570
mturner5 0:72480818e4a9 571 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
mturner5 0:72480818e4a9 572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
mturner5 0:72480818e4a9 573
mturner5 0:72480818e4a9 574 /*@} end of group CMSIS_SCB */
mturner5 0:72480818e4a9 575
mturner5 0:72480818e4a9 576
mturner5 0:72480818e4a9 577 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 578 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mturner5 0:72480818e4a9 579 \brief Type definitions for the System Control and ID Register not in the SCB
mturner5 0:72480818e4a9 580 @{
mturner5 0:72480818e4a9 581 */
mturner5 0:72480818e4a9 582
mturner5 0:72480818e4a9 583 /** \brief Structure type to access the System Control and ID Register not in the SCB.
mturner5 0:72480818e4a9 584 */
mturner5 0:72480818e4a9 585 typedef struct
mturner5 0:72480818e4a9 586 {
mturner5 0:72480818e4a9 587 uint32_t RESERVED0[1];
mturner5 0:72480818e4a9 588 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
mturner5 0:72480818e4a9 589 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mturner5 0:72480818e4a9 590 } SCnSCB_Type;
mturner5 0:72480818e4a9 591
mturner5 0:72480818e4a9 592 /* Interrupt Controller Type Register Definitions */
mturner5 0:72480818e4a9 593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
mturner5 0:72480818e4a9 594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
mturner5 0:72480818e4a9 595
mturner5 0:72480818e4a9 596 /* Auxiliary Control Register Definitions */
mturner5 0:72480818e4a9 597 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
mturner5 0:72480818e4a9 598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
mturner5 0:72480818e4a9 599
mturner5 0:72480818e4a9 600 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
mturner5 0:72480818e4a9 601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
mturner5 0:72480818e4a9 602
mturner5 0:72480818e4a9 603 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
mturner5 0:72480818e4a9 604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
mturner5 0:72480818e4a9 605
mturner5 0:72480818e4a9 606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
mturner5 0:72480818e4a9 607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
mturner5 0:72480818e4a9 608
mturner5 0:72480818e4a9 609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
mturner5 0:72480818e4a9 610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
mturner5 0:72480818e4a9 611
mturner5 0:72480818e4a9 612 /*@} end of group CMSIS_SCnotSCB */
mturner5 0:72480818e4a9 613
mturner5 0:72480818e4a9 614
mturner5 0:72480818e4a9 615 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 616 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mturner5 0:72480818e4a9 617 \brief Type definitions for the System Timer Registers.
mturner5 0:72480818e4a9 618 @{
mturner5 0:72480818e4a9 619 */
mturner5 0:72480818e4a9 620
mturner5 0:72480818e4a9 621 /** \brief Structure type to access the System Timer (SysTick).
mturner5 0:72480818e4a9 622 */
mturner5 0:72480818e4a9 623 typedef struct
mturner5 0:72480818e4a9 624 {
mturner5 0:72480818e4a9 625 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mturner5 0:72480818e4a9 626 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mturner5 0:72480818e4a9 627 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mturner5 0:72480818e4a9 628 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mturner5 0:72480818e4a9 629 } SysTick_Type;
mturner5 0:72480818e4a9 630
mturner5 0:72480818e4a9 631 /* SysTick Control / Status Register Definitions */
mturner5 0:72480818e4a9 632 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mturner5 0:72480818e4a9 633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mturner5 0:72480818e4a9 634
mturner5 0:72480818e4a9 635 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mturner5 0:72480818e4a9 636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mturner5 0:72480818e4a9 637
mturner5 0:72480818e4a9 638 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mturner5 0:72480818e4a9 639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mturner5 0:72480818e4a9 640
mturner5 0:72480818e4a9 641 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mturner5 0:72480818e4a9 642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
mturner5 0:72480818e4a9 643
mturner5 0:72480818e4a9 644 /* SysTick Reload Register Definitions */
mturner5 0:72480818e4a9 645 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mturner5 0:72480818e4a9 646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
mturner5 0:72480818e4a9 647
mturner5 0:72480818e4a9 648 /* SysTick Current Register Definitions */
mturner5 0:72480818e4a9 649 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mturner5 0:72480818e4a9 650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
mturner5 0:72480818e4a9 651
mturner5 0:72480818e4a9 652 /* SysTick Calibration Register Definitions */
mturner5 0:72480818e4a9 653 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mturner5 0:72480818e4a9 654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mturner5 0:72480818e4a9 655
mturner5 0:72480818e4a9 656 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mturner5 0:72480818e4a9 657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mturner5 0:72480818e4a9 658
mturner5 0:72480818e4a9 659 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mturner5 0:72480818e4a9 660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
mturner5 0:72480818e4a9 661
mturner5 0:72480818e4a9 662 /*@} end of group CMSIS_SysTick */
mturner5 0:72480818e4a9 663
mturner5 0:72480818e4a9 664
mturner5 0:72480818e4a9 665 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 666 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mturner5 0:72480818e4a9 667 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mturner5 0:72480818e4a9 668 @{
mturner5 0:72480818e4a9 669 */
mturner5 0:72480818e4a9 670
mturner5 0:72480818e4a9 671 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mturner5 0:72480818e4a9 672 */
mturner5 0:72480818e4a9 673 typedef struct
mturner5 0:72480818e4a9 674 {
mturner5 0:72480818e4a9 675 __O union
mturner5 0:72480818e4a9 676 {
mturner5 0:72480818e4a9 677 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
mturner5 0:72480818e4a9 678 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
mturner5 0:72480818e4a9 679 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
mturner5 0:72480818e4a9 680 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
mturner5 0:72480818e4a9 681 uint32_t RESERVED0[864];
mturner5 0:72480818e4a9 682 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
mturner5 0:72480818e4a9 683 uint32_t RESERVED1[15];
mturner5 0:72480818e4a9 684 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
mturner5 0:72480818e4a9 685 uint32_t RESERVED2[15];
mturner5 0:72480818e4a9 686 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
mturner5 0:72480818e4a9 687 uint32_t RESERVED3[29];
mturner5 0:72480818e4a9 688 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
mturner5 0:72480818e4a9 689 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
mturner5 0:72480818e4a9 690 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
mturner5 0:72480818e4a9 691 uint32_t RESERVED4[43];
mturner5 0:72480818e4a9 692 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
mturner5 0:72480818e4a9 693 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
mturner5 0:72480818e4a9 694 uint32_t RESERVED5[6];
mturner5 0:72480818e4a9 695 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
mturner5 0:72480818e4a9 696 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
mturner5 0:72480818e4a9 697 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
mturner5 0:72480818e4a9 698 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
mturner5 0:72480818e4a9 699 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
mturner5 0:72480818e4a9 700 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
mturner5 0:72480818e4a9 701 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
mturner5 0:72480818e4a9 702 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
mturner5 0:72480818e4a9 703 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
mturner5 0:72480818e4a9 704 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
mturner5 0:72480818e4a9 705 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
mturner5 0:72480818e4a9 706 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
mturner5 0:72480818e4a9 707 } ITM_Type;
mturner5 0:72480818e4a9 708
mturner5 0:72480818e4a9 709 /* ITM Trace Privilege Register Definitions */
mturner5 0:72480818e4a9 710 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
mturner5 0:72480818e4a9 711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
mturner5 0:72480818e4a9 712
mturner5 0:72480818e4a9 713 /* ITM Trace Control Register Definitions */
mturner5 0:72480818e4a9 714 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
mturner5 0:72480818e4a9 715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
mturner5 0:72480818e4a9 716
mturner5 0:72480818e4a9 717 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
mturner5 0:72480818e4a9 718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
mturner5 0:72480818e4a9 719
mturner5 0:72480818e4a9 720 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
mturner5 0:72480818e4a9 721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
mturner5 0:72480818e4a9 722
mturner5 0:72480818e4a9 723 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
mturner5 0:72480818e4a9 724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
mturner5 0:72480818e4a9 725
mturner5 0:72480818e4a9 726 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
mturner5 0:72480818e4a9 727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
mturner5 0:72480818e4a9 728
mturner5 0:72480818e4a9 729 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
mturner5 0:72480818e4a9 730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
mturner5 0:72480818e4a9 731
mturner5 0:72480818e4a9 732 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
mturner5 0:72480818e4a9 733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
mturner5 0:72480818e4a9 734
mturner5 0:72480818e4a9 735 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
mturner5 0:72480818e4a9 736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
mturner5 0:72480818e4a9 737
mturner5 0:72480818e4a9 738 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
mturner5 0:72480818e4a9 739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
mturner5 0:72480818e4a9 740
mturner5 0:72480818e4a9 741 /* ITM Integration Write Register Definitions */
mturner5 0:72480818e4a9 742 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
mturner5 0:72480818e4a9 743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
mturner5 0:72480818e4a9 744
mturner5 0:72480818e4a9 745 /* ITM Integration Read Register Definitions */
mturner5 0:72480818e4a9 746 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
mturner5 0:72480818e4a9 747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
mturner5 0:72480818e4a9 748
mturner5 0:72480818e4a9 749 /* ITM Integration Mode Control Register Definitions */
mturner5 0:72480818e4a9 750 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
mturner5 0:72480818e4a9 751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
mturner5 0:72480818e4a9 752
mturner5 0:72480818e4a9 753 /* ITM Lock Status Register Definitions */
mturner5 0:72480818e4a9 754 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
mturner5 0:72480818e4a9 755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
mturner5 0:72480818e4a9 756
mturner5 0:72480818e4a9 757 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
mturner5 0:72480818e4a9 758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
mturner5 0:72480818e4a9 759
mturner5 0:72480818e4a9 760 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
mturner5 0:72480818e4a9 761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
mturner5 0:72480818e4a9 762
mturner5 0:72480818e4a9 763 /*@}*/ /* end of group CMSIS_ITM */
mturner5 0:72480818e4a9 764
mturner5 0:72480818e4a9 765
mturner5 0:72480818e4a9 766 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 767 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mturner5 0:72480818e4a9 768 \brief Type definitions for the Data Watchpoint and Trace (DWT)
mturner5 0:72480818e4a9 769 @{
mturner5 0:72480818e4a9 770 */
mturner5 0:72480818e4a9 771
mturner5 0:72480818e4a9 772 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mturner5 0:72480818e4a9 773 */
mturner5 0:72480818e4a9 774 typedef struct
mturner5 0:72480818e4a9 775 {
mturner5 0:72480818e4a9 776 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
mturner5 0:72480818e4a9 777 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
mturner5 0:72480818e4a9 778 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
mturner5 0:72480818e4a9 779 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
mturner5 0:72480818e4a9 780 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
mturner5 0:72480818e4a9 781 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
mturner5 0:72480818e4a9 782 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
mturner5 0:72480818e4a9 783 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
mturner5 0:72480818e4a9 784 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
mturner5 0:72480818e4a9 785 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
mturner5 0:72480818e4a9 786 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
mturner5 0:72480818e4a9 787 uint32_t RESERVED0[1];
mturner5 0:72480818e4a9 788 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
mturner5 0:72480818e4a9 789 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
mturner5 0:72480818e4a9 790 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
mturner5 0:72480818e4a9 791 uint32_t RESERVED1[1];
mturner5 0:72480818e4a9 792 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
mturner5 0:72480818e4a9 793 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
mturner5 0:72480818e4a9 794 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
mturner5 0:72480818e4a9 795 uint32_t RESERVED2[1];
mturner5 0:72480818e4a9 796 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
mturner5 0:72480818e4a9 797 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
mturner5 0:72480818e4a9 798 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
mturner5 0:72480818e4a9 799 } DWT_Type;
mturner5 0:72480818e4a9 800
mturner5 0:72480818e4a9 801 /* DWT Control Register Definitions */
mturner5 0:72480818e4a9 802 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
mturner5 0:72480818e4a9 803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
mturner5 0:72480818e4a9 804
mturner5 0:72480818e4a9 805 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
mturner5 0:72480818e4a9 806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
mturner5 0:72480818e4a9 807
mturner5 0:72480818e4a9 808 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
mturner5 0:72480818e4a9 809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
mturner5 0:72480818e4a9 810
mturner5 0:72480818e4a9 811 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
mturner5 0:72480818e4a9 812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
mturner5 0:72480818e4a9 813
mturner5 0:72480818e4a9 814 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
mturner5 0:72480818e4a9 815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
mturner5 0:72480818e4a9 816
mturner5 0:72480818e4a9 817 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
mturner5 0:72480818e4a9 818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
mturner5 0:72480818e4a9 819
mturner5 0:72480818e4a9 820 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
mturner5 0:72480818e4a9 821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
mturner5 0:72480818e4a9 822
mturner5 0:72480818e4a9 823 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
mturner5 0:72480818e4a9 824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
mturner5 0:72480818e4a9 825
mturner5 0:72480818e4a9 826 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
mturner5 0:72480818e4a9 827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
mturner5 0:72480818e4a9 828
mturner5 0:72480818e4a9 829 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
mturner5 0:72480818e4a9 830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
mturner5 0:72480818e4a9 831
mturner5 0:72480818e4a9 832 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
mturner5 0:72480818e4a9 833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
mturner5 0:72480818e4a9 834
mturner5 0:72480818e4a9 835 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
mturner5 0:72480818e4a9 836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
mturner5 0:72480818e4a9 837
mturner5 0:72480818e4a9 838 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
mturner5 0:72480818e4a9 839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
mturner5 0:72480818e4a9 840
mturner5 0:72480818e4a9 841 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
mturner5 0:72480818e4a9 842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
mturner5 0:72480818e4a9 843
mturner5 0:72480818e4a9 844 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
mturner5 0:72480818e4a9 845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
mturner5 0:72480818e4a9 846
mturner5 0:72480818e4a9 847 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
mturner5 0:72480818e4a9 848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
mturner5 0:72480818e4a9 849
mturner5 0:72480818e4a9 850 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
mturner5 0:72480818e4a9 851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
mturner5 0:72480818e4a9 852
mturner5 0:72480818e4a9 853 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
mturner5 0:72480818e4a9 854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
mturner5 0:72480818e4a9 855
mturner5 0:72480818e4a9 856 /* DWT CPI Count Register Definitions */
mturner5 0:72480818e4a9 857 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
mturner5 0:72480818e4a9 858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
mturner5 0:72480818e4a9 859
mturner5 0:72480818e4a9 860 /* DWT Exception Overhead Count Register Definitions */
mturner5 0:72480818e4a9 861 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
mturner5 0:72480818e4a9 862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
mturner5 0:72480818e4a9 863
mturner5 0:72480818e4a9 864 /* DWT Sleep Count Register Definitions */
mturner5 0:72480818e4a9 865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
mturner5 0:72480818e4a9 866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
mturner5 0:72480818e4a9 867
mturner5 0:72480818e4a9 868 /* DWT LSU Count Register Definitions */
mturner5 0:72480818e4a9 869 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
mturner5 0:72480818e4a9 870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
mturner5 0:72480818e4a9 871
mturner5 0:72480818e4a9 872 /* DWT Folded-instruction Count Register Definitions */
mturner5 0:72480818e4a9 873 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
mturner5 0:72480818e4a9 874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
mturner5 0:72480818e4a9 875
mturner5 0:72480818e4a9 876 /* DWT Comparator Mask Register Definitions */
mturner5 0:72480818e4a9 877 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
mturner5 0:72480818e4a9 878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
mturner5 0:72480818e4a9 879
mturner5 0:72480818e4a9 880 /* DWT Comparator Function Register Definitions */
mturner5 0:72480818e4a9 881 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
mturner5 0:72480818e4a9 882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
mturner5 0:72480818e4a9 883
mturner5 0:72480818e4a9 884 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
mturner5 0:72480818e4a9 885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
mturner5 0:72480818e4a9 886
mturner5 0:72480818e4a9 887 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
mturner5 0:72480818e4a9 888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
mturner5 0:72480818e4a9 889
mturner5 0:72480818e4a9 890 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
mturner5 0:72480818e4a9 891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
mturner5 0:72480818e4a9 892
mturner5 0:72480818e4a9 893 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
mturner5 0:72480818e4a9 894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
mturner5 0:72480818e4a9 895
mturner5 0:72480818e4a9 896 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
mturner5 0:72480818e4a9 897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
mturner5 0:72480818e4a9 898
mturner5 0:72480818e4a9 899 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
mturner5 0:72480818e4a9 900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
mturner5 0:72480818e4a9 901
mturner5 0:72480818e4a9 902 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
mturner5 0:72480818e4a9 903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
mturner5 0:72480818e4a9 904
mturner5 0:72480818e4a9 905 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
mturner5 0:72480818e4a9 906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
mturner5 0:72480818e4a9 907
mturner5 0:72480818e4a9 908 /*@}*/ /* end of group CMSIS_DWT */
mturner5 0:72480818e4a9 909
mturner5 0:72480818e4a9 910
mturner5 0:72480818e4a9 911 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 912 \defgroup CMSIS_TPI Trace Port Interface (TPI)
mturner5 0:72480818e4a9 913 \brief Type definitions for the Trace Port Interface (TPI)
mturner5 0:72480818e4a9 914 @{
mturner5 0:72480818e4a9 915 */
mturner5 0:72480818e4a9 916
mturner5 0:72480818e4a9 917 /** \brief Structure type to access the Trace Port Interface Register (TPI).
mturner5 0:72480818e4a9 918 */
mturner5 0:72480818e4a9 919 typedef struct
mturner5 0:72480818e4a9 920 {
mturner5 0:72480818e4a9 921 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
mturner5 0:72480818e4a9 922 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
mturner5 0:72480818e4a9 923 uint32_t RESERVED0[2];
mturner5 0:72480818e4a9 924 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
mturner5 0:72480818e4a9 925 uint32_t RESERVED1[55];
mturner5 0:72480818e4a9 926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
mturner5 0:72480818e4a9 927 uint32_t RESERVED2[131];
mturner5 0:72480818e4a9 928 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
mturner5 0:72480818e4a9 929 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
mturner5 0:72480818e4a9 930 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
mturner5 0:72480818e4a9 931 uint32_t RESERVED3[759];
mturner5 0:72480818e4a9 932 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
mturner5 0:72480818e4a9 933 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
mturner5 0:72480818e4a9 934 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
mturner5 0:72480818e4a9 935 uint32_t RESERVED4[1];
mturner5 0:72480818e4a9 936 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
mturner5 0:72480818e4a9 937 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
mturner5 0:72480818e4a9 938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
mturner5 0:72480818e4a9 939 uint32_t RESERVED5[39];
mturner5 0:72480818e4a9 940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
mturner5 0:72480818e4a9 941 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
mturner5 0:72480818e4a9 942 uint32_t RESERVED7[8];
mturner5 0:72480818e4a9 943 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
mturner5 0:72480818e4a9 944 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
mturner5 0:72480818e4a9 945 } TPI_Type;
mturner5 0:72480818e4a9 946
mturner5 0:72480818e4a9 947 /* TPI Asynchronous Clock Prescaler Register Definitions */
mturner5 0:72480818e4a9 948 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
mturner5 0:72480818e4a9 949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
mturner5 0:72480818e4a9 950
mturner5 0:72480818e4a9 951 /* TPI Selected Pin Protocol Register Definitions */
mturner5 0:72480818e4a9 952 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
mturner5 0:72480818e4a9 953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
mturner5 0:72480818e4a9 954
mturner5 0:72480818e4a9 955 /* TPI Formatter and Flush Status Register Definitions */
mturner5 0:72480818e4a9 956 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
mturner5 0:72480818e4a9 957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
mturner5 0:72480818e4a9 958
mturner5 0:72480818e4a9 959 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
mturner5 0:72480818e4a9 960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
mturner5 0:72480818e4a9 961
mturner5 0:72480818e4a9 962 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
mturner5 0:72480818e4a9 963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
mturner5 0:72480818e4a9 964
mturner5 0:72480818e4a9 965 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
mturner5 0:72480818e4a9 966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
mturner5 0:72480818e4a9 967
mturner5 0:72480818e4a9 968 /* TPI Formatter and Flush Control Register Definitions */
mturner5 0:72480818e4a9 969 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
mturner5 0:72480818e4a9 970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
mturner5 0:72480818e4a9 971
mturner5 0:72480818e4a9 972 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
mturner5 0:72480818e4a9 973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
mturner5 0:72480818e4a9 974
mturner5 0:72480818e4a9 975 /* TPI TRIGGER Register Definitions */
mturner5 0:72480818e4a9 976 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
mturner5 0:72480818e4a9 977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
mturner5 0:72480818e4a9 978
mturner5 0:72480818e4a9 979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
mturner5 0:72480818e4a9 980 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
mturner5 0:72480818e4a9 981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
mturner5 0:72480818e4a9 982
mturner5 0:72480818e4a9 983 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
mturner5 0:72480818e4a9 984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
mturner5 0:72480818e4a9 985
mturner5 0:72480818e4a9 986 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
mturner5 0:72480818e4a9 987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
mturner5 0:72480818e4a9 988
mturner5 0:72480818e4a9 989 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
mturner5 0:72480818e4a9 990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
mturner5 0:72480818e4a9 991
mturner5 0:72480818e4a9 992 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
mturner5 0:72480818e4a9 993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
mturner5 0:72480818e4a9 994
mturner5 0:72480818e4a9 995 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
mturner5 0:72480818e4a9 996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
mturner5 0:72480818e4a9 997
mturner5 0:72480818e4a9 998 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
mturner5 0:72480818e4a9 999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
mturner5 0:72480818e4a9 1000
mturner5 0:72480818e4a9 1001 /* TPI ITATBCTR2 Register Definitions */
mturner5 0:72480818e4a9 1002 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
mturner5 0:72480818e4a9 1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
mturner5 0:72480818e4a9 1004
mturner5 0:72480818e4a9 1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
mturner5 0:72480818e4a9 1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
mturner5 0:72480818e4a9 1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
mturner5 0:72480818e4a9 1008
mturner5 0:72480818e4a9 1009 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
mturner5 0:72480818e4a9 1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
mturner5 0:72480818e4a9 1011
mturner5 0:72480818e4a9 1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
mturner5 0:72480818e4a9 1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
mturner5 0:72480818e4a9 1014
mturner5 0:72480818e4a9 1015 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
mturner5 0:72480818e4a9 1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
mturner5 0:72480818e4a9 1017
mturner5 0:72480818e4a9 1018 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
mturner5 0:72480818e4a9 1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
mturner5 0:72480818e4a9 1020
mturner5 0:72480818e4a9 1021 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
mturner5 0:72480818e4a9 1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
mturner5 0:72480818e4a9 1023
mturner5 0:72480818e4a9 1024 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
mturner5 0:72480818e4a9 1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
mturner5 0:72480818e4a9 1026
mturner5 0:72480818e4a9 1027 /* TPI ITATBCTR0 Register Definitions */
mturner5 0:72480818e4a9 1028 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
mturner5 0:72480818e4a9 1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
mturner5 0:72480818e4a9 1030
mturner5 0:72480818e4a9 1031 /* TPI Integration Mode Control Register Definitions */
mturner5 0:72480818e4a9 1032 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
mturner5 0:72480818e4a9 1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
mturner5 0:72480818e4a9 1034
mturner5 0:72480818e4a9 1035 /* TPI DEVID Register Definitions */
mturner5 0:72480818e4a9 1036 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
mturner5 0:72480818e4a9 1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
mturner5 0:72480818e4a9 1038
mturner5 0:72480818e4a9 1039 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
mturner5 0:72480818e4a9 1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
mturner5 0:72480818e4a9 1041
mturner5 0:72480818e4a9 1042 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
mturner5 0:72480818e4a9 1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
mturner5 0:72480818e4a9 1044
mturner5 0:72480818e4a9 1045 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
mturner5 0:72480818e4a9 1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
mturner5 0:72480818e4a9 1047
mturner5 0:72480818e4a9 1048 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
mturner5 0:72480818e4a9 1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
mturner5 0:72480818e4a9 1050
mturner5 0:72480818e4a9 1051 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
mturner5 0:72480818e4a9 1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
mturner5 0:72480818e4a9 1053
mturner5 0:72480818e4a9 1054 /* TPI DEVTYPE Register Definitions */
mturner5 0:72480818e4a9 1055 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
mturner5 0:72480818e4a9 1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
mturner5 0:72480818e4a9 1057
mturner5 0:72480818e4a9 1058 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
mturner5 0:72480818e4a9 1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
mturner5 0:72480818e4a9 1060
mturner5 0:72480818e4a9 1061 /*@}*/ /* end of group CMSIS_TPI */
mturner5 0:72480818e4a9 1062
mturner5 0:72480818e4a9 1063
mturner5 0:72480818e4a9 1064 #if (__MPU_PRESENT == 1)
mturner5 0:72480818e4a9 1065 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 1066 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mturner5 0:72480818e4a9 1067 \brief Type definitions for the Memory Protection Unit (MPU)
mturner5 0:72480818e4a9 1068 @{
mturner5 0:72480818e4a9 1069 */
mturner5 0:72480818e4a9 1070
mturner5 0:72480818e4a9 1071 /** \brief Structure type to access the Memory Protection Unit (MPU).
mturner5 0:72480818e4a9 1072 */
mturner5 0:72480818e4a9 1073 typedef struct
mturner5 0:72480818e4a9 1074 {
mturner5 0:72480818e4a9 1075 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mturner5 0:72480818e4a9 1076 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mturner5 0:72480818e4a9 1077 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mturner5 0:72480818e4a9 1078 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mturner5 0:72480818e4a9 1079 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mturner5 0:72480818e4a9 1080 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
mturner5 0:72480818e4a9 1081 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
mturner5 0:72480818e4a9 1082 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
mturner5 0:72480818e4a9 1083 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
mturner5 0:72480818e4a9 1084 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
mturner5 0:72480818e4a9 1085 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
mturner5 0:72480818e4a9 1086 } MPU_Type;
mturner5 0:72480818e4a9 1087
mturner5 0:72480818e4a9 1088 /* MPU Type Register */
mturner5 0:72480818e4a9 1089 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mturner5 0:72480818e4a9 1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mturner5 0:72480818e4a9 1091
mturner5 0:72480818e4a9 1092 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mturner5 0:72480818e4a9 1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mturner5 0:72480818e4a9 1094
mturner5 0:72480818e4a9 1095 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mturner5 0:72480818e4a9 1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
mturner5 0:72480818e4a9 1097
mturner5 0:72480818e4a9 1098 /* MPU Control Register */
mturner5 0:72480818e4a9 1099 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mturner5 0:72480818e4a9 1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mturner5 0:72480818e4a9 1101
mturner5 0:72480818e4a9 1102 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mturner5 0:72480818e4a9 1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mturner5 0:72480818e4a9 1104
mturner5 0:72480818e4a9 1105 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mturner5 0:72480818e4a9 1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
mturner5 0:72480818e4a9 1107
mturner5 0:72480818e4a9 1108 /* MPU Region Number Register */
mturner5 0:72480818e4a9 1109 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mturner5 0:72480818e4a9 1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
mturner5 0:72480818e4a9 1111
mturner5 0:72480818e4a9 1112 /* MPU Region Base Address Register */
mturner5 0:72480818e4a9 1113 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
mturner5 0:72480818e4a9 1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mturner5 0:72480818e4a9 1115
mturner5 0:72480818e4a9 1116 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mturner5 0:72480818e4a9 1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mturner5 0:72480818e4a9 1118
mturner5 0:72480818e4a9 1119 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mturner5 0:72480818e4a9 1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
mturner5 0:72480818e4a9 1121
mturner5 0:72480818e4a9 1122 /* MPU Region Attribute and Size Register */
mturner5 0:72480818e4a9 1123 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mturner5 0:72480818e4a9 1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mturner5 0:72480818e4a9 1125
mturner5 0:72480818e4a9 1126 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mturner5 0:72480818e4a9 1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mturner5 0:72480818e4a9 1128
mturner5 0:72480818e4a9 1129 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mturner5 0:72480818e4a9 1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mturner5 0:72480818e4a9 1131
mturner5 0:72480818e4a9 1132 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mturner5 0:72480818e4a9 1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mturner5 0:72480818e4a9 1134
mturner5 0:72480818e4a9 1135 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mturner5 0:72480818e4a9 1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mturner5 0:72480818e4a9 1137
mturner5 0:72480818e4a9 1138 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mturner5 0:72480818e4a9 1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mturner5 0:72480818e4a9 1140
mturner5 0:72480818e4a9 1141 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mturner5 0:72480818e4a9 1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mturner5 0:72480818e4a9 1143
mturner5 0:72480818e4a9 1144 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mturner5 0:72480818e4a9 1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mturner5 0:72480818e4a9 1146
mturner5 0:72480818e4a9 1147 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mturner5 0:72480818e4a9 1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mturner5 0:72480818e4a9 1149
mturner5 0:72480818e4a9 1150 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mturner5 0:72480818e4a9 1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
mturner5 0:72480818e4a9 1152
mturner5 0:72480818e4a9 1153 /*@} end of group CMSIS_MPU */
mturner5 0:72480818e4a9 1154 #endif
mturner5 0:72480818e4a9 1155
mturner5 0:72480818e4a9 1156
mturner5 0:72480818e4a9 1157 #if (__FPU_PRESENT == 1)
mturner5 0:72480818e4a9 1158 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 1159 \defgroup CMSIS_FPU Floating Point Unit (FPU)
mturner5 0:72480818e4a9 1160 \brief Type definitions for the Floating Point Unit (FPU)
mturner5 0:72480818e4a9 1161 @{
mturner5 0:72480818e4a9 1162 */
mturner5 0:72480818e4a9 1163
mturner5 0:72480818e4a9 1164 /** \brief Structure type to access the Floating Point Unit (FPU).
mturner5 0:72480818e4a9 1165 */
mturner5 0:72480818e4a9 1166 typedef struct
mturner5 0:72480818e4a9 1167 {
mturner5 0:72480818e4a9 1168 uint32_t RESERVED0[1];
mturner5 0:72480818e4a9 1169 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
mturner5 0:72480818e4a9 1170 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
mturner5 0:72480818e4a9 1171 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
mturner5 0:72480818e4a9 1172 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
mturner5 0:72480818e4a9 1173 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
mturner5 0:72480818e4a9 1174 } FPU_Type;
mturner5 0:72480818e4a9 1175
mturner5 0:72480818e4a9 1176 /* Floating-Point Context Control Register */
mturner5 0:72480818e4a9 1177 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
mturner5 0:72480818e4a9 1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
mturner5 0:72480818e4a9 1179
mturner5 0:72480818e4a9 1180 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
mturner5 0:72480818e4a9 1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
mturner5 0:72480818e4a9 1182
mturner5 0:72480818e4a9 1183 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
mturner5 0:72480818e4a9 1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
mturner5 0:72480818e4a9 1185
mturner5 0:72480818e4a9 1186 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
mturner5 0:72480818e4a9 1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
mturner5 0:72480818e4a9 1188
mturner5 0:72480818e4a9 1189 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
mturner5 0:72480818e4a9 1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
mturner5 0:72480818e4a9 1191
mturner5 0:72480818e4a9 1192 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
mturner5 0:72480818e4a9 1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
mturner5 0:72480818e4a9 1194
mturner5 0:72480818e4a9 1195 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
mturner5 0:72480818e4a9 1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
mturner5 0:72480818e4a9 1197
mturner5 0:72480818e4a9 1198 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
mturner5 0:72480818e4a9 1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
mturner5 0:72480818e4a9 1200
mturner5 0:72480818e4a9 1201 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
mturner5 0:72480818e4a9 1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
mturner5 0:72480818e4a9 1203
mturner5 0:72480818e4a9 1204 /* Floating-Point Context Address Register */
mturner5 0:72480818e4a9 1205 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
mturner5 0:72480818e4a9 1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
mturner5 0:72480818e4a9 1207
mturner5 0:72480818e4a9 1208 /* Floating-Point Default Status Control Register */
mturner5 0:72480818e4a9 1209 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
mturner5 0:72480818e4a9 1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
mturner5 0:72480818e4a9 1211
mturner5 0:72480818e4a9 1212 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
mturner5 0:72480818e4a9 1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
mturner5 0:72480818e4a9 1214
mturner5 0:72480818e4a9 1215 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
mturner5 0:72480818e4a9 1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
mturner5 0:72480818e4a9 1217
mturner5 0:72480818e4a9 1218 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
mturner5 0:72480818e4a9 1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
mturner5 0:72480818e4a9 1220
mturner5 0:72480818e4a9 1221 /* Media and FP Feature Register 0 */
mturner5 0:72480818e4a9 1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
mturner5 0:72480818e4a9 1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
mturner5 0:72480818e4a9 1224
mturner5 0:72480818e4a9 1225 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
mturner5 0:72480818e4a9 1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
mturner5 0:72480818e4a9 1227
mturner5 0:72480818e4a9 1228 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
mturner5 0:72480818e4a9 1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
mturner5 0:72480818e4a9 1230
mturner5 0:72480818e4a9 1231 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
mturner5 0:72480818e4a9 1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
mturner5 0:72480818e4a9 1233
mturner5 0:72480818e4a9 1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
mturner5 0:72480818e4a9 1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
mturner5 0:72480818e4a9 1236
mturner5 0:72480818e4a9 1237 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
mturner5 0:72480818e4a9 1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
mturner5 0:72480818e4a9 1239
mturner5 0:72480818e4a9 1240 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
mturner5 0:72480818e4a9 1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
mturner5 0:72480818e4a9 1242
mturner5 0:72480818e4a9 1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
mturner5 0:72480818e4a9 1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
mturner5 0:72480818e4a9 1245
mturner5 0:72480818e4a9 1246 /* Media and FP Feature Register 1 */
mturner5 0:72480818e4a9 1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
mturner5 0:72480818e4a9 1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
mturner5 0:72480818e4a9 1249
mturner5 0:72480818e4a9 1250 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
mturner5 0:72480818e4a9 1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
mturner5 0:72480818e4a9 1252
mturner5 0:72480818e4a9 1253 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
mturner5 0:72480818e4a9 1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
mturner5 0:72480818e4a9 1255
mturner5 0:72480818e4a9 1256 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
mturner5 0:72480818e4a9 1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
mturner5 0:72480818e4a9 1258
mturner5 0:72480818e4a9 1259 /*@} end of group CMSIS_FPU */
mturner5 0:72480818e4a9 1260 #endif
mturner5 0:72480818e4a9 1261
mturner5 0:72480818e4a9 1262
mturner5 0:72480818e4a9 1263 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 1264 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mturner5 0:72480818e4a9 1265 \brief Type definitions for the Core Debug Registers
mturner5 0:72480818e4a9 1266 @{
mturner5 0:72480818e4a9 1267 */
mturner5 0:72480818e4a9 1268
mturner5 0:72480818e4a9 1269 /** \brief Structure type to access the Core Debug Register (CoreDebug).
mturner5 0:72480818e4a9 1270 */
mturner5 0:72480818e4a9 1271 typedef struct
mturner5 0:72480818e4a9 1272 {
mturner5 0:72480818e4a9 1273 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
mturner5 0:72480818e4a9 1274 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
mturner5 0:72480818e4a9 1275 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
mturner5 0:72480818e4a9 1276 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
mturner5 0:72480818e4a9 1277 } CoreDebug_Type;
mturner5 0:72480818e4a9 1278
mturner5 0:72480818e4a9 1279 /* Debug Halting Control and Status Register */
mturner5 0:72480818e4a9 1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
mturner5 0:72480818e4a9 1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
mturner5 0:72480818e4a9 1282
mturner5 0:72480818e4a9 1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
mturner5 0:72480818e4a9 1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
mturner5 0:72480818e4a9 1285
mturner5 0:72480818e4a9 1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
mturner5 0:72480818e4a9 1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
mturner5 0:72480818e4a9 1288
mturner5 0:72480818e4a9 1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
mturner5 0:72480818e4a9 1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
mturner5 0:72480818e4a9 1291
mturner5 0:72480818e4a9 1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
mturner5 0:72480818e4a9 1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
mturner5 0:72480818e4a9 1294
mturner5 0:72480818e4a9 1295 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
mturner5 0:72480818e4a9 1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
mturner5 0:72480818e4a9 1297
mturner5 0:72480818e4a9 1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
mturner5 0:72480818e4a9 1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
mturner5 0:72480818e4a9 1300
mturner5 0:72480818e4a9 1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
mturner5 0:72480818e4a9 1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
mturner5 0:72480818e4a9 1303
mturner5 0:72480818e4a9 1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
mturner5 0:72480818e4a9 1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
mturner5 0:72480818e4a9 1306
mturner5 0:72480818e4a9 1307 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
mturner5 0:72480818e4a9 1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
mturner5 0:72480818e4a9 1309
mturner5 0:72480818e4a9 1310 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
mturner5 0:72480818e4a9 1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
mturner5 0:72480818e4a9 1312
mturner5 0:72480818e4a9 1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
mturner5 0:72480818e4a9 1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
mturner5 0:72480818e4a9 1315
mturner5 0:72480818e4a9 1316 /* Debug Core Register Selector Register */
mturner5 0:72480818e4a9 1317 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
mturner5 0:72480818e4a9 1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
mturner5 0:72480818e4a9 1319
mturner5 0:72480818e4a9 1320 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
mturner5 0:72480818e4a9 1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
mturner5 0:72480818e4a9 1322
mturner5 0:72480818e4a9 1323 /* Debug Exception and Monitor Control Register */
mturner5 0:72480818e4a9 1324 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
mturner5 0:72480818e4a9 1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
mturner5 0:72480818e4a9 1326
mturner5 0:72480818e4a9 1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
mturner5 0:72480818e4a9 1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
mturner5 0:72480818e4a9 1329
mturner5 0:72480818e4a9 1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
mturner5 0:72480818e4a9 1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
mturner5 0:72480818e4a9 1332
mturner5 0:72480818e4a9 1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
mturner5 0:72480818e4a9 1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
mturner5 0:72480818e4a9 1335
mturner5 0:72480818e4a9 1336 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
mturner5 0:72480818e4a9 1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
mturner5 0:72480818e4a9 1338
mturner5 0:72480818e4a9 1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
mturner5 0:72480818e4a9 1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
mturner5 0:72480818e4a9 1341
mturner5 0:72480818e4a9 1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
mturner5 0:72480818e4a9 1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
mturner5 0:72480818e4a9 1344
mturner5 0:72480818e4a9 1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
mturner5 0:72480818e4a9 1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
mturner5 0:72480818e4a9 1347
mturner5 0:72480818e4a9 1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
mturner5 0:72480818e4a9 1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
mturner5 0:72480818e4a9 1350
mturner5 0:72480818e4a9 1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
mturner5 0:72480818e4a9 1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
mturner5 0:72480818e4a9 1353
mturner5 0:72480818e4a9 1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
mturner5 0:72480818e4a9 1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
mturner5 0:72480818e4a9 1356
mturner5 0:72480818e4a9 1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
mturner5 0:72480818e4a9 1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
mturner5 0:72480818e4a9 1359
mturner5 0:72480818e4a9 1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
mturner5 0:72480818e4a9 1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
mturner5 0:72480818e4a9 1362
mturner5 0:72480818e4a9 1363 /*@} end of group CMSIS_CoreDebug */
mturner5 0:72480818e4a9 1364
mturner5 0:72480818e4a9 1365
mturner5 0:72480818e4a9 1366 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 1367 \defgroup CMSIS_core_base Core Definitions
mturner5 0:72480818e4a9 1368 \brief Definitions for base addresses, unions, and structures.
mturner5 0:72480818e4a9 1369 @{
mturner5 0:72480818e4a9 1370 */
mturner5 0:72480818e4a9 1371
mturner5 0:72480818e4a9 1372 /* Memory mapping of Cortex-M4 Hardware */
mturner5 0:72480818e4a9 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mturner5 0:72480818e4a9 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
mturner5 0:72480818e4a9 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
mturner5 0:72480818e4a9 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
mturner5 0:72480818e4a9 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
mturner5 0:72480818e4a9 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mturner5 0:72480818e4a9 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mturner5 0:72480818e4a9 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mturner5 0:72480818e4a9 1381
mturner5 0:72480818e4a9 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mturner5 0:72480818e4a9 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mturner5 0:72480818e4a9 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mturner5 0:72480818e4a9 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mturner5 0:72480818e4a9 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
mturner5 0:72480818e4a9 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
mturner5 0:72480818e4a9 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
mturner5 0:72480818e4a9 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
mturner5 0:72480818e4a9 1390
mturner5 0:72480818e4a9 1391 #if (__MPU_PRESENT == 1)
mturner5 0:72480818e4a9 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mturner5 0:72480818e4a9 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mturner5 0:72480818e4a9 1394 #endif
mturner5 0:72480818e4a9 1395
mturner5 0:72480818e4a9 1396 #if (__FPU_PRESENT == 1)
mturner5 0:72480818e4a9 1397 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
mturner5 0:72480818e4a9 1398 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
mturner5 0:72480818e4a9 1399 #endif
mturner5 0:72480818e4a9 1400
mturner5 0:72480818e4a9 1401 /*@} */
mturner5 0:72480818e4a9 1402
mturner5 0:72480818e4a9 1403
mturner5 0:72480818e4a9 1404
mturner5 0:72480818e4a9 1405 /*******************************************************************************
mturner5 0:72480818e4a9 1406 * Hardware Abstraction Layer
mturner5 0:72480818e4a9 1407 Core Function Interface contains:
mturner5 0:72480818e4a9 1408 - Core NVIC Functions
mturner5 0:72480818e4a9 1409 - Core SysTick Functions
mturner5 0:72480818e4a9 1410 - Core Debug Functions
mturner5 0:72480818e4a9 1411 - Core Register Access Functions
mturner5 0:72480818e4a9 1412 ******************************************************************************/
mturner5 0:72480818e4a9 1413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mturner5 0:72480818e4a9 1414 */
mturner5 0:72480818e4a9 1415
mturner5 0:72480818e4a9 1416
mturner5 0:72480818e4a9 1417
mturner5 0:72480818e4a9 1418 /* ########################## NVIC functions #################################### */
mturner5 0:72480818e4a9 1419 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:72480818e4a9 1420 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mturner5 0:72480818e4a9 1421 \brief Functions that manage interrupts and exceptions via the NVIC.
mturner5 0:72480818e4a9 1422 @{
mturner5 0:72480818e4a9 1423 */
mturner5 0:72480818e4a9 1424
mturner5 0:72480818e4a9 1425 /** \brief Set Priority Grouping
mturner5 0:72480818e4a9 1426
mturner5 0:72480818e4a9 1427 The function sets the priority grouping field using the required unlock sequence.
mturner5 0:72480818e4a9 1428 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mturner5 0:72480818e4a9 1429 Only values from 0..7 are used.
mturner5 0:72480818e4a9 1430 In case of a conflict between priority grouping and available
mturner5 0:72480818e4a9 1431 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mturner5 0:72480818e4a9 1432
mturner5 0:72480818e4a9 1433 \param [in] PriorityGroup Priority grouping field.
mturner5 0:72480818e4a9 1434 */
mturner5 0:72480818e4a9 1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mturner5 0:72480818e4a9 1436 {
mturner5 0:72480818e4a9 1437 uint32_t reg_value;
mturner5 0:72480818e4a9 1438 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
mturner5 0:72480818e4a9 1439
mturner5 0:72480818e4a9 1440 reg_value = SCB->AIRCR; /* read old register configuration */
mturner5 0:72480818e4a9 1441 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
mturner5 0:72480818e4a9 1442 reg_value = (reg_value |
mturner5 0:72480818e4a9 1443 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mturner5 0:72480818e4a9 1444 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
mturner5 0:72480818e4a9 1445 SCB->AIRCR = reg_value;
mturner5 0:72480818e4a9 1446 }
mturner5 0:72480818e4a9 1447
mturner5 0:72480818e4a9 1448
mturner5 0:72480818e4a9 1449 /** \brief Get Priority Grouping
mturner5 0:72480818e4a9 1450
mturner5 0:72480818e4a9 1451 The function reads the priority grouping field from the NVIC Interrupt Controller.
mturner5 0:72480818e4a9 1452
mturner5 0:72480818e4a9 1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mturner5 0:72480818e4a9 1454 */
mturner5 0:72480818e4a9 1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
mturner5 0:72480818e4a9 1456 {
mturner5 0:72480818e4a9 1457 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
mturner5 0:72480818e4a9 1458 }
mturner5 0:72480818e4a9 1459
mturner5 0:72480818e4a9 1460
mturner5 0:72480818e4a9 1461 /** \brief Enable External Interrupt
mturner5 0:72480818e4a9 1462
mturner5 0:72480818e4a9 1463 The function enables a device-specific interrupt in the NVIC interrupt controller.
mturner5 0:72480818e4a9 1464
mturner5 0:72480818e4a9 1465 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:72480818e4a9 1466 */
mturner5 0:72480818e4a9 1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 1468 {
mturner5 0:72480818e4a9 1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
mturner5 0:72480818e4a9 1470 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
mturner5 0:72480818e4a9 1471 }
mturner5 0:72480818e4a9 1472
mturner5 0:72480818e4a9 1473
mturner5 0:72480818e4a9 1474 /** \brief Disable External Interrupt
mturner5 0:72480818e4a9 1475
mturner5 0:72480818e4a9 1476 The function disables a device-specific interrupt in the NVIC interrupt controller.
mturner5 0:72480818e4a9 1477
mturner5 0:72480818e4a9 1478 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:72480818e4a9 1479 */
mturner5 0:72480818e4a9 1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 1481 {
mturner5 0:72480818e4a9 1482 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
mturner5 0:72480818e4a9 1483 }
mturner5 0:72480818e4a9 1484
mturner5 0:72480818e4a9 1485
mturner5 0:72480818e4a9 1486 /** \brief Get Pending Interrupt
mturner5 0:72480818e4a9 1487
mturner5 0:72480818e4a9 1488 The function reads the pending register in the NVIC and returns the pending bit
mturner5 0:72480818e4a9 1489 for the specified interrupt.
mturner5 0:72480818e4a9 1490
mturner5 0:72480818e4a9 1491 \param [in] IRQn Interrupt number.
mturner5 0:72480818e4a9 1492
mturner5 0:72480818e4a9 1493 \return 0 Interrupt status is not pending.
mturner5 0:72480818e4a9 1494 \return 1 Interrupt status is pending.
mturner5 0:72480818e4a9 1495 */
mturner5 0:72480818e4a9 1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 1497 {
mturner5 0:72480818e4a9 1498 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
mturner5 0:72480818e4a9 1499 }
mturner5 0:72480818e4a9 1500
mturner5 0:72480818e4a9 1501
mturner5 0:72480818e4a9 1502 /** \brief Set Pending Interrupt
mturner5 0:72480818e4a9 1503
mturner5 0:72480818e4a9 1504 The function sets the pending bit of an external interrupt.
mturner5 0:72480818e4a9 1505
mturner5 0:72480818e4a9 1506 \param [in] IRQn Interrupt number. Value cannot be negative.
mturner5 0:72480818e4a9 1507 */
mturner5 0:72480818e4a9 1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 1509 {
mturner5 0:72480818e4a9 1510 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
mturner5 0:72480818e4a9 1511 }
mturner5 0:72480818e4a9 1512
mturner5 0:72480818e4a9 1513
mturner5 0:72480818e4a9 1514 /** \brief Clear Pending Interrupt
mturner5 0:72480818e4a9 1515
mturner5 0:72480818e4a9 1516 The function clears the pending bit of an external interrupt.
mturner5 0:72480818e4a9 1517
mturner5 0:72480818e4a9 1518 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:72480818e4a9 1519 */
mturner5 0:72480818e4a9 1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 1521 {
mturner5 0:72480818e4a9 1522 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mturner5 0:72480818e4a9 1523 }
mturner5 0:72480818e4a9 1524
mturner5 0:72480818e4a9 1525
mturner5 0:72480818e4a9 1526 /** \brief Get Active Interrupt
mturner5 0:72480818e4a9 1527
mturner5 0:72480818e4a9 1528 The function reads the active register in NVIC and returns the active bit.
mturner5 0:72480818e4a9 1529
mturner5 0:72480818e4a9 1530 \param [in] IRQn Interrupt number.
mturner5 0:72480818e4a9 1531
mturner5 0:72480818e4a9 1532 \return 0 Interrupt status is not active.
mturner5 0:72480818e4a9 1533 \return 1 Interrupt status is active.
mturner5 0:72480818e4a9 1534 */
mturner5 0:72480818e4a9 1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
mturner5 0:72480818e4a9 1536 {
mturner5 0:72480818e4a9 1537 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
mturner5 0:72480818e4a9 1538 }
mturner5 0:72480818e4a9 1539
mturner5 0:72480818e4a9 1540
mturner5 0:72480818e4a9 1541 /** \brief Set Interrupt Priority
mturner5 0:72480818e4a9 1542
mturner5 0:72480818e4a9 1543 The function sets the priority of an interrupt.
mturner5 0:72480818e4a9 1544
mturner5 0:72480818e4a9 1545 \note The priority cannot be set for every core interrupt.
mturner5 0:72480818e4a9 1546
mturner5 0:72480818e4a9 1547 \param [in] IRQn Interrupt number.
mturner5 0:72480818e4a9 1548 \param [in] priority Priority to set.
mturner5 0:72480818e4a9 1549 */
mturner5 0:72480818e4a9 1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mturner5 0:72480818e4a9 1551 {
mturner5 0:72480818e4a9 1552 if(IRQn < 0) {
mturner5 0:72480818e4a9 1553 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
mturner5 0:72480818e4a9 1554 else {
mturner5 0:72480818e4a9 1555 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
mturner5 0:72480818e4a9 1556 }
mturner5 0:72480818e4a9 1557
mturner5 0:72480818e4a9 1558
mturner5 0:72480818e4a9 1559 /** \brief Get Interrupt Priority
mturner5 0:72480818e4a9 1560
mturner5 0:72480818e4a9 1561 The function reads the priority of an interrupt. The interrupt
mturner5 0:72480818e4a9 1562 number can be positive to specify an external (device specific)
mturner5 0:72480818e4a9 1563 interrupt, or negative to specify an internal (core) interrupt.
mturner5 0:72480818e4a9 1564
mturner5 0:72480818e4a9 1565
mturner5 0:72480818e4a9 1566 \param [in] IRQn Interrupt number.
mturner5 0:72480818e4a9 1567 \return Interrupt Priority. Value is aligned automatically to the implemented
mturner5 0:72480818e4a9 1568 priority bits of the microcontroller.
mturner5 0:72480818e4a9 1569 */
mturner5 0:72480818e4a9 1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mturner5 0:72480818e4a9 1571 {
mturner5 0:72480818e4a9 1572
mturner5 0:72480818e4a9 1573 if(IRQn < 0) {
mturner5 0:72480818e4a9 1574 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
mturner5 0:72480818e4a9 1575 else {
mturner5 0:72480818e4a9 1576 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mturner5 0:72480818e4a9 1577 }
mturner5 0:72480818e4a9 1578
mturner5 0:72480818e4a9 1579
mturner5 0:72480818e4a9 1580 /** \brief Encode Priority
mturner5 0:72480818e4a9 1581
mturner5 0:72480818e4a9 1582 The function encodes the priority for an interrupt with the given priority group,
mturner5 0:72480818e4a9 1583 preemptive priority value, and subpriority value.
mturner5 0:72480818e4a9 1584 In case of a conflict between priority grouping and available
mturner5 0:72480818e4a9 1585 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
mturner5 0:72480818e4a9 1586
mturner5 0:72480818e4a9 1587 \param [in] PriorityGroup Used priority group.
mturner5 0:72480818e4a9 1588 \param [in] PreemptPriority Preemptive priority value (starting from 0).
mturner5 0:72480818e4a9 1589 \param [in] SubPriority Subpriority value (starting from 0).
mturner5 0:72480818e4a9 1590 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mturner5 0:72480818e4a9 1591 */
mturner5 0:72480818e4a9 1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mturner5 0:72480818e4a9 1593 {
mturner5 0:72480818e4a9 1594 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
mturner5 0:72480818e4a9 1595 uint32_t PreemptPriorityBits;
mturner5 0:72480818e4a9 1596 uint32_t SubPriorityBits;
mturner5 0:72480818e4a9 1597
mturner5 0:72480818e4a9 1598 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
mturner5 0:72480818e4a9 1599 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
mturner5 0:72480818e4a9 1600
mturner5 0:72480818e4a9 1601 return (
mturner5 0:72480818e4a9 1602 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
mturner5 0:72480818e4a9 1603 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
mturner5 0:72480818e4a9 1604 );
mturner5 0:72480818e4a9 1605 }
mturner5 0:72480818e4a9 1606
mturner5 0:72480818e4a9 1607
mturner5 0:72480818e4a9 1608 /** \brief Decode Priority
mturner5 0:72480818e4a9 1609
mturner5 0:72480818e4a9 1610 The function decodes an interrupt priority value with a given priority group to
mturner5 0:72480818e4a9 1611 preemptive priority value and subpriority value.
mturner5 0:72480818e4a9 1612 In case of a conflict between priority grouping and available
mturner5 0:72480818e4a9 1613 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
mturner5 0:72480818e4a9 1614
mturner5 0:72480818e4a9 1615 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mturner5 0:72480818e4a9 1616 \param [in] PriorityGroup Used priority group.
mturner5 0:72480818e4a9 1617 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
mturner5 0:72480818e4a9 1618 \param [out] pSubPriority Subpriority value (starting from 0).
mturner5 0:72480818e4a9 1619 */
mturner5 0:72480818e4a9 1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
mturner5 0:72480818e4a9 1621 {
mturner5 0:72480818e4a9 1622 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
mturner5 0:72480818e4a9 1623 uint32_t PreemptPriorityBits;
mturner5 0:72480818e4a9 1624 uint32_t SubPriorityBits;
mturner5 0:72480818e4a9 1625
mturner5 0:72480818e4a9 1626 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
mturner5 0:72480818e4a9 1627 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
mturner5 0:72480818e4a9 1628
mturner5 0:72480818e4a9 1629 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
mturner5 0:72480818e4a9 1630 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
mturner5 0:72480818e4a9 1631 }
mturner5 0:72480818e4a9 1632
mturner5 0:72480818e4a9 1633
mturner5 0:72480818e4a9 1634 /** \brief System Reset
mturner5 0:72480818e4a9 1635
mturner5 0:72480818e4a9 1636 The function initiates a system reset request to reset the MCU.
mturner5 0:72480818e4a9 1637 */
mturner5 0:72480818e4a9 1638 __STATIC_INLINE void NVIC_SystemReset(void)
mturner5 0:72480818e4a9 1639 {
mturner5 0:72480818e4a9 1640 __DSB(); /* Ensure all outstanding memory accesses included
mturner5 0:72480818e4a9 1641 buffered write are completed before reset */
mturner5 0:72480818e4a9 1642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mturner5 0:72480818e4a9 1643 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
mturner5 0:72480818e4a9 1644 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
mturner5 0:72480818e4a9 1645 __DSB(); /* Ensure completion of memory access */
mturner5 0:72480818e4a9 1646 while(1); /* wait until reset */
mturner5 0:72480818e4a9 1647 }
mturner5 0:72480818e4a9 1648
mturner5 0:72480818e4a9 1649 /*@} end of CMSIS_Core_NVICFunctions */
mturner5 0:72480818e4a9 1650
mturner5 0:72480818e4a9 1651
mturner5 0:72480818e4a9 1652
mturner5 0:72480818e4a9 1653 /* ################################## SysTick function ############################################ */
mturner5 0:72480818e4a9 1654 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:72480818e4a9 1655 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mturner5 0:72480818e4a9 1656 \brief Functions that configure the System.
mturner5 0:72480818e4a9 1657 @{
mturner5 0:72480818e4a9 1658 */
mturner5 0:72480818e4a9 1659
mturner5 0:72480818e4a9 1660 #if (__Vendor_SysTickConfig == 0)
mturner5 0:72480818e4a9 1661
mturner5 0:72480818e4a9 1662 /** \brief System Tick Configuration
mturner5 0:72480818e4a9 1663
mturner5 0:72480818e4a9 1664 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mturner5 0:72480818e4a9 1665 Counter is in free running mode to generate periodic interrupts.
mturner5 0:72480818e4a9 1666
mturner5 0:72480818e4a9 1667 \param [in] ticks Number of ticks between two interrupts.
mturner5 0:72480818e4a9 1668
mturner5 0:72480818e4a9 1669 \return 0 Function succeeded.
mturner5 0:72480818e4a9 1670 \return 1 Function failed.
mturner5 0:72480818e4a9 1671
mturner5 0:72480818e4a9 1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mturner5 0:72480818e4a9 1673 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mturner5 0:72480818e4a9 1674 must contain a vendor-specific implementation of this function.
mturner5 0:72480818e4a9 1675
mturner5 0:72480818e4a9 1676 */
mturner5 0:72480818e4a9 1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mturner5 0:72480818e4a9 1678 {
mturner5 0:72480818e4a9 1679 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mturner5 0:72480818e4a9 1680
mturner5 0:72480818e4a9 1681 SysTick->LOAD = ticks - 1; /* set reload register */
mturner5 0:72480818e4a9 1682 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mturner5 0:72480818e4a9 1683 SysTick->VAL = 0; /* Load the SysTick Counter Value */
mturner5 0:72480818e4a9 1684 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mturner5 0:72480818e4a9 1685 SysTick_CTRL_TICKINT_Msk |
mturner5 0:72480818e4a9 1686 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mturner5 0:72480818e4a9 1687 return (0); /* Function successful */
mturner5 0:72480818e4a9 1688 }
mturner5 0:72480818e4a9 1689
mturner5 0:72480818e4a9 1690 #endif
mturner5 0:72480818e4a9 1691
mturner5 0:72480818e4a9 1692 /*@} end of CMSIS_Core_SysTickFunctions */
mturner5 0:72480818e4a9 1693
mturner5 0:72480818e4a9 1694
mturner5 0:72480818e4a9 1695
mturner5 0:72480818e4a9 1696 /* ##################################### Debug In/Output function ########################################### */
mturner5 0:72480818e4a9 1697 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:72480818e4a9 1698 \defgroup CMSIS_core_DebugFunctions ITM Functions
mturner5 0:72480818e4a9 1699 \brief Functions that access the ITM debug interface.
mturner5 0:72480818e4a9 1700 @{
mturner5 0:72480818e4a9 1701 */
mturner5 0:72480818e4a9 1702
mturner5 0:72480818e4a9 1703 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
mturner5 0:72480818e4a9 1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
mturner5 0:72480818e4a9 1705
mturner5 0:72480818e4a9 1706
mturner5 0:72480818e4a9 1707 /** \brief ITM Send Character
mturner5 0:72480818e4a9 1708
mturner5 0:72480818e4a9 1709 The function transmits a character via the ITM channel 0, and
mturner5 0:72480818e4a9 1710 \li Just returns when no debugger is connected that has booked the output.
mturner5 0:72480818e4a9 1711 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mturner5 0:72480818e4a9 1712
mturner5 0:72480818e4a9 1713 \param [in] ch Character to transmit.
mturner5 0:72480818e4a9 1714
mturner5 0:72480818e4a9 1715 \returns Character to transmit.
mturner5 0:72480818e4a9 1716 */
mturner5 0:72480818e4a9 1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mturner5 0:72480818e4a9 1718 {
mturner5 0:72480818e4a9 1719 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
mturner5 0:72480818e4a9 1720 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
mturner5 0:72480818e4a9 1721 {
mturner5 0:72480818e4a9 1722 while (ITM->PORT[0].u32 == 0);
mturner5 0:72480818e4a9 1723 ITM->PORT[0].u8 = (uint8_t) ch;
mturner5 0:72480818e4a9 1724 }
mturner5 0:72480818e4a9 1725 return (ch);
mturner5 0:72480818e4a9 1726 }
mturner5 0:72480818e4a9 1727
mturner5 0:72480818e4a9 1728
mturner5 0:72480818e4a9 1729 /** \brief ITM Receive Character
mturner5 0:72480818e4a9 1730
mturner5 0:72480818e4a9 1731 The function inputs a character via the external variable \ref ITM_RxBuffer.
mturner5 0:72480818e4a9 1732
mturner5 0:72480818e4a9 1733 \return Received character.
mturner5 0:72480818e4a9 1734 \return -1 No character pending.
mturner5 0:72480818e4a9 1735 */
mturner5 0:72480818e4a9 1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
mturner5 0:72480818e4a9 1737 int32_t ch = -1; /* no character available */
mturner5 0:72480818e4a9 1738
mturner5 0:72480818e4a9 1739 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
mturner5 0:72480818e4a9 1740 ch = ITM_RxBuffer;
mturner5 0:72480818e4a9 1741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mturner5 0:72480818e4a9 1742 }
mturner5 0:72480818e4a9 1743
mturner5 0:72480818e4a9 1744 return (ch);
mturner5 0:72480818e4a9 1745 }
mturner5 0:72480818e4a9 1746
mturner5 0:72480818e4a9 1747
mturner5 0:72480818e4a9 1748 /** \brief ITM Check Character
mturner5 0:72480818e4a9 1749
mturner5 0:72480818e4a9 1750 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mturner5 0:72480818e4a9 1751
mturner5 0:72480818e4a9 1752 \return 0 No character available.
mturner5 0:72480818e4a9 1753 \return 1 Character available.
mturner5 0:72480818e4a9 1754 */
mturner5 0:72480818e4a9 1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
mturner5 0:72480818e4a9 1756
mturner5 0:72480818e4a9 1757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
mturner5 0:72480818e4a9 1758 return (0); /* no character available */
mturner5 0:72480818e4a9 1759 } else {
mturner5 0:72480818e4a9 1760 return (1); /* character available */
mturner5 0:72480818e4a9 1761 }
mturner5 0:72480818e4a9 1762 }
mturner5 0:72480818e4a9 1763
mturner5 0:72480818e4a9 1764 /*@} end of CMSIS_core_DebugFunctions */
mturner5 0:72480818e4a9 1765
mturner5 0:72480818e4a9 1766 #endif /* __CORE_CM4_H_DEPENDANT */
mturner5 0:72480818e4a9 1767
mturner5 0:72480818e4a9 1768 #endif /* __CMSIS_GENERIC */
mturner5 0:72480818e4a9 1769
mturner5 0:72480818e4a9 1770 #ifdef __cplusplus
mturner5 0:72480818e4a9 1771 }
mturner5 0:72480818e4a9 1772 #endif