Mark Turner / MarksMbed

This is a repository for all my programs or modified programs.

TARGET_KL46Z/core_cm0plus.h@0:72480818e4a9, 2016-09-11 (annotated)

Committer:
mturner5
Date:
Sun Sep 11 23:48:09 2016 +0000
Revision:
0:72480818e4a9
Made delays for the LEDS and button presses

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:72480818e4a9 1 /**************************************************************************//**
mturner5 0:72480818e4a9 2 * @file core_cm0plus.h
mturner5 0:72480818e4a9 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
mturner5 0:72480818e4a9 4 * @version V3.20
mturner5 0:72480818e4a9 5 * @date 25. February 2013
mturner5 0:72480818e4a9 6 *
mturner5 0:72480818e4a9 7 * @note
mturner5 0:72480818e4a9 8 *
mturner5 0:72480818e4a9 9 ******************************************************************************/
mturner5 0:72480818e4a9 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mturner5 0:72480818e4a9 11
mturner5 0:72480818e4a9 12 All rights reserved.
mturner5 0:72480818e4a9 13 Redistribution and use in source and binary forms, with or without
mturner5 0:72480818e4a9 14 modification, are permitted provided that the following conditions are met:
mturner5 0:72480818e4a9 15 - Redistributions of source code must retain the above copyright
mturner5 0:72480818e4a9 16 notice, this list of conditions and the following disclaimer.
mturner5 0:72480818e4a9 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:72480818e4a9 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:72480818e4a9 19 documentation and/or other materials provided with the distribution.
mturner5 0:72480818e4a9 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:72480818e4a9 21 to endorse or promote products derived from this software without
mturner5 0:72480818e4a9 22 specific prior written permission.
mturner5 0:72480818e4a9 23 *
mturner5 0:72480818e4a9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:72480818e4a9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:72480818e4a9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:72480818e4a9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:72480818e4a9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:72480818e4a9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:72480818e4a9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:72480818e4a9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:72480818e4a9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:72480818e4a9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:72480818e4a9 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:72480818e4a9 35 ---------------------------------------------------------------------------*/
mturner5 0:72480818e4a9 36
mturner5 0:72480818e4a9 37
mturner5 0:72480818e4a9 38 #if defined ( __ICCARM__ )
mturner5 0:72480818e4a9 39 #pragma system_include /* treat file as system include file for MISRA check */
mturner5 0:72480818e4a9 40 #endif
mturner5 0:72480818e4a9 41
mturner5 0:72480818e4a9 42 #ifdef __cplusplus
mturner5 0:72480818e4a9 43 extern "C" {
mturner5 0:72480818e4a9 44 #endif
mturner5 0:72480818e4a9 45
mturner5 0:72480818e4a9 46 #ifndef __CORE_CM0PLUS_H_GENERIC
mturner5 0:72480818e4a9 47 #define __CORE_CM0PLUS_H_GENERIC
mturner5 0:72480818e4a9 48
mturner5 0:72480818e4a9 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mturner5 0:72480818e4a9 50 CMSIS violates the following MISRA-C:2004 rules:
mturner5 0:72480818e4a9 51
mturner5 0:72480818e4a9 52 \li Required Rule 8.5, object/function definition in header file.<br>
mturner5 0:72480818e4a9 53 Function definitions in header files are used to allow 'inlining'.
mturner5 0:72480818e4a9 54
mturner5 0:72480818e4a9 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mturner5 0:72480818e4a9 56 Unions are used for effective representation of core registers.
mturner5 0:72480818e4a9 57
mturner5 0:72480818e4a9 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mturner5 0:72480818e4a9 59 Function-like macros are used to allow more efficient code.
mturner5 0:72480818e4a9 60 */
mturner5 0:72480818e4a9 61
mturner5 0:72480818e4a9 62
mturner5 0:72480818e4a9 63 /*******************************************************************************
mturner5 0:72480818e4a9 64 * CMSIS definitions
mturner5 0:72480818e4a9 65 ******************************************************************************/
mturner5 0:72480818e4a9 66 /** \ingroup Cortex-M0+
mturner5 0:72480818e4a9 67 @{
mturner5 0:72480818e4a9 68 */
mturner5 0:72480818e4a9 69
mturner5 0:72480818e4a9 70 /* CMSIS CM0P definitions */
mturner5 0:72480818e4a9 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mturner5 0:72480818e4a9 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
mturner5 0:72480818e4a9 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
mturner5 0:72480818e4a9 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
mturner5 0:72480818e4a9 75
mturner5 0:72480818e4a9 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
mturner5 0:72480818e4a9 77
mturner5 0:72480818e4a9 78
mturner5 0:72480818e4a9 79 #if defined ( __CC_ARM )
mturner5 0:72480818e4a9 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mturner5 0:72480818e4a9 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mturner5 0:72480818e4a9 82 #define __STATIC_INLINE static __inline
mturner5 0:72480818e4a9 83
mturner5 0:72480818e4a9 84 #elif defined ( __ICCARM__ )
mturner5 0:72480818e4a9 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mturner5 0:72480818e4a9 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mturner5 0:72480818e4a9 87 #define __STATIC_INLINE static inline
mturner5 0:72480818e4a9 88
mturner5 0:72480818e4a9 89 #elif defined ( __GNUC__ )
mturner5 0:72480818e4a9 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mturner5 0:72480818e4a9 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mturner5 0:72480818e4a9 92 #define __STATIC_INLINE static inline
mturner5 0:72480818e4a9 93
mturner5 0:72480818e4a9 94 #elif defined ( __TASKING__ )
mturner5 0:72480818e4a9 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mturner5 0:72480818e4a9 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mturner5 0:72480818e4a9 97 #define __STATIC_INLINE static inline
mturner5 0:72480818e4a9 98
mturner5 0:72480818e4a9 99 #endif
mturner5 0:72480818e4a9 100
mturner5 0:72480818e4a9 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
mturner5 0:72480818e4a9 102 */
mturner5 0:72480818e4a9 103 #define __FPU_USED 0
mturner5 0:72480818e4a9 104
mturner5 0:72480818e4a9 105 #if defined ( __CC_ARM )
mturner5 0:72480818e4a9 106 #if defined __TARGET_FPU_VFP
mturner5 0:72480818e4a9 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 108 #endif
mturner5 0:72480818e4a9 109
mturner5 0:72480818e4a9 110 #elif defined ( __ICCARM__ )
mturner5 0:72480818e4a9 111 #if defined __ARMVFP__
mturner5 0:72480818e4a9 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 113 #endif
mturner5 0:72480818e4a9 114
mturner5 0:72480818e4a9 115 #elif defined ( __GNUC__ )
mturner5 0:72480818e4a9 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mturner5 0:72480818e4a9 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 118 #endif
mturner5 0:72480818e4a9 119
mturner5 0:72480818e4a9 120 #elif defined ( __TASKING__ )
mturner5 0:72480818e4a9 121 #if defined __FPU_VFP__
mturner5 0:72480818e4a9 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:72480818e4a9 123 #endif
mturner5 0:72480818e4a9 124 #endif
mturner5 0:72480818e4a9 125
mturner5 0:72480818e4a9 126 #include <stdint.h> /* standard types definitions */
mturner5 0:72480818e4a9 127 #include <core_cmInstr.h> /* Core Instruction Access */
mturner5 0:72480818e4a9 128 #include <core_cmFunc.h> /* Core Function Access */
mturner5 0:72480818e4a9 129
mturner5 0:72480818e4a9 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
mturner5 0:72480818e4a9 131
mturner5 0:72480818e4a9 132 #ifndef __CMSIS_GENERIC
mturner5 0:72480818e4a9 133
mturner5 0:72480818e4a9 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
mturner5 0:72480818e4a9 135 #define __CORE_CM0PLUS_H_DEPENDANT
mturner5 0:72480818e4a9 136
mturner5 0:72480818e4a9 137 /* check device defines and use defaults */
mturner5 0:72480818e4a9 138 #if defined __CHECK_DEVICE_DEFINES
mturner5 0:72480818e4a9 139 #ifndef __CM0PLUS_REV
mturner5 0:72480818e4a9 140 #define __CM0PLUS_REV 0x0000
mturner5 0:72480818e4a9 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
mturner5 0:72480818e4a9 142 #endif
mturner5 0:72480818e4a9 143
mturner5 0:72480818e4a9 144 #ifndef __MPU_PRESENT
mturner5 0:72480818e4a9 145 #define __MPU_PRESENT 0
mturner5 0:72480818e4a9 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
mturner5 0:72480818e4a9 147 #endif
mturner5 0:72480818e4a9 148
mturner5 0:72480818e4a9 149 #ifndef __VTOR_PRESENT
mturner5 0:72480818e4a9 150 #define __VTOR_PRESENT 0
mturner5 0:72480818e4a9 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
mturner5 0:72480818e4a9 152 #endif
mturner5 0:72480818e4a9 153
mturner5 0:72480818e4a9 154 #ifndef __NVIC_PRIO_BITS
mturner5 0:72480818e4a9 155 #define __NVIC_PRIO_BITS 2
mturner5 0:72480818e4a9 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mturner5 0:72480818e4a9 157 #endif
mturner5 0:72480818e4a9 158
mturner5 0:72480818e4a9 159 #ifndef __Vendor_SysTickConfig
mturner5 0:72480818e4a9 160 #define __Vendor_SysTickConfig 0
mturner5 0:72480818e4a9 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mturner5 0:72480818e4a9 162 #endif
mturner5 0:72480818e4a9 163 #endif
mturner5 0:72480818e4a9 164
mturner5 0:72480818e4a9 165 /* IO definitions (access restrictions to peripheral registers) */
mturner5 0:72480818e4a9 166 /**
mturner5 0:72480818e4a9 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
mturner5 0:72480818e4a9 168
mturner5 0:72480818e4a9 169 <strong>IO Type Qualifiers</strong> are used
mturner5 0:72480818e4a9 170 \li to specify the access to peripheral variables.
mturner5 0:72480818e4a9 171 \li for automatic generation of peripheral register debug information.
mturner5 0:72480818e4a9 172 */
mturner5 0:72480818e4a9 173 #ifdef __cplusplus
mturner5 0:72480818e4a9 174 #define __I volatile /*!< Defines 'read only' permissions */
mturner5 0:72480818e4a9 175 #else
mturner5 0:72480818e4a9 176 #define __I volatile const /*!< Defines 'read only' permissions */
mturner5 0:72480818e4a9 177 #endif
mturner5 0:72480818e4a9 178 #define __O volatile /*!< Defines 'write only' permissions */
mturner5 0:72480818e4a9 179 #define __IO volatile /*!< Defines 'read / write' permissions */
mturner5 0:72480818e4a9 180
mturner5 0:72480818e4a9 181 /*@} end of group Cortex-M0+ */
mturner5 0:72480818e4a9 182
mturner5 0:72480818e4a9 183
mturner5 0:72480818e4a9 184
mturner5 0:72480818e4a9 185 /*******************************************************************************
mturner5 0:72480818e4a9 186 * Register Abstraction
mturner5 0:72480818e4a9 187 Core Register contain:
mturner5 0:72480818e4a9 188 - Core Register
mturner5 0:72480818e4a9 189 - Core NVIC Register
mturner5 0:72480818e4a9 190 - Core SCB Register
mturner5 0:72480818e4a9 191 - Core SysTick Register
mturner5 0:72480818e4a9 192 - Core MPU Register
mturner5 0:72480818e4a9 193 ******************************************************************************/
mturner5 0:72480818e4a9 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
mturner5 0:72480818e4a9 195 \brief Type definitions and defines for Cortex-M processor based devices.
mturner5 0:72480818e4a9 196 */
mturner5 0:72480818e4a9 197
mturner5 0:72480818e4a9 198 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 199 \defgroup CMSIS_CORE Status and Control Registers
mturner5 0:72480818e4a9 200 \brief Core Register type definitions.
mturner5 0:72480818e4a9 201 @{
mturner5 0:72480818e4a9 202 */
mturner5 0:72480818e4a9 203
mturner5 0:72480818e4a9 204 /** \brief Union type to access the Application Program Status Register (APSR).
mturner5 0:72480818e4a9 205 */
mturner5 0:72480818e4a9 206 typedef union
mturner5 0:72480818e4a9 207 {
mturner5 0:72480818e4a9 208 struct
mturner5 0:72480818e4a9 209 {
mturner5 0:72480818e4a9 210 #if (__CORTEX_M != 0x04)
mturner5 0:72480818e4a9 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mturner5 0:72480818e4a9 212 #else
mturner5 0:72480818e4a9 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mturner5 0:72480818e4a9 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mturner5 0:72480818e4a9 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mturner5 0:72480818e4a9 216 #endif
mturner5 0:72480818e4a9 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mturner5 0:72480818e4a9 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mturner5 0:72480818e4a9 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mturner5 0:72480818e4a9 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mturner5 0:72480818e4a9 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mturner5 0:72480818e4a9 222 } b; /*!< Structure used for bit access */
mturner5 0:72480818e4a9 223 uint32_t w; /*!< Type used for word access */
mturner5 0:72480818e4a9 224 } APSR_Type;
mturner5 0:72480818e4a9 225
mturner5 0:72480818e4a9 226
mturner5 0:72480818e4a9 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mturner5 0:72480818e4a9 228 */
mturner5 0:72480818e4a9 229 typedef union
mturner5 0:72480818e4a9 230 {
mturner5 0:72480818e4a9 231 struct
mturner5 0:72480818e4a9 232 {
mturner5 0:72480818e4a9 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mturner5 0:72480818e4a9 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mturner5 0:72480818e4a9 235 } b; /*!< Structure used for bit access */
mturner5 0:72480818e4a9 236 uint32_t w; /*!< Type used for word access */
mturner5 0:72480818e4a9 237 } IPSR_Type;
mturner5 0:72480818e4a9 238
mturner5 0:72480818e4a9 239
mturner5 0:72480818e4a9 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mturner5 0:72480818e4a9 241 */
mturner5 0:72480818e4a9 242 typedef union
mturner5 0:72480818e4a9 243 {
mturner5 0:72480818e4a9 244 struct
mturner5 0:72480818e4a9 245 {
mturner5 0:72480818e4a9 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mturner5 0:72480818e4a9 247 #if (__CORTEX_M != 0x04)
mturner5 0:72480818e4a9 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mturner5 0:72480818e4a9 249 #else
mturner5 0:72480818e4a9 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mturner5 0:72480818e4a9 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mturner5 0:72480818e4a9 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mturner5 0:72480818e4a9 253 #endif
mturner5 0:72480818e4a9 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mturner5 0:72480818e4a9 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mturner5 0:72480818e4a9 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mturner5 0:72480818e4a9 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mturner5 0:72480818e4a9 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mturner5 0:72480818e4a9 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mturner5 0:72480818e4a9 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mturner5 0:72480818e4a9 261 } b; /*!< Structure used for bit access */
mturner5 0:72480818e4a9 262 uint32_t w; /*!< Type used for word access */
mturner5 0:72480818e4a9 263 } xPSR_Type;
mturner5 0:72480818e4a9 264
mturner5 0:72480818e4a9 265
mturner5 0:72480818e4a9 266 /** \brief Union type to access the Control Registers (CONTROL).
mturner5 0:72480818e4a9 267 */
mturner5 0:72480818e4a9 268 typedef union
mturner5 0:72480818e4a9 269 {
mturner5 0:72480818e4a9 270 struct
mturner5 0:72480818e4a9 271 {
mturner5 0:72480818e4a9 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mturner5 0:72480818e4a9 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mturner5 0:72480818e4a9 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mturner5 0:72480818e4a9 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mturner5 0:72480818e4a9 276 } b; /*!< Structure used for bit access */
mturner5 0:72480818e4a9 277 uint32_t w; /*!< Type used for word access */
mturner5 0:72480818e4a9 278 } CONTROL_Type;
mturner5 0:72480818e4a9 279
mturner5 0:72480818e4a9 280 /*@} end of group CMSIS_CORE */
mturner5 0:72480818e4a9 281
mturner5 0:72480818e4a9 282
mturner5 0:72480818e4a9 283 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mturner5 0:72480818e4a9 285 \brief Type definitions for the NVIC Registers
mturner5 0:72480818e4a9 286 @{
mturner5 0:72480818e4a9 287 */
mturner5 0:72480818e4a9 288
mturner5 0:72480818e4a9 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mturner5 0:72480818e4a9 290 */
mturner5 0:72480818e4a9 291 typedef struct
mturner5 0:72480818e4a9 292 {
mturner5 0:72480818e4a9 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mturner5 0:72480818e4a9 294 uint32_t RESERVED0[31];
mturner5 0:72480818e4a9 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mturner5 0:72480818e4a9 296 uint32_t RSERVED1[31];
mturner5 0:72480818e4a9 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mturner5 0:72480818e4a9 298 uint32_t RESERVED2[31];
mturner5 0:72480818e4a9 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mturner5 0:72480818e4a9 300 uint32_t RESERVED3[31];
mturner5 0:72480818e4a9 301 uint32_t RESERVED4[64];
mturner5 0:72480818e4a9 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mturner5 0:72480818e4a9 303 } NVIC_Type;
mturner5 0:72480818e4a9 304
mturner5 0:72480818e4a9 305 /*@} end of group CMSIS_NVIC */
mturner5 0:72480818e4a9 306
mturner5 0:72480818e4a9 307
mturner5 0:72480818e4a9 308 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 309 \defgroup CMSIS_SCB System Control Block (SCB)
mturner5 0:72480818e4a9 310 \brief Type definitions for the System Control Block Registers
mturner5 0:72480818e4a9 311 @{
mturner5 0:72480818e4a9 312 */
mturner5 0:72480818e4a9 313
mturner5 0:72480818e4a9 314 /** \brief Structure type to access the System Control Block (SCB).
mturner5 0:72480818e4a9 315 */
mturner5 0:72480818e4a9 316 typedef struct
mturner5 0:72480818e4a9 317 {
mturner5 0:72480818e4a9 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mturner5 0:72480818e4a9 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mturner5 0:72480818e4a9 320 #if (__VTOR_PRESENT == 1)
mturner5 0:72480818e4a9 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mturner5 0:72480818e4a9 322 #else
mturner5 0:72480818e4a9 323 uint32_t RESERVED0;
mturner5 0:72480818e4a9 324 #endif
mturner5 0:72480818e4a9 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mturner5 0:72480818e4a9 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mturner5 0:72480818e4a9 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mturner5 0:72480818e4a9 328 uint32_t RESERVED1;
mturner5 0:72480818e4a9 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mturner5 0:72480818e4a9 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mturner5 0:72480818e4a9 331 } SCB_Type;
mturner5 0:72480818e4a9 332
mturner5 0:72480818e4a9 333 /* SCB CPUID Register Definitions */
mturner5 0:72480818e4a9 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mturner5 0:72480818e4a9 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mturner5 0:72480818e4a9 336
mturner5 0:72480818e4a9 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mturner5 0:72480818e4a9 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mturner5 0:72480818e4a9 339
mturner5 0:72480818e4a9 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mturner5 0:72480818e4a9 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mturner5 0:72480818e4a9 342
mturner5 0:72480818e4a9 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mturner5 0:72480818e4a9 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mturner5 0:72480818e4a9 345
mturner5 0:72480818e4a9 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mturner5 0:72480818e4a9 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
mturner5 0:72480818e4a9 348
mturner5 0:72480818e4a9 349 /* SCB Interrupt Control State Register Definitions */
mturner5 0:72480818e4a9 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mturner5 0:72480818e4a9 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mturner5 0:72480818e4a9 352
mturner5 0:72480818e4a9 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mturner5 0:72480818e4a9 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mturner5 0:72480818e4a9 355
mturner5 0:72480818e4a9 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mturner5 0:72480818e4a9 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mturner5 0:72480818e4a9 358
mturner5 0:72480818e4a9 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mturner5 0:72480818e4a9 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mturner5 0:72480818e4a9 361
mturner5 0:72480818e4a9 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mturner5 0:72480818e4a9 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mturner5 0:72480818e4a9 364
mturner5 0:72480818e4a9 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mturner5 0:72480818e4a9 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mturner5 0:72480818e4a9 367
mturner5 0:72480818e4a9 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mturner5 0:72480818e4a9 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mturner5 0:72480818e4a9 370
mturner5 0:72480818e4a9 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mturner5 0:72480818e4a9 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mturner5 0:72480818e4a9 373
mturner5 0:72480818e4a9 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mturner5 0:72480818e4a9 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
mturner5 0:72480818e4a9 376
mturner5 0:72480818e4a9 377 #if (__VTOR_PRESENT == 1)
mturner5 0:72480818e4a9 378 /* SCB Interrupt Control State Register Definitions */
mturner5 0:72480818e4a9 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
mturner5 0:72480818e4a9 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mturner5 0:72480818e4a9 381 #endif
mturner5 0:72480818e4a9 382
mturner5 0:72480818e4a9 383 /* SCB Application Interrupt and Reset Control Register Definitions */
mturner5 0:72480818e4a9 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mturner5 0:72480818e4a9 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mturner5 0:72480818e4a9 386
mturner5 0:72480818e4a9 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mturner5 0:72480818e4a9 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mturner5 0:72480818e4a9 389
mturner5 0:72480818e4a9 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mturner5 0:72480818e4a9 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mturner5 0:72480818e4a9 392
mturner5 0:72480818e4a9 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mturner5 0:72480818e4a9 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mturner5 0:72480818e4a9 395
mturner5 0:72480818e4a9 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mturner5 0:72480818e4a9 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mturner5 0:72480818e4a9 398
mturner5 0:72480818e4a9 399 /* SCB System Control Register Definitions */
mturner5 0:72480818e4a9 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mturner5 0:72480818e4a9 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mturner5 0:72480818e4a9 402
mturner5 0:72480818e4a9 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mturner5 0:72480818e4a9 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mturner5 0:72480818e4a9 405
mturner5 0:72480818e4a9 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mturner5 0:72480818e4a9 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mturner5 0:72480818e4a9 408
mturner5 0:72480818e4a9 409 /* SCB Configuration Control Register Definitions */
mturner5 0:72480818e4a9 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mturner5 0:72480818e4a9 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mturner5 0:72480818e4a9 412
mturner5 0:72480818e4a9 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mturner5 0:72480818e4a9 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mturner5 0:72480818e4a9 415
mturner5 0:72480818e4a9 416 /* SCB System Handler Control and State Register Definitions */
mturner5 0:72480818e4a9 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mturner5 0:72480818e4a9 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mturner5 0:72480818e4a9 419
mturner5 0:72480818e4a9 420 /*@} end of group CMSIS_SCB */
mturner5 0:72480818e4a9 421
mturner5 0:72480818e4a9 422
mturner5 0:72480818e4a9 423 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mturner5 0:72480818e4a9 425 \brief Type definitions for the System Timer Registers.
mturner5 0:72480818e4a9 426 @{
mturner5 0:72480818e4a9 427 */
mturner5 0:72480818e4a9 428
mturner5 0:72480818e4a9 429 /** \brief Structure type to access the System Timer (SysTick).
mturner5 0:72480818e4a9 430 */
mturner5 0:72480818e4a9 431 typedef struct
mturner5 0:72480818e4a9 432 {
mturner5 0:72480818e4a9 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mturner5 0:72480818e4a9 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mturner5 0:72480818e4a9 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mturner5 0:72480818e4a9 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mturner5 0:72480818e4a9 437 } SysTick_Type;
mturner5 0:72480818e4a9 438
mturner5 0:72480818e4a9 439 /* SysTick Control / Status Register Definitions */
mturner5 0:72480818e4a9 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mturner5 0:72480818e4a9 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mturner5 0:72480818e4a9 442
mturner5 0:72480818e4a9 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mturner5 0:72480818e4a9 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mturner5 0:72480818e4a9 445
mturner5 0:72480818e4a9 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mturner5 0:72480818e4a9 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mturner5 0:72480818e4a9 448
mturner5 0:72480818e4a9 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mturner5 0:72480818e4a9 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
mturner5 0:72480818e4a9 451
mturner5 0:72480818e4a9 452 /* SysTick Reload Register Definitions */
mturner5 0:72480818e4a9 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mturner5 0:72480818e4a9 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
mturner5 0:72480818e4a9 455
mturner5 0:72480818e4a9 456 /* SysTick Current Register Definitions */
mturner5 0:72480818e4a9 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mturner5 0:72480818e4a9 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
mturner5 0:72480818e4a9 459
mturner5 0:72480818e4a9 460 /* SysTick Calibration Register Definitions */
mturner5 0:72480818e4a9 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mturner5 0:72480818e4a9 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mturner5 0:72480818e4a9 463
mturner5 0:72480818e4a9 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mturner5 0:72480818e4a9 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mturner5 0:72480818e4a9 466
mturner5 0:72480818e4a9 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mturner5 0:72480818e4a9 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
mturner5 0:72480818e4a9 469
mturner5 0:72480818e4a9 470 /*@} end of group CMSIS_SysTick */
mturner5 0:72480818e4a9 471
mturner5 0:72480818e4a9 472 #if (__MPU_PRESENT == 1)
mturner5 0:72480818e4a9 473 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mturner5 0:72480818e4a9 475 \brief Type definitions for the Memory Protection Unit (MPU)
mturner5 0:72480818e4a9 476 @{
mturner5 0:72480818e4a9 477 */
mturner5 0:72480818e4a9 478
mturner5 0:72480818e4a9 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
mturner5 0:72480818e4a9 480 */
mturner5 0:72480818e4a9 481 typedef struct
mturner5 0:72480818e4a9 482 {
mturner5 0:72480818e4a9 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mturner5 0:72480818e4a9 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mturner5 0:72480818e4a9 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mturner5 0:72480818e4a9 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mturner5 0:72480818e4a9 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mturner5 0:72480818e4a9 488 } MPU_Type;
mturner5 0:72480818e4a9 489
mturner5 0:72480818e4a9 490 /* MPU Type Register */
mturner5 0:72480818e4a9 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mturner5 0:72480818e4a9 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mturner5 0:72480818e4a9 493
mturner5 0:72480818e4a9 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mturner5 0:72480818e4a9 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mturner5 0:72480818e4a9 496
mturner5 0:72480818e4a9 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mturner5 0:72480818e4a9 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
mturner5 0:72480818e4a9 499
mturner5 0:72480818e4a9 500 /* MPU Control Register */
mturner5 0:72480818e4a9 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mturner5 0:72480818e4a9 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mturner5 0:72480818e4a9 503
mturner5 0:72480818e4a9 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mturner5 0:72480818e4a9 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mturner5 0:72480818e4a9 506
mturner5 0:72480818e4a9 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mturner5 0:72480818e4a9 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
mturner5 0:72480818e4a9 509
mturner5 0:72480818e4a9 510 /* MPU Region Number Register */
mturner5 0:72480818e4a9 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mturner5 0:72480818e4a9 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
mturner5 0:72480818e4a9 513
mturner5 0:72480818e4a9 514 /* MPU Region Base Address Register */
mturner5 0:72480818e4a9 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
mturner5 0:72480818e4a9 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mturner5 0:72480818e4a9 517
mturner5 0:72480818e4a9 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mturner5 0:72480818e4a9 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mturner5 0:72480818e4a9 520
mturner5 0:72480818e4a9 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mturner5 0:72480818e4a9 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
mturner5 0:72480818e4a9 523
mturner5 0:72480818e4a9 524 /* MPU Region Attribute and Size Register */
mturner5 0:72480818e4a9 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mturner5 0:72480818e4a9 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mturner5 0:72480818e4a9 527
mturner5 0:72480818e4a9 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mturner5 0:72480818e4a9 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mturner5 0:72480818e4a9 530
mturner5 0:72480818e4a9 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mturner5 0:72480818e4a9 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mturner5 0:72480818e4a9 533
mturner5 0:72480818e4a9 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mturner5 0:72480818e4a9 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mturner5 0:72480818e4a9 536
mturner5 0:72480818e4a9 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mturner5 0:72480818e4a9 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mturner5 0:72480818e4a9 539
mturner5 0:72480818e4a9 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mturner5 0:72480818e4a9 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mturner5 0:72480818e4a9 542
mturner5 0:72480818e4a9 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mturner5 0:72480818e4a9 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mturner5 0:72480818e4a9 545
mturner5 0:72480818e4a9 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mturner5 0:72480818e4a9 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mturner5 0:72480818e4a9 548
mturner5 0:72480818e4a9 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mturner5 0:72480818e4a9 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mturner5 0:72480818e4a9 551
mturner5 0:72480818e4a9 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mturner5 0:72480818e4a9 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
mturner5 0:72480818e4a9 554
mturner5 0:72480818e4a9 555 /*@} end of group CMSIS_MPU */
mturner5 0:72480818e4a9 556 #endif
mturner5 0:72480818e4a9 557
mturner5 0:72480818e4a9 558
mturner5 0:72480818e4a9 559 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mturner5 0:72480818e4a9 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
mturner5 0:72480818e4a9 562 are only accessible over DAP and not via processor. Therefore
mturner5 0:72480818e4a9 563 they are not covered by the Cortex-M0 header file.
mturner5 0:72480818e4a9 564 @{
mturner5 0:72480818e4a9 565 */
mturner5 0:72480818e4a9 566 /*@} end of group CMSIS_CoreDebug */
mturner5 0:72480818e4a9 567
mturner5 0:72480818e4a9 568
mturner5 0:72480818e4a9 569 /** \ingroup CMSIS_core_register
mturner5 0:72480818e4a9 570 \defgroup CMSIS_core_base Core Definitions
mturner5 0:72480818e4a9 571 \brief Definitions for base addresses, unions, and structures.
mturner5 0:72480818e4a9 572 @{
mturner5 0:72480818e4a9 573 */
mturner5 0:72480818e4a9 574
mturner5 0:72480818e4a9 575 /* Memory mapping of Cortex-M0+ Hardware */
mturner5 0:72480818e4a9 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mturner5 0:72480818e4a9 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mturner5 0:72480818e4a9 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mturner5 0:72480818e4a9 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mturner5 0:72480818e4a9 580
mturner5 0:72480818e4a9 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mturner5 0:72480818e4a9 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mturner5 0:72480818e4a9 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mturner5 0:72480818e4a9 584
mturner5 0:72480818e4a9 585 #if (__MPU_PRESENT == 1)
mturner5 0:72480818e4a9 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mturner5 0:72480818e4a9 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mturner5 0:72480818e4a9 588 #endif
mturner5 0:72480818e4a9 589
mturner5 0:72480818e4a9 590 /*@} */
mturner5 0:72480818e4a9 591
mturner5 0:72480818e4a9 592
mturner5 0:72480818e4a9 593
mturner5 0:72480818e4a9 594 /*******************************************************************************
mturner5 0:72480818e4a9 595 * Hardware Abstraction Layer
mturner5 0:72480818e4a9 596 Core Function Interface contains:
mturner5 0:72480818e4a9 597 - Core NVIC Functions
mturner5 0:72480818e4a9 598 - Core SysTick Functions
mturner5 0:72480818e4a9 599 - Core Register Access Functions
mturner5 0:72480818e4a9 600 ******************************************************************************/
mturner5 0:72480818e4a9 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mturner5 0:72480818e4a9 602 */
mturner5 0:72480818e4a9 603
mturner5 0:72480818e4a9 604
mturner5 0:72480818e4a9 605
mturner5 0:72480818e4a9 606 /* ########################## NVIC functions #################################### */
mturner5 0:72480818e4a9 607 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:72480818e4a9 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mturner5 0:72480818e4a9 609 \brief Functions that manage interrupts and exceptions via the NVIC.
mturner5 0:72480818e4a9 610 @{
mturner5 0:72480818e4a9 611 */
mturner5 0:72480818e4a9 612
mturner5 0:72480818e4a9 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mturner5 0:72480818e4a9 614 /* The following MACROS handle generation of the register offset and byte masks */
mturner5 0:72480818e4a9 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
mturner5 0:72480818e4a9 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
mturner5 0:72480818e4a9 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
mturner5 0:72480818e4a9 618
mturner5 0:72480818e4a9 619
mturner5 0:72480818e4a9 620 /** \brief Enable External Interrupt
mturner5 0:72480818e4a9 621
mturner5 0:72480818e4a9 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
mturner5 0:72480818e4a9 623
mturner5 0:72480818e4a9 624 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:72480818e4a9 625 */
mturner5 0:72480818e4a9 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 627 {
mturner5 0:72480818e4a9 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mturner5 0:72480818e4a9 629 }
mturner5 0:72480818e4a9 630
mturner5 0:72480818e4a9 631
mturner5 0:72480818e4a9 632 /** \brief Disable External Interrupt
mturner5 0:72480818e4a9 633
mturner5 0:72480818e4a9 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
mturner5 0:72480818e4a9 635
mturner5 0:72480818e4a9 636 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:72480818e4a9 637 */
mturner5 0:72480818e4a9 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 639 {
mturner5 0:72480818e4a9 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mturner5 0:72480818e4a9 641 }
mturner5 0:72480818e4a9 642
mturner5 0:72480818e4a9 643
mturner5 0:72480818e4a9 644 /** \brief Get Pending Interrupt
mturner5 0:72480818e4a9 645
mturner5 0:72480818e4a9 646 The function reads the pending register in the NVIC and returns the pending bit
mturner5 0:72480818e4a9 647 for the specified interrupt.
mturner5 0:72480818e4a9 648
mturner5 0:72480818e4a9 649 \param [in] IRQn Interrupt number.
mturner5 0:72480818e4a9 650
mturner5 0:72480818e4a9 651 \return 0 Interrupt status is not pending.
mturner5 0:72480818e4a9 652 \return 1 Interrupt status is pending.
mturner5 0:72480818e4a9 653 */
mturner5 0:72480818e4a9 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 655 {
mturner5 0:72480818e4a9 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
mturner5 0:72480818e4a9 657 }
mturner5 0:72480818e4a9 658
mturner5 0:72480818e4a9 659
mturner5 0:72480818e4a9 660 /** \brief Set Pending Interrupt
mturner5 0:72480818e4a9 661
mturner5 0:72480818e4a9 662 The function sets the pending bit of an external interrupt.
mturner5 0:72480818e4a9 663
mturner5 0:72480818e4a9 664 \param [in] IRQn Interrupt number. Value cannot be negative.
mturner5 0:72480818e4a9 665 */
mturner5 0:72480818e4a9 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 667 {
mturner5 0:72480818e4a9 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mturner5 0:72480818e4a9 669 }
mturner5 0:72480818e4a9 670
mturner5 0:72480818e4a9 671
mturner5 0:72480818e4a9 672 /** \brief Clear Pending Interrupt
mturner5 0:72480818e4a9 673
mturner5 0:72480818e4a9 674 The function clears the pending bit of an external interrupt.
mturner5 0:72480818e4a9 675
mturner5 0:72480818e4a9 676 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:72480818e4a9 677 */
mturner5 0:72480818e4a9 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mturner5 0:72480818e4a9 679 {
mturner5 0:72480818e4a9 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mturner5 0:72480818e4a9 681 }
mturner5 0:72480818e4a9 682
mturner5 0:72480818e4a9 683
mturner5 0:72480818e4a9 684 /** \brief Set Interrupt Priority
mturner5 0:72480818e4a9 685
mturner5 0:72480818e4a9 686 The function sets the priority of an interrupt.
mturner5 0:72480818e4a9 687
mturner5 0:72480818e4a9 688 \note The priority cannot be set for every core interrupt.
mturner5 0:72480818e4a9 689
mturner5 0:72480818e4a9 690 \param [in] IRQn Interrupt number.
mturner5 0:72480818e4a9 691 \param [in] priority Priority to set.
mturner5 0:72480818e4a9 692 */
mturner5 0:72480818e4a9 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mturner5 0:72480818e4a9 694 {
mturner5 0:72480818e4a9 695 if(IRQn < 0) {
mturner5 0:72480818e4a9 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mturner5 0:72480818e4a9 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mturner5 0:72480818e4a9 698 else {
mturner5 0:72480818e4a9 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mturner5 0:72480818e4a9 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mturner5 0:72480818e4a9 701 }
mturner5 0:72480818e4a9 702
mturner5 0:72480818e4a9 703
mturner5 0:72480818e4a9 704 /** \brief Get Interrupt Priority
mturner5 0:72480818e4a9 705
mturner5 0:72480818e4a9 706 The function reads the priority of an interrupt. The interrupt
mturner5 0:72480818e4a9 707 number can be positive to specify an external (device specific)
mturner5 0:72480818e4a9 708 interrupt, or negative to specify an internal (core) interrupt.
mturner5 0:72480818e4a9 709
mturner5 0:72480818e4a9 710
mturner5 0:72480818e4a9 711 \param [in] IRQn Interrupt number.
mturner5 0:72480818e4a9 712 \return Interrupt Priority. Value is aligned automatically to the implemented
mturner5 0:72480818e4a9 713 priority bits of the microcontroller.
mturner5 0:72480818e4a9 714 */
mturner5 0:72480818e4a9 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mturner5 0:72480818e4a9 716 {
mturner5 0:72480818e4a9 717
mturner5 0:72480818e4a9 718 if(IRQn < 0) {
mturner5 0:72480818e4a9 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
mturner5 0:72480818e4a9 720 else {
mturner5 0:72480818e4a9 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mturner5 0:72480818e4a9 722 }
mturner5 0:72480818e4a9 723
mturner5 0:72480818e4a9 724
mturner5 0:72480818e4a9 725 /** \brief System Reset
mturner5 0:72480818e4a9 726
mturner5 0:72480818e4a9 727 The function initiates a system reset request to reset the MCU.
mturner5 0:72480818e4a9 728 */
mturner5 0:72480818e4a9 729 __STATIC_INLINE void NVIC_SystemReset(void)
mturner5 0:72480818e4a9 730 {
mturner5 0:72480818e4a9 731 __DSB(); /* Ensure all outstanding memory accesses included
mturner5 0:72480818e4a9 732 buffered write are completed before reset */
mturner5 0:72480818e4a9 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mturner5 0:72480818e4a9 734 SCB_AIRCR_SYSRESETREQ_Msk);
mturner5 0:72480818e4a9 735 __DSB(); /* Ensure completion of memory access */
mturner5 0:72480818e4a9 736 while(1); /* wait until reset */
mturner5 0:72480818e4a9 737 }
mturner5 0:72480818e4a9 738
mturner5 0:72480818e4a9 739 /*@} end of CMSIS_Core_NVICFunctions */
mturner5 0:72480818e4a9 740
mturner5 0:72480818e4a9 741
mturner5 0:72480818e4a9 742
mturner5 0:72480818e4a9 743 /* ################################## SysTick function ############################################ */
mturner5 0:72480818e4a9 744 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:72480818e4a9 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mturner5 0:72480818e4a9 746 \brief Functions that configure the System.
mturner5 0:72480818e4a9 747 @{
mturner5 0:72480818e4a9 748 */
mturner5 0:72480818e4a9 749
mturner5 0:72480818e4a9 750 #if (__Vendor_SysTickConfig == 0)
mturner5 0:72480818e4a9 751
mturner5 0:72480818e4a9 752 /** \brief System Tick Configuration
mturner5 0:72480818e4a9 753
mturner5 0:72480818e4a9 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mturner5 0:72480818e4a9 755 Counter is in free running mode to generate periodic interrupts.
mturner5 0:72480818e4a9 756
mturner5 0:72480818e4a9 757 \param [in] ticks Number of ticks between two interrupts.
mturner5 0:72480818e4a9 758
mturner5 0:72480818e4a9 759 \return 0 Function succeeded.
mturner5 0:72480818e4a9 760 \return 1 Function failed.
mturner5 0:72480818e4a9 761
mturner5 0:72480818e4a9 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mturner5 0:72480818e4a9 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mturner5 0:72480818e4a9 764 must contain a vendor-specific implementation of this function.
mturner5 0:72480818e4a9 765
mturner5 0:72480818e4a9 766 */
mturner5 0:72480818e4a9 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mturner5 0:72480818e4a9 768 {
mturner5 0:72480818e4a9 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mturner5 0:72480818e4a9 770
mturner5 0:72480818e4a9 771 SysTick->LOAD = ticks - 1; /* set reload register */
mturner5 0:72480818e4a9 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mturner5 0:72480818e4a9 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
mturner5 0:72480818e4a9 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mturner5 0:72480818e4a9 775 SysTick_CTRL_TICKINT_Msk |
mturner5 0:72480818e4a9 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mturner5 0:72480818e4a9 777 return (0); /* Function successful */
mturner5 0:72480818e4a9 778 }
mturner5 0:72480818e4a9 779
mturner5 0:72480818e4a9 780 #endif
mturner5 0:72480818e4a9 781
mturner5 0:72480818e4a9 782 /*@} end of CMSIS_Core_SysTickFunctions */
mturner5 0:72480818e4a9 783
mturner5 0:72480818e4a9 784
mturner5 0:72480818e4a9 785
mturner5 0:72480818e4a9 786
mturner5 0:72480818e4a9 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
mturner5 0:72480818e4a9 788
mturner5 0:72480818e4a9 789 #endif /* __CMSIS_GENERIC */
mturner5 0:72480818e4a9 790
mturner5 0:72480818e4a9 791 #ifdef __cplusplus
mturner5 0:72480818e4a9 792 }
mturner5 0:72480818e4a9 793 #endif