t k / Mbed 2 deprecated MovPlayer

This program plays QuickTime movies on GR-Peach

Dependencies:   AsciiFont GR-PEACH_video GraphicsFramework LCD_shield_config R_BSP TLV320_RBSP mbed-rtos mbed

Requirements

  • GR-Peach
  • GR-Peach Audio Camera Shield or I²S compatible audio DAC
  • GR-Peach LCD Shield
  • USB memory stick

How to play movie files

  • Encode movie files

encode movies with ffmpeg

$ ffmpeg -i <input -ar 44100 -acodec pcm_s16le -s 480x270 -vcodec mjpeg -q:v 3 -movflags faststart -threads 4 -vf fps=30 <output>.mov
  • Copy movies to the root directory of USB memory
  • Build and upload this program
  • Run it

USBHost/USBHost/USBHALHost_RZ_A1.cpp@1:3e638b9e91cd, 2017-03-12 (annotated)

Committer:
mtkrtk
Date:
Sun Mar 12 02:01:46 2017 +0000
Revision:
1:3e638b9e91cd
Parent:
0:d0f130e27d32 
fixed lcd contrast pin

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mtkrtk 0:d0f130e27d32 1 /* mbed USBHost Library
mtkrtk 0:d0f130e27d32 2 * Copyright (c) 2006-2013 ARM Limited
mtkrtk 0:d0f130e27d32 3 *
mtkrtk 0:d0f130e27d32 4 * Licensed under the Apache License, Version 2.0 (the "License");
mtkrtk 0:d0f130e27d32 5 * you may not use this file except in compliance with the License.
mtkrtk 0:d0f130e27d32 6 * You may obtain a copy of the License at
mtkrtk 0:d0f130e27d32 7 *
mtkrtk 0:d0f130e27d32 8 * http://www.apache.org/licenses/LICENSE-2.0
mtkrtk 0:d0f130e27d32 9 *
mtkrtk 0:d0f130e27d32 10 * Unless required by applicable law or agreed to in writing, software
mtkrtk 0:d0f130e27d32 11 * distributed under the License is distributed on an "AS IS" BASIS,
mtkrtk 0:d0f130e27d32 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mtkrtk 0:d0f130e27d32 13 * See the License for the specific language governing permissions and
mtkrtk 0:d0f130e27d32 14 * limitations under the License.
mtkrtk 0:d0f130e27d32 15 */
mtkrtk 0:d0f130e27d32 16
mtkrtk 0:d0f130e27d32 17 #if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
mtkrtk 0:d0f130e27d32 18
mtkrtk 0:d0f130e27d32 19 #include "mbed.h"
mtkrtk 0:d0f130e27d32 20 #include "USBHALHost.h"
mtkrtk 0:d0f130e27d32 21 #include "dbg.h"
mtkrtk 0:d0f130e27d32 22
mtkrtk 0:d0f130e27d32 23 #include "ohci_wrapp_RZ_A1.h"
mtkrtk 0:d0f130e27d32 24
mtkrtk 0:d0f130e27d32 25
mtkrtk 0:d0f130e27d32 26 #define HCCA_SIZE sizeof(HCCA)
mtkrtk 0:d0f130e27d32 27 #define ED_SIZE sizeof(HCED)
mtkrtk 0:d0f130e27d32 28 #define TD_SIZE sizeof(HCTD)
mtkrtk 0:d0f130e27d32 29
mtkrtk 0:d0f130e27d32 30 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
mtkrtk 0:d0f130e27d32 31 #define ALIGNE_MSK (0x0000000F)
mtkrtk 0:d0f130e27d32 32
mtkrtk 0:d0f130e27d32 33 static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK]; //16 bytes aligned!
mtkrtk 0:d0f130e27d32 34
mtkrtk 0:d0f130e27d32 35 USBHALHost * USBHALHost::instHost;
mtkrtk 0:d0f130e27d32 36
mtkrtk 0:d0f130e27d32 37 USBHALHost::USBHALHost() {
mtkrtk 0:d0f130e27d32 38 instHost = this;
mtkrtk 0:d0f130e27d32 39 memInit();
mtkrtk 0:d0f130e27d32 40 memset((void*)usb_hcca, 0, HCCA_SIZE);
mtkrtk 0:d0f130e27d32 41 for (int i = 0; i < MAX_ENDPOINT; i++) {
mtkrtk 0:d0f130e27d32 42 edBufAlloc[i] = false;
mtkrtk 0:d0f130e27d32 43 }
mtkrtk 0:d0f130e27d32 44 for (int i = 0; i < MAX_TD; i++) {
mtkrtk 0:d0f130e27d32 45 tdBufAlloc[i] = false;
mtkrtk 0:d0f130e27d32 46 }
mtkrtk 0:d0f130e27d32 47 }
mtkrtk 0:d0f130e27d32 48
mtkrtk 0:d0f130e27d32 49 void USBHALHost::init() {
mtkrtk 0:d0f130e27d32 50 ohciwrapp_init(&_usbisr);
mtkrtk 0:d0f130e27d32 51
mtkrtk 0:d0f130e27d32 52 ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET
mtkrtk 0:d0f130e27d32 53 ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero
mtkrtk 0:d0f130e27d32 54 ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0); // Initialize Bulk list head to Zero
mtkrtk 0:d0f130e27d32 55
mtkrtk 0:d0f130e27d32 56 // Wait 100 ms before apply reset
mtkrtk 0:d0f130e27d32 57 wait_ms(100);
mtkrtk 0:d0f130e27d32 58
mtkrtk 0:d0f130e27d32 59 // software reset
mtkrtk 0:d0f130e27d32 60 ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR);
mtkrtk 0:d0f130e27d32 61
mtkrtk 0:d0f130e27d32 62 // Write Fm Interval and Largest Data Packet Counter
mtkrtk 0:d0f130e27d32 63 ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL);
mtkrtk 0:d0f130e27d32 64 ohciwrapp_reg_w(OHCI_REG_PERIODICSTART, FI * 90 / 100);
mtkrtk 0:d0f130e27d32 65
mtkrtk 0:d0f130e27d32 66 // Put HC in operational state
mtkrtk 0:d0f130e27d32 67 ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER);
mtkrtk 0:d0f130e27d32 68 // Set Global Power
mtkrtk 0:d0f130e27d32 69 ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC);
mtkrtk 0:d0f130e27d32 70
mtkrtk 0:d0f130e27d32 71 ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca));
mtkrtk 0:d0f130e27d32 72
mtkrtk 0:d0f130e27d32 73 // Clear Interrrupt Status
mtkrtk 0:d0f130e27d32 74 ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS));
mtkrtk 0:d0f130e27d32 75
mtkrtk 0:d0f130e27d32 76 ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC);
mtkrtk 0:d0f130e27d32 77
mtkrtk 0:d0f130e27d32 78 // Enable the USB Interrupt
mtkrtk 0:d0f130e27d32 79 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
mtkrtk 0:d0f130e27d32 80 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
mtkrtk 0:d0f130e27d32 81
mtkrtk 0:d0f130e27d32 82 // Check for any connected devices
mtkrtk 0:d0f130e27d32 83 if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
mtkrtk 0:d0f130e27d32 84 //Device connected
mtkrtk 0:d0f130e27d32 85 wait_ms(150);
mtkrtk 0:d0f130e27d32 86 USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1));
mtkrtk 0:d0f130e27d32 87 deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
mtkrtk 0:d0f130e27d32 88 }
mtkrtk 0:d0f130e27d32 89 }
mtkrtk 0:d0f130e27d32 90
mtkrtk 0:d0f130e27d32 91 uint32_t USBHALHost::controlHeadED() {
mtkrtk 0:d0f130e27d32 92 return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED);
mtkrtk 0:d0f130e27d32 93 }
mtkrtk 0:d0f130e27d32 94
mtkrtk 0:d0f130e27d32 95 uint32_t USBHALHost::bulkHeadED() {
mtkrtk 0:d0f130e27d32 96 return ohciwrapp_reg_r(OHCI_REG_BULKHEADED);
mtkrtk 0:d0f130e27d32 97 }
mtkrtk 0:d0f130e27d32 98
mtkrtk 0:d0f130e27d32 99 uint32_t USBHALHost::interruptHeadED() {
mtkrtk 0:d0f130e27d32 100 return usb_hcca->IntTable[0];
mtkrtk 0:d0f130e27d32 101 }
mtkrtk 0:d0f130e27d32 102
mtkrtk 0:d0f130e27d32 103 void USBHALHost::updateBulkHeadED(uint32_t addr) {
mtkrtk 0:d0f130e27d32 104 ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr);
mtkrtk 0:d0f130e27d32 105 }
mtkrtk 0:d0f130e27d32 106
mtkrtk 0:d0f130e27d32 107
mtkrtk 0:d0f130e27d32 108 void USBHALHost::updateControlHeadED(uint32_t addr) {
mtkrtk 0:d0f130e27d32 109 ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr);
mtkrtk 0:d0f130e27d32 110 }
mtkrtk 0:d0f130e27d32 111
mtkrtk 0:d0f130e27d32 112 void USBHALHost::updateInterruptHeadED(uint32_t addr) {
mtkrtk 0:d0f130e27d32 113 usb_hcca->IntTable[0] = addr;
mtkrtk 0:d0f130e27d32 114 }
mtkrtk 0:d0f130e27d32 115
mtkrtk 0:d0f130e27d32 116
mtkrtk 0:d0f130e27d32 117 void USBHALHost::enableList(ENDPOINT_TYPE type) {
mtkrtk 0:d0f130e27d32 118 uint32_t wk_data;
mtkrtk 0:d0f130e27d32 119
mtkrtk 0:d0f130e27d32 120 switch(type) {
mtkrtk 0:d0f130e27d32 121 case CONTROL_ENDPOINT:
mtkrtk 0:d0f130e27d32 122 ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF);
mtkrtk 0:d0f130e27d32 123 wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE);
mtkrtk 0:d0f130e27d32 124 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
mtkrtk 0:d0f130e27d32 125 break;
mtkrtk 0:d0f130e27d32 126 case ISOCHRONOUS_ENDPOINT:
mtkrtk 0:d0f130e27d32 127 break;
mtkrtk 0:d0f130e27d32 128 case BULK_ENDPOINT:
mtkrtk 0:d0f130e27d32 129 ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF);
mtkrtk 0:d0f130e27d32 130 wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE);
mtkrtk 0:d0f130e27d32 131 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
mtkrtk 0:d0f130e27d32 132 break;
mtkrtk 0:d0f130e27d32 133 case INTERRUPT_ENDPOINT:
mtkrtk 0:d0f130e27d32 134 wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE);
mtkrtk 0:d0f130e27d32 135 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
mtkrtk 0:d0f130e27d32 136 break;
mtkrtk 0:d0f130e27d32 137 }
mtkrtk 0:d0f130e27d32 138 }
mtkrtk 0:d0f130e27d32 139
mtkrtk 0:d0f130e27d32 140
mtkrtk 0:d0f130e27d32 141 bool USBHALHost::disableList(ENDPOINT_TYPE type) {
mtkrtk 0:d0f130e27d32 142 uint32_t wk_data;
mtkrtk 0:d0f130e27d32 143
mtkrtk 0:d0f130e27d32 144 switch(type) {
mtkrtk 0:d0f130e27d32 145 case CONTROL_ENDPOINT:
mtkrtk 0:d0f130e27d32 146 wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
mtkrtk 0:d0f130e27d32 147 if(wk_data & OR_CONTROL_CLE) {
mtkrtk 0:d0f130e27d32 148 wk_data &= ~OR_CONTROL_CLE;
mtkrtk 0:d0f130e27d32 149 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
mtkrtk 0:d0f130e27d32 150 return true;
mtkrtk 0:d0f130e27d32 151 }
mtkrtk 0:d0f130e27d32 152 return false;
mtkrtk 0:d0f130e27d32 153 case ISOCHRONOUS_ENDPOINT:
mtkrtk 0:d0f130e27d32 154 return false;
mtkrtk 0:d0f130e27d32 155 case BULK_ENDPOINT:
mtkrtk 0:d0f130e27d32 156 wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
mtkrtk 0:d0f130e27d32 157 if(wk_data & OR_CONTROL_BLE) {
mtkrtk 0:d0f130e27d32 158 wk_data &= ~OR_CONTROL_BLE;
mtkrtk 0:d0f130e27d32 159 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
mtkrtk 0:d0f130e27d32 160 return true;
mtkrtk 0:d0f130e27d32 161 }
mtkrtk 0:d0f130e27d32 162 return false;
mtkrtk 0:d0f130e27d32 163 case INTERRUPT_ENDPOINT:
mtkrtk 0:d0f130e27d32 164 wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
mtkrtk 0:d0f130e27d32 165 if(wk_data & OR_CONTROL_PLE) {
mtkrtk 0:d0f130e27d32 166 wk_data &= ~OR_CONTROL_PLE;
mtkrtk 0:d0f130e27d32 167 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
mtkrtk 0:d0f130e27d32 168 return true;
mtkrtk 0:d0f130e27d32 169 }
mtkrtk 0:d0f130e27d32 170 return false;
mtkrtk 0:d0f130e27d32 171 }
mtkrtk 0:d0f130e27d32 172 return false;
mtkrtk 0:d0f130e27d32 173 }
mtkrtk 0:d0f130e27d32 174
mtkrtk 0:d0f130e27d32 175
mtkrtk 0:d0f130e27d32 176 void USBHALHost::memInit() {
mtkrtk 0:d0f130e27d32 177 volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK);
mtkrtk 0:d0f130e27d32 178
mtkrtk 0:d0f130e27d32 179 usb_hcca = (volatile HCCA *)p_wk_buf;
mtkrtk 0:d0f130e27d32 180 usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE);
mtkrtk 0:d0f130e27d32 181 usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE));
mtkrtk 0:d0f130e27d32 182 }
mtkrtk 0:d0f130e27d32 183
mtkrtk 0:d0f130e27d32 184 volatile uint8_t * USBHALHost::getED() {
mtkrtk 0:d0f130e27d32 185 for (int i = 0; i < MAX_ENDPOINT; i++) {
mtkrtk 0:d0f130e27d32 186 if ( !edBufAlloc[i] ) {
mtkrtk 0:d0f130e27d32 187 edBufAlloc[i] = true;
mtkrtk 0:d0f130e27d32 188 return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
mtkrtk 0:d0f130e27d32 189 }
mtkrtk 0:d0f130e27d32 190 }
mtkrtk 0:d0f130e27d32 191 perror("Could not allocate ED\r\n");
mtkrtk 0:d0f130e27d32 192 return NULL; //Could not alloc ED
mtkrtk 0:d0f130e27d32 193 }
mtkrtk 0:d0f130e27d32 194
mtkrtk 0:d0f130e27d32 195 volatile uint8_t * USBHALHost::getTD() {
mtkrtk 0:d0f130e27d32 196 int i;
mtkrtk 0:d0f130e27d32 197 for (i = 0; i < MAX_TD; i++) {
mtkrtk 0:d0f130e27d32 198 if ( !tdBufAlloc[i] ) {
mtkrtk 0:d0f130e27d32 199 tdBufAlloc[i] = true;
mtkrtk 0:d0f130e27d32 200 return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
mtkrtk 0:d0f130e27d32 201 }
mtkrtk 0:d0f130e27d32 202 }
mtkrtk 0:d0f130e27d32 203 perror("Could not allocate TD\r\n");
mtkrtk 0:d0f130e27d32 204 return NULL; //Could not alloc TD
mtkrtk 0:d0f130e27d32 205 }
mtkrtk 0:d0f130e27d32 206
mtkrtk 0:d0f130e27d32 207
mtkrtk 0:d0f130e27d32 208 void USBHALHost::freeED(volatile uint8_t * ed) {
mtkrtk 0:d0f130e27d32 209 int i;
mtkrtk 0:d0f130e27d32 210 i = (ed - usb_edBuf) / ED_SIZE;
mtkrtk 0:d0f130e27d32 211 edBufAlloc[i] = false;
mtkrtk 0:d0f130e27d32 212 }
mtkrtk 0:d0f130e27d32 213
mtkrtk 0:d0f130e27d32 214 void USBHALHost::freeTD(volatile uint8_t * td) {
mtkrtk 0:d0f130e27d32 215 int i;
mtkrtk 0:d0f130e27d32 216 i = (td - usb_tdBuf) / TD_SIZE;
mtkrtk 0:d0f130e27d32 217 tdBufAlloc[i] = false;
mtkrtk 0:d0f130e27d32 218 }
mtkrtk 0:d0f130e27d32 219
mtkrtk 0:d0f130e27d32 220
mtkrtk 0:d0f130e27d32 221 void USBHALHost::resetRootHub() {
mtkrtk 0:d0f130e27d32 222 // Initiate port reset
mtkrtk 0:d0f130e27d32 223 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS);
mtkrtk 0:d0f130e27d32 224
mtkrtk 0:d0f130e27d32 225 while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS);
mtkrtk 0:d0f130e27d32 226
mtkrtk 0:d0f130e27d32 227 // ...and clear port reset signal
mtkrtk 0:d0f130e27d32 228 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
mtkrtk 0:d0f130e27d32 229 }
mtkrtk 0:d0f130e27d32 230
mtkrtk 0:d0f130e27d32 231
mtkrtk 0:d0f130e27d32 232 void USBHALHost::_usbisr(void) {
mtkrtk 0:d0f130e27d32 233 if (instHost) {
mtkrtk 0:d0f130e27d32 234 instHost->UsbIrqhandler();
mtkrtk 0:d0f130e27d32 235 }
mtkrtk 0:d0f130e27d32 236 }
mtkrtk 0:d0f130e27d32 237
mtkrtk 0:d0f130e27d32 238 void USBHALHost::UsbIrqhandler() {
mtkrtk 0:d0f130e27d32 239 uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE);
mtkrtk 0:d0f130e27d32 240 uint32_t data;
mtkrtk 0:d0f130e27d32 241
mtkrtk 0:d0f130e27d32 242 if (int_status != 0) { //Is there something to actually process?
mtkrtk 0:d0f130e27d32 243 // Root hub status change interrupt
mtkrtk 0:d0f130e27d32 244 if (int_status & OR_INTR_STATUS_RHSC) {
mtkrtk 0:d0f130e27d32 245 if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) {
mtkrtk 0:d0f130e27d32 246 if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) {
mtkrtk 0:d0f130e27d32 247 // When DRWE is on, Connect Status Change
mtkrtk 0:d0f130e27d32 248 // means a remote wakeup event.
mtkrtk 0:d0f130e27d32 249 } else {
mtkrtk 0:d0f130e27d32 250
mtkrtk 0:d0f130e27d32 251 //Root device connected
mtkrtk 0:d0f130e27d32 252 if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
mtkrtk 0:d0f130e27d32 253
mtkrtk 0:d0f130e27d32 254 // wait 150ms to avoid bounce
mtkrtk 0:d0f130e27d32 255 wait_ms(150);
mtkrtk 0:d0f130e27d32 256
mtkrtk 0:d0f130e27d32 257 //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
mtkrtk 0:d0f130e27d32 258 data = ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA;
mtkrtk 0:d0f130e27d32 259 deviceConnected(0, 1, data);
mtkrtk 0:d0f130e27d32 260 }
mtkrtk 0:d0f130e27d32 261
mtkrtk 0:d0f130e27d32 262 //Root device disconnected
mtkrtk 0:d0f130e27d32 263 else {
mtkrtk 0:d0f130e27d32 264 deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
mtkrtk 0:d0f130e27d32 265 }
mtkrtk 0:d0f130e27d32 266 }
mtkrtk 0:d0f130e27d32 267 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
mtkrtk 0:d0f130e27d32 268 }
mtkrtk 0:d0f130e27d32 269 if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) {
mtkrtk 0:d0f130e27d32 270 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
mtkrtk 0:d0f130e27d32 271 }
mtkrtk 0:d0f130e27d32 272 ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC);
mtkrtk 0:d0f130e27d32 273 }
mtkrtk 0:d0f130e27d32 274
mtkrtk 0:d0f130e27d32 275 // Writeback Done Head interrupt
mtkrtk 0:d0f130e27d32 276 if (int_status & OR_INTR_STATUS_WDH) {
mtkrtk 0:d0f130e27d32 277 transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
mtkrtk 0:d0f130e27d32 278 ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
mtkrtk 0:d0f130e27d32 279 }
mtkrtk 0:d0f130e27d32 280 }
mtkrtk 0:d0f130e27d32 281 }
mtkrtk 0:d0f130e27d32 282 #endif
mtkrtk 0:d0f130e27d32 283