Martin Smith / Mbed 2 deprecated OV7670_Testing

A program that records images from the OV7670 camera and displays them on a SPI TFT display. Working at 15fps

Dependencies:   mbed TFT_fonts_old

ov7670reg.h@1:c98598814170, 2012-03-31 (annotated)

Committer:
ms523
Date:
Sat Mar 31 10:05:59 2012 +0000
Revision:
1:c98598814170
Parent:
0:aabbf2286bf2 
Working at 15fps for 160*120 RGB565 video

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ms523 0:aabbf2286bf2 1 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
ms523 0:aabbf2286bf2 2 #define REG_BLUE 0x01 /* blue gain */
ms523 0:aabbf2286bf2 3 #define REG_RED 0x02 /* red gain */
ms523 0:aabbf2286bf2 4 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
ms523 0:aabbf2286bf2 5 #define REG_COM1 0x04 /* Control 1 */
ms523 0:aabbf2286bf2 6 #define COM1_CCIR656 0x40 /* CCIR656 enable */
ms523 0:aabbf2286bf2 7 #define REG_BAVE 0x05 /* U/B Average level */
ms523 0:aabbf2286bf2 8 #define REG_GbAVE 0x06 /* Y/Gb Average level */
ms523 0:aabbf2286bf2 9 #define REG_AECHH 0x07 /* AEC MS 5 bits */
ms523 0:aabbf2286bf2 10 #define REG_RAVE 0x08 /* V/R Average level */
ms523 0:aabbf2286bf2 11 #define REG_COM2 0x09 /* Control 2 */
ms523 0:aabbf2286bf2 12 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
ms523 0:aabbf2286bf2 13 #define REG_PID 0x0a /* Product ID MSB */
ms523 0:aabbf2286bf2 14 #define REG_VER 0x0b /* Product ID LSB */
ms523 0:aabbf2286bf2 15 #define REG_COM3 0x0c /* Control 3 */
ms523 0:aabbf2286bf2 16 #define COM3_SWAP 0x40 /* Byte swap */
ms523 0:aabbf2286bf2 17 #define COM3_SCALEEN 0x08 /* Enable scaling */
ms523 0:aabbf2286bf2 18 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
ms523 0:aabbf2286bf2 19 #define REG_COM4 0x0d /* Control 4 */
ms523 0:aabbf2286bf2 20 #define REG_COM5 0x0e /* All "reserved" */
ms523 0:aabbf2286bf2 21 #define REG_COM6 0x0f /* Control 6 */
ms523 0:aabbf2286bf2 22 #define REG_AECH 0x10 /* More bits of AEC value */
ms523 0:aabbf2286bf2 23 #define REG_CLKRC 0x11 /* Clocl control */
ms523 0:aabbf2286bf2 24 #define CLK_EXT 0x40 /* Use external clock directly */
ms523 0:aabbf2286bf2 25 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
ms523 0:aabbf2286bf2 26 #define REG_COM7 0x12 /* Control 7 */
ms523 0:aabbf2286bf2 27 #define COM7_RESET 0x80 /* Register reset */
ms523 0:aabbf2286bf2 28 #define COM7_FMT_MASK 0x38
ms523 0:aabbf2286bf2 29 #define COM7_FMT_VGA 0x00
ms523 0:aabbf2286bf2 30 #define COM7_FMT_CIF 0x20 /* CIF format */
ms523 0:aabbf2286bf2 31 #define COM7_FMT_QVGA 0x10 /* QVGA format */
ms523 0:aabbf2286bf2 32 #define COM7_FMT_QCIF 0x08 /* QCIF format */
ms523 0:aabbf2286bf2 33 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
ms523 0:aabbf2286bf2 34 #define COM7_YUV 0x00 /* YUV */
ms523 0:aabbf2286bf2 35 #define COM7_BAYER 0x01 /* Bayer format */
ms523 0:aabbf2286bf2 36 #define COM7_PBAYER 0x05 /* "Processed bayer" */
ms523 0:aabbf2286bf2 37 #define REG_COM8 0x13 /* Control 8 */
ms523 0:aabbf2286bf2 38 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
ms523 0:aabbf2286bf2 39 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
ms523 0:aabbf2286bf2 40 #define COM8_BFILT 0x20 /* Band filter enable */
ms523 0:aabbf2286bf2 41 #define COM8_AGC 0x04 /* Auto gain enable */
ms523 0:aabbf2286bf2 42 #define COM8_AWB 0x02 /* White balance enable */
ms523 0:aabbf2286bf2 43 #define COM8_AEC 0x01 /* Auto exposure enable */
ms523 0:aabbf2286bf2 44 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
ms523 0:aabbf2286bf2 45 #define REG_COM10 0x15 /* Control 10 */
ms523 0:aabbf2286bf2 46 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
ms523 0:aabbf2286bf2 47 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
ms523 0:aabbf2286bf2 48 #define COM10_HREF_REV 0x08 /* Reverse HREF */
ms523 0:aabbf2286bf2 49 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
ms523 0:aabbf2286bf2 50 #define COM10_VS_NEG 0x02 /* VSYNC negative */
ms523 0:aabbf2286bf2 51 #define COM10_HS_NEG 0x01 /* HSYNC negative */
ms523 0:aabbf2286bf2 52 #define REG_HSTART 0x17 /* Horiz start high bits */
ms523 0:aabbf2286bf2 53 #define REG_HSTOP 0x18 /* Horiz stop high bits */
ms523 0:aabbf2286bf2 54 #define REG_VSTART 0x19 /* Vert start high bits */
ms523 0:aabbf2286bf2 55 #define REG_VSTOP 0x1a /* Vert stop high bits */
ms523 0:aabbf2286bf2 56 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
ms523 0:aabbf2286bf2 57 #define REG_MIDH 0x1c /* Manuf. ID high */
ms523 0:aabbf2286bf2 58 #define REG_MIDL 0x1d /* Manuf. ID low */
ms523 0:aabbf2286bf2 59 #define REG_MVFP 0x1e /* Mirror / vflip */
ms523 0:aabbf2286bf2 60 #define MVFP_MIRROR 0x20 /* Mirror image */
ms523 0:aabbf2286bf2 61 #define MVFP_FLIP 0x10 /* Vertical flip */
ms523 0:aabbf2286bf2 62 #define REG_AEW 0x24 /* AGC upper limit */
ms523 0:aabbf2286bf2 63 #define REG_AEB 0x25 /* AGC lower limit */
ms523 0:aabbf2286bf2 64 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
ms523 0:aabbf2286bf2 65 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
ms523 0:aabbf2286bf2 66 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
ms523 0:aabbf2286bf2 67 #define REG_HREF 0x32 /* HREF pieces */
ms523 0:aabbf2286bf2 68 #define REG_TSLB 0x3a /* lots of stuff */
ms523 0:aabbf2286bf2 69 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
ms523 0:aabbf2286bf2 70 #define REG_COM11 0x3b /* Control 11 */
ms523 0:aabbf2286bf2 71 #define COM11_NIGHT 0x80 /* NIght mode enable */
ms523 0:aabbf2286bf2 72 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
ms523 0:aabbf2286bf2 73 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
ms523 0:aabbf2286bf2 74 #define COM11_50HZ 0x08 /* Manual 50Hz select */
ms523 0:aabbf2286bf2 75 #define COM11_EXP 0x02
ms523 0:aabbf2286bf2 76 #define REG_COM12 0x3c /* Control 12 */
ms523 0:aabbf2286bf2 77 #define COM12_HREF 0x80 /* HREF always */
ms523 0:aabbf2286bf2 78 #define REG_COM13 0x3d /* Control 13 */
ms523 0:aabbf2286bf2 79 #define COM13_GAMMA 0x80 /* Gamma enable */
ms523 0:aabbf2286bf2 80 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
ms523 0:aabbf2286bf2 81 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
ms523 0:aabbf2286bf2 82 #define REG_COM14 0x3e /* Control 14 */
ms523 0:aabbf2286bf2 83 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
ms523 0:aabbf2286bf2 84 #define REG_EDGE 0x3f /* Edge enhancement factor */
ms523 0:aabbf2286bf2 85 #define REG_COM15 0x40 /* Control 15 */
ms523 0:aabbf2286bf2 86 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
ms523 0:aabbf2286bf2 87 #define COM15_R01FE 0x80 /* 01 to FE */
ms523 0:aabbf2286bf2 88 #define COM15_R00FF 0xc0 /* 00 to FF */
ms523 0:aabbf2286bf2 89 #define COM15_RGB565 0x10 /* RGB565 output */
ms523 0:aabbf2286bf2 90 #define COM15_RGB555 0x30 /* RGB555 output */
ms523 0:aabbf2286bf2 91 #define REG_COM16 0x41 /* Control 16 */
ms523 0:aabbf2286bf2 92 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
ms523 0:aabbf2286bf2 93 #define REG_COM17 0x42 /* Control 17 */
ms523 0:aabbf2286bf2 94 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
ms523 0:aabbf2286bf2 95 #define COM17_CBAR 0x08 /* DSP Color bar */
ms523 0:aabbf2286bf2 96 #define REG_CMATRIX_BASE 0x4f
ms523 0:aabbf2286bf2 97 #define CMATRIX_LEN 6
ms523 0:aabbf2286bf2 98 #define REG_CMATRIX_SIGN 0x58
ms523 0:aabbf2286bf2 99 #define REG_BRIGHT 0x55 /* Brightness */
ms523 0:aabbf2286bf2 100 #define REG_CONTRAS 0x56 /* Contrast control */
ms523 0:aabbf2286bf2 101 #define REG_GFIX 0x69 /* Fix gain control */
ms523 0:aabbf2286bf2 102 #define REG_REG76 0x76 /* OV's name */
ms523 0:aabbf2286bf2 103 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
ms523 0:aabbf2286bf2 104 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
ms523 0:aabbf2286bf2 105 #define REG_RGB444 0x8c /* RGB 444 control */
ms523 0:aabbf2286bf2 106 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
ms523 0:aabbf2286bf2 107 #define R444_RGBX 0x01 /* Empty nibble at end */
ms523 0:aabbf2286bf2 108 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
ms523 0:aabbf2286bf2 109 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
ms523 0:aabbf2286bf2 110 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
ms523 0:aabbf2286bf2 111 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
ms523 0:aabbf2286bf2 112 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
ms523 0:aabbf2286bf2 113 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
ms523 0:aabbf2286bf2 114 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
ms523 0:aabbf2286bf2 115 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
ms523 0:aabbf2286bf2 116 #define REG_BD60MAX 0xab /* 60hz banding step limit */