Sertel_Srinath Gopalan / USB_Log_Drive

Sertel USB Log

Fork of MSCFileSystem by Chris Styles

USBHostLite/usbhost_lpc17xx.cpp@8:cccdf653258b, 2016-06-12 (annotated)

Committer:
mrsoundhar
Date:
Sun Jun 12 16:44:44 2016 +0000
Revision:
8:cccdf653258b
Parent:
4:dcc326e4d358 
Soundharrajan USB Log for Drive

Who changed what in which revision?

UserRevisionLine numberNew contents of line
chris 0:3e7d2baed4b4 1 /*
chris 0:3e7d2baed4b4 2 **************************************************************************************************************
chris 0:3e7d2baed4b4 3 * NXP USB Host Stack
chris 0:3e7d2baed4b4 4 *
chris 0:3e7d2baed4b4 5 * (c) Copyright 2008, NXP SemiConductors
chris 0:3e7d2baed4b4 6 * (c) Copyright 2008, OnChip Technologies LLC
chris 0:3e7d2baed4b4 7 * All Rights Reserved
chris 0:3e7d2baed4b4 8 *
chris 0:3e7d2baed4b4 9 * www.nxp.com
chris 0:3e7d2baed4b4 10 * www.onchiptech.com
chris 0:3e7d2baed4b4 11 *
chris 0:3e7d2baed4b4 12 * File : usbhost_lpc17xx.c
chris 0:3e7d2baed4b4 13 * Programmer(s) : Ravikanth.P
chris 0:3e7d2baed4b4 14 * Version :
chris 0:3e7d2baed4b4 15 *
chris 0:3e7d2baed4b4 16 **************************************************************************************************************
chris 0:3e7d2baed4b4 17 */
chris 0:3e7d2baed4b4 18
chris 0:3e7d2baed4b4 19 /*
chris 0:3e7d2baed4b4 20 **************************************************************************************************************
chris 0:3e7d2baed4b4 21 * INCLUDE HEADER FILES
chris 0:3e7d2baed4b4 22 **************************************************************************************************************
chris 0:3e7d2baed4b4 23 */
chris 0:3e7d2baed4b4 24
chris 0:3e7d2baed4b4 25 #include "usbhost_lpc17xx.h"
chris 0:3e7d2baed4b4 26
chris 0:3e7d2baed4b4 27 /*
chris 0:3e7d2baed4b4 28 **************************************************************************************************************
chris 0:3e7d2baed4b4 29 * GLOBAL VARIABLES
chris 0:3e7d2baed4b4 30 **************************************************************************************************************
chris 0:3e7d2baed4b4 31 */
chris 0:3e7d2baed4b4 32 int gUSBConnected;
chris 0:3e7d2baed4b4 33
chris 0:3e7d2baed4b4 34 volatile USB_INT32U HOST_RhscIntr = 0; /* Root Hub Status Change interrupt */
chris 0:3e7d2baed4b4 35 volatile USB_INT32U HOST_WdhIntr = 0; /* Semaphore to wait until the TD is submitted */
chris 0:3e7d2baed4b4 36 volatile USB_INT08U HOST_TDControlStatus = 0;
chris 0:3e7d2baed4b4 37 volatile HCED *EDCtrl; /* Control endpoint descriptor structure */
chris 0:3e7d2baed4b4 38 volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
chris 0:3e7d2baed4b4 39 volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
chris 0:3e7d2baed4b4 40 volatile HCTD *TDHead; /* Head transfer descriptor structure */
chris 0:3e7d2baed4b4 41 volatile HCTD *TDTail; /* Tail transfer descriptor structure */
chris 0:3e7d2baed4b4 42 volatile HCCA *Hcca; /* Host Controller Communications Area structure */
chris 0:3e7d2baed4b4 43 USB_INT16U *TDBufNonVol; /* Identical to TDBuffer just to reduce compiler warnings */
chris 0:3e7d2baed4b4 44 volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
chris 0:3e7d2baed4b4 45
chris 0:3e7d2baed4b4 46 // USB host structures
chris 0:3e7d2baed4b4 47 // AHB SRAM block 1
chris 0:3e7d2baed4b4 48 #define HOSTBASEADDR 0x2007C000
chris 0:3e7d2baed4b4 49 // reserve memory for the linker
chris 0:3e7d2baed4b4 50 static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
chris 0:3e7d2baed4b4 51 /*
chris 0:3e7d2baed4b4 52 **************************************************************************************************************
chris 0:3e7d2baed4b4 53 * DELAY IN MILLI SECONDS
chris 0:3e7d2baed4b4 54 *
chris 0:3e7d2baed4b4 55 * Description: This function provides a delay in milli seconds
chris 0:3e7d2baed4b4 56 *
chris 0:3e7d2baed4b4 57 * Arguments : delay The delay required
chris 0:3e7d2baed4b4 58 *
chris 0:3e7d2baed4b4 59 * Returns : None
chris 0:3e7d2baed4b4 60 *
chris 0:3e7d2baed4b4 61 **************************************************************************************************************
chris 0:3e7d2baed4b4 62 */
chris 0:3e7d2baed4b4 63
chris 0:3e7d2baed4b4 64 void Host_DelayMS (USB_INT32U delay)
chris 0:3e7d2baed4b4 65 {
chris 0:3e7d2baed4b4 66 volatile USB_INT32U i;
chris 0:3e7d2baed4b4 67
chris 0:3e7d2baed4b4 68
chris 0:3e7d2baed4b4 69 for (i = 0; i < delay; i++) {
chris 0:3e7d2baed4b4 70 Host_DelayUS(1000);
chris 0:3e7d2baed4b4 71 }
chris 0:3e7d2baed4b4 72 }
chris 0:3e7d2baed4b4 73
chris 0:3e7d2baed4b4 74 /*
chris 0:3e7d2baed4b4 75 **************************************************************************************************************
chris 0:3e7d2baed4b4 76 * DELAY IN MICRO SECONDS
chris 0:3e7d2baed4b4 77 *
chris 0:3e7d2baed4b4 78 * Description: This function provides a delay in micro seconds
chris 0:3e7d2baed4b4 79 *
chris 0:3e7d2baed4b4 80 * Arguments : delay The delay required
chris 0:3e7d2baed4b4 81 *
chris 0:3e7d2baed4b4 82 * Returns : None
chris 0:3e7d2baed4b4 83 *
chris 0:3e7d2baed4b4 84 **************************************************************************************************************
chris 0:3e7d2baed4b4 85 */
chris 0:3e7d2baed4b4 86
chris 0:3e7d2baed4b4 87 void Host_DelayUS (USB_INT32U delay)
chris 0:3e7d2baed4b4 88 {
chris 0:3e7d2baed4b4 89 volatile USB_INT32U i;
chris 0:3e7d2baed4b4 90
chris 0:3e7d2baed4b4 91
chris 0:3e7d2baed4b4 92 for (i = 0; i < (4 * delay); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
chris 0:3e7d2baed4b4 93 ;
chris 0:3e7d2baed4b4 94 }
chris 0:3e7d2baed4b4 95 }
chris 0:3e7d2baed4b4 96
chris 0:3e7d2baed4b4 97 // bits of the USB/OTG clock control register
chris 0:3e7d2baed4b4 98 #define HOST_CLK_EN (1<<0)
chris 0:3e7d2baed4b4 99 #define DEV_CLK_EN (1<<1)
chris 0:3e7d2baed4b4 100 #define PORTSEL_CLK_EN (1<<3)
chris 0:3e7d2baed4b4 101 #define AHB_CLK_EN (1<<4)
chris 0:3e7d2baed4b4 102
chris 0:3e7d2baed4b4 103 // bits of the USB/OTG clock status register
chris 0:3e7d2baed4b4 104 #define HOST_CLK_ON (1<<0)
chris 0:3e7d2baed4b4 105 #define DEV_CLK_ON (1<<1)
chris 0:3e7d2baed4b4 106 #define PORTSEL_CLK_ON (1<<3)
chris 0:3e7d2baed4b4 107 #define AHB_CLK_ON (1<<4)
chris 0:3e7d2baed4b4 108
chris 0:3e7d2baed4b4 109 // we need host clock, OTG/portsel clock and AHB clock
chris 0:3e7d2baed4b4 110 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
chris 0:3e7d2baed4b4 111
chris 0:3e7d2baed4b4 112 /*
chris 0:3e7d2baed4b4 113 **************************************************************************************************************
chris 0:3e7d2baed4b4 114 * INITIALIZE THE HOST CONTROLLER
chris 0:3e7d2baed4b4 115 *
chris 0:3e7d2baed4b4 116 * Description: This function initializes lpc17xx host controller
chris 0:3e7d2baed4b4 117 *
chris 0:3e7d2baed4b4 118 * Arguments : None
chris 0:3e7d2baed4b4 119 *
chris 0:3e7d2baed4b4 120 * Returns :
chris 0:3e7d2baed4b4 121 *
chris 0:3e7d2baed4b4 122 **************************************************************************************************************
chris 0:3e7d2baed4b4 123 */
chris 0:3e7d2baed4b4 124 void Host_Init (void)
chris 0:3e7d2baed4b4 125 {
chris 0:3e7d2baed4b4 126 PRINT_Log("In Host_Init\n");
chris 0:3e7d2baed4b4 127 NVIC_DisableIRQ(USB_IRQn); /* Disable the USB interrupt source */
chris 0:3e7d2baed4b4 128
chris 0:3e7d2baed4b4 129 // turn on power for USB
chris 0:3e7d2baed4b4 130 LPC_SC->PCONP |= (1UL<<31);
chris 0:3e7d2baed4b4 131 // Enable USB host clock, port selection and AHB clock
chris 0:3e7d2baed4b4 132 LPC_USB->USBClkCtrl |= CLOCK_MASK;
chris 0:3e7d2baed4b4 133 // Wait for clocks to become available
mrsoundhar 8:cccdf653258b 134 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK) ;
chris 0:3e7d2baed4b4 135
chris 0:3e7d2baed4b4 136 // it seems the bits[0:1] mean the following
chris 0:3e7d2baed4b4 137 // 0: U1=device, U2=host
chris 0:3e7d2baed4b4 138 // 1: U1=host, U2=host
chris 0:3e7d2baed4b4 139 // 2: reserved
chris 0:3e7d2baed4b4 140 // 3: U1=host, U2=device
chris 0:3e7d2baed4b4 141 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
chris 0:3e7d2baed4b4 142 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
chris 0:3e7d2baed4b4 143 LPC_USB->OTGStCtrl |= 1;
chris 0:3e7d2baed4b4 144
chris 0:3e7d2baed4b4 145 // now that we've configured the ports, we can turn off the portsel clock
chris 0:3e7d2baed4b4 146 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
chris 0:3e7d2baed4b4 147
chris 0:3e7d2baed4b4 148 // power pins are not connected on mbed, so we can skip them
chris 0:3e7d2baed4b4 149 /* P1[18] = USB_UP_LED, 01 */
chris 0:3e7d2baed4b4 150 /* P1[19] = /USB_PPWR, 10 */
chris 0:3e7d2baed4b4 151 /* P1[22] = USB_PWRD, 10 */
chris 0:3e7d2baed4b4 152 /* P1[27] = /USB_OVRCR, 10 */
chris 0:3e7d2baed4b4 153 /*LPC_PINCON->PINSEL3 &= ~((3<<4) | (3<<6) | (3<<12) | (3<<22));
chris 0:3e7d2baed4b4 154 LPC_PINCON->PINSEL3 |= ((1<<4)|(2<<6) | (2<<12) | (2<<22)); // 0x00802080
chris 0:3e7d2baed4b4 155 */
chris 0:3e7d2baed4b4 156
chris 0:3e7d2baed4b4 157 // configure USB D+/D- pins
chris 0:3e7d2baed4b4 158 /* P0[29] = USB_D+, 01 */
chris 0:3e7d2baed4b4 159 /* P0[30] = USB_D-, 01 */
chris 0:3e7d2baed4b4 160 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
chris 0:3e7d2baed4b4 161 LPC_PINCON->PINSEL1 |= ((1<<26)|(1<<28)); // 0x14000000
chris 0:3e7d2baed4b4 162
chris 0:3e7d2baed4b4 163 PRINT_Log("Initializing Host Stack\n");
chris 0:3e7d2baed4b4 164
chris 0:3e7d2baed4b4 165 Hcca = (volatile HCCA *)(HostBuf+0x000);
chris 0:3e7d2baed4b4 166 TDHead = (volatile HCTD *)(HostBuf+0x100);
chris 0:3e7d2baed4b4 167 TDTail = (volatile HCTD *)(HostBuf+0x110);
chris 0:3e7d2baed4b4 168 EDCtrl = (volatile HCED *)(HostBuf+0x120);
chris 0:3e7d2baed4b4 169 EDBulkIn = (volatile HCED *)(HostBuf+0x130);
chris 0:3e7d2baed4b4 170 EDBulkOut = (volatile HCED *)(HostBuf+0x140);
chris 0:3e7d2baed4b4 171 TDBuffer = (volatile USB_INT08U *)(HostBuf+0x150);
chris 0:3e7d2baed4b4 172
chris 0:3e7d2baed4b4 173 /* Initialize all the TDs, EDs and HCCA to 0 */
chris 0:3e7d2baed4b4 174 Host_EDInit(EDCtrl);
chris 0:3e7d2baed4b4 175 Host_EDInit(EDBulkIn);
chris 0:3e7d2baed4b4 176 Host_EDInit(EDBulkOut);
chris 0:3e7d2baed4b4 177 Host_TDInit(TDHead);
chris 0:3e7d2baed4b4 178 Host_TDInit(TDTail);
chris 0:3e7d2baed4b4 179 Host_HCCAInit(Hcca);
chris 0:3e7d2baed4b4 180
chris 0:3e7d2baed4b4 181 Host_DelayMS(50); /* Wait 50 ms before apply reset */
chris 0:3e7d2baed4b4 182 LPC_USB->HcControl = 0; /* HARDWARE RESET */
chris 0:3e7d2baed4b4 183 LPC_USB->HcControlHeadED = 0; /* Initialize Control list head to Zero */
chris 0:3e7d2baed4b4 184 LPC_USB->HcBulkHeadED = 0; /* Initialize Bulk list head to Zero */
chris 0:3e7d2baed4b4 185
chris 0:3e7d2baed4b4 186 /* SOFTWARE RESET */
chris 0:3e7d2baed4b4 187 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
chris 0:3e7d2baed4b4 188 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; /* Write Fm Interval and Largest Data Packet Counter */
chris 0:3e7d2baed4b4 189
chris 0:3e7d2baed4b4 190 /* Put HC in operational state */
chris 0:3e7d2baed4b4 191 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
chris 0:3e7d2baed4b4 192 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; /* Set Global Power */
chris 0:3e7d2baed4b4 193
chris 0:3e7d2baed4b4 194 LPC_USB->HcHCCA = (USB_INT32U)Hcca;
chris 0:3e7d2baed4b4 195 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus; /* Clear Interrrupt Status */
chris 0:3e7d2baed4b4 196
chris 0:3e7d2baed4b4 197
chris 0:3e7d2baed4b4 198 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE |
chris 0:3e7d2baed4b4 199 OR_INTR_ENABLE_WDH |
chris 0:3e7d2baed4b4 200 OR_INTR_ENABLE_RHSC;
chris 0:3e7d2baed4b4 201
chris 0:3e7d2baed4b4 202 NVIC_SetPriority(USB_IRQn, 0); /* highest priority */
chris 0:3e7d2baed4b4 203 /* Enable the USB Interrupt */
chris 0:3e7d2baed4b4 204 NVIC_EnableIRQ(USB_IRQn);
chris 0:3e7d2baed4b4 205 PRINT_Log("Host Initialized\n");
chris 0:3e7d2baed4b4 206 }
chris 0:3e7d2baed4b4 207
chris 0:3e7d2baed4b4 208 /*
chris 0:3e7d2baed4b4 209 **************************************************************************************************************
chris 0:3e7d2baed4b4 210 * INTERRUPT SERVICE ROUTINE
chris 0:3e7d2baed4b4 211 *
chris 0:3e7d2baed4b4 212 * Description: This function services the interrupt caused by host controller
chris 0:3e7d2baed4b4 213 *
chris 0:3e7d2baed4b4 214 * Arguments : None
chris 0:3e7d2baed4b4 215 *
chris 0:3e7d2baed4b4 216 * Returns : None
chris 0:3e7d2baed4b4 217 *
chris 0:3e7d2baed4b4 218 **************************************************************************************************************
chris 0:3e7d2baed4b4 219 */
chris 0:3e7d2baed4b4 220
chris 0:3e7d2baed4b4 221 void USB_IRQHandler (void) __irq
chris 0:3e7d2baed4b4 222 {
chris 0:3e7d2baed4b4 223 USB_INT32U int_status;
chris 0:3e7d2baed4b4 224 USB_INT32U ie_status;
chris 0:3e7d2baed4b4 225
chris 0:3e7d2baed4b4 226 int_status = LPC_USB->HcInterruptStatus; /* Read Interrupt Status */
chris 0:3e7d2baed4b4 227 ie_status = LPC_USB->HcInterruptEnable; /* Read Interrupt enable status */
chris 0:3e7d2baed4b4 228
chris 0:3e7d2baed4b4 229 if (!(int_status & ie_status)) {
chris 0:3e7d2baed4b4 230 return;
chris 0:3e7d2baed4b4 231 } else {
chris 0:3e7d2baed4b4 232
chris 0:3e7d2baed4b4 233 int_status = int_status & ie_status;
chris 0:3e7d2baed4b4 234 if (int_status & OR_INTR_STATUS_RHSC) { /* Root hub status change interrupt */
chris 0:3e7d2baed4b4 235 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
chris 0:3e7d2baed4b4 236 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
chris 0:3e7d2baed4b4 237 /*
chris 0:3e7d2baed4b4 238 * When DRWE is on, Connect Status Change
chris 0:3e7d2baed4b4 239 * means a remote wakeup event.
chris 0:3e7d2baed4b4 240 */
chris 0:3e7d2baed4b4 241 HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
chris 0:3e7d2baed4b4 242 }
chris 0:3e7d2baed4b4 243 else {
chris 0:3e7d2baed4b4 244 /*
chris 0:3e7d2baed4b4 245 * When DRWE is off, Connect Status Change
chris 0:3e7d2baed4b4 246 * is NOT a remote wakeup event
chris 0:3e7d2baed4b4 247 */
chris 0:3e7d2baed4b4 248 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
chris 0:3e7d2baed4b4 249 if (!gUSBConnected) {
chris 0:3e7d2baed4b4 250 HOST_TDControlStatus = 0;
chris 0:3e7d2baed4b4 251 HOST_WdhIntr = 0;
chris 0:3e7d2baed4b4 252 HOST_RhscIntr = 1;
chris 0:3e7d2baed4b4 253 gUSBConnected = 1;
chris 0:3e7d2baed4b4 254 }
chris 0:3e7d2baed4b4 255 else
chris 0:3e7d2baed4b4 256 PRINT_Log("Spurious status change (connected)?\n");
chris 0:3e7d2baed4b4 257 } else {
chris 0:3e7d2baed4b4 258 if (gUSBConnected) {
chris 0:3e7d2baed4b4 259 LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
chris 0:3e7d2baed4b4 260 HOST_RhscIntr = 0;
chris 0:3e7d2baed4b4 261 gUSBConnected = 0;
chris 0:3e7d2baed4b4 262 }
chris 0:3e7d2baed4b4 263 else
chris 0:3e7d2baed4b4 264 PRINT_Log("Spurious status change (disconnected)?\n");
chris 0:3e7d2baed4b4 265 }
chris 0:3e7d2baed4b4 266 }
chris 0:3e7d2baed4b4 267 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
chris 0:3e7d2baed4b4 268 }
chris 0:3e7d2baed4b4 269 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
chris 0:3e7d2baed4b4 270 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
chris 0:3e7d2baed4b4 271 }
chris 0:3e7d2baed4b4 272 }
chris 0:3e7d2baed4b4 273 if (int_status & OR_INTR_STATUS_WDH) { /* Writeback Done Head interrupt */
chris 0:3e7d2baed4b4 274 HOST_WdhIntr = 1;
chris 0:3e7d2baed4b4 275 HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
chris 0:3e7d2baed4b4 276 }
chris 0:3e7d2baed4b4 277 LPC_USB->HcInterruptStatus = int_status; /* Clear interrupt status register */
chris 0:3e7d2baed4b4 278 }
chris 0:3e7d2baed4b4 279 return;
chris 0:3e7d2baed4b4 280 }
chris 0:3e7d2baed4b4 281
chris 0:3e7d2baed4b4 282 /*
chris 0:3e7d2baed4b4 283 **************************************************************************************************************
chris 0:3e7d2baed4b4 284 * PROCESS TRANSFER DESCRIPTOR
chris 0:3e7d2baed4b4 285 *
chris 0:3e7d2baed4b4 286 * Description: This function processes the transfer descriptor
chris 0:3e7d2baed4b4 287 *
chris 0:3e7d2baed4b4 288 * Arguments : ed Endpoint descriptor that contains this transfer descriptor
chris 0:3e7d2baed4b4 289 * token SETUP, IN, OUT
chris 0:3e7d2baed4b4 290 * buffer Current Buffer Pointer of the transfer descriptor
chris 0:3e7d2baed4b4 291 * buffer_len Length of the buffer
chris 0:3e7d2baed4b4 292 *
chris 0:3e7d2baed4b4 293 * Returns : OK if TD submission is successful
chris 0:3e7d2baed4b4 294 * ERROR if TD submission fails
chris 0:3e7d2baed4b4 295 *
chris 0:3e7d2baed4b4 296 **************************************************************************************************************
chris 0:3e7d2baed4b4 297 */
chris 0:3e7d2baed4b4 298
chris 0:3e7d2baed4b4 299 USB_INT32S Host_ProcessTD (volatile HCED *ed,
chris 0:3e7d2baed4b4 300 volatile USB_INT32U token,
chris 0:3e7d2baed4b4 301 volatile USB_INT08U *buffer,
chris 0:3e7d2baed4b4 302 USB_INT32U buffer_len)
chris 0:3e7d2baed4b4 303 {
chris 0:3e7d2baed4b4 304 volatile USB_INT32U td_toggle;
chris 0:3e7d2baed4b4 305
chris 0:3e7d2baed4b4 306
chris 0:3e7d2baed4b4 307 if (ed == EDCtrl) {
chris 0:3e7d2baed4b4 308 if (token == TD_SETUP) {
chris 0:3e7d2baed4b4 309 td_toggle = TD_TOGGLE_0;
chris 0:3e7d2baed4b4 310 } else {
chris 0:3e7d2baed4b4 311 td_toggle = TD_TOGGLE_1;
chris 0:3e7d2baed4b4 312 }
chris 0:3e7d2baed4b4 313 } else {
chris 0:3e7d2baed4b4 314 td_toggle = 0;
chris 0:3e7d2baed4b4 315 }
chris 0:3e7d2baed4b4 316 TDHead->Control = (TD_ROUNDING |
chris 0:3e7d2baed4b4 317 token |
chris 0:3e7d2baed4b4 318 TD_DELAY_INT(0) |
chris 0:3e7d2baed4b4 319 td_toggle |
chris 0:3e7d2baed4b4 320 TD_CC);
chris 0:3e7d2baed4b4 321 TDTail->Control = 0;
chris 0:3e7d2baed4b4 322 TDHead->CurrBufPtr = (USB_INT32U) buffer;
chris 0:3e7d2baed4b4 323 TDTail->CurrBufPtr = 0;
chris 0:3e7d2baed4b4 324 TDHead->Next = (USB_INT32U) TDTail;
chris 0:3e7d2baed4b4 325 TDTail->Next = 0;
chris 0:3e7d2baed4b4 326 TDHead->BufEnd = (USB_INT32U)(buffer + (buffer_len - 1));
chris 0:3e7d2baed4b4 327 TDTail->BufEnd = 0;
chris 0:3e7d2baed4b4 328
chris 0:3e7d2baed4b4 329 ed->HeadTd = (USB_INT32U)TDHead | ((ed->HeadTd) & 0x00000002);
chris 0:3e7d2baed4b4 330 ed->TailTd = (USB_INT32U)TDTail;
chris 0:3e7d2baed4b4 331 ed->Next = 0;
chris 0:3e7d2baed4b4 332
chris 0:3e7d2baed4b4 333 if (ed == EDCtrl) {
chris 0:3e7d2baed4b4 334 LPC_USB->HcControlHeadED = (USB_INT32U)ed;
chris 0:3e7d2baed4b4 335 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_CLF;
chris 0:3e7d2baed4b4 336 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_CLE;
chris 0:3e7d2baed4b4 337 } else {
chris 0:3e7d2baed4b4 338 LPC_USB->HcBulkHeadED = (USB_INT32U)ed;
chris 0:3e7d2baed4b4 339 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_BLF;
chris 0:3e7d2baed4b4 340 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_BLE;
chris 0:3e7d2baed4b4 341 }
chris 0:3e7d2baed4b4 342
chris 0:3e7d2baed4b4 343 Host_WDHWait();
chris 0:3e7d2baed4b4 344
chris 0:3e7d2baed4b4 345 // if (!(TDHead->Control & 0xF0000000)) {
chris 0:3e7d2baed4b4 346 if (!HOST_TDControlStatus) {
chris 0:3e7d2baed4b4 347 return (OK);
chris 0:3e7d2baed4b4 348 } else {
chris 0:3e7d2baed4b4 349 return (ERR_TD_FAIL);
chris 0:3e7d2baed4b4 350 }
chris 0:3e7d2baed4b4 351 }
chris 0:3e7d2baed4b4 352
chris 0:3e7d2baed4b4 353 /*
chris 0:3e7d2baed4b4 354 **************************************************************************************************************
chris 0:3e7d2baed4b4 355 * ENUMERATE THE DEVICE
chris 0:3e7d2baed4b4 356 *
chris 0:3e7d2baed4b4 357 * Description: This function is used to enumerate the device connected
chris 0:3e7d2baed4b4 358 *
chris 0:3e7d2baed4b4 359 * Arguments : None
chris 0:3e7d2baed4b4 360 *
chris 0:3e7d2baed4b4 361 * Returns : None
chris 0:3e7d2baed4b4 362 *
chris 0:3e7d2baed4b4 363 **************************************************************************************************************
chris 0:3e7d2baed4b4 364 */
chris 0:3e7d2baed4b4 365
chris 0:3e7d2baed4b4 366 USB_INT32S Host_EnumDev (void)
chris 0:3e7d2baed4b4 367 {
chris 0:3e7d2baed4b4 368 USB_INT32S rc;
chris 0:3e7d2baed4b4 369
chris 0:3e7d2baed4b4 370 PRINT_Log("Connect a Mass Storage device\n");
chris 0:3e7d2baed4b4 371 while (!HOST_RhscIntr)
chris 0:3e7d2baed4b4 372 __WFI();
chris 0:3e7d2baed4b4 373 Host_DelayMS(100); /* USB 2.0 spec says atleast 50ms delay beore port reset */
chris 0:3e7d2baed4b4 374 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
chris 0:3e7d2baed4b4 375 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
chris 0:3e7d2baed4b4 376 __WFI(); // Wait for port reset to complete...
chris 0:3e7d2baed4b4 377 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
chris 0:3e7d2baed4b4 378 Host_DelayMS(200); /* Wait for 100 MS after port reset */
chris 0:3e7d2baed4b4 379
chris 0:3e7d2baed4b4 380 EDCtrl->Control = 8 << 16; /* Put max pkt size = 8 */
chris 0:3e7d2baed4b4 381 /* Read first 8 bytes of device desc */
chris 0:3e7d2baed4b4 382 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
chris 0:3e7d2baed4b4 383 if (rc != OK) {
chris 0:3e7d2baed4b4 384 PRINT_Err(rc);
chris 0:3e7d2baed4b4 385 return (rc);
chris 0:3e7d2baed4b4 386 }
chris 0:3e7d2baed4b4 387 EDCtrl->Control = TDBuffer[7] << 16; /* Get max pkt size of endpoint 0 */
chris 0:3e7d2baed4b4 388 rc = HOST_SET_ADDRESS(1); /* Set the device address to 1 */
chris 0:3e7d2baed4b4 389 if (rc != OK) {
chris 0:3e7d2baed4b4 390 PRINT_Err(rc);
chris 0:3e7d2baed4b4 391 return (rc);
chris 0:3e7d2baed4b4 392 }
chris 0:3e7d2baed4b4 393 Host_DelayMS(2);
chris 0:3e7d2baed4b4 394 EDCtrl->Control = (EDCtrl->Control) | 1; /* Modify control pipe with address 1 */
chris 0:3e7d2baed4b4 395 /* Get the configuration descriptor */
chris 0:3e7d2baed4b4 396 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
chris 0:3e7d2baed4b4 397 if (rc != OK) {
chris 0:3e7d2baed4b4 398 PRINT_Err(rc);
chris 0:3e7d2baed4b4 399 return (rc);
chris 0:3e7d2baed4b4 400 }
chris 0:3e7d2baed4b4 401 /* Get the first configuration data */
chris 0:3e7d2baed4b4 402 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
chris 0:3e7d2baed4b4 403 if (rc != OK) {
chris 0:3e7d2baed4b4 404 PRINT_Err(rc);
chris 0:3e7d2baed4b4 405 return (rc);
chris 0:3e7d2baed4b4 406 }
chris 0:3e7d2baed4b4 407 rc = MS_ParseConfiguration(); /* Parse the configuration */
chris 0:3e7d2baed4b4 408 if (rc != OK) {
chris 0:3e7d2baed4b4 409 PRINT_Err(rc);
chris 0:3e7d2baed4b4 410 return (rc);
chris 0:3e7d2baed4b4 411 }
chris 0:3e7d2baed4b4 412 rc = USBH_SET_CONFIGURATION(1); /* Select device configuration 1 */
chris 0:3e7d2baed4b4 413 if (rc != OK) {
chris 0:3e7d2baed4b4 414 PRINT_Err(rc);
chris 0:3e7d2baed4b4 415 }
chris 0:3e7d2baed4b4 416 Host_DelayMS(100); /* Some devices may require this delay */
chris 0:3e7d2baed4b4 417 return (rc);
chris 0:3e7d2baed4b4 418 }
chris 0:3e7d2baed4b4 419
chris 0:3e7d2baed4b4 420 /*
chris 0:3e7d2baed4b4 421 **************************************************************************************************************
chris 0:3e7d2baed4b4 422 * RECEIVE THE CONTROL INFORMATION
chris 0:3e7d2baed4b4 423 *
chris 0:3e7d2baed4b4 424 * Description: This function is used to receive the control information
chris 0:3e7d2baed4b4 425 *
chris 0:3e7d2baed4b4 426 * Arguments : bm_request_type
chris 0:3e7d2baed4b4 427 * b_request
chris 0:3e7d2baed4b4 428 * w_value
chris 0:3e7d2baed4b4 429 * w_index
chris 0:3e7d2baed4b4 430 * w_length
chris 0:3e7d2baed4b4 431 * buffer
chris 0:3e7d2baed4b4 432 *
chris 0:3e7d2baed4b4 433 * Returns : OK if Success
chris 0:3e7d2baed4b4 434 * ERROR if Failed
chris 0:3e7d2baed4b4 435 *
chris 0:3e7d2baed4b4 436 **************************************************************************************************************
chris 0:3e7d2baed4b4 437 */
chris 0:3e7d2baed4b4 438
chris 0:3e7d2baed4b4 439 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
chris 0:3e7d2baed4b4 440 USB_INT08U b_request,
chris 0:3e7d2baed4b4 441 USB_INT16U w_value,
chris 0:3e7d2baed4b4 442 USB_INT16U w_index,
chris 0:3e7d2baed4b4 443 USB_INT16U w_length,
chris 0:3e7d2baed4b4 444 volatile USB_INT08U *buffer)
chris 0:3e7d2baed4b4 445 {
chris 0:3e7d2baed4b4 446 USB_INT32S rc;
chris 0:3e7d2baed4b4 447
chris 0:3e7d2baed4b4 448
chris 0:3e7d2baed4b4 449 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
chris 0:3e7d2baed4b4 450 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
chris 0:3e7d2baed4b4 451 if (rc == OK) {
chris 0:3e7d2baed4b4 452 if (w_length) {
chris 0:3e7d2baed4b4 453 rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
chris 0:3e7d2baed4b4 454 }
chris 0:3e7d2baed4b4 455 if (rc == OK) {
chris 0:3e7d2baed4b4 456 rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
chris 0:3e7d2baed4b4 457 }
chris 0:3e7d2baed4b4 458 }
chris 0:3e7d2baed4b4 459 return (rc);
chris 0:3e7d2baed4b4 460 }
chris 0:3e7d2baed4b4 461
chris 0:3e7d2baed4b4 462 /*
chris 0:3e7d2baed4b4 463 **************************************************************************************************************
chris 0:3e7d2baed4b4 464 * SEND THE CONTROL INFORMATION
chris 0:3e7d2baed4b4 465 *
chris 0:3e7d2baed4b4 466 * Description: This function is used to send the control information
chris 0:3e7d2baed4b4 467 *
chris 0:3e7d2baed4b4 468 * Arguments : None
chris 0:3e7d2baed4b4 469 *
chris 0:3e7d2baed4b4 470 * Returns : OK if Success
chris 0:3e7d2baed4b4 471 * ERR_INVALID_BOOTSIG if Failed
chris 0:3e7d2baed4b4 472 *
chris 0:3e7d2baed4b4 473 **************************************************************************************************************
chris 0:3e7d2baed4b4 474 */
chris 0:3e7d2baed4b4 475
chris 0:3e7d2baed4b4 476 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
chris 0:3e7d2baed4b4 477 USB_INT08U b_request,
chris 0:3e7d2baed4b4 478 USB_INT16U w_value,
chris 0:3e7d2baed4b4 479 USB_INT16U w_index,
chris 0:3e7d2baed4b4 480 USB_INT16U w_length,
chris 0:3e7d2baed4b4 481 volatile USB_INT08U *buffer)
chris 0:3e7d2baed4b4 482 {
chris 0:3e7d2baed4b4 483 USB_INT32S rc;
chris 0:3e7d2baed4b4 484
chris 0:3e7d2baed4b4 485
chris 0:3e7d2baed4b4 486 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
chris 0:3e7d2baed4b4 487
chris 0:3e7d2baed4b4 488 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
chris 0:3e7d2baed4b4 489 if (rc == OK) {
chris 0:3e7d2baed4b4 490 if (w_length) {
chris 0:3e7d2baed4b4 491 rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
chris 0:3e7d2baed4b4 492 }
chris 0:3e7d2baed4b4 493 if (rc == OK) {
chris 0:3e7d2baed4b4 494 rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
chris 0:3e7d2baed4b4 495 }
chris 0:3e7d2baed4b4 496 }
chris 0:3e7d2baed4b4 497 return (rc);
chris 0:3e7d2baed4b4 498 }
chris 0:3e7d2baed4b4 499
chris 0:3e7d2baed4b4 500 /*
chris 0:3e7d2baed4b4 501 **************************************************************************************************************
chris 0:3e7d2baed4b4 502 * FILL SETUP PACKET
chris 0:3e7d2baed4b4 503 *
chris 0:3e7d2baed4b4 504 * Description: This function is used to fill the setup packet
chris 0:3e7d2baed4b4 505 *
chris 0:3e7d2baed4b4 506 * Arguments : None
chris 0:3e7d2baed4b4 507 *
chris 0:3e7d2baed4b4 508 * Returns : OK if Success
chris 0:3e7d2baed4b4 509 * ERR_INVALID_BOOTSIG if Failed
chris 0:3e7d2baed4b4 510 *
chris 0:3e7d2baed4b4 511 **************************************************************************************************************
chris 0:3e7d2baed4b4 512 */
chris 0:3e7d2baed4b4 513
chris 0:3e7d2baed4b4 514 void Host_FillSetup (USB_INT08U bm_request_type,
chris 0:3e7d2baed4b4 515 USB_INT08U b_request,
chris 0:3e7d2baed4b4 516 USB_INT16U w_value,
chris 0:3e7d2baed4b4 517 USB_INT16U w_index,
chris 0:3e7d2baed4b4 518 USB_INT16U w_length)
chris 0:3e7d2baed4b4 519 {
chris 0:3e7d2baed4b4 520 int i;
chris 0:3e7d2baed4b4 521 for (i=0;i<w_length;i++)
chris 0:3e7d2baed4b4 522 TDBuffer[i] = 0;
chris 0:3e7d2baed4b4 523
chris 0:3e7d2baed4b4 524 TDBuffer[0] = bm_request_type;
chris 0:3e7d2baed4b4 525 TDBuffer[1] = b_request;
chris 0:3e7d2baed4b4 526 WriteLE16U(&TDBuffer[2], w_value);
chris 0:3e7d2baed4b4 527 WriteLE16U(&TDBuffer[4], w_index);
chris 0:3e7d2baed4b4 528 WriteLE16U(&TDBuffer[6], w_length);
chris 0:3e7d2baed4b4 529 }
chris 0:3e7d2baed4b4 530
chris 0:3e7d2baed4b4 531
chris 0:3e7d2baed4b4 532
chris 0:3e7d2baed4b4 533 /*
chris 0:3e7d2baed4b4 534 **************************************************************************************************************
chris 0:3e7d2baed4b4 535 * INITIALIZE THE TRANSFER DESCRIPTOR
chris 0:3e7d2baed4b4 536 *
chris 0:3e7d2baed4b4 537 * Description: This function initializes transfer descriptor
chris 0:3e7d2baed4b4 538 *
chris 0:3e7d2baed4b4 539 * Arguments : Pointer to TD structure
chris 0:3e7d2baed4b4 540 *
chris 0:3e7d2baed4b4 541 * Returns : None
chris 0:3e7d2baed4b4 542 *
chris 0:3e7d2baed4b4 543 **************************************************************************************************************
chris 0:3e7d2baed4b4 544 */
chris 0:3e7d2baed4b4 545
chris 0:3e7d2baed4b4 546 void Host_TDInit (volatile HCTD *td)
chris 0:3e7d2baed4b4 547 {
chris 0:3e7d2baed4b4 548
chris 0:3e7d2baed4b4 549 td->Control = 0;
chris 0:3e7d2baed4b4 550 td->CurrBufPtr = 0;
chris 0:3e7d2baed4b4 551 td->Next = 0;
chris 0:3e7d2baed4b4 552 td->BufEnd = 0;
chris 0:3e7d2baed4b4 553 }
chris 0:3e7d2baed4b4 554
chris 0:3e7d2baed4b4 555 /*
chris 0:3e7d2baed4b4 556 **************************************************************************************************************
chris 0:3e7d2baed4b4 557 * INITIALIZE THE ENDPOINT DESCRIPTOR
chris 0:3e7d2baed4b4 558 *
chris 0:3e7d2baed4b4 559 * Description: This function initializes endpoint descriptor
chris 0:3e7d2baed4b4 560 *
chris 0:3e7d2baed4b4 561 * Arguments : Pointer to ED strcuture
chris 0:3e7d2baed4b4 562 *
chris 0:3e7d2baed4b4 563 * Returns : None
chris 0:3e7d2baed4b4 564 *
chris 0:3e7d2baed4b4 565 **************************************************************************************************************
chris 0:3e7d2baed4b4 566 */
chris 0:3e7d2baed4b4 567
chris 0:3e7d2baed4b4 568 void Host_EDInit (volatile HCED *ed)
chris 0:3e7d2baed4b4 569 {
chris 0:3e7d2baed4b4 570
chris 0:3e7d2baed4b4 571 ed->Control = 0;
chris 0:3e7d2baed4b4 572 ed->TailTd = 0;
chris 0:3e7d2baed4b4 573 ed->HeadTd = 0;
chris 0:3e7d2baed4b4 574 ed->Next = 0;
chris 0:3e7d2baed4b4 575 }
chris 0:3e7d2baed4b4 576
chris 0:3e7d2baed4b4 577 /*
chris 0:3e7d2baed4b4 578 **************************************************************************************************************
chris 0:3e7d2baed4b4 579 * INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
chris 0:3e7d2baed4b4 580 *
chris 0:3e7d2baed4b4 581 * Description: This function initializes host controller communications area
chris 0:3e7d2baed4b4 582 *
chris 0:3e7d2baed4b4 583 * Arguments : Pointer to HCCA
chris 0:3e7d2baed4b4 584 *
chris 0:3e7d2baed4b4 585 * Returns :
chris 0:3e7d2baed4b4 586 *
chris 0:3e7d2baed4b4 587 **************************************************************************************************************
chris 0:3e7d2baed4b4 588 */
chris 0:3e7d2baed4b4 589
chris 0:3e7d2baed4b4 590 void Host_HCCAInit (volatile HCCA *hcca)
chris 0:3e7d2baed4b4 591 {
chris 0:3e7d2baed4b4 592 USB_INT32U i;
chris 0:3e7d2baed4b4 593
chris 0:3e7d2baed4b4 594
chris 0:3e7d2baed4b4 595 for (i = 0; i < 32; i++) {
chris 0:3e7d2baed4b4 596
chris 0:3e7d2baed4b4 597 hcca->IntTable[i] = 0;
chris 0:3e7d2baed4b4 598 hcca->FrameNumber = 0;
chris 0:3e7d2baed4b4 599 hcca->DoneHead = 0;
chris 0:3e7d2baed4b4 600 }
chris 0:3e7d2baed4b4 601
chris 0:3e7d2baed4b4 602 }
chris 0:3e7d2baed4b4 603
chris 0:3e7d2baed4b4 604 /*
chris 0:3e7d2baed4b4 605 **************************************************************************************************************
chris 0:3e7d2baed4b4 606 * WAIT FOR WDH INTERRUPT
chris 0:3e7d2baed4b4 607 *
chris 0:3e7d2baed4b4 608 * Description: This function is infinite loop which breaks when ever a WDH interrupt rises
chris 0:3e7d2baed4b4 609 *
chris 0:3e7d2baed4b4 610 * Arguments : None
chris 0:3e7d2baed4b4 611 *
chris 0:3e7d2baed4b4 612 * Returns : None
chris 0:3e7d2baed4b4 613 *
chris 0:3e7d2baed4b4 614 **************************************************************************************************************
chris 0:3e7d2baed4b4 615 */
chris 0:3e7d2baed4b4 616
chris 0:3e7d2baed4b4 617 void Host_WDHWait (void)
chris 0:3e7d2baed4b4 618 {
chris 1:a82ee02f2e91 619 while (!HOST_WdhIntr) {
chris 1:a82ee02f2e91 620 ;
chris 1:a82ee02f2e91 621 }
chris 0:3e7d2baed4b4 622 HOST_WdhIntr = 0;
chris 0:3e7d2baed4b4 623 }
chris 0:3e7d2baed4b4 624
chris 1:a82ee02f2e91 625
chris 1:a82ee02f2e91 626
chris 1:a82ee02f2e91 627
chris 1:a82ee02f2e91 628
chris 1:a82ee02f2e91 629
chris 1:a82ee02f2e91 630
chris 1:a82ee02f2e91 631
chris 0:3e7d2baed4b4 632 /*
chris 0:3e7d2baed4b4 633 **************************************************************************************************************
chris 0:3e7d2baed4b4 634 * READ LE 32U
chris 0:3e7d2baed4b4 635 *
chris 0:3e7d2baed4b4 636 * Description: This function is used to read an unsigned integer from a character buffer in the platform
chris 0:3e7d2baed4b4 637 * containing little endian processor
chris 0:3e7d2baed4b4 638 *
chris 0:3e7d2baed4b4 639 * Arguments : pmem Pointer to the character buffer
chris 0:3e7d2baed4b4 640 *
chris 0:3e7d2baed4b4 641 * Returns : val Unsigned integer
chris 0:3e7d2baed4b4 642 *
chris 0:3e7d2baed4b4 643 **************************************************************************************************************
chris 0:3e7d2baed4b4 644 */
chris 0:3e7d2baed4b4 645
chris 0:3e7d2baed4b4 646 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem)
chris 0:3e7d2baed4b4 647 {
chris 0:3e7d2baed4b4 648 USB_INT32U val = *(USB_INT32U*)pmem;
chris 0:3e7d2baed4b4 649 #ifdef __BIG_ENDIAN
chris 0:3e7d2baed4b4 650 return __REV(val);
chris 0:3e7d2baed4b4 651 #else
chris 0:3e7d2baed4b4 652 return val;
chris 0:3e7d2baed4b4 653 #endif
chris 0:3e7d2baed4b4 654 }
chris 0:3e7d2baed4b4 655
chris 0:3e7d2baed4b4 656 /*
chris 0:3e7d2baed4b4 657 **************************************************************************************************************
chris 0:3e7d2baed4b4 658 * WRITE LE 32U
chris 0:3e7d2baed4b4 659 *
chris 0:3e7d2baed4b4 660 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
chris 0:3e7d2baed4b4 661 * containing little endian processor.
chris 0:3e7d2baed4b4 662 *
chris 0:3e7d2baed4b4 663 * Arguments : pmem Pointer to the charecter buffer
chris 0:3e7d2baed4b4 664 * val Integer value to be placed in the charecter buffer
chris 0:3e7d2baed4b4 665 *
chris 0:3e7d2baed4b4 666 * Returns : None
chris 0:3e7d2baed4b4 667 *
chris 0:3e7d2baed4b4 668 **************************************************************************************************************
chris 0:3e7d2baed4b4 669 */
chris 0:3e7d2baed4b4 670
chris 0:3e7d2baed4b4 671 void WriteLE32U (volatile USB_INT08U *pmem,
chris 0:3e7d2baed4b4 672 USB_INT32U val)
chris 0:3e7d2baed4b4 673 {
chris 0:3e7d2baed4b4 674 #ifdef __BIG_ENDIAN
chris 0:3e7d2baed4b4 675 *(USB_INT32U*)pmem = __REV(val);
chris 0:3e7d2baed4b4 676 #else
chris 0:3e7d2baed4b4 677 *(USB_INT32U*)pmem = val;
chris 0:3e7d2baed4b4 678 #endif
chris 0:3e7d2baed4b4 679 }
chris 0:3e7d2baed4b4 680
chris 0:3e7d2baed4b4 681 /*
chris 0:3e7d2baed4b4 682 **************************************************************************************************************
chris 0:3e7d2baed4b4 683 * READ LE 16U
chris 0:3e7d2baed4b4 684 *
chris 0:3e7d2baed4b4 685 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
chris 0:3e7d2baed4b4 686 * containing little endian processor
chris 0:3e7d2baed4b4 687 *
chris 0:3e7d2baed4b4 688 * Arguments : pmem Pointer to the charecter buffer
chris 0:3e7d2baed4b4 689 *
chris 0:3e7d2baed4b4 690 * Returns : val Unsigned short integer
chris 0:3e7d2baed4b4 691 *
chris 0:3e7d2baed4b4 692 **************************************************************************************************************
chris 0:3e7d2baed4b4 693 */
chris 0:3e7d2baed4b4 694
chris 0:3e7d2baed4b4 695 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem)
chris 0:3e7d2baed4b4 696 {
chris 0:3e7d2baed4b4 697 USB_INT16U val = *(USB_INT16U*)pmem;
chris 0:3e7d2baed4b4 698 #ifdef __BIG_ENDIAN
chris 0:3e7d2baed4b4 699 return __REV16(val);
chris 0:3e7d2baed4b4 700 #else
chris 0:3e7d2baed4b4 701 return val;
chris 0:3e7d2baed4b4 702 #endif
chris 0:3e7d2baed4b4 703 }
chris 0:3e7d2baed4b4 704
chris 0:3e7d2baed4b4 705 /*
chris 0:3e7d2baed4b4 706 **************************************************************************************************************
chris 0:3e7d2baed4b4 707 * WRITE LE 16U
chris 0:3e7d2baed4b4 708 *
chris 0:3e7d2baed4b4 709 * Description: This function is used to write an unsigned short integer into a charecter buffer in the
chris 0:3e7d2baed4b4 710 * platform containing little endian processor
chris 0:3e7d2baed4b4 711 *
chris 0:3e7d2baed4b4 712 * Arguments : pmem Pointer to the charecter buffer
chris 0:3e7d2baed4b4 713 * val Value to be placed in the charecter buffer
chris 0:3e7d2baed4b4 714 *
chris 0:3e7d2baed4b4 715 * Returns : None
chris 0:3e7d2baed4b4 716 *
chris 0:3e7d2baed4b4 717 **************************************************************************************************************
chris 0:3e7d2baed4b4 718 */
chris 0:3e7d2baed4b4 719
chris 0:3e7d2baed4b4 720 void WriteLE16U (volatile USB_INT08U *pmem,
chris 0:3e7d2baed4b4 721 USB_INT16U val)
chris 0:3e7d2baed4b4 722 {
chris 0:3e7d2baed4b4 723 #ifdef __BIG_ENDIAN
chris 0:3e7d2baed4b4 724 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
chris 0:3e7d2baed4b4 725 #else
chris 0:3e7d2baed4b4 726 *(USB_INT16U*)pmem = val;
chris 0:3e7d2baed4b4 727 #endif
chris 0:3e7d2baed4b4 728 }
chris 0:3e7d2baed4b4 729
chris 0:3e7d2baed4b4 730 /*
chris 0:3e7d2baed4b4 731 **************************************************************************************************************
chris 0:3e7d2baed4b4 732 * READ BE 32U
chris 0:3e7d2baed4b4 733 *
chris 0:3e7d2baed4b4 734 * Description: This function is used to read an unsigned integer from a charecter buffer in the platform
chris 0:3e7d2baed4b4 735 * containing big endian processor
chris 0:3e7d2baed4b4 736 *
chris 0:3e7d2baed4b4 737 * Arguments : pmem Pointer to the charecter buffer
chris 0:3e7d2baed4b4 738 *
chris 0:3e7d2baed4b4 739 * Returns : val Unsigned integer
chris 0:3e7d2baed4b4 740 *
chris 0:3e7d2baed4b4 741 **************************************************************************************************************
chris 0:3e7d2baed4b4 742 */
chris 0:3e7d2baed4b4 743
chris 0:3e7d2baed4b4 744 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem)
chris 0:3e7d2baed4b4 745 {
chris 0:3e7d2baed4b4 746 USB_INT32U val = *(USB_INT32U*)pmem;
chris 0:3e7d2baed4b4 747 #ifdef __BIG_ENDIAN
chris 0:3e7d2baed4b4 748 return val;
chris 0:3e7d2baed4b4 749 #else
chris 0:3e7d2baed4b4 750 return __REV(val);
chris 0:3e7d2baed4b4 751 #endif
chris 0:3e7d2baed4b4 752 }
chris 0:3e7d2baed4b4 753
chris 0:3e7d2baed4b4 754 /*
chris 0:3e7d2baed4b4 755 **************************************************************************************************************
chris 0:3e7d2baed4b4 756 * WRITE BE 32U
chris 0:3e7d2baed4b4 757 *
chris 0:3e7d2baed4b4 758 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
chris 0:3e7d2baed4b4 759 * containing big endian processor
chris 0:3e7d2baed4b4 760 *
chris 0:3e7d2baed4b4 761 * Arguments : pmem Pointer to the charecter buffer
chris 0:3e7d2baed4b4 762 * val Value to be placed in the charecter buffer
chris 0:3e7d2baed4b4 763 *
chris 0:3e7d2baed4b4 764 * Returns : None
chris 0:3e7d2baed4b4 765 *
chris 0:3e7d2baed4b4 766 **************************************************************************************************************
chris 0:3e7d2baed4b4 767 */
chris 0:3e7d2baed4b4 768
chris 0:3e7d2baed4b4 769 void WriteBE32U (volatile USB_INT08U *pmem,
chris 0:3e7d2baed4b4 770 USB_INT32U val)
chris 0:3e7d2baed4b4 771 {
chris 0:3e7d2baed4b4 772 #ifdef __BIG_ENDIAN
chris 0:3e7d2baed4b4 773 *(USB_INT32U*)pmem = val;
chris 0:3e7d2baed4b4 774 #else
chris 0:3e7d2baed4b4 775 *(USB_INT32U*)pmem = __REV(val);
chris 0:3e7d2baed4b4 776 #endif
chris 0:3e7d2baed4b4 777 }
chris 0:3e7d2baed4b4 778
chris 0:3e7d2baed4b4 779 /*
chris 0:3e7d2baed4b4 780 **************************************************************************************************************
chris 0:3e7d2baed4b4 781 * READ BE 16U
chris 0:3e7d2baed4b4 782 *
chris 0:3e7d2baed4b4 783 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
chris 0:3e7d2baed4b4 784 * containing big endian processor
chris 0:3e7d2baed4b4 785 *
chris 0:3e7d2baed4b4 786 * Arguments : pmem Pointer to the charecter buffer
chris 0:3e7d2baed4b4 787 *
chris 0:3e7d2baed4b4 788 * Returns : val Unsigned short integer
chris 0:3e7d2baed4b4 789 *
chris 0:3e7d2baed4b4 790 **************************************************************************************************************
chris 0:3e7d2baed4b4 791 */
chris 0:3e7d2baed4b4 792
chris 0:3e7d2baed4b4 793 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem)
chris 0:3e7d2baed4b4 794 {
chris 0:3e7d2baed4b4 795 USB_INT16U val = *(USB_INT16U*)pmem;
chris 0:3e7d2baed4b4 796 #ifdef __BIG_ENDIAN
chris 0:3e7d2baed4b4 797 return val;
chris 0:3e7d2baed4b4 798 #else
chris 0:3e7d2baed4b4 799 return __REV16(val);
chris 0:3e7d2baed4b4 800 #endif
chris 0:3e7d2baed4b4 801 }
chris 0:3e7d2baed4b4 802
chris 0:3e7d2baed4b4 803 /*
chris 0:3e7d2baed4b4 804 **************************************************************************************************************
chris 0:3e7d2baed4b4 805 * WRITE BE 16U
chris 0:3e7d2baed4b4 806 *
chris 0:3e7d2baed4b4 807 * Description: This function is used to write an unsigned short integer into the charecter buffer in the
chris 0:3e7d2baed4b4 808 * platform containing big endian processor
chris 0:3e7d2baed4b4 809 *
chris 0:3e7d2baed4b4 810 * Arguments : pmem Pointer to the charecter buffer
chris 0:3e7d2baed4b4 811 * val Value to be placed in the charecter buffer
chris 0:3e7d2baed4b4 812 *
chris 0:3e7d2baed4b4 813 * Returns : None
chris 0:3e7d2baed4b4 814 *
chris 0:3e7d2baed4b4 815 **************************************************************************************************************
chris 0:3e7d2baed4b4 816 */
chris 0:3e7d2baed4b4 817
chris 0:3e7d2baed4b4 818 void WriteBE16U (volatile USB_INT08U *pmem,
chris 0:3e7d2baed4b4 819 USB_INT16U val)
chris 0:3e7d2baed4b4 820 {
chris 0:3e7d2baed4b4 821 #ifdef __BIG_ENDIAN
chris 0:3e7d2baed4b4 822 *(USB_INT16U*)pmem = val;
chris 0:3e7d2baed4b4 823 #else
chris 0:3e7d2baed4b4 824 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
chris 0:3e7d2baed4b4 825 #endif
chris 0:3e7d2baed4b4 826 }