Sertel_Srinath Gopalan / TARGET_LPC1768_N

LPC1768

core_cm4_simd.h@0:ae306d3f6076, 2014-11-19 (annotated)

Committer:
mrsoundhar
Date:
Wed Nov 19 05:50:22 2014 +0000
Revision:
0:ae306d3f6076
publish

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mrsoundhar 0:ae306d3f6076 1 /**************************************************************************//**
mrsoundhar 0:ae306d3f6076 2 * @file core_cm4_simd.h
mrsoundhar 0:ae306d3f6076 3 * @brief CMSIS Cortex-M4 SIMD Header File
mrsoundhar 0:ae306d3f6076 4 * @version V3.20
mrsoundhar 0:ae306d3f6076 5 * @date 25. February 2013
mrsoundhar 0:ae306d3f6076 6 *
mrsoundhar 0:ae306d3f6076 7 * @note
mrsoundhar 0:ae306d3f6076 8 *
mrsoundhar 0:ae306d3f6076 9 ******************************************************************************/
mrsoundhar 0:ae306d3f6076 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mrsoundhar 0:ae306d3f6076 11
mrsoundhar 0:ae306d3f6076 12 All rights reserved.
mrsoundhar 0:ae306d3f6076 13 Redistribution and use in source and binary forms, with or without
mrsoundhar 0:ae306d3f6076 14 modification, are permitted provided that the following conditions are met:
mrsoundhar 0:ae306d3f6076 15 - Redistributions of source code must retain the above copyright
mrsoundhar 0:ae306d3f6076 16 notice, this list of conditions and the following disclaimer.
mrsoundhar 0:ae306d3f6076 17 - Redistributions in binary form must reproduce the above copyright
mrsoundhar 0:ae306d3f6076 18 notice, this list of conditions and the following disclaimer in the
mrsoundhar 0:ae306d3f6076 19 documentation and/or other materials provided with the distribution.
mrsoundhar 0:ae306d3f6076 20 - Neither the name of ARM nor the names of its contributors may be used
mrsoundhar 0:ae306d3f6076 21 to endorse or promote products derived from this software without
mrsoundhar 0:ae306d3f6076 22 specific prior written permission.
mrsoundhar 0:ae306d3f6076 23 *
mrsoundhar 0:ae306d3f6076 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mrsoundhar 0:ae306d3f6076 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mrsoundhar 0:ae306d3f6076 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mrsoundhar 0:ae306d3f6076 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mrsoundhar 0:ae306d3f6076 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mrsoundhar 0:ae306d3f6076 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mrsoundhar 0:ae306d3f6076 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mrsoundhar 0:ae306d3f6076 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mrsoundhar 0:ae306d3f6076 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mrsoundhar 0:ae306d3f6076 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mrsoundhar 0:ae306d3f6076 34 POSSIBILITY OF SUCH DAMAGE.
mrsoundhar 0:ae306d3f6076 35 ---------------------------------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 36
mrsoundhar 0:ae306d3f6076 37
mrsoundhar 0:ae306d3f6076 38 #ifdef __cplusplus
mrsoundhar 0:ae306d3f6076 39 extern "C" {
mrsoundhar 0:ae306d3f6076 40 #endif
mrsoundhar 0:ae306d3f6076 41
mrsoundhar 0:ae306d3f6076 42 #ifndef __CORE_CM4_SIMD_H
mrsoundhar 0:ae306d3f6076 43 #define __CORE_CM4_SIMD_H
mrsoundhar 0:ae306d3f6076 44
mrsoundhar 0:ae306d3f6076 45
mrsoundhar 0:ae306d3f6076 46 /*******************************************************************************
mrsoundhar 0:ae306d3f6076 47 * Hardware Abstraction Layer
mrsoundhar 0:ae306d3f6076 48 ******************************************************************************/
mrsoundhar 0:ae306d3f6076 49
mrsoundhar 0:ae306d3f6076 50
mrsoundhar 0:ae306d3f6076 51 /* ################### Compiler specific Intrinsics ########################### */
mrsoundhar 0:ae306d3f6076 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
mrsoundhar 0:ae306d3f6076 53 Access to dedicated SIMD instructions
mrsoundhar 0:ae306d3f6076 54 @{
mrsoundhar 0:ae306d3f6076 55 */
mrsoundhar 0:ae306d3f6076 56
mrsoundhar 0:ae306d3f6076 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mrsoundhar 0:ae306d3f6076 58 /* ARM armcc specific functions */
mrsoundhar 0:ae306d3f6076 59
mrsoundhar 0:ae306d3f6076 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 61 #define __SADD8 __sadd8
mrsoundhar 0:ae306d3f6076 62 #define __QADD8 __qadd8
mrsoundhar 0:ae306d3f6076 63 #define __SHADD8 __shadd8
mrsoundhar 0:ae306d3f6076 64 #define __UADD8 __uadd8
mrsoundhar 0:ae306d3f6076 65 #define __UQADD8 __uqadd8
mrsoundhar 0:ae306d3f6076 66 #define __UHADD8 __uhadd8
mrsoundhar 0:ae306d3f6076 67 #define __SSUB8 __ssub8
mrsoundhar 0:ae306d3f6076 68 #define __QSUB8 __qsub8
mrsoundhar 0:ae306d3f6076 69 #define __SHSUB8 __shsub8
mrsoundhar 0:ae306d3f6076 70 #define __USUB8 __usub8
mrsoundhar 0:ae306d3f6076 71 #define __UQSUB8 __uqsub8
mrsoundhar 0:ae306d3f6076 72 #define __UHSUB8 __uhsub8
mrsoundhar 0:ae306d3f6076 73 #define __SADD16 __sadd16
mrsoundhar 0:ae306d3f6076 74 #define __QADD16 __qadd16
mrsoundhar 0:ae306d3f6076 75 #define __SHADD16 __shadd16
mrsoundhar 0:ae306d3f6076 76 #define __UADD16 __uadd16
mrsoundhar 0:ae306d3f6076 77 #define __UQADD16 __uqadd16
mrsoundhar 0:ae306d3f6076 78 #define __UHADD16 __uhadd16
mrsoundhar 0:ae306d3f6076 79 #define __SSUB16 __ssub16
mrsoundhar 0:ae306d3f6076 80 #define __QSUB16 __qsub16
mrsoundhar 0:ae306d3f6076 81 #define __SHSUB16 __shsub16
mrsoundhar 0:ae306d3f6076 82 #define __USUB16 __usub16
mrsoundhar 0:ae306d3f6076 83 #define __UQSUB16 __uqsub16
mrsoundhar 0:ae306d3f6076 84 #define __UHSUB16 __uhsub16
mrsoundhar 0:ae306d3f6076 85 #define __SASX __sasx
mrsoundhar 0:ae306d3f6076 86 #define __QASX __qasx
mrsoundhar 0:ae306d3f6076 87 #define __SHASX __shasx
mrsoundhar 0:ae306d3f6076 88 #define __UASX __uasx
mrsoundhar 0:ae306d3f6076 89 #define __UQASX __uqasx
mrsoundhar 0:ae306d3f6076 90 #define __UHASX __uhasx
mrsoundhar 0:ae306d3f6076 91 #define __SSAX __ssax
mrsoundhar 0:ae306d3f6076 92 #define __QSAX __qsax
mrsoundhar 0:ae306d3f6076 93 #define __SHSAX __shsax
mrsoundhar 0:ae306d3f6076 94 #define __USAX __usax
mrsoundhar 0:ae306d3f6076 95 #define __UQSAX __uqsax
mrsoundhar 0:ae306d3f6076 96 #define __UHSAX __uhsax
mrsoundhar 0:ae306d3f6076 97 #define __USAD8 __usad8
mrsoundhar 0:ae306d3f6076 98 #define __USADA8 __usada8
mrsoundhar 0:ae306d3f6076 99 #define __SSAT16 __ssat16
mrsoundhar 0:ae306d3f6076 100 #define __USAT16 __usat16
mrsoundhar 0:ae306d3f6076 101 #define __UXTB16 __uxtb16
mrsoundhar 0:ae306d3f6076 102 #define __UXTAB16 __uxtab16
mrsoundhar 0:ae306d3f6076 103 #define __SXTB16 __sxtb16
mrsoundhar 0:ae306d3f6076 104 #define __SXTAB16 __sxtab16
mrsoundhar 0:ae306d3f6076 105 #define __SMUAD __smuad
mrsoundhar 0:ae306d3f6076 106 #define __SMUADX __smuadx
mrsoundhar 0:ae306d3f6076 107 #define __SMLAD __smlad
mrsoundhar 0:ae306d3f6076 108 #define __SMLADX __smladx
mrsoundhar 0:ae306d3f6076 109 #define __SMLALD __smlald
mrsoundhar 0:ae306d3f6076 110 #define __SMLALDX __smlaldx
mrsoundhar 0:ae306d3f6076 111 #define __SMUSD __smusd
mrsoundhar 0:ae306d3f6076 112 #define __SMUSDX __smusdx
mrsoundhar 0:ae306d3f6076 113 #define __SMLSD __smlsd
mrsoundhar 0:ae306d3f6076 114 #define __SMLSDX __smlsdx
mrsoundhar 0:ae306d3f6076 115 #define __SMLSLD __smlsld
mrsoundhar 0:ae306d3f6076 116 #define __SMLSLDX __smlsldx
mrsoundhar 0:ae306d3f6076 117 #define __SEL __sel
mrsoundhar 0:ae306d3f6076 118 #define __QADD __qadd
mrsoundhar 0:ae306d3f6076 119 #define __QSUB __qsub
mrsoundhar 0:ae306d3f6076 120
mrsoundhar 0:ae306d3f6076 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
mrsoundhar 0:ae306d3f6076 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
mrsoundhar 0:ae306d3f6076 123
mrsoundhar 0:ae306d3f6076 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
mrsoundhar 0:ae306d3f6076 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
mrsoundhar 0:ae306d3f6076 126
mrsoundhar 0:ae306d3f6076 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
mrsoundhar 0:ae306d3f6076 128 ((int64_t)(ARG3) << 32) ) >> 32))
mrsoundhar 0:ae306d3f6076 129
mrsoundhar 0:ae306d3f6076 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 131
mrsoundhar 0:ae306d3f6076 132
mrsoundhar 0:ae306d3f6076 133
mrsoundhar 0:ae306d3f6076 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mrsoundhar 0:ae306d3f6076 135 /* IAR iccarm specific functions */
mrsoundhar 0:ae306d3f6076 136
mrsoundhar 0:ae306d3f6076 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 138 #include <cmsis_iar.h>
mrsoundhar 0:ae306d3f6076 139
mrsoundhar 0:ae306d3f6076 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 141
mrsoundhar 0:ae306d3f6076 142
mrsoundhar 0:ae306d3f6076 143
mrsoundhar 0:ae306d3f6076 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mrsoundhar 0:ae306d3f6076 145 /* TI CCS specific functions */
mrsoundhar 0:ae306d3f6076 146
mrsoundhar 0:ae306d3f6076 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 148 #include <cmsis_ccs.h>
mrsoundhar 0:ae306d3f6076 149
mrsoundhar 0:ae306d3f6076 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 151
mrsoundhar 0:ae306d3f6076 152
mrsoundhar 0:ae306d3f6076 153
mrsoundhar 0:ae306d3f6076 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mrsoundhar 0:ae306d3f6076 155 /* GNU gcc specific functions */
mrsoundhar 0:ae306d3f6076 156
mrsoundhar 0:ae306d3f6076 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 159 {
mrsoundhar 0:ae306d3f6076 160 uint32_t result;
mrsoundhar 0:ae306d3f6076 161
mrsoundhar 0:ae306d3f6076 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 163 return(result);
mrsoundhar 0:ae306d3f6076 164 }
mrsoundhar 0:ae306d3f6076 165
mrsoundhar 0:ae306d3f6076 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 167 {
mrsoundhar 0:ae306d3f6076 168 uint32_t result;
mrsoundhar 0:ae306d3f6076 169
mrsoundhar 0:ae306d3f6076 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 171 return(result);
mrsoundhar 0:ae306d3f6076 172 }
mrsoundhar 0:ae306d3f6076 173
mrsoundhar 0:ae306d3f6076 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 175 {
mrsoundhar 0:ae306d3f6076 176 uint32_t result;
mrsoundhar 0:ae306d3f6076 177
mrsoundhar 0:ae306d3f6076 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 179 return(result);
mrsoundhar 0:ae306d3f6076 180 }
mrsoundhar 0:ae306d3f6076 181
mrsoundhar 0:ae306d3f6076 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 183 {
mrsoundhar 0:ae306d3f6076 184 uint32_t result;
mrsoundhar 0:ae306d3f6076 185
mrsoundhar 0:ae306d3f6076 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 187 return(result);
mrsoundhar 0:ae306d3f6076 188 }
mrsoundhar 0:ae306d3f6076 189
mrsoundhar 0:ae306d3f6076 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 191 {
mrsoundhar 0:ae306d3f6076 192 uint32_t result;
mrsoundhar 0:ae306d3f6076 193
mrsoundhar 0:ae306d3f6076 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 195 return(result);
mrsoundhar 0:ae306d3f6076 196 }
mrsoundhar 0:ae306d3f6076 197
mrsoundhar 0:ae306d3f6076 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 199 {
mrsoundhar 0:ae306d3f6076 200 uint32_t result;
mrsoundhar 0:ae306d3f6076 201
mrsoundhar 0:ae306d3f6076 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 203 return(result);
mrsoundhar 0:ae306d3f6076 204 }
mrsoundhar 0:ae306d3f6076 205
mrsoundhar 0:ae306d3f6076 206
mrsoundhar 0:ae306d3f6076 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 208 {
mrsoundhar 0:ae306d3f6076 209 uint32_t result;
mrsoundhar 0:ae306d3f6076 210
mrsoundhar 0:ae306d3f6076 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 212 return(result);
mrsoundhar 0:ae306d3f6076 213 }
mrsoundhar 0:ae306d3f6076 214
mrsoundhar 0:ae306d3f6076 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 216 {
mrsoundhar 0:ae306d3f6076 217 uint32_t result;
mrsoundhar 0:ae306d3f6076 218
mrsoundhar 0:ae306d3f6076 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 220 return(result);
mrsoundhar 0:ae306d3f6076 221 }
mrsoundhar 0:ae306d3f6076 222
mrsoundhar 0:ae306d3f6076 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 224 {
mrsoundhar 0:ae306d3f6076 225 uint32_t result;
mrsoundhar 0:ae306d3f6076 226
mrsoundhar 0:ae306d3f6076 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 228 return(result);
mrsoundhar 0:ae306d3f6076 229 }
mrsoundhar 0:ae306d3f6076 230
mrsoundhar 0:ae306d3f6076 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 232 {
mrsoundhar 0:ae306d3f6076 233 uint32_t result;
mrsoundhar 0:ae306d3f6076 234
mrsoundhar 0:ae306d3f6076 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 236 return(result);
mrsoundhar 0:ae306d3f6076 237 }
mrsoundhar 0:ae306d3f6076 238
mrsoundhar 0:ae306d3f6076 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 240 {
mrsoundhar 0:ae306d3f6076 241 uint32_t result;
mrsoundhar 0:ae306d3f6076 242
mrsoundhar 0:ae306d3f6076 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 244 return(result);
mrsoundhar 0:ae306d3f6076 245 }
mrsoundhar 0:ae306d3f6076 246
mrsoundhar 0:ae306d3f6076 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 248 {
mrsoundhar 0:ae306d3f6076 249 uint32_t result;
mrsoundhar 0:ae306d3f6076 250
mrsoundhar 0:ae306d3f6076 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 252 return(result);
mrsoundhar 0:ae306d3f6076 253 }
mrsoundhar 0:ae306d3f6076 254
mrsoundhar 0:ae306d3f6076 255
mrsoundhar 0:ae306d3f6076 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 257 {
mrsoundhar 0:ae306d3f6076 258 uint32_t result;
mrsoundhar 0:ae306d3f6076 259
mrsoundhar 0:ae306d3f6076 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 261 return(result);
mrsoundhar 0:ae306d3f6076 262 }
mrsoundhar 0:ae306d3f6076 263
mrsoundhar 0:ae306d3f6076 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 265 {
mrsoundhar 0:ae306d3f6076 266 uint32_t result;
mrsoundhar 0:ae306d3f6076 267
mrsoundhar 0:ae306d3f6076 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 269 return(result);
mrsoundhar 0:ae306d3f6076 270 }
mrsoundhar 0:ae306d3f6076 271
mrsoundhar 0:ae306d3f6076 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 273 {
mrsoundhar 0:ae306d3f6076 274 uint32_t result;
mrsoundhar 0:ae306d3f6076 275
mrsoundhar 0:ae306d3f6076 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 277 return(result);
mrsoundhar 0:ae306d3f6076 278 }
mrsoundhar 0:ae306d3f6076 279
mrsoundhar 0:ae306d3f6076 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 281 {
mrsoundhar 0:ae306d3f6076 282 uint32_t result;
mrsoundhar 0:ae306d3f6076 283
mrsoundhar 0:ae306d3f6076 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 285 return(result);
mrsoundhar 0:ae306d3f6076 286 }
mrsoundhar 0:ae306d3f6076 287
mrsoundhar 0:ae306d3f6076 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 289 {
mrsoundhar 0:ae306d3f6076 290 uint32_t result;
mrsoundhar 0:ae306d3f6076 291
mrsoundhar 0:ae306d3f6076 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 293 return(result);
mrsoundhar 0:ae306d3f6076 294 }
mrsoundhar 0:ae306d3f6076 295
mrsoundhar 0:ae306d3f6076 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 297 {
mrsoundhar 0:ae306d3f6076 298 uint32_t result;
mrsoundhar 0:ae306d3f6076 299
mrsoundhar 0:ae306d3f6076 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 301 return(result);
mrsoundhar 0:ae306d3f6076 302 }
mrsoundhar 0:ae306d3f6076 303
mrsoundhar 0:ae306d3f6076 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 305 {
mrsoundhar 0:ae306d3f6076 306 uint32_t result;
mrsoundhar 0:ae306d3f6076 307
mrsoundhar 0:ae306d3f6076 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 309 return(result);
mrsoundhar 0:ae306d3f6076 310 }
mrsoundhar 0:ae306d3f6076 311
mrsoundhar 0:ae306d3f6076 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 313 {
mrsoundhar 0:ae306d3f6076 314 uint32_t result;
mrsoundhar 0:ae306d3f6076 315
mrsoundhar 0:ae306d3f6076 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 317 return(result);
mrsoundhar 0:ae306d3f6076 318 }
mrsoundhar 0:ae306d3f6076 319
mrsoundhar 0:ae306d3f6076 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 321 {
mrsoundhar 0:ae306d3f6076 322 uint32_t result;
mrsoundhar 0:ae306d3f6076 323
mrsoundhar 0:ae306d3f6076 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 325 return(result);
mrsoundhar 0:ae306d3f6076 326 }
mrsoundhar 0:ae306d3f6076 327
mrsoundhar 0:ae306d3f6076 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 329 {
mrsoundhar 0:ae306d3f6076 330 uint32_t result;
mrsoundhar 0:ae306d3f6076 331
mrsoundhar 0:ae306d3f6076 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 333 return(result);
mrsoundhar 0:ae306d3f6076 334 }
mrsoundhar 0:ae306d3f6076 335
mrsoundhar 0:ae306d3f6076 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 337 {
mrsoundhar 0:ae306d3f6076 338 uint32_t result;
mrsoundhar 0:ae306d3f6076 339
mrsoundhar 0:ae306d3f6076 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 341 return(result);
mrsoundhar 0:ae306d3f6076 342 }
mrsoundhar 0:ae306d3f6076 343
mrsoundhar 0:ae306d3f6076 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 345 {
mrsoundhar 0:ae306d3f6076 346 uint32_t result;
mrsoundhar 0:ae306d3f6076 347
mrsoundhar 0:ae306d3f6076 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 349 return(result);
mrsoundhar 0:ae306d3f6076 350 }
mrsoundhar 0:ae306d3f6076 351
mrsoundhar 0:ae306d3f6076 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 353 {
mrsoundhar 0:ae306d3f6076 354 uint32_t result;
mrsoundhar 0:ae306d3f6076 355
mrsoundhar 0:ae306d3f6076 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 357 return(result);
mrsoundhar 0:ae306d3f6076 358 }
mrsoundhar 0:ae306d3f6076 359
mrsoundhar 0:ae306d3f6076 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 361 {
mrsoundhar 0:ae306d3f6076 362 uint32_t result;
mrsoundhar 0:ae306d3f6076 363
mrsoundhar 0:ae306d3f6076 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 365 return(result);
mrsoundhar 0:ae306d3f6076 366 }
mrsoundhar 0:ae306d3f6076 367
mrsoundhar 0:ae306d3f6076 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 369 {
mrsoundhar 0:ae306d3f6076 370 uint32_t result;
mrsoundhar 0:ae306d3f6076 371
mrsoundhar 0:ae306d3f6076 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 373 return(result);
mrsoundhar 0:ae306d3f6076 374 }
mrsoundhar 0:ae306d3f6076 375
mrsoundhar 0:ae306d3f6076 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 377 {
mrsoundhar 0:ae306d3f6076 378 uint32_t result;
mrsoundhar 0:ae306d3f6076 379
mrsoundhar 0:ae306d3f6076 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 381 return(result);
mrsoundhar 0:ae306d3f6076 382 }
mrsoundhar 0:ae306d3f6076 383
mrsoundhar 0:ae306d3f6076 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 385 {
mrsoundhar 0:ae306d3f6076 386 uint32_t result;
mrsoundhar 0:ae306d3f6076 387
mrsoundhar 0:ae306d3f6076 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 389 return(result);
mrsoundhar 0:ae306d3f6076 390 }
mrsoundhar 0:ae306d3f6076 391
mrsoundhar 0:ae306d3f6076 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 393 {
mrsoundhar 0:ae306d3f6076 394 uint32_t result;
mrsoundhar 0:ae306d3f6076 395
mrsoundhar 0:ae306d3f6076 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 397 return(result);
mrsoundhar 0:ae306d3f6076 398 }
mrsoundhar 0:ae306d3f6076 399
mrsoundhar 0:ae306d3f6076 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 401 {
mrsoundhar 0:ae306d3f6076 402 uint32_t result;
mrsoundhar 0:ae306d3f6076 403
mrsoundhar 0:ae306d3f6076 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 405 return(result);
mrsoundhar 0:ae306d3f6076 406 }
mrsoundhar 0:ae306d3f6076 407
mrsoundhar 0:ae306d3f6076 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 409 {
mrsoundhar 0:ae306d3f6076 410 uint32_t result;
mrsoundhar 0:ae306d3f6076 411
mrsoundhar 0:ae306d3f6076 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 413 return(result);
mrsoundhar 0:ae306d3f6076 414 }
mrsoundhar 0:ae306d3f6076 415
mrsoundhar 0:ae306d3f6076 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 417 {
mrsoundhar 0:ae306d3f6076 418 uint32_t result;
mrsoundhar 0:ae306d3f6076 419
mrsoundhar 0:ae306d3f6076 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 421 return(result);
mrsoundhar 0:ae306d3f6076 422 }
mrsoundhar 0:ae306d3f6076 423
mrsoundhar 0:ae306d3f6076 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 425 {
mrsoundhar 0:ae306d3f6076 426 uint32_t result;
mrsoundhar 0:ae306d3f6076 427
mrsoundhar 0:ae306d3f6076 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 429 return(result);
mrsoundhar 0:ae306d3f6076 430 }
mrsoundhar 0:ae306d3f6076 431
mrsoundhar 0:ae306d3f6076 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 433 {
mrsoundhar 0:ae306d3f6076 434 uint32_t result;
mrsoundhar 0:ae306d3f6076 435
mrsoundhar 0:ae306d3f6076 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 437 return(result);
mrsoundhar 0:ae306d3f6076 438 }
mrsoundhar 0:ae306d3f6076 439
mrsoundhar 0:ae306d3f6076 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 441 {
mrsoundhar 0:ae306d3f6076 442 uint32_t result;
mrsoundhar 0:ae306d3f6076 443
mrsoundhar 0:ae306d3f6076 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 445 return(result);
mrsoundhar 0:ae306d3f6076 446 }
mrsoundhar 0:ae306d3f6076 447
mrsoundhar 0:ae306d3f6076 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 449 {
mrsoundhar 0:ae306d3f6076 450 uint32_t result;
mrsoundhar 0:ae306d3f6076 451
mrsoundhar 0:ae306d3f6076 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 453 return(result);
mrsoundhar 0:ae306d3f6076 454 }
mrsoundhar 0:ae306d3f6076 455
mrsoundhar 0:ae306d3f6076 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:ae306d3f6076 457 {
mrsoundhar 0:ae306d3f6076 458 uint32_t result;
mrsoundhar 0:ae306d3f6076 459
mrsoundhar 0:ae306d3f6076 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:ae306d3f6076 461 return(result);
mrsoundhar 0:ae306d3f6076 462 }
mrsoundhar 0:ae306d3f6076 463
mrsoundhar 0:ae306d3f6076 464 #define __SSAT16(ARG1,ARG2) \
mrsoundhar 0:ae306d3f6076 465 ({ \
mrsoundhar 0:ae306d3f6076 466 uint32_t __RES, __ARG1 = (ARG1); \
mrsoundhar 0:ae306d3f6076 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mrsoundhar 0:ae306d3f6076 468 __RES; \
mrsoundhar 0:ae306d3f6076 469 })
mrsoundhar 0:ae306d3f6076 470
mrsoundhar 0:ae306d3f6076 471 #define __USAT16(ARG1,ARG2) \
mrsoundhar 0:ae306d3f6076 472 ({ \
mrsoundhar 0:ae306d3f6076 473 uint32_t __RES, __ARG1 = (ARG1); \
mrsoundhar 0:ae306d3f6076 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mrsoundhar 0:ae306d3f6076 475 __RES; \
mrsoundhar 0:ae306d3f6076 476 })
mrsoundhar 0:ae306d3f6076 477
mrsoundhar 0:ae306d3f6076 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
mrsoundhar 0:ae306d3f6076 479 {
mrsoundhar 0:ae306d3f6076 480 uint32_t result;
mrsoundhar 0:ae306d3f6076 481
mrsoundhar 0:ae306d3f6076 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
mrsoundhar 0:ae306d3f6076 483 return(result);
mrsoundhar 0:ae306d3f6076 484 }
mrsoundhar 0:ae306d3f6076 485
mrsoundhar 0:ae306d3f6076 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 487 {
mrsoundhar 0:ae306d3f6076 488 uint32_t result;
mrsoundhar 0:ae306d3f6076 489
mrsoundhar 0:ae306d3f6076 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 491 return(result);
mrsoundhar 0:ae306d3f6076 492 }
mrsoundhar 0:ae306d3f6076 493
mrsoundhar 0:ae306d3f6076 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
mrsoundhar 0:ae306d3f6076 495 {
mrsoundhar 0:ae306d3f6076 496 uint32_t result;
mrsoundhar 0:ae306d3f6076 497
mrsoundhar 0:ae306d3f6076 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
mrsoundhar 0:ae306d3f6076 499 return(result);
mrsoundhar 0:ae306d3f6076 500 }
mrsoundhar 0:ae306d3f6076 501
mrsoundhar 0:ae306d3f6076 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 503 {
mrsoundhar 0:ae306d3f6076 504 uint32_t result;
mrsoundhar 0:ae306d3f6076 505
mrsoundhar 0:ae306d3f6076 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 507 return(result);
mrsoundhar 0:ae306d3f6076 508 }
mrsoundhar 0:ae306d3f6076 509
mrsoundhar 0:ae306d3f6076 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 511 {
mrsoundhar 0:ae306d3f6076 512 uint32_t result;
mrsoundhar 0:ae306d3f6076 513
mrsoundhar 0:ae306d3f6076 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 515 return(result);
mrsoundhar 0:ae306d3f6076 516 }
mrsoundhar 0:ae306d3f6076 517
mrsoundhar 0:ae306d3f6076 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 519 {
mrsoundhar 0:ae306d3f6076 520 uint32_t result;
mrsoundhar 0:ae306d3f6076 521
mrsoundhar 0:ae306d3f6076 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 523 return(result);
mrsoundhar 0:ae306d3f6076 524 }
mrsoundhar 0:ae306d3f6076 525
mrsoundhar 0:ae306d3f6076 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:ae306d3f6076 527 {
mrsoundhar 0:ae306d3f6076 528 uint32_t result;
mrsoundhar 0:ae306d3f6076 529
mrsoundhar 0:ae306d3f6076 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:ae306d3f6076 531 return(result);
mrsoundhar 0:ae306d3f6076 532 }
mrsoundhar 0:ae306d3f6076 533
mrsoundhar 0:ae306d3f6076 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:ae306d3f6076 535 {
mrsoundhar 0:ae306d3f6076 536 uint32_t result;
mrsoundhar 0:ae306d3f6076 537
mrsoundhar 0:ae306d3f6076 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:ae306d3f6076 539 return(result);
mrsoundhar 0:ae306d3f6076 540 }
mrsoundhar 0:ae306d3f6076 541
mrsoundhar 0:ae306d3f6076 542 #define __SMLALD(ARG1,ARG2,ARG3) \
mrsoundhar 0:ae306d3f6076 543 ({ \
mrsoundhar 0:ae306d3f6076 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
mrsoundhar 0:ae306d3f6076 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
mrsoundhar 0:ae306d3f6076 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
mrsoundhar 0:ae306d3f6076 547 })
mrsoundhar 0:ae306d3f6076 548
mrsoundhar 0:ae306d3f6076 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
mrsoundhar 0:ae306d3f6076 550 ({ \
mrsoundhar 0:ae306d3f6076 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
mrsoundhar 0:ae306d3f6076 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
mrsoundhar 0:ae306d3f6076 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
mrsoundhar 0:ae306d3f6076 554 })
mrsoundhar 0:ae306d3f6076 555
mrsoundhar 0:ae306d3f6076 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 557 {
mrsoundhar 0:ae306d3f6076 558 uint32_t result;
mrsoundhar 0:ae306d3f6076 559
mrsoundhar 0:ae306d3f6076 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 561 return(result);
mrsoundhar 0:ae306d3f6076 562 }
mrsoundhar 0:ae306d3f6076 563
mrsoundhar 0:ae306d3f6076 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 565 {
mrsoundhar 0:ae306d3f6076 566 uint32_t result;
mrsoundhar 0:ae306d3f6076 567
mrsoundhar 0:ae306d3f6076 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 569 return(result);
mrsoundhar 0:ae306d3f6076 570 }
mrsoundhar 0:ae306d3f6076 571
mrsoundhar 0:ae306d3f6076 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:ae306d3f6076 573 {
mrsoundhar 0:ae306d3f6076 574 uint32_t result;
mrsoundhar 0:ae306d3f6076 575
mrsoundhar 0:ae306d3f6076 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:ae306d3f6076 577 return(result);
mrsoundhar 0:ae306d3f6076 578 }
mrsoundhar 0:ae306d3f6076 579
mrsoundhar 0:ae306d3f6076 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:ae306d3f6076 581 {
mrsoundhar 0:ae306d3f6076 582 uint32_t result;
mrsoundhar 0:ae306d3f6076 583
mrsoundhar 0:ae306d3f6076 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:ae306d3f6076 585 return(result);
mrsoundhar 0:ae306d3f6076 586 }
mrsoundhar 0:ae306d3f6076 587
mrsoundhar 0:ae306d3f6076 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
mrsoundhar 0:ae306d3f6076 589 ({ \
mrsoundhar 0:ae306d3f6076 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
mrsoundhar 0:ae306d3f6076 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
mrsoundhar 0:ae306d3f6076 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
mrsoundhar 0:ae306d3f6076 593 })
mrsoundhar 0:ae306d3f6076 594
mrsoundhar 0:ae306d3f6076 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
mrsoundhar 0:ae306d3f6076 596 ({ \
mrsoundhar 0:ae306d3f6076 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
mrsoundhar 0:ae306d3f6076 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
mrsoundhar 0:ae306d3f6076 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
mrsoundhar 0:ae306d3f6076 600 })
mrsoundhar 0:ae306d3f6076 601
mrsoundhar 0:ae306d3f6076 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 603 {
mrsoundhar 0:ae306d3f6076 604 uint32_t result;
mrsoundhar 0:ae306d3f6076 605
mrsoundhar 0:ae306d3f6076 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 607 return(result);
mrsoundhar 0:ae306d3f6076 608 }
mrsoundhar 0:ae306d3f6076 609
mrsoundhar 0:ae306d3f6076 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 611 {
mrsoundhar 0:ae306d3f6076 612 uint32_t result;
mrsoundhar 0:ae306d3f6076 613
mrsoundhar 0:ae306d3f6076 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 615 return(result);
mrsoundhar 0:ae306d3f6076 616 }
mrsoundhar 0:ae306d3f6076 617
mrsoundhar 0:ae306d3f6076 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 619 {
mrsoundhar 0:ae306d3f6076 620 uint32_t result;
mrsoundhar 0:ae306d3f6076 621
mrsoundhar 0:ae306d3f6076 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:ae306d3f6076 623 return(result);
mrsoundhar 0:ae306d3f6076 624 }
mrsoundhar 0:ae306d3f6076 625
mrsoundhar 0:ae306d3f6076 626 #define __PKHBT(ARG1,ARG2,ARG3) \
mrsoundhar 0:ae306d3f6076 627 ({ \
mrsoundhar 0:ae306d3f6076 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
mrsoundhar 0:ae306d3f6076 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
mrsoundhar 0:ae306d3f6076 630 __RES; \
mrsoundhar 0:ae306d3f6076 631 })
mrsoundhar 0:ae306d3f6076 632
mrsoundhar 0:ae306d3f6076 633 #define __PKHTB(ARG1,ARG2,ARG3) \
mrsoundhar 0:ae306d3f6076 634 ({ \
mrsoundhar 0:ae306d3f6076 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
mrsoundhar 0:ae306d3f6076 636 if (ARG3 == 0) \
mrsoundhar 0:ae306d3f6076 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
mrsoundhar 0:ae306d3f6076 638 else \
mrsoundhar 0:ae306d3f6076 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
mrsoundhar 0:ae306d3f6076 640 __RES; \
mrsoundhar 0:ae306d3f6076 641 })
mrsoundhar 0:ae306d3f6076 642
mrsoundhar 0:ae306d3f6076 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
mrsoundhar 0:ae306d3f6076 644 {
mrsoundhar 0:ae306d3f6076 645 int32_t result;
mrsoundhar 0:ae306d3f6076 646
mrsoundhar 0:ae306d3f6076 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:ae306d3f6076 648 return(result);
mrsoundhar 0:ae306d3f6076 649 }
mrsoundhar 0:ae306d3f6076 650
mrsoundhar 0:ae306d3f6076 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 652
mrsoundhar 0:ae306d3f6076 653
mrsoundhar 0:ae306d3f6076 654
mrsoundhar 0:ae306d3f6076 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mrsoundhar 0:ae306d3f6076 656 /* TASKING carm specific functions */
mrsoundhar 0:ae306d3f6076 657
mrsoundhar 0:ae306d3f6076 658
mrsoundhar 0:ae306d3f6076 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 660 /* not yet supported */
mrsoundhar 0:ae306d3f6076 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 662
mrsoundhar 0:ae306d3f6076 663
mrsoundhar 0:ae306d3f6076 664 #endif
mrsoundhar 0:ae306d3f6076 665
mrsoundhar 0:ae306d3f6076 666 /*@} end of group CMSIS_SIMD_intrinsics */
mrsoundhar 0:ae306d3f6076 667
mrsoundhar 0:ae306d3f6076 668
mrsoundhar 0:ae306d3f6076 669 #endif /* __CORE_CM4_SIMD_H */
mrsoundhar 0:ae306d3f6076 670
mrsoundhar 0:ae306d3f6076 671 #ifdef __cplusplus
mrsoundhar 0:ae306d3f6076 672 }
mrsoundhar 0:ae306d3f6076 673 #endif