Sertel_Srinath Gopalan / TARGET_LPC1768_N

LPC1768

core_cm4.h@0:ae306d3f6076, 2014-11-19 (annotated)

Committer:
mrsoundhar
Date:
Wed Nov 19 05:50:22 2014 +0000
Revision:
0:ae306d3f6076
publish

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mrsoundhar 0:ae306d3f6076 1 /**************************************************************************//**
mrsoundhar 0:ae306d3f6076 2 * @file core_cm4.h
mrsoundhar 0:ae306d3f6076 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
mrsoundhar 0:ae306d3f6076 4 * @version V3.20
mrsoundhar 0:ae306d3f6076 5 * @date 25. February 2013
mrsoundhar 0:ae306d3f6076 6 *
mrsoundhar 0:ae306d3f6076 7 * @note
mrsoundhar 0:ae306d3f6076 8 *
mrsoundhar 0:ae306d3f6076 9 ******************************************************************************/
mrsoundhar 0:ae306d3f6076 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mrsoundhar 0:ae306d3f6076 11
mrsoundhar 0:ae306d3f6076 12 All rights reserved.
mrsoundhar 0:ae306d3f6076 13 Redistribution and use in source and binary forms, with or without
mrsoundhar 0:ae306d3f6076 14 modification, are permitted provided that the following conditions are met:
mrsoundhar 0:ae306d3f6076 15 - Redistributions of source code must retain the above copyright
mrsoundhar 0:ae306d3f6076 16 notice, this list of conditions and the following disclaimer.
mrsoundhar 0:ae306d3f6076 17 - Redistributions in binary form must reproduce the above copyright
mrsoundhar 0:ae306d3f6076 18 notice, this list of conditions and the following disclaimer in the
mrsoundhar 0:ae306d3f6076 19 documentation and/or other materials provided with the distribution.
mrsoundhar 0:ae306d3f6076 20 - Neither the name of ARM nor the names of its contributors may be used
mrsoundhar 0:ae306d3f6076 21 to endorse or promote products derived from this software without
mrsoundhar 0:ae306d3f6076 22 specific prior written permission.
mrsoundhar 0:ae306d3f6076 23 *
mrsoundhar 0:ae306d3f6076 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mrsoundhar 0:ae306d3f6076 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mrsoundhar 0:ae306d3f6076 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mrsoundhar 0:ae306d3f6076 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mrsoundhar 0:ae306d3f6076 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mrsoundhar 0:ae306d3f6076 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mrsoundhar 0:ae306d3f6076 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mrsoundhar 0:ae306d3f6076 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mrsoundhar 0:ae306d3f6076 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mrsoundhar 0:ae306d3f6076 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mrsoundhar 0:ae306d3f6076 34 POSSIBILITY OF SUCH DAMAGE.
mrsoundhar 0:ae306d3f6076 35 ---------------------------------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 36
mrsoundhar 0:ae306d3f6076 37
mrsoundhar 0:ae306d3f6076 38 #if defined ( __ICCARM__ )
mrsoundhar 0:ae306d3f6076 39 #pragma system_include /* treat file as system include file for MISRA check */
mrsoundhar 0:ae306d3f6076 40 #endif
mrsoundhar 0:ae306d3f6076 41
mrsoundhar 0:ae306d3f6076 42 #ifdef __cplusplus
mrsoundhar 0:ae306d3f6076 43 extern "C" {
mrsoundhar 0:ae306d3f6076 44 #endif
mrsoundhar 0:ae306d3f6076 45
mrsoundhar 0:ae306d3f6076 46 #ifndef __CORE_CM4_H_GENERIC
mrsoundhar 0:ae306d3f6076 47 #define __CORE_CM4_H_GENERIC
mrsoundhar 0:ae306d3f6076 48
mrsoundhar 0:ae306d3f6076 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mrsoundhar 0:ae306d3f6076 50 CMSIS violates the following MISRA-C:2004 rules:
mrsoundhar 0:ae306d3f6076 51
mrsoundhar 0:ae306d3f6076 52 \li Required Rule 8.5, object/function definition in header file.<br>
mrsoundhar 0:ae306d3f6076 53 Function definitions in header files are used to allow 'inlining'.
mrsoundhar 0:ae306d3f6076 54
mrsoundhar 0:ae306d3f6076 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mrsoundhar 0:ae306d3f6076 56 Unions are used for effective representation of core registers.
mrsoundhar 0:ae306d3f6076 57
mrsoundhar 0:ae306d3f6076 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mrsoundhar 0:ae306d3f6076 59 Function-like macros are used to allow more efficient code.
mrsoundhar 0:ae306d3f6076 60 */
mrsoundhar 0:ae306d3f6076 61
mrsoundhar 0:ae306d3f6076 62
mrsoundhar 0:ae306d3f6076 63 /*******************************************************************************
mrsoundhar 0:ae306d3f6076 64 * CMSIS definitions
mrsoundhar 0:ae306d3f6076 65 ******************************************************************************/
mrsoundhar 0:ae306d3f6076 66 /** \ingroup Cortex_M4
mrsoundhar 0:ae306d3f6076 67 @{
mrsoundhar 0:ae306d3f6076 68 */
mrsoundhar 0:ae306d3f6076 69
mrsoundhar 0:ae306d3f6076 70 /* CMSIS CM4 definitions */
mrsoundhar 0:ae306d3f6076 71 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mrsoundhar 0:ae306d3f6076 72 #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
mrsoundhar 0:ae306d3f6076 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
mrsoundhar 0:ae306d3f6076 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mrsoundhar 0:ae306d3f6076 75
mrsoundhar 0:ae306d3f6076 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
mrsoundhar 0:ae306d3f6076 77
mrsoundhar 0:ae306d3f6076 78
mrsoundhar 0:ae306d3f6076 79 #if defined ( __CC_ARM )
mrsoundhar 0:ae306d3f6076 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mrsoundhar 0:ae306d3f6076 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mrsoundhar 0:ae306d3f6076 82 #define __STATIC_INLINE static __inline
mrsoundhar 0:ae306d3f6076 83
mrsoundhar 0:ae306d3f6076 84 #elif defined ( __ICCARM__ )
mrsoundhar 0:ae306d3f6076 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mrsoundhar 0:ae306d3f6076 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mrsoundhar 0:ae306d3f6076 87 #define __STATIC_INLINE static inline
mrsoundhar 0:ae306d3f6076 88
mrsoundhar 0:ae306d3f6076 89 #elif defined ( __TMS470__ )
mrsoundhar 0:ae306d3f6076 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mrsoundhar 0:ae306d3f6076 91 #define __STATIC_INLINE static inline
mrsoundhar 0:ae306d3f6076 92
mrsoundhar 0:ae306d3f6076 93 #elif defined ( __GNUC__ )
mrsoundhar 0:ae306d3f6076 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mrsoundhar 0:ae306d3f6076 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mrsoundhar 0:ae306d3f6076 96 #define __STATIC_INLINE static inline
mrsoundhar 0:ae306d3f6076 97
mrsoundhar 0:ae306d3f6076 98 #elif defined ( __TASKING__ )
mrsoundhar 0:ae306d3f6076 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mrsoundhar 0:ae306d3f6076 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mrsoundhar 0:ae306d3f6076 101 #define __STATIC_INLINE static inline
mrsoundhar 0:ae306d3f6076 102
mrsoundhar 0:ae306d3f6076 103 #endif
mrsoundhar 0:ae306d3f6076 104
mrsoundhar 0:ae306d3f6076 105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
mrsoundhar 0:ae306d3f6076 106 */
mrsoundhar 0:ae306d3f6076 107 #if defined ( __CC_ARM )
mrsoundhar 0:ae306d3f6076 108 #if defined __TARGET_FPU_VFP
mrsoundhar 0:ae306d3f6076 109 #if (__FPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 110 #define __FPU_USED 1
mrsoundhar 0:ae306d3f6076 111 #else
mrsoundhar 0:ae306d3f6076 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:ae306d3f6076 113 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 114 #endif
mrsoundhar 0:ae306d3f6076 115 #else
mrsoundhar 0:ae306d3f6076 116 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 117 #endif
mrsoundhar 0:ae306d3f6076 118
mrsoundhar 0:ae306d3f6076 119 #elif defined ( __ICCARM__ )
mrsoundhar 0:ae306d3f6076 120 #if defined __ARMVFP__
mrsoundhar 0:ae306d3f6076 121 #if (__FPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 122 #define __FPU_USED 1
mrsoundhar 0:ae306d3f6076 123 #else
mrsoundhar 0:ae306d3f6076 124 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:ae306d3f6076 125 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 126 #endif
mrsoundhar 0:ae306d3f6076 127 #else
mrsoundhar 0:ae306d3f6076 128 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 129 #endif
mrsoundhar 0:ae306d3f6076 130
mrsoundhar 0:ae306d3f6076 131 #elif defined ( __TMS470__ )
mrsoundhar 0:ae306d3f6076 132 #if defined __TI_VFP_SUPPORT__
mrsoundhar 0:ae306d3f6076 133 #if (__FPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 134 #define __FPU_USED 1
mrsoundhar 0:ae306d3f6076 135 #else
mrsoundhar 0:ae306d3f6076 136 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:ae306d3f6076 137 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 138 #endif
mrsoundhar 0:ae306d3f6076 139 #else
mrsoundhar 0:ae306d3f6076 140 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 141 #endif
mrsoundhar 0:ae306d3f6076 142
mrsoundhar 0:ae306d3f6076 143 #elif defined ( __GNUC__ )
mrsoundhar 0:ae306d3f6076 144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mrsoundhar 0:ae306d3f6076 145 #if (__FPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 146 #define __FPU_USED 1
mrsoundhar 0:ae306d3f6076 147 #else
mrsoundhar 0:ae306d3f6076 148 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:ae306d3f6076 149 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 150 #endif
mrsoundhar 0:ae306d3f6076 151 #else
mrsoundhar 0:ae306d3f6076 152 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 153 #endif
mrsoundhar 0:ae306d3f6076 154
mrsoundhar 0:ae306d3f6076 155 #elif defined ( __TASKING__ )
mrsoundhar 0:ae306d3f6076 156 #if defined __FPU_VFP__
mrsoundhar 0:ae306d3f6076 157 #if (__FPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 158 #define __FPU_USED 1
mrsoundhar 0:ae306d3f6076 159 #else
mrsoundhar 0:ae306d3f6076 160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:ae306d3f6076 161 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 162 #endif
mrsoundhar 0:ae306d3f6076 163 #else
mrsoundhar 0:ae306d3f6076 164 #define __FPU_USED 0
mrsoundhar 0:ae306d3f6076 165 #endif
mrsoundhar 0:ae306d3f6076 166 #endif
mrsoundhar 0:ae306d3f6076 167
mrsoundhar 0:ae306d3f6076 168 #include <stdint.h> /* standard types definitions */
mrsoundhar 0:ae306d3f6076 169 #include <core_cmInstr.h> /* Core Instruction Access */
mrsoundhar 0:ae306d3f6076 170 #include <core_cmFunc.h> /* Core Function Access */
mrsoundhar 0:ae306d3f6076 171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
mrsoundhar 0:ae306d3f6076 172
mrsoundhar 0:ae306d3f6076 173 #endif /* __CORE_CM4_H_GENERIC */
mrsoundhar 0:ae306d3f6076 174
mrsoundhar 0:ae306d3f6076 175 #ifndef __CMSIS_GENERIC
mrsoundhar 0:ae306d3f6076 176
mrsoundhar 0:ae306d3f6076 177 #ifndef __CORE_CM4_H_DEPENDANT
mrsoundhar 0:ae306d3f6076 178 #define __CORE_CM4_H_DEPENDANT
mrsoundhar 0:ae306d3f6076 179
mrsoundhar 0:ae306d3f6076 180 /* check device defines and use defaults */
mrsoundhar 0:ae306d3f6076 181 #if defined __CHECK_DEVICE_DEFINES
mrsoundhar 0:ae306d3f6076 182 #ifndef __CM4_REV
mrsoundhar 0:ae306d3f6076 183 #define __CM4_REV 0x0000
mrsoundhar 0:ae306d3f6076 184 #warning "__CM4_REV not defined in device header file; using default!"
mrsoundhar 0:ae306d3f6076 185 #endif
mrsoundhar 0:ae306d3f6076 186
mrsoundhar 0:ae306d3f6076 187 #ifndef __FPU_PRESENT
mrsoundhar 0:ae306d3f6076 188 #define __FPU_PRESENT 0
mrsoundhar 0:ae306d3f6076 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
mrsoundhar 0:ae306d3f6076 190 #endif
mrsoundhar 0:ae306d3f6076 191
mrsoundhar 0:ae306d3f6076 192 #ifndef __MPU_PRESENT
mrsoundhar 0:ae306d3f6076 193 #define __MPU_PRESENT 0
mrsoundhar 0:ae306d3f6076 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
mrsoundhar 0:ae306d3f6076 195 #endif
mrsoundhar 0:ae306d3f6076 196
mrsoundhar 0:ae306d3f6076 197 #ifndef __NVIC_PRIO_BITS
mrsoundhar 0:ae306d3f6076 198 #define __NVIC_PRIO_BITS 4
mrsoundhar 0:ae306d3f6076 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mrsoundhar 0:ae306d3f6076 200 #endif
mrsoundhar 0:ae306d3f6076 201
mrsoundhar 0:ae306d3f6076 202 #ifndef __Vendor_SysTickConfig
mrsoundhar 0:ae306d3f6076 203 #define __Vendor_SysTickConfig 0
mrsoundhar 0:ae306d3f6076 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mrsoundhar 0:ae306d3f6076 205 #endif
mrsoundhar 0:ae306d3f6076 206 #endif
mrsoundhar 0:ae306d3f6076 207
mrsoundhar 0:ae306d3f6076 208 /* IO definitions (access restrictions to peripheral registers) */
mrsoundhar 0:ae306d3f6076 209 /**
mrsoundhar 0:ae306d3f6076 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
mrsoundhar 0:ae306d3f6076 211
mrsoundhar 0:ae306d3f6076 212 <strong>IO Type Qualifiers</strong> are used
mrsoundhar 0:ae306d3f6076 213 \li to specify the access to peripheral variables.
mrsoundhar 0:ae306d3f6076 214 \li for automatic generation of peripheral register debug information.
mrsoundhar 0:ae306d3f6076 215 */
mrsoundhar 0:ae306d3f6076 216 #ifdef __cplusplus
mrsoundhar 0:ae306d3f6076 217 #define __I volatile /*!< Defines 'read only' permissions */
mrsoundhar 0:ae306d3f6076 218 #else
mrsoundhar 0:ae306d3f6076 219 #define __I volatile const /*!< Defines 'read only' permissions */
mrsoundhar 0:ae306d3f6076 220 #endif
mrsoundhar 0:ae306d3f6076 221 #define __O volatile /*!< Defines 'write only' permissions */
mrsoundhar 0:ae306d3f6076 222 #define __IO volatile /*!< Defines 'read / write' permissions */
mrsoundhar 0:ae306d3f6076 223
mrsoundhar 0:ae306d3f6076 224 /*@} end of group Cortex_M4 */
mrsoundhar 0:ae306d3f6076 225
mrsoundhar 0:ae306d3f6076 226
mrsoundhar 0:ae306d3f6076 227
mrsoundhar 0:ae306d3f6076 228 /*******************************************************************************
mrsoundhar 0:ae306d3f6076 229 * Register Abstraction
mrsoundhar 0:ae306d3f6076 230 Core Register contain:
mrsoundhar 0:ae306d3f6076 231 - Core Register
mrsoundhar 0:ae306d3f6076 232 - Core NVIC Register
mrsoundhar 0:ae306d3f6076 233 - Core SCB Register
mrsoundhar 0:ae306d3f6076 234 - Core SysTick Register
mrsoundhar 0:ae306d3f6076 235 - Core Debug Register
mrsoundhar 0:ae306d3f6076 236 - Core MPU Register
mrsoundhar 0:ae306d3f6076 237 - Core FPU Register
mrsoundhar 0:ae306d3f6076 238 ******************************************************************************/
mrsoundhar 0:ae306d3f6076 239 /** \defgroup CMSIS_core_register Defines and Type Definitions
mrsoundhar 0:ae306d3f6076 240 \brief Type definitions and defines for Cortex-M processor based devices.
mrsoundhar 0:ae306d3f6076 241 */
mrsoundhar 0:ae306d3f6076 242
mrsoundhar 0:ae306d3f6076 243 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 244 \defgroup CMSIS_CORE Status and Control Registers
mrsoundhar 0:ae306d3f6076 245 \brief Core Register type definitions.
mrsoundhar 0:ae306d3f6076 246 @{
mrsoundhar 0:ae306d3f6076 247 */
mrsoundhar 0:ae306d3f6076 248
mrsoundhar 0:ae306d3f6076 249 /** \brief Union type to access the Application Program Status Register (APSR).
mrsoundhar 0:ae306d3f6076 250 */
mrsoundhar 0:ae306d3f6076 251 typedef union
mrsoundhar 0:ae306d3f6076 252 {
mrsoundhar 0:ae306d3f6076 253 struct
mrsoundhar 0:ae306d3f6076 254 {
mrsoundhar 0:ae306d3f6076 255 #if (__CORTEX_M != 0x04)
mrsoundhar 0:ae306d3f6076 256 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mrsoundhar 0:ae306d3f6076 257 #else
mrsoundhar 0:ae306d3f6076 258 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mrsoundhar 0:ae306d3f6076 259 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mrsoundhar 0:ae306d3f6076 260 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mrsoundhar 0:ae306d3f6076 261 #endif
mrsoundhar 0:ae306d3f6076 262 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mrsoundhar 0:ae306d3f6076 263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mrsoundhar 0:ae306d3f6076 264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mrsoundhar 0:ae306d3f6076 265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mrsoundhar 0:ae306d3f6076 266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mrsoundhar 0:ae306d3f6076 267 } b; /*!< Structure used for bit access */
mrsoundhar 0:ae306d3f6076 268 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:ae306d3f6076 269 } APSR_Type;
mrsoundhar 0:ae306d3f6076 270
mrsoundhar 0:ae306d3f6076 271
mrsoundhar 0:ae306d3f6076 272 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mrsoundhar 0:ae306d3f6076 273 */
mrsoundhar 0:ae306d3f6076 274 typedef union
mrsoundhar 0:ae306d3f6076 275 {
mrsoundhar 0:ae306d3f6076 276 struct
mrsoundhar 0:ae306d3f6076 277 {
mrsoundhar 0:ae306d3f6076 278 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mrsoundhar 0:ae306d3f6076 279 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mrsoundhar 0:ae306d3f6076 280 } b; /*!< Structure used for bit access */
mrsoundhar 0:ae306d3f6076 281 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:ae306d3f6076 282 } IPSR_Type;
mrsoundhar 0:ae306d3f6076 283
mrsoundhar 0:ae306d3f6076 284
mrsoundhar 0:ae306d3f6076 285 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mrsoundhar 0:ae306d3f6076 286 */
mrsoundhar 0:ae306d3f6076 287 typedef union
mrsoundhar 0:ae306d3f6076 288 {
mrsoundhar 0:ae306d3f6076 289 struct
mrsoundhar 0:ae306d3f6076 290 {
mrsoundhar 0:ae306d3f6076 291 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mrsoundhar 0:ae306d3f6076 292 #if (__CORTEX_M != 0x04)
mrsoundhar 0:ae306d3f6076 293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mrsoundhar 0:ae306d3f6076 294 #else
mrsoundhar 0:ae306d3f6076 295 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mrsoundhar 0:ae306d3f6076 296 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mrsoundhar 0:ae306d3f6076 297 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mrsoundhar 0:ae306d3f6076 298 #endif
mrsoundhar 0:ae306d3f6076 299 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mrsoundhar 0:ae306d3f6076 300 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mrsoundhar 0:ae306d3f6076 301 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mrsoundhar 0:ae306d3f6076 302 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mrsoundhar 0:ae306d3f6076 303 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mrsoundhar 0:ae306d3f6076 304 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mrsoundhar 0:ae306d3f6076 305 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mrsoundhar 0:ae306d3f6076 306 } b; /*!< Structure used for bit access */
mrsoundhar 0:ae306d3f6076 307 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:ae306d3f6076 308 } xPSR_Type;
mrsoundhar 0:ae306d3f6076 309
mrsoundhar 0:ae306d3f6076 310
mrsoundhar 0:ae306d3f6076 311 /** \brief Union type to access the Control Registers (CONTROL).
mrsoundhar 0:ae306d3f6076 312 */
mrsoundhar 0:ae306d3f6076 313 typedef union
mrsoundhar 0:ae306d3f6076 314 {
mrsoundhar 0:ae306d3f6076 315 struct
mrsoundhar 0:ae306d3f6076 316 {
mrsoundhar 0:ae306d3f6076 317 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mrsoundhar 0:ae306d3f6076 318 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mrsoundhar 0:ae306d3f6076 319 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mrsoundhar 0:ae306d3f6076 320 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mrsoundhar 0:ae306d3f6076 321 } b; /*!< Structure used for bit access */
mrsoundhar 0:ae306d3f6076 322 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:ae306d3f6076 323 } CONTROL_Type;
mrsoundhar 0:ae306d3f6076 324
mrsoundhar 0:ae306d3f6076 325 /*@} end of group CMSIS_CORE */
mrsoundhar 0:ae306d3f6076 326
mrsoundhar 0:ae306d3f6076 327
mrsoundhar 0:ae306d3f6076 328 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 329 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mrsoundhar 0:ae306d3f6076 330 \brief Type definitions for the NVIC Registers
mrsoundhar 0:ae306d3f6076 331 @{
mrsoundhar 0:ae306d3f6076 332 */
mrsoundhar 0:ae306d3f6076 333
mrsoundhar 0:ae306d3f6076 334 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mrsoundhar 0:ae306d3f6076 335 */
mrsoundhar 0:ae306d3f6076 336 typedef struct
mrsoundhar 0:ae306d3f6076 337 {
mrsoundhar 0:ae306d3f6076 338 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mrsoundhar 0:ae306d3f6076 339 uint32_t RESERVED0[24];
mrsoundhar 0:ae306d3f6076 340 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mrsoundhar 0:ae306d3f6076 341 uint32_t RSERVED1[24];
mrsoundhar 0:ae306d3f6076 342 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mrsoundhar 0:ae306d3f6076 343 uint32_t RESERVED2[24];
mrsoundhar 0:ae306d3f6076 344 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mrsoundhar 0:ae306d3f6076 345 uint32_t RESERVED3[24];
mrsoundhar 0:ae306d3f6076 346 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
mrsoundhar 0:ae306d3f6076 347 uint32_t RESERVED4[56];
mrsoundhar 0:ae306d3f6076 348 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
mrsoundhar 0:ae306d3f6076 349 uint32_t RESERVED5[644];
mrsoundhar 0:ae306d3f6076 350 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
mrsoundhar 0:ae306d3f6076 351 } NVIC_Type;
mrsoundhar 0:ae306d3f6076 352
mrsoundhar 0:ae306d3f6076 353 /* Software Triggered Interrupt Register Definitions */
mrsoundhar 0:ae306d3f6076 354 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
mrsoundhar 0:ae306d3f6076 355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
mrsoundhar 0:ae306d3f6076 356
mrsoundhar 0:ae306d3f6076 357 /*@} end of group CMSIS_NVIC */
mrsoundhar 0:ae306d3f6076 358
mrsoundhar 0:ae306d3f6076 359
mrsoundhar 0:ae306d3f6076 360 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 361 \defgroup CMSIS_SCB System Control Block (SCB)
mrsoundhar 0:ae306d3f6076 362 \brief Type definitions for the System Control Block Registers
mrsoundhar 0:ae306d3f6076 363 @{
mrsoundhar 0:ae306d3f6076 364 */
mrsoundhar 0:ae306d3f6076 365
mrsoundhar 0:ae306d3f6076 366 /** \brief Structure type to access the System Control Block (SCB).
mrsoundhar 0:ae306d3f6076 367 */
mrsoundhar 0:ae306d3f6076 368 typedef struct
mrsoundhar 0:ae306d3f6076 369 {
mrsoundhar 0:ae306d3f6076 370 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mrsoundhar 0:ae306d3f6076 371 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mrsoundhar 0:ae306d3f6076 372 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mrsoundhar 0:ae306d3f6076 373 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mrsoundhar 0:ae306d3f6076 374 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mrsoundhar 0:ae306d3f6076 375 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mrsoundhar 0:ae306d3f6076 376 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
mrsoundhar 0:ae306d3f6076 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mrsoundhar 0:ae306d3f6076 378 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
mrsoundhar 0:ae306d3f6076 379 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
mrsoundhar 0:ae306d3f6076 380 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
mrsoundhar 0:ae306d3f6076 381 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
mrsoundhar 0:ae306d3f6076 382 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
mrsoundhar 0:ae306d3f6076 383 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
mrsoundhar 0:ae306d3f6076 384 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
mrsoundhar 0:ae306d3f6076 385 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
mrsoundhar 0:ae306d3f6076 386 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
mrsoundhar 0:ae306d3f6076 387 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
mrsoundhar 0:ae306d3f6076 388 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
mrsoundhar 0:ae306d3f6076 389 uint32_t RESERVED0[5];
mrsoundhar 0:ae306d3f6076 390 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
mrsoundhar 0:ae306d3f6076 391 } SCB_Type;
mrsoundhar 0:ae306d3f6076 392
mrsoundhar 0:ae306d3f6076 393 /* SCB CPUID Register Definitions */
mrsoundhar 0:ae306d3f6076 394 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mrsoundhar 0:ae306d3f6076 395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mrsoundhar 0:ae306d3f6076 396
mrsoundhar 0:ae306d3f6076 397 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mrsoundhar 0:ae306d3f6076 398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mrsoundhar 0:ae306d3f6076 399
mrsoundhar 0:ae306d3f6076 400 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mrsoundhar 0:ae306d3f6076 401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mrsoundhar 0:ae306d3f6076 402
mrsoundhar 0:ae306d3f6076 403 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mrsoundhar 0:ae306d3f6076 404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mrsoundhar 0:ae306d3f6076 405
mrsoundhar 0:ae306d3f6076 406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mrsoundhar 0:ae306d3f6076 407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
mrsoundhar 0:ae306d3f6076 408
mrsoundhar 0:ae306d3f6076 409 /* SCB Interrupt Control State Register Definitions */
mrsoundhar 0:ae306d3f6076 410 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mrsoundhar 0:ae306d3f6076 411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mrsoundhar 0:ae306d3f6076 412
mrsoundhar 0:ae306d3f6076 413 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mrsoundhar 0:ae306d3f6076 414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mrsoundhar 0:ae306d3f6076 415
mrsoundhar 0:ae306d3f6076 416 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mrsoundhar 0:ae306d3f6076 417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mrsoundhar 0:ae306d3f6076 418
mrsoundhar 0:ae306d3f6076 419 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mrsoundhar 0:ae306d3f6076 420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mrsoundhar 0:ae306d3f6076 421
mrsoundhar 0:ae306d3f6076 422 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mrsoundhar 0:ae306d3f6076 423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mrsoundhar 0:ae306d3f6076 424
mrsoundhar 0:ae306d3f6076 425 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mrsoundhar 0:ae306d3f6076 426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mrsoundhar 0:ae306d3f6076 427
mrsoundhar 0:ae306d3f6076 428 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mrsoundhar 0:ae306d3f6076 429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mrsoundhar 0:ae306d3f6076 430
mrsoundhar 0:ae306d3f6076 431 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mrsoundhar 0:ae306d3f6076 432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mrsoundhar 0:ae306d3f6076 433
mrsoundhar 0:ae306d3f6076 434 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
mrsoundhar 0:ae306d3f6076 435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
mrsoundhar 0:ae306d3f6076 436
mrsoundhar 0:ae306d3f6076 437 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mrsoundhar 0:ae306d3f6076 438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
mrsoundhar 0:ae306d3f6076 439
mrsoundhar 0:ae306d3f6076 440 /* SCB Vector Table Offset Register Definitions */
mrsoundhar 0:ae306d3f6076 441 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
mrsoundhar 0:ae306d3f6076 442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mrsoundhar 0:ae306d3f6076 443
mrsoundhar 0:ae306d3f6076 444 /* SCB Application Interrupt and Reset Control Register Definitions */
mrsoundhar 0:ae306d3f6076 445 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mrsoundhar 0:ae306d3f6076 446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mrsoundhar 0:ae306d3f6076 447
mrsoundhar 0:ae306d3f6076 448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mrsoundhar 0:ae306d3f6076 449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mrsoundhar 0:ae306d3f6076 450
mrsoundhar 0:ae306d3f6076 451 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mrsoundhar 0:ae306d3f6076 452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mrsoundhar 0:ae306d3f6076 453
mrsoundhar 0:ae306d3f6076 454 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
mrsoundhar 0:ae306d3f6076 455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
mrsoundhar 0:ae306d3f6076 456
mrsoundhar 0:ae306d3f6076 457 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mrsoundhar 0:ae306d3f6076 458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mrsoundhar 0:ae306d3f6076 459
mrsoundhar 0:ae306d3f6076 460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mrsoundhar 0:ae306d3f6076 461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mrsoundhar 0:ae306d3f6076 462
mrsoundhar 0:ae306d3f6076 463 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
mrsoundhar 0:ae306d3f6076 464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
mrsoundhar 0:ae306d3f6076 465
mrsoundhar 0:ae306d3f6076 466 /* SCB System Control Register Definitions */
mrsoundhar 0:ae306d3f6076 467 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mrsoundhar 0:ae306d3f6076 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mrsoundhar 0:ae306d3f6076 469
mrsoundhar 0:ae306d3f6076 470 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mrsoundhar 0:ae306d3f6076 471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mrsoundhar 0:ae306d3f6076 472
mrsoundhar 0:ae306d3f6076 473 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mrsoundhar 0:ae306d3f6076 474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mrsoundhar 0:ae306d3f6076 475
mrsoundhar 0:ae306d3f6076 476 /* SCB Configuration Control Register Definitions */
mrsoundhar 0:ae306d3f6076 477 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mrsoundhar 0:ae306d3f6076 478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mrsoundhar 0:ae306d3f6076 479
mrsoundhar 0:ae306d3f6076 480 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
mrsoundhar 0:ae306d3f6076 481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
mrsoundhar 0:ae306d3f6076 482
mrsoundhar 0:ae306d3f6076 483 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
mrsoundhar 0:ae306d3f6076 484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
mrsoundhar 0:ae306d3f6076 485
mrsoundhar 0:ae306d3f6076 486 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mrsoundhar 0:ae306d3f6076 487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mrsoundhar 0:ae306d3f6076 488
mrsoundhar 0:ae306d3f6076 489 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
mrsoundhar 0:ae306d3f6076 490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
mrsoundhar 0:ae306d3f6076 491
mrsoundhar 0:ae306d3f6076 492 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
mrsoundhar 0:ae306d3f6076 493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
mrsoundhar 0:ae306d3f6076 494
mrsoundhar 0:ae306d3f6076 495 /* SCB System Handler Control and State Register Definitions */
mrsoundhar 0:ae306d3f6076 496 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
mrsoundhar 0:ae306d3f6076 497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
mrsoundhar 0:ae306d3f6076 498
mrsoundhar 0:ae306d3f6076 499 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
mrsoundhar 0:ae306d3f6076 500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
mrsoundhar 0:ae306d3f6076 501
mrsoundhar 0:ae306d3f6076 502 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
mrsoundhar 0:ae306d3f6076 503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
mrsoundhar 0:ae306d3f6076 504
mrsoundhar 0:ae306d3f6076 505 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mrsoundhar 0:ae306d3f6076 506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mrsoundhar 0:ae306d3f6076 507
mrsoundhar 0:ae306d3f6076 508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
mrsoundhar 0:ae306d3f6076 509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
mrsoundhar 0:ae306d3f6076 510
mrsoundhar 0:ae306d3f6076 511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
mrsoundhar 0:ae306d3f6076 512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
mrsoundhar 0:ae306d3f6076 513
mrsoundhar 0:ae306d3f6076 514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
mrsoundhar 0:ae306d3f6076 515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
mrsoundhar 0:ae306d3f6076 516
mrsoundhar 0:ae306d3f6076 517 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
mrsoundhar 0:ae306d3f6076 518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
mrsoundhar 0:ae306d3f6076 519
mrsoundhar 0:ae306d3f6076 520 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
mrsoundhar 0:ae306d3f6076 521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
mrsoundhar 0:ae306d3f6076 522
mrsoundhar 0:ae306d3f6076 523 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
mrsoundhar 0:ae306d3f6076 524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
mrsoundhar 0:ae306d3f6076 525
mrsoundhar 0:ae306d3f6076 526 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
mrsoundhar 0:ae306d3f6076 527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
mrsoundhar 0:ae306d3f6076 528
mrsoundhar 0:ae306d3f6076 529 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
mrsoundhar 0:ae306d3f6076 530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
mrsoundhar 0:ae306d3f6076 531
mrsoundhar 0:ae306d3f6076 532 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
mrsoundhar 0:ae306d3f6076 533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
mrsoundhar 0:ae306d3f6076 534
mrsoundhar 0:ae306d3f6076 535 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
mrsoundhar 0:ae306d3f6076 536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
mrsoundhar 0:ae306d3f6076 537
mrsoundhar 0:ae306d3f6076 538 /* SCB Configurable Fault Status Registers Definitions */
mrsoundhar 0:ae306d3f6076 539 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
mrsoundhar 0:ae306d3f6076 540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
mrsoundhar 0:ae306d3f6076 541
mrsoundhar 0:ae306d3f6076 542 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
mrsoundhar 0:ae306d3f6076 543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
mrsoundhar 0:ae306d3f6076 544
mrsoundhar 0:ae306d3f6076 545 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
mrsoundhar 0:ae306d3f6076 546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
mrsoundhar 0:ae306d3f6076 547
mrsoundhar 0:ae306d3f6076 548 /* SCB Hard Fault Status Registers Definitions */
mrsoundhar 0:ae306d3f6076 549 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
mrsoundhar 0:ae306d3f6076 550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
mrsoundhar 0:ae306d3f6076 551
mrsoundhar 0:ae306d3f6076 552 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
mrsoundhar 0:ae306d3f6076 553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
mrsoundhar 0:ae306d3f6076 554
mrsoundhar 0:ae306d3f6076 555 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
mrsoundhar 0:ae306d3f6076 556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
mrsoundhar 0:ae306d3f6076 557
mrsoundhar 0:ae306d3f6076 558 /* SCB Debug Fault Status Register Definitions */
mrsoundhar 0:ae306d3f6076 559 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
mrsoundhar 0:ae306d3f6076 560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
mrsoundhar 0:ae306d3f6076 561
mrsoundhar 0:ae306d3f6076 562 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
mrsoundhar 0:ae306d3f6076 563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
mrsoundhar 0:ae306d3f6076 564
mrsoundhar 0:ae306d3f6076 565 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
mrsoundhar 0:ae306d3f6076 566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
mrsoundhar 0:ae306d3f6076 567
mrsoundhar 0:ae306d3f6076 568 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
mrsoundhar 0:ae306d3f6076 569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
mrsoundhar 0:ae306d3f6076 570
mrsoundhar 0:ae306d3f6076 571 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
mrsoundhar 0:ae306d3f6076 572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
mrsoundhar 0:ae306d3f6076 573
mrsoundhar 0:ae306d3f6076 574 /*@} end of group CMSIS_SCB */
mrsoundhar 0:ae306d3f6076 575
mrsoundhar 0:ae306d3f6076 576
mrsoundhar 0:ae306d3f6076 577 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 578 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mrsoundhar 0:ae306d3f6076 579 \brief Type definitions for the System Control and ID Register not in the SCB
mrsoundhar 0:ae306d3f6076 580 @{
mrsoundhar 0:ae306d3f6076 581 */
mrsoundhar 0:ae306d3f6076 582
mrsoundhar 0:ae306d3f6076 583 /** \brief Structure type to access the System Control and ID Register not in the SCB.
mrsoundhar 0:ae306d3f6076 584 */
mrsoundhar 0:ae306d3f6076 585 typedef struct
mrsoundhar 0:ae306d3f6076 586 {
mrsoundhar 0:ae306d3f6076 587 uint32_t RESERVED0[1];
mrsoundhar 0:ae306d3f6076 588 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
mrsoundhar 0:ae306d3f6076 589 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mrsoundhar 0:ae306d3f6076 590 } SCnSCB_Type;
mrsoundhar 0:ae306d3f6076 591
mrsoundhar 0:ae306d3f6076 592 /* Interrupt Controller Type Register Definitions */
mrsoundhar 0:ae306d3f6076 593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
mrsoundhar 0:ae306d3f6076 594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
mrsoundhar 0:ae306d3f6076 595
mrsoundhar 0:ae306d3f6076 596 /* Auxiliary Control Register Definitions */
mrsoundhar 0:ae306d3f6076 597 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
mrsoundhar 0:ae306d3f6076 598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
mrsoundhar 0:ae306d3f6076 599
mrsoundhar 0:ae306d3f6076 600 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
mrsoundhar 0:ae306d3f6076 601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
mrsoundhar 0:ae306d3f6076 602
mrsoundhar 0:ae306d3f6076 603 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
mrsoundhar 0:ae306d3f6076 604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
mrsoundhar 0:ae306d3f6076 605
mrsoundhar 0:ae306d3f6076 606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
mrsoundhar 0:ae306d3f6076 607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
mrsoundhar 0:ae306d3f6076 608
mrsoundhar 0:ae306d3f6076 609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
mrsoundhar 0:ae306d3f6076 610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
mrsoundhar 0:ae306d3f6076 611
mrsoundhar 0:ae306d3f6076 612 /*@} end of group CMSIS_SCnotSCB */
mrsoundhar 0:ae306d3f6076 613
mrsoundhar 0:ae306d3f6076 614
mrsoundhar 0:ae306d3f6076 615 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 616 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mrsoundhar 0:ae306d3f6076 617 \brief Type definitions for the System Timer Registers.
mrsoundhar 0:ae306d3f6076 618 @{
mrsoundhar 0:ae306d3f6076 619 */
mrsoundhar 0:ae306d3f6076 620
mrsoundhar 0:ae306d3f6076 621 /** \brief Structure type to access the System Timer (SysTick).
mrsoundhar 0:ae306d3f6076 622 */
mrsoundhar 0:ae306d3f6076 623 typedef struct
mrsoundhar 0:ae306d3f6076 624 {
mrsoundhar 0:ae306d3f6076 625 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mrsoundhar 0:ae306d3f6076 626 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mrsoundhar 0:ae306d3f6076 627 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mrsoundhar 0:ae306d3f6076 628 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mrsoundhar 0:ae306d3f6076 629 } SysTick_Type;
mrsoundhar 0:ae306d3f6076 630
mrsoundhar 0:ae306d3f6076 631 /* SysTick Control / Status Register Definitions */
mrsoundhar 0:ae306d3f6076 632 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mrsoundhar 0:ae306d3f6076 633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mrsoundhar 0:ae306d3f6076 634
mrsoundhar 0:ae306d3f6076 635 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mrsoundhar 0:ae306d3f6076 636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mrsoundhar 0:ae306d3f6076 637
mrsoundhar 0:ae306d3f6076 638 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mrsoundhar 0:ae306d3f6076 639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mrsoundhar 0:ae306d3f6076 640
mrsoundhar 0:ae306d3f6076 641 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mrsoundhar 0:ae306d3f6076 642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
mrsoundhar 0:ae306d3f6076 643
mrsoundhar 0:ae306d3f6076 644 /* SysTick Reload Register Definitions */
mrsoundhar 0:ae306d3f6076 645 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mrsoundhar 0:ae306d3f6076 646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
mrsoundhar 0:ae306d3f6076 647
mrsoundhar 0:ae306d3f6076 648 /* SysTick Current Register Definitions */
mrsoundhar 0:ae306d3f6076 649 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mrsoundhar 0:ae306d3f6076 650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
mrsoundhar 0:ae306d3f6076 651
mrsoundhar 0:ae306d3f6076 652 /* SysTick Calibration Register Definitions */
mrsoundhar 0:ae306d3f6076 653 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mrsoundhar 0:ae306d3f6076 654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mrsoundhar 0:ae306d3f6076 655
mrsoundhar 0:ae306d3f6076 656 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mrsoundhar 0:ae306d3f6076 657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mrsoundhar 0:ae306d3f6076 658
mrsoundhar 0:ae306d3f6076 659 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mrsoundhar 0:ae306d3f6076 660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
mrsoundhar 0:ae306d3f6076 661
mrsoundhar 0:ae306d3f6076 662 /*@} end of group CMSIS_SysTick */
mrsoundhar 0:ae306d3f6076 663
mrsoundhar 0:ae306d3f6076 664
mrsoundhar 0:ae306d3f6076 665 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 666 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mrsoundhar 0:ae306d3f6076 667 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mrsoundhar 0:ae306d3f6076 668 @{
mrsoundhar 0:ae306d3f6076 669 */
mrsoundhar 0:ae306d3f6076 670
mrsoundhar 0:ae306d3f6076 671 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mrsoundhar 0:ae306d3f6076 672 */
mrsoundhar 0:ae306d3f6076 673 typedef struct
mrsoundhar 0:ae306d3f6076 674 {
mrsoundhar 0:ae306d3f6076 675 __O union
mrsoundhar 0:ae306d3f6076 676 {
mrsoundhar 0:ae306d3f6076 677 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
mrsoundhar 0:ae306d3f6076 678 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
mrsoundhar 0:ae306d3f6076 679 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
mrsoundhar 0:ae306d3f6076 680 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
mrsoundhar 0:ae306d3f6076 681 uint32_t RESERVED0[864];
mrsoundhar 0:ae306d3f6076 682 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
mrsoundhar 0:ae306d3f6076 683 uint32_t RESERVED1[15];
mrsoundhar 0:ae306d3f6076 684 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
mrsoundhar 0:ae306d3f6076 685 uint32_t RESERVED2[15];
mrsoundhar 0:ae306d3f6076 686 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
mrsoundhar 0:ae306d3f6076 687 uint32_t RESERVED3[29];
mrsoundhar 0:ae306d3f6076 688 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
mrsoundhar 0:ae306d3f6076 689 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
mrsoundhar 0:ae306d3f6076 690 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
mrsoundhar 0:ae306d3f6076 691 uint32_t RESERVED4[43];
mrsoundhar 0:ae306d3f6076 692 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
mrsoundhar 0:ae306d3f6076 693 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
mrsoundhar 0:ae306d3f6076 694 uint32_t RESERVED5[6];
mrsoundhar 0:ae306d3f6076 695 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
mrsoundhar 0:ae306d3f6076 696 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
mrsoundhar 0:ae306d3f6076 697 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
mrsoundhar 0:ae306d3f6076 698 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
mrsoundhar 0:ae306d3f6076 699 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
mrsoundhar 0:ae306d3f6076 700 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
mrsoundhar 0:ae306d3f6076 701 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
mrsoundhar 0:ae306d3f6076 702 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
mrsoundhar 0:ae306d3f6076 703 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
mrsoundhar 0:ae306d3f6076 704 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
mrsoundhar 0:ae306d3f6076 705 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
mrsoundhar 0:ae306d3f6076 706 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
mrsoundhar 0:ae306d3f6076 707 } ITM_Type;
mrsoundhar 0:ae306d3f6076 708
mrsoundhar 0:ae306d3f6076 709 /* ITM Trace Privilege Register Definitions */
mrsoundhar 0:ae306d3f6076 710 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
mrsoundhar 0:ae306d3f6076 711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
mrsoundhar 0:ae306d3f6076 712
mrsoundhar 0:ae306d3f6076 713 /* ITM Trace Control Register Definitions */
mrsoundhar 0:ae306d3f6076 714 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
mrsoundhar 0:ae306d3f6076 715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
mrsoundhar 0:ae306d3f6076 716
mrsoundhar 0:ae306d3f6076 717 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
mrsoundhar 0:ae306d3f6076 718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
mrsoundhar 0:ae306d3f6076 719
mrsoundhar 0:ae306d3f6076 720 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
mrsoundhar 0:ae306d3f6076 721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
mrsoundhar 0:ae306d3f6076 722
mrsoundhar 0:ae306d3f6076 723 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
mrsoundhar 0:ae306d3f6076 724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
mrsoundhar 0:ae306d3f6076 725
mrsoundhar 0:ae306d3f6076 726 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
mrsoundhar 0:ae306d3f6076 727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
mrsoundhar 0:ae306d3f6076 728
mrsoundhar 0:ae306d3f6076 729 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
mrsoundhar 0:ae306d3f6076 730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
mrsoundhar 0:ae306d3f6076 731
mrsoundhar 0:ae306d3f6076 732 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
mrsoundhar 0:ae306d3f6076 733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
mrsoundhar 0:ae306d3f6076 734
mrsoundhar 0:ae306d3f6076 735 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
mrsoundhar 0:ae306d3f6076 736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
mrsoundhar 0:ae306d3f6076 737
mrsoundhar 0:ae306d3f6076 738 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
mrsoundhar 0:ae306d3f6076 739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
mrsoundhar 0:ae306d3f6076 740
mrsoundhar 0:ae306d3f6076 741 /* ITM Integration Write Register Definitions */
mrsoundhar 0:ae306d3f6076 742 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
mrsoundhar 0:ae306d3f6076 743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
mrsoundhar 0:ae306d3f6076 744
mrsoundhar 0:ae306d3f6076 745 /* ITM Integration Read Register Definitions */
mrsoundhar 0:ae306d3f6076 746 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
mrsoundhar 0:ae306d3f6076 747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
mrsoundhar 0:ae306d3f6076 748
mrsoundhar 0:ae306d3f6076 749 /* ITM Integration Mode Control Register Definitions */
mrsoundhar 0:ae306d3f6076 750 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
mrsoundhar 0:ae306d3f6076 751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
mrsoundhar 0:ae306d3f6076 752
mrsoundhar 0:ae306d3f6076 753 /* ITM Lock Status Register Definitions */
mrsoundhar 0:ae306d3f6076 754 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
mrsoundhar 0:ae306d3f6076 755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
mrsoundhar 0:ae306d3f6076 756
mrsoundhar 0:ae306d3f6076 757 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
mrsoundhar 0:ae306d3f6076 758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
mrsoundhar 0:ae306d3f6076 759
mrsoundhar 0:ae306d3f6076 760 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
mrsoundhar 0:ae306d3f6076 761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
mrsoundhar 0:ae306d3f6076 762
mrsoundhar 0:ae306d3f6076 763 /*@}*/ /* end of group CMSIS_ITM */
mrsoundhar 0:ae306d3f6076 764
mrsoundhar 0:ae306d3f6076 765
mrsoundhar 0:ae306d3f6076 766 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 767 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mrsoundhar 0:ae306d3f6076 768 \brief Type definitions for the Data Watchpoint and Trace (DWT)
mrsoundhar 0:ae306d3f6076 769 @{
mrsoundhar 0:ae306d3f6076 770 */
mrsoundhar 0:ae306d3f6076 771
mrsoundhar 0:ae306d3f6076 772 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mrsoundhar 0:ae306d3f6076 773 */
mrsoundhar 0:ae306d3f6076 774 typedef struct
mrsoundhar 0:ae306d3f6076 775 {
mrsoundhar 0:ae306d3f6076 776 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
mrsoundhar 0:ae306d3f6076 777 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
mrsoundhar 0:ae306d3f6076 778 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
mrsoundhar 0:ae306d3f6076 779 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
mrsoundhar 0:ae306d3f6076 780 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
mrsoundhar 0:ae306d3f6076 781 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
mrsoundhar 0:ae306d3f6076 782 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
mrsoundhar 0:ae306d3f6076 783 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
mrsoundhar 0:ae306d3f6076 784 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
mrsoundhar 0:ae306d3f6076 785 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
mrsoundhar 0:ae306d3f6076 786 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
mrsoundhar 0:ae306d3f6076 787 uint32_t RESERVED0[1];
mrsoundhar 0:ae306d3f6076 788 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
mrsoundhar 0:ae306d3f6076 789 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
mrsoundhar 0:ae306d3f6076 790 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
mrsoundhar 0:ae306d3f6076 791 uint32_t RESERVED1[1];
mrsoundhar 0:ae306d3f6076 792 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
mrsoundhar 0:ae306d3f6076 793 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
mrsoundhar 0:ae306d3f6076 794 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
mrsoundhar 0:ae306d3f6076 795 uint32_t RESERVED2[1];
mrsoundhar 0:ae306d3f6076 796 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
mrsoundhar 0:ae306d3f6076 797 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
mrsoundhar 0:ae306d3f6076 798 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
mrsoundhar 0:ae306d3f6076 799 } DWT_Type;
mrsoundhar 0:ae306d3f6076 800
mrsoundhar 0:ae306d3f6076 801 /* DWT Control Register Definitions */
mrsoundhar 0:ae306d3f6076 802 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
mrsoundhar 0:ae306d3f6076 803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
mrsoundhar 0:ae306d3f6076 804
mrsoundhar 0:ae306d3f6076 805 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
mrsoundhar 0:ae306d3f6076 806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
mrsoundhar 0:ae306d3f6076 807
mrsoundhar 0:ae306d3f6076 808 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
mrsoundhar 0:ae306d3f6076 809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
mrsoundhar 0:ae306d3f6076 810
mrsoundhar 0:ae306d3f6076 811 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
mrsoundhar 0:ae306d3f6076 812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
mrsoundhar 0:ae306d3f6076 813
mrsoundhar 0:ae306d3f6076 814 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
mrsoundhar 0:ae306d3f6076 815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
mrsoundhar 0:ae306d3f6076 816
mrsoundhar 0:ae306d3f6076 817 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
mrsoundhar 0:ae306d3f6076 818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
mrsoundhar 0:ae306d3f6076 819
mrsoundhar 0:ae306d3f6076 820 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
mrsoundhar 0:ae306d3f6076 821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
mrsoundhar 0:ae306d3f6076 822
mrsoundhar 0:ae306d3f6076 823 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
mrsoundhar 0:ae306d3f6076 824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
mrsoundhar 0:ae306d3f6076 825
mrsoundhar 0:ae306d3f6076 826 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
mrsoundhar 0:ae306d3f6076 827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
mrsoundhar 0:ae306d3f6076 828
mrsoundhar 0:ae306d3f6076 829 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
mrsoundhar 0:ae306d3f6076 830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
mrsoundhar 0:ae306d3f6076 831
mrsoundhar 0:ae306d3f6076 832 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
mrsoundhar 0:ae306d3f6076 833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
mrsoundhar 0:ae306d3f6076 834
mrsoundhar 0:ae306d3f6076 835 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
mrsoundhar 0:ae306d3f6076 836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
mrsoundhar 0:ae306d3f6076 837
mrsoundhar 0:ae306d3f6076 838 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
mrsoundhar 0:ae306d3f6076 839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
mrsoundhar 0:ae306d3f6076 840
mrsoundhar 0:ae306d3f6076 841 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
mrsoundhar 0:ae306d3f6076 842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
mrsoundhar 0:ae306d3f6076 843
mrsoundhar 0:ae306d3f6076 844 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
mrsoundhar 0:ae306d3f6076 845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
mrsoundhar 0:ae306d3f6076 846
mrsoundhar 0:ae306d3f6076 847 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
mrsoundhar 0:ae306d3f6076 848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
mrsoundhar 0:ae306d3f6076 849
mrsoundhar 0:ae306d3f6076 850 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
mrsoundhar 0:ae306d3f6076 851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
mrsoundhar 0:ae306d3f6076 852
mrsoundhar 0:ae306d3f6076 853 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
mrsoundhar 0:ae306d3f6076 854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
mrsoundhar 0:ae306d3f6076 855
mrsoundhar 0:ae306d3f6076 856 /* DWT CPI Count Register Definitions */
mrsoundhar 0:ae306d3f6076 857 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
mrsoundhar 0:ae306d3f6076 858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
mrsoundhar 0:ae306d3f6076 859
mrsoundhar 0:ae306d3f6076 860 /* DWT Exception Overhead Count Register Definitions */
mrsoundhar 0:ae306d3f6076 861 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
mrsoundhar 0:ae306d3f6076 862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
mrsoundhar 0:ae306d3f6076 863
mrsoundhar 0:ae306d3f6076 864 /* DWT Sleep Count Register Definitions */
mrsoundhar 0:ae306d3f6076 865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
mrsoundhar 0:ae306d3f6076 866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
mrsoundhar 0:ae306d3f6076 867
mrsoundhar 0:ae306d3f6076 868 /* DWT LSU Count Register Definitions */
mrsoundhar 0:ae306d3f6076 869 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
mrsoundhar 0:ae306d3f6076 870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
mrsoundhar 0:ae306d3f6076 871
mrsoundhar 0:ae306d3f6076 872 /* DWT Folded-instruction Count Register Definitions */
mrsoundhar 0:ae306d3f6076 873 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
mrsoundhar 0:ae306d3f6076 874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
mrsoundhar 0:ae306d3f6076 875
mrsoundhar 0:ae306d3f6076 876 /* DWT Comparator Mask Register Definitions */
mrsoundhar 0:ae306d3f6076 877 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
mrsoundhar 0:ae306d3f6076 878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
mrsoundhar 0:ae306d3f6076 879
mrsoundhar 0:ae306d3f6076 880 /* DWT Comparator Function Register Definitions */
mrsoundhar 0:ae306d3f6076 881 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
mrsoundhar 0:ae306d3f6076 882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
mrsoundhar 0:ae306d3f6076 883
mrsoundhar 0:ae306d3f6076 884 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
mrsoundhar 0:ae306d3f6076 885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
mrsoundhar 0:ae306d3f6076 886
mrsoundhar 0:ae306d3f6076 887 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
mrsoundhar 0:ae306d3f6076 888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
mrsoundhar 0:ae306d3f6076 889
mrsoundhar 0:ae306d3f6076 890 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
mrsoundhar 0:ae306d3f6076 891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
mrsoundhar 0:ae306d3f6076 892
mrsoundhar 0:ae306d3f6076 893 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
mrsoundhar 0:ae306d3f6076 894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
mrsoundhar 0:ae306d3f6076 895
mrsoundhar 0:ae306d3f6076 896 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
mrsoundhar 0:ae306d3f6076 897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
mrsoundhar 0:ae306d3f6076 898
mrsoundhar 0:ae306d3f6076 899 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
mrsoundhar 0:ae306d3f6076 900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
mrsoundhar 0:ae306d3f6076 901
mrsoundhar 0:ae306d3f6076 902 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
mrsoundhar 0:ae306d3f6076 903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
mrsoundhar 0:ae306d3f6076 904
mrsoundhar 0:ae306d3f6076 905 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
mrsoundhar 0:ae306d3f6076 906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
mrsoundhar 0:ae306d3f6076 907
mrsoundhar 0:ae306d3f6076 908 /*@}*/ /* end of group CMSIS_DWT */
mrsoundhar 0:ae306d3f6076 909
mrsoundhar 0:ae306d3f6076 910
mrsoundhar 0:ae306d3f6076 911 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 912 \defgroup CMSIS_TPI Trace Port Interface (TPI)
mrsoundhar 0:ae306d3f6076 913 \brief Type definitions for the Trace Port Interface (TPI)
mrsoundhar 0:ae306d3f6076 914 @{
mrsoundhar 0:ae306d3f6076 915 */
mrsoundhar 0:ae306d3f6076 916
mrsoundhar 0:ae306d3f6076 917 /** \brief Structure type to access the Trace Port Interface Register (TPI).
mrsoundhar 0:ae306d3f6076 918 */
mrsoundhar 0:ae306d3f6076 919 typedef struct
mrsoundhar 0:ae306d3f6076 920 {
mrsoundhar 0:ae306d3f6076 921 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
mrsoundhar 0:ae306d3f6076 922 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
mrsoundhar 0:ae306d3f6076 923 uint32_t RESERVED0[2];
mrsoundhar 0:ae306d3f6076 924 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
mrsoundhar 0:ae306d3f6076 925 uint32_t RESERVED1[55];
mrsoundhar 0:ae306d3f6076 926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
mrsoundhar 0:ae306d3f6076 927 uint32_t RESERVED2[131];
mrsoundhar 0:ae306d3f6076 928 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
mrsoundhar 0:ae306d3f6076 929 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
mrsoundhar 0:ae306d3f6076 930 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
mrsoundhar 0:ae306d3f6076 931 uint32_t RESERVED3[759];
mrsoundhar 0:ae306d3f6076 932 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
mrsoundhar 0:ae306d3f6076 933 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
mrsoundhar 0:ae306d3f6076 934 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
mrsoundhar 0:ae306d3f6076 935 uint32_t RESERVED4[1];
mrsoundhar 0:ae306d3f6076 936 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
mrsoundhar 0:ae306d3f6076 937 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
mrsoundhar 0:ae306d3f6076 938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
mrsoundhar 0:ae306d3f6076 939 uint32_t RESERVED5[39];
mrsoundhar 0:ae306d3f6076 940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
mrsoundhar 0:ae306d3f6076 941 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
mrsoundhar 0:ae306d3f6076 942 uint32_t RESERVED7[8];
mrsoundhar 0:ae306d3f6076 943 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
mrsoundhar 0:ae306d3f6076 944 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
mrsoundhar 0:ae306d3f6076 945 } TPI_Type;
mrsoundhar 0:ae306d3f6076 946
mrsoundhar 0:ae306d3f6076 947 /* TPI Asynchronous Clock Prescaler Register Definitions */
mrsoundhar 0:ae306d3f6076 948 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
mrsoundhar 0:ae306d3f6076 949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
mrsoundhar 0:ae306d3f6076 950
mrsoundhar 0:ae306d3f6076 951 /* TPI Selected Pin Protocol Register Definitions */
mrsoundhar 0:ae306d3f6076 952 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
mrsoundhar 0:ae306d3f6076 953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
mrsoundhar 0:ae306d3f6076 954
mrsoundhar 0:ae306d3f6076 955 /* TPI Formatter and Flush Status Register Definitions */
mrsoundhar 0:ae306d3f6076 956 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
mrsoundhar 0:ae306d3f6076 957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
mrsoundhar 0:ae306d3f6076 958
mrsoundhar 0:ae306d3f6076 959 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
mrsoundhar 0:ae306d3f6076 960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
mrsoundhar 0:ae306d3f6076 961
mrsoundhar 0:ae306d3f6076 962 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
mrsoundhar 0:ae306d3f6076 963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
mrsoundhar 0:ae306d3f6076 964
mrsoundhar 0:ae306d3f6076 965 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
mrsoundhar 0:ae306d3f6076 966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
mrsoundhar 0:ae306d3f6076 967
mrsoundhar 0:ae306d3f6076 968 /* TPI Formatter and Flush Control Register Definitions */
mrsoundhar 0:ae306d3f6076 969 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
mrsoundhar 0:ae306d3f6076 970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
mrsoundhar 0:ae306d3f6076 971
mrsoundhar 0:ae306d3f6076 972 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
mrsoundhar 0:ae306d3f6076 973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
mrsoundhar 0:ae306d3f6076 974
mrsoundhar 0:ae306d3f6076 975 /* TPI TRIGGER Register Definitions */
mrsoundhar 0:ae306d3f6076 976 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
mrsoundhar 0:ae306d3f6076 977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
mrsoundhar 0:ae306d3f6076 978
mrsoundhar 0:ae306d3f6076 979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
mrsoundhar 0:ae306d3f6076 980 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
mrsoundhar 0:ae306d3f6076 981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
mrsoundhar 0:ae306d3f6076 982
mrsoundhar 0:ae306d3f6076 983 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
mrsoundhar 0:ae306d3f6076 984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
mrsoundhar 0:ae306d3f6076 985
mrsoundhar 0:ae306d3f6076 986 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
mrsoundhar 0:ae306d3f6076 987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
mrsoundhar 0:ae306d3f6076 988
mrsoundhar 0:ae306d3f6076 989 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
mrsoundhar 0:ae306d3f6076 990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
mrsoundhar 0:ae306d3f6076 991
mrsoundhar 0:ae306d3f6076 992 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
mrsoundhar 0:ae306d3f6076 993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
mrsoundhar 0:ae306d3f6076 994
mrsoundhar 0:ae306d3f6076 995 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
mrsoundhar 0:ae306d3f6076 996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
mrsoundhar 0:ae306d3f6076 997
mrsoundhar 0:ae306d3f6076 998 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
mrsoundhar 0:ae306d3f6076 999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
mrsoundhar 0:ae306d3f6076 1000
mrsoundhar 0:ae306d3f6076 1001 /* TPI ITATBCTR2 Register Definitions */
mrsoundhar 0:ae306d3f6076 1002 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
mrsoundhar 0:ae306d3f6076 1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
mrsoundhar 0:ae306d3f6076 1004
mrsoundhar 0:ae306d3f6076 1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
mrsoundhar 0:ae306d3f6076 1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
mrsoundhar 0:ae306d3f6076 1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
mrsoundhar 0:ae306d3f6076 1008
mrsoundhar 0:ae306d3f6076 1009 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
mrsoundhar 0:ae306d3f6076 1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
mrsoundhar 0:ae306d3f6076 1011
mrsoundhar 0:ae306d3f6076 1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
mrsoundhar 0:ae306d3f6076 1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
mrsoundhar 0:ae306d3f6076 1014
mrsoundhar 0:ae306d3f6076 1015 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
mrsoundhar 0:ae306d3f6076 1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
mrsoundhar 0:ae306d3f6076 1017
mrsoundhar 0:ae306d3f6076 1018 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
mrsoundhar 0:ae306d3f6076 1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
mrsoundhar 0:ae306d3f6076 1020
mrsoundhar 0:ae306d3f6076 1021 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
mrsoundhar 0:ae306d3f6076 1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
mrsoundhar 0:ae306d3f6076 1023
mrsoundhar 0:ae306d3f6076 1024 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
mrsoundhar 0:ae306d3f6076 1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
mrsoundhar 0:ae306d3f6076 1026
mrsoundhar 0:ae306d3f6076 1027 /* TPI ITATBCTR0 Register Definitions */
mrsoundhar 0:ae306d3f6076 1028 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
mrsoundhar 0:ae306d3f6076 1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
mrsoundhar 0:ae306d3f6076 1030
mrsoundhar 0:ae306d3f6076 1031 /* TPI Integration Mode Control Register Definitions */
mrsoundhar 0:ae306d3f6076 1032 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
mrsoundhar 0:ae306d3f6076 1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
mrsoundhar 0:ae306d3f6076 1034
mrsoundhar 0:ae306d3f6076 1035 /* TPI DEVID Register Definitions */
mrsoundhar 0:ae306d3f6076 1036 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
mrsoundhar 0:ae306d3f6076 1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
mrsoundhar 0:ae306d3f6076 1038
mrsoundhar 0:ae306d3f6076 1039 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
mrsoundhar 0:ae306d3f6076 1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
mrsoundhar 0:ae306d3f6076 1041
mrsoundhar 0:ae306d3f6076 1042 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
mrsoundhar 0:ae306d3f6076 1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
mrsoundhar 0:ae306d3f6076 1044
mrsoundhar 0:ae306d3f6076 1045 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
mrsoundhar 0:ae306d3f6076 1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
mrsoundhar 0:ae306d3f6076 1047
mrsoundhar 0:ae306d3f6076 1048 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
mrsoundhar 0:ae306d3f6076 1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
mrsoundhar 0:ae306d3f6076 1050
mrsoundhar 0:ae306d3f6076 1051 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
mrsoundhar 0:ae306d3f6076 1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
mrsoundhar 0:ae306d3f6076 1053
mrsoundhar 0:ae306d3f6076 1054 /* TPI DEVTYPE Register Definitions */
mrsoundhar 0:ae306d3f6076 1055 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
mrsoundhar 0:ae306d3f6076 1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
mrsoundhar 0:ae306d3f6076 1057
mrsoundhar 0:ae306d3f6076 1058 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
mrsoundhar 0:ae306d3f6076 1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
mrsoundhar 0:ae306d3f6076 1060
mrsoundhar 0:ae306d3f6076 1061 /*@}*/ /* end of group CMSIS_TPI */
mrsoundhar 0:ae306d3f6076 1062
mrsoundhar 0:ae306d3f6076 1063
mrsoundhar 0:ae306d3f6076 1064 #if (__MPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 1065 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 1066 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mrsoundhar 0:ae306d3f6076 1067 \brief Type definitions for the Memory Protection Unit (MPU)
mrsoundhar 0:ae306d3f6076 1068 @{
mrsoundhar 0:ae306d3f6076 1069 */
mrsoundhar 0:ae306d3f6076 1070
mrsoundhar 0:ae306d3f6076 1071 /** \brief Structure type to access the Memory Protection Unit (MPU).
mrsoundhar 0:ae306d3f6076 1072 */
mrsoundhar 0:ae306d3f6076 1073 typedef struct
mrsoundhar 0:ae306d3f6076 1074 {
mrsoundhar 0:ae306d3f6076 1075 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mrsoundhar 0:ae306d3f6076 1076 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mrsoundhar 0:ae306d3f6076 1077 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mrsoundhar 0:ae306d3f6076 1078 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mrsoundhar 0:ae306d3f6076 1079 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mrsoundhar 0:ae306d3f6076 1080 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
mrsoundhar 0:ae306d3f6076 1081 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
mrsoundhar 0:ae306d3f6076 1082 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
mrsoundhar 0:ae306d3f6076 1083 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
mrsoundhar 0:ae306d3f6076 1084 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
mrsoundhar 0:ae306d3f6076 1085 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
mrsoundhar 0:ae306d3f6076 1086 } MPU_Type;
mrsoundhar 0:ae306d3f6076 1087
mrsoundhar 0:ae306d3f6076 1088 /* MPU Type Register */
mrsoundhar 0:ae306d3f6076 1089 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mrsoundhar 0:ae306d3f6076 1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mrsoundhar 0:ae306d3f6076 1091
mrsoundhar 0:ae306d3f6076 1092 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mrsoundhar 0:ae306d3f6076 1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mrsoundhar 0:ae306d3f6076 1094
mrsoundhar 0:ae306d3f6076 1095 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mrsoundhar 0:ae306d3f6076 1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
mrsoundhar 0:ae306d3f6076 1097
mrsoundhar 0:ae306d3f6076 1098 /* MPU Control Register */
mrsoundhar 0:ae306d3f6076 1099 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mrsoundhar 0:ae306d3f6076 1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mrsoundhar 0:ae306d3f6076 1101
mrsoundhar 0:ae306d3f6076 1102 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mrsoundhar 0:ae306d3f6076 1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mrsoundhar 0:ae306d3f6076 1104
mrsoundhar 0:ae306d3f6076 1105 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mrsoundhar 0:ae306d3f6076 1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
mrsoundhar 0:ae306d3f6076 1107
mrsoundhar 0:ae306d3f6076 1108 /* MPU Region Number Register */
mrsoundhar 0:ae306d3f6076 1109 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mrsoundhar 0:ae306d3f6076 1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
mrsoundhar 0:ae306d3f6076 1111
mrsoundhar 0:ae306d3f6076 1112 /* MPU Region Base Address Register */
mrsoundhar 0:ae306d3f6076 1113 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
mrsoundhar 0:ae306d3f6076 1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mrsoundhar 0:ae306d3f6076 1115
mrsoundhar 0:ae306d3f6076 1116 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mrsoundhar 0:ae306d3f6076 1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mrsoundhar 0:ae306d3f6076 1118
mrsoundhar 0:ae306d3f6076 1119 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mrsoundhar 0:ae306d3f6076 1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
mrsoundhar 0:ae306d3f6076 1121
mrsoundhar 0:ae306d3f6076 1122 /* MPU Region Attribute and Size Register */
mrsoundhar 0:ae306d3f6076 1123 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mrsoundhar 0:ae306d3f6076 1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mrsoundhar 0:ae306d3f6076 1125
mrsoundhar 0:ae306d3f6076 1126 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mrsoundhar 0:ae306d3f6076 1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mrsoundhar 0:ae306d3f6076 1128
mrsoundhar 0:ae306d3f6076 1129 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mrsoundhar 0:ae306d3f6076 1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mrsoundhar 0:ae306d3f6076 1131
mrsoundhar 0:ae306d3f6076 1132 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mrsoundhar 0:ae306d3f6076 1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mrsoundhar 0:ae306d3f6076 1134
mrsoundhar 0:ae306d3f6076 1135 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mrsoundhar 0:ae306d3f6076 1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mrsoundhar 0:ae306d3f6076 1137
mrsoundhar 0:ae306d3f6076 1138 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mrsoundhar 0:ae306d3f6076 1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mrsoundhar 0:ae306d3f6076 1140
mrsoundhar 0:ae306d3f6076 1141 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mrsoundhar 0:ae306d3f6076 1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mrsoundhar 0:ae306d3f6076 1143
mrsoundhar 0:ae306d3f6076 1144 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mrsoundhar 0:ae306d3f6076 1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mrsoundhar 0:ae306d3f6076 1146
mrsoundhar 0:ae306d3f6076 1147 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mrsoundhar 0:ae306d3f6076 1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mrsoundhar 0:ae306d3f6076 1149
mrsoundhar 0:ae306d3f6076 1150 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mrsoundhar 0:ae306d3f6076 1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
mrsoundhar 0:ae306d3f6076 1152
mrsoundhar 0:ae306d3f6076 1153 /*@} end of group CMSIS_MPU */
mrsoundhar 0:ae306d3f6076 1154 #endif
mrsoundhar 0:ae306d3f6076 1155
mrsoundhar 0:ae306d3f6076 1156
mrsoundhar 0:ae306d3f6076 1157 #if (__FPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 1158 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 1159 \defgroup CMSIS_FPU Floating Point Unit (FPU)
mrsoundhar 0:ae306d3f6076 1160 \brief Type definitions for the Floating Point Unit (FPU)
mrsoundhar 0:ae306d3f6076 1161 @{
mrsoundhar 0:ae306d3f6076 1162 */
mrsoundhar 0:ae306d3f6076 1163
mrsoundhar 0:ae306d3f6076 1164 /** \brief Structure type to access the Floating Point Unit (FPU).
mrsoundhar 0:ae306d3f6076 1165 */
mrsoundhar 0:ae306d3f6076 1166 typedef struct
mrsoundhar 0:ae306d3f6076 1167 {
mrsoundhar 0:ae306d3f6076 1168 uint32_t RESERVED0[1];
mrsoundhar 0:ae306d3f6076 1169 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
mrsoundhar 0:ae306d3f6076 1170 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
mrsoundhar 0:ae306d3f6076 1171 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
mrsoundhar 0:ae306d3f6076 1172 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
mrsoundhar 0:ae306d3f6076 1173 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
mrsoundhar 0:ae306d3f6076 1174 } FPU_Type;
mrsoundhar 0:ae306d3f6076 1175
mrsoundhar 0:ae306d3f6076 1176 /* Floating-Point Context Control Register */
mrsoundhar 0:ae306d3f6076 1177 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
mrsoundhar 0:ae306d3f6076 1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
mrsoundhar 0:ae306d3f6076 1179
mrsoundhar 0:ae306d3f6076 1180 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
mrsoundhar 0:ae306d3f6076 1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
mrsoundhar 0:ae306d3f6076 1182
mrsoundhar 0:ae306d3f6076 1183 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
mrsoundhar 0:ae306d3f6076 1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
mrsoundhar 0:ae306d3f6076 1185
mrsoundhar 0:ae306d3f6076 1186 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
mrsoundhar 0:ae306d3f6076 1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
mrsoundhar 0:ae306d3f6076 1188
mrsoundhar 0:ae306d3f6076 1189 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
mrsoundhar 0:ae306d3f6076 1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
mrsoundhar 0:ae306d3f6076 1191
mrsoundhar 0:ae306d3f6076 1192 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
mrsoundhar 0:ae306d3f6076 1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
mrsoundhar 0:ae306d3f6076 1194
mrsoundhar 0:ae306d3f6076 1195 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
mrsoundhar 0:ae306d3f6076 1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
mrsoundhar 0:ae306d3f6076 1197
mrsoundhar 0:ae306d3f6076 1198 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
mrsoundhar 0:ae306d3f6076 1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
mrsoundhar 0:ae306d3f6076 1200
mrsoundhar 0:ae306d3f6076 1201 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
mrsoundhar 0:ae306d3f6076 1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
mrsoundhar 0:ae306d3f6076 1203
mrsoundhar 0:ae306d3f6076 1204 /* Floating-Point Context Address Register */
mrsoundhar 0:ae306d3f6076 1205 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
mrsoundhar 0:ae306d3f6076 1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
mrsoundhar 0:ae306d3f6076 1207
mrsoundhar 0:ae306d3f6076 1208 /* Floating-Point Default Status Control Register */
mrsoundhar 0:ae306d3f6076 1209 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
mrsoundhar 0:ae306d3f6076 1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
mrsoundhar 0:ae306d3f6076 1211
mrsoundhar 0:ae306d3f6076 1212 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
mrsoundhar 0:ae306d3f6076 1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
mrsoundhar 0:ae306d3f6076 1214
mrsoundhar 0:ae306d3f6076 1215 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
mrsoundhar 0:ae306d3f6076 1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
mrsoundhar 0:ae306d3f6076 1217
mrsoundhar 0:ae306d3f6076 1218 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
mrsoundhar 0:ae306d3f6076 1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
mrsoundhar 0:ae306d3f6076 1220
mrsoundhar 0:ae306d3f6076 1221 /* Media and FP Feature Register 0 */
mrsoundhar 0:ae306d3f6076 1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
mrsoundhar 0:ae306d3f6076 1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
mrsoundhar 0:ae306d3f6076 1224
mrsoundhar 0:ae306d3f6076 1225 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
mrsoundhar 0:ae306d3f6076 1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
mrsoundhar 0:ae306d3f6076 1227
mrsoundhar 0:ae306d3f6076 1228 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
mrsoundhar 0:ae306d3f6076 1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
mrsoundhar 0:ae306d3f6076 1230
mrsoundhar 0:ae306d3f6076 1231 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
mrsoundhar 0:ae306d3f6076 1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
mrsoundhar 0:ae306d3f6076 1233
mrsoundhar 0:ae306d3f6076 1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
mrsoundhar 0:ae306d3f6076 1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
mrsoundhar 0:ae306d3f6076 1236
mrsoundhar 0:ae306d3f6076 1237 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
mrsoundhar 0:ae306d3f6076 1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
mrsoundhar 0:ae306d3f6076 1239
mrsoundhar 0:ae306d3f6076 1240 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
mrsoundhar 0:ae306d3f6076 1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
mrsoundhar 0:ae306d3f6076 1242
mrsoundhar 0:ae306d3f6076 1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
mrsoundhar 0:ae306d3f6076 1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
mrsoundhar 0:ae306d3f6076 1245
mrsoundhar 0:ae306d3f6076 1246 /* Media and FP Feature Register 1 */
mrsoundhar 0:ae306d3f6076 1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
mrsoundhar 0:ae306d3f6076 1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
mrsoundhar 0:ae306d3f6076 1249
mrsoundhar 0:ae306d3f6076 1250 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
mrsoundhar 0:ae306d3f6076 1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
mrsoundhar 0:ae306d3f6076 1252
mrsoundhar 0:ae306d3f6076 1253 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
mrsoundhar 0:ae306d3f6076 1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
mrsoundhar 0:ae306d3f6076 1255
mrsoundhar 0:ae306d3f6076 1256 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
mrsoundhar 0:ae306d3f6076 1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
mrsoundhar 0:ae306d3f6076 1258
mrsoundhar 0:ae306d3f6076 1259 /*@} end of group CMSIS_FPU */
mrsoundhar 0:ae306d3f6076 1260 #endif
mrsoundhar 0:ae306d3f6076 1261
mrsoundhar 0:ae306d3f6076 1262
mrsoundhar 0:ae306d3f6076 1263 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 1264 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mrsoundhar 0:ae306d3f6076 1265 \brief Type definitions for the Core Debug Registers
mrsoundhar 0:ae306d3f6076 1266 @{
mrsoundhar 0:ae306d3f6076 1267 */
mrsoundhar 0:ae306d3f6076 1268
mrsoundhar 0:ae306d3f6076 1269 /** \brief Structure type to access the Core Debug Register (CoreDebug).
mrsoundhar 0:ae306d3f6076 1270 */
mrsoundhar 0:ae306d3f6076 1271 typedef struct
mrsoundhar 0:ae306d3f6076 1272 {
mrsoundhar 0:ae306d3f6076 1273 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
mrsoundhar 0:ae306d3f6076 1274 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
mrsoundhar 0:ae306d3f6076 1275 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
mrsoundhar 0:ae306d3f6076 1276 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
mrsoundhar 0:ae306d3f6076 1277 } CoreDebug_Type;
mrsoundhar 0:ae306d3f6076 1278
mrsoundhar 0:ae306d3f6076 1279 /* Debug Halting Control and Status Register */
mrsoundhar 0:ae306d3f6076 1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
mrsoundhar 0:ae306d3f6076 1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
mrsoundhar 0:ae306d3f6076 1282
mrsoundhar 0:ae306d3f6076 1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
mrsoundhar 0:ae306d3f6076 1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
mrsoundhar 0:ae306d3f6076 1285
mrsoundhar 0:ae306d3f6076 1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
mrsoundhar 0:ae306d3f6076 1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
mrsoundhar 0:ae306d3f6076 1288
mrsoundhar 0:ae306d3f6076 1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
mrsoundhar 0:ae306d3f6076 1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
mrsoundhar 0:ae306d3f6076 1291
mrsoundhar 0:ae306d3f6076 1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
mrsoundhar 0:ae306d3f6076 1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
mrsoundhar 0:ae306d3f6076 1294
mrsoundhar 0:ae306d3f6076 1295 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
mrsoundhar 0:ae306d3f6076 1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
mrsoundhar 0:ae306d3f6076 1297
mrsoundhar 0:ae306d3f6076 1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
mrsoundhar 0:ae306d3f6076 1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
mrsoundhar 0:ae306d3f6076 1300
mrsoundhar 0:ae306d3f6076 1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
mrsoundhar 0:ae306d3f6076 1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
mrsoundhar 0:ae306d3f6076 1303
mrsoundhar 0:ae306d3f6076 1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
mrsoundhar 0:ae306d3f6076 1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
mrsoundhar 0:ae306d3f6076 1306
mrsoundhar 0:ae306d3f6076 1307 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
mrsoundhar 0:ae306d3f6076 1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
mrsoundhar 0:ae306d3f6076 1309
mrsoundhar 0:ae306d3f6076 1310 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
mrsoundhar 0:ae306d3f6076 1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
mrsoundhar 0:ae306d3f6076 1312
mrsoundhar 0:ae306d3f6076 1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
mrsoundhar 0:ae306d3f6076 1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
mrsoundhar 0:ae306d3f6076 1315
mrsoundhar 0:ae306d3f6076 1316 /* Debug Core Register Selector Register */
mrsoundhar 0:ae306d3f6076 1317 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
mrsoundhar 0:ae306d3f6076 1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
mrsoundhar 0:ae306d3f6076 1319
mrsoundhar 0:ae306d3f6076 1320 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
mrsoundhar 0:ae306d3f6076 1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
mrsoundhar 0:ae306d3f6076 1322
mrsoundhar 0:ae306d3f6076 1323 /* Debug Exception and Monitor Control Register */
mrsoundhar 0:ae306d3f6076 1324 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
mrsoundhar 0:ae306d3f6076 1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
mrsoundhar 0:ae306d3f6076 1326
mrsoundhar 0:ae306d3f6076 1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
mrsoundhar 0:ae306d3f6076 1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
mrsoundhar 0:ae306d3f6076 1329
mrsoundhar 0:ae306d3f6076 1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
mrsoundhar 0:ae306d3f6076 1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
mrsoundhar 0:ae306d3f6076 1332
mrsoundhar 0:ae306d3f6076 1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
mrsoundhar 0:ae306d3f6076 1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
mrsoundhar 0:ae306d3f6076 1335
mrsoundhar 0:ae306d3f6076 1336 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
mrsoundhar 0:ae306d3f6076 1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
mrsoundhar 0:ae306d3f6076 1338
mrsoundhar 0:ae306d3f6076 1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
mrsoundhar 0:ae306d3f6076 1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
mrsoundhar 0:ae306d3f6076 1341
mrsoundhar 0:ae306d3f6076 1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
mrsoundhar 0:ae306d3f6076 1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
mrsoundhar 0:ae306d3f6076 1344
mrsoundhar 0:ae306d3f6076 1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
mrsoundhar 0:ae306d3f6076 1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
mrsoundhar 0:ae306d3f6076 1347
mrsoundhar 0:ae306d3f6076 1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
mrsoundhar 0:ae306d3f6076 1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
mrsoundhar 0:ae306d3f6076 1350
mrsoundhar 0:ae306d3f6076 1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
mrsoundhar 0:ae306d3f6076 1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
mrsoundhar 0:ae306d3f6076 1353
mrsoundhar 0:ae306d3f6076 1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
mrsoundhar 0:ae306d3f6076 1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
mrsoundhar 0:ae306d3f6076 1356
mrsoundhar 0:ae306d3f6076 1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
mrsoundhar 0:ae306d3f6076 1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
mrsoundhar 0:ae306d3f6076 1359
mrsoundhar 0:ae306d3f6076 1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
mrsoundhar 0:ae306d3f6076 1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
mrsoundhar 0:ae306d3f6076 1362
mrsoundhar 0:ae306d3f6076 1363 /*@} end of group CMSIS_CoreDebug */
mrsoundhar 0:ae306d3f6076 1364
mrsoundhar 0:ae306d3f6076 1365
mrsoundhar 0:ae306d3f6076 1366 /** \ingroup CMSIS_core_register
mrsoundhar 0:ae306d3f6076 1367 \defgroup CMSIS_core_base Core Definitions
mrsoundhar 0:ae306d3f6076 1368 \brief Definitions for base addresses, unions, and structures.
mrsoundhar 0:ae306d3f6076 1369 @{
mrsoundhar 0:ae306d3f6076 1370 */
mrsoundhar 0:ae306d3f6076 1371
mrsoundhar 0:ae306d3f6076 1372 /* Memory mapping of Cortex-M4 Hardware */
mrsoundhar 0:ae306d3f6076 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mrsoundhar 0:ae306d3f6076 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
mrsoundhar 0:ae306d3f6076 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
mrsoundhar 0:ae306d3f6076 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
mrsoundhar 0:ae306d3f6076 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
mrsoundhar 0:ae306d3f6076 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mrsoundhar 0:ae306d3f6076 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mrsoundhar 0:ae306d3f6076 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mrsoundhar 0:ae306d3f6076 1381
mrsoundhar 0:ae306d3f6076 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mrsoundhar 0:ae306d3f6076 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mrsoundhar 0:ae306d3f6076 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mrsoundhar 0:ae306d3f6076 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mrsoundhar 0:ae306d3f6076 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
mrsoundhar 0:ae306d3f6076 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
mrsoundhar 0:ae306d3f6076 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
mrsoundhar 0:ae306d3f6076 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
mrsoundhar 0:ae306d3f6076 1390
mrsoundhar 0:ae306d3f6076 1391 #if (__MPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mrsoundhar 0:ae306d3f6076 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mrsoundhar 0:ae306d3f6076 1394 #endif
mrsoundhar 0:ae306d3f6076 1395
mrsoundhar 0:ae306d3f6076 1396 #if (__FPU_PRESENT == 1)
mrsoundhar 0:ae306d3f6076 1397 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
mrsoundhar 0:ae306d3f6076 1398 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
mrsoundhar 0:ae306d3f6076 1399 #endif
mrsoundhar 0:ae306d3f6076 1400
mrsoundhar 0:ae306d3f6076 1401 /*@} */
mrsoundhar 0:ae306d3f6076 1402
mrsoundhar 0:ae306d3f6076 1403
mrsoundhar 0:ae306d3f6076 1404
mrsoundhar 0:ae306d3f6076 1405 /*******************************************************************************
mrsoundhar 0:ae306d3f6076 1406 * Hardware Abstraction Layer
mrsoundhar 0:ae306d3f6076 1407 Core Function Interface contains:
mrsoundhar 0:ae306d3f6076 1408 - Core NVIC Functions
mrsoundhar 0:ae306d3f6076 1409 - Core SysTick Functions
mrsoundhar 0:ae306d3f6076 1410 - Core Debug Functions
mrsoundhar 0:ae306d3f6076 1411 - Core Register Access Functions
mrsoundhar 0:ae306d3f6076 1412 ******************************************************************************/
mrsoundhar 0:ae306d3f6076 1413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mrsoundhar 0:ae306d3f6076 1414 */
mrsoundhar 0:ae306d3f6076 1415
mrsoundhar 0:ae306d3f6076 1416
mrsoundhar 0:ae306d3f6076 1417
mrsoundhar 0:ae306d3f6076 1418 /* ########################## NVIC functions #################################### */
mrsoundhar 0:ae306d3f6076 1419 /** \ingroup CMSIS_Core_FunctionInterface
mrsoundhar 0:ae306d3f6076 1420 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mrsoundhar 0:ae306d3f6076 1421 \brief Functions that manage interrupts and exceptions via the NVIC.
mrsoundhar 0:ae306d3f6076 1422 @{
mrsoundhar 0:ae306d3f6076 1423 */
mrsoundhar 0:ae306d3f6076 1424
mrsoundhar 0:ae306d3f6076 1425 /** \brief Set Priority Grouping
mrsoundhar 0:ae306d3f6076 1426
mrsoundhar 0:ae306d3f6076 1427 The function sets the priority grouping field using the required unlock sequence.
mrsoundhar 0:ae306d3f6076 1428 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mrsoundhar 0:ae306d3f6076 1429 Only values from 0..7 are used.
mrsoundhar 0:ae306d3f6076 1430 In case of a conflict between priority grouping and available
mrsoundhar 0:ae306d3f6076 1431 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mrsoundhar 0:ae306d3f6076 1432
mrsoundhar 0:ae306d3f6076 1433 \param [in] PriorityGroup Priority grouping field.
mrsoundhar 0:ae306d3f6076 1434 */
mrsoundhar 0:ae306d3f6076 1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mrsoundhar 0:ae306d3f6076 1436 {
mrsoundhar 0:ae306d3f6076 1437 uint32_t reg_value;
mrsoundhar 0:ae306d3f6076 1438 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
mrsoundhar 0:ae306d3f6076 1439
mrsoundhar 0:ae306d3f6076 1440 reg_value = SCB->AIRCR; /* read old register configuration */
mrsoundhar 0:ae306d3f6076 1441 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
mrsoundhar 0:ae306d3f6076 1442 reg_value = (reg_value |
mrsoundhar 0:ae306d3f6076 1443 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mrsoundhar 0:ae306d3f6076 1444 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
mrsoundhar 0:ae306d3f6076 1445 SCB->AIRCR = reg_value;
mrsoundhar 0:ae306d3f6076 1446 }
mrsoundhar 0:ae306d3f6076 1447
mrsoundhar 0:ae306d3f6076 1448
mrsoundhar 0:ae306d3f6076 1449 /** \brief Get Priority Grouping
mrsoundhar 0:ae306d3f6076 1450
mrsoundhar 0:ae306d3f6076 1451 The function reads the priority grouping field from the NVIC Interrupt Controller.
mrsoundhar 0:ae306d3f6076 1452
mrsoundhar 0:ae306d3f6076 1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mrsoundhar 0:ae306d3f6076 1454 */
mrsoundhar 0:ae306d3f6076 1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
mrsoundhar 0:ae306d3f6076 1456 {
mrsoundhar 0:ae306d3f6076 1457 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
mrsoundhar 0:ae306d3f6076 1458 }
mrsoundhar 0:ae306d3f6076 1459
mrsoundhar 0:ae306d3f6076 1460
mrsoundhar 0:ae306d3f6076 1461 /** \brief Enable External Interrupt
mrsoundhar 0:ae306d3f6076 1462
mrsoundhar 0:ae306d3f6076 1463 The function enables a device-specific interrupt in the NVIC interrupt controller.
mrsoundhar 0:ae306d3f6076 1464
mrsoundhar 0:ae306d3f6076 1465 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:ae306d3f6076 1466 */
mrsoundhar 0:ae306d3f6076 1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mrsoundhar 0:ae306d3f6076 1468 {
mrsoundhar 0:ae306d3f6076 1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
mrsoundhar 0:ae306d3f6076 1470 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
mrsoundhar 0:ae306d3f6076 1471 }
mrsoundhar 0:ae306d3f6076 1472
mrsoundhar 0:ae306d3f6076 1473
mrsoundhar 0:ae306d3f6076 1474 /** \brief Disable External Interrupt
mrsoundhar 0:ae306d3f6076 1475
mrsoundhar 0:ae306d3f6076 1476 The function disables a device-specific interrupt in the NVIC interrupt controller.
mrsoundhar 0:ae306d3f6076 1477
mrsoundhar 0:ae306d3f6076 1478 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:ae306d3f6076 1479 */
mrsoundhar 0:ae306d3f6076 1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mrsoundhar 0:ae306d3f6076 1481 {
mrsoundhar 0:ae306d3f6076 1482 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
mrsoundhar 0:ae306d3f6076 1483 }
mrsoundhar 0:ae306d3f6076 1484
mrsoundhar 0:ae306d3f6076 1485
mrsoundhar 0:ae306d3f6076 1486 /** \brief Get Pending Interrupt
mrsoundhar 0:ae306d3f6076 1487
mrsoundhar 0:ae306d3f6076 1488 The function reads the pending register in the NVIC and returns the pending bit
mrsoundhar 0:ae306d3f6076 1489 for the specified interrupt.
mrsoundhar 0:ae306d3f6076 1490
mrsoundhar 0:ae306d3f6076 1491 \param [in] IRQn Interrupt number.
mrsoundhar 0:ae306d3f6076 1492
mrsoundhar 0:ae306d3f6076 1493 \return 0 Interrupt status is not pending.
mrsoundhar 0:ae306d3f6076 1494 \return 1 Interrupt status is pending.
mrsoundhar 0:ae306d3f6076 1495 */
mrsoundhar 0:ae306d3f6076 1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:ae306d3f6076 1497 {
mrsoundhar 0:ae306d3f6076 1498 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
mrsoundhar 0:ae306d3f6076 1499 }
mrsoundhar 0:ae306d3f6076 1500
mrsoundhar 0:ae306d3f6076 1501
mrsoundhar 0:ae306d3f6076 1502 /** \brief Set Pending Interrupt
mrsoundhar 0:ae306d3f6076 1503
mrsoundhar 0:ae306d3f6076 1504 The function sets the pending bit of an external interrupt.
mrsoundhar 0:ae306d3f6076 1505
mrsoundhar 0:ae306d3f6076 1506 \param [in] IRQn Interrupt number. Value cannot be negative.
mrsoundhar 0:ae306d3f6076 1507 */
mrsoundhar 0:ae306d3f6076 1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:ae306d3f6076 1509 {
mrsoundhar 0:ae306d3f6076 1510 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
mrsoundhar 0:ae306d3f6076 1511 }
mrsoundhar 0:ae306d3f6076 1512
mrsoundhar 0:ae306d3f6076 1513
mrsoundhar 0:ae306d3f6076 1514 /** \brief Clear Pending Interrupt
mrsoundhar 0:ae306d3f6076 1515
mrsoundhar 0:ae306d3f6076 1516 The function clears the pending bit of an external interrupt.
mrsoundhar 0:ae306d3f6076 1517
mrsoundhar 0:ae306d3f6076 1518 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:ae306d3f6076 1519 */
mrsoundhar 0:ae306d3f6076 1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:ae306d3f6076 1521 {
mrsoundhar 0:ae306d3f6076 1522 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mrsoundhar 0:ae306d3f6076 1523 }
mrsoundhar 0:ae306d3f6076 1524
mrsoundhar 0:ae306d3f6076 1525
mrsoundhar 0:ae306d3f6076 1526 /** \brief Get Active Interrupt
mrsoundhar 0:ae306d3f6076 1527
mrsoundhar 0:ae306d3f6076 1528 The function reads the active register in NVIC and returns the active bit.
mrsoundhar 0:ae306d3f6076 1529
mrsoundhar 0:ae306d3f6076 1530 \param [in] IRQn Interrupt number.
mrsoundhar 0:ae306d3f6076 1531
mrsoundhar 0:ae306d3f6076 1532 \return 0 Interrupt status is not active.
mrsoundhar 0:ae306d3f6076 1533 \return 1 Interrupt status is active.
mrsoundhar 0:ae306d3f6076 1534 */
mrsoundhar 0:ae306d3f6076 1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
mrsoundhar 0:ae306d3f6076 1536 {
mrsoundhar 0:ae306d3f6076 1537 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
mrsoundhar 0:ae306d3f6076 1538 }
mrsoundhar 0:ae306d3f6076 1539
mrsoundhar 0:ae306d3f6076 1540
mrsoundhar 0:ae306d3f6076 1541 /** \brief Set Interrupt Priority
mrsoundhar 0:ae306d3f6076 1542
mrsoundhar 0:ae306d3f6076 1543 The function sets the priority of an interrupt.
mrsoundhar 0:ae306d3f6076 1544
mrsoundhar 0:ae306d3f6076 1545 \note The priority cannot be set for every core interrupt.
mrsoundhar 0:ae306d3f6076 1546
mrsoundhar 0:ae306d3f6076 1547 \param [in] IRQn Interrupt number.
mrsoundhar 0:ae306d3f6076 1548 \param [in] priority Priority to set.
mrsoundhar 0:ae306d3f6076 1549 */
mrsoundhar 0:ae306d3f6076 1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mrsoundhar 0:ae306d3f6076 1551 {
mrsoundhar 0:ae306d3f6076 1552 if(IRQn < 0) {
mrsoundhar 0:ae306d3f6076 1553 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
mrsoundhar 0:ae306d3f6076 1554 else {
mrsoundhar 0:ae306d3f6076 1555 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
mrsoundhar 0:ae306d3f6076 1556 }
mrsoundhar 0:ae306d3f6076 1557
mrsoundhar 0:ae306d3f6076 1558
mrsoundhar 0:ae306d3f6076 1559 /** \brief Get Interrupt Priority
mrsoundhar 0:ae306d3f6076 1560
mrsoundhar 0:ae306d3f6076 1561 The function reads the priority of an interrupt. The interrupt
mrsoundhar 0:ae306d3f6076 1562 number can be positive to specify an external (device specific)
mrsoundhar 0:ae306d3f6076 1563 interrupt, or negative to specify an internal (core) interrupt.
mrsoundhar 0:ae306d3f6076 1564
mrsoundhar 0:ae306d3f6076 1565
mrsoundhar 0:ae306d3f6076 1566 \param [in] IRQn Interrupt number.
mrsoundhar 0:ae306d3f6076 1567 \return Interrupt Priority. Value is aligned automatically to the implemented
mrsoundhar 0:ae306d3f6076 1568 priority bits of the microcontroller.
mrsoundhar 0:ae306d3f6076 1569 */
mrsoundhar 0:ae306d3f6076 1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mrsoundhar 0:ae306d3f6076 1571 {
mrsoundhar 0:ae306d3f6076 1572
mrsoundhar 0:ae306d3f6076 1573 if(IRQn < 0) {
mrsoundhar 0:ae306d3f6076 1574 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
mrsoundhar 0:ae306d3f6076 1575 else {
mrsoundhar 0:ae306d3f6076 1576 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mrsoundhar 0:ae306d3f6076 1577 }
mrsoundhar 0:ae306d3f6076 1578
mrsoundhar 0:ae306d3f6076 1579
mrsoundhar 0:ae306d3f6076 1580 /** \brief Encode Priority
mrsoundhar 0:ae306d3f6076 1581
mrsoundhar 0:ae306d3f6076 1582 The function encodes the priority for an interrupt with the given priority group,
mrsoundhar 0:ae306d3f6076 1583 preemptive priority value, and subpriority value.
mrsoundhar 0:ae306d3f6076 1584 In case of a conflict between priority grouping and available
mrsoundhar 0:ae306d3f6076 1585 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
mrsoundhar 0:ae306d3f6076 1586
mrsoundhar 0:ae306d3f6076 1587 \param [in] PriorityGroup Used priority group.
mrsoundhar 0:ae306d3f6076 1588 \param [in] PreemptPriority Preemptive priority value (starting from 0).
mrsoundhar 0:ae306d3f6076 1589 \param [in] SubPriority Subpriority value (starting from 0).
mrsoundhar 0:ae306d3f6076 1590 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mrsoundhar 0:ae306d3f6076 1591 */
mrsoundhar 0:ae306d3f6076 1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mrsoundhar 0:ae306d3f6076 1593 {
mrsoundhar 0:ae306d3f6076 1594 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
mrsoundhar 0:ae306d3f6076 1595 uint32_t PreemptPriorityBits;
mrsoundhar 0:ae306d3f6076 1596 uint32_t SubPriorityBits;
mrsoundhar 0:ae306d3f6076 1597
mrsoundhar 0:ae306d3f6076 1598 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
mrsoundhar 0:ae306d3f6076 1599 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
mrsoundhar 0:ae306d3f6076 1600
mrsoundhar 0:ae306d3f6076 1601 return (
mrsoundhar 0:ae306d3f6076 1602 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
mrsoundhar 0:ae306d3f6076 1603 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
mrsoundhar 0:ae306d3f6076 1604 );
mrsoundhar 0:ae306d3f6076 1605 }
mrsoundhar 0:ae306d3f6076 1606
mrsoundhar 0:ae306d3f6076 1607
mrsoundhar 0:ae306d3f6076 1608 /** \brief Decode Priority
mrsoundhar 0:ae306d3f6076 1609
mrsoundhar 0:ae306d3f6076 1610 The function decodes an interrupt priority value with a given priority group to
mrsoundhar 0:ae306d3f6076 1611 preemptive priority value and subpriority value.
mrsoundhar 0:ae306d3f6076 1612 In case of a conflict between priority grouping and available
mrsoundhar 0:ae306d3f6076 1613 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
mrsoundhar 0:ae306d3f6076 1614
mrsoundhar 0:ae306d3f6076 1615 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mrsoundhar 0:ae306d3f6076 1616 \param [in] PriorityGroup Used priority group.
mrsoundhar 0:ae306d3f6076 1617 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
mrsoundhar 0:ae306d3f6076 1618 \param [out] pSubPriority Subpriority value (starting from 0).
mrsoundhar 0:ae306d3f6076 1619 */
mrsoundhar 0:ae306d3f6076 1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
mrsoundhar 0:ae306d3f6076 1621 {
mrsoundhar 0:ae306d3f6076 1622 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
mrsoundhar 0:ae306d3f6076 1623 uint32_t PreemptPriorityBits;
mrsoundhar 0:ae306d3f6076 1624 uint32_t SubPriorityBits;
mrsoundhar 0:ae306d3f6076 1625
mrsoundhar 0:ae306d3f6076 1626 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
mrsoundhar 0:ae306d3f6076 1627 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
mrsoundhar 0:ae306d3f6076 1628
mrsoundhar 0:ae306d3f6076 1629 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
mrsoundhar 0:ae306d3f6076 1630 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
mrsoundhar 0:ae306d3f6076 1631 }
mrsoundhar 0:ae306d3f6076 1632
mrsoundhar 0:ae306d3f6076 1633
mrsoundhar 0:ae306d3f6076 1634 /** \brief System Reset
mrsoundhar 0:ae306d3f6076 1635
mrsoundhar 0:ae306d3f6076 1636 The function initiates a system reset request to reset the MCU.
mrsoundhar 0:ae306d3f6076 1637 */
mrsoundhar 0:ae306d3f6076 1638 __STATIC_INLINE void NVIC_SystemReset(void)
mrsoundhar 0:ae306d3f6076 1639 {
mrsoundhar 0:ae306d3f6076 1640 __DSB(); /* Ensure all outstanding memory accesses included
mrsoundhar 0:ae306d3f6076 1641 buffered write are completed before reset */
mrsoundhar 0:ae306d3f6076 1642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mrsoundhar 0:ae306d3f6076 1643 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
mrsoundhar 0:ae306d3f6076 1644 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
mrsoundhar 0:ae306d3f6076 1645 __DSB(); /* Ensure completion of memory access */
mrsoundhar 0:ae306d3f6076 1646 while(1); /* wait until reset */
mrsoundhar 0:ae306d3f6076 1647 }
mrsoundhar 0:ae306d3f6076 1648
mrsoundhar 0:ae306d3f6076 1649 /*@} end of CMSIS_Core_NVICFunctions */
mrsoundhar 0:ae306d3f6076 1650
mrsoundhar 0:ae306d3f6076 1651
mrsoundhar 0:ae306d3f6076 1652
mrsoundhar 0:ae306d3f6076 1653 /* ################################## SysTick function ############################################ */
mrsoundhar 0:ae306d3f6076 1654 /** \ingroup CMSIS_Core_FunctionInterface
mrsoundhar 0:ae306d3f6076 1655 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mrsoundhar 0:ae306d3f6076 1656 \brief Functions that configure the System.
mrsoundhar 0:ae306d3f6076 1657 @{
mrsoundhar 0:ae306d3f6076 1658 */
mrsoundhar 0:ae306d3f6076 1659
mrsoundhar 0:ae306d3f6076 1660 #if (__Vendor_SysTickConfig == 0)
mrsoundhar 0:ae306d3f6076 1661
mrsoundhar 0:ae306d3f6076 1662 /** \brief System Tick Configuration
mrsoundhar 0:ae306d3f6076 1663
mrsoundhar 0:ae306d3f6076 1664 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mrsoundhar 0:ae306d3f6076 1665 Counter is in free running mode to generate periodic interrupts.
mrsoundhar 0:ae306d3f6076 1666
mrsoundhar 0:ae306d3f6076 1667 \param [in] ticks Number of ticks between two interrupts.
mrsoundhar 0:ae306d3f6076 1668
mrsoundhar 0:ae306d3f6076 1669 \return 0 Function succeeded.
mrsoundhar 0:ae306d3f6076 1670 \return 1 Function failed.
mrsoundhar 0:ae306d3f6076 1671
mrsoundhar 0:ae306d3f6076 1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mrsoundhar 0:ae306d3f6076 1673 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mrsoundhar 0:ae306d3f6076 1674 must contain a vendor-specific implementation of this function.
mrsoundhar 0:ae306d3f6076 1675
mrsoundhar 0:ae306d3f6076 1676 */
mrsoundhar 0:ae306d3f6076 1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mrsoundhar 0:ae306d3f6076 1678 {
mrsoundhar 0:ae306d3f6076 1679 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mrsoundhar 0:ae306d3f6076 1680
mrsoundhar 0:ae306d3f6076 1681 SysTick->LOAD = ticks - 1; /* set reload register */
mrsoundhar 0:ae306d3f6076 1682 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mrsoundhar 0:ae306d3f6076 1683 SysTick->VAL = 0; /* Load the SysTick Counter Value */
mrsoundhar 0:ae306d3f6076 1684 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mrsoundhar 0:ae306d3f6076 1685 SysTick_CTRL_TICKINT_Msk |
mrsoundhar 0:ae306d3f6076 1686 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mrsoundhar 0:ae306d3f6076 1687 return (0); /* Function successful */
mrsoundhar 0:ae306d3f6076 1688 }
mrsoundhar 0:ae306d3f6076 1689
mrsoundhar 0:ae306d3f6076 1690 #endif
mrsoundhar 0:ae306d3f6076 1691
mrsoundhar 0:ae306d3f6076 1692 /*@} end of CMSIS_Core_SysTickFunctions */
mrsoundhar 0:ae306d3f6076 1693
mrsoundhar 0:ae306d3f6076 1694
mrsoundhar 0:ae306d3f6076 1695
mrsoundhar 0:ae306d3f6076 1696 /* ##################################### Debug In/Output function ########################################### */
mrsoundhar 0:ae306d3f6076 1697 /** \ingroup CMSIS_Core_FunctionInterface
mrsoundhar 0:ae306d3f6076 1698 \defgroup CMSIS_core_DebugFunctions ITM Functions
mrsoundhar 0:ae306d3f6076 1699 \brief Functions that access the ITM debug interface.
mrsoundhar 0:ae306d3f6076 1700 @{
mrsoundhar 0:ae306d3f6076 1701 */
mrsoundhar 0:ae306d3f6076 1702
mrsoundhar 0:ae306d3f6076 1703 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
mrsoundhar 0:ae306d3f6076 1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
mrsoundhar 0:ae306d3f6076 1705
mrsoundhar 0:ae306d3f6076 1706
mrsoundhar 0:ae306d3f6076 1707 /** \brief ITM Send Character
mrsoundhar 0:ae306d3f6076 1708
mrsoundhar 0:ae306d3f6076 1709 The function transmits a character via the ITM channel 0, and
mrsoundhar 0:ae306d3f6076 1710 \li Just returns when no debugger is connected that has booked the output.
mrsoundhar 0:ae306d3f6076 1711 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mrsoundhar 0:ae306d3f6076 1712
mrsoundhar 0:ae306d3f6076 1713 \param [in] ch Character to transmit.
mrsoundhar 0:ae306d3f6076 1714
mrsoundhar 0:ae306d3f6076 1715 \returns Character to transmit.
mrsoundhar 0:ae306d3f6076 1716 */
mrsoundhar 0:ae306d3f6076 1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mrsoundhar 0:ae306d3f6076 1718 {
mrsoundhar 0:ae306d3f6076 1719 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
mrsoundhar 0:ae306d3f6076 1720 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
mrsoundhar 0:ae306d3f6076 1721 {
mrsoundhar 0:ae306d3f6076 1722 while (ITM->PORT[0].u32 == 0);
mrsoundhar 0:ae306d3f6076 1723 ITM->PORT[0].u8 = (uint8_t) ch;
mrsoundhar 0:ae306d3f6076 1724 }
mrsoundhar 0:ae306d3f6076 1725 return (ch);
mrsoundhar 0:ae306d3f6076 1726 }
mrsoundhar 0:ae306d3f6076 1727
mrsoundhar 0:ae306d3f6076 1728
mrsoundhar 0:ae306d3f6076 1729 /** \brief ITM Receive Character
mrsoundhar 0:ae306d3f6076 1730
mrsoundhar 0:ae306d3f6076 1731 The function inputs a character via the external variable \ref ITM_RxBuffer.
mrsoundhar 0:ae306d3f6076 1732
mrsoundhar 0:ae306d3f6076 1733 \return Received character.
mrsoundhar 0:ae306d3f6076 1734 \return -1 No character pending.
mrsoundhar 0:ae306d3f6076 1735 */
mrsoundhar 0:ae306d3f6076 1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
mrsoundhar 0:ae306d3f6076 1737 int32_t ch = -1; /* no character available */
mrsoundhar 0:ae306d3f6076 1738
mrsoundhar 0:ae306d3f6076 1739 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
mrsoundhar 0:ae306d3f6076 1740 ch = ITM_RxBuffer;
mrsoundhar 0:ae306d3f6076 1741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mrsoundhar 0:ae306d3f6076 1742 }
mrsoundhar 0:ae306d3f6076 1743
mrsoundhar 0:ae306d3f6076 1744 return (ch);
mrsoundhar 0:ae306d3f6076 1745 }
mrsoundhar 0:ae306d3f6076 1746
mrsoundhar 0:ae306d3f6076 1747
mrsoundhar 0:ae306d3f6076 1748 /** \brief ITM Check Character
mrsoundhar 0:ae306d3f6076 1749
mrsoundhar 0:ae306d3f6076 1750 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mrsoundhar 0:ae306d3f6076 1751
mrsoundhar 0:ae306d3f6076 1752 \return 0 No character available.
mrsoundhar 0:ae306d3f6076 1753 \return 1 Character available.
mrsoundhar 0:ae306d3f6076 1754 */
mrsoundhar 0:ae306d3f6076 1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
mrsoundhar 0:ae306d3f6076 1756
mrsoundhar 0:ae306d3f6076 1757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
mrsoundhar 0:ae306d3f6076 1758 return (0); /* no character available */
mrsoundhar 0:ae306d3f6076 1759 } else {
mrsoundhar 0:ae306d3f6076 1760 return (1); /* character available */
mrsoundhar 0:ae306d3f6076 1761 }
mrsoundhar 0:ae306d3f6076 1762 }
mrsoundhar 0:ae306d3f6076 1763
mrsoundhar 0:ae306d3f6076 1764 /*@} end of CMSIS_core_DebugFunctions */
mrsoundhar 0:ae306d3f6076 1765
mrsoundhar 0:ae306d3f6076 1766 #endif /* __CORE_CM4_H_DEPENDANT */
mrsoundhar 0:ae306d3f6076 1767
mrsoundhar 0:ae306d3f6076 1768 #endif /* __CMSIS_GENERIC */
mrsoundhar 0:ae306d3f6076 1769
mrsoundhar 0:ae306d3f6076 1770 #ifdef __cplusplus
mrsoundhar 0:ae306d3f6076 1771 }
mrsoundhar 0:ae306d3f6076 1772 #endif