Marcell Rausch / mbed-dev-no-serial

mbed library sources. Supersedes mbed-src. removed serial

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

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<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Real-Time Clock data types, definitions and function prototypes.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5 /* ****************************************************************************
<> 157:ff67d9f36b67 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 7 *
<> 157:ff67d9f36b67 8 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 9 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 10 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 12 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 13 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 14 *
<> 157:ff67d9f36b67 15 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 16 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 17 *
<> 157:ff67d9f36b67 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 24 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 29 *
<> 157:ff67d9f36b67 30 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 31 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 32 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 34 * ownership rights.
<> 157:ff67d9f36b67 35 *
<> 157:ff67d9f36b67 36 * $Date: 2016-10-10 19:28:26 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 37 * $Revision: 24670 $
<> 157:ff67d9f36b67 38 *
<> 157:ff67d9f36b67 39 **************************************************************************** */
<> 157:ff67d9f36b67 40
<> 157:ff67d9f36b67 41 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 42 #ifndef _RTC_H_
<> 157:ff67d9f36b67 43 #define _RTC_H_
<> 157:ff67d9f36b67 44
<> 157:ff67d9f36b67 45 /* **** Includes **** */
<> 157:ff67d9f36b67 46 #include "mxc_config.h"
<> 157:ff67d9f36b67 47 #include "rtc_regs.h"
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 #ifdef __cplusplus
<> 157:ff67d9f36b67 50 extern "C" {
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 /**
<> 157:ff67d9f36b67 54 * @ingroup periphlibs
<> 157:ff67d9f36b67 55 * @defgroup rtc Real-Time Clock (RTC)
<> 157:ff67d9f36b67 56 * @brief Functions, types, and registers for the Real-Time Clock Peripheral.
<> 157:ff67d9f36b67 57 * @{
<> 157:ff67d9f36b67 58 */
<> 157:ff67d9f36b67 59
<> 157:ff67d9f36b67 60 /* **** Definitions **** */
<> 157:ff67d9f36b67 61 /**
<> 157:ff67d9f36b67 62 * Enumeration type for scaling down the 4096Hz input clock to the RTC.
<> 157:ff67d9f36b67 63 */
<> 157:ff67d9f36b67 64 typedef enum {
<> 157:ff67d9f36b67 65 RTC_PRESCALE_DIV_2_0 = MXC_V_RTC_PRESCALE_DIV_2_0, /**< \f$ f_{RTC} = \frac {4096} {2^{0}} = 4096Hz \f$ */
<> 157:ff67d9f36b67 66 RTC_PRESCALE_DIV_2_1 = MXC_V_RTC_PRESCALE_DIV_2_1, /**< \f$ f_{RTC} = \frac {4096} {2^{1}} = 2048Hz \f$ */
<> 157:ff67d9f36b67 67 RTC_PRESCALE_DIV_2_2 = MXC_V_RTC_PRESCALE_DIV_2_2, /**< \f$ f_{RTC} = \frac {4096} {2^{2}} = 1024Hz \f$ */
<> 157:ff67d9f36b67 68 RTC_PRESCALE_DIV_2_3 = MXC_V_RTC_PRESCALE_DIV_2_3, /**< \f$ f_{RTC} = \frac {4096} {2^{3}} = 512Hz \f$ */
<> 157:ff67d9f36b67 69 RTC_PRESCALE_DIV_2_4 = MXC_V_RTC_PRESCALE_DIV_2_4, /**< \f$ f_{RTC} = \frac {4096} {2^{4}} = 256Hz \f$ */
<> 157:ff67d9f36b67 70 RTC_PRESCALE_DIV_2_5 = MXC_V_RTC_PRESCALE_DIV_2_5, /**< \f$ f_{RTC} = \frac {4096} {2^{5}} = 128Hz \f$ */
<> 157:ff67d9f36b67 71 RTC_PRESCALE_DIV_2_6 = MXC_V_RTC_PRESCALE_DIV_2_6, /**< \f$ f_{RTC} = \frac {4096} {2^{6}} = 64Hz \f$ */
<> 157:ff67d9f36b67 72 RTC_PRESCALE_DIV_2_7 = MXC_V_RTC_PRESCALE_DIV_2_7, /**< \f$ f_{RTC} = \frac {4096} {2^{7}} = 32Hz \f$ */
<> 157:ff67d9f36b67 73 RTC_PRESCALE_DIV_2_8 = MXC_V_RTC_PRESCALE_DIV_2_8, /**< \f$ f_{RTC} = \frac {4096} {2^{8}} = 16Hz \f$ */
<> 157:ff67d9f36b67 74 RTC_PRESCALE_DIV_2_9 = MXC_V_RTC_PRESCALE_DIV_2_9, /**< \f$ f_{RTC} = \frac {4096} {2^{9}} = 8Hz \f$ */
<> 157:ff67d9f36b67 75 RTC_PRESCALE_DIV_2_10 = MXC_V_RTC_PRESCALE_DIV_2_10, /**< \f$ f_{RTC} = \frac {4096} {2^{10}} = 4Hz \f$ */
<> 157:ff67d9f36b67 76 RTC_PRESCALE_DIV_2_11 = MXC_V_RTC_PRESCALE_DIV_2_11, /**< \f$ f_{RTC} = \frac {4096} {2^{11}} = 2Hz \f$ */
<> 157:ff67d9f36b67 77 RTC_PRESCALE_DIV_2_12 = MXC_V_RTC_PRESCALE_DIV_2_12, /**< \f$ f_{RTC} = \frac {4096} {2^{12}} = 1Hz \f$ */
<> 157:ff67d9f36b67 78 } rtc_prescale_t;
<> 157:ff67d9f36b67 79
<> 157:ff67d9f36b67 80 /**
<> 157:ff67d9f36b67 81 * Mask of the RTC Flags for the Active Transaction.
<> 157:ff67d9f36b67 82 */
<> 157:ff67d9f36b67 83 #define RTC_CTRL_ACTIVE_TRANS (MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE | \
<> 157:ff67d9f36b67 84 MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE | \
<> 157:ff67d9f36b67 85 MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE | \
<> 157:ff67d9f36b67 86 MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE | \
<> 157:ff67d9f36b67 87 MXC_F_RTC_CTRL_RTC_SET_ACTIVE | \
<> 157:ff67d9f36b67 88 MXC_F_RTC_CTRL_RTC_CLR_ACTIVE | \
<> 157:ff67d9f36b67 89 MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE | \
<> 157:ff67d9f36b67 90 MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE | \
<> 157:ff67d9f36b67 91 MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE | \
<> 157:ff67d9f36b67 92 MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE | \
<> 157:ff67d9f36b67 93 MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE | \
<> 157:ff67d9f36b67 94 MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE | \
<> 157:ff67d9f36b67 95 MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE | \
<> 157:ff67d9f36b67 96 MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE | \
<> 157:ff67d9f36b67 97 MXC_F_RTC_CTRL_ACTIVE_TRANS_0)
<> 157:ff67d9f36b67 98
<> 157:ff67d9f36b67 99 /**
<> 157:ff67d9f36b67 100 * Mask used to clear all RTC interrupt flags, see \ref RTC_FLAGS_Register Register.
<> 157:ff67d9f36b67 101 */
<> 157:ff67d9f36b67 102 #define RTC_FLAGS_CLEAR_ALL (MXC_F_RTC_FLAGS_COMP0 | \
<> 157:ff67d9f36b67 103 MXC_F_RTC_FLAGS_COMP1| \
<> 157:ff67d9f36b67 104 MXC_F_RTC_FLAGS_PRESCALE_COMP | \
<> 157:ff67d9f36b67 105 MXC_F_RTC_FLAGS_OVERFLOW | \
<> 157:ff67d9f36b67 106 MXC_F_RTC_FLAGS_TRIM)
<> 157:ff67d9f36b67 107 /**
<> 157:ff67d9f36b67 108 * Enumeration type to select the type of RTC Snooze Mode for an alarm condition.
<> 157:ff67d9f36b67 109 */
<> 157:ff67d9f36b67 110 typedef enum {
<> 157:ff67d9f36b67 111 RTC_SNOOZE_DISABLE = MXC_V_RTC_CTRL_SNOOZE_DISABLE, /**< Snooze Mode Disabled */
<> 157:ff67d9f36b67 112 RTC_SNOOZE_MODE_A = MXC_V_RTC_CTRL_SNOOZE_MODE_A, /**< \f$ COMP1 = COMP1 + RTC\_SNZ\_VALUE \f$ when snooze flag is set */
<> 157:ff67d9f36b67 113 RTC_SNOOZE_MODE_B = MXC_V_RTC_CTRL_SNOOZE_MODE_B, /**< \f$ COMP1 = RTC\_TIMER + RTC\_SNZ\_VALUE \f$ when snooze flag is set */
<> 157:ff67d9f36b67 114 } rtc_snooze_t;
<> 157:ff67d9f36b67 115
<> 157:ff67d9f36b67 116 /**
<> 157:ff67d9f36b67 117 * Number of RTC Compare registers for this peripheral instance.
<> 157:ff67d9f36b67 118 */
<> 157:ff67d9f36b67 119 #define RTC_NUM_COMPARE 2
<> 157:ff67d9f36b67 120
<> 157:ff67d9f36b67 121 /**
<> 157:ff67d9f36b67 122 * Structure type that represents the current configuration of the RTC.
<> 157:ff67d9f36b67 123 */
<> 157:ff67d9f36b67 124
<> 157:ff67d9f36b67 125 typedef struct {
<> 157:ff67d9f36b67 126 rtc_prescale_t prescaler; /**< prescale value for the input 4096Hz clock. */
<> 157:ff67d9f36b67 127 rtc_prescale_t prescalerMask; /**< Mask value used to compare to the rtc prescale value, when the \f$ (Count_{prescaler}\,\&\,Prescale\,Mask) == 0 \f$, the prescale compare flag will be set. */
<> 157:ff67d9f36b67 128 uint32_t compareCount[RTC_NUM_COMPARE]; /**< Values used for setting the RTC alarms. See RTC_SetCompare() and RTC_GetCompare(). */
<> 157:ff67d9f36b67 129 uint32_t snoozeCount; /**< The number of RTC ticks to snooze if enabled. */
<> 157:ff67d9f36b67 130 rtc_snooze_t snoozeMode; /**< The desired snooze mode, see #rtc_snooze_t. */
<> 157:ff67d9f36b67 131 } rtc_cfg_t;
<> 157:ff67d9f36b67 132
<> 157:ff67d9f36b67 133 /**
<> 157:ff67d9f36b67 134 * @brief Initializes the RTC
<> 157:ff67d9f36b67 135 * @note Must setup clocking and power prior to this function.
<> 157:ff67d9f36b67 136 *
<> 157:ff67d9f36b67 137 * @param cfg RTC configuration object.
<> 157:ff67d9f36b67 138 *
<> 157:ff67d9f36b67 139 * @retval #E_NO_ERROR RTC initialized successfully.
<> 157:ff67d9f36b67 140 * @retval #E_NULL_PTR \p cfg pointer is NULL.
<> 157:ff67d9f36b67 141 * @retval #E_INVALID if comparison index, prescaler mask or snooze mask
<> 157:ff67d9f36b67 142 * are out of bounds, see #rtc_cfg_t.
<> 157:ff67d9f36b67 143 */
<> 157:ff67d9f36b67 144 int RTC_Init(const rtc_cfg_t *cfg);
<> 157:ff67d9f36b67 145
<> 157:ff67d9f36b67 146 /**
<> 157:ff67d9f36b67 147 * @brief Enable and start the real-time clock continuing from its current value.
<> 157:ff67d9f36b67 148 */
<> 157:ff67d9f36b67 149 __STATIC_INLINE void RTC_Start(void)
<> 157:ff67d9f36b67 150 {
<> 157:ff67d9f36b67 151 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
<> 157:ff67d9f36b67 152
<> 157:ff67d9f36b67 153 //wait for pending actions to complete
<> 157:ff67d9f36b67 154 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 155 }
<> 157:ff67d9f36b67 156
<> 157:ff67d9f36b67 157 /**
<> 157:ff67d9f36b67 158 * @brief Disable and stop the real-time clock counting.
<> 157:ff67d9f36b67 159 */
<> 157:ff67d9f36b67 160 __STATIC_INLINE void RTC_Stop(void)
<> 157:ff67d9f36b67 161 {
<> 157:ff67d9f36b67 162 MXC_RTCTMR->ctrl &= ~(MXC_F_RTC_CTRL_ENABLE);
<> 157:ff67d9f36b67 163
<> 157:ff67d9f36b67 164 //wait for pending actions to complete
<> 157:ff67d9f36b67 165 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 166 }
<> 157:ff67d9f36b67 167
<> 157:ff67d9f36b67 168 /**
<> 157:ff67d9f36b67 169 * @brief Returns the state (running or disabled) for the RTC.
<> 157:ff67d9f36b67 170 *
<> 157:ff67d9f36b67 171 * @retval 0 Disabled.
<> 157:ff67d9f36b67 172 * @retval Non-zero Active.
<> 157:ff67d9f36b67 173 */
<> 157:ff67d9f36b67 174 __STATIC_INLINE uint32_t RTC_IsActive(void)
<> 157:ff67d9f36b67 175 {
<> 157:ff67d9f36b67 176 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
<> 157:ff67d9f36b67 177 }
<> 157:ff67d9f36b67 178
<> 157:ff67d9f36b67 179 /**
<> 157:ff67d9f36b67 180 * @brief Set the current count of the RTC
<> 157:ff67d9f36b67 181 *
<> 157:ff67d9f36b67 182 * @param count The desired count value to set for the RTC count.
<> 157:ff67d9f36b67 183 */
<> 157:ff67d9f36b67 184 __STATIC_INLINE void RTC_SetCount(uint32_t count)
<> 157:ff67d9f36b67 185 {
<> 157:ff67d9f36b67 186 MXC_RTCTMR->timer = count;
<> 157:ff67d9f36b67 187
<> 157:ff67d9f36b67 188 //wait for pending actions to complete
<> 157:ff67d9f36b67 189 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 190 }
<> 157:ff67d9f36b67 191
<> 157:ff67d9f36b67 192 /**
<> 157:ff67d9f36b67 193 * @brief Get the current count value of the RTC.
<> 157:ff67d9f36b67 194 *
<> 157:ff67d9f36b67 195 * @retval The value of the RTC counter.
<> 157:ff67d9f36b67 196 */
<> 157:ff67d9f36b67 197 __STATIC_INLINE uint32_t RTC_GetCount(void)
<> 157:ff67d9f36b67 198 {
<> 157:ff67d9f36b67 199 return (MXC_RTCTMR->timer);
<> 157:ff67d9f36b67 200 }
<> 157:ff67d9f36b67 201
<> 157:ff67d9f36b67 202 /**
<> 157:ff67d9f36b67 203 * @brief Sets the compare value for the RTC.
<> 157:ff67d9f36b67 204 *
<> 157:ff67d9f36b67 205 * @param compareIndex Index of comparator to set, see #RTC_NUM_COMPARE
<> 157:ff67d9f36b67 206 * for the total number of compare registers
<> 157:ff67d9f36b67 207 * available.
<> 157:ff67d9f36b67 208 * @param counts The value to set for the compare.
<> 157:ff67d9f36b67 209 * @retval #E_NO_ERROR Compare count register set successfully for
<> 157:ff67d9f36b67 210 * requested comparator.
<> 157:ff67d9f36b67 211 * @retval #E_INVALID compareIndex is @>= RTC_NUM_COMPARE.
<> 157:ff67d9f36b67 212 */
<> 157:ff67d9f36b67 213 int RTC_SetCompare(uint8_t compareIndex, uint32_t counts);
<> 157:ff67d9f36b67 214
<> 157:ff67d9f36b67 215 /**
<> 157:ff67d9f36b67 216 * @brief Gets the compare value for the RTC.
<> 157:ff67d9f36b67 217 *
<> 157:ff67d9f36b67 218 * @param compareIndex Index of the compare value to return. See #RTC_NUM_COMPARE
<> 157:ff67d9f36b67 219 * for the total number of compare registers available.
<> 157:ff67d9f36b67 220 *
<> 157:ff67d9f36b67 221 * @returns The current value of the specified compare register for the RTC.
<> 157:ff67d9f36b67 222 */
<> 157:ff67d9f36b67 223 uint32_t RTC_GetCompare(uint8_t compareIndex);
<> 157:ff67d9f36b67 224
<> 157:ff67d9f36b67 225 /**
<> 157:ff67d9f36b67 226 * @brief Set the prescale reload value for the real-time clock.
<> 157:ff67d9f36b67 227 * @details The prescale reload value determines the number of 4kHz ticks
<> 157:ff67d9f36b67 228 * that will occur before the timer is incremented.
<> 157:ff67d9f36b67 229 * <table>
<> 157:ff67d9f36b67 230 * <caption id="prescaler_val">Prescaler Settings and Corresponding RTC Resolutions</caption>
<> 157:ff67d9f36b67 231 * <tr><th>PRESCALE <th>Prescale Reload <th>4kHz ticks in LSB <th>Min Timer Value (sec) <th> Max Timer Value (sec) <th>Max Timer Value (Days) <th> Max Timer Value (Years)
<> 157:ff67d9f36b67 232 * <tr><td align="right">0h<td align="center">RTC_PRESCALE_DIV_2_0<td align="right">1<td align="right">0.00024<td align="right">1048576<td align="right">12<td align="right">0.0
<> 157:ff67d9f36b67 233 * <tr><td align="right">1h<td align="center">RTC_PRESCALE_DIV_2_1<td align="right">2<td align="right">0.00049<td align="right">2097152<td align="right">24<td align="right">0.1
<> 157:ff67d9f36b67 234 * <tr><td align="right">2h<td align="center">RTC_PRESCALE_DIV_2_2<td align="right">4<td align="right">0.00098<td align="right">4194304<td align="right">49<td align="right">0.1
<> 157:ff67d9f36b67 235 * <tr><td align="right">3h<td align="center">RTC_PRESCALE_DIV_2_3<td align="right">8<td align="right">0.00195<td align="right">8388608<td align="right">97<td align="right">0.3
<> 157:ff67d9f36b67 236 * <tr><td align="right">4h<td align="center">RTC_PRESCALE_DIV_2_4<td align="right">16<td align="right">0.00391<td align="right">16777216<td align="right">194 <td align="right">0.5
<> 157:ff67d9f36b67 237 * <tr><td align="right">5h<td align="center">RTC_PRESCALE_DIV_2_5<td align="right">32<td align="right">0.00781<td align="right">33554432<td align="right">388 <td align="right">1.1
<> 157:ff67d9f36b67 238 * <tr><td align="right">6h<td align="center">RTC_PRESCALE_DIV_2_6<td align="right">64<td align="right">0.01563<td align="right">67108864<td align="right">777 <td align="right">2.2
<> 157:ff67d9f36b67 239 * <tr><td align="right">7h<td align="center">RTC_PRESCALE_DIV_2_7<td align="right">128<td align="right">0.03125<td align="right">134217728<td align="right">1553 <td align="right">4.4
<> 157:ff67d9f36b67 240 * <tr><td align="right">8h<td align="center">RTC_PRESCALE_DIV_2_8<td align="right">256<td align="right">0.06250<td align="right">268435456<td align="right">3107 <td align="right">8.7
<> 157:ff67d9f36b67 241 * <tr><td align="right">9h<td align="center">RTC_PRESCALE_DIV_2_9<td align="right">512<td align="right">0.12500<td align="right">536870912<td align="right">6214 <td align="right">17.5
<> 157:ff67d9f36b67 242 * <tr><td align="right">Ah<td align="center">RTC_PRESCALE_DIV_2_10<td align="right">1024 <td align="right">0.25000<td align="right">1073741824<td align="right">12428<td align="right">34.9
<> 157:ff67d9f36b67 243 * <tr><td align="right">Bh<td align="center">RTC_PRESCALE_DIV_2_11<td align="right">2048 <td align="right">0.50000<td align="right">2147483648<td align="right">24855<td align="right">69.8
<> 157:ff67d9f36b67 244 * <tr><td align="right">Ch<td align="center">RTC_PRESCALE_DIV_2_12<td align="right">4096 <td align="right">1.00000<td align="right">4294967296<td align="right">49710<td align="right">139.6
<> 157:ff67d9f36b67 245 * </table>
<> 157:ff67d9f36b67 246 *
<> 157:ff67d9f36b67 247 * @param prescaler Prescale value to set, see #rtc_prescale_t.
<> 157:ff67d9f36b67 248 */
<> 157:ff67d9f36b67 249 __STATIC_INLINE void RTC_SetPrescaler(rtc_prescale_t prescaler)
<> 157:ff67d9f36b67 250 {
<> 157:ff67d9f36b67 251 MXC_RTCTMR->prescale = prescaler;
<> 157:ff67d9f36b67 252
<> 157:ff67d9f36b67 253 //wait for pending actions to complete
<> 157:ff67d9f36b67 254 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 255 }
<> 157:ff67d9f36b67 256
<> 157:ff67d9f36b67 257 /**
<> 157:ff67d9f36b67 258 * @brief Get the current value of the real-time clock prescaler.
<> 157:ff67d9f36b67 259 *
<> 157:ff67d9f36b67 260 * @retval rtc_prescale_t Returns the current RTC prescaler setting,
<> 157:ff67d9f36b67 261 * See #rtc_prescale_t for values of the prescaler.
<> 157:ff67d9f36b67 262 */
<> 157:ff67d9f36b67 263 __STATIC_INLINE rtc_prescale_t RTC_GetPrescaler(void)
<> 157:ff67d9f36b67 264 {
<> 157:ff67d9f36b67 265 return (rtc_prescale_t)(MXC_RTCTMR->prescale);
<> 157:ff67d9f36b67 266 }
<> 157:ff67d9f36b67 267
<> 157:ff67d9f36b67 268 /**
<> 157:ff67d9f36b67 269 * @brief Set the prescaler mask, which is used to set the RTC prescale counter
<> 157:ff67d9f36b67 270 * compare flag when the prescaler timer matches the bits indicated
<> 157:ff67d9f36b67 271 * by the mask.
<> 157:ff67d9f36b67 272 * @param mask A bit mask that is used to set the prescale compare flag if the
<> 157:ff67d9f36b67 273 * prescale timer has the corresponding bits set. @note This mask must
<> 157:ff67d9f36b67 274 * be less than or equal to the prescaler reload value.
<> 157:ff67d9f36b67 275 * See RTC_SetPrescaler()
<> 157:ff67d9f36b67 276 * @details When \f$ Count_{prescaler}\,\&\,Prescale\,Mask = 0 \f$, the prescale compare flag is set
<> 157:ff67d9f36b67 277 * @retval int Returns #E_NO_ERROR if prescale value is valid and is set.
<> 157:ff67d9f36b67 278 * @retval int Returns #E_INVALID if mask is \> than prescaler value
<> 157:ff67d9f36b67 279 */
<> 157:ff67d9f36b67 280 __STATIC_INLINE int RTC_SetPrescalerMask(rtc_prescale_t mask)
<> 157:ff67d9f36b67 281 {
<> 157:ff67d9f36b67 282 if (mask > ((rtc_prescale_t)(MXC_RTCTMR->prescale)))
<> 157:ff67d9f36b67 283 {
<> 157:ff67d9f36b67 284 return E_INVALID;
<> 157:ff67d9f36b67 285 }
<> 157:ff67d9f36b67 286 MXC_RTCTMR->prescale_mask = mask;
<> 157:ff67d9f36b67 287
<> 157:ff67d9f36b67 288 //wait for pending actions to complete
<> 157:ff67d9f36b67 289 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 290 return E_NO_ERROR;
<> 157:ff67d9f36b67 291 }
<> 157:ff67d9f36b67 292
<> 157:ff67d9f36b67 293 /**
<> 157:ff67d9f36b67 294 * @brief Set the count for snooze mode. See RTC_Snooze().
<> 157:ff67d9f36b67 295 * @details This value is used to set the snooze count. The meaning of this value is dependant on the snooze mode. p
<> 157:ff67d9f36b67 296 * See RTC_SetSnoozeMode() for details of calculating the snooze time period based on the mode and snooze count.
<> 157:ff67d9f36b67 297 * @param count Sets the count used for snooze when snooze mode is
<> 157:ff67d9f36b67 298 * enabled and the snooze flag is set.
<> 157:ff67d9f36b67 299 * @retval #E_NO_ERROR Snooze value is set correctly and value is valid.
<> 157:ff67d9f36b67 300 * @retval #E_INVALID SnoozeCount exceeds maximum supported, see
<> 157:ff67d9f36b67 301 * MXC_F_RTC_SNZ_VAL_VALUE
<> 157:ff67d9f36b67 302 */
<> 157:ff67d9f36b67 303 __STATIC_INLINE int RTC_SetSnoozeCount(uint32_t count)
<> 157:ff67d9f36b67 304 {
<> 157:ff67d9f36b67 305 // Check to make sure max value is not being exceeded
<> 157:ff67d9f36b67 306 if (count > MXC_F_RTC_SNZ_VAL_VALUE)
<> 157:ff67d9f36b67 307 return E_INVALID;
<> 157:ff67d9f36b67 308
<> 157:ff67d9f36b67 309 MXC_RTCTMR->snz_val = count;
<> 157:ff67d9f36b67 310
<> 157:ff67d9f36b67 311 //wait for pending actions to complete
<> 157:ff67d9f36b67 312 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 313 return E_NO_ERROR;
<> 157:ff67d9f36b67 314 }
<> 157:ff67d9f36b67 315
<> 157:ff67d9f36b67 316 /**
<> 157:ff67d9f36b67 317 * @brief Gets the current Snooze Count value.
<> 157:ff67d9f36b67 318 * @details Returns the current value for the Snooze Count. This value is
<> 157:ff67d9f36b67 319 * used as part of the snooze calculation depending on the snooze
<> 157:ff67d9f36b67 320 * mode. See RTC_SetSnoozeMode() for details of calculating the
<> 157:ff67d9f36b67 321 * snooze time period based on the mode and count.
<> 157:ff67d9f36b67 322 * @return Value of the snooze register.
<> 157:ff67d9f36b67 323 */
<> 157:ff67d9f36b67 324 __STATIC_INLINE uint32_t RTC_GetSnoozeCount(void)
<> 157:ff67d9f36b67 325 {
<> 157:ff67d9f36b67 326 return MXC_RTCTMR->snz_val;
<> 157:ff67d9f36b67 327 }
<> 157:ff67d9f36b67 328
<> 157:ff67d9f36b67 329 /**
<> 157:ff67d9f36b67 330 * @brief Activates snooze mode.
<> 157:ff67d9f36b67 331 * @details Begins a snooze of the RTC. When this function is called
<> 157:ff67d9f36b67 332 * the snooze time period is determined based on the snooze mode and the count.
<> 157:ff67d9f36b67 333 * See RTC_GetCount() and RTC_SetSnoozeMode()
<> 157:ff67d9f36b67 334 */
<> 157:ff67d9f36b67 335 __STATIC_INLINE void RTC_Snooze(void)
<> 157:ff67d9f36b67 336 {
<> 157:ff67d9f36b67 337 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_SNOOZE_A | MXC_F_RTC_FLAGS_SNOOZE_B;
<> 157:ff67d9f36b67 338
<> 157:ff67d9f36b67 339 //wait for pending actions to complete
<> 157:ff67d9f36b67 340 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 341 }
<> 157:ff67d9f36b67 342
<> 157:ff67d9f36b67 343 /**
<> 157:ff67d9f36b67 344 * @brief Sets the Snooze Mode.
<> 157:ff67d9f36b67 345 * @details <table> <caption id="snoozeModesTable">Snooze Modes</caption>
<> 157:ff67d9f36b67 346 * <tr><th>Mode<th>Snooze Time Calculation
<> 157:ff67d9f36b67 347 * <tr><td>RTC_SNOOZE_DISABLE<td>Snooze Disabled
<> 157:ff67d9f36b67 348 * <tr><td>RTC_SNOOZE_MODE_A<td>\f$ compare1 = compare1 + snoozeCount \f$
<> 157:ff67d9f36b67 349 * <tr><td>RTC_SNOOZE_MODE_B<td>\f$ compare1 = count + snoozeCount \f$
<> 157:ff67d9f36b67 350 * </table>
<> 157:ff67d9f36b67 351 * @note @a count is the value of the RTC counter when RTC_Snooze()
<> 157:ff67d9f36b67 352 * is called to start a snooze cycle and @a snoozeCount is the value set by the RTC_SetSnoozeCount(uint32_t count) function.
<> 157:ff67d9f36b67 353 *
<> 157:ff67d9f36b67 354 * @param mode Specifies the desired snooze mode, see #rtc_snooze_t.
<> 157:ff67d9f36b67 355 *
<> 157:ff67d9f36b67 356 */
<> 157:ff67d9f36b67 357 __STATIC_INLINE void RTC_SetSnoozeMode(rtc_snooze_t mode)
<> 157:ff67d9f36b67 358 {
<> 157:ff67d9f36b67 359 uint32_t ctrl;
<> 157:ff67d9f36b67 360 // Get the control register and mask off the non-snooze bits
<> 157:ff67d9f36b67 361 ctrl = (MXC_RTCTMR->ctrl & ~(MXC_F_RTC_CTRL_SNOOZE_ENABLE));
<> 157:ff67d9f36b67 362 // set the requested snooze mode bits and save the settings
<> 157:ff67d9f36b67 363 MXC_RTCTMR->ctrl = (ctrl | (mode << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS));
<> 157:ff67d9f36b67 364
<> 157:ff67d9f36b67 365 //wait for pending actions to complete
<> 157:ff67d9f36b67 366 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 367 }
<> 157:ff67d9f36b67 368
<> 157:ff67d9f36b67 369 /**
<> 157:ff67d9f36b67 370 * @brief Enables the interrupts specified for the RTC.
<> 157:ff67d9f36b67 371 * @details <table>
<> 157:ff67d9f36b67 372 * <caption id="RTC_interrupts">RTC Interrupts</caption>
<> 157:ff67d9f36b67 373 * <tr><th>Interrupt<th>Mask
<> 157:ff67d9f36b67 374 * <tr><td>Compare 0<td>#MXC_F_RTC_INTEN_COMP0
<> 157:ff67d9f36b67 375 * <tr><td>Compare 1 and Snooze<td>#MXC_F_RTC_INTEN_COMP1
<> 157:ff67d9f36b67 376 * <tr><td>Prescale Comp<td>#MXC_F_RTC_INTEN_PRESCALE_COMP
<> 157:ff67d9f36b67 377 * <tr><td>RTC Count Overflow<td>#MXC_F_RTC_INTEN_OVERFLOW
<> 157:ff67d9f36b67 378 * <tr><td>Trim<td>#MXC_F_RTC_INTEN_TRIM
<> 157:ff67d9f36b67 379 * </table>
<> 157:ff67d9f36b67 380 * @param mask A mask of the RTC interrupts to enable, 1 = Enable. See
<> 157:ff67d9f36b67 381 * @ref RTC_FLAGS_Register Register for the RTC interrupt enable bit masks and positions.
<> 157:ff67d9f36b67 382 */
<> 157:ff67d9f36b67 383 __STATIC_INLINE void RTC_EnableINT(uint32_t mask)
<> 157:ff67d9f36b67 384 {
<> 157:ff67d9f36b67 385 MXC_RTCTMR->inten |= mask;
<> 157:ff67d9f36b67 386 }
<> 157:ff67d9f36b67 387
<> 157:ff67d9f36b67 388 /**
<> 157:ff67d9f36b67 389 * @brief Disable the interrupts specified for the RTC. See the
<> 157:ff67d9f36b67 390 * @ref RTC_INTEN_Register Register for the RTC interrupt enable bit masks and positions.
<> 157:ff67d9f36b67 391 *
<> 157:ff67d9f36b67 392 * @param mask A mask of the RTC interrupts to disable, 1 = Disable.
<> 157:ff67d9f36b67 393 */
<> 157:ff67d9f36b67 394 __STATIC_INLINE void RTC_DisableINT(uint32_t mask)
<> 157:ff67d9f36b67 395 {
<> 157:ff67d9f36b67 396 MXC_RTCTMR->inten &= ~mask;
<> 157:ff67d9f36b67 397 }
<> 157:ff67d9f36b67 398
<> 157:ff67d9f36b67 399 /**
<> 157:ff67d9f36b67 400 * @brief Returns the current interrupt flags that are set.
<> 157:ff67d9f36b67 401 *
<> 157:ff67d9f36b67 402 * @return A mask of the current interrupt flags, see the
<> 157:ff67d9f36b67 403 * @ref RTC_FLAGS_Register Register for the details of the RTC interrupt
<> 157:ff67d9f36b67 404 * flags.
<> 157:ff67d9f36b67 405 */
<> 157:ff67d9f36b67 406 __STATIC_INLINE uint32_t RTC_GetFlags(void)
<> 157:ff67d9f36b67 407 {
<> 157:ff67d9f36b67 408 return (MXC_RTCTMR->flags);
<> 157:ff67d9f36b67 409 }
<> 157:ff67d9f36b67 410
<> 157:ff67d9f36b67 411 /**
<> 157:ff67d9f36b67 412 * @brief Clears the interrupt flags specified.
<> 157:ff67d9f36b67 413 *
<> 157:ff67d9f36b67 414 * @param mask A mask of interrupts to clear, see the @ref RTC_FLAGS_Register
<> 157:ff67d9f36b67 415 * Register for the interrupt flag bit masks and positions.
<> 157:ff67d9f36b67 416 */
<> 157:ff67d9f36b67 417 __STATIC_INLINE void RTC_ClearFlags(uint32_t mask)
<> 157:ff67d9f36b67 418 {
<> 157:ff67d9f36b67 419 MXC_RTCTMR->flags = mask;
<> 157:ff67d9f36b67 420
<> 157:ff67d9f36b67 421 //wait for pending actions to complete
<> 157:ff67d9f36b67 422 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 157:ff67d9f36b67 423 }
<> 157:ff67d9f36b67 424
<> 157:ff67d9f36b67 425 /**
<> 157:ff67d9f36b67 426 * @brief Gets the active transaction flags, see @ref RTC_CTRL_Register Register for the list of ACTIVE flags.
<> 157:ff67d9f36b67 427 *
<> 157:ff67d9f36b67 428 * @retval 0 No active transactions.
<> 157:ff67d9f36b67 429 * @retval nonzero A mask of active transaction bits.
<> 157:ff67d9f36b67 430 */
<> 157:ff67d9f36b67 431 __STATIC_INLINE uint32_t RTC_GetActiveTrans(void)
<> 157:ff67d9f36b67 432 {
<> 157:ff67d9f36b67 433 return (MXC_RTCTMR->ctrl & RTC_CTRL_ACTIVE_TRANS);
<> 157:ff67d9f36b67 434 }
<> 157:ff67d9f36b67 435
<> 157:ff67d9f36b67 436 /**
<> 157:ff67d9f36b67 437 * @brief Sets the trim value and trim slow/fast option.
<> 157:ff67d9f36b67 438 * @warning The RTC must be disabled prior to calling this function, see RTC_Stop(void) to disable the RTC.
<> 157:ff67d9f36b67 439 *
<> 157:ff67d9f36b67 440 * @param trim The desired trim value. @note The maximum trim value setting is 0x03FFFF.
<> 157:ff67d9f36b67 441 * @param trimSlow 1 = trim slow, 0 = trim fast
<> 157:ff67d9f36b67 442 *
<> 157:ff67d9f36b67 443 * @return #E_NO_ERROR Trim value is valid and set.
<> 157:ff67d9f36b67 444 * @return #E_INVALID Trim value exceeds max trim.
<> 157:ff67d9f36b67 445 * @return #E_BAD_STATE RTC is active.
<> 157:ff67d9f36b67 446 */
<> 157:ff67d9f36b67 447 int RTC_SetTrim(uint32_t trim, uint8_t trimSlow);
<> 157:ff67d9f36b67 448
<> 157:ff67d9f36b67 449 /**
<> 157:ff67d9f36b67 450 * @brief Gets the current trim value.
<> 157:ff67d9f36b67 451 * @note Ensure RTC is disabled prior to calling this function, see RTC_Stop(void).
<> 157:ff67d9f36b67 452 *
<> 157:ff67d9f36b67 453 * @retval uint32_t Current trim value of RTC.
<> 157:ff67d9f36b67 454 */
<> 157:ff67d9f36b67 455 uint32_t RTC_GetTrim(void);
<> 157:ff67d9f36b67 456
<> 157:ff67d9f36b67 457 /**
<> 157:ff67d9f36b67 458 * @brief Enable the trim.
<> 157:ff67d9f36b67 459 * @warning The RTC must be disabled prior to calling this function, see RTC_Stop(void) to disable the RTC.
<> 157:ff67d9f36b67 460 * @retval #E_NO_ERROR Trim is enabled.
<> 157:ff67d9f36b67 461 * @retval #E_INVALID RTC is active, see RTC_Stop(void).
<> 157:ff67d9f36b67 462 */
<> 157:ff67d9f36b67 463 int RTC_TrimEnable(void);
<> 157:ff67d9f36b67 464
<> 157:ff67d9f36b67 465 /**
<> 157:ff67d9f36b67 466 * @brief Disable the trim.
<> 157:ff67d9f36b67 467 */
<> 157:ff67d9f36b67 468 void RTC_TrimDisable(void);
<> 157:ff67d9f36b67 469
<> 157:ff67d9f36b67 470 /**@}*/
<> 157:ff67d9f36b67 471
<> 157:ff67d9f36b67 472 #ifdef __cplusplus
<> 157:ff67d9f36b67 473 }
<> 157:ff67d9f36b67 474 #endif
<> 157:ff67d9f36b67 475
<> 157:ff67d9f36b67 476 #endif /* _RTC_H */