Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /* mbed Microcontroller Library
sam_grove 5:3f93dd1d4cb3 2 * Copyright (c) 2006-2013 ARM Limited
sam_grove 5:3f93dd1d4cb3 3 *
sam_grove 5:3f93dd1d4cb3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sam_grove 5:3f93dd1d4cb3 5 * you may not use this file except in compliance with the License.
sam_grove 5:3f93dd1d4cb3 6 * You may obtain a copy of the License at
sam_grove 5:3f93dd1d4cb3 7 *
sam_grove 5:3f93dd1d4cb3 8 * http://www.apache.org/licenses/LICENSE-2.0
sam_grove 5:3f93dd1d4cb3 9 *
sam_grove 5:3f93dd1d4cb3 10 * Unless required by applicable law or agreed to in writing, software
sam_grove 5:3f93dd1d4cb3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sam_grove 5:3f93dd1d4cb3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sam_grove 5:3f93dd1d4cb3 13 * See the License for the specific language governing permissions and
sam_grove 5:3f93dd1d4cb3 14 * limitations under the License.
sam_grove 5:3f93dd1d4cb3 15 */
sam_grove 5:3f93dd1d4cb3 16 #include <math.h>
sam_grove 5:3f93dd1d4cb3 17
sam_grove 5:3f93dd1d4cb3 18 #include "spi_api.h"
sam_grove 5:3f93dd1d4cb3 19 #include "cmsis.h"
sam_grove 5:3f93dd1d4cb3 20 #include "pinmap.h"
sam_grove 5:3f93dd1d4cb3 21 #include "error.h"
sam_grove 5:3f93dd1d4cb3 22
sam_grove 5:3f93dd1d4cb3 23 static const PinMap PinMap_SPI_SCLK[] = {
sam_grove 5:3f93dd1d4cb3 24 {P0_7 , SPI_1, 2},
sam_grove 5:3f93dd1d4cb3 25 {P0_15, SPI_0, 2},
sam_grove 5:3f93dd1d4cb3 26 {P1_20, SPI_0, 3},
sam_grove 5:3f93dd1d4cb3 27 {P1_31, SPI_1, 2},
sam_grove 5:3f93dd1d4cb3 28 {NC , NC , 0}
sam_grove 5:3f93dd1d4cb3 29 };
sam_grove 5:3f93dd1d4cb3 30
sam_grove 5:3f93dd1d4cb3 31 static const PinMap PinMap_SPI_MOSI[] = {
sam_grove 5:3f93dd1d4cb3 32 {P0_9 , SPI_1, 2},
sam_grove 5:3f93dd1d4cb3 33 {P0_13, SPI_1, 2},
sam_grove 5:3f93dd1d4cb3 34 {P0_18, SPI_0, 2},
sam_grove 5:3f93dd1d4cb3 35 {P1_24, SPI_0, 3},
sam_grove 5:3f93dd1d4cb3 36 {NC , NC , 0}
sam_grove 5:3f93dd1d4cb3 37 };
sam_grove 5:3f93dd1d4cb3 38
sam_grove 5:3f93dd1d4cb3 39 static const PinMap PinMap_SPI_MISO[] = {
sam_grove 5:3f93dd1d4cb3 40 {P0_8 , SPI_1, 2},
sam_grove 5:3f93dd1d4cb3 41 {P0_12, SPI_1, 2},
sam_grove 5:3f93dd1d4cb3 42 {P0_17, SPI_0, 2},
sam_grove 5:3f93dd1d4cb3 43 {P1_23, SPI_0, 3},
sam_grove 5:3f93dd1d4cb3 44 {NC , NC , 0}
sam_grove 5:3f93dd1d4cb3 45 };
sam_grove 5:3f93dd1d4cb3 46
sam_grove 5:3f93dd1d4cb3 47 static const PinMap PinMap_SPI_SSEL[] = {
sam_grove 5:3f93dd1d4cb3 48 {P0_6 , SPI_1, 2},
sam_grove 5:3f93dd1d4cb3 49 {P0_11, SPI_1, 2},
sam_grove 5:3f93dd1d4cb3 50 {P0_16, SPI_0, 2},
sam_grove 5:3f93dd1d4cb3 51 {P1_21, SPI_0, 3},
sam_grove 5:3f93dd1d4cb3 52 {NC , NC , 0}
sam_grove 5:3f93dd1d4cb3 53 };
sam_grove 5:3f93dd1d4cb3 54
sam_grove 5:3f93dd1d4cb3 55 static inline int ssp_disable(spi_t *obj);
sam_grove 5:3f93dd1d4cb3 56 static inline int ssp_enable(spi_t *obj);
sam_grove 5:3f93dd1d4cb3 57
sam_grove 5:3f93dd1d4cb3 58 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
sam_grove 5:3f93dd1d4cb3 59 // determine the SPI to use
sam_grove 5:3f93dd1d4cb3 60 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sam_grove 5:3f93dd1d4cb3 61 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
sam_grove 5:3f93dd1d4cb3 62 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sam_grove 5:3f93dd1d4cb3 63 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sam_grove 5:3f93dd1d4cb3 64 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
sam_grove 5:3f93dd1d4cb3 65 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
sam_grove 5:3f93dd1d4cb3 66 obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
sam_grove 5:3f93dd1d4cb3 67 if ((int)obj->spi == NC) {
sam_grove 5:3f93dd1d4cb3 68 error("SPI pinout mapping failed");
sam_grove 5:3f93dd1d4cb3 69 }
sam_grove 5:3f93dd1d4cb3 70
sam_grove 5:3f93dd1d4cb3 71 // enable power and clocking
sam_grove 5:3f93dd1d4cb3 72 switch ((int)obj->spi) {
sam_grove 5:3f93dd1d4cb3 73 case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
sam_grove 5:3f93dd1d4cb3 74 case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
sam_grove 5:3f93dd1d4cb3 75 }
sam_grove 5:3f93dd1d4cb3 76
sam_grove 5:3f93dd1d4cb3 77 // set default format and frequency
sam_grove 5:3f93dd1d4cb3 78 if (ssel == NC) {
sam_grove 5:3f93dd1d4cb3 79 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
sam_grove 5:3f93dd1d4cb3 80 } else {
sam_grove 5:3f93dd1d4cb3 81 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
sam_grove 5:3f93dd1d4cb3 82 }
sam_grove 5:3f93dd1d4cb3 83 spi_frequency(obj, 1000000);
sam_grove 5:3f93dd1d4cb3 84
sam_grove 5:3f93dd1d4cb3 85 // enable the ssp channel
sam_grove 5:3f93dd1d4cb3 86 ssp_enable(obj);
sam_grove 5:3f93dd1d4cb3 87
sam_grove 5:3f93dd1d4cb3 88 // pin out the spi pins
sam_grove 5:3f93dd1d4cb3 89 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sam_grove 5:3f93dd1d4cb3 90 pinmap_pinout(miso, PinMap_SPI_MISO);
sam_grove 5:3f93dd1d4cb3 91 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sam_grove 5:3f93dd1d4cb3 92 if (ssel != NC) {
sam_grove 5:3f93dd1d4cb3 93 pinmap_pinout(ssel, PinMap_SPI_SSEL);
sam_grove 5:3f93dd1d4cb3 94 }
sam_grove 5:3f93dd1d4cb3 95 }
sam_grove 5:3f93dd1d4cb3 96
sam_grove 5:3f93dd1d4cb3 97 void spi_free(spi_t *obj) {}
sam_grove 5:3f93dd1d4cb3 98
sam_grove 5:3f93dd1d4cb3 99 void spi_format(spi_t *obj, int bits, int mode, int slave) {
sam_grove 5:3f93dd1d4cb3 100 ssp_disable(obj);
sam_grove 5:3f93dd1d4cb3 101 if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
sam_grove 5:3f93dd1d4cb3 102 error("SPI format error");
sam_grove 5:3f93dd1d4cb3 103 }
sam_grove 5:3f93dd1d4cb3 104
sam_grove 5:3f93dd1d4cb3 105 int polarity = (mode & 0x2) ? 1 : 0;
sam_grove 5:3f93dd1d4cb3 106 int phase = (mode & 0x1) ? 1 : 0;
sam_grove 5:3f93dd1d4cb3 107
sam_grove 5:3f93dd1d4cb3 108 // set it up
sam_grove 5:3f93dd1d4cb3 109 int DSS = bits - 1; // DSS (data select size)
sam_grove 5:3f93dd1d4cb3 110 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
sam_grove 5:3f93dd1d4cb3 111 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
sam_grove 5:3f93dd1d4cb3 112
sam_grove 5:3f93dd1d4cb3 113 int FRF = 0; // FRF (frame format) = SPI
sam_grove 5:3f93dd1d4cb3 114 uint32_t tmp = obj->spi->CR0;
sam_grove 5:3f93dd1d4cb3 115 tmp &= ~(0xFFFF);
sam_grove 5:3f93dd1d4cb3 116 tmp |= DSS << 0
sam_grove 5:3f93dd1d4cb3 117 | FRF << 4
sam_grove 5:3f93dd1d4cb3 118 | SPO << 6
sam_grove 5:3f93dd1d4cb3 119 | SPH << 7;
sam_grove 5:3f93dd1d4cb3 120 obj->spi->CR0 = tmp;
sam_grove 5:3f93dd1d4cb3 121
sam_grove 5:3f93dd1d4cb3 122 tmp = obj->spi->CR1;
sam_grove 5:3f93dd1d4cb3 123 tmp &= ~(0xD);
sam_grove 5:3f93dd1d4cb3 124 tmp |= 0 << 0 // LBM - loop back mode - off
sam_grove 5:3f93dd1d4cb3 125 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
sam_grove 5:3f93dd1d4cb3 126 | 0 << 3; // SOD - slave output disable - na
sam_grove 5:3f93dd1d4cb3 127 obj->spi->CR1 = tmp;
sam_grove 5:3f93dd1d4cb3 128
sam_grove 5:3f93dd1d4cb3 129 ssp_enable(obj);
sam_grove 5:3f93dd1d4cb3 130 }
sam_grove 5:3f93dd1d4cb3 131
sam_grove 5:3f93dd1d4cb3 132 void spi_frequency(spi_t *obj, int hz) {
sam_grove 5:3f93dd1d4cb3 133 ssp_disable(obj);
sam_grove 5:3f93dd1d4cb3 134
sam_grove 5:3f93dd1d4cb3 135 // setup the spi clock diveder to /1
sam_grove 5:3f93dd1d4cb3 136 switch ((int)obj->spi) {
sam_grove 5:3f93dd1d4cb3 137 case SPI_0:
sam_grove 5:3f93dd1d4cb3 138 LPC_SC->PCLKSEL1 &= ~(3 << 10);
sam_grove 5:3f93dd1d4cb3 139 LPC_SC->PCLKSEL1 |= (1 << 10);
sam_grove 5:3f93dd1d4cb3 140 break;
sam_grove 5:3f93dd1d4cb3 141 case SPI_1:
sam_grove 5:3f93dd1d4cb3 142 LPC_SC->PCLKSEL0 &= ~(3 << 20);
sam_grove 5:3f93dd1d4cb3 143 LPC_SC->PCLKSEL0 |= (1 << 20);
sam_grove 5:3f93dd1d4cb3 144 break;
sam_grove 5:3f93dd1d4cb3 145 }
sam_grove 5:3f93dd1d4cb3 146
sam_grove 5:3f93dd1d4cb3 147 uint32_t PCLK = SystemCoreClock;
sam_grove 5:3f93dd1d4cb3 148
sam_grove 5:3f93dd1d4cb3 149 int prescaler;
sam_grove 5:3f93dd1d4cb3 150
sam_grove 5:3f93dd1d4cb3 151 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
sam_grove 5:3f93dd1d4cb3 152 int prescale_hz = PCLK / prescaler;
sam_grove 5:3f93dd1d4cb3 153
sam_grove 5:3f93dd1d4cb3 154 // calculate the divider
sam_grove 5:3f93dd1d4cb3 155 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
sam_grove 5:3f93dd1d4cb3 156
sam_grove 5:3f93dd1d4cb3 157 // check we can support the divider
sam_grove 5:3f93dd1d4cb3 158 if (divider < 256) {
sam_grove 5:3f93dd1d4cb3 159 // prescaler
sam_grove 5:3f93dd1d4cb3 160 obj->spi->CPSR = prescaler;
sam_grove 5:3f93dd1d4cb3 161
sam_grove 5:3f93dd1d4cb3 162 // divider
sam_grove 5:3f93dd1d4cb3 163 obj->spi->CR0 &= ~(0xFFFF << 8);
sam_grove 5:3f93dd1d4cb3 164 obj->spi->CR0 |= (divider - 1) << 8;
sam_grove 5:3f93dd1d4cb3 165 ssp_enable(obj);
sam_grove 5:3f93dd1d4cb3 166 return;
sam_grove 5:3f93dd1d4cb3 167 }
sam_grove 5:3f93dd1d4cb3 168 }
sam_grove 5:3f93dd1d4cb3 169 error("Couldn't setup requested SPI frequency");
sam_grove 5:3f93dd1d4cb3 170 }
sam_grove 5:3f93dd1d4cb3 171
sam_grove 5:3f93dd1d4cb3 172 static inline int ssp_disable(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 173 return obj->spi->CR1 &= ~(1 << 1);
sam_grove 5:3f93dd1d4cb3 174 }
sam_grove 5:3f93dd1d4cb3 175
sam_grove 5:3f93dd1d4cb3 176 static inline int ssp_enable(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 177 return obj->spi->CR1 |= (1 << 1);
sam_grove 5:3f93dd1d4cb3 178 }
sam_grove 5:3f93dd1d4cb3 179
sam_grove 5:3f93dd1d4cb3 180 static inline int ssp_readable(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 181 return obj->spi->SR & (1 << 2);
sam_grove 5:3f93dd1d4cb3 182 }
sam_grove 5:3f93dd1d4cb3 183
sam_grove 5:3f93dd1d4cb3 184 static inline int ssp_writeable(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 185 return obj->spi->SR & (1 << 1);
sam_grove 5:3f93dd1d4cb3 186 }
sam_grove 5:3f93dd1d4cb3 187
sam_grove 5:3f93dd1d4cb3 188 static inline void ssp_write(spi_t *obj, int value) {
sam_grove 5:3f93dd1d4cb3 189 while (!ssp_writeable(obj));
sam_grove 5:3f93dd1d4cb3 190 obj->spi->DR = value;
sam_grove 5:3f93dd1d4cb3 191 }
sam_grove 5:3f93dd1d4cb3 192
sam_grove 5:3f93dd1d4cb3 193 static inline int ssp_read(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 194 while (!ssp_readable(obj));
sam_grove 5:3f93dd1d4cb3 195 return obj->spi->DR;
sam_grove 5:3f93dd1d4cb3 196 }
sam_grove 5:3f93dd1d4cb3 197
sam_grove 5:3f93dd1d4cb3 198 static inline int ssp_busy(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 199 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
sam_grove 5:3f93dd1d4cb3 200 }
sam_grove 5:3f93dd1d4cb3 201
sam_grove 5:3f93dd1d4cb3 202 int spi_master_write(spi_t *obj, int value) {
sam_grove 5:3f93dd1d4cb3 203 ssp_write(obj, value);
sam_grove 5:3f93dd1d4cb3 204 return ssp_read(obj);
sam_grove 5:3f93dd1d4cb3 205 }
sam_grove 5:3f93dd1d4cb3 206
sam_grove 5:3f93dd1d4cb3 207 int spi_slave_receive(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 208 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
sam_grove 5:3f93dd1d4cb3 209 };
sam_grove 5:3f93dd1d4cb3 210
sam_grove 5:3f93dd1d4cb3 211 int spi_slave_read(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 212 return obj->spi->DR;
sam_grove 5:3f93dd1d4cb3 213 }
sam_grove 5:3f93dd1d4cb3 214
sam_grove 5:3f93dd1d4cb3 215 void spi_slave_write(spi_t *obj, int value) {
sam_grove 5:3f93dd1d4cb3 216 while (ssp_writeable(obj) == 0) ;
sam_grove 5:3f93dd1d4cb3 217 obj->spi->DR = value;
sam_grove 5:3f93dd1d4cb3 218 }
sam_grove 5:3f93dd1d4cb3 219
sam_grove 5:3f93dd1d4cb3 220 int spi_busy(spi_t *obj) {
sam_grove 5:3f93dd1d4cb3 221 return ssp_busy(obj);
sam_grove 5:3f93dd1d4cb3 222 }