Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/hal/TARGET_NXP/TARGET_LPC176X/i2c_api.c@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /* mbed Microcontroller Library
sam_grove 5:3f93dd1d4cb3 2 * Copyright (c) 2006-2013 ARM Limited
sam_grove 5:3f93dd1d4cb3 3 *
sam_grove 5:3f93dd1d4cb3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sam_grove 5:3f93dd1d4cb3 5 * you may not use this file except in compliance with the License.
sam_grove 5:3f93dd1d4cb3 6 * You may obtain a copy of the License at
sam_grove 5:3f93dd1d4cb3 7 *
sam_grove 5:3f93dd1d4cb3 8 * http://www.apache.org/licenses/LICENSE-2.0
sam_grove 5:3f93dd1d4cb3 9 *
sam_grove 5:3f93dd1d4cb3 10 * Unless required by applicable law or agreed to in writing, software
sam_grove 5:3f93dd1d4cb3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sam_grove 5:3f93dd1d4cb3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sam_grove 5:3f93dd1d4cb3 13 * See the License for the specific language governing permissions and
sam_grove 5:3f93dd1d4cb3 14 * limitations under the License.
sam_grove 5:3f93dd1d4cb3 15 */
sam_grove 5:3f93dd1d4cb3 16 #include "i2c_api.h"
sam_grove 5:3f93dd1d4cb3 17 #include "cmsis.h"
sam_grove 5:3f93dd1d4cb3 18 #include "pinmap.h"
sam_grove 5:3f93dd1d4cb3 19 #include "error.h"
sam_grove 5:3f93dd1d4cb3 20
sam_grove 5:3f93dd1d4cb3 21 static const PinMap PinMap_I2C_SDA[] = {
sam_grove 5:3f93dd1d4cb3 22 {P0_0 , I2C_1, 3},
sam_grove 5:3f93dd1d4cb3 23 {P0_10, I2C_2, 2},
sam_grove 5:3f93dd1d4cb3 24 {P0_19, I2C_1, 3},
sam_grove 5:3f93dd1d4cb3 25 {P0_27, I2C_0, 1},
sam_grove 5:3f93dd1d4cb3 26 {NC , NC , 0}
sam_grove 5:3f93dd1d4cb3 27 };
sam_grove 5:3f93dd1d4cb3 28
sam_grove 5:3f93dd1d4cb3 29 static const PinMap PinMap_I2C_SCL[] = {
sam_grove 5:3f93dd1d4cb3 30 {P0_1 , I2C_1, 3},
sam_grove 5:3f93dd1d4cb3 31 {P0_11, I2C_2, 2},
sam_grove 5:3f93dd1d4cb3 32 {P0_20, I2C_1, 3},
sam_grove 5:3f93dd1d4cb3 33 {P0_28, I2C_0, 1},
sam_grove 5:3f93dd1d4cb3 34 {NC , NC, 0}
sam_grove 5:3f93dd1d4cb3 35 };
sam_grove 5:3f93dd1d4cb3 36
sam_grove 5:3f93dd1d4cb3 37 #define I2C_CONSET(x) (x->i2c->I2CONSET)
sam_grove 5:3f93dd1d4cb3 38 #define I2C_CONCLR(x) (x->i2c->I2CONCLR)
sam_grove 5:3f93dd1d4cb3 39 #define I2C_STAT(x) (x->i2c->I2STAT)
sam_grove 5:3f93dd1d4cb3 40 #define I2C_DAT(x) (x->i2c->I2DAT)
sam_grove 5:3f93dd1d4cb3 41 #define I2C_SCLL(x, val) (x->i2c->I2SCLL = val)
sam_grove 5:3f93dd1d4cb3 42 #define I2C_SCLH(x, val) (x->i2c->I2SCLH = val)
sam_grove 5:3f93dd1d4cb3 43
sam_grove 5:3f93dd1d4cb3 44 static const uint32_t I2C_addr_offset[2][4] = {
sam_grove 5:3f93dd1d4cb3 45 {0x0C, 0x20, 0x24, 0x28},
sam_grove 5:3f93dd1d4cb3 46 {0x30, 0x34, 0x38, 0x3C}
sam_grove 5:3f93dd1d4cb3 47 };
sam_grove 5:3f93dd1d4cb3 48
sam_grove 5:3f93dd1d4cb3 49 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
sam_grove 5:3f93dd1d4cb3 50 I2C_CONCLR(obj) = (start << 5)
sam_grove 5:3f93dd1d4cb3 51 | (stop << 4)
sam_grove 5:3f93dd1d4cb3 52 | (interrupt << 3)
sam_grove 5:3f93dd1d4cb3 53 | (acknowledge << 2);
sam_grove 5:3f93dd1d4cb3 54 }
sam_grove 5:3f93dd1d4cb3 55
sam_grove 5:3f93dd1d4cb3 56 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
sam_grove 5:3f93dd1d4cb3 57 I2C_CONSET(obj) = (start << 5)
sam_grove 5:3f93dd1d4cb3 58 | (stop << 4)
sam_grove 5:3f93dd1d4cb3 59 | (interrupt << 3)
sam_grove 5:3f93dd1d4cb3 60 | (acknowledge << 2);
sam_grove 5:3f93dd1d4cb3 61 }
sam_grove 5:3f93dd1d4cb3 62
sam_grove 5:3f93dd1d4cb3 63 // Clear the Serial Interrupt (SI)
sam_grove 5:3f93dd1d4cb3 64 static inline void i2c_clear_SI(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 65 i2c_conclr(obj, 0, 0, 1, 0);
sam_grove 5:3f93dd1d4cb3 66 }
sam_grove 5:3f93dd1d4cb3 67
sam_grove 5:3f93dd1d4cb3 68 static inline int i2c_status(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 69 return I2C_STAT(obj);
sam_grove 5:3f93dd1d4cb3 70 }
sam_grove 5:3f93dd1d4cb3 71
sam_grove 5:3f93dd1d4cb3 72 // Wait until the Serial Interrupt (SI) is set
sam_grove 5:3f93dd1d4cb3 73 static int i2c_wait_SI(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 74 int timeout = 0;
sam_grove 5:3f93dd1d4cb3 75 while (!(I2C_CONSET(obj) & (1 << 3))) {
sam_grove 5:3f93dd1d4cb3 76 timeout++;
sam_grove 5:3f93dd1d4cb3 77 if (timeout > 100000) return -1;
sam_grove 5:3f93dd1d4cb3 78 }
sam_grove 5:3f93dd1d4cb3 79 return 0;
sam_grove 5:3f93dd1d4cb3 80 }
sam_grove 5:3f93dd1d4cb3 81
sam_grove 5:3f93dd1d4cb3 82 static inline void i2c_interface_enable(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 83 I2C_CONSET(obj) = 0x40;
sam_grove 5:3f93dd1d4cb3 84 }
sam_grove 5:3f93dd1d4cb3 85
sam_grove 5:3f93dd1d4cb3 86 static inline void i2c_power_enable(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 87 switch ((int)obj->i2c) {
sam_grove 5:3f93dd1d4cb3 88 case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
sam_grove 5:3f93dd1d4cb3 89 case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
sam_grove 5:3f93dd1d4cb3 90 case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
sam_grove 5:3f93dd1d4cb3 91 }
sam_grove 5:3f93dd1d4cb3 92 }
sam_grove 5:3f93dd1d4cb3 93
sam_grove 5:3f93dd1d4cb3 94 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
sam_grove 5:3f93dd1d4cb3 95 // determine the SPI to use
sam_grove 5:3f93dd1d4cb3 96 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
sam_grove 5:3f93dd1d4cb3 97 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
sam_grove 5:3f93dd1d4cb3 98 obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
sam_grove 5:3f93dd1d4cb3 99
sam_grove 5:3f93dd1d4cb3 100 if ((int)obj->i2c == NC) {
sam_grove 5:3f93dd1d4cb3 101 error("I2C pin mapping failed");
sam_grove 5:3f93dd1d4cb3 102 }
sam_grove 5:3f93dd1d4cb3 103
sam_grove 5:3f93dd1d4cb3 104 // enable power
sam_grove 5:3f93dd1d4cb3 105 i2c_power_enable(obj);
sam_grove 5:3f93dd1d4cb3 106
sam_grove 5:3f93dd1d4cb3 107 // set default frequency at 100k
sam_grove 5:3f93dd1d4cb3 108 i2c_frequency(obj, 100000);
sam_grove 5:3f93dd1d4cb3 109 i2c_conclr(obj, 1, 1, 1, 1);
sam_grove 5:3f93dd1d4cb3 110 i2c_interface_enable(obj);
sam_grove 5:3f93dd1d4cb3 111
sam_grove 5:3f93dd1d4cb3 112 pinmap_pinout(sda, PinMap_I2C_SDA);
sam_grove 5:3f93dd1d4cb3 113 pinmap_pinout(scl, PinMap_I2C_SCL);
sam_grove 5:3f93dd1d4cb3 114 }
sam_grove 5:3f93dd1d4cb3 115
sam_grove 5:3f93dd1d4cb3 116 inline int i2c_start(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 117 int status = 0;
sam_grove 5:3f93dd1d4cb3 118 // 8.1 Before master mode can be entered, I2CON must be initialised to:
sam_grove 5:3f93dd1d4cb3 119 // - I2EN STA STO SI AA - -
sam_grove 5:3f93dd1d4cb3 120 // - 1 0 0 0 x - -
sam_grove 5:3f93dd1d4cb3 121 // if AA = 0, it can't enter slave mode
sam_grove 5:3f93dd1d4cb3 122 i2c_conclr(obj, 1, 1, 1, 1);
sam_grove 5:3f93dd1d4cb3 123
sam_grove 5:3f93dd1d4cb3 124 // The master mode may now be entered by setting the STA bit
sam_grove 5:3f93dd1d4cb3 125 // this will generate a start condition when the bus becomes free
sam_grove 5:3f93dd1d4cb3 126 i2c_conset(obj, 1, 0, 0, 1);
sam_grove 5:3f93dd1d4cb3 127
sam_grove 5:3f93dd1d4cb3 128 i2c_wait_SI(obj);
sam_grove 5:3f93dd1d4cb3 129 status = i2c_status(obj);
sam_grove 5:3f93dd1d4cb3 130
sam_grove 5:3f93dd1d4cb3 131 // Clear start bit now transmitted, and interrupt bit
sam_grove 5:3f93dd1d4cb3 132 i2c_conclr(obj, 1, 0, 0, 0);
sam_grove 5:3f93dd1d4cb3 133 return status;
sam_grove 5:3f93dd1d4cb3 134 }
sam_grove 5:3f93dd1d4cb3 135
sam_grove 5:3f93dd1d4cb3 136 inline int i2c_stop(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 137 int timeout = 0;
sam_grove 5:3f93dd1d4cb3 138
sam_grove 5:3f93dd1d4cb3 139 // write the stop bit
sam_grove 5:3f93dd1d4cb3 140 i2c_conset(obj, 0, 1, 0, 0);
sam_grove 5:3f93dd1d4cb3 141 i2c_clear_SI(obj);
sam_grove 5:3f93dd1d4cb3 142
sam_grove 5:3f93dd1d4cb3 143 // wait for STO bit to reset
sam_grove 5:3f93dd1d4cb3 144 while(I2C_CONSET(obj) & (1 << 4)) {
sam_grove 5:3f93dd1d4cb3 145 timeout ++;
sam_grove 5:3f93dd1d4cb3 146 if (timeout > 100000) return 1;
sam_grove 5:3f93dd1d4cb3 147 }
sam_grove 5:3f93dd1d4cb3 148
sam_grove 5:3f93dd1d4cb3 149 return 0;
sam_grove 5:3f93dd1d4cb3 150 }
sam_grove 5:3f93dd1d4cb3 151
sam_grove 5:3f93dd1d4cb3 152 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
sam_grove 5:3f93dd1d4cb3 153 // write the data
sam_grove 5:3f93dd1d4cb3 154 I2C_DAT(obj) = value;
sam_grove 5:3f93dd1d4cb3 155
sam_grove 5:3f93dd1d4cb3 156 // clear SI to init a send
sam_grove 5:3f93dd1d4cb3 157 i2c_clear_SI(obj);
sam_grove 5:3f93dd1d4cb3 158
sam_grove 5:3f93dd1d4cb3 159 // wait and return status
sam_grove 5:3f93dd1d4cb3 160 i2c_wait_SI(obj);
sam_grove 5:3f93dd1d4cb3 161 return i2c_status(obj);
sam_grove 5:3f93dd1d4cb3 162 }
sam_grove 5:3f93dd1d4cb3 163
sam_grove 5:3f93dd1d4cb3 164 static inline int i2c_do_read(i2c_t *obj, int last) {
sam_grove 5:3f93dd1d4cb3 165 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
sam_grove 5:3f93dd1d4cb3 166 if(last) {
sam_grove 5:3f93dd1d4cb3 167 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
sam_grove 5:3f93dd1d4cb3 168 } else {
sam_grove 5:3f93dd1d4cb3 169 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
sam_grove 5:3f93dd1d4cb3 170 }
sam_grove 5:3f93dd1d4cb3 171
sam_grove 5:3f93dd1d4cb3 172 // accept byte
sam_grove 5:3f93dd1d4cb3 173 i2c_clear_SI(obj);
sam_grove 5:3f93dd1d4cb3 174
sam_grove 5:3f93dd1d4cb3 175 // wait for it to arrive
sam_grove 5:3f93dd1d4cb3 176 i2c_wait_SI(obj);
sam_grove 5:3f93dd1d4cb3 177
sam_grove 5:3f93dd1d4cb3 178 // return the data
sam_grove 5:3f93dd1d4cb3 179 return (I2C_DAT(obj) & 0xFF);
sam_grove 5:3f93dd1d4cb3 180 }
sam_grove 5:3f93dd1d4cb3 181
sam_grove 5:3f93dd1d4cb3 182 void i2c_frequency(i2c_t *obj, int hz) {
sam_grove 5:3f93dd1d4cb3 183 // [TODO] set pclk to /4
sam_grove 5:3f93dd1d4cb3 184 uint32_t PCLK = SystemCoreClock / 4;
sam_grove 5:3f93dd1d4cb3 185
sam_grove 5:3f93dd1d4cb3 186 uint32_t pulse = PCLK / (hz * 2);
sam_grove 5:3f93dd1d4cb3 187
sam_grove 5:3f93dd1d4cb3 188 // I2C Rate
sam_grove 5:3f93dd1d4cb3 189 I2C_SCLL(obj, pulse);
sam_grove 5:3f93dd1d4cb3 190 I2C_SCLH(obj, pulse);
sam_grove 5:3f93dd1d4cb3 191 }
sam_grove 5:3f93dd1d4cb3 192
sam_grove 5:3f93dd1d4cb3 193 // The I2C does a read or a write as a whole operation
sam_grove 5:3f93dd1d4cb3 194 // There are two types of error conditions it can encounter
sam_grove 5:3f93dd1d4cb3 195 // 1) it can not obtain the bus
sam_grove 5:3f93dd1d4cb3 196 // 2) it gets error responses at part of the transmission
sam_grove 5:3f93dd1d4cb3 197 //
sam_grove 5:3f93dd1d4cb3 198 // We tackle them as follows:
sam_grove 5:3f93dd1d4cb3 199 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
sam_grove 5:3f93dd1d4cb3 200 // which basically turns it in to a 2)
sam_grove 5:3f93dd1d4cb3 201 // 2) on error, we use the standard error mechanisms to report/debug
sam_grove 5:3f93dd1d4cb3 202 //
sam_grove 5:3f93dd1d4cb3 203 // Therefore an I2C transaction should always complete. If it doesn't it is usually
sam_grove 5:3f93dd1d4cb3 204 // because something is setup wrong (e.g. wiring), and we don't need to programatically
sam_grove 5:3f93dd1d4cb3 205 // check for that
sam_grove 5:3f93dd1d4cb3 206
sam_grove 5:3f93dd1d4cb3 207 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
sam_grove 5:3f93dd1d4cb3 208 int count, status;
sam_grove 5:3f93dd1d4cb3 209
sam_grove 5:3f93dd1d4cb3 210 status = i2c_start(obj);
sam_grove 5:3f93dd1d4cb3 211
sam_grove 5:3f93dd1d4cb3 212 if ((status != 0x10) && (status != 0x08)) {
sam_grove 5:3f93dd1d4cb3 213 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 214 return I2C_ERROR_BUS_BUSY;
sam_grove 5:3f93dd1d4cb3 215 }
sam_grove 5:3f93dd1d4cb3 216
sam_grove 5:3f93dd1d4cb3 217 status = i2c_do_write(obj, (address | 0x01), 1);
sam_grove 5:3f93dd1d4cb3 218 if (status != 0x40) {
sam_grove 5:3f93dd1d4cb3 219 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 220 return I2C_ERROR_NO_SLAVE;
sam_grove 5:3f93dd1d4cb3 221 }
sam_grove 5:3f93dd1d4cb3 222
sam_grove 5:3f93dd1d4cb3 223 // Read in all except last byte
sam_grove 5:3f93dd1d4cb3 224 for (count = 0; count < (length - 1); count++) {
sam_grove 5:3f93dd1d4cb3 225 int value = i2c_do_read(obj, 0);
sam_grove 5:3f93dd1d4cb3 226 status = i2c_status(obj);
sam_grove 5:3f93dd1d4cb3 227 if (status != 0x50) {
sam_grove 5:3f93dd1d4cb3 228 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 229 return count;
sam_grove 5:3f93dd1d4cb3 230 }
sam_grove 5:3f93dd1d4cb3 231 data[count] = (char) value;
sam_grove 5:3f93dd1d4cb3 232 }
sam_grove 5:3f93dd1d4cb3 233
sam_grove 5:3f93dd1d4cb3 234 // read in last byte
sam_grove 5:3f93dd1d4cb3 235 int value = i2c_do_read(obj, 1);
sam_grove 5:3f93dd1d4cb3 236 status = i2c_status(obj);
sam_grove 5:3f93dd1d4cb3 237 if (status != 0x58) {
sam_grove 5:3f93dd1d4cb3 238 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 239 return length - 1;
sam_grove 5:3f93dd1d4cb3 240 }
sam_grove 5:3f93dd1d4cb3 241
sam_grove 5:3f93dd1d4cb3 242 data[count] = (char) value;
sam_grove 5:3f93dd1d4cb3 243
sam_grove 5:3f93dd1d4cb3 244 // If not repeated start, send stop.
sam_grove 5:3f93dd1d4cb3 245 if (stop) {
sam_grove 5:3f93dd1d4cb3 246 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 247 }
sam_grove 5:3f93dd1d4cb3 248
sam_grove 5:3f93dd1d4cb3 249 return length;
sam_grove 5:3f93dd1d4cb3 250 }
sam_grove 5:3f93dd1d4cb3 251
sam_grove 5:3f93dd1d4cb3 252 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
sam_grove 5:3f93dd1d4cb3 253 int i, status;
sam_grove 5:3f93dd1d4cb3 254
sam_grove 5:3f93dd1d4cb3 255 status = i2c_start(obj);
sam_grove 5:3f93dd1d4cb3 256
sam_grove 5:3f93dd1d4cb3 257 if ((status != 0x10) && (status != 0x08)) {
sam_grove 5:3f93dd1d4cb3 258 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 259 return I2C_ERROR_BUS_BUSY;
sam_grove 5:3f93dd1d4cb3 260 }
sam_grove 5:3f93dd1d4cb3 261
sam_grove 5:3f93dd1d4cb3 262 status = i2c_do_write(obj, (address & 0xFE), 1);
sam_grove 5:3f93dd1d4cb3 263 if (status != 0x18) {
sam_grove 5:3f93dd1d4cb3 264 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 265 return I2C_ERROR_NO_SLAVE;
sam_grove 5:3f93dd1d4cb3 266 }
sam_grove 5:3f93dd1d4cb3 267
sam_grove 5:3f93dd1d4cb3 268 for (i=0; i<length; i++) {
sam_grove 5:3f93dd1d4cb3 269 status = i2c_do_write(obj, data[i], 0);
sam_grove 5:3f93dd1d4cb3 270 if(status != 0x28) {
sam_grove 5:3f93dd1d4cb3 271 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 272 return i;
sam_grove 5:3f93dd1d4cb3 273 }
sam_grove 5:3f93dd1d4cb3 274 }
sam_grove 5:3f93dd1d4cb3 275
sam_grove 5:3f93dd1d4cb3 276 // clearing the serial interrupt here might cause an unintended rewrite of the last byte
sam_grove 5:3f93dd1d4cb3 277 // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
sam_grove 5:3f93dd1d4cb3 278 // i2c_clear_SI(obj);
sam_grove 5:3f93dd1d4cb3 279
sam_grove 5:3f93dd1d4cb3 280 // If not repeated start, send stop.
sam_grove 5:3f93dd1d4cb3 281 if (stop) {
sam_grove 5:3f93dd1d4cb3 282 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 283 }
sam_grove 5:3f93dd1d4cb3 284
sam_grove 5:3f93dd1d4cb3 285 return length;
sam_grove 5:3f93dd1d4cb3 286 }
sam_grove 5:3f93dd1d4cb3 287
sam_grove 5:3f93dd1d4cb3 288 void i2c_reset(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 289 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 290 }
sam_grove 5:3f93dd1d4cb3 291
sam_grove 5:3f93dd1d4cb3 292 int i2c_byte_read(i2c_t *obj, int last) {
sam_grove 5:3f93dd1d4cb3 293 return (i2c_do_read(obj, last) & 0xFF);
sam_grove 5:3f93dd1d4cb3 294 }
sam_grove 5:3f93dd1d4cb3 295
sam_grove 5:3f93dd1d4cb3 296 int i2c_byte_write(i2c_t *obj, int data) {
sam_grove 5:3f93dd1d4cb3 297 int ack;
sam_grove 5:3f93dd1d4cb3 298 int status = i2c_do_write(obj, (data & 0xFF), 0);
sam_grove 5:3f93dd1d4cb3 299
sam_grove 5:3f93dd1d4cb3 300 switch(status) {
sam_grove 5:3f93dd1d4cb3 301 case 0x18: case 0x28: // Master transmit ACKs
sam_grove 5:3f93dd1d4cb3 302 ack = 1;
sam_grove 5:3f93dd1d4cb3 303 break;
sam_grove 5:3f93dd1d4cb3 304 case 0x40: // Master receive address transmitted ACK
sam_grove 5:3f93dd1d4cb3 305 ack = 1;
sam_grove 5:3f93dd1d4cb3 306 break;
sam_grove 5:3f93dd1d4cb3 307 case 0xB8: // Slave transmit ACK
sam_grove 5:3f93dd1d4cb3 308 ack = 1;
sam_grove 5:3f93dd1d4cb3 309 break;
sam_grove 5:3f93dd1d4cb3 310 default:
sam_grove 5:3f93dd1d4cb3 311 ack = 0;
sam_grove 5:3f93dd1d4cb3 312 break;
sam_grove 5:3f93dd1d4cb3 313 }
sam_grove 5:3f93dd1d4cb3 314
sam_grove 5:3f93dd1d4cb3 315 return ack;
sam_grove 5:3f93dd1d4cb3 316 }
sam_grove 5:3f93dd1d4cb3 317
sam_grove 5:3f93dd1d4cb3 318 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
sam_grove 5:3f93dd1d4cb3 319 if (enable_slave != 0) {
sam_grove 5:3f93dd1d4cb3 320 i2c_conclr(obj, 1, 1, 1, 0);
sam_grove 5:3f93dd1d4cb3 321 i2c_conset(obj, 0, 0, 0, 1);
sam_grove 5:3f93dd1d4cb3 322 } else {
sam_grove 5:3f93dd1d4cb3 323 i2c_conclr(obj, 1, 1, 1, 1);
sam_grove 5:3f93dd1d4cb3 324 }
sam_grove 5:3f93dd1d4cb3 325 }
sam_grove 5:3f93dd1d4cb3 326
sam_grove 5:3f93dd1d4cb3 327 int i2c_slave_receive(i2c_t *obj) {
sam_grove 5:3f93dd1d4cb3 328 int status;
sam_grove 5:3f93dd1d4cb3 329 int retval;
sam_grove 5:3f93dd1d4cb3 330
sam_grove 5:3f93dd1d4cb3 331 status = i2c_status(obj);
sam_grove 5:3f93dd1d4cb3 332 switch(status) {
sam_grove 5:3f93dd1d4cb3 333 case 0x60: retval = 3; break;
sam_grove 5:3f93dd1d4cb3 334 case 0x70: retval = 2; break;
sam_grove 5:3f93dd1d4cb3 335 case 0xA8: retval = 1; break;
sam_grove 5:3f93dd1d4cb3 336 default : retval = 0; break;
sam_grove 5:3f93dd1d4cb3 337 }
sam_grove 5:3f93dd1d4cb3 338
sam_grove 5:3f93dd1d4cb3 339 return(retval);
sam_grove 5:3f93dd1d4cb3 340 }
sam_grove 5:3f93dd1d4cb3 341
sam_grove 5:3f93dd1d4cb3 342 int i2c_slave_read(i2c_t *obj, char *data, int length) {
sam_grove 5:3f93dd1d4cb3 343 int count = 0;
sam_grove 5:3f93dd1d4cb3 344 int status;
sam_grove 5:3f93dd1d4cb3 345
sam_grove 5:3f93dd1d4cb3 346 do {
sam_grove 5:3f93dd1d4cb3 347 i2c_clear_SI(obj);
sam_grove 5:3f93dd1d4cb3 348 i2c_wait_SI(obj);
sam_grove 5:3f93dd1d4cb3 349 status = i2c_status(obj);
sam_grove 5:3f93dd1d4cb3 350 if((status == 0x80) || (status == 0x90)) {
sam_grove 5:3f93dd1d4cb3 351 data[count] = I2C_DAT(obj) & 0xFF;
sam_grove 5:3f93dd1d4cb3 352 }
sam_grove 5:3f93dd1d4cb3 353 count++;
sam_grove 5:3f93dd1d4cb3 354 } while (((status == 0x80) || (status == 0x90) ||
sam_grove 5:3f93dd1d4cb3 355 (status == 0x060) || (status == 0x70)) && (count < length));
sam_grove 5:3f93dd1d4cb3 356
sam_grove 5:3f93dd1d4cb3 357 if(status != 0xA0) {
sam_grove 5:3f93dd1d4cb3 358 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 359 }
sam_grove 5:3f93dd1d4cb3 360
sam_grove 5:3f93dd1d4cb3 361 i2c_clear_SI(obj);
sam_grove 5:3f93dd1d4cb3 362
sam_grove 5:3f93dd1d4cb3 363 return count;
sam_grove 5:3f93dd1d4cb3 364 }
sam_grove 5:3f93dd1d4cb3 365
sam_grove 5:3f93dd1d4cb3 366 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
sam_grove 5:3f93dd1d4cb3 367 int count = 0;
sam_grove 5:3f93dd1d4cb3 368 int status;
sam_grove 5:3f93dd1d4cb3 369
sam_grove 5:3f93dd1d4cb3 370 if(length <= 0) {
sam_grove 5:3f93dd1d4cb3 371 return(0);
sam_grove 5:3f93dd1d4cb3 372 }
sam_grove 5:3f93dd1d4cb3 373
sam_grove 5:3f93dd1d4cb3 374 do {
sam_grove 5:3f93dd1d4cb3 375 status = i2c_do_write(obj, data[count], 0);
sam_grove 5:3f93dd1d4cb3 376 count++;
sam_grove 5:3f93dd1d4cb3 377 } while ((count < length) && (status == 0xB8));
sam_grove 5:3f93dd1d4cb3 378
sam_grove 5:3f93dd1d4cb3 379 if ((status != 0xC0) && (status != 0xC8)) {
sam_grove 5:3f93dd1d4cb3 380 i2c_stop(obj);
sam_grove 5:3f93dd1d4cb3 381 }
sam_grove 5:3f93dd1d4cb3 382
sam_grove 5:3f93dd1d4cb3 383 i2c_clear_SI(obj);
sam_grove 5:3f93dd1d4cb3 384
sam_grove 5:3f93dd1d4cb3 385 return(count);
sam_grove 5:3f93dd1d4cb3 386 }
sam_grove 5:3f93dd1d4cb3 387
sam_grove 5:3f93dd1d4cb3 388 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
sam_grove 5:3f93dd1d4cb3 389 uint32_t addr;
sam_grove 5:3f93dd1d4cb3 390
sam_grove 5:3f93dd1d4cb3 391 if ((idx >= 0) && (idx <= 3)) {
sam_grove 5:3f93dd1d4cb3 392 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
sam_grove 5:3f93dd1d4cb3 393 *((uint32_t *) addr) = address & 0xFF;
sam_grove 5:3f93dd1d4cb3 394 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
sam_grove 5:3f93dd1d4cb3 395 *((uint32_t *) addr) = mask & 0xFE;
sam_grove 5:3f93dd1d4cb3 396 }
sam_grove 5:3f93dd1d4cb3 397 }