Mike Pulice
Integrating the ublox LISA C200 modem
Fork of
SprintUSBModemHTTPClientTest
by 
Donatien Garnier
mbed-src/targets/hal/TARGET_NXP/TARGET_LPC176X/ethernet_api.c@5:3f93dd1d4cb3, 2013-09-26 (annotated)
- Committer:
- sam_grove
- Date:
- Thu Sep 26 00:44:20 2013 -0500
- Revision:
- 5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source
to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys
and socket. these have newer versions under mbed_official but were starting
from a know working point
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| sam_grove | 5:3f93dd1d4cb3 | 1 | /* mbed Microcontroller Library |
| sam_grove | 5:3f93dd1d4cb3 | 2 | * Copyright (c) 2006-2013 ARM Limited |
| sam_grove | 5:3f93dd1d4cb3 | 3 | * |
| sam_grove | 5:3f93dd1d4cb3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| sam_grove | 5:3f93dd1d4cb3 | 5 | * you may not use this file except in compliance with the License. |
| sam_grove | 5:3f93dd1d4cb3 | 6 | * You may obtain a copy of the License at |
| sam_grove | 5:3f93dd1d4cb3 | 7 | * |
| sam_grove | 5:3f93dd1d4cb3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| sam_grove | 5:3f93dd1d4cb3 | 9 | * |
| sam_grove | 5:3f93dd1d4cb3 | 10 | * Unless required by applicable law or agreed to in writing, software |
| sam_grove | 5:3f93dd1d4cb3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| sam_grove | 5:3f93dd1d4cb3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| sam_grove | 5:3f93dd1d4cb3 | 13 | * See the License for the specific language governing permissions and |
| sam_grove | 5:3f93dd1d4cb3 | 14 | * limitations under the License. |
| sam_grove | 5:3f93dd1d4cb3 | 15 | */ |
| sam_grove | 5:3f93dd1d4cb3 | 16 | #include "ethernet_api.h" |
| sam_grove | 5:3f93dd1d4cb3 | 17 | |
| sam_grove | 5:3f93dd1d4cb3 | 18 | #include <string.h> |
| sam_grove | 5:3f93dd1d4cb3 | 19 | #include "cmsis.h" |
| sam_grove | 5:3f93dd1d4cb3 | 20 | #include "mbed_interface.h" |
| sam_grove | 5:3f93dd1d4cb3 | 21 | #include "toolchain.h" |
| sam_grove | 5:3f93dd1d4cb3 | 22 | #include "error.h" |
| sam_grove | 5:3f93dd1d4cb3 | 23 | |
| sam_grove | 5:3f93dd1d4cb3 | 24 | #define NEW_LOGIC 0 |
| sam_grove | 5:3f93dd1d4cb3 | 25 | #define NEW_ETH_BUFFER 0 |
| sam_grove | 5:3f93dd1d4cb3 | 26 | |
| sam_grove | 5:3f93dd1d4cb3 | 27 | #if NEW_ETH_BUFFER |
| sam_grove | 5:3f93dd1d4cb3 | 28 | |
| sam_grove | 5:3f93dd1d4cb3 | 29 | #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets) |
| sam_grove | 5:3f93dd1d4cb3 | 30 | #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets) |
| sam_grove | 5:3f93dd1d4cb3 | 31 | |
| sam_grove | 5:3f93dd1d4cb3 | 32 | #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size |
| sam_grove | 5:3f93dd1d4cb3 | 33 | #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length) |
| sam_grove | 5:3f93dd1d4cb3 | 34 | |
| sam_grove | 5:3f93dd1d4cb3 | 35 | #else |
| sam_grove | 5:3f93dd1d4cb3 | 36 | |
| sam_grove | 5:3f93dd1d4cb3 | 37 | // Memfree calculation: |
| sam_grove | 5:3f93dd1d4cb3 | 38 | // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) + |
| sam_grove | 5:3f93dd1d4cb3 | 39 | // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556 |
| sam_grove | 5:3f93dd1d4cb3 | 40 | /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ |
| sam_grove | 5:3f93dd1d4cb3 | 41 | #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ |
| sam_grove | 5:3f93dd1d4cb3 | 42 | #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ |
| sam_grove | 5:3f93dd1d4cb3 | 43 | //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ |
| sam_grove | 5:3f93dd1d4cb3 | 44 | |
| sam_grove | 5:3f93dd1d4cb3 | 45 | //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ |
| sam_grove | 5:3f93dd1d4cb3 | 46 | #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */ |
| sam_grove | 5:3f93dd1d4cb3 | 47 | #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */ |
| sam_grove | 5:3f93dd1d4cb3 | 48 | |
| sam_grove | 5:3f93dd1d4cb3 | 49 | const int ethernet_MTU_SIZE = 0x300; |
| sam_grove | 5:3f93dd1d4cb3 | 50 | |
| sam_grove | 5:3f93dd1d4cb3 | 51 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 52 | |
| sam_grove | 5:3f93dd1d4cb3 | 53 | #define ETHERNET_ADDR_SIZE 6 |
| sam_grove | 5:3f93dd1d4cb3 | 54 | |
| sam_grove | 5:3f93dd1d4cb3 | 55 | PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */ |
| sam_grove | 5:3f93dd1d4cb3 | 56 | unsigned int Packet; |
| sam_grove | 5:3f93dd1d4cb3 | 57 | unsigned int Ctrl; |
| sam_grove | 5:3f93dd1d4cb3 | 58 | }; |
| sam_grove | 5:3f93dd1d4cb3 | 59 | typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; |
| sam_grove | 5:3f93dd1d4cb3 | 60 | |
| sam_grove | 5:3f93dd1d4cb3 | 61 | PACKED struct RX_STAT_TypeDef { /* RX Status struct */ |
| sam_grove | 5:3f93dd1d4cb3 | 62 | unsigned int Info; |
| sam_grove | 5:3f93dd1d4cb3 | 63 | unsigned int HashCRC; |
| sam_grove | 5:3f93dd1d4cb3 | 64 | }; |
| sam_grove | 5:3f93dd1d4cb3 | 65 | typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; |
| sam_grove | 5:3f93dd1d4cb3 | 66 | |
| sam_grove | 5:3f93dd1d4cb3 | 67 | PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */ |
| sam_grove | 5:3f93dd1d4cb3 | 68 | unsigned int Packet; |
| sam_grove | 5:3f93dd1d4cb3 | 69 | unsigned int Ctrl; |
| sam_grove | 5:3f93dd1d4cb3 | 70 | }; |
| sam_grove | 5:3f93dd1d4cb3 | 71 | typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; |
| sam_grove | 5:3f93dd1d4cb3 | 72 | |
| sam_grove | 5:3f93dd1d4cb3 | 73 | PACKED struct TX_STAT_TypeDef { /* TX Status struct */ |
| sam_grove | 5:3f93dd1d4cb3 | 74 | unsigned int Info; |
| sam_grove | 5:3f93dd1d4cb3 | 75 | }; |
| sam_grove | 5:3f93dd1d4cb3 | 76 | typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; |
| sam_grove | 5:3f93dd1d4cb3 | 77 | |
| sam_grove | 5:3f93dd1d4cb3 | 78 | /* MAC Configuration Register 1 */ |
| sam_grove | 5:3f93dd1d4cb3 | 79 | #define MAC1_REC_EN 0x00000001 /* Receive Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 80 | #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ |
| sam_grove | 5:3f93dd1d4cb3 | 81 | #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ |
| sam_grove | 5:3f93dd1d4cb3 | 82 | #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ |
| sam_grove | 5:3f93dd1d4cb3 | 83 | #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ |
| sam_grove | 5:3f93dd1d4cb3 | 84 | #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ |
| sam_grove | 5:3f93dd1d4cb3 | 85 | #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ |
| sam_grove | 5:3f93dd1d4cb3 | 86 | #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ |
| sam_grove | 5:3f93dd1d4cb3 | 87 | #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ |
| sam_grove | 5:3f93dd1d4cb3 | 88 | #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ |
| sam_grove | 5:3f93dd1d4cb3 | 89 | #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ |
| sam_grove | 5:3f93dd1d4cb3 | 90 | |
| sam_grove | 5:3f93dd1d4cb3 | 91 | /* MAC Configuration Register 2 */ |
| sam_grove | 5:3f93dd1d4cb3 | 92 | #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ |
| sam_grove | 5:3f93dd1d4cb3 | 93 | #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ |
| sam_grove | 5:3f93dd1d4cb3 | 94 | #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 95 | #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ |
| sam_grove | 5:3f93dd1d4cb3 | 96 | #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 97 | #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ |
| sam_grove | 5:3f93dd1d4cb3 | 98 | #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 99 | #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 100 | #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ |
| sam_grove | 5:3f93dd1d4cb3 | 101 | #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ |
| sam_grove | 5:3f93dd1d4cb3 | 102 | #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ |
| sam_grove | 5:3f93dd1d4cb3 | 103 | #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ |
| sam_grove | 5:3f93dd1d4cb3 | 104 | #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ |
| sam_grove | 5:3f93dd1d4cb3 | 105 | |
| sam_grove | 5:3f93dd1d4cb3 | 106 | /* Back-to-Back Inter-Packet-Gap Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 107 | #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ |
| sam_grove | 5:3f93dd1d4cb3 | 108 | #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ |
| sam_grove | 5:3f93dd1d4cb3 | 109 | |
| sam_grove | 5:3f93dd1d4cb3 | 110 | /* Non Back-to-Back Inter-Packet-Gap Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 111 | #define IPGR_DEF 0x00000012 /* Recommended value */ |
| sam_grove | 5:3f93dd1d4cb3 | 112 | |
| sam_grove | 5:3f93dd1d4cb3 | 113 | /* Collision Window/Retry Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 114 | #define CLRT_DEF 0x0000370F /* Default value */ |
| sam_grove | 5:3f93dd1d4cb3 | 115 | |
| sam_grove | 5:3f93dd1d4cb3 | 116 | /* PHY Support Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 117 | #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ |
| sam_grove | 5:3f93dd1d4cb3 | 118 | //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ |
| sam_grove | 5:3f93dd1d4cb3 | 119 | #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ |
| sam_grove | 5:3f93dd1d4cb3 | 120 | |
| sam_grove | 5:3f93dd1d4cb3 | 121 | /* Test Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 122 | #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ |
| sam_grove | 5:3f93dd1d4cb3 | 123 | #define TEST_TST_PAUSE 0x00000002 /* Test Pause */ |
| sam_grove | 5:3f93dd1d4cb3 | 124 | #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ |
| sam_grove | 5:3f93dd1d4cb3 | 125 | |
| sam_grove | 5:3f93dd1d4cb3 | 126 | /* MII Management Configuration Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 127 | #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ |
| sam_grove | 5:3f93dd1d4cb3 | 128 | #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ |
| sam_grove | 5:3f93dd1d4cb3 | 129 | #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ |
| sam_grove | 5:3f93dd1d4cb3 | 130 | #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ |
| sam_grove | 5:3f93dd1d4cb3 | 131 | |
| sam_grove | 5:3f93dd1d4cb3 | 132 | /* MII Management Command Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 133 | #define MCMD_READ 0x00000001 /* MII Read */ |
| sam_grove | 5:3f93dd1d4cb3 | 134 | #define MCMD_SCAN 0x00000002 /* MII Scan continuously */ |
| sam_grove | 5:3f93dd1d4cb3 | 135 | |
| sam_grove | 5:3f93dd1d4cb3 | 136 | #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ |
| sam_grove | 5:3f93dd1d4cb3 | 137 | #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ |
| sam_grove | 5:3f93dd1d4cb3 | 138 | |
| sam_grove | 5:3f93dd1d4cb3 | 139 | /* MII Management Address Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 140 | #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ |
| sam_grove | 5:3f93dd1d4cb3 | 141 | #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ |
| sam_grove | 5:3f93dd1d4cb3 | 142 | |
| sam_grove | 5:3f93dd1d4cb3 | 143 | /* MII Management Indicators Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 144 | #define MIND_BUSY 0x00000001 /* MII is Busy */ |
| sam_grove | 5:3f93dd1d4cb3 | 145 | #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ |
| sam_grove | 5:3f93dd1d4cb3 | 146 | #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ |
| sam_grove | 5:3f93dd1d4cb3 | 147 | #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ |
| sam_grove | 5:3f93dd1d4cb3 | 148 | |
| sam_grove | 5:3f93dd1d4cb3 | 149 | /* Command Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 150 | #define CR_RX_EN 0x00000001 /* Enable Receive */ |
| sam_grove | 5:3f93dd1d4cb3 | 151 | #define CR_TX_EN 0x00000002 /* Enable Transmit */ |
| sam_grove | 5:3f93dd1d4cb3 | 152 | #define CR_REG_RES 0x00000008 /* Reset Host Registers */ |
| sam_grove | 5:3f93dd1d4cb3 | 153 | #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ |
| sam_grove | 5:3f93dd1d4cb3 | 154 | #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ |
| sam_grove | 5:3f93dd1d4cb3 | 155 | #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ |
| sam_grove | 5:3f93dd1d4cb3 | 156 | #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ |
| sam_grove | 5:3f93dd1d4cb3 | 157 | #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ |
| sam_grove | 5:3f93dd1d4cb3 | 158 | #define CR_RMII 0x00000200 /* Reduced MII Interface */ |
| sam_grove | 5:3f93dd1d4cb3 | 159 | #define CR_FULL_DUP 0x00000400 /* Full Duplex */ |
| sam_grove | 5:3f93dd1d4cb3 | 160 | |
| sam_grove | 5:3f93dd1d4cb3 | 161 | /* Status Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 162 | #define SR_RX_EN 0x00000001 /* Enable Receive */ |
| sam_grove | 5:3f93dd1d4cb3 | 163 | #define SR_TX_EN 0x00000002 /* Enable Transmit */ |
| sam_grove | 5:3f93dd1d4cb3 | 164 | |
| sam_grove | 5:3f93dd1d4cb3 | 165 | /* Transmit Status Vector 0 Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 166 | #define TSV0_CRC_ERR 0x00000001 /* CRC error */ |
| sam_grove | 5:3f93dd1d4cb3 | 167 | #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ |
| sam_grove | 5:3f93dd1d4cb3 | 168 | #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ |
| sam_grove | 5:3f93dd1d4cb3 | 169 | #define TSV0_DONE 0x00000008 /* Tramsmission Completed */ |
| sam_grove | 5:3f93dd1d4cb3 | 170 | #define TSV0_MCAST 0x00000010 /* Multicast Destination */ |
| sam_grove | 5:3f93dd1d4cb3 | 171 | #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ |
| sam_grove | 5:3f93dd1d4cb3 | 172 | #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ |
| sam_grove | 5:3f93dd1d4cb3 | 173 | #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ |
| sam_grove | 5:3f93dd1d4cb3 | 174 | #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ |
| sam_grove | 5:3f93dd1d4cb3 | 175 | #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ |
| sam_grove | 5:3f93dd1d4cb3 | 176 | #define TSV0_GIANT 0x00000400 /* Giant Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 177 | #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ |
| sam_grove | 5:3f93dd1d4cb3 | 178 | #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ |
| sam_grove | 5:3f93dd1d4cb3 | 179 | #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 180 | #define TSV0_PAUSE 0x20000000 /* Pause Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 181 | #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ |
| sam_grove | 5:3f93dd1d4cb3 | 182 | #define TSV0_VLAN 0x80000000 /* VLAN Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 183 | |
| sam_grove | 5:3f93dd1d4cb3 | 184 | /* Transmit Status Vector 1 Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 185 | #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ |
| sam_grove | 5:3f93dd1d4cb3 | 186 | #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ |
| sam_grove | 5:3f93dd1d4cb3 | 187 | |
| sam_grove | 5:3f93dd1d4cb3 | 188 | /* Receive Status Vector Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 189 | #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ |
| sam_grove | 5:3f93dd1d4cb3 | 190 | #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ |
| sam_grove | 5:3f93dd1d4cb3 | 191 | #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ |
| sam_grove | 5:3f93dd1d4cb3 | 192 | #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ |
| sam_grove | 5:3f93dd1d4cb3 | 193 | #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ |
| sam_grove | 5:3f93dd1d4cb3 | 194 | #define RSV_CRC_ERR 0x00100000 /* CRC Error */ |
| sam_grove | 5:3f93dd1d4cb3 | 195 | #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ |
| sam_grove | 5:3f93dd1d4cb3 | 196 | #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ |
| sam_grove | 5:3f93dd1d4cb3 | 197 | #define RSV_REC_OK 0x00800000 /* Frame Received OK */ |
| sam_grove | 5:3f93dd1d4cb3 | 198 | #define RSV_MCAST 0x01000000 /* Multicast Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 199 | #define RSV_BCAST 0x02000000 /* Broadcast Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 200 | #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ |
| sam_grove | 5:3f93dd1d4cb3 | 201 | #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 202 | #define RSV_PAUSE 0x10000000 /* Pause Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 203 | #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ |
| sam_grove | 5:3f93dd1d4cb3 | 204 | #define RSV_VLAN 0x40000000 /* VLAN Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 205 | |
| sam_grove | 5:3f93dd1d4cb3 | 206 | /* Flow Control Counter Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 207 | #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ |
| sam_grove | 5:3f93dd1d4cb3 | 208 | #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ |
| sam_grove | 5:3f93dd1d4cb3 | 209 | |
| sam_grove | 5:3f93dd1d4cb3 | 210 | /* Flow Control Status Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 211 | #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ |
| sam_grove | 5:3f93dd1d4cb3 | 212 | |
| sam_grove | 5:3f93dd1d4cb3 | 213 | /* Receive Filter Control Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 214 | #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 215 | #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 216 | #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 217 | #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ |
| sam_grove | 5:3f93dd1d4cb3 | 218 | #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ |
| sam_grove | 5:3f93dd1d4cb3 | 219 | #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 220 | #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 221 | #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ |
| sam_grove | 5:3f93dd1d4cb3 | 222 | |
| sam_grove | 5:3f93dd1d4cb3 | 223 | /* Receive Filter WoL Status/Clear Registers */ |
| sam_grove | 5:3f93dd1d4cb3 | 224 | #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ |
| sam_grove | 5:3f93dd1d4cb3 | 225 | #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ |
| sam_grove | 5:3f93dd1d4cb3 | 226 | #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ |
| sam_grove | 5:3f93dd1d4cb3 | 227 | #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ |
| sam_grove | 5:3f93dd1d4cb3 | 228 | #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ |
| sam_grove | 5:3f93dd1d4cb3 | 229 | #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ |
| sam_grove | 5:3f93dd1d4cb3 | 230 | #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ |
| sam_grove | 5:3f93dd1d4cb3 | 231 | #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ |
| sam_grove | 5:3f93dd1d4cb3 | 232 | |
| sam_grove | 5:3f93dd1d4cb3 | 233 | /* Interrupt Status/Enable/Clear/Set Registers */ |
| sam_grove | 5:3f93dd1d4cb3 | 234 | #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ |
| sam_grove | 5:3f93dd1d4cb3 | 235 | #define INT_RX_ERR 0x00000002 /* Receive Error */ |
| sam_grove | 5:3f93dd1d4cb3 | 236 | #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ |
| sam_grove | 5:3f93dd1d4cb3 | 237 | #define INT_RX_DONE 0x00000008 /* Receive Done */ |
| sam_grove | 5:3f93dd1d4cb3 | 238 | #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ |
| sam_grove | 5:3f93dd1d4cb3 | 239 | #define INT_TX_ERR 0x00000020 /* Transmit Error */ |
| sam_grove | 5:3f93dd1d4cb3 | 240 | #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ |
| sam_grove | 5:3f93dd1d4cb3 | 241 | #define INT_TX_DONE 0x00000080 /* Transmit Done */ |
| sam_grove | 5:3f93dd1d4cb3 | 242 | #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ |
| sam_grove | 5:3f93dd1d4cb3 | 243 | #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ |
| sam_grove | 5:3f93dd1d4cb3 | 244 | |
| sam_grove | 5:3f93dd1d4cb3 | 245 | /* Power Down Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 246 | #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ |
| sam_grove | 5:3f93dd1d4cb3 | 247 | |
| sam_grove | 5:3f93dd1d4cb3 | 248 | /* RX Descriptor Control Word */ |
| sam_grove | 5:3f93dd1d4cb3 | 249 | #define RCTRL_SIZE 0x000007FF /* Buffer size mask */ |
| sam_grove | 5:3f93dd1d4cb3 | 250 | #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ |
| sam_grove | 5:3f93dd1d4cb3 | 251 | |
| sam_grove | 5:3f93dd1d4cb3 | 252 | /* RX Status Hash CRC Word */ |
| sam_grove | 5:3f93dd1d4cb3 | 253 | #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ |
| sam_grove | 5:3f93dd1d4cb3 | 254 | #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ |
| sam_grove | 5:3f93dd1d4cb3 | 255 | |
| sam_grove | 5:3f93dd1d4cb3 | 256 | /* RX Status Information Word */ |
| sam_grove | 5:3f93dd1d4cb3 | 257 | #define RINFO_SIZE 0x000007FF /* Data size in bytes */ |
| sam_grove | 5:3f93dd1d4cb3 | 258 | #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 259 | #define RINFO_VLAN 0x00080000 /* VLAN Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 260 | #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ |
| sam_grove | 5:3f93dd1d4cb3 | 261 | #define RINFO_MCAST 0x00200000 /* Multicast Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 262 | #define RINFO_BCAST 0x00400000 /* Broadcast Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 263 | #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 264 | #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ |
| sam_grove | 5:3f93dd1d4cb3 | 265 | #define RINFO_LEN_ERR 0x02000000 /* Length Error */ |
| sam_grove | 5:3f93dd1d4cb3 | 266 | #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ |
| sam_grove | 5:3f93dd1d4cb3 | 267 | #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ |
| sam_grove | 5:3f93dd1d4cb3 | 268 | #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ |
| sam_grove | 5:3f93dd1d4cb3 | 269 | #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ |
| sam_grove | 5:3f93dd1d4cb3 | 270 | #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 271 | #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
| sam_grove | 5:3f93dd1d4cb3 | 272 | |
| sam_grove | 5:3f93dd1d4cb3 | 273 | //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) |
| sam_grove | 5:3f93dd1d4cb3 | 274 | #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ |
| sam_grove | 5:3f93dd1d4cb3 | 275 | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) |
| sam_grove | 5:3f93dd1d4cb3 | 276 | |
| sam_grove | 5:3f93dd1d4cb3 | 277 | |
| sam_grove | 5:3f93dd1d4cb3 | 278 | /* TX Descriptor Control Word */ |
| sam_grove | 5:3f93dd1d4cb3 | 279 | #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ |
| sam_grove | 5:3f93dd1d4cb3 | 280 | #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ |
| sam_grove | 5:3f93dd1d4cb3 | 281 | #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 282 | #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ |
| sam_grove | 5:3f93dd1d4cb3 | 283 | #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 284 | #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ |
| sam_grove | 5:3f93dd1d4cb3 | 285 | #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ |
| sam_grove | 5:3f93dd1d4cb3 | 286 | |
| sam_grove | 5:3f93dd1d4cb3 | 287 | /* TX Status Information Word */ |
| sam_grove | 5:3f93dd1d4cb3 | 288 | #define TINFO_COL_CNT 0x01E00000 /* Collision Count */ |
| sam_grove | 5:3f93dd1d4cb3 | 289 | #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ |
| sam_grove | 5:3f93dd1d4cb3 | 290 | #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ |
| sam_grove | 5:3f93dd1d4cb3 | 291 | #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ |
| sam_grove | 5:3f93dd1d4cb3 | 292 | #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ |
| sam_grove | 5:3f93dd1d4cb3 | 293 | #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ |
| sam_grove | 5:3f93dd1d4cb3 | 294 | #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ |
| sam_grove | 5:3f93dd1d4cb3 | 295 | #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
| sam_grove | 5:3f93dd1d4cb3 | 296 | |
| sam_grove | 5:3f93dd1d4cb3 | 297 | /* ENET Device Revision ID */ |
| sam_grove | 5:3f93dd1d4cb3 | 298 | #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ |
| sam_grove | 5:3f93dd1d4cb3 | 299 | |
| sam_grove | 5:3f93dd1d4cb3 | 300 | /* DP83848C PHY Registers */ |
| sam_grove | 5:3f93dd1d4cb3 | 301 | #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 302 | #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 303 | #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ |
| sam_grove | 5:3f93dd1d4cb3 | 304 | #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ |
| sam_grove | 5:3f93dd1d4cb3 | 305 | #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ |
| sam_grove | 5:3f93dd1d4cb3 | 306 | #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ |
| sam_grove | 5:3f93dd1d4cb3 | 307 | #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 308 | #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ |
| sam_grove | 5:3f93dd1d4cb3 | 309 | |
| sam_grove | 5:3f93dd1d4cb3 | 310 | /* PHY Extended Registers */ |
| sam_grove | 5:3f93dd1d4cb3 | 311 | #define PHY_REG_STS 0x10 /* Status Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 312 | #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 313 | #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 314 | #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ |
| sam_grove | 5:3f93dd1d4cb3 | 315 | #define PHY_REG_RECR 0x15 /* Receive Error Counter */ |
| sam_grove | 5:3f93dd1d4cb3 | 316 | #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ |
| sam_grove | 5:3f93dd1d4cb3 | 317 | #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 318 | #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 319 | #define PHY_REG_PHYCR 0x19 /* PHY Control Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 320 | #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 321 | #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ |
| sam_grove | 5:3f93dd1d4cb3 | 322 | #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 323 | |
| sam_grove | 5:3f93dd1d4cb3 | 324 | #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ |
| sam_grove | 5:3f93dd1d4cb3 | 325 | |
| sam_grove | 5:3f93dd1d4cb3 | 326 | #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ |
| sam_grove | 5:3f93dd1d4cb3 | 327 | #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ |
| sam_grove | 5:3f93dd1d4cb3 | 328 | #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ |
| sam_grove | 5:3f93dd1d4cb3 | 329 | #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ |
| sam_grove | 5:3f93dd1d4cb3 | 330 | #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ |
| sam_grove | 5:3f93dd1d4cb3 | 331 | |
| sam_grove | 5:3f93dd1d4cb3 | 332 | #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ |
| sam_grove | 5:3f93dd1d4cb3 | 333 | #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ |
| sam_grove | 5:3f93dd1d4cb3 | 334 | |
| sam_grove | 5:3f93dd1d4cb3 | 335 | #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */ |
| sam_grove | 5:3f93dd1d4cb3 | 336 | |
| sam_grove | 5:3f93dd1d4cb3 | 337 | #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ |
| sam_grove | 5:3f93dd1d4cb3 | 338 | #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ |
| sam_grove | 5:3f93dd1d4cb3 | 339 | #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ |
| sam_grove | 5:3f93dd1d4cb3 | 340 | |
| sam_grove | 5:3f93dd1d4cb3 | 341 | #define PHY_BMCR_RESET 0x8000 /* PHY Reset */ |
| sam_grove | 5:3f93dd1d4cb3 | 342 | |
| sam_grove | 5:3f93dd1d4cb3 | 343 | #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ |
| sam_grove | 5:3f93dd1d4cb3 | 344 | |
| sam_grove | 5:3f93dd1d4cb3 | 345 | #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ |
| sam_grove | 5:3f93dd1d4cb3 | 346 | #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */ |
| sam_grove | 5:3f93dd1d4cb3 | 347 | |
| sam_grove | 5:3f93dd1d4cb3 | 348 | |
| sam_grove | 5:3f93dd1d4cb3 | 349 | static int phy_read(unsigned int PhyReg); |
| sam_grove | 5:3f93dd1d4cb3 | 350 | static int phy_write(unsigned int PhyReg, unsigned short Data); |
| sam_grove | 5:3f93dd1d4cb3 | 351 | |
| sam_grove | 5:3f93dd1d4cb3 | 352 | static void txdscr_init(void); |
| sam_grove | 5:3f93dd1d4cb3 | 353 | static void rxdscr_init(void); |
| sam_grove | 5:3f93dd1d4cb3 | 354 | |
| sam_grove | 5:3f93dd1d4cb3 | 355 | #if defined (__ICCARM__) |
| sam_grove | 5:3f93dd1d4cb3 | 356 | # define AHBSRAM1 |
| sam_grove | 5:3f93dd1d4cb3 | 357 | #elif defined(TOOLCHAIN_GCC_CR) |
| sam_grove | 5:3f93dd1d4cb3 | 358 | # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32"))) |
| sam_grove | 5:3f93dd1d4cb3 | 359 | #else |
| sam_grove | 5:3f93dd1d4cb3 | 360 | # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned)) |
| sam_grove | 5:3f93dd1d4cb3 | 361 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 362 | |
| sam_grove | 5:3f93dd1d4cb3 | 363 | AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE]; |
| sam_grove | 5:3f93dd1d4cb3 | 364 | AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE]; |
| sam_grove | 5:3f93dd1d4cb3 | 365 | AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG]; |
| sam_grove | 5:3f93dd1d4cb3 | 366 | AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG]; |
| sam_grove | 5:3f93dd1d4cb3 | 367 | AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG]; |
| sam_grove | 5:3f93dd1d4cb3 | 368 | AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG]; |
| sam_grove | 5:3f93dd1d4cb3 | 369 | |
| sam_grove | 5:3f93dd1d4cb3 | 370 | |
| sam_grove | 5:3f93dd1d4cb3 | 371 | #if NEW_LOGIC |
| sam_grove | 5:3f93dd1d4cb3 | 372 | static int rx_consume_offset = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 373 | static int tx_produce_offset = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 374 | #else |
| sam_grove | 5:3f93dd1d4cb3 | 375 | static int send_doff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 376 | static int send_idx = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 377 | static int send_size = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 378 | |
| sam_grove | 5:3f93dd1d4cb3 | 379 | static int receive_soff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 380 | static int receive_idx = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 381 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 382 | |
| sam_grove | 5:3f93dd1d4cb3 | 383 | static uint32_t phy_id = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 384 | |
| sam_grove | 5:3f93dd1d4cb3 | 385 | static inline int rinc(int idx, int mod) { |
| sam_grove | 5:3f93dd1d4cb3 | 386 | ++idx; |
| sam_grove | 5:3f93dd1d4cb3 | 387 | idx %= mod; |
| sam_grove | 5:3f93dd1d4cb3 | 388 | return idx; |
| sam_grove | 5:3f93dd1d4cb3 | 389 | } |
| sam_grove | 5:3f93dd1d4cb3 | 390 | |
| sam_grove | 5:3f93dd1d4cb3 | 391 | //extern unsigned int SystemFrequency; |
| sam_grove | 5:3f93dd1d4cb3 | 392 | static inline unsigned int clockselect() { |
| sam_grove | 5:3f93dd1d4cb3 | 393 | if(SystemCoreClock < 10000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 394 | return 1; |
| sam_grove | 5:3f93dd1d4cb3 | 395 | } else if(SystemCoreClock < 15000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 396 | return 2; |
| sam_grove | 5:3f93dd1d4cb3 | 397 | } else if(SystemCoreClock < 20000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 398 | return 3; |
| sam_grove | 5:3f93dd1d4cb3 | 399 | } else if(SystemCoreClock < 25000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 400 | return 4; |
| sam_grove | 5:3f93dd1d4cb3 | 401 | } else if(SystemCoreClock < 35000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 402 | return 5; |
| sam_grove | 5:3f93dd1d4cb3 | 403 | } else if(SystemCoreClock < 50000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 404 | return 6; |
| sam_grove | 5:3f93dd1d4cb3 | 405 | } else if(SystemCoreClock < 70000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 406 | return 7; |
| sam_grove | 5:3f93dd1d4cb3 | 407 | } else if(SystemCoreClock < 80000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 408 | return 8; |
| sam_grove | 5:3f93dd1d4cb3 | 409 | } else if(SystemCoreClock < 90000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 410 | return 9; |
| sam_grove | 5:3f93dd1d4cb3 | 411 | } else if(SystemCoreClock < 100000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 412 | return 10; |
| sam_grove | 5:3f93dd1d4cb3 | 413 | } else if(SystemCoreClock < 120000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 414 | return 11; |
| sam_grove | 5:3f93dd1d4cb3 | 415 | } else if(SystemCoreClock < 130000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 416 | return 12; |
| sam_grove | 5:3f93dd1d4cb3 | 417 | } else if(SystemCoreClock < 140000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 418 | return 13; |
| sam_grove | 5:3f93dd1d4cb3 | 419 | } else if(SystemCoreClock < 150000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 420 | return 15; |
| sam_grove | 5:3f93dd1d4cb3 | 421 | } else if(SystemCoreClock < 160000000) { |
| sam_grove | 5:3f93dd1d4cb3 | 422 | return 16; |
| sam_grove | 5:3f93dd1d4cb3 | 423 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 424 | return 0; |
| sam_grove | 5:3f93dd1d4cb3 | 425 | } |
| sam_grove | 5:3f93dd1d4cb3 | 426 | } |
| sam_grove | 5:3f93dd1d4cb3 | 427 | |
| sam_grove | 5:3f93dd1d4cb3 | 428 | #ifndef min |
| sam_grove | 5:3f93dd1d4cb3 | 429 | #define min(x, y) (((x)<(y))?(x):(y)) |
| sam_grove | 5:3f93dd1d4cb3 | 430 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 431 | |
| sam_grove | 5:3f93dd1d4cb3 | 432 | /*---------------------------------------------------------------------------- |
| sam_grove | 5:3f93dd1d4cb3 | 433 | Ethernet Device initialize |
| sam_grove | 5:3f93dd1d4cb3 | 434 | *----------------------------------------------------------------------------*/ |
| sam_grove | 5:3f93dd1d4cb3 | 435 | int ethernet_init() { |
| sam_grove | 5:3f93dd1d4cb3 | 436 | int regv, tout; |
| sam_grove | 5:3f93dd1d4cb3 | 437 | char mac[ETHERNET_ADDR_SIZE]; |
| sam_grove | 5:3f93dd1d4cb3 | 438 | unsigned int clock = clockselect(); |
| sam_grove | 5:3f93dd1d4cb3 | 439 | |
| sam_grove | 5:3f93dd1d4cb3 | 440 | LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ |
| sam_grove | 5:3f93dd1d4cb3 | 441 | |
| sam_grove | 5:3f93dd1d4cb3 | 442 | LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */ |
| sam_grove | 5:3f93dd1d4cb3 | 443 | LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; |
| sam_grove | 5:3f93dd1d4cb3 | 444 | |
| sam_grove | 5:3f93dd1d4cb3 | 445 | /* Reset all EMAC internal modules. */ |
| sam_grove | 5:3f93dd1d4cb3 | 446 | LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | |
| sam_grove | 5:3f93dd1d4cb3 | 447 | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; |
| sam_grove | 5:3f93dd1d4cb3 | 448 | LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; |
| sam_grove | 5:3f93dd1d4cb3 | 449 | |
| sam_grove | 5:3f93dd1d4cb3 | 450 | for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */ |
| sam_grove | 5:3f93dd1d4cb3 | 451 | |
| sam_grove | 5:3f93dd1d4cb3 | 452 | LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */ |
| sam_grove | 5:3f93dd1d4cb3 | 453 | LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; |
| sam_grove | 5:3f93dd1d4cb3 | 454 | LPC_EMAC->MAXF = ETH_MAX_FLEN; |
| sam_grove | 5:3f93dd1d4cb3 | 455 | LPC_EMAC->CLRT = CLRT_DEF; |
| sam_grove | 5:3f93dd1d4cb3 | 456 | LPC_EMAC->IPGR = IPGR_DEF; |
| sam_grove | 5:3f93dd1d4cb3 | 457 | |
| sam_grove | 5:3f93dd1d4cb3 | 458 | LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */ |
| sam_grove | 5:3f93dd1d4cb3 | 459 | |
| sam_grove | 5:3f93dd1d4cb3 | 460 | LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ |
| sam_grove | 5:3f93dd1d4cb3 | 461 | LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ |
| sam_grove | 5:3f93dd1d4cb3 | 462 | |
| sam_grove | 5:3f93dd1d4cb3 | 463 | for(tout = 100; tout; tout--) __NOP(); /* A short delay */ |
| sam_grove | 5:3f93dd1d4cb3 | 464 | |
| sam_grove | 5:3f93dd1d4cb3 | 465 | LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; |
| sam_grove | 5:3f93dd1d4cb3 | 466 | LPC_EMAC->MCMD = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 467 | |
| sam_grove | 5:3f93dd1d4cb3 | 468 | LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ |
| sam_grove | 5:3f93dd1d4cb3 | 469 | |
| sam_grove | 5:3f93dd1d4cb3 | 470 | for (tout = 100; tout; tout--) __NOP(); /* A short delay */ |
| sam_grove | 5:3f93dd1d4cb3 | 471 | |
| sam_grove | 5:3f93dd1d4cb3 | 472 | LPC_EMAC->SUPP = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 473 | |
| sam_grove | 5:3f93dd1d4cb3 | 474 | phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ |
| sam_grove | 5:3f93dd1d4cb3 | 475 | for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ |
| sam_grove | 5:3f93dd1d4cb3 | 476 | regv = phy_read(PHY_REG_BMCR); |
| sam_grove | 5:3f93dd1d4cb3 | 477 | if(regv < 0 || tout == 0) { |
| sam_grove | 5:3f93dd1d4cb3 | 478 | return -1; /* Error */ |
| sam_grove | 5:3f93dd1d4cb3 | 479 | } |
| sam_grove | 5:3f93dd1d4cb3 | 480 | if(!(regv & PHY_BMCR_RESET)) { |
| sam_grove | 5:3f93dd1d4cb3 | 481 | break; /* Reset complete. */ |
| sam_grove | 5:3f93dd1d4cb3 | 482 | } |
| sam_grove | 5:3f93dd1d4cb3 | 483 | } |
| sam_grove | 5:3f93dd1d4cb3 | 484 | |
| sam_grove | 5:3f93dd1d4cb3 | 485 | phy_id = (phy_read(PHY_REG_IDR1) << 16); |
| sam_grove | 5:3f93dd1d4cb3 | 486 | phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); |
| sam_grove | 5:3f93dd1d4cb3 | 487 | |
| sam_grove | 5:3f93dd1d4cb3 | 488 | if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) { |
| sam_grove | 5:3f93dd1d4cb3 | 489 | error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id); |
| sam_grove | 5:3f93dd1d4cb3 | 490 | } |
| sam_grove | 5:3f93dd1d4cb3 | 491 | |
| sam_grove | 5:3f93dd1d4cb3 | 492 | ethernet_set_link(-1, 0); |
| sam_grove | 5:3f93dd1d4cb3 | 493 | |
| sam_grove | 5:3f93dd1d4cb3 | 494 | /* Set the Ethernet MAC Address registers */ |
| sam_grove | 5:3f93dd1d4cb3 | 495 | ethernet_address(mac); |
| sam_grove | 5:3f93dd1d4cb3 | 496 | LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4]; |
| sam_grove | 5:3f93dd1d4cb3 | 497 | LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2]; |
| sam_grove | 5:3f93dd1d4cb3 | 498 | LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0]; |
| sam_grove | 5:3f93dd1d4cb3 | 499 | |
| sam_grove | 5:3f93dd1d4cb3 | 500 | txdscr_init(); /* initialize DMA TX Descriptor */ |
| sam_grove | 5:3f93dd1d4cb3 | 501 | rxdscr_init(); /* initialize DMA RX Descriptor */ |
| sam_grove | 5:3f93dd1d4cb3 | 502 | |
| sam_grove | 5:3f93dd1d4cb3 | 503 | LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; |
| sam_grove | 5:3f93dd1d4cb3 | 504 | /* Receive Broadcast, Perfect Match Packets */ |
| sam_grove | 5:3f93dd1d4cb3 | 505 | |
| sam_grove | 5:3f93dd1d4cb3 | 506 | LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ |
| sam_grove | 5:3f93dd1d4cb3 | 507 | LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ |
| sam_grove | 5:3f93dd1d4cb3 | 508 | |
| sam_grove | 5:3f93dd1d4cb3 | 509 | |
| sam_grove | 5:3f93dd1d4cb3 | 510 | LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ |
| sam_grove | 5:3f93dd1d4cb3 | 511 | LPC_EMAC->MAC1 |= MAC1_REC_EN; |
| sam_grove | 5:3f93dd1d4cb3 | 512 | |
| sam_grove | 5:3f93dd1d4cb3 | 513 | #if NEW_LOGIC |
| sam_grove | 5:3f93dd1d4cb3 | 514 | rx_consume_offset = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 515 | tx_produce_offset = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 516 | #else |
| sam_grove | 5:3f93dd1d4cb3 | 517 | send_doff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 518 | send_idx = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 519 | send_size = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 520 | |
| sam_grove | 5:3f93dd1d4cb3 | 521 | receive_soff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 522 | receive_idx = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 523 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 524 | |
| sam_grove | 5:3f93dd1d4cb3 | 525 | return 0; |
| sam_grove | 5:3f93dd1d4cb3 | 526 | } |
| sam_grove | 5:3f93dd1d4cb3 | 527 | |
| sam_grove | 5:3f93dd1d4cb3 | 528 | /*---------------------------------------------------------------------------- |
| sam_grove | 5:3f93dd1d4cb3 | 529 | Ethernet Device Uninitialize |
| sam_grove | 5:3f93dd1d4cb3 | 530 | *----------------------------------------------------------------------------*/ |
| sam_grove | 5:3f93dd1d4cb3 | 531 | void ethernet_free() { |
| sam_grove | 5:3f93dd1d4cb3 | 532 | LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE); |
| sam_grove | 5:3f93dd1d4cb3 | 533 | LPC_EMAC->IntClear = 0xFFFF; |
| sam_grove | 5:3f93dd1d4cb3 | 534 | |
| sam_grove | 5:3f93dd1d4cb3 | 535 | LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */ |
| sam_grove | 5:3f93dd1d4cb3 | 536 | |
| sam_grove | 5:3f93dd1d4cb3 | 537 | LPC_PINCON->PINSEL2 &= ~0x50150105; /* Disable P1 ethernet pins. */ |
| sam_grove | 5:3f93dd1d4cb3 | 538 | LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000; |
| sam_grove | 5:3f93dd1d4cb3 | 539 | } |
| sam_grove | 5:3f93dd1d4cb3 | 540 | |
| sam_grove | 5:3f93dd1d4cb3 | 541 | // if(TxProduceIndex == TxConsumeIndex) buffer array is empty |
| sam_grove | 5:3f93dd1d4cb3 | 542 | // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill |
| sam_grove | 5:3f93dd1d4cb3 | 543 | // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment |
| sam_grove | 5:3f93dd1d4cb3 | 544 | // TxConsumeIndex - The buffer that will/is beign sent by hardware |
| sam_grove | 5:3f93dd1d4cb3 | 545 | |
| sam_grove | 5:3f93dd1d4cb3 | 546 | int ethernet_write(const char *data, int slen) { |
| sam_grove | 5:3f93dd1d4cb3 | 547 | |
| sam_grove | 5:3f93dd1d4cb3 | 548 | #if NEW_LOGIC |
| sam_grove | 5:3f93dd1d4cb3 | 549 | |
| sam_grove | 5:3f93dd1d4cb3 | 550 | if(tx_produce_offset < 0) { // mark as active if not already |
| sam_grove | 5:3f93dd1d4cb3 | 551 | tx_produce_offset = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 552 | } |
| sam_grove | 5:3f93dd1d4cb3 | 553 | |
| sam_grove | 5:3f93dd1d4cb3 | 554 | int index = LPC_EMAC->TxProduceIndex; |
| sam_grove | 5:3f93dd1d4cb3 | 555 | |
| sam_grove | 5:3f93dd1d4cb3 | 556 | int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum |
| sam_grove | 5:3f93dd1d4cb3 | 557 | int requested = slen; |
| sam_grove | 5:3f93dd1d4cb3 | 558 | int ncopy = min(remaining, requested); |
| sam_grove | 5:3f93dd1d4cb3 | 559 | |
| sam_grove | 5:3f93dd1d4cb3 | 560 | void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset); |
| sam_grove | 5:3f93dd1d4cb3 | 561 | void *psrc = (void *)(data); |
| sam_grove | 5:3f93dd1d4cb3 | 562 | |
| sam_grove | 5:3f93dd1d4cb3 | 563 | if(ncopy > 0 ){ |
| sam_grove | 5:3f93dd1d4cb3 | 564 | if(data != NULL) { |
| sam_grove | 5:3f93dd1d4cb3 | 565 | memcpy(pdst, psrc, ncopy); |
| sam_grove | 5:3f93dd1d4cb3 | 566 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 567 | memset(pdst, 0, ncopy); |
| sam_grove | 5:3f93dd1d4cb3 | 568 | } |
| sam_grove | 5:3f93dd1d4cb3 | 569 | } |
| sam_grove | 5:3f93dd1d4cb3 | 570 | |
| sam_grove | 5:3f93dd1d4cb3 | 571 | tx_produce_offset += ncopy; |
| sam_grove | 5:3f93dd1d4cb3 | 572 | |
| sam_grove | 5:3f93dd1d4cb3 | 573 | return ncopy; |
| sam_grove | 5:3f93dd1d4cb3 | 574 | |
| sam_grove | 5:3f93dd1d4cb3 | 575 | #else |
| sam_grove | 5:3f93dd1d4cb3 | 576 | void *pdst, *psrc; |
| sam_grove | 5:3f93dd1d4cb3 | 577 | const int dlen = ETH_FRAG_SIZE; |
| sam_grove | 5:3f93dd1d4cb3 | 578 | int copy = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 579 | int soff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 580 | |
| sam_grove | 5:3f93dd1d4cb3 | 581 | if(send_idx == -1) { |
| sam_grove | 5:3f93dd1d4cb3 | 582 | send_idx = LPC_EMAC->TxProduceIndex; |
| sam_grove | 5:3f93dd1d4cb3 | 583 | } |
| sam_grove | 5:3f93dd1d4cb3 | 584 | |
| sam_grove | 5:3f93dd1d4cb3 | 585 | if(slen + send_doff > ethernet_MTU_SIZE) { |
| sam_grove | 5:3f93dd1d4cb3 | 586 | return -1; |
| sam_grove | 5:3f93dd1d4cb3 | 587 | } |
| sam_grove | 5:3f93dd1d4cb3 | 588 | |
| sam_grove | 5:3f93dd1d4cb3 | 589 | do { |
| sam_grove | 5:3f93dd1d4cb3 | 590 | copy = min(slen - soff, dlen - send_doff); |
| sam_grove | 5:3f93dd1d4cb3 | 591 | pdst = (void *)(txdesc[send_idx].Packet + send_doff); |
| sam_grove | 5:3f93dd1d4cb3 | 592 | psrc = (void *)(data + soff); |
| sam_grove | 5:3f93dd1d4cb3 | 593 | if(send_doff + copy > ETH_FRAG_SIZE) { |
| sam_grove | 5:3f93dd1d4cb3 | 594 | txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT); |
| sam_grove | 5:3f93dd1d4cb3 | 595 | send_idx = rinc(send_idx, NUM_TX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 596 | send_doff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 597 | } |
| sam_grove | 5:3f93dd1d4cb3 | 598 | |
| sam_grove | 5:3f93dd1d4cb3 | 599 | if(data != NULL) { |
| sam_grove | 5:3f93dd1d4cb3 | 600 | memcpy(pdst, psrc, copy); |
| sam_grove | 5:3f93dd1d4cb3 | 601 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 602 | memset(pdst, 0, copy); |
| sam_grove | 5:3f93dd1d4cb3 | 603 | } |
| sam_grove | 5:3f93dd1d4cb3 | 604 | |
| sam_grove | 5:3f93dd1d4cb3 | 605 | soff += copy; |
| sam_grove | 5:3f93dd1d4cb3 | 606 | send_doff += copy; |
| sam_grove | 5:3f93dd1d4cb3 | 607 | send_size += copy; |
| sam_grove | 5:3f93dd1d4cb3 | 608 | } while(soff != slen); |
| sam_grove | 5:3f93dd1d4cb3 | 609 | |
| sam_grove | 5:3f93dd1d4cb3 | 610 | return soff; |
| sam_grove | 5:3f93dd1d4cb3 | 611 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 612 | } |
| sam_grove | 5:3f93dd1d4cb3 | 613 | |
| sam_grove | 5:3f93dd1d4cb3 | 614 | int ethernet_send() { |
| sam_grove | 5:3f93dd1d4cb3 | 615 | |
| sam_grove | 5:3f93dd1d4cb3 | 616 | #if NEW_LOGIC |
| sam_grove | 5:3f93dd1d4cb3 | 617 | if(tx_produce_offset < 0) { // no buffer active |
| sam_grove | 5:3f93dd1d4cb3 | 618 | return -1; |
| sam_grove | 5:3f93dd1d4cb3 | 619 | } |
| sam_grove | 5:3f93dd1d4cb3 | 620 | |
| sam_grove | 5:3f93dd1d4cb3 | 621 | // ensure there is a link |
| sam_grove | 5:3f93dd1d4cb3 | 622 | if(!ethernet_link()) { |
| sam_grove | 5:3f93dd1d4cb3 | 623 | return -2; |
| sam_grove | 5:3f93dd1d4cb3 | 624 | } |
| sam_grove | 5:3f93dd1d4cb3 | 625 | |
| sam_grove | 5:3f93dd1d4cb3 | 626 | // we have been writing in to a buffer, so finalise it |
| sam_grove | 5:3f93dd1d4cb3 | 627 | int size = tx_produce_offset; |
| sam_grove | 5:3f93dd1d4cb3 | 628 | int index = LPC_EMAC->TxProduceIndex; |
| sam_grove | 5:3f93dd1d4cb3 | 629 | txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST); |
| sam_grove | 5:3f93dd1d4cb3 | 630 | |
| sam_grove | 5:3f93dd1d4cb3 | 631 | // Increment ProduceIndex to allow it to be sent |
| sam_grove | 5:3f93dd1d4cb3 | 632 | // We can only do this if the next slot is free |
| sam_grove | 5:3f93dd1d4cb3 | 633 | int next = rinc(index, NUM_TX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 634 | while(next == LPC_EMAC->TxConsumeIndex) { |
| sam_grove | 5:3f93dd1d4cb3 | 635 | for(int i=0; i<1000; i++) { __NOP(); } |
| sam_grove | 5:3f93dd1d4cb3 | 636 | } |
| sam_grove | 5:3f93dd1d4cb3 | 637 | |
| sam_grove | 5:3f93dd1d4cb3 | 638 | LPC_EMAC->TxProduceIndex = next; |
| sam_grove | 5:3f93dd1d4cb3 | 639 | tx_produce_offset = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 640 | return size; |
| sam_grove | 5:3f93dd1d4cb3 | 641 | |
| sam_grove | 5:3f93dd1d4cb3 | 642 | #else |
| sam_grove | 5:3f93dd1d4cb3 | 643 | int s = send_size; |
| sam_grove | 5:3f93dd1d4cb3 | 644 | txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST); |
| sam_grove | 5:3f93dd1d4cb3 | 645 | send_idx = rinc(send_idx, NUM_TX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 646 | LPC_EMAC->TxProduceIndex = send_idx; |
| sam_grove | 5:3f93dd1d4cb3 | 647 | send_doff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 648 | send_idx = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 649 | send_size = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 650 | return s; |
| sam_grove | 5:3f93dd1d4cb3 | 651 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 652 | } |
| sam_grove | 5:3f93dd1d4cb3 | 653 | |
| sam_grove | 5:3f93dd1d4cb3 | 654 | // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read |
| sam_grove | 5:3f93dd1d4cb3 | 655 | // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd |
| sam_grove | 5:3f93dd1d4cb3 | 656 | // |
| sam_grove | 5:3f93dd1d4cb3 | 657 | // if(RxConsumeIndex == RxProduceIndex) buffer array is empty |
| sam_grove | 5:3f93dd1d4cb3 | 658 | // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full |
| sam_grove | 5:3f93dd1d4cb3 | 659 | |
| sam_grove | 5:3f93dd1d4cb3 | 660 | // Recevies an arrived ethernet packet. |
| sam_grove | 5:3f93dd1d4cb3 | 661 | // Receiving an ethernet packet will drop the last received ethernet packet |
| sam_grove | 5:3f93dd1d4cb3 | 662 | // and make a new ethernet packet ready to read. |
| sam_grove | 5:3f93dd1d4cb3 | 663 | // Returns size of packet, else 0 if nothing to receive |
| sam_grove | 5:3f93dd1d4cb3 | 664 | |
| sam_grove | 5:3f93dd1d4cb3 | 665 | // We read from RxConsumeIndex from position rx_consume_offset |
| sam_grove | 5:3f93dd1d4cb3 | 666 | // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading |
| sam_grove | 5:3f93dd1d4cb3 | 667 | // rx_consume_offset = -1 // no frame |
| sam_grove | 5:3f93dd1d4cb3 | 668 | // rx_consume_offset = 0 // start of frame |
| sam_grove | 5:3f93dd1d4cb3 | 669 | // Assumption: A fragment should alway be a whole frame |
| sam_grove | 5:3f93dd1d4cb3 | 670 | |
| sam_grove | 5:3f93dd1d4cb3 | 671 | int ethernet_receive() { |
| sam_grove | 5:3f93dd1d4cb3 | 672 | #if NEW_LOGIC |
| sam_grove | 5:3f93dd1d4cb3 | 673 | |
| sam_grove | 5:3f93dd1d4cb3 | 674 | // if we are currently reading a valid RxConsume buffer, increment to the next one |
| sam_grove | 5:3f93dd1d4cb3 | 675 | if(rx_consume_offset >= 0) { |
| sam_grove | 5:3f93dd1d4cb3 | 676 | LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 677 | } |
| sam_grove | 5:3f93dd1d4cb3 | 678 | |
| sam_grove | 5:3f93dd1d4cb3 | 679 | // if the buffer is empty, mark it as no valid buffer |
| sam_grove | 5:3f93dd1d4cb3 | 680 | if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) { |
| sam_grove | 5:3f93dd1d4cb3 | 681 | rx_consume_offset = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 682 | return 0; |
| sam_grove | 5:3f93dd1d4cb3 | 683 | } |
| sam_grove | 5:3f93dd1d4cb3 | 684 | |
| sam_grove | 5:3f93dd1d4cb3 | 685 | uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; |
| sam_grove | 5:3f93dd1d4cb3 | 686 | rx_consume_offset = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 687 | |
| sam_grove | 5:3f93dd1d4cb3 | 688 | // check if it is not marked as last or for errors |
| sam_grove | 5:3f93dd1d4cb3 | 689 | if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) { |
| sam_grove | 5:3f93dd1d4cb3 | 690 | return -1; |
| sam_grove | 5:3f93dd1d4cb3 | 691 | } |
| sam_grove | 5:3f93dd1d4cb3 | 692 | |
| sam_grove | 5:3f93dd1d4cb3 | 693 | int size = (info & RINFO_SIZE) + 1; |
| sam_grove | 5:3f93dd1d4cb3 | 694 | return size - 4; // don't include checksum bytes |
| sam_grove | 5:3f93dd1d4cb3 | 695 | |
| sam_grove | 5:3f93dd1d4cb3 | 696 | #else |
| sam_grove | 5:3f93dd1d4cb3 | 697 | if(receive_idx == -1) { |
| sam_grove | 5:3f93dd1d4cb3 | 698 | receive_idx = LPC_EMAC->RxConsumeIndex; |
| sam_grove | 5:3f93dd1d4cb3 | 699 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 700 | while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) { |
| sam_grove | 5:3f93dd1d4cb3 | 701 | receive_idx = rinc(receive_idx, NUM_RX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 702 | } |
| sam_grove | 5:3f93dd1d4cb3 | 703 | unsigned int info = rxstat[receive_idx].Info; |
| sam_grove | 5:3f93dd1d4cb3 | 704 | int slen = (info & RINFO_SIZE) + 1; |
| sam_grove | 5:3f93dd1d4cb3 | 705 | |
| sam_grove | 5:3f93dd1d4cb3 | 706 | if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { |
| sam_grove | 5:3f93dd1d4cb3 | 707 | /* Invalid frame, ignore it and free buffer. */ |
| sam_grove | 5:3f93dd1d4cb3 | 708 | receive_idx = rinc(receive_idx, NUM_RX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 709 | } |
| sam_grove | 5:3f93dd1d4cb3 | 710 | receive_idx = rinc(receive_idx, NUM_RX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 711 | receive_soff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 712 | |
| sam_grove | 5:3f93dd1d4cb3 | 713 | LPC_EMAC->RxConsumeIndex = receive_idx; |
| sam_grove | 5:3f93dd1d4cb3 | 714 | } |
| sam_grove | 5:3f93dd1d4cb3 | 715 | |
| sam_grove | 5:3f93dd1d4cb3 | 716 | if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) { |
| sam_grove | 5:3f93dd1d4cb3 | 717 | receive_idx = -1; |
| sam_grove | 5:3f93dd1d4cb3 | 718 | return 0; |
| sam_grove | 5:3f93dd1d4cb3 | 719 | } |
| sam_grove | 5:3f93dd1d4cb3 | 720 | |
| sam_grove | 5:3f93dd1d4cb3 | 721 | return (rxstat[receive_idx].Info & RINFO_SIZE) - 3; |
| sam_grove | 5:3f93dd1d4cb3 | 722 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 723 | } |
| sam_grove | 5:3f93dd1d4cb3 | 724 | |
| sam_grove | 5:3f93dd1d4cb3 | 725 | // Read from an recevied ethernet packet. |
| sam_grove | 5:3f93dd1d4cb3 | 726 | // After receive returnd a number bigger than 0 it is |
| sam_grove | 5:3f93dd1d4cb3 | 727 | // possible to read bytes from this packet. |
| sam_grove | 5:3f93dd1d4cb3 | 728 | // Read will write up to size bytes into data. |
| sam_grove | 5:3f93dd1d4cb3 | 729 | // It is possible to use read multible times. |
| sam_grove | 5:3f93dd1d4cb3 | 730 | // Each time read will start reading after the last read byte before. |
| sam_grove | 5:3f93dd1d4cb3 | 731 | |
| sam_grove | 5:3f93dd1d4cb3 | 732 | int ethernet_read(char *data, int dlen) { |
| sam_grove | 5:3f93dd1d4cb3 | 733 | #if NEW_LOGIC |
| sam_grove | 5:3f93dd1d4cb3 | 734 | // Check we have a valid buffer to read |
| sam_grove | 5:3f93dd1d4cb3 | 735 | if(rx_consume_offset < 0) { |
| sam_grove | 5:3f93dd1d4cb3 | 736 | return 0; |
| sam_grove | 5:3f93dd1d4cb3 | 737 | } |
| sam_grove | 5:3f93dd1d4cb3 | 738 | |
| sam_grove | 5:3f93dd1d4cb3 | 739 | // Assume 1 fragment block |
| sam_grove | 5:3f93dd1d4cb3 | 740 | uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; |
| sam_grove | 5:3f93dd1d4cb3 | 741 | int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum |
| sam_grove | 5:3f93dd1d4cb3 | 742 | |
| sam_grove | 5:3f93dd1d4cb3 | 743 | int remaining = size - rx_consume_offset; |
| sam_grove | 5:3f93dd1d4cb3 | 744 | int requested = dlen; |
| sam_grove | 5:3f93dd1d4cb3 | 745 | int ncopy = min(remaining, requested); |
| sam_grove | 5:3f93dd1d4cb3 | 746 | |
| sam_grove | 5:3f93dd1d4cb3 | 747 | void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset); |
| sam_grove | 5:3f93dd1d4cb3 | 748 | void *pdst = (void *)(data); |
| sam_grove | 5:3f93dd1d4cb3 | 749 | |
| sam_grove | 5:3f93dd1d4cb3 | 750 | if(data != NULL && ncopy > 0) { |
| sam_grove | 5:3f93dd1d4cb3 | 751 | memcpy(pdst, psrc, ncopy); |
| sam_grove | 5:3f93dd1d4cb3 | 752 | } |
| sam_grove | 5:3f93dd1d4cb3 | 753 | |
| sam_grove | 5:3f93dd1d4cb3 | 754 | rx_consume_offset += ncopy; |
| sam_grove | 5:3f93dd1d4cb3 | 755 | |
| sam_grove | 5:3f93dd1d4cb3 | 756 | return ncopy; |
| sam_grove | 5:3f93dd1d4cb3 | 757 | #else |
| sam_grove | 5:3f93dd1d4cb3 | 758 | int slen; |
| sam_grove | 5:3f93dd1d4cb3 | 759 | int copy = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 760 | unsigned int more; |
| sam_grove | 5:3f93dd1d4cb3 | 761 | unsigned int info; |
| sam_grove | 5:3f93dd1d4cb3 | 762 | void *pdst, *psrc; |
| sam_grove | 5:3f93dd1d4cb3 | 763 | int doff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 764 | |
| sam_grove | 5:3f93dd1d4cb3 | 765 | if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) { |
| sam_grove | 5:3f93dd1d4cb3 | 766 | return 0; |
| sam_grove | 5:3f93dd1d4cb3 | 767 | } |
| sam_grove | 5:3f93dd1d4cb3 | 768 | |
| sam_grove | 5:3f93dd1d4cb3 | 769 | do { |
| sam_grove | 5:3f93dd1d4cb3 | 770 | info = rxstat[receive_idx].Info; |
| sam_grove | 5:3f93dd1d4cb3 | 771 | more = !(info & RINFO_LAST_FLAG); |
| sam_grove | 5:3f93dd1d4cb3 | 772 | slen = (info & RINFO_SIZE) + 1; |
| sam_grove | 5:3f93dd1d4cb3 | 773 | |
| sam_grove | 5:3f93dd1d4cb3 | 774 | if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { |
| sam_grove | 5:3f93dd1d4cb3 | 775 | /* Invalid frame, ignore it and free buffer. */ |
| sam_grove | 5:3f93dd1d4cb3 | 776 | receive_idx = rinc(receive_idx, NUM_RX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 777 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 778 | |
| sam_grove | 5:3f93dd1d4cb3 | 779 | copy = min(slen - receive_soff, dlen - doff); |
| sam_grove | 5:3f93dd1d4cb3 | 780 | psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff); |
| sam_grove | 5:3f93dd1d4cb3 | 781 | pdst = (void *)(data + doff); |
| sam_grove | 5:3f93dd1d4cb3 | 782 | |
| sam_grove | 5:3f93dd1d4cb3 | 783 | if(data != NULL) { |
| sam_grove | 5:3f93dd1d4cb3 | 784 | /* check if Buffer available */ |
| sam_grove | 5:3f93dd1d4cb3 | 785 | memcpy(pdst, psrc, copy); |
| sam_grove | 5:3f93dd1d4cb3 | 786 | } |
| sam_grove | 5:3f93dd1d4cb3 | 787 | |
| sam_grove | 5:3f93dd1d4cb3 | 788 | receive_soff += copy; |
| sam_grove | 5:3f93dd1d4cb3 | 789 | doff += copy; |
| sam_grove | 5:3f93dd1d4cb3 | 790 | |
| sam_grove | 5:3f93dd1d4cb3 | 791 | if((more && (receive_soff == slen))) { |
| sam_grove | 5:3f93dd1d4cb3 | 792 | receive_idx = rinc(receive_idx, NUM_RX_FRAG); |
| sam_grove | 5:3f93dd1d4cb3 | 793 | receive_soff = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 794 | } |
| sam_grove | 5:3f93dd1d4cb3 | 795 | } |
| sam_grove | 5:3f93dd1d4cb3 | 796 | } while(more && !(doff == dlen) && !receive_soff); |
| sam_grove | 5:3f93dd1d4cb3 | 797 | |
| sam_grove | 5:3f93dd1d4cb3 | 798 | return doff; |
| sam_grove | 5:3f93dd1d4cb3 | 799 | #endif |
| sam_grove | 5:3f93dd1d4cb3 | 800 | } |
| sam_grove | 5:3f93dd1d4cb3 | 801 | |
| sam_grove | 5:3f93dd1d4cb3 | 802 | int ethernet_link(void) { |
| sam_grove | 5:3f93dd1d4cb3 | 803 | |
| sam_grove | 5:3f93dd1d4cb3 | 804 | if (phy_id == DP83848C_ID) { |
| sam_grove | 5:3f93dd1d4cb3 | 805 | return (phy_read(PHY_REG_STS) & PHY_STS_LINK); |
| sam_grove | 5:3f93dd1d4cb3 | 806 | } |
| sam_grove | 5:3f93dd1d4cb3 | 807 | else { // LAN8720_ID |
| sam_grove | 5:3f93dd1d4cb3 | 808 | return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK); |
| sam_grove | 5:3f93dd1d4cb3 | 809 | } |
| sam_grove | 5:3f93dd1d4cb3 | 810 | } |
| sam_grove | 5:3f93dd1d4cb3 | 811 | |
| sam_grove | 5:3f93dd1d4cb3 | 812 | static int phy_write(unsigned int PhyReg, unsigned short Data) { |
| sam_grove | 5:3f93dd1d4cb3 | 813 | unsigned int timeOut; |
| sam_grove | 5:3f93dd1d4cb3 | 814 | |
| sam_grove | 5:3f93dd1d4cb3 | 815 | LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; |
| sam_grove | 5:3f93dd1d4cb3 | 816 | LPC_EMAC->MWTD = Data; |
| sam_grove | 5:3f93dd1d4cb3 | 817 | |
| sam_grove | 5:3f93dd1d4cb3 | 818 | for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */ |
| sam_grove | 5:3f93dd1d4cb3 | 819 | if((LPC_EMAC->MIND & MIND_BUSY) == 0) { |
| sam_grove | 5:3f93dd1d4cb3 | 820 | return 0; |
| sam_grove | 5:3f93dd1d4cb3 | 821 | } |
| sam_grove | 5:3f93dd1d4cb3 | 822 | } |
| sam_grove | 5:3f93dd1d4cb3 | 823 | |
| sam_grove | 5:3f93dd1d4cb3 | 824 | return -1; |
| sam_grove | 5:3f93dd1d4cb3 | 825 | } |
| sam_grove | 5:3f93dd1d4cb3 | 826 | |
| sam_grove | 5:3f93dd1d4cb3 | 827 | |
| sam_grove | 5:3f93dd1d4cb3 | 828 | static int phy_read(unsigned int PhyReg) { |
| sam_grove | 5:3f93dd1d4cb3 | 829 | unsigned int timeOut; |
| sam_grove | 5:3f93dd1d4cb3 | 830 | |
| sam_grove | 5:3f93dd1d4cb3 | 831 | LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; |
| sam_grove | 5:3f93dd1d4cb3 | 832 | LPC_EMAC->MCMD = MCMD_READ; |
| sam_grove | 5:3f93dd1d4cb3 | 833 | |
| sam_grove | 5:3f93dd1d4cb3 | 834 | for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */ |
| sam_grove | 5:3f93dd1d4cb3 | 835 | if((LPC_EMAC->MIND & MIND_BUSY) == 0) { |
| sam_grove | 5:3f93dd1d4cb3 | 836 | LPC_EMAC->MCMD = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 837 | return LPC_EMAC->MRDD; /* Return a 16-bit value. */ |
| sam_grove | 5:3f93dd1d4cb3 | 838 | } |
| sam_grove | 5:3f93dd1d4cb3 | 839 | } |
| sam_grove | 5:3f93dd1d4cb3 | 840 | |
| sam_grove | 5:3f93dd1d4cb3 | 841 | return -1; |
| sam_grove | 5:3f93dd1d4cb3 | 842 | } |
| sam_grove | 5:3f93dd1d4cb3 | 843 | |
| sam_grove | 5:3f93dd1d4cb3 | 844 | |
| sam_grove | 5:3f93dd1d4cb3 | 845 | static void txdscr_init() { |
| sam_grove | 5:3f93dd1d4cb3 | 846 | int i; |
| sam_grove | 5:3f93dd1d4cb3 | 847 | |
| sam_grove | 5:3f93dd1d4cb3 | 848 | for(i = 0; i < NUM_TX_FRAG; i++) { |
| sam_grove | 5:3f93dd1d4cb3 | 849 | txdesc[i].Packet = (uint32_t)&txbuf[i]; |
| sam_grove | 5:3f93dd1d4cb3 | 850 | txdesc[i].Ctrl = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 851 | txstat[i].Info = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 852 | } |
| sam_grove | 5:3f93dd1d4cb3 | 853 | |
| sam_grove | 5:3f93dd1d4cb3 | 854 | LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */ |
| sam_grove | 5:3f93dd1d4cb3 | 855 | LPC_EMAC->TxStatus = (uint32_t)txstat; |
| sam_grove | 5:3f93dd1d4cb3 | 856 | LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; |
| sam_grove | 5:3f93dd1d4cb3 | 857 | |
| sam_grove | 5:3f93dd1d4cb3 | 858 | LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */ |
| sam_grove | 5:3f93dd1d4cb3 | 859 | } |
| sam_grove | 5:3f93dd1d4cb3 | 860 | |
| sam_grove | 5:3f93dd1d4cb3 | 861 | |
| sam_grove | 5:3f93dd1d4cb3 | 862 | static void rxdscr_init() { |
| sam_grove | 5:3f93dd1d4cb3 | 863 | int i; |
| sam_grove | 5:3f93dd1d4cb3 | 864 | |
| sam_grove | 5:3f93dd1d4cb3 | 865 | for(i = 0; i < NUM_RX_FRAG; i++) { |
| sam_grove | 5:3f93dd1d4cb3 | 866 | rxdesc[i].Packet = (uint32_t)&rxbuf[i]; |
| sam_grove | 5:3f93dd1d4cb3 | 867 | rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1); |
| sam_grove | 5:3f93dd1d4cb3 | 868 | rxstat[i].Info = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 869 | rxstat[i].HashCRC = 0; |
| sam_grove | 5:3f93dd1d4cb3 | 870 | } |
| sam_grove | 5:3f93dd1d4cb3 | 871 | |
| sam_grove | 5:3f93dd1d4cb3 | 872 | LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */ |
| sam_grove | 5:3f93dd1d4cb3 | 873 | LPC_EMAC->RxStatus = (uint32_t)rxstat; |
| sam_grove | 5:3f93dd1d4cb3 | 874 | LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; |
| sam_grove | 5:3f93dd1d4cb3 | 875 | |
| sam_grove | 5:3f93dd1d4cb3 | 876 | LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */ |
| sam_grove | 5:3f93dd1d4cb3 | 877 | } |
| sam_grove | 5:3f93dd1d4cb3 | 878 | |
| sam_grove | 5:3f93dd1d4cb3 | 879 | void ethernet_address(char *mac) { |
| sam_grove | 5:3f93dd1d4cb3 | 880 | mbed_mac_address(mac); |
| sam_grove | 5:3f93dd1d4cb3 | 881 | } |
| sam_grove | 5:3f93dd1d4cb3 | 882 | |
| sam_grove | 5:3f93dd1d4cb3 | 883 | void ethernet_set_link(int speed, int duplex) { |
| sam_grove | 5:3f93dd1d4cb3 | 884 | unsigned short phy_data; |
| sam_grove | 5:3f93dd1d4cb3 | 885 | int tout; |
| sam_grove | 5:3f93dd1d4cb3 | 886 | |
| sam_grove | 5:3f93dd1d4cb3 | 887 | if((speed < 0) || (speed > 1)) { |
| sam_grove | 5:3f93dd1d4cb3 | 888 | |
| sam_grove | 5:3f93dd1d4cb3 | 889 | phy_data = PHY_AUTO_NEG; |
| sam_grove | 5:3f93dd1d4cb3 | 890 | |
| sam_grove | 5:3f93dd1d4cb3 | 891 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 892 | |
| sam_grove | 5:3f93dd1d4cb3 | 893 | phy_data = (((unsigned short) speed << 13) | |
| sam_grove | 5:3f93dd1d4cb3 | 894 | ((unsigned short) duplex << 8)); |
| sam_grove | 5:3f93dd1d4cb3 | 895 | } |
| sam_grove | 5:3f93dd1d4cb3 | 896 | |
| sam_grove | 5:3f93dd1d4cb3 | 897 | phy_write(PHY_REG_BMCR, phy_data); |
| sam_grove | 5:3f93dd1d4cb3 | 898 | |
| sam_grove | 5:3f93dd1d4cb3 | 899 | for(tout = 100; tout; tout--) { __NOP(); } /* A short delay */ |
| sam_grove | 5:3f93dd1d4cb3 | 900 | |
| sam_grove | 5:3f93dd1d4cb3 | 901 | switch(phy_id) { |
| sam_grove | 5:3f93dd1d4cb3 | 902 | case DP83848C_ID: |
| sam_grove | 5:3f93dd1d4cb3 | 903 | |
| sam_grove | 5:3f93dd1d4cb3 | 904 | phy_data = phy_read(PHY_REG_STS); |
| sam_grove | 5:3f93dd1d4cb3 | 905 | |
| sam_grove | 5:3f93dd1d4cb3 | 906 | if(phy_data & PHY_STS_DUPLEX) { |
| sam_grove | 5:3f93dd1d4cb3 | 907 | LPC_EMAC->MAC2 |= MAC2_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 908 | LPC_EMAC->Command |= CR_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 909 | LPC_EMAC->IPGT = IPGT_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 910 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 911 | LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 912 | LPC_EMAC->Command &= ~CR_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 913 | LPC_EMAC->IPGT = IPGT_HALF_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 914 | } |
| sam_grove | 5:3f93dd1d4cb3 | 915 | |
| sam_grove | 5:3f93dd1d4cb3 | 916 | if(phy_data & PHY_STS_SPEED) { |
| sam_grove | 5:3f93dd1d4cb3 | 917 | LPC_EMAC->SUPP &= ~SUPP_SPEED; |
| sam_grove | 5:3f93dd1d4cb3 | 918 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 919 | LPC_EMAC->SUPP |= SUPP_SPEED; |
| sam_grove | 5:3f93dd1d4cb3 | 920 | } |
| sam_grove | 5:3f93dd1d4cb3 | 921 | |
| sam_grove | 5:3f93dd1d4cb3 | 922 | |
| sam_grove | 5:3f93dd1d4cb3 | 923 | break; |
| sam_grove | 5:3f93dd1d4cb3 | 924 | case LAN8720_ID: |
| sam_grove | 5:3f93dd1d4cb3 | 925 | |
| sam_grove | 5:3f93dd1d4cb3 | 926 | phy_data = phy_read(PHY_REG_SCSR); |
| sam_grove | 5:3f93dd1d4cb3 | 927 | |
| sam_grove | 5:3f93dd1d4cb3 | 928 | if (phy_data & PHY_SCSR_DUPLEX) { |
| sam_grove | 5:3f93dd1d4cb3 | 929 | LPC_EMAC->MAC2 |= MAC2_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 930 | LPC_EMAC->Command |= CR_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 931 | LPC_EMAC->IPGT = IPGT_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 932 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 933 | LPC_EMAC->Command &= ~CR_FULL_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 934 | LPC_EMAC->IPGT = IPGT_HALF_DUP; |
| sam_grove | 5:3f93dd1d4cb3 | 935 | } |
| sam_grove | 5:3f93dd1d4cb3 | 936 | |
| sam_grove | 5:3f93dd1d4cb3 | 937 | if(phy_data & PHY_SCSR_100MBIT) { |
| sam_grove | 5:3f93dd1d4cb3 | 938 | LPC_EMAC->SUPP |= SUPP_SPEED; |
| sam_grove | 5:3f93dd1d4cb3 | 939 | } else { |
| sam_grove | 5:3f93dd1d4cb3 | 940 | LPC_EMAC->SUPP &= ~SUPP_SPEED; |
| sam_grove | 5:3f93dd1d4cb3 | 941 | } |
| sam_grove | 5:3f93dd1d4cb3 | 942 | |
| sam_grove | 5:3f93dd1d4cb3 | 943 | |
| sam_grove | 5:3f93dd1d4cb3 | 944 | break; |
| sam_grove | 5:3f93dd1d4cb3 | 945 | } |
| sam_grove | 5:3f93dd1d4cb3 | 946 | |
| sam_grove | 5:3f93dd1d4cb3 | 947 | |
| sam_grove | 5:3f93dd1d4cb3 | 948 | } |
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Repository details
| Type: | Program |
|---|---|
| Created: | 24 Sep 2013 |
| Imports: | 6 |
| Forks: | 0 |
| Commits: | 22 |
| Dependents: | 0 |
| Dependencies: | 0 |
| Followers: | 4 |
This repository is Public (Unlisted).
The code in this repository is Apache licensed.