Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/hal/TARGET_NXP/TARGET_LPC176X/can_api.c@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /* mbed Microcontroller Library
sam_grove 5:3f93dd1d4cb3 2 * Copyright (c) 2006-2013 ARM Limited
sam_grove 5:3f93dd1d4cb3 3 *
sam_grove 5:3f93dd1d4cb3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sam_grove 5:3f93dd1d4cb3 5 * you may not use this file except in compliance with the License.
sam_grove 5:3f93dd1d4cb3 6 * You may obtain a copy of the License at
sam_grove 5:3f93dd1d4cb3 7 *
sam_grove 5:3f93dd1d4cb3 8 * http://www.apache.org/licenses/LICENSE-2.0
sam_grove 5:3f93dd1d4cb3 9 *
sam_grove 5:3f93dd1d4cb3 10 * Unless required by applicable law or agreed to in writing, software
sam_grove 5:3f93dd1d4cb3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sam_grove 5:3f93dd1d4cb3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sam_grove 5:3f93dd1d4cb3 13 * See the License for the specific language governing permissions and
sam_grove 5:3f93dd1d4cb3 14 * limitations under the License.
sam_grove 5:3f93dd1d4cb3 15 */
sam_grove 5:3f93dd1d4cb3 16 #include "can_api.h"
sam_grove 5:3f93dd1d4cb3 17
sam_grove 5:3f93dd1d4cb3 18 #include "cmsis.h"
sam_grove 5:3f93dd1d4cb3 19 #include "pinmap.h"
sam_grove 5:3f93dd1d4cb3 20 #include "error.h"
sam_grove 5:3f93dd1d4cb3 21
sam_grove 5:3f93dd1d4cb3 22 #include <math.h>
sam_grove 5:3f93dd1d4cb3 23 #include <string.h>
sam_grove 5:3f93dd1d4cb3 24
sam_grove 5:3f93dd1d4cb3 25 #define CAN_NUM 2
sam_grove 5:3f93dd1d4cb3 26
sam_grove 5:3f93dd1d4cb3 27 /* Acceptance filter mode in AFMR register */
sam_grove 5:3f93dd1d4cb3 28 #define ACCF_OFF 0x01
sam_grove 5:3f93dd1d4cb3 29 #define ACCF_BYPASS 0x02
sam_grove 5:3f93dd1d4cb3 30 #define ACCF_ON 0x00
sam_grove 5:3f93dd1d4cb3 31 #define ACCF_FULLCAN 0x04
sam_grove 5:3f93dd1d4cb3 32
sam_grove 5:3f93dd1d4cb3 33 /* There are several bit timing calculators on the internet.
sam_grove 5:3f93dd1d4cb3 34 http://www.port.de/engl/canprod/sv_req_form.html
sam_grove 5:3f93dd1d4cb3 35 http://www.kvaser.com/can/index.htm
sam_grove 5:3f93dd1d4cb3 36 */
sam_grove 5:3f93dd1d4cb3 37
sam_grove 5:3f93dd1d4cb3 38 static const PinMap PinMap_CAN_RD[] = {
sam_grove 5:3f93dd1d4cb3 39 {P0_0 , CAN_1, 1},
sam_grove 5:3f93dd1d4cb3 40 {P0_4 , CAN_2, 2},
sam_grove 5:3f93dd1d4cb3 41 {P0_21, CAN_1, 3},
sam_grove 5:3f93dd1d4cb3 42 {P2_7 , CAN_2, 1},
sam_grove 5:3f93dd1d4cb3 43 {NC , NC , 0}
sam_grove 5:3f93dd1d4cb3 44 };
sam_grove 5:3f93dd1d4cb3 45
sam_grove 5:3f93dd1d4cb3 46 static const PinMap PinMap_CAN_TD[] = {
sam_grove 5:3f93dd1d4cb3 47 {P0_1 , CAN_1, 1},
sam_grove 5:3f93dd1d4cb3 48 {P0_5 , CAN_2, 2},
sam_grove 5:3f93dd1d4cb3 49 {P0_22, CAN_1, 3},
sam_grove 5:3f93dd1d4cb3 50 {P2_8 , CAN_2, 1},
sam_grove 5:3f93dd1d4cb3 51 {NC , NC , 0}
sam_grove 5:3f93dd1d4cb3 52 };
sam_grove 5:3f93dd1d4cb3 53
sam_grove 5:3f93dd1d4cb3 54 // Type definition to hold a CAN message
sam_grove 5:3f93dd1d4cb3 55 struct CANMsg {
sam_grove 5:3f93dd1d4cb3 56 unsigned int reserved1 : 16;
sam_grove 5:3f93dd1d4cb3 57 unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
sam_grove 5:3f93dd1d4cb3 58 unsigned int reserved0 : 10;
sam_grove 5:3f93dd1d4cb3 59 unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
sam_grove 5:3f93dd1d4cb3 60 unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
sam_grove 5:3f93dd1d4cb3 61 unsigned int id; // CAN Message ID (11-bit or 29-bit)
sam_grove 5:3f93dd1d4cb3 62 unsigned char data[8]; // CAN Message Data Bytes 0-7
sam_grove 5:3f93dd1d4cb3 63 };
sam_grove 5:3f93dd1d4cb3 64 typedef struct CANMsg CANMsg;
sam_grove 5:3f93dd1d4cb3 65
sam_grove 5:3f93dd1d4cb3 66 static uint32_t can_irq_ids[CAN_NUM] = {0};
sam_grove 5:3f93dd1d4cb3 67 static can_irq_handler irq_handler;
sam_grove 5:3f93dd1d4cb3 68
sam_grove 5:3f93dd1d4cb3 69 static uint32_t can_disable(can_t *obj) {
sam_grove 5:3f93dd1d4cb3 70 uint32_t sm = obj->dev->MOD;
sam_grove 5:3f93dd1d4cb3 71 obj->dev->MOD |= 1;
sam_grove 5:3f93dd1d4cb3 72 return sm;
sam_grove 5:3f93dd1d4cb3 73 }
sam_grove 5:3f93dd1d4cb3 74
sam_grove 5:3f93dd1d4cb3 75 static inline void can_enable(can_t *obj) {
sam_grove 5:3f93dd1d4cb3 76 if (obj->dev->MOD & 1) {
sam_grove 5:3f93dd1d4cb3 77 obj->dev->MOD &= ~(1);
sam_grove 5:3f93dd1d4cb3 78 }
sam_grove 5:3f93dd1d4cb3 79 }
sam_grove 5:3f93dd1d4cb3 80
sam_grove 5:3f93dd1d4cb3 81 int can_mode(can_t *obj, CanMode mode)
sam_grove 5:3f93dd1d4cb3 82 {
sam_grove 5:3f93dd1d4cb3 83 return 0; // not implemented
sam_grove 5:3f93dd1d4cb3 84 }
sam_grove 5:3f93dd1d4cb3 85
sam_grove 5:3f93dd1d4cb3 86 static inline void can_irq(uint32_t icr, uint32_t index) {
sam_grove 5:3f93dd1d4cb3 87 uint32_t i;
sam_grove 5:3f93dd1d4cb3 88
sam_grove 5:3f93dd1d4cb3 89 for(i = 0; i < 8; i++)
sam_grove 5:3f93dd1d4cb3 90 {
sam_grove 5:3f93dd1d4cb3 91 if((can_irq_ids[index] != 0) && (icr & (1 << i)))
sam_grove 5:3f93dd1d4cb3 92 {
sam_grove 5:3f93dd1d4cb3 93 switch (i) {
sam_grove 5:3f93dd1d4cb3 94 case 0: irq_handler(can_irq_ids[index], IRQ_RX); break;
sam_grove 5:3f93dd1d4cb3 95 case 1: irq_handler(can_irq_ids[index], IRQ_TX); break;
sam_grove 5:3f93dd1d4cb3 96 case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break;
sam_grove 5:3f93dd1d4cb3 97 case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
sam_grove 5:3f93dd1d4cb3 98 case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break;
sam_grove 5:3f93dd1d4cb3 99 case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
sam_grove 5:3f93dd1d4cb3 100 case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break;
sam_grove 5:3f93dd1d4cb3 101 case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break;
sam_grove 5:3f93dd1d4cb3 102 case 8: irq_handler(can_irq_ids[index], IRQ_READY); break;
sam_grove 5:3f93dd1d4cb3 103 }
sam_grove 5:3f93dd1d4cb3 104 }
sam_grove 5:3f93dd1d4cb3 105 }
sam_grove 5:3f93dd1d4cb3 106 }
sam_grove 5:3f93dd1d4cb3 107
sam_grove 5:3f93dd1d4cb3 108 // Have to check that the CAN block is active before reading the Interrupt
sam_grove 5:3f93dd1d4cb3 109 // Control Register, or the mbed hangs
sam_grove 5:3f93dd1d4cb3 110 void can_irq_n() {
sam_grove 5:3f93dd1d4cb3 111 uint32_t icr;
sam_grove 5:3f93dd1d4cb3 112
sam_grove 5:3f93dd1d4cb3 113 if(LPC_SC->PCONP & (1 << 13)) {
sam_grove 5:3f93dd1d4cb3 114 icr = LPC_CAN1->ICR & 0x1FF;
sam_grove 5:3f93dd1d4cb3 115 can_irq(icr, 0);
sam_grove 5:3f93dd1d4cb3 116 }
sam_grove 5:3f93dd1d4cb3 117
sam_grove 5:3f93dd1d4cb3 118 if(LPC_SC->PCONP & (1 << 14)) {
sam_grove 5:3f93dd1d4cb3 119 icr = LPC_CAN2->ICR & 0x1FF;
sam_grove 5:3f93dd1d4cb3 120 can_irq(icr, 1);
sam_grove 5:3f93dd1d4cb3 121 }
sam_grove 5:3f93dd1d4cb3 122 }
sam_grove 5:3f93dd1d4cb3 123
sam_grove 5:3f93dd1d4cb3 124 // Register CAN object's irq handler
sam_grove 5:3f93dd1d4cb3 125 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
sam_grove 5:3f93dd1d4cb3 126 irq_handler = handler;
sam_grove 5:3f93dd1d4cb3 127 can_irq_ids[obj->index] = id;
sam_grove 5:3f93dd1d4cb3 128 }
sam_grove 5:3f93dd1d4cb3 129
sam_grove 5:3f93dd1d4cb3 130 // Unregister CAN object's irq handler
sam_grove 5:3f93dd1d4cb3 131 void can_irq_free(can_t *obj) {
sam_grove 5:3f93dd1d4cb3 132 obj->dev->IER &= ~(1);
sam_grove 5:3f93dd1d4cb3 133 can_irq_ids[obj->index] = 0;
sam_grove 5:3f93dd1d4cb3 134
sam_grove 5:3f93dd1d4cb3 135 if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
sam_grove 5:3f93dd1d4cb3 136 NVIC_DisableIRQ(CAN_IRQn);
sam_grove 5:3f93dd1d4cb3 137 }
sam_grove 5:3f93dd1d4cb3 138 }
sam_grove 5:3f93dd1d4cb3 139
sam_grove 5:3f93dd1d4cb3 140 // Clear or set a irq
sam_grove 5:3f93dd1d4cb3 141 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
sam_grove 5:3f93dd1d4cb3 142 uint32_t ier;
sam_grove 5:3f93dd1d4cb3 143
sam_grove 5:3f93dd1d4cb3 144 switch (type) {
sam_grove 5:3f93dd1d4cb3 145 case IRQ_RX: ier = (1 << 0); break;
sam_grove 5:3f93dd1d4cb3 146 case IRQ_TX: ier = (1 << 1); break;
sam_grove 5:3f93dd1d4cb3 147 case IRQ_ERROR: ier = (1 << 2); break;
sam_grove 5:3f93dd1d4cb3 148 case IRQ_OVERRUN: ier = (1 << 3); break;
sam_grove 5:3f93dd1d4cb3 149 case IRQ_WAKEUP: ier = (1 << 4); break;
sam_grove 5:3f93dd1d4cb3 150 case IRQ_PASSIVE: ier = (1 << 5); break;
sam_grove 5:3f93dd1d4cb3 151 case IRQ_ARB: ier = (1 << 6); break;
sam_grove 5:3f93dd1d4cb3 152 case IRQ_BUS: ier = (1 << 7); break;
sam_grove 5:3f93dd1d4cb3 153 case IRQ_READY: ier = (1 << 8); break;
sam_grove 5:3f93dd1d4cb3 154 default: return;
sam_grove 5:3f93dd1d4cb3 155 }
sam_grove 5:3f93dd1d4cb3 156
sam_grove 5:3f93dd1d4cb3 157 obj->dev->MOD |= 1;
sam_grove 5:3f93dd1d4cb3 158 if(enable == 0) {
sam_grove 5:3f93dd1d4cb3 159 obj->dev->IER &= ~ier;
sam_grove 5:3f93dd1d4cb3 160 }
sam_grove 5:3f93dd1d4cb3 161 else {
sam_grove 5:3f93dd1d4cb3 162 obj->dev->IER |= ier;
sam_grove 5:3f93dd1d4cb3 163 }
sam_grove 5:3f93dd1d4cb3 164 obj->dev->MOD &= ~(1);
sam_grove 5:3f93dd1d4cb3 165
sam_grove 5:3f93dd1d4cb3 166 // Enable NVIC if at least 1 interrupt is active
sam_grove 5:3f93dd1d4cb3 167 if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) {
sam_grove 5:3f93dd1d4cb3 168 NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
sam_grove 5:3f93dd1d4cb3 169 NVIC_EnableIRQ(CAN_IRQn);
sam_grove 5:3f93dd1d4cb3 170 }
sam_grove 5:3f93dd1d4cb3 171 else {
sam_grove 5:3f93dd1d4cb3 172 NVIC_DisableIRQ(CAN_IRQn);
sam_grove 5:3f93dd1d4cb3 173 }
sam_grove 5:3f93dd1d4cb3 174 }
sam_grove 5:3f93dd1d4cb3 175
sam_grove 5:3f93dd1d4cb3 176 static int can_pclk(can_t *obj) {
sam_grove 5:3f93dd1d4cb3 177 int value = 0;
sam_grove 5:3f93dd1d4cb3 178 switch ((int)obj->dev) {
sam_grove 5:3f93dd1d4cb3 179 case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break;
sam_grove 5:3f93dd1d4cb3 180 case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break;
sam_grove 5:3f93dd1d4cb3 181 }
sam_grove 5:3f93dd1d4cb3 182
sam_grove 5:3f93dd1d4cb3 183 switch (value) {
sam_grove 5:3f93dd1d4cb3 184 case 1: return 1;
sam_grove 5:3f93dd1d4cb3 185 case 2: return 2;
sam_grove 5:3f93dd1d4cb3 186 case 3: return 6;
sam_grove 5:3f93dd1d4cb3 187 default: return 4;
sam_grove 5:3f93dd1d4cb3 188 }
sam_grove 5:3f93dd1d4cb3 189 }
sam_grove 5:3f93dd1d4cb3 190
sam_grove 5:3f93dd1d4cb3 191 // This table has the sampling points as close to 75% as possible. The first
sam_grove 5:3f93dd1d4cb3 192 // value is TSEG1, the second TSEG2.
sam_grove 5:3f93dd1d4cb3 193 static const int timing_pts[23][2] = {
sam_grove 5:3f93dd1d4cb3 194 {0x0, 0x0}, // 2, 50%
sam_grove 5:3f93dd1d4cb3 195 {0x1, 0x0}, // 3, 67%
sam_grove 5:3f93dd1d4cb3 196 {0x2, 0x0}, // 4, 75%
sam_grove 5:3f93dd1d4cb3 197 {0x3, 0x0}, // 5, 80%
sam_grove 5:3f93dd1d4cb3 198 {0x3, 0x1}, // 6, 67%
sam_grove 5:3f93dd1d4cb3 199 {0x4, 0x1}, // 7, 71%
sam_grove 5:3f93dd1d4cb3 200 {0x5, 0x1}, // 8, 75%
sam_grove 5:3f93dd1d4cb3 201 {0x6, 0x1}, // 9, 78%
sam_grove 5:3f93dd1d4cb3 202 {0x6, 0x2}, // 10, 70%
sam_grove 5:3f93dd1d4cb3 203 {0x7, 0x2}, // 11, 73%
sam_grove 5:3f93dd1d4cb3 204 {0x8, 0x2}, // 12, 75%
sam_grove 5:3f93dd1d4cb3 205 {0x9, 0x2}, // 13, 77%
sam_grove 5:3f93dd1d4cb3 206 {0x9, 0x3}, // 14, 71%
sam_grove 5:3f93dd1d4cb3 207 {0xA, 0x3}, // 15, 73%
sam_grove 5:3f93dd1d4cb3 208 {0xB, 0x3}, // 16, 75%
sam_grove 5:3f93dd1d4cb3 209 {0xC, 0x3}, // 17, 76%
sam_grove 5:3f93dd1d4cb3 210 {0xD, 0x3}, // 18, 78%
sam_grove 5:3f93dd1d4cb3 211 {0xD, 0x4}, // 19, 74%
sam_grove 5:3f93dd1d4cb3 212 {0xE, 0x4}, // 20, 75%
sam_grove 5:3f93dd1d4cb3 213 {0xF, 0x4}, // 21, 76%
sam_grove 5:3f93dd1d4cb3 214 {0xF, 0x5}, // 22, 73%
sam_grove 5:3f93dd1d4cb3 215 {0xF, 0x6}, // 23, 70%
sam_grove 5:3f93dd1d4cb3 216 {0xF, 0x7}, // 24, 67%
sam_grove 5:3f93dd1d4cb3 217 };
sam_grove 5:3f93dd1d4cb3 218
sam_grove 5:3f93dd1d4cb3 219 static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
sam_grove 5:3f93dd1d4cb3 220 uint32_t btr;
sam_grove 5:3f93dd1d4cb3 221 uint16_t brp = 0;
sam_grove 5:3f93dd1d4cb3 222 uint32_t calcbit;
sam_grove 5:3f93dd1d4cb3 223 uint32_t bitwidth;
sam_grove 5:3f93dd1d4cb3 224 int hit = 0;
sam_grove 5:3f93dd1d4cb3 225 int bits;
sam_grove 5:3f93dd1d4cb3 226
sam_grove 5:3f93dd1d4cb3 227 bitwidth = sclk / (pclk * cclk);
sam_grove 5:3f93dd1d4cb3 228
sam_grove 5:3f93dd1d4cb3 229 brp = bitwidth / 0x18;
sam_grove 5:3f93dd1d4cb3 230 while ((!hit) && (brp < bitwidth / 4)) {
sam_grove 5:3f93dd1d4cb3 231 brp++;
sam_grove 5:3f93dd1d4cb3 232 for (bits = 22; bits > 0; bits--) {
sam_grove 5:3f93dd1d4cb3 233 calcbit = (bits + 3) * (brp + 1);
sam_grove 5:3f93dd1d4cb3 234 if (calcbit == bitwidth) {
sam_grove 5:3f93dd1d4cb3 235 hit = 1;
sam_grove 5:3f93dd1d4cb3 236 break;
sam_grove 5:3f93dd1d4cb3 237 }
sam_grove 5:3f93dd1d4cb3 238 }
sam_grove 5:3f93dd1d4cb3 239 }
sam_grove 5:3f93dd1d4cb3 240
sam_grove 5:3f93dd1d4cb3 241 if (hit) {
sam_grove 5:3f93dd1d4cb3 242 btr = ((timing_pts[bits][1] << 20) & 0x00700000)
sam_grove 5:3f93dd1d4cb3 243 | ((timing_pts[bits][0] << 16) & 0x000F0000)
sam_grove 5:3f93dd1d4cb3 244 | ((psjw << 14) & 0x0000C000)
sam_grove 5:3f93dd1d4cb3 245 | ((brp << 0) & 0x000003FF);
sam_grove 5:3f93dd1d4cb3 246 } else {
sam_grove 5:3f93dd1d4cb3 247 btr = 0xFFFFFFFF;
sam_grove 5:3f93dd1d4cb3 248 }
sam_grove 5:3f93dd1d4cb3 249
sam_grove 5:3f93dd1d4cb3 250 return btr;
sam_grove 5:3f93dd1d4cb3 251
sam_grove 5:3f93dd1d4cb3 252 }
sam_grove 5:3f93dd1d4cb3 253
sam_grove 5:3f93dd1d4cb3 254 void can_init(can_t *obj, PinName rd, PinName td) {
sam_grove 5:3f93dd1d4cb3 255 CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
sam_grove 5:3f93dd1d4cb3 256 CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
sam_grove 5:3f93dd1d4cb3 257 obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
sam_grove 5:3f93dd1d4cb3 258 if ((int)obj->dev == NC) {
sam_grove 5:3f93dd1d4cb3 259 error("CAN pin mapping failed");
sam_grove 5:3f93dd1d4cb3 260 }
sam_grove 5:3f93dd1d4cb3 261
sam_grove 5:3f93dd1d4cb3 262 switch ((int)obj->dev) {
sam_grove 5:3f93dd1d4cb3 263 case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
sam_grove 5:3f93dd1d4cb3 264 case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
sam_grove 5:3f93dd1d4cb3 265 }
sam_grove 5:3f93dd1d4cb3 266
sam_grove 5:3f93dd1d4cb3 267 pinmap_pinout(rd, PinMap_CAN_RD);
sam_grove 5:3f93dd1d4cb3 268 pinmap_pinout(td, PinMap_CAN_TD);
sam_grove 5:3f93dd1d4cb3 269
sam_grove 5:3f93dd1d4cb3 270 switch ((int)obj->dev) {
sam_grove 5:3f93dd1d4cb3 271 case CAN_1: obj->index = 0; break;
sam_grove 5:3f93dd1d4cb3 272 case CAN_2: obj->index = 1; break;
sam_grove 5:3f93dd1d4cb3 273 }
sam_grove 5:3f93dd1d4cb3 274
sam_grove 5:3f93dd1d4cb3 275 can_reset(obj);
sam_grove 5:3f93dd1d4cb3 276 obj->dev->IER = 0; // Disable Interrupts
sam_grove 5:3f93dd1d4cb3 277 can_frequency(obj, 100000);
sam_grove 5:3f93dd1d4cb3 278
sam_grove 5:3f93dd1d4cb3 279 LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
sam_grove 5:3f93dd1d4cb3 280 }
sam_grove 5:3f93dd1d4cb3 281
sam_grove 5:3f93dd1d4cb3 282 void can_free(can_t *obj) {
sam_grove 5:3f93dd1d4cb3 283 switch ((int)obj->dev) {
sam_grove 5:3f93dd1d4cb3 284 case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
sam_grove 5:3f93dd1d4cb3 285 case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
sam_grove 5:3f93dd1d4cb3 286 }
sam_grove 5:3f93dd1d4cb3 287 }
sam_grove 5:3f93dd1d4cb3 288
sam_grove 5:3f93dd1d4cb3 289 int can_frequency(can_t *obj, int f) {
sam_grove 5:3f93dd1d4cb3 290 int pclk = can_pclk(obj);
sam_grove 5:3f93dd1d4cb3 291
sam_grove 5:3f93dd1d4cb3 292 int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
sam_grove 5:3f93dd1d4cb3 293
sam_grove 5:3f93dd1d4cb3 294 if (btr > 0) {
sam_grove 5:3f93dd1d4cb3 295 uint32_t modmask = can_disable(obj);
sam_grove 5:3f93dd1d4cb3 296 obj->dev->BTR = btr;
sam_grove 5:3f93dd1d4cb3 297 obj->dev->MOD = modmask;
sam_grove 5:3f93dd1d4cb3 298 return 1;
sam_grove 5:3f93dd1d4cb3 299 } else {
sam_grove 5:3f93dd1d4cb3 300 return 0;
sam_grove 5:3f93dd1d4cb3 301 }
sam_grove 5:3f93dd1d4cb3 302 }
sam_grove 5:3f93dd1d4cb3 303
sam_grove 5:3f93dd1d4cb3 304 int can_write(can_t *obj, CAN_Message msg, int cc) {
sam_grove 5:3f93dd1d4cb3 305 unsigned int CANStatus;
sam_grove 5:3f93dd1d4cb3 306 CANMsg m;
sam_grove 5:3f93dd1d4cb3 307
sam_grove 5:3f93dd1d4cb3 308 can_enable(obj);
sam_grove 5:3f93dd1d4cb3 309
sam_grove 5:3f93dd1d4cb3 310 m.id = msg.id ;
sam_grove 5:3f93dd1d4cb3 311 m.dlc = msg.len & 0xF;
sam_grove 5:3f93dd1d4cb3 312 m.rtr = msg.type;
sam_grove 5:3f93dd1d4cb3 313 m.type = msg.format;
sam_grove 5:3f93dd1d4cb3 314 memcpy(m.data, msg.data, msg.len);
sam_grove 5:3f93dd1d4cb3 315 const unsigned int *buf = (const unsigned int *)&m;
sam_grove 5:3f93dd1d4cb3 316
sam_grove 5:3f93dd1d4cb3 317 CANStatus = obj->dev->SR;
sam_grove 5:3f93dd1d4cb3 318 if (CANStatus & 0x00000004) {
sam_grove 5:3f93dd1d4cb3 319 obj->dev->TFI1 = buf[0] & 0xC00F0000;
sam_grove 5:3f93dd1d4cb3 320 obj->dev->TID1 = buf[1];
sam_grove 5:3f93dd1d4cb3 321 obj->dev->TDA1 = buf[2];
sam_grove 5:3f93dd1d4cb3 322 obj->dev->TDB1 = buf[3];
sam_grove 5:3f93dd1d4cb3 323 if(cc) {
sam_grove 5:3f93dd1d4cb3 324 obj->dev->CMR = 0x30;
sam_grove 5:3f93dd1d4cb3 325 } else {
sam_grove 5:3f93dd1d4cb3 326 obj->dev->CMR = 0x21;
sam_grove 5:3f93dd1d4cb3 327 }
sam_grove 5:3f93dd1d4cb3 328 return 1;
sam_grove 5:3f93dd1d4cb3 329
sam_grove 5:3f93dd1d4cb3 330 } else if (CANStatus & 0x00000400) {
sam_grove 5:3f93dd1d4cb3 331 obj->dev->TFI2 = buf[0] & 0xC00F0000;
sam_grove 5:3f93dd1d4cb3 332 obj->dev->TID2 = buf[1];
sam_grove 5:3f93dd1d4cb3 333 obj->dev->TDA2 = buf[2];
sam_grove 5:3f93dd1d4cb3 334 obj->dev->TDB2 = buf[3];
sam_grove 5:3f93dd1d4cb3 335 if (cc) {
sam_grove 5:3f93dd1d4cb3 336 obj->dev->CMR = 0x50;
sam_grove 5:3f93dd1d4cb3 337 } else {
sam_grove 5:3f93dd1d4cb3 338 obj->dev->CMR = 0x41;
sam_grove 5:3f93dd1d4cb3 339 }
sam_grove 5:3f93dd1d4cb3 340 return 1;
sam_grove 5:3f93dd1d4cb3 341
sam_grove 5:3f93dd1d4cb3 342 } else if (CANStatus & 0x00040000) {
sam_grove 5:3f93dd1d4cb3 343 obj->dev->TFI3 = buf[0] & 0xC00F0000;
sam_grove 5:3f93dd1d4cb3 344 obj->dev->TID3 = buf[1];
sam_grove 5:3f93dd1d4cb3 345 obj->dev->TDA3 = buf[2];
sam_grove 5:3f93dd1d4cb3 346 obj->dev->TDB3 = buf[3];
sam_grove 5:3f93dd1d4cb3 347 if (cc) {
sam_grove 5:3f93dd1d4cb3 348 obj->dev->CMR = 0x90;
sam_grove 5:3f93dd1d4cb3 349 } else {
sam_grove 5:3f93dd1d4cb3 350 obj->dev->CMR = 0x81;
sam_grove 5:3f93dd1d4cb3 351 }
sam_grove 5:3f93dd1d4cb3 352 return 1;
sam_grove 5:3f93dd1d4cb3 353 }
sam_grove 5:3f93dd1d4cb3 354
sam_grove 5:3f93dd1d4cb3 355 return 0;
sam_grove 5:3f93dd1d4cb3 356 }
sam_grove 5:3f93dd1d4cb3 357
sam_grove 5:3f93dd1d4cb3 358 int can_read(can_t *obj, CAN_Message *msg) {
sam_grove 5:3f93dd1d4cb3 359 CANMsg x;
sam_grove 5:3f93dd1d4cb3 360 unsigned int *i = (unsigned int *)&x;
sam_grove 5:3f93dd1d4cb3 361
sam_grove 5:3f93dd1d4cb3 362 can_enable(obj);
sam_grove 5:3f93dd1d4cb3 363
sam_grove 5:3f93dd1d4cb3 364 if (obj->dev->GSR & 0x1) {
sam_grove 5:3f93dd1d4cb3 365 *i++ = obj->dev->RFS; // Frame
sam_grove 5:3f93dd1d4cb3 366 *i++ = obj->dev->RID; // ID
sam_grove 5:3f93dd1d4cb3 367 *i++ = obj->dev->RDA; // Data A
sam_grove 5:3f93dd1d4cb3 368 *i++ = obj->dev->RDB; // Data B
sam_grove 5:3f93dd1d4cb3 369 obj->dev->CMR = 0x04; // release receive buffer
sam_grove 5:3f93dd1d4cb3 370
sam_grove 5:3f93dd1d4cb3 371 msg->id = x.id;
sam_grove 5:3f93dd1d4cb3 372 msg->len = x.dlc;
sam_grove 5:3f93dd1d4cb3 373 msg->format = (x.type)? CANExtended : CANStandard;
sam_grove 5:3f93dd1d4cb3 374 msg->type = (x.rtr)? CANRemote: CANData;
sam_grove 5:3f93dd1d4cb3 375 memcpy(msg->data,x.data,x.dlc);
sam_grove 5:3f93dd1d4cb3 376 return 1;
sam_grove 5:3f93dd1d4cb3 377 }
sam_grove 5:3f93dd1d4cb3 378
sam_grove 5:3f93dd1d4cb3 379 return 0;
sam_grove 5:3f93dd1d4cb3 380 }
sam_grove 5:3f93dd1d4cb3 381
sam_grove 5:3f93dd1d4cb3 382 void can_reset(can_t *obj) {
sam_grove 5:3f93dd1d4cb3 383 can_disable(obj);
sam_grove 5:3f93dd1d4cb3 384 obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
sam_grove 5:3f93dd1d4cb3 385 }
sam_grove 5:3f93dd1d4cb3 386
sam_grove 5:3f93dd1d4cb3 387 unsigned char can_rderror(can_t *obj) {
sam_grove 5:3f93dd1d4cb3 388 return (obj->dev->GSR >> 16) & 0xFF;
sam_grove 5:3f93dd1d4cb3 389 }
sam_grove 5:3f93dd1d4cb3 390
sam_grove 5:3f93dd1d4cb3 391 unsigned char can_tderror(can_t *obj) {
sam_grove 5:3f93dd1d4cb3 392 return (obj->dev->GSR >> 24) & 0xFF;
sam_grove 5:3f93dd1d4cb3 393 }
sam_grove 5:3f93dd1d4cb3 394
sam_grove 5:3f93dd1d4cb3 395 void can_monitor(can_t *obj, int silent) {
sam_grove 5:3f93dd1d4cb3 396 uint32_t mod_mask = can_disable(obj);
sam_grove 5:3f93dd1d4cb3 397 if (silent) {
sam_grove 5:3f93dd1d4cb3 398 obj->dev->MOD |= (1 << 1);
sam_grove 5:3f93dd1d4cb3 399 } else {
sam_grove 5:3f93dd1d4cb3 400 obj->dev->MOD &= ~(1 << 1);
sam_grove 5:3f93dd1d4cb3 401 }
sam_grove 5:3f93dd1d4cb3 402 if (!(mod_mask & 1)) {
sam_grove 5:3f93dd1d4cb3 403 can_enable(obj);
sam_grove 5:3f93dd1d4cb3 404 }
sam_grove 5:3f93dd1d4cb3 405 }