Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/cmsis/core_cmFunc.h@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /**************************************************************************//**
sam_grove 5:3f93dd1d4cb3 2 * @file core_cmFunc.h
sam_grove 5:3f93dd1d4cb3 3 * @brief CMSIS Cortex-M Core Function Access Header File
sam_grove 5:3f93dd1d4cb3 4 * @version V3.20
sam_grove 5:3f93dd1d4cb3 5 * @date 25. February 2013
sam_grove 5:3f93dd1d4cb3 6 *
sam_grove 5:3f93dd1d4cb3 7 * @note
sam_grove 5:3f93dd1d4cb3 8 *
sam_grove 5:3f93dd1d4cb3 9 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
sam_grove 5:3f93dd1d4cb3 11
sam_grove 5:3f93dd1d4cb3 12 All rights reserved.
sam_grove 5:3f93dd1d4cb3 13 Redistribution and use in source and binary forms, with or without
sam_grove 5:3f93dd1d4cb3 14 modification, are permitted provided that the following conditions are met:
sam_grove 5:3f93dd1d4cb3 15 - Redistributions of source code must retain the above copyright
sam_grove 5:3f93dd1d4cb3 16 notice, this list of conditions and the following disclaimer.
sam_grove 5:3f93dd1d4cb3 17 - Redistributions in binary form must reproduce the above copyright
sam_grove 5:3f93dd1d4cb3 18 notice, this list of conditions and the following disclaimer in the
sam_grove 5:3f93dd1d4cb3 19 documentation and/or other materials provided with the distribution.
sam_grove 5:3f93dd1d4cb3 20 - Neither the name of ARM nor the names of its contributors may be used
sam_grove 5:3f93dd1d4cb3 21 to endorse or promote products derived from this software without
sam_grove 5:3f93dd1d4cb3 22 specific prior written permission.
sam_grove 5:3f93dd1d4cb3 23 *
sam_grove 5:3f93dd1d4cb3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sam_grove 5:3f93dd1d4cb3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sam_grove 5:3f93dd1d4cb3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sam_grove 5:3f93dd1d4cb3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sam_grove 5:3f93dd1d4cb3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sam_grove 5:3f93dd1d4cb3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sam_grove 5:3f93dd1d4cb3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sam_grove 5:3f93dd1d4cb3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sam_grove 5:3f93dd1d4cb3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sam_grove 5:3f93dd1d4cb3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sam_grove 5:3f93dd1d4cb3 34 POSSIBILITY OF SUCH DAMAGE.
sam_grove 5:3f93dd1d4cb3 35 ---------------------------------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 36
sam_grove 5:3f93dd1d4cb3 37
sam_grove 5:3f93dd1d4cb3 38 #ifndef __CORE_CMFUNC_H
sam_grove 5:3f93dd1d4cb3 39 #define __CORE_CMFUNC_H
sam_grove 5:3f93dd1d4cb3 40
sam_grove 5:3f93dd1d4cb3 41
sam_grove 5:3f93dd1d4cb3 42 /* ########################### Core Function Access ########################### */
sam_grove 5:3f93dd1d4cb3 43 /** \ingroup CMSIS_Core_FunctionInterface
sam_grove 5:3f93dd1d4cb3 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
sam_grove 5:3f93dd1d4cb3 45 @{
sam_grove 5:3f93dd1d4cb3 46 */
sam_grove 5:3f93dd1d4cb3 47
sam_grove 5:3f93dd1d4cb3 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
sam_grove 5:3f93dd1d4cb3 49 /* ARM armcc specific functions */
sam_grove 5:3f93dd1d4cb3 50
sam_grove 5:3f93dd1d4cb3 51 #if (__ARMCC_VERSION < 400677)
sam_grove 5:3f93dd1d4cb3 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
sam_grove 5:3f93dd1d4cb3 53 #endif
sam_grove 5:3f93dd1d4cb3 54
sam_grove 5:3f93dd1d4cb3 55 /* intrinsic void __enable_irq(); */
sam_grove 5:3f93dd1d4cb3 56 /* intrinsic void __disable_irq(); */
sam_grove 5:3f93dd1d4cb3 57
sam_grove 5:3f93dd1d4cb3 58 /** \brief Get Control Register
sam_grove 5:3f93dd1d4cb3 59
sam_grove 5:3f93dd1d4cb3 60 This function returns the content of the Control Register.
sam_grove 5:3f93dd1d4cb3 61
sam_grove 5:3f93dd1d4cb3 62 \return Control Register value
sam_grove 5:3f93dd1d4cb3 63 */
sam_grove 5:3f93dd1d4cb3 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
sam_grove 5:3f93dd1d4cb3 65 {
sam_grove 5:3f93dd1d4cb3 66 register uint32_t __regControl __ASM("control");
sam_grove 5:3f93dd1d4cb3 67 return(__regControl);
sam_grove 5:3f93dd1d4cb3 68 }
sam_grove 5:3f93dd1d4cb3 69
sam_grove 5:3f93dd1d4cb3 70
sam_grove 5:3f93dd1d4cb3 71 /** \brief Set Control Register
sam_grove 5:3f93dd1d4cb3 72
sam_grove 5:3f93dd1d4cb3 73 This function writes the given value to the Control Register.
sam_grove 5:3f93dd1d4cb3 74
sam_grove 5:3f93dd1d4cb3 75 \param [in] control Control Register value to set
sam_grove 5:3f93dd1d4cb3 76 */
sam_grove 5:3f93dd1d4cb3 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
sam_grove 5:3f93dd1d4cb3 78 {
sam_grove 5:3f93dd1d4cb3 79 register uint32_t __regControl __ASM("control");
sam_grove 5:3f93dd1d4cb3 80 __regControl = control;
sam_grove 5:3f93dd1d4cb3 81 }
sam_grove 5:3f93dd1d4cb3 82
sam_grove 5:3f93dd1d4cb3 83
sam_grove 5:3f93dd1d4cb3 84 /** \brief Get IPSR Register
sam_grove 5:3f93dd1d4cb3 85
sam_grove 5:3f93dd1d4cb3 86 This function returns the content of the IPSR Register.
sam_grove 5:3f93dd1d4cb3 87
sam_grove 5:3f93dd1d4cb3 88 \return IPSR Register value
sam_grove 5:3f93dd1d4cb3 89 */
sam_grove 5:3f93dd1d4cb3 90 __STATIC_INLINE uint32_t __get_IPSR(void)
sam_grove 5:3f93dd1d4cb3 91 {
sam_grove 5:3f93dd1d4cb3 92 register uint32_t __regIPSR __ASM("ipsr");
sam_grove 5:3f93dd1d4cb3 93 return(__regIPSR);
sam_grove 5:3f93dd1d4cb3 94 }
sam_grove 5:3f93dd1d4cb3 95
sam_grove 5:3f93dd1d4cb3 96
sam_grove 5:3f93dd1d4cb3 97 /** \brief Get APSR Register
sam_grove 5:3f93dd1d4cb3 98
sam_grove 5:3f93dd1d4cb3 99 This function returns the content of the APSR Register.
sam_grove 5:3f93dd1d4cb3 100
sam_grove 5:3f93dd1d4cb3 101 \return APSR Register value
sam_grove 5:3f93dd1d4cb3 102 */
sam_grove 5:3f93dd1d4cb3 103 __STATIC_INLINE uint32_t __get_APSR(void)
sam_grove 5:3f93dd1d4cb3 104 {
sam_grove 5:3f93dd1d4cb3 105 register uint32_t __regAPSR __ASM("apsr");
sam_grove 5:3f93dd1d4cb3 106 return(__regAPSR);
sam_grove 5:3f93dd1d4cb3 107 }
sam_grove 5:3f93dd1d4cb3 108
sam_grove 5:3f93dd1d4cb3 109
sam_grove 5:3f93dd1d4cb3 110 /** \brief Get xPSR Register
sam_grove 5:3f93dd1d4cb3 111
sam_grove 5:3f93dd1d4cb3 112 This function returns the content of the xPSR Register.
sam_grove 5:3f93dd1d4cb3 113
sam_grove 5:3f93dd1d4cb3 114 \return xPSR Register value
sam_grove 5:3f93dd1d4cb3 115 */
sam_grove 5:3f93dd1d4cb3 116 __STATIC_INLINE uint32_t __get_xPSR(void)
sam_grove 5:3f93dd1d4cb3 117 {
sam_grove 5:3f93dd1d4cb3 118 register uint32_t __regXPSR __ASM("xpsr");
sam_grove 5:3f93dd1d4cb3 119 return(__regXPSR);
sam_grove 5:3f93dd1d4cb3 120 }
sam_grove 5:3f93dd1d4cb3 121
sam_grove 5:3f93dd1d4cb3 122
sam_grove 5:3f93dd1d4cb3 123 /** \brief Get Process Stack Pointer
sam_grove 5:3f93dd1d4cb3 124
sam_grove 5:3f93dd1d4cb3 125 This function returns the current value of the Process Stack Pointer (PSP).
sam_grove 5:3f93dd1d4cb3 126
sam_grove 5:3f93dd1d4cb3 127 \return PSP Register value
sam_grove 5:3f93dd1d4cb3 128 */
sam_grove 5:3f93dd1d4cb3 129 __STATIC_INLINE uint32_t __get_PSP(void)
sam_grove 5:3f93dd1d4cb3 130 {
sam_grove 5:3f93dd1d4cb3 131 register uint32_t __regProcessStackPointer __ASM("psp");
sam_grove 5:3f93dd1d4cb3 132 return(__regProcessStackPointer);
sam_grove 5:3f93dd1d4cb3 133 }
sam_grove 5:3f93dd1d4cb3 134
sam_grove 5:3f93dd1d4cb3 135
sam_grove 5:3f93dd1d4cb3 136 /** \brief Set Process Stack Pointer
sam_grove 5:3f93dd1d4cb3 137
sam_grove 5:3f93dd1d4cb3 138 This function assigns the given value to the Process Stack Pointer (PSP).
sam_grove 5:3f93dd1d4cb3 139
sam_grove 5:3f93dd1d4cb3 140 \param [in] topOfProcStack Process Stack Pointer value to set
sam_grove 5:3f93dd1d4cb3 141 */
sam_grove 5:3f93dd1d4cb3 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
sam_grove 5:3f93dd1d4cb3 143 {
sam_grove 5:3f93dd1d4cb3 144 register uint32_t __regProcessStackPointer __ASM("psp");
sam_grove 5:3f93dd1d4cb3 145 __regProcessStackPointer = topOfProcStack;
sam_grove 5:3f93dd1d4cb3 146 }
sam_grove 5:3f93dd1d4cb3 147
sam_grove 5:3f93dd1d4cb3 148
sam_grove 5:3f93dd1d4cb3 149 /** \brief Get Main Stack Pointer
sam_grove 5:3f93dd1d4cb3 150
sam_grove 5:3f93dd1d4cb3 151 This function returns the current value of the Main Stack Pointer (MSP).
sam_grove 5:3f93dd1d4cb3 152
sam_grove 5:3f93dd1d4cb3 153 \return MSP Register value
sam_grove 5:3f93dd1d4cb3 154 */
sam_grove 5:3f93dd1d4cb3 155 __STATIC_INLINE uint32_t __get_MSP(void)
sam_grove 5:3f93dd1d4cb3 156 {
sam_grove 5:3f93dd1d4cb3 157 register uint32_t __regMainStackPointer __ASM("msp");
sam_grove 5:3f93dd1d4cb3 158 return(__regMainStackPointer);
sam_grove 5:3f93dd1d4cb3 159 }
sam_grove 5:3f93dd1d4cb3 160
sam_grove 5:3f93dd1d4cb3 161
sam_grove 5:3f93dd1d4cb3 162 /** \brief Set Main Stack Pointer
sam_grove 5:3f93dd1d4cb3 163
sam_grove 5:3f93dd1d4cb3 164 This function assigns the given value to the Main Stack Pointer (MSP).
sam_grove 5:3f93dd1d4cb3 165
sam_grove 5:3f93dd1d4cb3 166 \param [in] topOfMainStack Main Stack Pointer value to set
sam_grove 5:3f93dd1d4cb3 167 */
sam_grove 5:3f93dd1d4cb3 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
sam_grove 5:3f93dd1d4cb3 169 {
sam_grove 5:3f93dd1d4cb3 170 register uint32_t __regMainStackPointer __ASM("msp");
sam_grove 5:3f93dd1d4cb3 171 __regMainStackPointer = topOfMainStack;
sam_grove 5:3f93dd1d4cb3 172 }
sam_grove 5:3f93dd1d4cb3 173
sam_grove 5:3f93dd1d4cb3 174
sam_grove 5:3f93dd1d4cb3 175 /** \brief Get Priority Mask
sam_grove 5:3f93dd1d4cb3 176
sam_grove 5:3f93dd1d4cb3 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
sam_grove 5:3f93dd1d4cb3 178
sam_grove 5:3f93dd1d4cb3 179 \return Priority Mask value
sam_grove 5:3f93dd1d4cb3 180 */
sam_grove 5:3f93dd1d4cb3 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
sam_grove 5:3f93dd1d4cb3 182 {
sam_grove 5:3f93dd1d4cb3 183 register uint32_t __regPriMask __ASM("primask");
sam_grove 5:3f93dd1d4cb3 184 return(__regPriMask);
sam_grove 5:3f93dd1d4cb3 185 }
sam_grove 5:3f93dd1d4cb3 186
sam_grove 5:3f93dd1d4cb3 187
sam_grove 5:3f93dd1d4cb3 188 /** \brief Set Priority Mask
sam_grove 5:3f93dd1d4cb3 189
sam_grove 5:3f93dd1d4cb3 190 This function assigns the given value to the Priority Mask Register.
sam_grove 5:3f93dd1d4cb3 191
sam_grove 5:3f93dd1d4cb3 192 \param [in] priMask Priority Mask
sam_grove 5:3f93dd1d4cb3 193 */
sam_grove 5:3f93dd1d4cb3 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
sam_grove 5:3f93dd1d4cb3 195 {
sam_grove 5:3f93dd1d4cb3 196 register uint32_t __regPriMask __ASM("primask");
sam_grove 5:3f93dd1d4cb3 197 __regPriMask = (priMask);
sam_grove 5:3f93dd1d4cb3 198 }
sam_grove 5:3f93dd1d4cb3 199
sam_grove 5:3f93dd1d4cb3 200
sam_grove 5:3f93dd1d4cb3 201 #if (__CORTEX_M >= 0x03)
sam_grove 5:3f93dd1d4cb3 202
sam_grove 5:3f93dd1d4cb3 203 /** \brief Enable FIQ
sam_grove 5:3f93dd1d4cb3 204
sam_grove 5:3f93dd1d4cb3 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
sam_grove 5:3f93dd1d4cb3 206 Can only be executed in Privileged modes.
sam_grove 5:3f93dd1d4cb3 207 */
sam_grove 5:3f93dd1d4cb3 208 #define __enable_fault_irq __enable_fiq
sam_grove 5:3f93dd1d4cb3 209
sam_grove 5:3f93dd1d4cb3 210
sam_grove 5:3f93dd1d4cb3 211 /** \brief Disable FIQ
sam_grove 5:3f93dd1d4cb3 212
sam_grove 5:3f93dd1d4cb3 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
sam_grove 5:3f93dd1d4cb3 214 Can only be executed in Privileged modes.
sam_grove 5:3f93dd1d4cb3 215 */
sam_grove 5:3f93dd1d4cb3 216 #define __disable_fault_irq __disable_fiq
sam_grove 5:3f93dd1d4cb3 217
sam_grove 5:3f93dd1d4cb3 218
sam_grove 5:3f93dd1d4cb3 219 /** \brief Get Base Priority
sam_grove 5:3f93dd1d4cb3 220
sam_grove 5:3f93dd1d4cb3 221 This function returns the current value of the Base Priority register.
sam_grove 5:3f93dd1d4cb3 222
sam_grove 5:3f93dd1d4cb3 223 \return Base Priority register value
sam_grove 5:3f93dd1d4cb3 224 */
sam_grove 5:3f93dd1d4cb3 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
sam_grove 5:3f93dd1d4cb3 226 {
sam_grove 5:3f93dd1d4cb3 227 register uint32_t __regBasePri __ASM("basepri");
sam_grove 5:3f93dd1d4cb3 228 return(__regBasePri);
sam_grove 5:3f93dd1d4cb3 229 }
sam_grove 5:3f93dd1d4cb3 230
sam_grove 5:3f93dd1d4cb3 231
sam_grove 5:3f93dd1d4cb3 232 /** \brief Set Base Priority
sam_grove 5:3f93dd1d4cb3 233
sam_grove 5:3f93dd1d4cb3 234 This function assigns the given value to the Base Priority register.
sam_grove 5:3f93dd1d4cb3 235
sam_grove 5:3f93dd1d4cb3 236 \param [in] basePri Base Priority value to set
sam_grove 5:3f93dd1d4cb3 237 */
sam_grove 5:3f93dd1d4cb3 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
sam_grove 5:3f93dd1d4cb3 239 {
sam_grove 5:3f93dd1d4cb3 240 register uint32_t __regBasePri __ASM("basepri");
sam_grove 5:3f93dd1d4cb3 241 __regBasePri = (basePri & 0xff);
sam_grove 5:3f93dd1d4cb3 242 }
sam_grove 5:3f93dd1d4cb3 243
sam_grove 5:3f93dd1d4cb3 244
sam_grove 5:3f93dd1d4cb3 245 /** \brief Get Fault Mask
sam_grove 5:3f93dd1d4cb3 246
sam_grove 5:3f93dd1d4cb3 247 This function returns the current value of the Fault Mask register.
sam_grove 5:3f93dd1d4cb3 248
sam_grove 5:3f93dd1d4cb3 249 \return Fault Mask register value
sam_grove 5:3f93dd1d4cb3 250 */
sam_grove 5:3f93dd1d4cb3 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
sam_grove 5:3f93dd1d4cb3 252 {
sam_grove 5:3f93dd1d4cb3 253 register uint32_t __regFaultMask __ASM("faultmask");
sam_grove 5:3f93dd1d4cb3 254 return(__regFaultMask);
sam_grove 5:3f93dd1d4cb3 255 }
sam_grove 5:3f93dd1d4cb3 256
sam_grove 5:3f93dd1d4cb3 257
sam_grove 5:3f93dd1d4cb3 258 /** \brief Set Fault Mask
sam_grove 5:3f93dd1d4cb3 259
sam_grove 5:3f93dd1d4cb3 260 This function assigns the given value to the Fault Mask register.
sam_grove 5:3f93dd1d4cb3 261
sam_grove 5:3f93dd1d4cb3 262 \param [in] faultMask Fault Mask value to set
sam_grove 5:3f93dd1d4cb3 263 */
sam_grove 5:3f93dd1d4cb3 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
sam_grove 5:3f93dd1d4cb3 265 {
sam_grove 5:3f93dd1d4cb3 266 register uint32_t __regFaultMask __ASM("faultmask");
sam_grove 5:3f93dd1d4cb3 267 __regFaultMask = (faultMask & (uint32_t)1);
sam_grove 5:3f93dd1d4cb3 268 }
sam_grove 5:3f93dd1d4cb3 269
sam_grove 5:3f93dd1d4cb3 270 #endif /* (__CORTEX_M >= 0x03) */
sam_grove 5:3f93dd1d4cb3 271
sam_grove 5:3f93dd1d4cb3 272
sam_grove 5:3f93dd1d4cb3 273 #if (__CORTEX_M == 0x04)
sam_grove 5:3f93dd1d4cb3 274
sam_grove 5:3f93dd1d4cb3 275 /** \brief Get FPSCR
sam_grove 5:3f93dd1d4cb3 276
sam_grove 5:3f93dd1d4cb3 277 This function returns the current value of the Floating Point Status/Control register.
sam_grove 5:3f93dd1d4cb3 278
sam_grove 5:3f93dd1d4cb3 279 \return Floating Point Status/Control register value
sam_grove 5:3f93dd1d4cb3 280 */
sam_grove 5:3f93dd1d4cb3 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
sam_grove 5:3f93dd1d4cb3 282 {
sam_grove 5:3f93dd1d4cb3 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sam_grove 5:3f93dd1d4cb3 284 register uint32_t __regfpscr __ASM("fpscr");
sam_grove 5:3f93dd1d4cb3 285 return(__regfpscr);
sam_grove 5:3f93dd1d4cb3 286 #else
sam_grove 5:3f93dd1d4cb3 287 return(0);
sam_grove 5:3f93dd1d4cb3 288 #endif
sam_grove 5:3f93dd1d4cb3 289 }
sam_grove 5:3f93dd1d4cb3 290
sam_grove 5:3f93dd1d4cb3 291
sam_grove 5:3f93dd1d4cb3 292 /** \brief Set FPSCR
sam_grove 5:3f93dd1d4cb3 293
sam_grove 5:3f93dd1d4cb3 294 This function assigns the given value to the Floating Point Status/Control register.
sam_grove 5:3f93dd1d4cb3 295
sam_grove 5:3f93dd1d4cb3 296 \param [in] fpscr Floating Point Status/Control value to set
sam_grove 5:3f93dd1d4cb3 297 */
sam_grove 5:3f93dd1d4cb3 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
sam_grove 5:3f93dd1d4cb3 299 {
sam_grove 5:3f93dd1d4cb3 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sam_grove 5:3f93dd1d4cb3 301 register uint32_t __regfpscr __ASM("fpscr");
sam_grove 5:3f93dd1d4cb3 302 __regfpscr = (fpscr);
sam_grove 5:3f93dd1d4cb3 303 #endif
sam_grove 5:3f93dd1d4cb3 304 }
sam_grove 5:3f93dd1d4cb3 305
sam_grove 5:3f93dd1d4cb3 306 #endif /* (__CORTEX_M == 0x04) */
sam_grove 5:3f93dd1d4cb3 307
sam_grove 5:3f93dd1d4cb3 308
sam_grove 5:3f93dd1d4cb3 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
sam_grove 5:3f93dd1d4cb3 310 /* IAR iccarm specific functions */
sam_grove 5:3f93dd1d4cb3 311
sam_grove 5:3f93dd1d4cb3 312 #include <cmsis_iar.h>
sam_grove 5:3f93dd1d4cb3 313
sam_grove 5:3f93dd1d4cb3 314
sam_grove 5:3f93dd1d4cb3 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
sam_grove 5:3f93dd1d4cb3 316 /* TI CCS specific functions */
sam_grove 5:3f93dd1d4cb3 317
sam_grove 5:3f93dd1d4cb3 318 #include <cmsis_ccs.h>
sam_grove 5:3f93dd1d4cb3 319
sam_grove 5:3f93dd1d4cb3 320
sam_grove 5:3f93dd1d4cb3 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
sam_grove 5:3f93dd1d4cb3 322 /* GNU gcc specific functions */
sam_grove 5:3f93dd1d4cb3 323
sam_grove 5:3f93dd1d4cb3 324 /** \brief Enable IRQ Interrupts
sam_grove 5:3f93dd1d4cb3 325
sam_grove 5:3f93dd1d4cb3 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
sam_grove 5:3f93dd1d4cb3 327 Can only be executed in Privileged modes.
sam_grove 5:3f93dd1d4cb3 328 */
sam_grove 5:3f93dd1d4cb3 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
sam_grove 5:3f93dd1d4cb3 330 {
sam_grove 5:3f93dd1d4cb3 331 __ASM volatile ("cpsie i" : : : "memory");
sam_grove 5:3f93dd1d4cb3 332 }
sam_grove 5:3f93dd1d4cb3 333
sam_grove 5:3f93dd1d4cb3 334
sam_grove 5:3f93dd1d4cb3 335 /** \brief Disable IRQ Interrupts
sam_grove 5:3f93dd1d4cb3 336
sam_grove 5:3f93dd1d4cb3 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
sam_grove 5:3f93dd1d4cb3 338 Can only be executed in Privileged modes.
sam_grove 5:3f93dd1d4cb3 339 */
sam_grove 5:3f93dd1d4cb3 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
sam_grove 5:3f93dd1d4cb3 341 {
sam_grove 5:3f93dd1d4cb3 342 __ASM volatile ("cpsid i" : : : "memory");
sam_grove 5:3f93dd1d4cb3 343 }
sam_grove 5:3f93dd1d4cb3 344
sam_grove 5:3f93dd1d4cb3 345
sam_grove 5:3f93dd1d4cb3 346 /** \brief Get Control Register
sam_grove 5:3f93dd1d4cb3 347
sam_grove 5:3f93dd1d4cb3 348 This function returns the content of the Control Register.
sam_grove 5:3f93dd1d4cb3 349
sam_grove 5:3f93dd1d4cb3 350 \return Control Register value
sam_grove 5:3f93dd1d4cb3 351 */
sam_grove 5:3f93dd1d4cb3 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
sam_grove 5:3f93dd1d4cb3 353 {
sam_grove 5:3f93dd1d4cb3 354 uint32_t result;
sam_grove 5:3f93dd1d4cb3 355
sam_grove 5:3f93dd1d4cb3 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 357 return(result);
sam_grove 5:3f93dd1d4cb3 358 }
sam_grove 5:3f93dd1d4cb3 359
sam_grove 5:3f93dd1d4cb3 360
sam_grove 5:3f93dd1d4cb3 361 /** \brief Set Control Register
sam_grove 5:3f93dd1d4cb3 362
sam_grove 5:3f93dd1d4cb3 363 This function writes the given value to the Control Register.
sam_grove 5:3f93dd1d4cb3 364
sam_grove 5:3f93dd1d4cb3 365 \param [in] control Control Register value to set
sam_grove 5:3f93dd1d4cb3 366 */
sam_grove 5:3f93dd1d4cb3 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
sam_grove 5:3f93dd1d4cb3 368 {
sam_grove 5:3f93dd1d4cb3 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
sam_grove 5:3f93dd1d4cb3 370 }
sam_grove 5:3f93dd1d4cb3 371
sam_grove 5:3f93dd1d4cb3 372
sam_grove 5:3f93dd1d4cb3 373 /** \brief Get IPSR Register
sam_grove 5:3f93dd1d4cb3 374
sam_grove 5:3f93dd1d4cb3 375 This function returns the content of the IPSR Register.
sam_grove 5:3f93dd1d4cb3 376
sam_grove 5:3f93dd1d4cb3 377 \return IPSR Register value
sam_grove 5:3f93dd1d4cb3 378 */
sam_grove 5:3f93dd1d4cb3 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
sam_grove 5:3f93dd1d4cb3 380 {
sam_grove 5:3f93dd1d4cb3 381 uint32_t result;
sam_grove 5:3f93dd1d4cb3 382
sam_grove 5:3f93dd1d4cb3 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 384 return(result);
sam_grove 5:3f93dd1d4cb3 385 }
sam_grove 5:3f93dd1d4cb3 386
sam_grove 5:3f93dd1d4cb3 387
sam_grove 5:3f93dd1d4cb3 388 /** \brief Get APSR Register
sam_grove 5:3f93dd1d4cb3 389
sam_grove 5:3f93dd1d4cb3 390 This function returns the content of the APSR Register.
sam_grove 5:3f93dd1d4cb3 391
sam_grove 5:3f93dd1d4cb3 392 \return APSR Register value
sam_grove 5:3f93dd1d4cb3 393 */
sam_grove 5:3f93dd1d4cb3 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
sam_grove 5:3f93dd1d4cb3 395 {
sam_grove 5:3f93dd1d4cb3 396 uint32_t result;
sam_grove 5:3f93dd1d4cb3 397
sam_grove 5:3f93dd1d4cb3 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 399 return(result);
sam_grove 5:3f93dd1d4cb3 400 }
sam_grove 5:3f93dd1d4cb3 401
sam_grove 5:3f93dd1d4cb3 402
sam_grove 5:3f93dd1d4cb3 403 /** \brief Get xPSR Register
sam_grove 5:3f93dd1d4cb3 404
sam_grove 5:3f93dd1d4cb3 405 This function returns the content of the xPSR Register.
sam_grove 5:3f93dd1d4cb3 406
sam_grove 5:3f93dd1d4cb3 407 \return xPSR Register value
sam_grove 5:3f93dd1d4cb3 408 */
sam_grove 5:3f93dd1d4cb3 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
sam_grove 5:3f93dd1d4cb3 410 {
sam_grove 5:3f93dd1d4cb3 411 uint32_t result;
sam_grove 5:3f93dd1d4cb3 412
sam_grove 5:3f93dd1d4cb3 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 414 return(result);
sam_grove 5:3f93dd1d4cb3 415 }
sam_grove 5:3f93dd1d4cb3 416
sam_grove 5:3f93dd1d4cb3 417
sam_grove 5:3f93dd1d4cb3 418 /** \brief Get Process Stack Pointer
sam_grove 5:3f93dd1d4cb3 419
sam_grove 5:3f93dd1d4cb3 420 This function returns the current value of the Process Stack Pointer (PSP).
sam_grove 5:3f93dd1d4cb3 421
sam_grove 5:3f93dd1d4cb3 422 \return PSP Register value
sam_grove 5:3f93dd1d4cb3 423 */
sam_grove 5:3f93dd1d4cb3 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
sam_grove 5:3f93dd1d4cb3 425 {
sam_grove 5:3f93dd1d4cb3 426 register uint32_t result;
sam_grove 5:3f93dd1d4cb3 427
sam_grove 5:3f93dd1d4cb3 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 429 return(result);
sam_grove 5:3f93dd1d4cb3 430 }
sam_grove 5:3f93dd1d4cb3 431
sam_grove 5:3f93dd1d4cb3 432
sam_grove 5:3f93dd1d4cb3 433 /** \brief Set Process Stack Pointer
sam_grove 5:3f93dd1d4cb3 434
sam_grove 5:3f93dd1d4cb3 435 This function assigns the given value to the Process Stack Pointer (PSP).
sam_grove 5:3f93dd1d4cb3 436
sam_grove 5:3f93dd1d4cb3 437 \param [in] topOfProcStack Process Stack Pointer value to set
sam_grove 5:3f93dd1d4cb3 438 */
sam_grove 5:3f93dd1d4cb3 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
sam_grove 5:3f93dd1d4cb3 440 {
sam_grove 5:3f93dd1d4cb3 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
sam_grove 5:3f93dd1d4cb3 442 }
sam_grove 5:3f93dd1d4cb3 443
sam_grove 5:3f93dd1d4cb3 444
sam_grove 5:3f93dd1d4cb3 445 /** \brief Get Main Stack Pointer
sam_grove 5:3f93dd1d4cb3 446
sam_grove 5:3f93dd1d4cb3 447 This function returns the current value of the Main Stack Pointer (MSP).
sam_grove 5:3f93dd1d4cb3 448
sam_grove 5:3f93dd1d4cb3 449 \return MSP Register value
sam_grove 5:3f93dd1d4cb3 450 */
sam_grove 5:3f93dd1d4cb3 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
sam_grove 5:3f93dd1d4cb3 452 {
sam_grove 5:3f93dd1d4cb3 453 register uint32_t result;
sam_grove 5:3f93dd1d4cb3 454
sam_grove 5:3f93dd1d4cb3 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 456 return(result);
sam_grove 5:3f93dd1d4cb3 457 }
sam_grove 5:3f93dd1d4cb3 458
sam_grove 5:3f93dd1d4cb3 459
sam_grove 5:3f93dd1d4cb3 460 /** \brief Set Main Stack Pointer
sam_grove 5:3f93dd1d4cb3 461
sam_grove 5:3f93dd1d4cb3 462 This function assigns the given value to the Main Stack Pointer (MSP).
sam_grove 5:3f93dd1d4cb3 463
sam_grove 5:3f93dd1d4cb3 464 \param [in] topOfMainStack Main Stack Pointer value to set
sam_grove 5:3f93dd1d4cb3 465 */
sam_grove 5:3f93dd1d4cb3 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
sam_grove 5:3f93dd1d4cb3 467 {
sam_grove 5:3f93dd1d4cb3 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
sam_grove 5:3f93dd1d4cb3 469 }
sam_grove 5:3f93dd1d4cb3 470
sam_grove 5:3f93dd1d4cb3 471
sam_grove 5:3f93dd1d4cb3 472 /** \brief Get Priority Mask
sam_grove 5:3f93dd1d4cb3 473
sam_grove 5:3f93dd1d4cb3 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
sam_grove 5:3f93dd1d4cb3 475
sam_grove 5:3f93dd1d4cb3 476 \return Priority Mask value
sam_grove 5:3f93dd1d4cb3 477 */
sam_grove 5:3f93dd1d4cb3 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
sam_grove 5:3f93dd1d4cb3 479 {
sam_grove 5:3f93dd1d4cb3 480 uint32_t result;
sam_grove 5:3f93dd1d4cb3 481
sam_grove 5:3f93dd1d4cb3 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 483 return(result);
sam_grove 5:3f93dd1d4cb3 484 }
sam_grove 5:3f93dd1d4cb3 485
sam_grove 5:3f93dd1d4cb3 486
sam_grove 5:3f93dd1d4cb3 487 /** \brief Set Priority Mask
sam_grove 5:3f93dd1d4cb3 488
sam_grove 5:3f93dd1d4cb3 489 This function assigns the given value to the Priority Mask Register.
sam_grove 5:3f93dd1d4cb3 490
sam_grove 5:3f93dd1d4cb3 491 \param [in] priMask Priority Mask
sam_grove 5:3f93dd1d4cb3 492 */
sam_grove 5:3f93dd1d4cb3 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
sam_grove 5:3f93dd1d4cb3 494 {
sam_grove 5:3f93dd1d4cb3 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
sam_grove 5:3f93dd1d4cb3 496 }
sam_grove 5:3f93dd1d4cb3 497
sam_grove 5:3f93dd1d4cb3 498
sam_grove 5:3f93dd1d4cb3 499 #if (__CORTEX_M >= 0x03)
sam_grove 5:3f93dd1d4cb3 500
sam_grove 5:3f93dd1d4cb3 501 /** \brief Enable FIQ
sam_grove 5:3f93dd1d4cb3 502
sam_grove 5:3f93dd1d4cb3 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
sam_grove 5:3f93dd1d4cb3 504 Can only be executed in Privileged modes.
sam_grove 5:3f93dd1d4cb3 505 */
sam_grove 5:3f93dd1d4cb3 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
sam_grove 5:3f93dd1d4cb3 507 {
sam_grove 5:3f93dd1d4cb3 508 __ASM volatile ("cpsie f" : : : "memory");
sam_grove 5:3f93dd1d4cb3 509 }
sam_grove 5:3f93dd1d4cb3 510
sam_grove 5:3f93dd1d4cb3 511
sam_grove 5:3f93dd1d4cb3 512 /** \brief Disable FIQ
sam_grove 5:3f93dd1d4cb3 513
sam_grove 5:3f93dd1d4cb3 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
sam_grove 5:3f93dd1d4cb3 515 Can only be executed in Privileged modes.
sam_grove 5:3f93dd1d4cb3 516 */
sam_grove 5:3f93dd1d4cb3 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
sam_grove 5:3f93dd1d4cb3 518 {
sam_grove 5:3f93dd1d4cb3 519 __ASM volatile ("cpsid f" : : : "memory");
sam_grove 5:3f93dd1d4cb3 520 }
sam_grove 5:3f93dd1d4cb3 521
sam_grove 5:3f93dd1d4cb3 522
sam_grove 5:3f93dd1d4cb3 523 /** \brief Get Base Priority
sam_grove 5:3f93dd1d4cb3 524
sam_grove 5:3f93dd1d4cb3 525 This function returns the current value of the Base Priority register.
sam_grove 5:3f93dd1d4cb3 526
sam_grove 5:3f93dd1d4cb3 527 \return Base Priority register value
sam_grove 5:3f93dd1d4cb3 528 */
sam_grove 5:3f93dd1d4cb3 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
sam_grove 5:3f93dd1d4cb3 530 {
sam_grove 5:3f93dd1d4cb3 531 uint32_t result;
sam_grove 5:3f93dd1d4cb3 532
sam_grove 5:3f93dd1d4cb3 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 534 return(result);
sam_grove 5:3f93dd1d4cb3 535 }
sam_grove 5:3f93dd1d4cb3 536
sam_grove 5:3f93dd1d4cb3 537
sam_grove 5:3f93dd1d4cb3 538 /** \brief Set Base Priority
sam_grove 5:3f93dd1d4cb3 539
sam_grove 5:3f93dd1d4cb3 540 This function assigns the given value to the Base Priority register.
sam_grove 5:3f93dd1d4cb3 541
sam_grove 5:3f93dd1d4cb3 542 \param [in] basePri Base Priority value to set
sam_grove 5:3f93dd1d4cb3 543 */
sam_grove 5:3f93dd1d4cb3 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
sam_grove 5:3f93dd1d4cb3 545 {
sam_grove 5:3f93dd1d4cb3 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
sam_grove 5:3f93dd1d4cb3 547 }
sam_grove 5:3f93dd1d4cb3 548
sam_grove 5:3f93dd1d4cb3 549
sam_grove 5:3f93dd1d4cb3 550 /** \brief Get Fault Mask
sam_grove 5:3f93dd1d4cb3 551
sam_grove 5:3f93dd1d4cb3 552 This function returns the current value of the Fault Mask register.
sam_grove 5:3f93dd1d4cb3 553
sam_grove 5:3f93dd1d4cb3 554 \return Fault Mask register value
sam_grove 5:3f93dd1d4cb3 555 */
sam_grove 5:3f93dd1d4cb3 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
sam_grove 5:3f93dd1d4cb3 557 {
sam_grove 5:3f93dd1d4cb3 558 uint32_t result;
sam_grove 5:3f93dd1d4cb3 559
sam_grove 5:3f93dd1d4cb3 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 561 return(result);
sam_grove 5:3f93dd1d4cb3 562 }
sam_grove 5:3f93dd1d4cb3 563
sam_grove 5:3f93dd1d4cb3 564
sam_grove 5:3f93dd1d4cb3 565 /** \brief Set Fault Mask
sam_grove 5:3f93dd1d4cb3 566
sam_grove 5:3f93dd1d4cb3 567 This function assigns the given value to the Fault Mask register.
sam_grove 5:3f93dd1d4cb3 568
sam_grove 5:3f93dd1d4cb3 569 \param [in] faultMask Fault Mask value to set
sam_grove 5:3f93dd1d4cb3 570 */
sam_grove 5:3f93dd1d4cb3 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
sam_grove 5:3f93dd1d4cb3 572 {
sam_grove 5:3f93dd1d4cb3 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
sam_grove 5:3f93dd1d4cb3 574 }
sam_grove 5:3f93dd1d4cb3 575
sam_grove 5:3f93dd1d4cb3 576 #endif /* (__CORTEX_M >= 0x03) */
sam_grove 5:3f93dd1d4cb3 577
sam_grove 5:3f93dd1d4cb3 578
sam_grove 5:3f93dd1d4cb3 579 #if (__CORTEX_M == 0x04)
sam_grove 5:3f93dd1d4cb3 580
sam_grove 5:3f93dd1d4cb3 581 /** \brief Get FPSCR
sam_grove 5:3f93dd1d4cb3 582
sam_grove 5:3f93dd1d4cb3 583 This function returns the current value of the Floating Point Status/Control register.
sam_grove 5:3f93dd1d4cb3 584
sam_grove 5:3f93dd1d4cb3 585 \return Floating Point Status/Control register value
sam_grove 5:3f93dd1d4cb3 586 */
sam_grove 5:3f93dd1d4cb3 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
sam_grove 5:3f93dd1d4cb3 588 {
sam_grove 5:3f93dd1d4cb3 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sam_grove 5:3f93dd1d4cb3 590 uint32_t result;
sam_grove 5:3f93dd1d4cb3 591
sam_grove 5:3f93dd1d4cb3 592 /* Empty asm statement works as a scheduling barrier */
sam_grove 5:3f93dd1d4cb3 593 __ASM volatile ("");
sam_grove 5:3f93dd1d4cb3 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
sam_grove 5:3f93dd1d4cb3 595 __ASM volatile ("");
sam_grove 5:3f93dd1d4cb3 596 return(result);
sam_grove 5:3f93dd1d4cb3 597 #else
sam_grove 5:3f93dd1d4cb3 598 return(0);
sam_grove 5:3f93dd1d4cb3 599 #endif
sam_grove 5:3f93dd1d4cb3 600 }
sam_grove 5:3f93dd1d4cb3 601
sam_grove 5:3f93dd1d4cb3 602
sam_grove 5:3f93dd1d4cb3 603 /** \brief Set FPSCR
sam_grove 5:3f93dd1d4cb3 604
sam_grove 5:3f93dd1d4cb3 605 This function assigns the given value to the Floating Point Status/Control register.
sam_grove 5:3f93dd1d4cb3 606
sam_grove 5:3f93dd1d4cb3 607 \param [in] fpscr Floating Point Status/Control value to set
sam_grove 5:3f93dd1d4cb3 608 */
sam_grove 5:3f93dd1d4cb3 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
sam_grove 5:3f93dd1d4cb3 610 {
sam_grove 5:3f93dd1d4cb3 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sam_grove 5:3f93dd1d4cb3 612 /* Empty asm statement works as a scheduling barrier */
sam_grove 5:3f93dd1d4cb3 613 __ASM volatile ("");
sam_grove 5:3f93dd1d4cb3 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
sam_grove 5:3f93dd1d4cb3 615 __ASM volatile ("");
sam_grove 5:3f93dd1d4cb3 616 #endif
sam_grove 5:3f93dd1d4cb3 617 }
sam_grove 5:3f93dd1d4cb3 618
sam_grove 5:3f93dd1d4cb3 619 #endif /* (__CORTEX_M == 0x04) */
sam_grove 5:3f93dd1d4cb3 620
sam_grove 5:3f93dd1d4cb3 621
sam_grove 5:3f93dd1d4cb3 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
sam_grove 5:3f93dd1d4cb3 623 /* TASKING carm specific functions */
sam_grove 5:3f93dd1d4cb3 624
sam_grove 5:3f93dd1d4cb3 625 /*
sam_grove 5:3f93dd1d4cb3 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
sam_grove 5:3f93dd1d4cb3 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
sam_grove 5:3f93dd1d4cb3 628 * Including the CMSIS ones.
sam_grove 5:3f93dd1d4cb3 629 */
sam_grove 5:3f93dd1d4cb3 630
sam_grove 5:3f93dd1d4cb3 631 #endif
sam_grove 5:3f93dd1d4cb3 632
sam_grove 5:3f93dd1d4cb3 633 /*@} end of CMSIS_Core_RegAccFunctions */
sam_grove 5:3f93dd1d4cb3 634
sam_grove 5:3f93dd1d4cb3 635
sam_grove 5:3f93dd1d4cb3 636 #endif /* __CORE_CMFUNC_H */