Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/cmsis/core_cm4_simd.h@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /**************************************************************************//**
sam_grove 5:3f93dd1d4cb3 2 * @file core_cm4_simd.h
sam_grove 5:3f93dd1d4cb3 3 * @brief CMSIS Cortex-M4 SIMD Header File
sam_grove 5:3f93dd1d4cb3 4 * @version V3.20
sam_grove 5:3f93dd1d4cb3 5 * @date 25. February 2013
sam_grove 5:3f93dd1d4cb3 6 *
sam_grove 5:3f93dd1d4cb3 7 * @note
sam_grove 5:3f93dd1d4cb3 8 *
sam_grove 5:3f93dd1d4cb3 9 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
sam_grove 5:3f93dd1d4cb3 11
sam_grove 5:3f93dd1d4cb3 12 All rights reserved.
sam_grove 5:3f93dd1d4cb3 13 Redistribution and use in source and binary forms, with or without
sam_grove 5:3f93dd1d4cb3 14 modification, are permitted provided that the following conditions are met:
sam_grove 5:3f93dd1d4cb3 15 - Redistributions of source code must retain the above copyright
sam_grove 5:3f93dd1d4cb3 16 notice, this list of conditions and the following disclaimer.
sam_grove 5:3f93dd1d4cb3 17 - Redistributions in binary form must reproduce the above copyright
sam_grove 5:3f93dd1d4cb3 18 notice, this list of conditions and the following disclaimer in the
sam_grove 5:3f93dd1d4cb3 19 documentation and/or other materials provided with the distribution.
sam_grove 5:3f93dd1d4cb3 20 - Neither the name of ARM nor the names of its contributors may be used
sam_grove 5:3f93dd1d4cb3 21 to endorse or promote products derived from this software without
sam_grove 5:3f93dd1d4cb3 22 specific prior written permission.
sam_grove 5:3f93dd1d4cb3 23 *
sam_grove 5:3f93dd1d4cb3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sam_grove 5:3f93dd1d4cb3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sam_grove 5:3f93dd1d4cb3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sam_grove 5:3f93dd1d4cb3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sam_grove 5:3f93dd1d4cb3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sam_grove 5:3f93dd1d4cb3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sam_grove 5:3f93dd1d4cb3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sam_grove 5:3f93dd1d4cb3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sam_grove 5:3f93dd1d4cb3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sam_grove 5:3f93dd1d4cb3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sam_grove 5:3f93dd1d4cb3 34 POSSIBILITY OF SUCH DAMAGE.
sam_grove 5:3f93dd1d4cb3 35 ---------------------------------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 36
sam_grove 5:3f93dd1d4cb3 37
sam_grove 5:3f93dd1d4cb3 38 #ifdef __cplusplus
sam_grove 5:3f93dd1d4cb3 39 extern "C" {
sam_grove 5:3f93dd1d4cb3 40 #endif
sam_grove 5:3f93dd1d4cb3 41
sam_grove 5:3f93dd1d4cb3 42 #ifndef __CORE_CM4_SIMD_H
sam_grove 5:3f93dd1d4cb3 43 #define __CORE_CM4_SIMD_H
sam_grove 5:3f93dd1d4cb3 44
sam_grove 5:3f93dd1d4cb3 45
sam_grove 5:3f93dd1d4cb3 46 /*******************************************************************************
sam_grove 5:3f93dd1d4cb3 47 * Hardware Abstraction Layer
sam_grove 5:3f93dd1d4cb3 48 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 49
sam_grove 5:3f93dd1d4cb3 50
sam_grove 5:3f93dd1d4cb3 51 /* ################### Compiler specific Intrinsics ########################### */
sam_grove 5:3f93dd1d4cb3 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
sam_grove 5:3f93dd1d4cb3 53 Access to dedicated SIMD instructions
sam_grove 5:3f93dd1d4cb3 54 @{
sam_grove 5:3f93dd1d4cb3 55 */
sam_grove 5:3f93dd1d4cb3 56
sam_grove 5:3f93dd1d4cb3 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
sam_grove 5:3f93dd1d4cb3 58 /* ARM armcc specific functions */
sam_grove 5:3f93dd1d4cb3 59
sam_grove 5:3f93dd1d4cb3 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 61 #define __SADD8 __sadd8
sam_grove 5:3f93dd1d4cb3 62 #define __QADD8 __qadd8
sam_grove 5:3f93dd1d4cb3 63 #define __SHADD8 __shadd8
sam_grove 5:3f93dd1d4cb3 64 #define __UADD8 __uadd8
sam_grove 5:3f93dd1d4cb3 65 #define __UQADD8 __uqadd8
sam_grove 5:3f93dd1d4cb3 66 #define __UHADD8 __uhadd8
sam_grove 5:3f93dd1d4cb3 67 #define __SSUB8 __ssub8
sam_grove 5:3f93dd1d4cb3 68 #define __QSUB8 __qsub8
sam_grove 5:3f93dd1d4cb3 69 #define __SHSUB8 __shsub8
sam_grove 5:3f93dd1d4cb3 70 #define __USUB8 __usub8
sam_grove 5:3f93dd1d4cb3 71 #define __UQSUB8 __uqsub8
sam_grove 5:3f93dd1d4cb3 72 #define __UHSUB8 __uhsub8
sam_grove 5:3f93dd1d4cb3 73 #define __SADD16 __sadd16
sam_grove 5:3f93dd1d4cb3 74 #define __QADD16 __qadd16
sam_grove 5:3f93dd1d4cb3 75 #define __SHADD16 __shadd16
sam_grove 5:3f93dd1d4cb3 76 #define __UADD16 __uadd16
sam_grove 5:3f93dd1d4cb3 77 #define __UQADD16 __uqadd16
sam_grove 5:3f93dd1d4cb3 78 #define __UHADD16 __uhadd16
sam_grove 5:3f93dd1d4cb3 79 #define __SSUB16 __ssub16
sam_grove 5:3f93dd1d4cb3 80 #define __QSUB16 __qsub16
sam_grove 5:3f93dd1d4cb3 81 #define __SHSUB16 __shsub16
sam_grove 5:3f93dd1d4cb3 82 #define __USUB16 __usub16
sam_grove 5:3f93dd1d4cb3 83 #define __UQSUB16 __uqsub16
sam_grove 5:3f93dd1d4cb3 84 #define __UHSUB16 __uhsub16
sam_grove 5:3f93dd1d4cb3 85 #define __SASX __sasx
sam_grove 5:3f93dd1d4cb3 86 #define __QASX __qasx
sam_grove 5:3f93dd1d4cb3 87 #define __SHASX __shasx
sam_grove 5:3f93dd1d4cb3 88 #define __UASX __uasx
sam_grove 5:3f93dd1d4cb3 89 #define __UQASX __uqasx
sam_grove 5:3f93dd1d4cb3 90 #define __UHASX __uhasx
sam_grove 5:3f93dd1d4cb3 91 #define __SSAX __ssax
sam_grove 5:3f93dd1d4cb3 92 #define __QSAX __qsax
sam_grove 5:3f93dd1d4cb3 93 #define __SHSAX __shsax
sam_grove 5:3f93dd1d4cb3 94 #define __USAX __usax
sam_grove 5:3f93dd1d4cb3 95 #define __UQSAX __uqsax
sam_grove 5:3f93dd1d4cb3 96 #define __UHSAX __uhsax
sam_grove 5:3f93dd1d4cb3 97 #define __USAD8 __usad8
sam_grove 5:3f93dd1d4cb3 98 #define __USADA8 __usada8
sam_grove 5:3f93dd1d4cb3 99 #define __SSAT16 __ssat16
sam_grove 5:3f93dd1d4cb3 100 #define __USAT16 __usat16
sam_grove 5:3f93dd1d4cb3 101 #define __UXTB16 __uxtb16
sam_grove 5:3f93dd1d4cb3 102 #define __UXTAB16 __uxtab16
sam_grove 5:3f93dd1d4cb3 103 #define __SXTB16 __sxtb16
sam_grove 5:3f93dd1d4cb3 104 #define __SXTAB16 __sxtab16
sam_grove 5:3f93dd1d4cb3 105 #define __SMUAD __smuad
sam_grove 5:3f93dd1d4cb3 106 #define __SMUADX __smuadx
sam_grove 5:3f93dd1d4cb3 107 #define __SMLAD __smlad
sam_grove 5:3f93dd1d4cb3 108 #define __SMLADX __smladx
sam_grove 5:3f93dd1d4cb3 109 #define __SMLALD __smlald
sam_grove 5:3f93dd1d4cb3 110 #define __SMLALDX __smlaldx
sam_grove 5:3f93dd1d4cb3 111 #define __SMUSD __smusd
sam_grove 5:3f93dd1d4cb3 112 #define __SMUSDX __smusdx
sam_grove 5:3f93dd1d4cb3 113 #define __SMLSD __smlsd
sam_grove 5:3f93dd1d4cb3 114 #define __SMLSDX __smlsdx
sam_grove 5:3f93dd1d4cb3 115 #define __SMLSLD __smlsld
sam_grove 5:3f93dd1d4cb3 116 #define __SMLSLDX __smlsldx
sam_grove 5:3f93dd1d4cb3 117 #define __SEL __sel
sam_grove 5:3f93dd1d4cb3 118 #define __QADD __qadd
sam_grove 5:3f93dd1d4cb3 119 #define __QSUB __qsub
sam_grove 5:3f93dd1d4cb3 120
sam_grove 5:3f93dd1d4cb3 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
sam_grove 5:3f93dd1d4cb3 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
sam_grove 5:3f93dd1d4cb3 123
sam_grove 5:3f93dd1d4cb3 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
sam_grove 5:3f93dd1d4cb3 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
sam_grove 5:3f93dd1d4cb3 126
sam_grove 5:3f93dd1d4cb3 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
sam_grove 5:3f93dd1d4cb3 128 ((int64_t)(ARG3) << 32) ) >> 32))
sam_grove 5:3f93dd1d4cb3 129
sam_grove 5:3f93dd1d4cb3 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 131
sam_grove 5:3f93dd1d4cb3 132
sam_grove 5:3f93dd1d4cb3 133
sam_grove 5:3f93dd1d4cb3 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
sam_grove 5:3f93dd1d4cb3 135 /* IAR iccarm specific functions */
sam_grove 5:3f93dd1d4cb3 136
sam_grove 5:3f93dd1d4cb3 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 138 #include <cmsis_iar.h>
sam_grove 5:3f93dd1d4cb3 139
sam_grove 5:3f93dd1d4cb3 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 141
sam_grove 5:3f93dd1d4cb3 142
sam_grove 5:3f93dd1d4cb3 143
sam_grove 5:3f93dd1d4cb3 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
sam_grove 5:3f93dd1d4cb3 145 /* TI CCS specific functions */
sam_grove 5:3f93dd1d4cb3 146
sam_grove 5:3f93dd1d4cb3 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 148 #include <cmsis_ccs.h>
sam_grove 5:3f93dd1d4cb3 149
sam_grove 5:3f93dd1d4cb3 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 151
sam_grove 5:3f93dd1d4cb3 152
sam_grove 5:3f93dd1d4cb3 153
sam_grove 5:3f93dd1d4cb3 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
sam_grove 5:3f93dd1d4cb3 155 /* GNU gcc specific functions */
sam_grove 5:3f93dd1d4cb3 156
sam_grove 5:3f93dd1d4cb3 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 159 {
sam_grove 5:3f93dd1d4cb3 160 uint32_t result;
sam_grove 5:3f93dd1d4cb3 161
sam_grove 5:3f93dd1d4cb3 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 163 return(result);
sam_grove 5:3f93dd1d4cb3 164 }
sam_grove 5:3f93dd1d4cb3 165
sam_grove 5:3f93dd1d4cb3 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 167 {
sam_grove 5:3f93dd1d4cb3 168 uint32_t result;
sam_grove 5:3f93dd1d4cb3 169
sam_grove 5:3f93dd1d4cb3 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 171 return(result);
sam_grove 5:3f93dd1d4cb3 172 }
sam_grove 5:3f93dd1d4cb3 173
sam_grove 5:3f93dd1d4cb3 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 175 {
sam_grove 5:3f93dd1d4cb3 176 uint32_t result;
sam_grove 5:3f93dd1d4cb3 177
sam_grove 5:3f93dd1d4cb3 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 179 return(result);
sam_grove 5:3f93dd1d4cb3 180 }
sam_grove 5:3f93dd1d4cb3 181
sam_grove 5:3f93dd1d4cb3 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 183 {
sam_grove 5:3f93dd1d4cb3 184 uint32_t result;
sam_grove 5:3f93dd1d4cb3 185
sam_grove 5:3f93dd1d4cb3 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 187 return(result);
sam_grove 5:3f93dd1d4cb3 188 }
sam_grove 5:3f93dd1d4cb3 189
sam_grove 5:3f93dd1d4cb3 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 191 {
sam_grove 5:3f93dd1d4cb3 192 uint32_t result;
sam_grove 5:3f93dd1d4cb3 193
sam_grove 5:3f93dd1d4cb3 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 195 return(result);
sam_grove 5:3f93dd1d4cb3 196 }
sam_grove 5:3f93dd1d4cb3 197
sam_grove 5:3f93dd1d4cb3 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 199 {
sam_grove 5:3f93dd1d4cb3 200 uint32_t result;
sam_grove 5:3f93dd1d4cb3 201
sam_grove 5:3f93dd1d4cb3 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 203 return(result);
sam_grove 5:3f93dd1d4cb3 204 }
sam_grove 5:3f93dd1d4cb3 205
sam_grove 5:3f93dd1d4cb3 206
sam_grove 5:3f93dd1d4cb3 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 208 {
sam_grove 5:3f93dd1d4cb3 209 uint32_t result;
sam_grove 5:3f93dd1d4cb3 210
sam_grove 5:3f93dd1d4cb3 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 212 return(result);
sam_grove 5:3f93dd1d4cb3 213 }
sam_grove 5:3f93dd1d4cb3 214
sam_grove 5:3f93dd1d4cb3 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 216 {
sam_grove 5:3f93dd1d4cb3 217 uint32_t result;
sam_grove 5:3f93dd1d4cb3 218
sam_grove 5:3f93dd1d4cb3 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 220 return(result);
sam_grove 5:3f93dd1d4cb3 221 }
sam_grove 5:3f93dd1d4cb3 222
sam_grove 5:3f93dd1d4cb3 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 224 {
sam_grove 5:3f93dd1d4cb3 225 uint32_t result;
sam_grove 5:3f93dd1d4cb3 226
sam_grove 5:3f93dd1d4cb3 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 228 return(result);
sam_grove 5:3f93dd1d4cb3 229 }
sam_grove 5:3f93dd1d4cb3 230
sam_grove 5:3f93dd1d4cb3 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 232 {
sam_grove 5:3f93dd1d4cb3 233 uint32_t result;
sam_grove 5:3f93dd1d4cb3 234
sam_grove 5:3f93dd1d4cb3 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 236 return(result);
sam_grove 5:3f93dd1d4cb3 237 }
sam_grove 5:3f93dd1d4cb3 238
sam_grove 5:3f93dd1d4cb3 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 240 {
sam_grove 5:3f93dd1d4cb3 241 uint32_t result;
sam_grove 5:3f93dd1d4cb3 242
sam_grove 5:3f93dd1d4cb3 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 244 return(result);
sam_grove 5:3f93dd1d4cb3 245 }
sam_grove 5:3f93dd1d4cb3 246
sam_grove 5:3f93dd1d4cb3 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 248 {
sam_grove 5:3f93dd1d4cb3 249 uint32_t result;
sam_grove 5:3f93dd1d4cb3 250
sam_grove 5:3f93dd1d4cb3 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 252 return(result);
sam_grove 5:3f93dd1d4cb3 253 }
sam_grove 5:3f93dd1d4cb3 254
sam_grove 5:3f93dd1d4cb3 255
sam_grove 5:3f93dd1d4cb3 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 257 {
sam_grove 5:3f93dd1d4cb3 258 uint32_t result;
sam_grove 5:3f93dd1d4cb3 259
sam_grove 5:3f93dd1d4cb3 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 261 return(result);
sam_grove 5:3f93dd1d4cb3 262 }
sam_grove 5:3f93dd1d4cb3 263
sam_grove 5:3f93dd1d4cb3 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 265 {
sam_grove 5:3f93dd1d4cb3 266 uint32_t result;
sam_grove 5:3f93dd1d4cb3 267
sam_grove 5:3f93dd1d4cb3 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 269 return(result);
sam_grove 5:3f93dd1d4cb3 270 }
sam_grove 5:3f93dd1d4cb3 271
sam_grove 5:3f93dd1d4cb3 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 273 {
sam_grove 5:3f93dd1d4cb3 274 uint32_t result;
sam_grove 5:3f93dd1d4cb3 275
sam_grove 5:3f93dd1d4cb3 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 277 return(result);
sam_grove 5:3f93dd1d4cb3 278 }
sam_grove 5:3f93dd1d4cb3 279
sam_grove 5:3f93dd1d4cb3 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 281 {
sam_grove 5:3f93dd1d4cb3 282 uint32_t result;
sam_grove 5:3f93dd1d4cb3 283
sam_grove 5:3f93dd1d4cb3 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 285 return(result);
sam_grove 5:3f93dd1d4cb3 286 }
sam_grove 5:3f93dd1d4cb3 287
sam_grove 5:3f93dd1d4cb3 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 289 {
sam_grove 5:3f93dd1d4cb3 290 uint32_t result;
sam_grove 5:3f93dd1d4cb3 291
sam_grove 5:3f93dd1d4cb3 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 293 return(result);
sam_grove 5:3f93dd1d4cb3 294 }
sam_grove 5:3f93dd1d4cb3 295
sam_grove 5:3f93dd1d4cb3 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 297 {
sam_grove 5:3f93dd1d4cb3 298 uint32_t result;
sam_grove 5:3f93dd1d4cb3 299
sam_grove 5:3f93dd1d4cb3 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 301 return(result);
sam_grove 5:3f93dd1d4cb3 302 }
sam_grove 5:3f93dd1d4cb3 303
sam_grove 5:3f93dd1d4cb3 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 305 {
sam_grove 5:3f93dd1d4cb3 306 uint32_t result;
sam_grove 5:3f93dd1d4cb3 307
sam_grove 5:3f93dd1d4cb3 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 309 return(result);
sam_grove 5:3f93dd1d4cb3 310 }
sam_grove 5:3f93dd1d4cb3 311
sam_grove 5:3f93dd1d4cb3 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 313 {
sam_grove 5:3f93dd1d4cb3 314 uint32_t result;
sam_grove 5:3f93dd1d4cb3 315
sam_grove 5:3f93dd1d4cb3 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 317 return(result);
sam_grove 5:3f93dd1d4cb3 318 }
sam_grove 5:3f93dd1d4cb3 319
sam_grove 5:3f93dd1d4cb3 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 321 {
sam_grove 5:3f93dd1d4cb3 322 uint32_t result;
sam_grove 5:3f93dd1d4cb3 323
sam_grove 5:3f93dd1d4cb3 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 325 return(result);
sam_grove 5:3f93dd1d4cb3 326 }
sam_grove 5:3f93dd1d4cb3 327
sam_grove 5:3f93dd1d4cb3 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 329 {
sam_grove 5:3f93dd1d4cb3 330 uint32_t result;
sam_grove 5:3f93dd1d4cb3 331
sam_grove 5:3f93dd1d4cb3 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 333 return(result);
sam_grove 5:3f93dd1d4cb3 334 }
sam_grove 5:3f93dd1d4cb3 335
sam_grove 5:3f93dd1d4cb3 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 337 {
sam_grove 5:3f93dd1d4cb3 338 uint32_t result;
sam_grove 5:3f93dd1d4cb3 339
sam_grove 5:3f93dd1d4cb3 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 341 return(result);
sam_grove 5:3f93dd1d4cb3 342 }
sam_grove 5:3f93dd1d4cb3 343
sam_grove 5:3f93dd1d4cb3 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 345 {
sam_grove 5:3f93dd1d4cb3 346 uint32_t result;
sam_grove 5:3f93dd1d4cb3 347
sam_grove 5:3f93dd1d4cb3 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 349 return(result);
sam_grove 5:3f93dd1d4cb3 350 }
sam_grove 5:3f93dd1d4cb3 351
sam_grove 5:3f93dd1d4cb3 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 353 {
sam_grove 5:3f93dd1d4cb3 354 uint32_t result;
sam_grove 5:3f93dd1d4cb3 355
sam_grove 5:3f93dd1d4cb3 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 357 return(result);
sam_grove 5:3f93dd1d4cb3 358 }
sam_grove 5:3f93dd1d4cb3 359
sam_grove 5:3f93dd1d4cb3 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 361 {
sam_grove 5:3f93dd1d4cb3 362 uint32_t result;
sam_grove 5:3f93dd1d4cb3 363
sam_grove 5:3f93dd1d4cb3 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 365 return(result);
sam_grove 5:3f93dd1d4cb3 366 }
sam_grove 5:3f93dd1d4cb3 367
sam_grove 5:3f93dd1d4cb3 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 369 {
sam_grove 5:3f93dd1d4cb3 370 uint32_t result;
sam_grove 5:3f93dd1d4cb3 371
sam_grove 5:3f93dd1d4cb3 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 373 return(result);
sam_grove 5:3f93dd1d4cb3 374 }
sam_grove 5:3f93dd1d4cb3 375
sam_grove 5:3f93dd1d4cb3 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 377 {
sam_grove 5:3f93dd1d4cb3 378 uint32_t result;
sam_grove 5:3f93dd1d4cb3 379
sam_grove 5:3f93dd1d4cb3 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 381 return(result);
sam_grove 5:3f93dd1d4cb3 382 }
sam_grove 5:3f93dd1d4cb3 383
sam_grove 5:3f93dd1d4cb3 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 385 {
sam_grove 5:3f93dd1d4cb3 386 uint32_t result;
sam_grove 5:3f93dd1d4cb3 387
sam_grove 5:3f93dd1d4cb3 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 389 return(result);
sam_grove 5:3f93dd1d4cb3 390 }
sam_grove 5:3f93dd1d4cb3 391
sam_grove 5:3f93dd1d4cb3 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 393 {
sam_grove 5:3f93dd1d4cb3 394 uint32_t result;
sam_grove 5:3f93dd1d4cb3 395
sam_grove 5:3f93dd1d4cb3 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 397 return(result);
sam_grove 5:3f93dd1d4cb3 398 }
sam_grove 5:3f93dd1d4cb3 399
sam_grove 5:3f93dd1d4cb3 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 401 {
sam_grove 5:3f93dd1d4cb3 402 uint32_t result;
sam_grove 5:3f93dd1d4cb3 403
sam_grove 5:3f93dd1d4cb3 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 405 return(result);
sam_grove 5:3f93dd1d4cb3 406 }
sam_grove 5:3f93dd1d4cb3 407
sam_grove 5:3f93dd1d4cb3 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 409 {
sam_grove 5:3f93dd1d4cb3 410 uint32_t result;
sam_grove 5:3f93dd1d4cb3 411
sam_grove 5:3f93dd1d4cb3 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 413 return(result);
sam_grove 5:3f93dd1d4cb3 414 }
sam_grove 5:3f93dd1d4cb3 415
sam_grove 5:3f93dd1d4cb3 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 417 {
sam_grove 5:3f93dd1d4cb3 418 uint32_t result;
sam_grove 5:3f93dd1d4cb3 419
sam_grove 5:3f93dd1d4cb3 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 421 return(result);
sam_grove 5:3f93dd1d4cb3 422 }
sam_grove 5:3f93dd1d4cb3 423
sam_grove 5:3f93dd1d4cb3 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 425 {
sam_grove 5:3f93dd1d4cb3 426 uint32_t result;
sam_grove 5:3f93dd1d4cb3 427
sam_grove 5:3f93dd1d4cb3 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 429 return(result);
sam_grove 5:3f93dd1d4cb3 430 }
sam_grove 5:3f93dd1d4cb3 431
sam_grove 5:3f93dd1d4cb3 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 433 {
sam_grove 5:3f93dd1d4cb3 434 uint32_t result;
sam_grove 5:3f93dd1d4cb3 435
sam_grove 5:3f93dd1d4cb3 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 437 return(result);
sam_grove 5:3f93dd1d4cb3 438 }
sam_grove 5:3f93dd1d4cb3 439
sam_grove 5:3f93dd1d4cb3 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 441 {
sam_grove 5:3f93dd1d4cb3 442 uint32_t result;
sam_grove 5:3f93dd1d4cb3 443
sam_grove 5:3f93dd1d4cb3 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 445 return(result);
sam_grove 5:3f93dd1d4cb3 446 }
sam_grove 5:3f93dd1d4cb3 447
sam_grove 5:3f93dd1d4cb3 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 449 {
sam_grove 5:3f93dd1d4cb3 450 uint32_t result;
sam_grove 5:3f93dd1d4cb3 451
sam_grove 5:3f93dd1d4cb3 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 453 return(result);
sam_grove 5:3f93dd1d4cb3 454 }
sam_grove 5:3f93dd1d4cb3 455
sam_grove 5:3f93dd1d4cb3 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
sam_grove 5:3f93dd1d4cb3 457 {
sam_grove 5:3f93dd1d4cb3 458 uint32_t result;
sam_grove 5:3f93dd1d4cb3 459
sam_grove 5:3f93dd1d4cb3 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sam_grove 5:3f93dd1d4cb3 461 return(result);
sam_grove 5:3f93dd1d4cb3 462 }
sam_grove 5:3f93dd1d4cb3 463
sam_grove 5:3f93dd1d4cb3 464 #define __SSAT16(ARG1,ARG2) \
sam_grove 5:3f93dd1d4cb3 465 ({ \
sam_grove 5:3f93dd1d4cb3 466 uint32_t __RES, __ARG1 = (ARG1); \
sam_grove 5:3f93dd1d4cb3 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
sam_grove 5:3f93dd1d4cb3 468 __RES; \
sam_grove 5:3f93dd1d4cb3 469 })
sam_grove 5:3f93dd1d4cb3 470
sam_grove 5:3f93dd1d4cb3 471 #define __USAT16(ARG1,ARG2) \
sam_grove 5:3f93dd1d4cb3 472 ({ \
sam_grove 5:3f93dd1d4cb3 473 uint32_t __RES, __ARG1 = (ARG1); \
sam_grove 5:3f93dd1d4cb3 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
sam_grove 5:3f93dd1d4cb3 475 __RES; \
sam_grove 5:3f93dd1d4cb3 476 })
sam_grove 5:3f93dd1d4cb3 477
sam_grove 5:3f93dd1d4cb3 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
sam_grove 5:3f93dd1d4cb3 479 {
sam_grove 5:3f93dd1d4cb3 480 uint32_t result;
sam_grove 5:3f93dd1d4cb3 481
sam_grove 5:3f93dd1d4cb3 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
sam_grove 5:3f93dd1d4cb3 483 return(result);
sam_grove 5:3f93dd1d4cb3 484 }
sam_grove 5:3f93dd1d4cb3 485
sam_grove 5:3f93dd1d4cb3 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 487 {
sam_grove 5:3f93dd1d4cb3 488 uint32_t result;
sam_grove 5:3f93dd1d4cb3 489
sam_grove 5:3f93dd1d4cb3 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 491 return(result);
sam_grove 5:3f93dd1d4cb3 492 }
sam_grove 5:3f93dd1d4cb3 493
sam_grove 5:3f93dd1d4cb3 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
sam_grove 5:3f93dd1d4cb3 495 {
sam_grove 5:3f93dd1d4cb3 496 uint32_t result;
sam_grove 5:3f93dd1d4cb3 497
sam_grove 5:3f93dd1d4cb3 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
sam_grove 5:3f93dd1d4cb3 499 return(result);
sam_grove 5:3f93dd1d4cb3 500 }
sam_grove 5:3f93dd1d4cb3 501
sam_grove 5:3f93dd1d4cb3 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 503 {
sam_grove 5:3f93dd1d4cb3 504 uint32_t result;
sam_grove 5:3f93dd1d4cb3 505
sam_grove 5:3f93dd1d4cb3 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 507 return(result);
sam_grove 5:3f93dd1d4cb3 508 }
sam_grove 5:3f93dd1d4cb3 509
sam_grove 5:3f93dd1d4cb3 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 511 {
sam_grove 5:3f93dd1d4cb3 512 uint32_t result;
sam_grove 5:3f93dd1d4cb3 513
sam_grove 5:3f93dd1d4cb3 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 515 return(result);
sam_grove 5:3f93dd1d4cb3 516 }
sam_grove 5:3f93dd1d4cb3 517
sam_grove 5:3f93dd1d4cb3 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 519 {
sam_grove 5:3f93dd1d4cb3 520 uint32_t result;
sam_grove 5:3f93dd1d4cb3 521
sam_grove 5:3f93dd1d4cb3 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 523 return(result);
sam_grove 5:3f93dd1d4cb3 524 }
sam_grove 5:3f93dd1d4cb3 525
sam_grove 5:3f93dd1d4cb3 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
sam_grove 5:3f93dd1d4cb3 527 {
sam_grove 5:3f93dd1d4cb3 528 uint32_t result;
sam_grove 5:3f93dd1d4cb3 529
sam_grove 5:3f93dd1d4cb3 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sam_grove 5:3f93dd1d4cb3 531 return(result);
sam_grove 5:3f93dd1d4cb3 532 }
sam_grove 5:3f93dd1d4cb3 533
sam_grove 5:3f93dd1d4cb3 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
sam_grove 5:3f93dd1d4cb3 535 {
sam_grove 5:3f93dd1d4cb3 536 uint32_t result;
sam_grove 5:3f93dd1d4cb3 537
sam_grove 5:3f93dd1d4cb3 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sam_grove 5:3f93dd1d4cb3 539 return(result);
sam_grove 5:3f93dd1d4cb3 540 }
sam_grove 5:3f93dd1d4cb3 541
sam_grove 5:3f93dd1d4cb3 542 #define __SMLALD(ARG1,ARG2,ARG3) \
sam_grove 5:3f93dd1d4cb3 543 ({ \
sam_grove 5:3f93dd1d4cb3 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
sam_grove 5:3f93dd1d4cb3 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
sam_grove 5:3f93dd1d4cb3 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
sam_grove 5:3f93dd1d4cb3 547 })
sam_grove 5:3f93dd1d4cb3 548
sam_grove 5:3f93dd1d4cb3 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
sam_grove 5:3f93dd1d4cb3 550 ({ \
sam_grove 5:3f93dd1d4cb3 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
sam_grove 5:3f93dd1d4cb3 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
sam_grove 5:3f93dd1d4cb3 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
sam_grove 5:3f93dd1d4cb3 554 })
sam_grove 5:3f93dd1d4cb3 555
sam_grove 5:3f93dd1d4cb3 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 557 {
sam_grove 5:3f93dd1d4cb3 558 uint32_t result;
sam_grove 5:3f93dd1d4cb3 559
sam_grove 5:3f93dd1d4cb3 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 561 return(result);
sam_grove 5:3f93dd1d4cb3 562 }
sam_grove 5:3f93dd1d4cb3 563
sam_grove 5:3f93dd1d4cb3 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 565 {
sam_grove 5:3f93dd1d4cb3 566 uint32_t result;
sam_grove 5:3f93dd1d4cb3 567
sam_grove 5:3f93dd1d4cb3 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 569 return(result);
sam_grove 5:3f93dd1d4cb3 570 }
sam_grove 5:3f93dd1d4cb3 571
sam_grove 5:3f93dd1d4cb3 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
sam_grove 5:3f93dd1d4cb3 573 {
sam_grove 5:3f93dd1d4cb3 574 uint32_t result;
sam_grove 5:3f93dd1d4cb3 575
sam_grove 5:3f93dd1d4cb3 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sam_grove 5:3f93dd1d4cb3 577 return(result);
sam_grove 5:3f93dd1d4cb3 578 }
sam_grove 5:3f93dd1d4cb3 579
sam_grove 5:3f93dd1d4cb3 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
sam_grove 5:3f93dd1d4cb3 581 {
sam_grove 5:3f93dd1d4cb3 582 uint32_t result;
sam_grove 5:3f93dd1d4cb3 583
sam_grove 5:3f93dd1d4cb3 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sam_grove 5:3f93dd1d4cb3 585 return(result);
sam_grove 5:3f93dd1d4cb3 586 }
sam_grove 5:3f93dd1d4cb3 587
sam_grove 5:3f93dd1d4cb3 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
sam_grove 5:3f93dd1d4cb3 589 ({ \
sam_grove 5:3f93dd1d4cb3 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
sam_grove 5:3f93dd1d4cb3 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
sam_grove 5:3f93dd1d4cb3 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
sam_grove 5:3f93dd1d4cb3 593 })
sam_grove 5:3f93dd1d4cb3 594
sam_grove 5:3f93dd1d4cb3 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
sam_grove 5:3f93dd1d4cb3 596 ({ \
sam_grove 5:3f93dd1d4cb3 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
sam_grove 5:3f93dd1d4cb3 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
sam_grove 5:3f93dd1d4cb3 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
sam_grove 5:3f93dd1d4cb3 600 })
sam_grove 5:3f93dd1d4cb3 601
sam_grove 5:3f93dd1d4cb3 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 603 {
sam_grove 5:3f93dd1d4cb3 604 uint32_t result;
sam_grove 5:3f93dd1d4cb3 605
sam_grove 5:3f93dd1d4cb3 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 607 return(result);
sam_grove 5:3f93dd1d4cb3 608 }
sam_grove 5:3f93dd1d4cb3 609
sam_grove 5:3f93dd1d4cb3 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 611 {
sam_grove 5:3f93dd1d4cb3 612 uint32_t result;
sam_grove 5:3f93dd1d4cb3 613
sam_grove 5:3f93dd1d4cb3 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 615 return(result);
sam_grove 5:3f93dd1d4cb3 616 }
sam_grove 5:3f93dd1d4cb3 617
sam_grove 5:3f93dd1d4cb3 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
sam_grove 5:3f93dd1d4cb3 619 {
sam_grove 5:3f93dd1d4cb3 620 uint32_t result;
sam_grove 5:3f93dd1d4cb3 621
sam_grove 5:3f93dd1d4cb3 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sam_grove 5:3f93dd1d4cb3 623 return(result);
sam_grove 5:3f93dd1d4cb3 624 }
sam_grove 5:3f93dd1d4cb3 625
sam_grove 5:3f93dd1d4cb3 626 #define __PKHBT(ARG1,ARG2,ARG3) \
sam_grove 5:3f93dd1d4cb3 627 ({ \
sam_grove 5:3f93dd1d4cb3 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
sam_grove 5:3f93dd1d4cb3 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
sam_grove 5:3f93dd1d4cb3 630 __RES; \
sam_grove 5:3f93dd1d4cb3 631 })
sam_grove 5:3f93dd1d4cb3 632
sam_grove 5:3f93dd1d4cb3 633 #define __PKHTB(ARG1,ARG2,ARG3) \
sam_grove 5:3f93dd1d4cb3 634 ({ \
sam_grove 5:3f93dd1d4cb3 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
sam_grove 5:3f93dd1d4cb3 636 if (ARG3 == 0) \
sam_grove 5:3f93dd1d4cb3 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
sam_grove 5:3f93dd1d4cb3 638 else \
sam_grove 5:3f93dd1d4cb3 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
sam_grove 5:3f93dd1d4cb3 640 __RES; \
sam_grove 5:3f93dd1d4cb3 641 })
sam_grove 5:3f93dd1d4cb3 642
sam_grove 5:3f93dd1d4cb3 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
sam_grove 5:3f93dd1d4cb3 644 {
sam_grove 5:3f93dd1d4cb3 645 int32_t result;
sam_grove 5:3f93dd1d4cb3 646
sam_grove 5:3f93dd1d4cb3 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
sam_grove 5:3f93dd1d4cb3 648 return(result);
sam_grove 5:3f93dd1d4cb3 649 }
sam_grove 5:3f93dd1d4cb3 650
sam_grove 5:3f93dd1d4cb3 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 652
sam_grove 5:3f93dd1d4cb3 653
sam_grove 5:3f93dd1d4cb3 654
sam_grove 5:3f93dd1d4cb3 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
sam_grove 5:3f93dd1d4cb3 656 /* TASKING carm specific functions */
sam_grove 5:3f93dd1d4cb3 657
sam_grove 5:3f93dd1d4cb3 658
sam_grove 5:3f93dd1d4cb3 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 660 /* not yet supported */
sam_grove 5:3f93dd1d4cb3 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 662
sam_grove 5:3f93dd1d4cb3 663
sam_grove 5:3f93dd1d4cb3 664 #endif
sam_grove 5:3f93dd1d4cb3 665
sam_grove 5:3f93dd1d4cb3 666 /*@} end of group CMSIS_SIMD_intrinsics */
sam_grove 5:3f93dd1d4cb3 667
sam_grove 5:3f93dd1d4cb3 668
sam_grove 5:3f93dd1d4cb3 669 #endif /* __CORE_CM4_SIMD_H */
sam_grove 5:3f93dd1d4cb3 670
sam_grove 5:3f93dd1d4cb3 671 #ifdef __cplusplus
sam_grove 5:3f93dd1d4cb3 672 }
sam_grove 5:3f93dd1d4cb3 673 #endif