ublox_C200Test - Integrating the ublox LISA C200 modem

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Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/cmsis/core_cm4.h@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:: sam_grove
Date:: Thu Sep 26 00:44:20 2013 -0500
Revision:: 5:3f93dd1d4cb3

Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

User	Revision	Line number	New contents of line
sam_grove	5:3f93dd1d4cb3	1	/************************************************************************//
sam_grove	5:3f93dd1d4cb3	2	* @file core_cm4.h
sam_grove	5:3f93dd1d4cb3	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
sam_grove	5:3f93dd1d4cb3	4	* @version V3.20
sam_grove	5:3f93dd1d4cb3	5	* @date 25. February 2013
sam_grove	5:3f93dd1d4cb3	6	*
sam_grove	5:3f93dd1d4cb3	7	* @note
sam_grove	5:3f93dd1d4cb3	8	*
sam_grove	5:3f93dd1d4cb3	9	******************************************************************************/
sam_grove	5:3f93dd1d4cb3	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
sam_grove	5:3f93dd1d4cb3	11
sam_grove	5:3f93dd1d4cb3	12	All rights reserved.
sam_grove	5:3f93dd1d4cb3	13	Redistribution and use in source and binary forms, with or without
sam_grove	5:3f93dd1d4cb3	14	modification, are permitted provided that the following conditions are met:
sam_grove	5:3f93dd1d4cb3	15	- Redistributions of source code must retain the above copyright
sam_grove	5:3f93dd1d4cb3	16	notice, this list of conditions and the following disclaimer.
sam_grove	5:3f93dd1d4cb3	17	- Redistributions in binary form must reproduce the above copyright
sam_grove	5:3f93dd1d4cb3	18	notice, this list of conditions and the following disclaimer in the
sam_grove	5:3f93dd1d4cb3	19	documentation and/or other materials provided with the distribution.
sam_grove	5:3f93dd1d4cb3	20	- Neither the name of ARM nor the names of its contributors may be used
sam_grove	5:3f93dd1d4cb3	21	to endorse or promote products derived from this software without
sam_grove	5:3f93dd1d4cb3	22	specific prior written permission.
sam_grove	5:3f93dd1d4cb3	23	*
sam_grove	5:3f93dd1d4cb3	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sam_grove	5:3f93dd1d4cb3	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sam_grove	5:3f93dd1d4cb3	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sam_grove	5:3f93dd1d4cb3	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sam_grove	5:3f93dd1d4cb3	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sam_grove	5:3f93dd1d4cb3	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sam_grove	5:3f93dd1d4cb3	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sam_grove	5:3f93dd1d4cb3	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sam_grove	5:3f93dd1d4cb3	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sam_grove	5:3f93dd1d4cb3	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sam_grove	5:3f93dd1d4cb3	34	POSSIBILITY OF SUCH DAMAGE.
sam_grove	5:3f93dd1d4cb3	35	---------------------------------------------------------------------------*/
sam_grove	5:3f93dd1d4cb3	36
sam_grove	5:3f93dd1d4cb3	37
sam_grove	5:3f93dd1d4cb3	38	#if defined ( __ICCARM__ )
sam_grove	5:3f93dd1d4cb3	39	#pragma system_include /* treat file as system include file for MISRA check */
sam_grove	5:3f93dd1d4cb3	40	#endif
sam_grove	5:3f93dd1d4cb3	41
sam_grove	5:3f93dd1d4cb3	42	#ifdef __cplusplus
sam_grove	5:3f93dd1d4cb3	43	extern "C" {
sam_grove	5:3f93dd1d4cb3	44	#endif
sam_grove	5:3f93dd1d4cb3	45
sam_grove	5:3f93dd1d4cb3	46	#ifndef __CORE_CM4_H_GENERIC
sam_grove	5:3f93dd1d4cb3	47	#define __CORE_CM4_H_GENERIC
sam_grove	5:3f93dd1d4cb3	48
sam_grove	5:3f93dd1d4cb3	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
sam_grove	5:3f93dd1d4cb3	50	CMSIS violates the following MISRA-C:2004 rules:
sam_grove	5:3f93dd1d4cb3	51
sam_grove	5:3f93dd1d4cb3	52	\li Required Rule 8.5, object/function definition in header file.<br>
sam_grove	5:3f93dd1d4cb3	53	Function definitions in header files are used to allow 'inlining'.
sam_grove	5:3f93dd1d4cb3	54
sam_grove	5:3f93dd1d4cb3	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
sam_grove	5:3f93dd1d4cb3	56	Unions are used for effective representation of core registers.
sam_grove	5:3f93dd1d4cb3	57
sam_grove	5:3f93dd1d4cb3	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
sam_grove	5:3f93dd1d4cb3	59	Function-like macros are used to allow more efficient code.
sam_grove	5:3f93dd1d4cb3	60	*/
sam_grove	5:3f93dd1d4cb3	61
sam_grove	5:3f93dd1d4cb3	62
sam_grove	5:3f93dd1d4cb3	63	/*******************************************************************************
sam_grove	5:3f93dd1d4cb3	64	* CMSIS definitions
sam_grove	5:3f93dd1d4cb3	65	******************************************************************************/
sam_grove	5:3f93dd1d4cb3	66	/** \ingroup Cortex_M4
sam_grove	5:3f93dd1d4cb3	67	@{
sam_grove	5:3f93dd1d4cb3	68	*/
sam_grove	5:3f93dd1d4cb3	69
sam_grove	5:3f93dd1d4cb3	70	/* CMSIS CM4 definitions */
sam_grove	5:3f93dd1d4cb3	71	#define __CM4_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
sam_grove	5:3f93dd1d4cb3	72	#define __CM4_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
sam_grove	5:3f93dd1d4cb3	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
sam_grove	5:3f93dd1d4cb3	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
sam_grove	5:3f93dd1d4cb3	75
sam_grove	5:3f93dd1d4cb3	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
sam_grove	5:3f93dd1d4cb3	77
sam_grove	5:3f93dd1d4cb3	78
sam_grove	5:3f93dd1d4cb3	79	#if defined ( __CC_ARM )
sam_grove	5:3f93dd1d4cb3	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
sam_grove	5:3f93dd1d4cb3	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
sam_grove	5:3f93dd1d4cb3	82	#define __STATIC_INLINE static __inline
sam_grove	5:3f93dd1d4cb3	83
sam_grove	5:3f93dd1d4cb3	84	#elif defined ( __ICCARM__ )
sam_grove	5:3f93dd1d4cb3	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
sam_grove	5:3f93dd1d4cb3	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
sam_grove	5:3f93dd1d4cb3	87	#define __STATIC_INLINE static inline
sam_grove	5:3f93dd1d4cb3	88
sam_grove	5:3f93dd1d4cb3	89	#elif defined ( __TMS470__ )
sam_grove	5:3f93dd1d4cb3	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
sam_grove	5:3f93dd1d4cb3	91	#define __STATIC_INLINE static inline
sam_grove	5:3f93dd1d4cb3	92
sam_grove	5:3f93dd1d4cb3	93	#elif defined ( __GNUC__ )
sam_grove	5:3f93dd1d4cb3	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
sam_grove	5:3f93dd1d4cb3	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
sam_grove	5:3f93dd1d4cb3	96	#define __STATIC_INLINE static inline
sam_grove	5:3f93dd1d4cb3	97
sam_grove	5:3f93dd1d4cb3	98	#elif defined ( __TASKING__ )
sam_grove	5:3f93dd1d4cb3	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
sam_grove	5:3f93dd1d4cb3	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
sam_grove	5:3f93dd1d4cb3	101	#define __STATIC_INLINE static inline
sam_grove	5:3f93dd1d4cb3	102
sam_grove	5:3f93dd1d4cb3	103	#endif
sam_grove	5:3f93dd1d4cb3	104
sam_grove	5:3f93dd1d4cb3	105	/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
sam_grove	5:3f93dd1d4cb3	106	*/
sam_grove	5:3f93dd1d4cb3	107	#if defined ( __CC_ARM )
sam_grove	5:3f93dd1d4cb3	108	#if defined __TARGET_FPU_VFP
sam_grove	5:3f93dd1d4cb3	109	#if (__FPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	110	#define __FPU_USED 1
sam_grove	5:3f93dd1d4cb3	111	#else
sam_grove	5:3f93dd1d4cb3	112	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove	5:3f93dd1d4cb3	113	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	114	#endif
sam_grove	5:3f93dd1d4cb3	115	#else
sam_grove	5:3f93dd1d4cb3	116	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	117	#endif
sam_grove	5:3f93dd1d4cb3	118
sam_grove	5:3f93dd1d4cb3	119	#elif defined ( __ICCARM__ )
sam_grove	5:3f93dd1d4cb3	120	#if defined __ARMVFP__
sam_grove	5:3f93dd1d4cb3	121	#if (__FPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	122	#define __FPU_USED 1
sam_grove	5:3f93dd1d4cb3	123	#else
sam_grove	5:3f93dd1d4cb3	124	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove	5:3f93dd1d4cb3	125	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	126	#endif
sam_grove	5:3f93dd1d4cb3	127	#else
sam_grove	5:3f93dd1d4cb3	128	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	129	#endif
sam_grove	5:3f93dd1d4cb3	130
sam_grove	5:3f93dd1d4cb3	131	#elif defined ( __TMS470__ )
sam_grove	5:3f93dd1d4cb3	132	#if defined __TI_VFP_SUPPORT__
sam_grove	5:3f93dd1d4cb3	133	#if (__FPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	134	#define __FPU_USED 1
sam_grove	5:3f93dd1d4cb3	135	#else
sam_grove	5:3f93dd1d4cb3	136	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove	5:3f93dd1d4cb3	137	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	138	#endif
sam_grove	5:3f93dd1d4cb3	139	#else
sam_grove	5:3f93dd1d4cb3	140	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	141	#endif
sam_grove	5:3f93dd1d4cb3	142
sam_grove	5:3f93dd1d4cb3	143	#elif defined ( __GNUC__ )
sam_grove	5:3f93dd1d4cb3	144	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
sam_grove	5:3f93dd1d4cb3	145	#if (__FPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	146	#define __FPU_USED 1
sam_grove	5:3f93dd1d4cb3	147	#else
sam_grove	5:3f93dd1d4cb3	148	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove	5:3f93dd1d4cb3	149	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	150	#endif
sam_grove	5:3f93dd1d4cb3	151	#else
sam_grove	5:3f93dd1d4cb3	152	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	153	#endif
sam_grove	5:3f93dd1d4cb3	154
sam_grove	5:3f93dd1d4cb3	155	#elif defined ( __TASKING__ )
sam_grove	5:3f93dd1d4cb3	156	#if defined __FPU_VFP__
sam_grove	5:3f93dd1d4cb3	157	#if (__FPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	158	#define __FPU_USED 1
sam_grove	5:3f93dd1d4cb3	159	#else
sam_grove	5:3f93dd1d4cb3	160	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove	5:3f93dd1d4cb3	161	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	162	#endif
sam_grove	5:3f93dd1d4cb3	163	#else
sam_grove	5:3f93dd1d4cb3	164	#define __FPU_USED 0
sam_grove	5:3f93dd1d4cb3	165	#endif
sam_grove	5:3f93dd1d4cb3	166	#endif
sam_grove	5:3f93dd1d4cb3	167
sam_grove	5:3f93dd1d4cb3	168	#include <stdint.h> /* standard types definitions */
sam_grove	5:3f93dd1d4cb3	169	#include <core_cmInstr.h> /* Core Instruction Access */
sam_grove	5:3f93dd1d4cb3	170	#include <core_cmFunc.h> /* Core Function Access */
sam_grove	5:3f93dd1d4cb3	171	#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
sam_grove	5:3f93dd1d4cb3	172
sam_grove	5:3f93dd1d4cb3	173	#endif /* __CORE_CM4_H_GENERIC */
sam_grove	5:3f93dd1d4cb3	174
sam_grove	5:3f93dd1d4cb3	175	#ifndef __CMSIS_GENERIC
sam_grove	5:3f93dd1d4cb3	176
sam_grove	5:3f93dd1d4cb3	177	#ifndef __CORE_CM4_H_DEPENDANT
sam_grove	5:3f93dd1d4cb3	178	#define __CORE_CM4_H_DEPENDANT
sam_grove	5:3f93dd1d4cb3	179
sam_grove	5:3f93dd1d4cb3	180	/* check device defines and use defaults */
sam_grove	5:3f93dd1d4cb3	181	#if defined __CHECK_DEVICE_DEFINES
sam_grove	5:3f93dd1d4cb3	182	#ifndef __CM4_REV
sam_grove	5:3f93dd1d4cb3	183	#define __CM4_REV 0x0000
sam_grove	5:3f93dd1d4cb3	184	#warning "__CM4_REV not defined in device header file; using default!"
sam_grove	5:3f93dd1d4cb3	185	#endif
sam_grove	5:3f93dd1d4cb3	186
sam_grove	5:3f93dd1d4cb3	187	#ifndef __FPU_PRESENT
sam_grove	5:3f93dd1d4cb3	188	#define __FPU_PRESENT 0
sam_grove	5:3f93dd1d4cb3	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
sam_grove	5:3f93dd1d4cb3	190	#endif
sam_grove	5:3f93dd1d4cb3	191
sam_grove	5:3f93dd1d4cb3	192	#ifndef __MPU_PRESENT
sam_grove	5:3f93dd1d4cb3	193	#define __MPU_PRESENT 0
sam_grove	5:3f93dd1d4cb3	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
sam_grove	5:3f93dd1d4cb3	195	#endif
sam_grove	5:3f93dd1d4cb3	196
sam_grove	5:3f93dd1d4cb3	197	#ifndef __NVIC_PRIO_BITS
sam_grove	5:3f93dd1d4cb3	198	#define __NVIC_PRIO_BITS 4
sam_grove	5:3f93dd1d4cb3	199	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
sam_grove	5:3f93dd1d4cb3	200	#endif
sam_grove	5:3f93dd1d4cb3	201
sam_grove	5:3f93dd1d4cb3	202	#ifndef __Vendor_SysTickConfig
sam_grove	5:3f93dd1d4cb3	203	#define __Vendor_SysTickConfig 0
sam_grove	5:3f93dd1d4cb3	204	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
sam_grove	5:3f93dd1d4cb3	205	#endif
sam_grove	5:3f93dd1d4cb3	206	#endif
sam_grove	5:3f93dd1d4cb3	207
sam_grove	5:3f93dd1d4cb3	208	/* IO definitions (access restrictions to peripheral registers) */
sam_grove	5:3f93dd1d4cb3	209	/**
sam_grove	5:3f93dd1d4cb3	210	\defgroup CMSIS_glob_defs CMSIS Global Defines
sam_grove	5:3f93dd1d4cb3	211
sam_grove	5:3f93dd1d4cb3	212	<strong>IO Type Qualifiers</strong> are used
sam_grove	5:3f93dd1d4cb3	213	\li to specify the access to peripheral variables.
sam_grove	5:3f93dd1d4cb3	214	\li for automatic generation of peripheral register debug information.
sam_grove	5:3f93dd1d4cb3	215	*/
sam_grove	5:3f93dd1d4cb3	216	#ifdef __cplusplus
sam_grove	5:3f93dd1d4cb3	217	#define __I volatile /!< Defines 'read only' permissions /
sam_grove	5:3f93dd1d4cb3	218	#else
sam_grove	5:3f93dd1d4cb3	219	#define __I volatile const /!< Defines 'read only' permissions /
sam_grove	5:3f93dd1d4cb3	220	#endif
sam_grove	5:3f93dd1d4cb3	221	#define __O volatile /!< Defines 'write only' permissions /
sam_grove	5:3f93dd1d4cb3	222	#define __IO volatile /!< Defines 'read / write' permissions /
sam_grove	5:3f93dd1d4cb3	223
sam_grove	5:3f93dd1d4cb3	224	/@} end of group Cortex_M4 /
sam_grove	5:3f93dd1d4cb3	225
sam_grove	5:3f93dd1d4cb3	226
sam_grove	5:3f93dd1d4cb3	227
sam_grove	5:3f93dd1d4cb3	228	/*******************************************************************************
sam_grove	5:3f93dd1d4cb3	229	* Register Abstraction
sam_grove	5:3f93dd1d4cb3	230	Core Register contain:
sam_grove	5:3f93dd1d4cb3	231	- Core Register
sam_grove	5:3f93dd1d4cb3	232	- Core NVIC Register
sam_grove	5:3f93dd1d4cb3	233	- Core SCB Register
sam_grove	5:3f93dd1d4cb3	234	- Core SysTick Register
sam_grove	5:3f93dd1d4cb3	235	- Core Debug Register
sam_grove	5:3f93dd1d4cb3	236	- Core MPU Register
sam_grove	5:3f93dd1d4cb3	237	- Core FPU Register
sam_grove	5:3f93dd1d4cb3	238	******************************************************************************/
sam_grove	5:3f93dd1d4cb3	239	/** \defgroup CMSIS_core_register Defines and Type Definitions
sam_grove	5:3f93dd1d4cb3	240	\brief Type definitions and defines for Cortex-M processor based devices.
sam_grove	5:3f93dd1d4cb3	241	*/
sam_grove	5:3f93dd1d4cb3	242
sam_grove	5:3f93dd1d4cb3	243	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	244	\defgroup CMSIS_CORE Status and Control Registers
sam_grove	5:3f93dd1d4cb3	245	\brief Core Register type definitions.
sam_grove	5:3f93dd1d4cb3	246	@{
sam_grove	5:3f93dd1d4cb3	247	*/
sam_grove	5:3f93dd1d4cb3	248
sam_grove	5:3f93dd1d4cb3	249	/** \brief Union type to access the Application Program Status Register (APSR).
sam_grove	5:3f93dd1d4cb3	250	*/
sam_grove	5:3f93dd1d4cb3	251	typedef union
sam_grove	5:3f93dd1d4cb3	252	{
sam_grove	5:3f93dd1d4cb3	253	struct
sam_grove	5:3f93dd1d4cb3	254	{
sam_grove	5:3f93dd1d4cb3	255	#if (__CORTEX_M != 0x04)
sam_grove	5:3f93dd1d4cb3	256	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
sam_grove	5:3f93dd1d4cb3	257	#else
sam_grove	5:3f93dd1d4cb3	258	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
sam_grove	5:3f93dd1d4cb3	259	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
sam_grove	5:3f93dd1d4cb3	260	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
sam_grove	5:3f93dd1d4cb3	261	#endif
sam_grove	5:3f93dd1d4cb3	262	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
sam_grove	5:3f93dd1d4cb3	263	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
sam_grove	5:3f93dd1d4cb3	264	uint32_t C:1; /!< bit: 29 Carry condition code flag /
sam_grove	5:3f93dd1d4cb3	265	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
sam_grove	5:3f93dd1d4cb3	266	uint32_t N:1; /!< bit: 31 Negative condition code flag /
sam_grove	5:3f93dd1d4cb3	267	} b; /!< Structure used for bit access /
sam_grove	5:3f93dd1d4cb3	268	uint32_t w; /!< Type used for word access /
sam_grove	5:3f93dd1d4cb3	269	} APSR_Type;
sam_grove	5:3f93dd1d4cb3	270
sam_grove	5:3f93dd1d4cb3	271
sam_grove	5:3f93dd1d4cb3	272	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
sam_grove	5:3f93dd1d4cb3	273	*/
sam_grove	5:3f93dd1d4cb3	274	typedef union
sam_grove	5:3f93dd1d4cb3	275	{
sam_grove	5:3f93dd1d4cb3	276	struct
sam_grove	5:3f93dd1d4cb3	277	{
sam_grove	5:3f93dd1d4cb3	278	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
sam_grove	5:3f93dd1d4cb3	279	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
sam_grove	5:3f93dd1d4cb3	280	} b; /!< Structure used for bit access /
sam_grove	5:3f93dd1d4cb3	281	uint32_t w; /!< Type used for word access /
sam_grove	5:3f93dd1d4cb3	282	} IPSR_Type;
sam_grove	5:3f93dd1d4cb3	283
sam_grove	5:3f93dd1d4cb3	284
sam_grove	5:3f93dd1d4cb3	285	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
sam_grove	5:3f93dd1d4cb3	286	*/
sam_grove	5:3f93dd1d4cb3	287	typedef union
sam_grove	5:3f93dd1d4cb3	288	{
sam_grove	5:3f93dd1d4cb3	289	struct
sam_grove	5:3f93dd1d4cb3	290	{
sam_grove	5:3f93dd1d4cb3	291	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
sam_grove	5:3f93dd1d4cb3	292	#if (__CORTEX_M != 0x04)
sam_grove	5:3f93dd1d4cb3	293	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
sam_grove	5:3f93dd1d4cb3	294	#else
sam_grove	5:3f93dd1d4cb3	295	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
sam_grove	5:3f93dd1d4cb3	296	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
sam_grove	5:3f93dd1d4cb3	297	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
sam_grove	5:3f93dd1d4cb3	298	#endif
sam_grove	5:3f93dd1d4cb3	299	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
sam_grove	5:3f93dd1d4cb3	300	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
sam_grove	5:3f93dd1d4cb3	301	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
sam_grove	5:3f93dd1d4cb3	302	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
sam_grove	5:3f93dd1d4cb3	303	uint32_t C:1; /!< bit: 29 Carry condition code flag /
sam_grove	5:3f93dd1d4cb3	304	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
sam_grove	5:3f93dd1d4cb3	305	uint32_t N:1; /!< bit: 31 Negative condition code flag /
sam_grove	5:3f93dd1d4cb3	306	} b; /!< Structure used for bit access /
sam_grove	5:3f93dd1d4cb3	307	uint32_t w; /!< Type used for word access /
sam_grove	5:3f93dd1d4cb3	308	} xPSR_Type;
sam_grove	5:3f93dd1d4cb3	309
sam_grove	5:3f93dd1d4cb3	310
sam_grove	5:3f93dd1d4cb3	311	/** \brief Union type to access the Control Registers (CONTROL).
sam_grove	5:3f93dd1d4cb3	312	*/
sam_grove	5:3f93dd1d4cb3	313	typedef union
sam_grove	5:3f93dd1d4cb3	314	{
sam_grove	5:3f93dd1d4cb3	315	struct
sam_grove	5:3f93dd1d4cb3	316	{
sam_grove	5:3f93dd1d4cb3	317	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
sam_grove	5:3f93dd1d4cb3	318	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
sam_grove	5:3f93dd1d4cb3	319	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
sam_grove	5:3f93dd1d4cb3	320	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
sam_grove	5:3f93dd1d4cb3	321	} b; /!< Structure used for bit access /
sam_grove	5:3f93dd1d4cb3	322	uint32_t w; /!< Type used for word access /
sam_grove	5:3f93dd1d4cb3	323	} CONTROL_Type;
sam_grove	5:3f93dd1d4cb3	324
sam_grove	5:3f93dd1d4cb3	325	/@} end of group CMSIS_CORE /
sam_grove	5:3f93dd1d4cb3	326
sam_grove	5:3f93dd1d4cb3	327
sam_grove	5:3f93dd1d4cb3	328	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	329	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
sam_grove	5:3f93dd1d4cb3	330	\brief Type definitions for the NVIC Registers
sam_grove	5:3f93dd1d4cb3	331	@{
sam_grove	5:3f93dd1d4cb3	332	*/
sam_grove	5:3f93dd1d4cb3	333
sam_grove	5:3f93dd1d4cb3	334	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
sam_grove	5:3f93dd1d4cb3	335	*/
sam_grove	5:3f93dd1d4cb3	336	typedef struct
sam_grove	5:3f93dd1d4cb3	337	{
sam_grove	5:3f93dd1d4cb3	338	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
sam_grove	5:3f93dd1d4cb3	339	uint32_t RESERVED0[24];
sam_grove	5:3f93dd1d4cb3	340	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
sam_grove	5:3f93dd1d4cb3	341	uint32_t RSERVED1[24];
sam_grove	5:3f93dd1d4cb3	342	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
sam_grove	5:3f93dd1d4cb3	343	uint32_t RESERVED2[24];
sam_grove	5:3f93dd1d4cb3	344	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
sam_grove	5:3f93dd1d4cb3	345	uint32_t RESERVED3[24];
sam_grove	5:3f93dd1d4cb3	346	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
sam_grove	5:3f93dd1d4cb3	347	uint32_t RESERVED4[56];
sam_grove	5:3f93dd1d4cb3	348	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
sam_grove	5:3f93dd1d4cb3	349	uint32_t RESERVED5[644];
sam_grove	5:3f93dd1d4cb3	350	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
sam_grove	5:3f93dd1d4cb3	351	} NVIC_Type;
sam_grove	5:3f93dd1d4cb3	352
sam_grove	5:3f93dd1d4cb3	353	/* Software Triggered Interrupt Register Definitions */
sam_grove	5:3f93dd1d4cb3	354	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
sam_grove	5:3f93dd1d4cb3	355	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
sam_grove	5:3f93dd1d4cb3	356
sam_grove	5:3f93dd1d4cb3	357	/@} end of group CMSIS_NVIC /
sam_grove	5:3f93dd1d4cb3	358
sam_grove	5:3f93dd1d4cb3	359
sam_grove	5:3f93dd1d4cb3	360	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	361	\defgroup CMSIS_SCB System Control Block (SCB)
sam_grove	5:3f93dd1d4cb3	362	\brief Type definitions for the System Control Block Registers
sam_grove	5:3f93dd1d4cb3	363	@{
sam_grove	5:3f93dd1d4cb3	364	*/
sam_grove	5:3f93dd1d4cb3	365
sam_grove	5:3f93dd1d4cb3	366	/** \brief Structure type to access the System Control Block (SCB).
sam_grove	5:3f93dd1d4cb3	367	*/
sam_grove	5:3f93dd1d4cb3	368	typedef struct
sam_grove	5:3f93dd1d4cb3	369	{
sam_grove	5:3f93dd1d4cb3	370	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
sam_grove	5:3f93dd1d4cb3	371	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
sam_grove	5:3f93dd1d4cb3	372	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
sam_grove	5:3f93dd1d4cb3	373	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
sam_grove	5:3f93dd1d4cb3	374	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
sam_grove	5:3f93dd1d4cb3	375	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
sam_grove	5:3f93dd1d4cb3	376	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
sam_grove	5:3f93dd1d4cb3	377	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
sam_grove	5:3f93dd1d4cb3	378	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
sam_grove	5:3f93dd1d4cb3	379	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
sam_grove	5:3f93dd1d4cb3	380	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
sam_grove	5:3f93dd1d4cb3	381	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
sam_grove	5:3f93dd1d4cb3	382	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
sam_grove	5:3f93dd1d4cb3	383	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
sam_grove	5:3f93dd1d4cb3	384	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
sam_grove	5:3f93dd1d4cb3	385	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
sam_grove	5:3f93dd1d4cb3	386	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
sam_grove	5:3f93dd1d4cb3	387	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
sam_grove	5:3f93dd1d4cb3	388	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
sam_grove	5:3f93dd1d4cb3	389	uint32_t RESERVED0[5];
sam_grove	5:3f93dd1d4cb3	390	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
sam_grove	5:3f93dd1d4cb3	391	} SCB_Type;
sam_grove	5:3f93dd1d4cb3	392
sam_grove	5:3f93dd1d4cb3	393	/* SCB CPUID Register Definitions */
sam_grove	5:3f93dd1d4cb3	394	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
sam_grove	5:3f93dd1d4cb3	395	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
sam_grove	5:3f93dd1d4cb3	396
sam_grove	5:3f93dd1d4cb3	397	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
sam_grove	5:3f93dd1d4cb3	398	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
sam_grove	5:3f93dd1d4cb3	399
sam_grove	5:3f93dd1d4cb3	400	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
sam_grove	5:3f93dd1d4cb3	401	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
sam_grove	5:3f93dd1d4cb3	402
sam_grove	5:3f93dd1d4cb3	403	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
sam_grove	5:3f93dd1d4cb3	404	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
sam_grove	5:3f93dd1d4cb3	405
sam_grove	5:3f93dd1d4cb3	406	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
sam_grove	5:3f93dd1d4cb3	407	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
sam_grove	5:3f93dd1d4cb3	408
sam_grove	5:3f93dd1d4cb3	409	/* SCB Interrupt Control State Register Definitions */
sam_grove	5:3f93dd1d4cb3	410	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
sam_grove	5:3f93dd1d4cb3	411	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
sam_grove	5:3f93dd1d4cb3	412
sam_grove	5:3f93dd1d4cb3	413	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
sam_grove	5:3f93dd1d4cb3	414	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
sam_grove	5:3f93dd1d4cb3	415
sam_grove	5:3f93dd1d4cb3	416	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
sam_grove	5:3f93dd1d4cb3	417	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
sam_grove	5:3f93dd1d4cb3	418
sam_grove	5:3f93dd1d4cb3	419	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
sam_grove	5:3f93dd1d4cb3	420	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
sam_grove	5:3f93dd1d4cb3	421
sam_grove	5:3f93dd1d4cb3	422	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
sam_grove	5:3f93dd1d4cb3	423	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
sam_grove	5:3f93dd1d4cb3	424
sam_grove	5:3f93dd1d4cb3	425	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
sam_grove	5:3f93dd1d4cb3	426	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
sam_grove	5:3f93dd1d4cb3	427
sam_grove	5:3f93dd1d4cb3	428	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
sam_grove	5:3f93dd1d4cb3	429	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
sam_grove	5:3f93dd1d4cb3	430
sam_grove	5:3f93dd1d4cb3	431	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
sam_grove	5:3f93dd1d4cb3	432	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
sam_grove	5:3f93dd1d4cb3	433
sam_grove	5:3f93dd1d4cb3	434	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
sam_grove	5:3f93dd1d4cb3	435	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
sam_grove	5:3f93dd1d4cb3	436
sam_grove	5:3f93dd1d4cb3	437	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
sam_grove	5:3f93dd1d4cb3	438	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
sam_grove	5:3f93dd1d4cb3	439
sam_grove	5:3f93dd1d4cb3	440	/* SCB Vector Table Offset Register Definitions */
sam_grove	5:3f93dd1d4cb3	441	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
sam_grove	5:3f93dd1d4cb3	442	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
sam_grove	5:3f93dd1d4cb3	443
sam_grove	5:3f93dd1d4cb3	444	/* SCB Application Interrupt and Reset Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	445	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
sam_grove	5:3f93dd1d4cb3	446	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
sam_grove	5:3f93dd1d4cb3	447
sam_grove	5:3f93dd1d4cb3	448	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
sam_grove	5:3f93dd1d4cb3	449	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
sam_grove	5:3f93dd1d4cb3	450
sam_grove	5:3f93dd1d4cb3	451	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
sam_grove	5:3f93dd1d4cb3	452	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
sam_grove	5:3f93dd1d4cb3	453
sam_grove	5:3f93dd1d4cb3	454	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
sam_grove	5:3f93dd1d4cb3	455	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
sam_grove	5:3f93dd1d4cb3	456
sam_grove	5:3f93dd1d4cb3	457	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
sam_grove	5:3f93dd1d4cb3	458	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
sam_grove	5:3f93dd1d4cb3	459
sam_grove	5:3f93dd1d4cb3	460	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
sam_grove	5:3f93dd1d4cb3	461	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
sam_grove	5:3f93dd1d4cb3	462
sam_grove	5:3f93dd1d4cb3	463	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
sam_grove	5:3f93dd1d4cb3	464	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
sam_grove	5:3f93dd1d4cb3	465
sam_grove	5:3f93dd1d4cb3	466	/* SCB System Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	467	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
sam_grove	5:3f93dd1d4cb3	468	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
sam_grove	5:3f93dd1d4cb3	469
sam_grove	5:3f93dd1d4cb3	470	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
sam_grove	5:3f93dd1d4cb3	471	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
sam_grove	5:3f93dd1d4cb3	472
sam_grove	5:3f93dd1d4cb3	473	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
sam_grove	5:3f93dd1d4cb3	474	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
sam_grove	5:3f93dd1d4cb3	475
sam_grove	5:3f93dd1d4cb3	476	/* SCB Configuration Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	477	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
sam_grove	5:3f93dd1d4cb3	478	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
sam_grove	5:3f93dd1d4cb3	479
sam_grove	5:3f93dd1d4cb3	480	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
sam_grove	5:3f93dd1d4cb3	481	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
sam_grove	5:3f93dd1d4cb3	482
sam_grove	5:3f93dd1d4cb3	483	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
sam_grove	5:3f93dd1d4cb3	484	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
sam_grove	5:3f93dd1d4cb3	485
sam_grove	5:3f93dd1d4cb3	486	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
sam_grove	5:3f93dd1d4cb3	487	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
sam_grove	5:3f93dd1d4cb3	488
sam_grove	5:3f93dd1d4cb3	489	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
sam_grove	5:3f93dd1d4cb3	490	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
sam_grove	5:3f93dd1d4cb3	491
sam_grove	5:3f93dd1d4cb3	492	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
sam_grove	5:3f93dd1d4cb3	493	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
sam_grove	5:3f93dd1d4cb3	494
sam_grove	5:3f93dd1d4cb3	495	/* SCB System Handler Control and State Register Definitions */
sam_grove	5:3f93dd1d4cb3	496	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
sam_grove	5:3f93dd1d4cb3	497	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
sam_grove	5:3f93dd1d4cb3	498
sam_grove	5:3f93dd1d4cb3	499	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
sam_grove	5:3f93dd1d4cb3	500	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
sam_grove	5:3f93dd1d4cb3	501
sam_grove	5:3f93dd1d4cb3	502	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
sam_grove	5:3f93dd1d4cb3	503	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
sam_grove	5:3f93dd1d4cb3	504
sam_grove	5:3f93dd1d4cb3	505	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
sam_grove	5:3f93dd1d4cb3	506	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
sam_grove	5:3f93dd1d4cb3	507
sam_grove	5:3f93dd1d4cb3	508	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
sam_grove	5:3f93dd1d4cb3	509	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
sam_grove	5:3f93dd1d4cb3	510
sam_grove	5:3f93dd1d4cb3	511	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
sam_grove	5:3f93dd1d4cb3	512	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
sam_grove	5:3f93dd1d4cb3	513
sam_grove	5:3f93dd1d4cb3	514	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
sam_grove	5:3f93dd1d4cb3	515	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
sam_grove	5:3f93dd1d4cb3	516
sam_grove	5:3f93dd1d4cb3	517	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
sam_grove	5:3f93dd1d4cb3	518	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
sam_grove	5:3f93dd1d4cb3	519
sam_grove	5:3f93dd1d4cb3	520	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
sam_grove	5:3f93dd1d4cb3	521	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
sam_grove	5:3f93dd1d4cb3	522
sam_grove	5:3f93dd1d4cb3	523	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
sam_grove	5:3f93dd1d4cb3	524	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
sam_grove	5:3f93dd1d4cb3	525
sam_grove	5:3f93dd1d4cb3	526	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
sam_grove	5:3f93dd1d4cb3	527	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
sam_grove	5:3f93dd1d4cb3	528
sam_grove	5:3f93dd1d4cb3	529	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
sam_grove	5:3f93dd1d4cb3	530	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
sam_grove	5:3f93dd1d4cb3	531
sam_grove	5:3f93dd1d4cb3	532	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
sam_grove	5:3f93dd1d4cb3	533	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
sam_grove	5:3f93dd1d4cb3	534
sam_grove	5:3f93dd1d4cb3	535	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
sam_grove	5:3f93dd1d4cb3	536	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
sam_grove	5:3f93dd1d4cb3	537
sam_grove	5:3f93dd1d4cb3	538	/* SCB Configurable Fault Status Registers Definitions */
sam_grove	5:3f93dd1d4cb3	539	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
sam_grove	5:3f93dd1d4cb3	540	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
sam_grove	5:3f93dd1d4cb3	541
sam_grove	5:3f93dd1d4cb3	542	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
sam_grove	5:3f93dd1d4cb3	543	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
sam_grove	5:3f93dd1d4cb3	544
sam_grove	5:3f93dd1d4cb3	545	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
sam_grove	5:3f93dd1d4cb3	546	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
sam_grove	5:3f93dd1d4cb3	547
sam_grove	5:3f93dd1d4cb3	548	/* SCB Hard Fault Status Registers Definitions */
sam_grove	5:3f93dd1d4cb3	549	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
sam_grove	5:3f93dd1d4cb3	550	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
sam_grove	5:3f93dd1d4cb3	551
sam_grove	5:3f93dd1d4cb3	552	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
sam_grove	5:3f93dd1d4cb3	553	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
sam_grove	5:3f93dd1d4cb3	554
sam_grove	5:3f93dd1d4cb3	555	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
sam_grove	5:3f93dd1d4cb3	556	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
sam_grove	5:3f93dd1d4cb3	557
sam_grove	5:3f93dd1d4cb3	558	/* SCB Debug Fault Status Register Definitions */
sam_grove	5:3f93dd1d4cb3	559	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
sam_grove	5:3f93dd1d4cb3	560	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
sam_grove	5:3f93dd1d4cb3	561
sam_grove	5:3f93dd1d4cb3	562	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
sam_grove	5:3f93dd1d4cb3	563	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
sam_grove	5:3f93dd1d4cb3	564
sam_grove	5:3f93dd1d4cb3	565	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
sam_grove	5:3f93dd1d4cb3	566	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
sam_grove	5:3f93dd1d4cb3	567
sam_grove	5:3f93dd1d4cb3	568	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
sam_grove	5:3f93dd1d4cb3	569	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
sam_grove	5:3f93dd1d4cb3	570
sam_grove	5:3f93dd1d4cb3	571	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
sam_grove	5:3f93dd1d4cb3	572	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
sam_grove	5:3f93dd1d4cb3	573
sam_grove	5:3f93dd1d4cb3	574	/@} end of group CMSIS_SCB /
sam_grove	5:3f93dd1d4cb3	575
sam_grove	5:3f93dd1d4cb3	576
sam_grove	5:3f93dd1d4cb3	577	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	578	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
sam_grove	5:3f93dd1d4cb3	579	\brief Type definitions for the System Control and ID Register not in the SCB
sam_grove	5:3f93dd1d4cb3	580	@{
sam_grove	5:3f93dd1d4cb3	581	*/
sam_grove	5:3f93dd1d4cb3	582
sam_grove	5:3f93dd1d4cb3	583	/** \brief Structure type to access the System Control and ID Register not in the SCB.
sam_grove	5:3f93dd1d4cb3	584	*/
sam_grove	5:3f93dd1d4cb3	585	typedef struct
sam_grove	5:3f93dd1d4cb3	586	{
sam_grove	5:3f93dd1d4cb3	587	uint32_t RESERVED0[1];
sam_grove	5:3f93dd1d4cb3	588	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
sam_grove	5:3f93dd1d4cb3	589	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
sam_grove	5:3f93dd1d4cb3	590	} SCnSCB_Type;
sam_grove	5:3f93dd1d4cb3	591
sam_grove	5:3f93dd1d4cb3	592	/* Interrupt Controller Type Register Definitions */
sam_grove	5:3f93dd1d4cb3	593	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
sam_grove	5:3f93dd1d4cb3	594	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
sam_grove	5:3f93dd1d4cb3	595
sam_grove	5:3f93dd1d4cb3	596	/* Auxiliary Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	597	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
sam_grove	5:3f93dd1d4cb3	598	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
sam_grove	5:3f93dd1d4cb3	599
sam_grove	5:3f93dd1d4cb3	600	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
sam_grove	5:3f93dd1d4cb3	601	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
sam_grove	5:3f93dd1d4cb3	602
sam_grove	5:3f93dd1d4cb3	603	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
sam_grove	5:3f93dd1d4cb3	604	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
sam_grove	5:3f93dd1d4cb3	605
sam_grove	5:3f93dd1d4cb3	606	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
sam_grove	5:3f93dd1d4cb3	607	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
sam_grove	5:3f93dd1d4cb3	608
sam_grove	5:3f93dd1d4cb3	609	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
sam_grove	5:3f93dd1d4cb3	610	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
sam_grove	5:3f93dd1d4cb3	611
sam_grove	5:3f93dd1d4cb3	612	/@} end of group CMSIS_SCnotSCB /
sam_grove	5:3f93dd1d4cb3	613
sam_grove	5:3f93dd1d4cb3	614
sam_grove	5:3f93dd1d4cb3	615	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	616	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
sam_grove	5:3f93dd1d4cb3	617	\brief Type definitions for the System Timer Registers.
sam_grove	5:3f93dd1d4cb3	618	@{
sam_grove	5:3f93dd1d4cb3	619	*/
sam_grove	5:3f93dd1d4cb3	620
sam_grove	5:3f93dd1d4cb3	621	/** \brief Structure type to access the System Timer (SysTick).
sam_grove	5:3f93dd1d4cb3	622	*/
sam_grove	5:3f93dd1d4cb3	623	typedef struct
sam_grove	5:3f93dd1d4cb3	624	{
sam_grove	5:3f93dd1d4cb3	625	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
sam_grove	5:3f93dd1d4cb3	626	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
sam_grove	5:3f93dd1d4cb3	627	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
sam_grove	5:3f93dd1d4cb3	628	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
sam_grove	5:3f93dd1d4cb3	629	} SysTick_Type;
sam_grove	5:3f93dd1d4cb3	630
sam_grove	5:3f93dd1d4cb3	631	/* SysTick Control / Status Register Definitions */
sam_grove	5:3f93dd1d4cb3	632	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
sam_grove	5:3f93dd1d4cb3	633	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
sam_grove	5:3f93dd1d4cb3	634
sam_grove	5:3f93dd1d4cb3	635	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
sam_grove	5:3f93dd1d4cb3	636	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
sam_grove	5:3f93dd1d4cb3	637
sam_grove	5:3f93dd1d4cb3	638	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
sam_grove	5:3f93dd1d4cb3	639	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
sam_grove	5:3f93dd1d4cb3	640
sam_grove	5:3f93dd1d4cb3	641	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
sam_grove	5:3f93dd1d4cb3	642	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
sam_grove	5:3f93dd1d4cb3	643
sam_grove	5:3f93dd1d4cb3	644	/* SysTick Reload Register Definitions */
sam_grove	5:3f93dd1d4cb3	645	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
sam_grove	5:3f93dd1d4cb3	646	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
sam_grove	5:3f93dd1d4cb3	647
sam_grove	5:3f93dd1d4cb3	648	/* SysTick Current Register Definitions */
sam_grove	5:3f93dd1d4cb3	649	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
sam_grove	5:3f93dd1d4cb3	650	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
sam_grove	5:3f93dd1d4cb3	651
sam_grove	5:3f93dd1d4cb3	652	/* SysTick Calibration Register Definitions */
sam_grove	5:3f93dd1d4cb3	653	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
sam_grove	5:3f93dd1d4cb3	654	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
sam_grove	5:3f93dd1d4cb3	655
sam_grove	5:3f93dd1d4cb3	656	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
sam_grove	5:3f93dd1d4cb3	657	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
sam_grove	5:3f93dd1d4cb3	658
sam_grove	5:3f93dd1d4cb3	659	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
sam_grove	5:3f93dd1d4cb3	660	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
sam_grove	5:3f93dd1d4cb3	661
sam_grove	5:3f93dd1d4cb3	662	/@} end of group CMSIS_SysTick /
sam_grove	5:3f93dd1d4cb3	663
sam_grove	5:3f93dd1d4cb3	664
sam_grove	5:3f93dd1d4cb3	665	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	666	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
sam_grove	5:3f93dd1d4cb3	667	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
sam_grove	5:3f93dd1d4cb3	668	@{
sam_grove	5:3f93dd1d4cb3	669	*/
sam_grove	5:3f93dd1d4cb3	670
sam_grove	5:3f93dd1d4cb3	671	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
sam_grove	5:3f93dd1d4cb3	672	*/
sam_grove	5:3f93dd1d4cb3	673	typedef struct
sam_grove	5:3f93dd1d4cb3	674	{
sam_grove	5:3f93dd1d4cb3	675	__O union
sam_grove	5:3f93dd1d4cb3	676	{
sam_grove	5:3f93dd1d4cb3	677	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
sam_grove	5:3f93dd1d4cb3	678	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
sam_grove	5:3f93dd1d4cb3	679	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
sam_grove	5:3f93dd1d4cb3	680	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
sam_grove	5:3f93dd1d4cb3	681	uint32_t RESERVED0[864];
sam_grove	5:3f93dd1d4cb3	682	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
sam_grove	5:3f93dd1d4cb3	683	uint32_t RESERVED1[15];
sam_grove	5:3f93dd1d4cb3	684	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
sam_grove	5:3f93dd1d4cb3	685	uint32_t RESERVED2[15];
sam_grove	5:3f93dd1d4cb3	686	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
sam_grove	5:3f93dd1d4cb3	687	uint32_t RESERVED3[29];
sam_grove	5:3f93dd1d4cb3	688	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
sam_grove	5:3f93dd1d4cb3	689	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
sam_grove	5:3f93dd1d4cb3	690	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
sam_grove	5:3f93dd1d4cb3	691	uint32_t RESERVED4[43];
sam_grove	5:3f93dd1d4cb3	692	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
sam_grove	5:3f93dd1d4cb3	693	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
sam_grove	5:3f93dd1d4cb3	694	uint32_t RESERVED5[6];
sam_grove	5:3f93dd1d4cb3	695	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
sam_grove	5:3f93dd1d4cb3	696	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
sam_grove	5:3f93dd1d4cb3	697	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
sam_grove	5:3f93dd1d4cb3	698	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
sam_grove	5:3f93dd1d4cb3	699	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
sam_grove	5:3f93dd1d4cb3	700	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
sam_grove	5:3f93dd1d4cb3	701	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
sam_grove	5:3f93dd1d4cb3	702	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
sam_grove	5:3f93dd1d4cb3	703	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
sam_grove	5:3f93dd1d4cb3	704	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
sam_grove	5:3f93dd1d4cb3	705	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
sam_grove	5:3f93dd1d4cb3	706	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
sam_grove	5:3f93dd1d4cb3	707	} ITM_Type;
sam_grove	5:3f93dd1d4cb3	708
sam_grove	5:3f93dd1d4cb3	709	/* ITM Trace Privilege Register Definitions */
sam_grove	5:3f93dd1d4cb3	710	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
sam_grove	5:3f93dd1d4cb3	711	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
sam_grove	5:3f93dd1d4cb3	712
sam_grove	5:3f93dd1d4cb3	713	/* ITM Trace Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	714	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
sam_grove	5:3f93dd1d4cb3	715	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
sam_grove	5:3f93dd1d4cb3	716
sam_grove	5:3f93dd1d4cb3	717	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
sam_grove	5:3f93dd1d4cb3	718	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
sam_grove	5:3f93dd1d4cb3	719
sam_grove	5:3f93dd1d4cb3	720	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
sam_grove	5:3f93dd1d4cb3	721	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
sam_grove	5:3f93dd1d4cb3	722
sam_grove	5:3f93dd1d4cb3	723	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
sam_grove	5:3f93dd1d4cb3	724	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
sam_grove	5:3f93dd1d4cb3	725
sam_grove	5:3f93dd1d4cb3	726	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
sam_grove	5:3f93dd1d4cb3	727	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
sam_grove	5:3f93dd1d4cb3	728
sam_grove	5:3f93dd1d4cb3	729	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
sam_grove	5:3f93dd1d4cb3	730	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
sam_grove	5:3f93dd1d4cb3	731
sam_grove	5:3f93dd1d4cb3	732	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
sam_grove	5:3f93dd1d4cb3	733	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
sam_grove	5:3f93dd1d4cb3	734
sam_grove	5:3f93dd1d4cb3	735	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
sam_grove	5:3f93dd1d4cb3	736	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
sam_grove	5:3f93dd1d4cb3	737
sam_grove	5:3f93dd1d4cb3	738	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
sam_grove	5:3f93dd1d4cb3	739	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
sam_grove	5:3f93dd1d4cb3	740
sam_grove	5:3f93dd1d4cb3	741	/* ITM Integration Write Register Definitions */
sam_grove	5:3f93dd1d4cb3	742	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
sam_grove	5:3f93dd1d4cb3	743	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
sam_grove	5:3f93dd1d4cb3	744
sam_grove	5:3f93dd1d4cb3	745	/* ITM Integration Read Register Definitions */
sam_grove	5:3f93dd1d4cb3	746	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
sam_grove	5:3f93dd1d4cb3	747	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
sam_grove	5:3f93dd1d4cb3	748
sam_grove	5:3f93dd1d4cb3	749	/* ITM Integration Mode Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	750	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
sam_grove	5:3f93dd1d4cb3	751	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
sam_grove	5:3f93dd1d4cb3	752
sam_grove	5:3f93dd1d4cb3	753	/* ITM Lock Status Register Definitions */
sam_grove	5:3f93dd1d4cb3	754	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
sam_grove	5:3f93dd1d4cb3	755	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
sam_grove	5:3f93dd1d4cb3	756
sam_grove	5:3f93dd1d4cb3	757	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
sam_grove	5:3f93dd1d4cb3	758	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
sam_grove	5:3f93dd1d4cb3	759
sam_grove	5:3f93dd1d4cb3	760	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
sam_grove	5:3f93dd1d4cb3	761	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
sam_grove	5:3f93dd1d4cb3	762
sam_grove	5:3f93dd1d4cb3	763	/@}/ /* end of group CMSIS_ITM */
sam_grove	5:3f93dd1d4cb3	764
sam_grove	5:3f93dd1d4cb3	765
sam_grove	5:3f93dd1d4cb3	766	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	767	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
sam_grove	5:3f93dd1d4cb3	768	\brief Type definitions for the Data Watchpoint and Trace (DWT)
sam_grove	5:3f93dd1d4cb3	769	@{
sam_grove	5:3f93dd1d4cb3	770	*/
sam_grove	5:3f93dd1d4cb3	771
sam_grove	5:3f93dd1d4cb3	772	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
sam_grove	5:3f93dd1d4cb3	773	*/
sam_grove	5:3f93dd1d4cb3	774	typedef struct
sam_grove	5:3f93dd1d4cb3	775	{
sam_grove	5:3f93dd1d4cb3	776	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
sam_grove	5:3f93dd1d4cb3	777	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
sam_grove	5:3f93dd1d4cb3	778	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
sam_grove	5:3f93dd1d4cb3	779	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
sam_grove	5:3f93dd1d4cb3	780	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
sam_grove	5:3f93dd1d4cb3	781	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
sam_grove	5:3f93dd1d4cb3	782	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
sam_grove	5:3f93dd1d4cb3	783	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
sam_grove	5:3f93dd1d4cb3	784	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
sam_grove	5:3f93dd1d4cb3	785	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
sam_grove	5:3f93dd1d4cb3	786	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
sam_grove	5:3f93dd1d4cb3	787	uint32_t RESERVED0[1];
sam_grove	5:3f93dd1d4cb3	788	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
sam_grove	5:3f93dd1d4cb3	789	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
sam_grove	5:3f93dd1d4cb3	790	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
sam_grove	5:3f93dd1d4cb3	791	uint32_t RESERVED1[1];
sam_grove	5:3f93dd1d4cb3	792	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
sam_grove	5:3f93dd1d4cb3	793	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
sam_grove	5:3f93dd1d4cb3	794	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
sam_grove	5:3f93dd1d4cb3	795	uint32_t RESERVED2[1];
sam_grove	5:3f93dd1d4cb3	796	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
sam_grove	5:3f93dd1d4cb3	797	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
sam_grove	5:3f93dd1d4cb3	798	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
sam_grove	5:3f93dd1d4cb3	799	} DWT_Type;
sam_grove	5:3f93dd1d4cb3	800
sam_grove	5:3f93dd1d4cb3	801	/* DWT Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	802	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
sam_grove	5:3f93dd1d4cb3	803	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
sam_grove	5:3f93dd1d4cb3	804
sam_grove	5:3f93dd1d4cb3	805	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
sam_grove	5:3f93dd1d4cb3	806	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
sam_grove	5:3f93dd1d4cb3	807
sam_grove	5:3f93dd1d4cb3	808	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
sam_grove	5:3f93dd1d4cb3	809	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
sam_grove	5:3f93dd1d4cb3	810
sam_grove	5:3f93dd1d4cb3	811	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
sam_grove	5:3f93dd1d4cb3	812	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
sam_grove	5:3f93dd1d4cb3	813
sam_grove	5:3f93dd1d4cb3	814	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
sam_grove	5:3f93dd1d4cb3	815	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
sam_grove	5:3f93dd1d4cb3	816
sam_grove	5:3f93dd1d4cb3	817	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
sam_grove	5:3f93dd1d4cb3	818	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
sam_grove	5:3f93dd1d4cb3	819
sam_grove	5:3f93dd1d4cb3	820	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
sam_grove	5:3f93dd1d4cb3	821	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
sam_grove	5:3f93dd1d4cb3	822
sam_grove	5:3f93dd1d4cb3	823	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
sam_grove	5:3f93dd1d4cb3	824	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
sam_grove	5:3f93dd1d4cb3	825
sam_grove	5:3f93dd1d4cb3	826	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
sam_grove	5:3f93dd1d4cb3	827	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
sam_grove	5:3f93dd1d4cb3	828
sam_grove	5:3f93dd1d4cb3	829	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
sam_grove	5:3f93dd1d4cb3	830	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
sam_grove	5:3f93dd1d4cb3	831
sam_grove	5:3f93dd1d4cb3	832	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
sam_grove	5:3f93dd1d4cb3	833	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
sam_grove	5:3f93dd1d4cb3	834
sam_grove	5:3f93dd1d4cb3	835	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
sam_grove	5:3f93dd1d4cb3	836	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
sam_grove	5:3f93dd1d4cb3	837
sam_grove	5:3f93dd1d4cb3	838	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
sam_grove	5:3f93dd1d4cb3	839	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
sam_grove	5:3f93dd1d4cb3	840
sam_grove	5:3f93dd1d4cb3	841	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
sam_grove	5:3f93dd1d4cb3	842	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
sam_grove	5:3f93dd1d4cb3	843
sam_grove	5:3f93dd1d4cb3	844	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
sam_grove	5:3f93dd1d4cb3	845	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
sam_grove	5:3f93dd1d4cb3	846
sam_grove	5:3f93dd1d4cb3	847	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
sam_grove	5:3f93dd1d4cb3	848	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
sam_grove	5:3f93dd1d4cb3	849
sam_grove	5:3f93dd1d4cb3	850	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
sam_grove	5:3f93dd1d4cb3	851	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
sam_grove	5:3f93dd1d4cb3	852
sam_grove	5:3f93dd1d4cb3	853	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
sam_grove	5:3f93dd1d4cb3	854	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
sam_grove	5:3f93dd1d4cb3	855
sam_grove	5:3f93dd1d4cb3	856	/* DWT CPI Count Register Definitions */
sam_grove	5:3f93dd1d4cb3	857	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
sam_grove	5:3f93dd1d4cb3	858	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
sam_grove	5:3f93dd1d4cb3	859
sam_grove	5:3f93dd1d4cb3	860	/* DWT Exception Overhead Count Register Definitions */
sam_grove	5:3f93dd1d4cb3	861	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
sam_grove	5:3f93dd1d4cb3	862	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
sam_grove	5:3f93dd1d4cb3	863
sam_grove	5:3f93dd1d4cb3	864	/* DWT Sleep Count Register Definitions */
sam_grove	5:3f93dd1d4cb3	865	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
sam_grove	5:3f93dd1d4cb3	866	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
sam_grove	5:3f93dd1d4cb3	867
sam_grove	5:3f93dd1d4cb3	868	/* DWT LSU Count Register Definitions */
sam_grove	5:3f93dd1d4cb3	869	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
sam_grove	5:3f93dd1d4cb3	870	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
sam_grove	5:3f93dd1d4cb3	871
sam_grove	5:3f93dd1d4cb3	872	/* DWT Folded-instruction Count Register Definitions */
sam_grove	5:3f93dd1d4cb3	873	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
sam_grove	5:3f93dd1d4cb3	874	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
sam_grove	5:3f93dd1d4cb3	875
sam_grove	5:3f93dd1d4cb3	876	/* DWT Comparator Mask Register Definitions */
sam_grove	5:3f93dd1d4cb3	877	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
sam_grove	5:3f93dd1d4cb3	878	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
sam_grove	5:3f93dd1d4cb3	879
sam_grove	5:3f93dd1d4cb3	880	/* DWT Comparator Function Register Definitions */
sam_grove	5:3f93dd1d4cb3	881	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
sam_grove	5:3f93dd1d4cb3	882	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
sam_grove	5:3f93dd1d4cb3	883
sam_grove	5:3f93dd1d4cb3	884	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
sam_grove	5:3f93dd1d4cb3	885	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
sam_grove	5:3f93dd1d4cb3	886
sam_grove	5:3f93dd1d4cb3	887	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
sam_grove	5:3f93dd1d4cb3	888	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
sam_grove	5:3f93dd1d4cb3	889
sam_grove	5:3f93dd1d4cb3	890	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
sam_grove	5:3f93dd1d4cb3	891	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
sam_grove	5:3f93dd1d4cb3	892
sam_grove	5:3f93dd1d4cb3	893	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
sam_grove	5:3f93dd1d4cb3	894	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
sam_grove	5:3f93dd1d4cb3	895
sam_grove	5:3f93dd1d4cb3	896	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
sam_grove	5:3f93dd1d4cb3	897	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
sam_grove	5:3f93dd1d4cb3	898
sam_grove	5:3f93dd1d4cb3	899	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
sam_grove	5:3f93dd1d4cb3	900	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
sam_grove	5:3f93dd1d4cb3	901
sam_grove	5:3f93dd1d4cb3	902	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
sam_grove	5:3f93dd1d4cb3	903	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
sam_grove	5:3f93dd1d4cb3	904
sam_grove	5:3f93dd1d4cb3	905	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
sam_grove	5:3f93dd1d4cb3	906	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
sam_grove	5:3f93dd1d4cb3	907
sam_grove	5:3f93dd1d4cb3	908	/@}/ /* end of group CMSIS_DWT */
sam_grove	5:3f93dd1d4cb3	909
sam_grove	5:3f93dd1d4cb3	910
sam_grove	5:3f93dd1d4cb3	911	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	912	\defgroup CMSIS_TPI Trace Port Interface (TPI)
sam_grove	5:3f93dd1d4cb3	913	\brief Type definitions for the Trace Port Interface (TPI)
sam_grove	5:3f93dd1d4cb3	914	@{
sam_grove	5:3f93dd1d4cb3	915	*/
sam_grove	5:3f93dd1d4cb3	916
sam_grove	5:3f93dd1d4cb3	917	/** \brief Structure type to access the Trace Port Interface Register (TPI).
sam_grove	5:3f93dd1d4cb3	918	*/
sam_grove	5:3f93dd1d4cb3	919	typedef struct
sam_grove	5:3f93dd1d4cb3	920	{
sam_grove	5:3f93dd1d4cb3	921	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
sam_grove	5:3f93dd1d4cb3	922	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
sam_grove	5:3f93dd1d4cb3	923	uint32_t RESERVED0[2];
sam_grove	5:3f93dd1d4cb3	924	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
sam_grove	5:3f93dd1d4cb3	925	uint32_t RESERVED1[55];
sam_grove	5:3f93dd1d4cb3	926	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
sam_grove	5:3f93dd1d4cb3	927	uint32_t RESERVED2[131];
sam_grove	5:3f93dd1d4cb3	928	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
sam_grove	5:3f93dd1d4cb3	929	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
sam_grove	5:3f93dd1d4cb3	930	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
sam_grove	5:3f93dd1d4cb3	931	uint32_t RESERVED3[759];
sam_grove	5:3f93dd1d4cb3	932	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
sam_grove	5:3f93dd1d4cb3	933	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
sam_grove	5:3f93dd1d4cb3	934	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
sam_grove	5:3f93dd1d4cb3	935	uint32_t RESERVED4[1];
sam_grove	5:3f93dd1d4cb3	936	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
sam_grove	5:3f93dd1d4cb3	937	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
sam_grove	5:3f93dd1d4cb3	938	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
sam_grove	5:3f93dd1d4cb3	939	uint32_t RESERVED5[39];
sam_grove	5:3f93dd1d4cb3	940	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
sam_grove	5:3f93dd1d4cb3	941	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
sam_grove	5:3f93dd1d4cb3	942	uint32_t RESERVED7[8];
sam_grove	5:3f93dd1d4cb3	943	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
sam_grove	5:3f93dd1d4cb3	944	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
sam_grove	5:3f93dd1d4cb3	945	} TPI_Type;
sam_grove	5:3f93dd1d4cb3	946
sam_grove	5:3f93dd1d4cb3	947	/* TPI Asynchronous Clock Prescaler Register Definitions */
sam_grove	5:3f93dd1d4cb3	948	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
sam_grove	5:3f93dd1d4cb3	949	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
sam_grove	5:3f93dd1d4cb3	950
sam_grove	5:3f93dd1d4cb3	951	/* TPI Selected Pin Protocol Register Definitions */
sam_grove	5:3f93dd1d4cb3	952	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
sam_grove	5:3f93dd1d4cb3	953	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
sam_grove	5:3f93dd1d4cb3	954
sam_grove	5:3f93dd1d4cb3	955	/* TPI Formatter and Flush Status Register Definitions */
sam_grove	5:3f93dd1d4cb3	956	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
sam_grove	5:3f93dd1d4cb3	957	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
sam_grove	5:3f93dd1d4cb3	958
sam_grove	5:3f93dd1d4cb3	959	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
sam_grove	5:3f93dd1d4cb3	960	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
sam_grove	5:3f93dd1d4cb3	961
sam_grove	5:3f93dd1d4cb3	962	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
sam_grove	5:3f93dd1d4cb3	963	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
sam_grove	5:3f93dd1d4cb3	964
sam_grove	5:3f93dd1d4cb3	965	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
sam_grove	5:3f93dd1d4cb3	966	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
sam_grove	5:3f93dd1d4cb3	967
sam_grove	5:3f93dd1d4cb3	968	/* TPI Formatter and Flush Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	969	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
sam_grove	5:3f93dd1d4cb3	970	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
sam_grove	5:3f93dd1d4cb3	971
sam_grove	5:3f93dd1d4cb3	972	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
sam_grove	5:3f93dd1d4cb3	973	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
sam_grove	5:3f93dd1d4cb3	974
sam_grove	5:3f93dd1d4cb3	975	/* TPI TRIGGER Register Definitions */
sam_grove	5:3f93dd1d4cb3	976	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
sam_grove	5:3f93dd1d4cb3	977	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
sam_grove	5:3f93dd1d4cb3	978
sam_grove	5:3f93dd1d4cb3	979	/* TPI Integration ETM Data Register Definitions (FIFO0) */
sam_grove	5:3f93dd1d4cb3	980	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
sam_grove	5:3f93dd1d4cb3	981	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
sam_grove	5:3f93dd1d4cb3	982
sam_grove	5:3f93dd1d4cb3	983	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
sam_grove	5:3f93dd1d4cb3	984	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
sam_grove	5:3f93dd1d4cb3	985
sam_grove	5:3f93dd1d4cb3	986	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
sam_grove	5:3f93dd1d4cb3	987	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
sam_grove	5:3f93dd1d4cb3	988
sam_grove	5:3f93dd1d4cb3	989	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
sam_grove	5:3f93dd1d4cb3	990	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
sam_grove	5:3f93dd1d4cb3	991
sam_grove	5:3f93dd1d4cb3	992	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
sam_grove	5:3f93dd1d4cb3	993	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
sam_grove	5:3f93dd1d4cb3	994
sam_grove	5:3f93dd1d4cb3	995	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
sam_grove	5:3f93dd1d4cb3	996	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
sam_grove	5:3f93dd1d4cb3	997
sam_grove	5:3f93dd1d4cb3	998	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
sam_grove	5:3f93dd1d4cb3	999	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
sam_grove	5:3f93dd1d4cb3	1000
sam_grove	5:3f93dd1d4cb3	1001	/* TPI ITATBCTR2 Register Definitions */
sam_grove	5:3f93dd1d4cb3	1002	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
sam_grove	5:3f93dd1d4cb3	1003	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
sam_grove	5:3f93dd1d4cb3	1004
sam_grove	5:3f93dd1d4cb3	1005	/* TPI Integration ITM Data Register Definitions (FIFO1) */
sam_grove	5:3f93dd1d4cb3	1006	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
sam_grove	5:3f93dd1d4cb3	1007	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
sam_grove	5:3f93dd1d4cb3	1008
sam_grove	5:3f93dd1d4cb3	1009	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
sam_grove	5:3f93dd1d4cb3	1010	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
sam_grove	5:3f93dd1d4cb3	1011
sam_grove	5:3f93dd1d4cb3	1012	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
sam_grove	5:3f93dd1d4cb3	1013	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
sam_grove	5:3f93dd1d4cb3	1014
sam_grove	5:3f93dd1d4cb3	1015	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
sam_grove	5:3f93dd1d4cb3	1016	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
sam_grove	5:3f93dd1d4cb3	1017
sam_grove	5:3f93dd1d4cb3	1018	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
sam_grove	5:3f93dd1d4cb3	1019	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
sam_grove	5:3f93dd1d4cb3	1020
sam_grove	5:3f93dd1d4cb3	1021	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
sam_grove	5:3f93dd1d4cb3	1022	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
sam_grove	5:3f93dd1d4cb3	1023
sam_grove	5:3f93dd1d4cb3	1024	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
sam_grove	5:3f93dd1d4cb3	1025	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
sam_grove	5:3f93dd1d4cb3	1026
sam_grove	5:3f93dd1d4cb3	1027	/* TPI ITATBCTR0 Register Definitions */
sam_grove	5:3f93dd1d4cb3	1028	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
sam_grove	5:3f93dd1d4cb3	1029	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
sam_grove	5:3f93dd1d4cb3	1030
sam_grove	5:3f93dd1d4cb3	1031	/* TPI Integration Mode Control Register Definitions */
sam_grove	5:3f93dd1d4cb3	1032	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
sam_grove	5:3f93dd1d4cb3	1033	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
sam_grove	5:3f93dd1d4cb3	1034
sam_grove	5:3f93dd1d4cb3	1035	/* TPI DEVID Register Definitions */
sam_grove	5:3f93dd1d4cb3	1036	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
sam_grove	5:3f93dd1d4cb3	1037	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
sam_grove	5:3f93dd1d4cb3	1038
sam_grove	5:3f93dd1d4cb3	1039	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
sam_grove	5:3f93dd1d4cb3	1040	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
sam_grove	5:3f93dd1d4cb3	1041
sam_grove	5:3f93dd1d4cb3	1042	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
sam_grove	5:3f93dd1d4cb3	1043	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
sam_grove	5:3f93dd1d4cb3	1044
sam_grove	5:3f93dd1d4cb3	1045	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
sam_grove	5:3f93dd1d4cb3	1046	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
sam_grove	5:3f93dd1d4cb3	1047
sam_grove	5:3f93dd1d4cb3	1048	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
sam_grove	5:3f93dd1d4cb3	1049	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
sam_grove	5:3f93dd1d4cb3	1050
sam_grove	5:3f93dd1d4cb3	1051	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
sam_grove	5:3f93dd1d4cb3	1052	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
sam_grove	5:3f93dd1d4cb3	1053
sam_grove	5:3f93dd1d4cb3	1054	/* TPI DEVTYPE Register Definitions */
sam_grove	5:3f93dd1d4cb3	1055	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
sam_grove	5:3f93dd1d4cb3	1056	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
sam_grove	5:3f93dd1d4cb3	1057
sam_grove	5:3f93dd1d4cb3	1058	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
sam_grove	5:3f93dd1d4cb3	1059	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
sam_grove	5:3f93dd1d4cb3	1060
sam_grove	5:3f93dd1d4cb3	1061	/@}/ /* end of group CMSIS_TPI */
sam_grove	5:3f93dd1d4cb3	1062
sam_grove	5:3f93dd1d4cb3	1063
sam_grove	5:3f93dd1d4cb3	1064	#if (__MPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	1065	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	1066	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
sam_grove	5:3f93dd1d4cb3	1067	\brief Type definitions for the Memory Protection Unit (MPU)
sam_grove	5:3f93dd1d4cb3	1068	@{
sam_grove	5:3f93dd1d4cb3	1069	*/
sam_grove	5:3f93dd1d4cb3	1070
sam_grove	5:3f93dd1d4cb3	1071	/** \brief Structure type to access the Memory Protection Unit (MPU).
sam_grove	5:3f93dd1d4cb3	1072	*/
sam_grove	5:3f93dd1d4cb3	1073	typedef struct
sam_grove	5:3f93dd1d4cb3	1074	{
sam_grove	5:3f93dd1d4cb3	1075	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
sam_grove	5:3f93dd1d4cb3	1076	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
sam_grove	5:3f93dd1d4cb3	1077	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
sam_grove	5:3f93dd1d4cb3	1078	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
sam_grove	5:3f93dd1d4cb3	1079	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
sam_grove	5:3f93dd1d4cb3	1080	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
sam_grove	5:3f93dd1d4cb3	1081	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
sam_grove	5:3f93dd1d4cb3	1082	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
sam_grove	5:3f93dd1d4cb3	1083	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
sam_grove	5:3f93dd1d4cb3	1084	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
sam_grove	5:3f93dd1d4cb3	1085	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
sam_grove	5:3f93dd1d4cb3	1086	} MPU_Type;
sam_grove	5:3f93dd1d4cb3	1087
sam_grove	5:3f93dd1d4cb3	1088	/* MPU Type Register */
sam_grove	5:3f93dd1d4cb3	1089	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
sam_grove	5:3f93dd1d4cb3	1090	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
sam_grove	5:3f93dd1d4cb3	1091
sam_grove	5:3f93dd1d4cb3	1092	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
sam_grove	5:3f93dd1d4cb3	1093	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
sam_grove	5:3f93dd1d4cb3	1094
sam_grove	5:3f93dd1d4cb3	1095	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
sam_grove	5:3f93dd1d4cb3	1096	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
sam_grove	5:3f93dd1d4cb3	1097
sam_grove	5:3f93dd1d4cb3	1098	/* MPU Control Register */
sam_grove	5:3f93dd1d4cb3	1099	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
sam_grove	5:3f93dd1d4cb3	1100	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
sam_grove	5:3f93dd1d4cb3	1101
sam_grove	5:3f93dd1d4cb3	1102	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
sam_grove	5:3f93dd1d4cb3	1103	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
sam_grove	5:3f93dd1d4cb3	1104
sam_grove	5:3f93dd1d4cb3	1105	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
sam_grove	5:3f93dd1d4cb3	1106	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
sam_grove	5:3f93dd1d4cb3	1107
sam_grove	5:3f93dd1d4cb3	1108	/* MPU Region Number Register */
sam_grove	5:3f93dd1d4cb3	1109	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
sam_grove	5:3f93dd1d4cb3	1110	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
sam_grove	5:3f93dd1d4cb3	1111
sam_grove	5:3f93dd1d4cb3	1112	/* MPU Region Base Address Register */
sam_grove	5:3f93dd1d4cb3	1113	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
sam_grove	5:3f93dd1d4cb3	1114	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
sam_grove	5:3f93dd1d4cb3	1115
sam_grove	5:3f93dd1d4cb3	1116	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
sam_grove	5:3f93dd1d4cb3	1117	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
sam_grove	5:3f93dd1d4cb3	1118
sam_grove	5:3f93dd1d4cb3	1119	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
sam_grove	5:3f93dd1d4cb3	1120	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
sam_grove	5:3f93dd1d4cb3	1121
sam_grove	5:3f93dd1d4cb3	1122	/* MPU Region Attribute and Size Register */
sam_grove	5:3f93dd1d4cb3	1123	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
sam_grove	5:3f93dd1d4cb3	1124	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
sam_grove	5:3f93dd1d4cb3	1125
sam_grove	5:3f93dd1d4cb3	1126	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
sam_grove	5:3f93dd1d4cb3	1127	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
sam_grove	5:3f93dd1d4cb3	1128
sam_grove	5:3f93dd1d4cb3	1129	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
sam_grove	5:3f93dd1d4cb3	1130	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
sam_grove	5:3f93dd1d4cb3	1131
sam_grove	5:3f93dd1d4cb3	1132	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
sam_grove	5:3f93dd1d4cb3	1133	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
sam_grove	5:3f93dd1d4cb3	1134
sam_grove	5:3f93dd1d4cb3	1135	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
sam_grove	5:3f93dd1d4cb3	1136	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
sam_grove	5:3f93dd1d4cb3	1137
sam_grove	5:3f93dd1d4cb3	1138	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
sam_grove	5:3f93dd1d4cb3	1139	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
sam_grove	5:3f93dd1d4cb3	1140
sam_grove	5:3f93dd1d4cb3	1141	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
sam_grove	5:3f93dd1d4cb3	1142	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
sam_grove	5:3f93dd1d4cb3	1143
sam_grove	5:3f93dd1d4cb3	1144	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
sam_grove	5:3f93dd1d4cb3	1145	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
sam_grove	5:3f93dd1d4cb3	1146
sam_grove	5:3f93dd1d4cb3	1147	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
sam_grove	5:3f93dd1d4cb3	1148	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
sam_grove	5:3f93dd1d4cb3	1149
sam_grove	5:3f93dd1d4cb3	1150	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
sam_grove	5:3f93dd1d4cb3	1151	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
sam_grove	5:3f93dd1d4cb3	1152
sam_grove	5:3f93dd1d4cb3	1153	/@} end of group CMSIS_MPU /
sam_grove	5:3f93dd1d4cb3	1154	#endif
sam_grove	5:3f93dd1d4cb3	1155
sam_grove	5:3f93dd1d4cb3	1156
sam_grove	5:3f93dd1d4cb3	1157	#if (__FPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	1158	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	1159	\defgroup CMSIS_FPU Floating Point Unit (FPU)
sam_grove	5:3f93dd1d4cb3	1160	\brief Type definitions for the Floating Point Unit (FPU)
sam_grove	5:3f93dd1d4cb3	1161	@{
sam_grove	5:3f93dd1d4cb3	1162	*/
sam_grove	5:3f93dd1d4cb3	1163
sam_grove	5:3f93dd1d4cb3	1164	/** \brief Structure type to access the Floating Point Unit (FPU).
sam_grove	5:3f93dd1d4cb3	1165	*/
sam_grove	5:3f93dd1d4cb3	1166	typedef struct
sam_grove	5:3f93dd1d4cb3	1167	{
sam_grove	5:3f93dd1d4cb3	1168	uint32_t RESERVED0[1];
sam_grove	5:3f93dd1d4cb3	1169	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
sam_grove	5:3f93dd1d4cb3	1170	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
sam_grove	5:3f93dd1d4cb3	1171	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
sam_grove	5:3f93dd1d4cb3	1172	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
sam_grove	5:3f93dd1d4cb3	1173	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
sam_grove	5:3f93dd1d4cb3	1174	} FPU_Type;
sam_grove	5:3f93dd1d4cb3	1175
sam_grove	5:3f93dd1d4cb3	1176	/* Floating-Point Context Control Register */
sam_grove	5:3f93dd1d4cb3	1177	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
sam_grove	5:3f93dd1d4cb3	1178	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
sam_grove	5:3f93dd1d4cb3	1179
sam_grove	5:3f93dd1d4cb3	1180	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
sam_grove	5:3f93dd1d4cb3	1181	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
sam_grove	5:3f93dd1d4cb3	1182
sam_grove	5:3f93dd1d4cb3	1183	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
sam_grove	5:3f93dd1d4cb3	1184	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
sam_grove	5:3f93dd1d4cb3	1185
sam_grove	5:3f93dd1d4cb3	1186	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
sam_grove	5:3f93dd1d4cb3	1187	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
sam_grove	5:3f93dd1d4cb3	1188
sam_grove	5:3f93dd1d4cb3	1189	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
sam_grove	5:3f93dd1d4cb3	1190	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
sam_grove	5:3f93dd1d4cb3	1191
sam_grove	5:3f93dd1d4cb3	1192	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
sam_grove	5:3f93dd1d4cb3	1193	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
sam_grove	5:3f93dd1d4cb3	1194
sam_grove	5:3f93dd1d4cb3	1195	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
sam_grove	5:3f93dd1d4cb3	1196	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
sam_grove	5:3f93dd1d4cb3	1197
sam_grove	5:3f93dd1d4cb3	1198	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
sam_grove	5:3f93dd1d4cb3	1199	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
sam_grove	5:3f93dd1d4cb3	1200
sam_grove	5:3f93dd1d4cb3	1201	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
sam_grove	5:3f93dd1d4cb3	1202	#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /!< FPCCR: Lazy state preservation active bit Mask /
sam_grove	5:3f93dd1d4cb3	1203
sam_grove	5:3f93dd1d4cb3	1204	/* Floating-Point Context Address Register */
sam_grove	5:3f93dd1d4cb3	1205	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
sam_grove	5:3f93dd1d4cb3	1206	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
sam_grove	5:3f93dd1d4cb3	1207
sam_grove	5:3f93dd1d4cb3	1208	/* Floating-Point Default Status Control Register */
sam_grove	5:3f93dd1d4cb3	1209	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
sam_grove	5:3f93dd1d4cb3	1210	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
sam_grove	5:3f93dd1d4cb3	1211
sam_grove	5:3f93dd1d4cb3	1212	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
sam_grove	5:3f93dd1d4cb3	1213	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
sam_grove	5:3f93dd1d4cb3	1214
sam_grove	5:3f93dd1d4cb3	1215	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
sam_grove	5:3f93dd1d4cb3	1216	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
sam_grove	5:3f93dd1d4cb3	1217
sam_grove	5:3f93dd1d4cb3	1218	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
sam_grove	5:3f93dd1d4cb3	1219	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
sam_grove	5:3f93dd1d4cb3	1220
sam_grove	5:3f93dd1d4cb3	1221	/* Media and FP Feature Register 0 */
sam_grove	5:3f93dd1d4cb3	1222	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
sam_grove	5:3f93dd1d4cb3	1223	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
sam_grove	5:3f93dd1d4cb3	1224
sam_grove	5:3f93dd1d4cb3	1225	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
sam_grove	5:3f93dd1d4cb3	1226	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
sam_grove	5:3f93dd1d4cb3	1227
sam_grove	5:3f93dd1d4cb3	1228	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
sam_grove	5:3f93dd1d4cb3	1229	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
sam_grove	5:3f93dd1d4cb3	1230
sam_grove	5:3f93dd1d4cb3	1231	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
sam_grove	5:3f93dd1d4cb3	1232	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
sam_grove	5:3f93dd1d4cb3	1233
sam_grove	5:3f93dd1d4cb3	1234	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
sam_grove	5:3f93dd1d4cb3	1235	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
sam_grove	5:3f93dd1d4cb3	1236
sam_grove	5:3f93dd1d4cb3	1237	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
sam_grove	5:3f93dd1d4cb3	1238	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
sam_grove	5:3f93dd1d4cb3	1239
sam_grove	5:3f93dd1d4cb3	1240	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
sam_grove	5:3f93dd1d4cb3	1241	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
sam_grove	5:3f93dd1d4cb3	1242
sam_grove	5:3f93dd1d4cb3	1243	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
sam_grove	5:3f93dd1d4cb3	1244	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /!< MVFR0: A_SIMD registers bits Mask /
sam_grove	5:3f93dd1d4cb3	1245
sam_grove	5:3f93dd1d4cb3	1246	/* Media and FP Feature Register 1 */
sam_grove	5:3f93dd1d4cb3	1247	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
sam_grove	5:3f93dd1d4cb3	1248	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
sam_grove	5:3f93dd1d4cb3	1249
sam_grove	5:3f93dd1d4cb3	1250	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
sam_grove	5:3f93dd1d4cb3	1251	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
sam_grove	5:3f93dd1d4cb3	1252
sam_grove	5:3f93dd1d4cb3	1253	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
sam_grove	5:3f93dd1d4cb3	1254	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
sam_grove	5:3f93dd1d4cb3	1255
sam_grove	5:3f93dd1d4cb3	1256	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
sam_grove	5:3f93dd1d4cb3	1257	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /!< MVFR1: FtZ mode bits Mask /
sam_grove	5:3f93dd1d4cb3	1258
sam_grove	5:3f93dd1d4cb3	1259	/@} end of group CMSIS_FPU /
sam_grove	5:3f93dd1d4cb3	1260	#endif
sam_grove	5:3f93dd1d4cb3	1261
sam_grove	5:3f93dd1d4cb3	1262
sam_grove	5:3f93dd1d4cb3	1263	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	1264	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
sam_grove	5:3f93dd1d4cb3	1265	\brief Type definitions for the Core Debug Registers
sam_grove	5:3f93dd1d4cb3	1266	@{
sam_grove	5:3f93dd1d4cb3	1267	*/
sam_grove	5:3f93dd1d4cb3	1268
sam_grove	5:3f93dd1d4cb3	1269	/** \brief Structure type to access the Core Debug Register (CoreDebug).
sam_grove	5:3f93dd1d4cb3	1270	*/
sam_grove	5:3f93dd1d4cb3	1271	typedef struct
sam_grove	5:3f93dd1d4cb3	1272	{
sam_grove	5:3f93dd1d4cb3	1273	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
sam_grove	5:3f93dd1d4cb3	1274	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
sam_grove	5:3f93dd1d4cb3	1275	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
sam_grove	5:3f93dd1d4cb3	1276	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
sam_grove	5:3f93dd1d4cb3	1277	} CoreDebug_Type;
sam_grove	5:3f93dd1d4cb3	1278
sam_grove	5:3f93dd1d4cb3	1279	/* Debug Halting Control and Status Register */
sam_grove	5:3f93dd1d4cb3	1280	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
sam_grove	5:3f93dd1d4cb3	1281	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
sam_grove	5:3f93dd1d4cb3	1282
sam_grove	5:3f93dd1d4cb3	1283	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
sam_grove	5:3f93dd1d4cb3	1284	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
sam_grove	5:3f93dd1d4cb3	1285
sam_grove	5:3f93dd1d4cb3	1286	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
sam_grove	5:3f93dd1d4cb3	1287	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
sam_grove	5:3f93dd1d4cb3	1288
sam_grove	5:3f93dd1d4cb3	1289	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
sam_grove	5:3f93dd1d4cb3	1290	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
sam_grove	5:3f93dd1d4cb3	1291
sam_grove	5:3f93dd1d4cb3	1292	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
sam_grove	5:3f93dd1d4cb3	1293	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
sam_grove	5:3f93dd1d4cb3	1294
sam_grove	5:3f93dd1d4cb3	1295	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
sam_grove	5:3f93dd1d4cb3	1296	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
sam_grove	5:3f93dd1d4cb3	1297
sam_grove	5:3f93dd1d4cb3	1298	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
sam_grove	5:3f93dd1d4cb3	1299	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
sam_grove	5:3f93dd1d4cb3	1300
sam_grove	5:3f93dd1d4cb3	1301	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
sam_grove	5:3f93dd1d4cb3	1302	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
sam_grove	5:3f93dd1d4cb3	1303
sam_grove	5:3f93dd1d4cb3	1304	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
sam_grove	5:3f93dd1d4cb3	1305	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
sam_grove	5:3f93dd1d4cb3	1306
sam_grove	5:3f93dd1d4cb3	1307	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
sam_grove	5:3f93dd1d4cb3	1308	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
sam_grove	5:3f93dd1d4cb3	1309
sam_grove	5:3f93dd1d4cb3	1310	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
sam_grove	5:3f93dd1d4cb3	1311	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
sam_grove	5:3f93dd1d4cb3	1312
sam_grove	5:3f93dd1d4cb3	1313	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
sam_grove	5:3f93dd1d4cb3	1314	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
sam_grove	5:3f93dd1d4cb3	1315
sam_grove	5:3f93dd1d4cb3	1316	/* Debug Core Register Selector Register */
sam_grove	5:3f93dd1d4cb3	1317	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
sam_grove	5:3f93dd1d4cb3	1318	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
sam_grove	5:3f93dd1d4cb3	1319
sam_grove	5:3f93dd1d4cb3	1320	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
sam_grove	5:3f93dd1d4cb3	1321	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
sam_grove	5:3f93dd1d4cb3	1322
sam_grove	5:3f93dd1d4cb3	1323	/* Debug Exception and Monitor Control Register */
sam_grove	5:3f93dd1d4cb3	1324	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
sam_grove	5:3f93dd1d4cb3	1325	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
sam_grove	5:3f93dd1d4cb3	1326
sam_grove	5:3f93dd1d4cb3	1327	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
sam_grove	5:3f93dd1d4cb3	1328	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
sam_grove	5:3f93dd1d4cb3	1329
sam_grove	5:3f93dd1d4cb3	1330	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
sam_grove	5:3f93dd1d4cb3	1331	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
sam_grove	5:3f93dd1d4cb3	1332
sam_grove	5:3f93dd1d4cb3	1333	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
sam_grove	5:3f93dd1d4cb3	1334	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
sam_grove	5:3f93dd1d4cb3	1335
sam_grove	5:3f93dd1d4cb3	1336	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
sam_grove	5:3f93dd1d4cb3	1337	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
sam_grove	5:3f93dd1d4cb3	1338
sam_grove	5:3f93dd1d4cb3	1339	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
sam_grove	5:3f93dd1d4cb3	1340	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
sam_grove	5:3f93dd1d4cb3	1341
sam_grove	5:3f93dd1d4cb3	1342	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
sam_grove	5:3f93dd1d4cb3	1343	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
sam_grove	5:3f93dd1d4cb3	1344
sam_grove	5:3f93dd1d4cb3	1345	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
sam_grove	5:3f93dd1d4cb3	1346	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
sam_grove	5:3f93dd1d4cb3	1347
sam_grove	5:3f93dd1d4cb3	1348	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
sam_grove	5:3f93dd1d4cb3	1349	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
sam_grove	5:3f93dd1d4cb3	1350
sam_grove	5:3f93dd1d4cb3	1351	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
sam_grove	5:3f93dd1d4cb3	1352	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
sam_grove	5:3f93dd1d4cb3	1353
sam_grove	5:3f93dd1d4cb3	1354	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
sam_grove	5:3f93dd1d4cb3	1355	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
sam_grove	5:3f93dd1d4cb3	1356
sam_grove	5:3f93dd1d4cb3	1357	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
sam_grove	5:3f93dd1d4cb3	1358	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
sam_grove	5:3f93dd1d4cb3	1359
sam_grove	5:3f93dd1d4cb3	1360	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
sam_grove	5:3f93dd1d4cb3	1361	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
sam_grove	5:3f93dd1d4cb3	1362
sam_grove	5:3f93dd1d4cb3	1363	/@} end of group CMSIS_CoreDebug /
sam_grove	5:3f93dd1d4cb3	1364
sam_grove	5:3f93dd1d4cb3	1365
sam_grove	5:3f93dd1d4cb3	1366	/** \ingroup CMSIS_core_register
sam_grove	5:3f93dd1d4cb3	1367	\defgroup CMSIS_core_base Core Definitions
sam_grove	5:3f93dd1d4cb3	1368	\brief Definitions for base addresses, unions, and structures.
sam_grove	5:3f93dd1d4cb3	1369	@{
sam_grove	5:3f93dd1d4cb3	1370	*/
sam_grove	5:3f93dd1d4cb3	1371
sam_grove	5:3f93dd1d4cb3	1372	/* Memory mapping of Cortex-M4 Hardware */
sam_grove	5:3f93dd1d4cb3	1373	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
sam_grove	5:3f93dd1d4cb3	1374	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
sam_grove	5:3f93dd1d4cb3	1375	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
sam_grove	5:3f93dd1d4cb3	1376	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
sam_grove	5:3f93dd1d4cb3	1377	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
sam_grove	5:3f93dd1d4cb3	1378	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
sam_grove	5:3f93dd1d4cb3	1379	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
sam_grove	5:3f93dd1d4cb3	1380	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
sam_grove	5:3f93dd1d4cb3	1381
sam_grove	5:3f93dd1d4cb3	1382	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
sam_grove	5:3f93dd1d4cb3	1383	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
sam_grove	5:3f93dd1d4cb3	1384	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
sam_grove	5:3f93dd1d4cb3	1385	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
sam_grove	5:3f93dd1d4cb3	1386	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
sam_grove	5:3f93dd1d4cb3	1387	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
sam_grove	5:3f93dd1d4cb3	1388	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
sam_grove	5:3f93dd1d4cb3	1389	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
sam_grove	5:3f93dd1d4cb3	1390
sam_grove	5:3f93dd1d4cb3	1391	#if (__MPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	1392	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
sam_grove	5:3f93dd1d4cb3	1393	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
sam_grove	5:3f93dd1d4cb3	1394	#endif
sam_grove	5:3f93dd1d4cb3	1395
sam_grove	5:3f93dd1d4cb3	1396	#if (__FPU_PRESENT == 1)
sam_grove	5:3f93dd1d4cb3	1397	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
sam_grove	5:3f93dd1d4cb3	1398	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
sam_grove	5:3f93dd1d4cb3	1399	#endif
sam_grove	5:3f93dd1d4cb3	1400
sam_grove	5:3f93dd1d4cb3	1401	/@} /
sam_grove	5:3f93dd1d4cb3	1402
sam_grove	5:3f93dd1d4cb3	1403
sam_grove	5:3f93dd1d4cb3	1404
sam_grove	5:3f93dd1d4cb3	1405	/*******************************************************************************
sam_grove	5:3f93dd1d4cb3	1406	* Hardware Abstraction Layer
sam_grove	5:3f93dd1d4cb3	1407	Core Function Interface contains:
sam_grove	5:3f93dd1d4cb3	1408	- Core NVIC Functions
sam_grove	5:3f93dd1d4cb3	1409	- Core SysTick Functions
sam_grove	5:3f93dd1d4cb3	1410	- Core Debug Functions
sam_grove	5:3f93dd1d4cb3	1411	- Core Register Access Functions
sam_grove	5:3f93dd1d4cb3	1412	******************************************************************************/
sam_grove	5:3f93dd1d4cb3	1413	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
sam_grove	5:3f93dd1d4cb3	1414	*/
sam_grove	5:3f93dd1d4cb3	1415
sam_grove	5:3f93dd1d4cb3	1416
sam_grove	5:3f93dd1d4cb3	1417
sam_grove	5:3f93dd1d4cb3	1418	/* ########################## NVIC functions #################################### */
sam_grove	5:3f93dd1d4cb3	1419	/** \ingroup CMSIS_Core_FunctionInterface
sam_grove	5:3f93dd1d4cb3	1420	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
sam_grove	5:3f93dd1d4cb3	1421	\brief Functions that manage interrupts and exceptions via the NVIC.
sam_grove	5:3f93dd1d4cb3	1422	@{
sam_grove	5:3f93dd1d4cb3	1423	*/
sam_grove	5:3f93dd1d4cb3	1424
sam_grove	5:3f93dd1d4cb3	1425	/** \brief Set Priority Grouping
sam_grove	5:3f93dd1d4cb3	1426
sam_grove	5:3f93dd1d4cb3	1427	The function sets the priority grouping field using the required unlock sequence.
sam_grove	5:3f93dd1d4cb3	1428	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
sam_grove	5:3f93dd1d4cb3	1429	Only values from 0..7 are used.
sam_grove	5:3f93dd1d4cb3	1430	In case of a conflict between priority grouping and available
sam_grove	5:3f93dd1d4cb3	1431	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
sam_grove	5:3f93dd1d4cb3	1432
sam_grove	5:3f93dd1d4cb3	1433	\param [in] PriorityGroup Priority grouping field.
sam_grove	5:3f93dd1d4cb3	1434	*/
sam_grove	5:3f93dd1d4cb3	1435	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
sam_grove	5:3f93dd1d4cb3	1436	{
sam_grove	5:3f93dd1d4cb3	1437	uint32_t reg_value;
sam_grove	5:3f93dd1d4cb3	1438	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
sam_grove	5:3f93dd1d4cb3	1439
sam_grove	5:3f93dd1d4cb3	1440	reg_value = SCB->AIRCR; /* read old register configuration */
sam_grove	5:3f93dd1d4cb3	1441	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
sam_grove	5:3f93dd1d4cb3	1442	reg_value = (reg_value \|
sam_grove	5:3f93dd1d4cb3	1443	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
sam_grove	5:3f93dd1d4cb3	1444	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
sam_grove	5:3f93dd1d4cb3	1445	SCB->AIRCR = reg_value;
sam_grove	5:3f93dd1d4cb3	1446	}
sam_grove	5:3f93dd1d4cb3	1447
sam_grove	5:3f93dd1d4cb3	1448
sam_grove	5:3f93dd1d4cb3	1449	/** \brief Get Priority Grouping
sam_grove	5:3f93dd1d4cb3	1450
sam_grove	5:3f93dd1d4cb3	1451	The function reads the priority grouping field from the NVIC Interrupt Controller.
sam_grove	5:3f93dd1d4cb3	1452
sam_grove	5:3f93dd1d4cb3	1453	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
sam_grove	5:3f93dd1d4cb3	1454	*/
sam_grove	5:3f93dd1d4cb3	1455	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
sam_grove	5:3f93dd1d4cb3	1456	{
sam_grove	5:3f93dd1d4cb3	1457	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
sam_grove	5:3f93dd1d4cb3	1458	}
sam_grove	5:3f93dd1d4cb3	1459
sam_grove	5:3f93dd1d4cb3	1460
sam_grove	5:3f93dd1d4cb3	1461	/** \brief Enable External Interrupt
sam_grove	5:3f93dd1d4cb3	1462
sam_grove	5:3f93dd1d4cb3	1463	The function enables a device-specific interrupt in the NVIC interrupt controller.
sam_grove	5:3f93dd1d4cb3	1464
sam_grove	5:3f93dd1d4cb3	1465	\param [in] IRQn External interrupt number. Value cannot be negative.
sam_grove	5:3f93dd1d4cb3	1466	*/
sam_grove	5:3f93dd1d4cb3	1467	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
sam_grove	5:3f93dd1d4cb3	1468	{
sam_grove	5:3f93dd1d4cb3	1469	/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
sam_grove	5:3f93dd1d4cb3	1470	NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
sam_grove	5:3f93dd1d4cb3	1471	}
sam_grove	5:3f93dd1d4cb3	1472
sam_grove	5:3f93dd1d4cb3	1473
sam_grove	5:3f93dd1d4cb3	1474	/** \brief Disable External Interrupt
sam_grove	5:3f93dd1d4cb3	1475
sam_grove	5:3f93dd1d4cb3	1476	The function disables a device-specific interrupt in the NVIC interrupt controller.
sam_grove	5:3f93dd1d4cb3	1477
sam_grove	5:3f93dd1d4cb3	1478	\param [in] IRQn External interrupt number. Value cannot be negative.
sam_grove	5:3f93dd1d4cb3	1479	*/
sam_grove	5:3f93dd1d4cb3	1480	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
sam_grove	5:3f93dd1d4cb3	1481	{
sam_grove	5:3f93dd1d4cb3	1482	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
sam_grove	5:3f93dd1d4cb3	1483	}
sam_grove	5:3f93dd1d4cb3	1484
sam_grove	5:3f93dd1d4cb3	1485
sam_grove	5:3f93dd1d4cb3	1486	/** \brief Get Pending Interrupt
sam_grove	5:3f93dd1d4cb3	1487
sam_grove	5:3f93dd1d4cb3	1488	The function reads the pending register in the NVIC and returns the pending bit
sam_grove	5:3f93dd1d4cb3	1489	for the specified interrupt.
sam_grove	5:3f93dd1d4cb3	1490
sam_grove	5:3f93dd1d4cb3	1491	\param [in] IRQn Interrupt number.
sam_grove	5:3f93dd1d4cb3	1492
sam_grove	5:3f93dd1d4cb3	1493	\return 0 Interrupt status is not pending.
sam_grove	5:3f93dd1d4cb3	1494	\return 1 Interrupt status is pending.
sam_grove	5:3f93dd1d4cb3	1495	*/
sam_grove	5:3f93dd1d4cb3	1496	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
sam_grove	5:3f93dd1d4cb3	1497	{
sam_grove	5:3f93dd1d4cb3	1498	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
sam_grove	5:3f93dd1d4cb3	1499	}
sam_grove	5:3f93dd1d4cb3	1500
sam_grove	5:3f93dd1d4cb3	1501
sam_grove	5:3f93dd1d4cb3	1502	/** \brief Set Pending Interrupt
sam_grove	5:3f93dd1d4cb3	1503
sam_grove	5:3f93dd1d4cb3	1504	The function sets the pending bit of an external interrupt.
sam_grove	5:3f93dd1d4cb3	1505
sam_grove	5:3f93dd1d4cb3	1506	\param [in] IRQn Interrupt number. Value cannot be negative.
sam_grove	5:3f93dd1d4cb3	1507	*/
sam_grove	5:3f93dd1d4cb3	1508	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
sam_grove	5:3f93dd1d4cb3	1509	{
sam_grove	5:3f93dd1d4cb3	1510	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
sam_grove	5:3f93dd1d4cb3	1511	}
sam_grove	5:3f93dd1d4cb3	1512
sam_grove	5:3f93dd1d4cb3	1513
sam_grove	5:3f93dd1d4cb3	1514	/** \brief Clear Pending Interrupt
sam_grove	5:3f93dd1d4cb3	1515
sam_grove	5:3f93dd1d4cb3	1516	The function clears the pending bit of an external interrupt.
sam_grove	5:3f93dd1d4cb3	1517
sam_grove	5:3f93dd1d4cb3	1518	\param [in] IRQn External interrupt number. Value cannot be negative.
sam_grove	5:3f93dd1d4cb3	1519	*/
sam_grove	5:3f93dd1d4cb3	1520	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
sam_grove	5:3f93dd1d4cb3	1521	{
sam_grove	5:3f93dd1d4cb3	1522	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
sam_grove	5:3f93dd1d4cb3	1523	}
sam_grove	5:3f93dd1d4cb3	1524
sam_grove	5:3f93dd1d4cb3	1525
sam_grove	5:3f93dd1d4cb3	1526	/** \brief Get Active Interrupt
sam_grove	5:3f93dd1d4cb3	1527
sam_grove	5:3f93dd1d4cb3	1528	The function reads the active register in NVIC and returns the active bit.
sam_grove	5:3f93dd1d4cb3	1529
sam_grove	5:3f93dd1d4cb3	1530	\param [in] IRQn Interrupt number.
sam_grove	5:3f93dd1d4cb3	1531
sam_grove	5:3f93dd1d4cb3	1532	\return 0 Interrupt status is not active.
sam_grove	5:3f93dd1d4cb3	1533	\return 1 Interrupt status is active.
sam_grove	5:3f93dd1d4cb3	1534	*/
sam_grove	5:3f93dd1d4cb3	1535	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
sam_grove	5:3f93dd1d4cb3	1536	{
sam_grove	5:3f93dd1d4cb3	1537	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
sam_grove	5:3f93dd1d4cb3	1538	}
sam_grove	5:3f93dd1d4cb3	1539
sam_grove	5:3f93dd1d4cb3	1540
sam_grove	5:3f93dd1d4cb3	1541	/** \brief Set Interrupt Priority
sam_grove	5:3f93dd1d4cb3	1542
sam_grove	5:3f93dd1d4cb3	1543	The function sets the priority of an interrupt.
sam_grove	5:3f93dd1d4cb3	1544
sam_grove	5:3f93dd1d4cb3	1545	\note The priority cannot be set for every core interrupt.
sam_grove	5:3f93dd1d4cb3	1546
sam_grove	5:3f93dd1d4cb3	1547	\param [in] IRQn Interrupt number.
sam_grove	5:3f93dd1d4cb3	1548	\param [in] priority Priority to set.
sam_grove	5:3f93dd1d4cb3	1549	*/
sam_grove	5:3f93dd1d4cb3	1550	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
sam_grove	5:3f93dd1d4cb3	1551	{
sam_grove	5:3f93dd1d4cb3	1552	if(IRQn < 0) {
sam_grove	5:3f93dd1d4cb3	1553	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
sam_grove	5:3f93dd1d4cb3	1554	else {
sam_grove	5:3f93dd1d4cb3	1555	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
sam_grove	5:3f93dd1d4cb3	1556	}
sam_grove	5:3f93dd1d4cb3	1557
sam_grove	5:3f93dd1d4cb3	1558
sam_grove	5:3f93dd1d4cb3	1559	/** \brief Get Interrupt Priority
sam_grove	5:3f93dd1d4cb3	1560
sam_grove	5:3f93dd1d4cb3	1561	The function reads the priority of an interrupt. The interrupt
sam_grove	5:3f93dd1d4cb3	1562	number can be positive to specify an external (device specific)
sam_grove	5:3f93dd1d4cb3	1563	interrupt, or negative to specify an internal (core) interrupt.
sam_grove	5:3f93dd1d4cb3	1564
sam_grove	5:3f93dd1d4cb3	1565
sam_grove	5:3f93dd1d4cb3	1566	\param [in] IRQn Interrupt number.
sam_grove	5:3f93dd1d4cb3	1567	\return Interrupt Priority. Value is aligned automatically to the implemented
sam_grove	5:3f93dd1d4cb3	1568	priority bits of the microcontroller.
sam_grove	5:3f93dd1d4cb3	1569	*/
sam_grove	5:3f93dd1d4cb3	1570	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
sam_grove	5:3f93dd1d4cb3	1571	{
sam_grove	5:3f93dd1d4cb3	1572
sam_grove	5:3f93dd1d4cb3	1573	if(IRQn < 0) {
sam_grove	5:3f93dd1d4cb3	1574	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
sam_grove	5:3f93dd1d4cb3	1575	else {
sam_grove	5:3f93dd1d4cb3	1576	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
sam_grove	5:3f93dd1d4cb3	1577	}
sam_grove	5:3f93dd1d4cb3	1578
sam_grove	5:3f93dd1d4cb3	1579
sam_grove	5:3f93dd1d4cb3	1580	/** \brief Encode Priority
sam_grove	5:3f93dd1d4cb3	1581
sam_grove	5:3f93dd1d4cb3	1582	The function encodes the priority for an interrupt with the given priority group,
sam_grove	5:3f93dd1d4cb3	1583	preemptive priority value, and subpriority value.
sam_grove	5:3f93dd1d4cb3	1584	In case of a conflict between priority grouping and available
sam_grove	5:3f93dd1d4cb3	1585	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
sam_grove	5:3f93dd1d4cb3	1586
sam_grove	5:3f93dd1d4cb3	1587	\param [in] PriorityGroup Used priority group.
sam_grove	5:3f93dd1d4cb3	1588	\param [in] PreemptPriority Preemptive priority value (starting from 0).
sam_grove	5:3f93dd1d4cb3	1589	\param [in] SubPriority Subpriority value (starting from 0).
sam_grove	5:3f93dd1d4cb3	1590	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
sam_grove	5:3f93dd1d4cb3	1591	*/
sam_grove	5:3f93dd1d4cb3	1592	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
sam_grove	5:3f93dd1d4cb3	1593	{
sam_grove	5:3f93dd1d4cb3	1594	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
sam_grove	5:3f93dd1d4cb3	1595	uint32_t PreemptPriorityBits;
sam_grove	5:3f93dd1d4cb3	1596	uint32_t SubPriorityBits;
sam_grove	5:3f93dd1d4cb3	1597
sam_grove	5:3f93dd1d4cb3	1598	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
sam_grove	5:3f93dd1d4cb3	1599	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
sam_grove	5:3f93dd1d4cb3	1600
sam_grove	5:3f93dd1d4cb3	1601	return (
sam_grove	5:3f93dd1d4cb3	1602	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
sam_grove	5:3f93dd1d4cb3	1603	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
sam_grove	5:3f93dd1d4cb3	1604	);
sam_grove	5:3f93dd1d4cb3	1605	}
sam_grove	5:3f93dd1d4cb3	1606
sam_grove	5:3f93dd1d4cb3	1607
sam_grove	5:3f93dd1d4cb3	1608	/** \brief Decode Priority
sam_grove	5:3f93dd1d4cb3	1609
sam_grove	5:3f93dd1d4cb3	1610	The function decodes an interrupt priority value with a given priority group to
sam_grove	5:3f93dd1d4cb3	1611	preemptive priority value and subpriority value.
sam_grove	5:3f93dd1d4cb3	1612	In case of a conflict between priority grouping and available
sam_grove	5:3f93dd1d4cb3	1613	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
sam_grove	5:3f93dd1d4cb3	1614
sam_grove	5:3f93dd1d4cb3	1615	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
sam_grove	5:3f93dd1d4cb3	1616	\param [in] PriorityGroup Used priority group.
sam_grove	5:3f93dd1d4cb3	1617	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
sam_grove	5:3f93dd1d4cb3	1618	\param [out] pSubPriority Subpriority value (starting from 0).
sam_grove	5:3f93dd1d4cb3	1619	*/
sam_grove	5:3f93dd1d4cb3	1620	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
sam_grove	5:3f93dd1d4cb3	1621	{
sam_grove	5:3f93dd1d4cb3	1622	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
sam_grove	5:3f93dd1d4cb3	1623	uint32_t PreemptPriorityBits;
sam_grove	5:3f93dd1d4cb3	1624	uint32_t SubPriorityBits;
sam_grove	5:3f93dd1d4cb3	1625
sam_grove	5:3f93dd1d4cb3	1626	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
sam_grove	5:3f93dd1d4cb3	1627	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
sam_grove	5:3f93dd1d4cb3	1628
sam_grove	5:3f93dd1d4cb3	1629	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
sam_grove	5:3f93dd1d4cb3	1630	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
sam_grove	5:3f93dd1d4cb3	1631	}
sam_grove	5:3f93dd1d4cb3	1632
sam_grove	5:3f93dd1d4cb3	1633
sam_grove	5:3f93dd1d4cb3	1634	/** \brief System Reset
sam_grove	5:3f93dd1d4cb3	1635
sam_grove	5:3f93dd1d4cb3	1636	The function initiates a system reset request to reset the MCU.
sam_grove	5:3f93dd1d4cb3	1637	*/
sam_grove	5:3f93dd1d4cb3	1638	__STATIC_INLINE void NVIC_SystemReset(void)
sam_grove	5:3f93dd1d4cb3	1639	{
sam_grove	5:3f93dd1d4cb3	1640	__DSB(); /* Ensure all outstanding memory accesses included
sam_grove	5:3f93dd1d4cb3	1641	buffered write are completed before reset */
sam_grove	5:3f93dd1d4cb3	1642	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
sam_grove	5:3f93dd1d4cb3	1643	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
sam_grove	5:3f93dd1d4cb3	1644	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
sam_grove	5:3f93dd1d4cb3	1645	__DSB(); /* Ensure completion of memory access */
sam_grove	5:3f93dd1d4cb3	1646	while(1); /* wait until reset */
sam_grove	5:3f93dd1d4cb3	1647	}
sam_grove	5:3f93dd1d4cb3	1648
sam_grove	5:3f93dd1d4cb3	1649	/@} end of CMSIS_Core_NVICFunctions /
sam_grove	5:3f93dd1d4cb3	1650
sam_grove	5:3f93dd1d4cb3	1651
sam_grove	5:3f93dd1d4cb3	1652
sam_grove	5:3f93dd1d4cb3	1653	/* ################################## SysTick function ############################################ */
sam_grove	5:3f93dd1d4cb3	1654	/** \ingroup CMSIS_Core_FunctionInterface
sam_grove	5:3f93dd1d4cb3	1655	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
sam_grove	5:3f93dd1d4cb3	1656	\brief Functions that configure the System.
sam_grove	5:3f93dd1d4cb3	1657	@{
sam_grove	5:3f93dd1d4cb3	1658	*/
sam_grove	5:3f93dd1d4cb3	1659
sam_grove	5:3f93dd1d4cb3	1660	#if (__Vendor_SysTickConfig == 0)
sam_grove	5:3f93dd1d4cb3	1661
sam_grove	5:3f93dd1d4cb3	1662	/** \brief System Tick Configuration
sam_grove	5:3f93dd1d4cb3	1663
sam_grove	5:3f93dd1d4cb3	1664	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
sam_grove	5:3f93dd1d4cb3	1665	Counter is in free running mode to generate periodic interrupts.
sam_grove	5:3f93dd1d4cb3	1666
sam_grove	5:3f93dd1d4cb3	1667	\param [in] ticks Number of ticks between two interrupts.
sam_grove	5:3f93dd1d4cb3	1668
sam_grove	5:3f93dd1d4cb3	1669	\return 0 Function succeeded.
sam_grove	5:3f93dd1d4cb3	1670	\return 1 Function failed.
sam_grove	5:3f93dd1d4cb3	1671
sam_grove	5:3f93dd1d4cb3	1672	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
sam_grove	5:3f93dd1d4cb3	1673	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
sam_grove	5:3f93dd1d4cb3	1674	must contain a vendor-specific implementation of this function.
sam_grove	5:3f93dd1d4cb3	1675
sam_grove	5:3f93dd1d4cb3	1676	*/
sam_grove	5:3f93dd1d4cb3	1677	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
sam_grove	5:3f93dd1d4cb3	1678	{
sam_grove	5:3f93dd1d4cb3	1679	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
sam_grove	5:3f93dd1d4cb3	1680
sam_grove	5:3f93dd1d4cb3	1681	SysTick->LOAD = ticks - 1; /* set reload register */
sam_grove	5:3f93dd1d4cb3	1682	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
sam_grove	5:3f93dd1d4cb3	1683	SysTick->VAL = 0; /* Load the SysTick Counter Value */
sam_grove	5:3f93dd1d4cb3	1684	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
sam_grove	5:3f93dd1d4cb3	1685	SysTick_CTRL_TICKINT_Msk \|
sam_grove	5:3f93dd1d4cb3	1686	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
sam_grove	5:3f93dd1d4cb3	1687	return (0); /* Function successful */
sam_grove	5:3f93dd1d4cb3	1688	}
sam_grove	5:3f93dd1d4cb3	1689
sam_grove	5:3f93dd1d4cb3	1690	#endif
sam_grove	5:3f93dd1d4cb3	1691
sam_grove	5:3f93dd1d4cb3	1692	/@} end of CMSIS_Core_SysTickFunctions /
sam_grove	5:3f93dd1d4cb3	1693
sam_grove	5:3f93dd1d4cb3	1694
sam_grove	5:3f93dd1d4cb3	1695
sam_grove	5:3f93dd1d4cb3	1696	/* ##################################### Debug In/Output function ########################################### */
sam_grove	5:3f93dd1d4cb3	1697	/** \ingroup CMSIS_Core_FunctionInterface
sam_grove	5:3f93dd1d4cb3	1698	\defgroup CMSIS_core_DebugFunctions ITM Functions
sam_grove	5:3f93dd1d4cb3	1699	\brief Functions that access the ITM debug interface.
sam_grove	5:3f93dd1d4cb3	1700	@{
sam_grove	5:3f93dd1d4cb3	1701	*/
sam_grove	5:3f93dd1d4cb3	1702
sam_grove	5:3f93dd1d4cb3	1703	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
sam_grove	5:3f93dd1d4cb3	1704	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
sam_grove	5:3f93dd1d4cb3	1705
sam_grove	5:3f93dd1d4cb3	1706
sam_grove	5:3f93dd1d4cb3	1707	/** \brief ITM Send Character
sam_grove	5:3f93dd1d4cb3	1708
sam_grove	5:3f93dd1d4cb3	1709	The function transmits a character via the ITM channel 0, and
sam_grove	5:3f93dd1d4cb3	1710	\li Just returns when no debugger is connected that has booked the output.
sam_grove	5:3f93dd1d4cb3	1711	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
sam_grove	5:3f93dd1d4cb3	1712
sam_grove	5:3f93dd1d4cb3	1713	\param [in] ch Character to transmit.
sam_grove	5:3f93dd1d4cb3	1714
sam_grove	5:3f93dd1d4cb3	1715	\returns Character to transmit.
sam_grove	5:3f93dd1d4cb3	1716	*/
sam_grove	5:3f93dd1d4cb3	1717	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
sam_grove	5:3f93dd1d4cb3	1718	{
sam_grove	5:3f93dd1d4cb3	1719	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
sam_grove	5:3f93dd1d4cb3	1720	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
sam_grove	5:3f93dd1d4cb3	1721	{
sam_grove	5:3f93dd1d4cb3	1722	while (ITM->PORT[0].u32 == 0);
sam_grove	5:3f93dd1d4cb3	1723	ITM->PORT[0].u8 = (uint8_t) ch;
sam_grove	5:3f93dd1d4cb3	1724	}
sam_grove	5:3f93dd1d4cb3	1725	return (ch);
sam_grove	5:3f93dd1d4cb3	1726	}
sam_grove	5:3f93dd1d4cb3	1727
sam_grove	5:3f93dd1d4cb3	1728
sam_grove	5:3f93dd1d4cb3	1729	/** \brief ITM Receive Character
sam_grove	5:3f93dd1d4cb3	1730
sam_grove	5:3f93dd1d4cb3	1731	The function inputs a character via the external variable \ref ITM_RxBuffer.
sam_grove	5:3f93dd1d4cb3	1732
sam_grove	5:3f93dd1d4cb3	1733	\return Received character.
sam_grove	5:3f93dd1d4cb3	1734	\return -1 No character pending.
sam_grove	5:3f93dd1d4cb3	1735	*/
sam_grove	5:3f93dd1d4cb3	1736	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
sam_grove	5:3f93dd1d4cb3	1737	int32_t ch = -1; /* no character available */
sam_grove	5:3f93dd1d4cb3	1738
sam_grove	5:3f93dd1d4cb3	1739	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
sam_grove	5:3f93dd1d4cb3	1740	ch = ITM_RxBuffer;
sam_grove	5:3f93dd1d4cb3	1741	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
sam_grove	5:3f93dd1d4cb3	1742	}
sam_grove	5:3f93dd1d4cb3	1743
sam_grove	5:3f93dd1d4cb3	1744	return (ch);
sam_grove	5:3f93dd1d4cb3	1745	}
sam_grove	5:3f93dd1d4cb3	1746
sam_grove	5:3f93dd1d4cb3	1747
sam_grove	5:3f93dd1d4cb3	1748	/** \brief ITM Check Character
sam_grove	5:3f93dd1d4cb3	1749
sam_grove	5:3f93dd1d4cb3	1750	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
sam_grove	5:3f93dd1d4cb3	1751
sam_grove	5:3f93dd1d4cb3	1752	\return 0 No character available.
sam_grove	5:3f93dd1d4cb3	1753	\return 1 Character available.
sam_grove	5:3f93dd1d4cb3	1754	*/
sam_grove	5:3f93dd1d4cb3	1755	__STATIC_INLINE int32_t ITM_CheckChar (void) {
sam_grove	5:3f93dd1d4cb3	1756
sam_grove	5:3f93dd1d4cb3	1757	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
sam_grove	5:3f93dd1d4cb3	1758	return (0); /* no character available */
sam_grove	5:3f93dd1d4cb3	1759	} else {
sam_grove	5:3f93dd1d4cb3	1760	return (1); /* character available */
sam_grove	5:3f93dd1d4cb3	1761	}
sam_grove	5:3f93dd1d4cb3	1762	}
sam_grove	5:3f93dd1d4cb3	1763
sam_grove	5:3f93dd1d4cb3	1764	/@} end of CMSIS_core_DebugFunctions /
sam_grove	5:3f93dd1d4cb3	1765
sam_grove	5:3f93dd1d4cb3	1766	#endif /* __CORE_CM4_H_DEPENDANT */
sam_grove	5:3f93dd1d4cb3	1767
sam_grove	5:3f93dd1d4cb3	1768	#endif /* __CMSIS_GENERIC */
sam_grove	5:3f93dd1d4cb3	1769
sam_grove	5:3f93dd1d4cb3	1770	#ifdef __cplusplus
sam_grove	5:3f93dd1d4cb3	1771	}
sam_grove	5:3f93dd1d4cb3	1772	#endif