Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/cmsis/core_cm0plus.h@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /**************************************************************************//**
sam_grove 5:3f93dd1d4cb3 2 * @file core_cm0plus.h
sam_grove 5:3f93dd1d4cb3 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
sam_grove 5:3f93dd1d4cb3 4 * @version V3.20
sam_grove 5:3f93dd1d4cb3 5 * @date 25. February 2013
sam_grove 5:3f93dd1d4cb3 6 *
sam_grove 5:3f93dd1d4cb3 7 * @note
sam_grove 5:3f93dd1d4cb3 8 *
sam_grove 5:3f93dd1d4cb3 9 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
sam_grove 5:3f93dd1d4cb3 11
sam_grove 5:3f93dd1d4cb3 12 All rights reserved.
sam_grove 5:3f93dd1d4cb3 13 Redistribution and use in source and binary forms, with or without
sam_grove 5:3f93dd1d4cb3 14 modification, are permitted provided that the following conditions are met:
sam_grove 5:3f93dd1d4cb3 15 - Redistributions of source code must retain the above copyright
sam_grove 5:3f93dd1d4cb3 16 notice, this list of conditions and the following disclaimer.
sam_grove 5:3f93dd1d4cb3 17 - Redistributions in binary form must reproduce the above copyright
sam_grove 5:3f93dd1d4cb3 18 notice, this list of conditions and the following disclaimer in the
sam_grove 5:3f93dd1d4cb3 19 documentation and/or other materials provided with the distribution.
sam_grove 5:3f93dd1d4cb3 20 - Neither the name of ARM nor the names of its contributors may be used
sam_grove 5:3f93dd1d4cb3 21 to endorse or promote products derived from this software without
sam_grove 5:3f93dd1d4cb3 22 specific prior written permission.
sam_grove 5:3f93dd1d4cb3 23 *
sam_grove 5:3f93dd1d4cb3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sam_grove 5:3f93dd1d4cb3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sam_grove 5:3f93dd1d4cb3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sam_grove 5:3f93dd1d4cb3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sam_grove 5:3f93dd1d4cb3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sam_grove 5:3f93dd1d4cb3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sam_grove 5:3f93dd1d4cb3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sam_grove 5:3f93dd1d4cb3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sam_grove 5:3f93dd1d4cb3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sam_grove 5:3f93dd1d4cb3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sam_grove 5:3f93dd1d4cb3 34 POSSIBILITY OF SUCH DAMAGE.
sam_grove 5:3f93dd1d4cb3 35 ---------------------------------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 36
sam_grove 5:3f93dd1d4cb3 37
sam_grove 5:3f93dd1d4cb3 38 #if defined ( __ICCARM__ )
sam_grove 5:3f93dd1d4cb3 39 #pragma system_include /* treat file as system include file for MISRA check */
sam_grove 5:3f93dd1d4cb3 40 #endif
sam_grove 5:3f93dd1d4cb3 41
sam_grove 5:3f93dd1d4cb3 42 #ifdef __cplusplus
sam_grove 5:3f93dd1d4cb3 43 extern "C" {
sam_grove 5:3f93dd1d4cb3 44 #endif
sam_grove 5:3f93dd1d4cb3 45
sam_grove 5:3f93dd1d4cb3 46 #ifndef __CORE_CM0PLUS_H_GENERIC
sam_grove 5:3f93dd1d4cb3 47 #define __CORE_CM0PLUS_H_GENERIC
sam_grove 5:3f93dd1d4cb3 48
sam_grove 5:3f93dd1d4cb3 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
sam_grove 5:3f93dd1d4cb3 50 CMSIS violates the following MISRA-C:2004 rules:
sam_grove 5:3f93dd1d4cb3 51
sam_grove 5:3f93dd1d4cb3 52 \li Required Rule 8.5, object/function definition in header file.<br>
sam_grove 5:3f93dd1d4cb3 53 Function definitions in header files are used to allow 'inlining'.
sam_grove 5:3f93dd1d4cb3 54
sam_grove 5:3f93dd1d4cb3 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
sam_grove 5:3f93dd1d4cb3 56 Unions are used for effective representation of core registers.
sam_grove 5:3f93dd1d4cb3 57
sam_grove 5:3f93dd1d4cb3 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
sam_grove 5:3f93dd1d4cb3 59 Function-like macros are used to allow more efficient code.
sam_grove 5:3f93dd1d4cb3 60 */
sam_grove 5:3f93dd1d4cb3 61
sam_grove 5:3f93dd1d4cb3 62
sam_grove 5:3f93dd1d4cb3 63 /*******************************************************************************
sam_grove 5:3f93dd1d4cb3 64 * CMSIS definitions
sam_grove 5:3f93dd1d4cb3 65 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 66 /** \ingroup Cortex-M0+
sam_grove 5:3f93dd1d4cb3 67 @{
sam_grove 5:3f93dd1d4cb3 68 */
sam_grove 5:3f93dd1d4cb3 69
sam_grove 5:3f93dd1d4cb3 70 /* CMSIS CM0P definitions */
sam_grove 5:3f93dd1d4cb3 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
sam_grove 5:3f93dd1d4cb3 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
sam_grove 5:3f93dd1d4cb3 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
sam_grove 5:3f93dd1d4cb3 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
sam_grove 5:3f93dd1d4cb3 75
sam_grove 5:3f93dd1d4cb3 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
sam_grove 5:3f93dd1d4cb3 77
sam_grove 5:3f93dd1d4cb3 78
sam_grove 5:3f93dd1d4cb3 79 #if defined ( __CC_ARM )
sam_grove 5:3f93dd1d4cb3 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
sam_grove 5:3f93dd1d4cb3 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
sam_grove 5:3f93dd1d4cb3 82 #define __STATIC_INLINE static __inline
sam_grove 5:3f93dd1d4cb3 83
sam_grove 5:3f93dd1d4cb3 84 #elif defined ( __ICCARM__ )
sam_grove 5:3f93dd1d4cb3 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
sam_grove 5:3f93dd1d4cb3 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
sam_grove 5:3f93dd1d4cb3 87 #define __STATIC_INLINE static inline
sam_grove 5:3f93dd1d4cb3 88
sam_grove 5:3f93dd1d4cb3 89 #elif defined ( __GNUC__ )
sam_grove 5:3f93dd1d4cb3 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
sam_grove 5:3f93dd1d4cb3 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
sam_grove 5:3f93dd1d4cb3 92 #define __STATIC_INLINE static inline
sam_grove 5:3f93dd1d4cb3 93
sam_grove 5:3f93dd1d4cb3 94 #elif defined ( __TASKING__ )
sam_grove 5:3f93dd1d4cb3 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
sam_grove 5:3f93dd1d4cb3 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
sam_grove 5:3f93dd1d4cb3 97 #define __STATIC_INLINE static inline
sam_grove 5:3f93dd1d4cb3 98
sam_grove 5:3f93dd1d4cb3 99 #endif
sam_grove 5:3f93dd1d4cb3 100
sam_grove 5:3f93dd1d4cb3 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
sam_grove 5:3f93dd1d4cb3 102 */
sam_grove 5:3f93dd1d4cb3 103 #define __FPU_USED 0
sam_grove 5:3f93dd1d4cb3 104
sam_grove 5:3f93dd1d4cb3 105 #if defined ( __CC_ARM )
sam_grove 5:3f93dd1d4cb3 106 #if defined __TARGET_FPU_VFP
sam_grove 5:3f93dd1d4cb3 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove 5:3f93dd1d4cb3 108 #endif
sam_grove 5:3f93dd1d4cb3 109
sam_grove 5:3f93dd1d4cb3 110 #elif defined ( __ICCARM__ )
sam_grove 5:3f93dd1d4cb3 111 #if defined __ARMVFP__
sam_grove 5:3f93dd1d4cb3 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove 5:3f93dd1d4cb3 113 #endif
sam_grove 5:3f93dd1d4cb3 114
sam_grove 5:3f93dd1d4cb3 115 #elif defined ( __GNUC__ )
sam_grove 5:3f93dd1d4cb3 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
sam_grove 5:3f93dd1d4cb3 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove 5:3f93dd1d4cb3 118 #endif
sam_grove 5:3f93dd1d4cb3 119
sam_grove 5:3f93dd1d4cb3 120 #elif defined ( __TASKING__ )
sam_grove 5:3f93dd1d4cb3 121 #if defined __FPU_VFP__
sam_grove 5:3f93dd1d4cb3 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sam_grove 5:3f93dd1d4cb3 123 #endif
sam_grove 5:3f93dd1d4cb3 124 #endif
sam_grove 5:3f93dd1d4cb3 125
sam_grove 5:3f93dd1d4cb3 126 #include <stdint.h> /* standard types definitions */
sam_grove 5:3f93dd1d4cb3 127 #include <core_cmInstr.h> /* Core Instruction Access */
sam_grove 5:3f93dd1d4cb3 128 #include <core_cmFunc.h> /* Core Function Access */
sam_grove 5:3f93dd1d4cb3 129
sam_grove 5:3f93dd1d4cb3 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
sam_grove 5:3f93dd1d4cb3 131
sam_grove 5:3f93dd1d4cb3 132 #ifndef __CMSIS_GENERIC
sam_grove 5:3f93dd1d4cb3 133
sam_grove 5:3f93dd1d4cb3 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
sam_grove 5:3f93dd1d4cb3 135 #define __CORE_CM0PLUS_H_DEPENDANT
sam_grove 5:3f93dd1d4cb3 136
sam_grove 5:3f93dd1d4cb3 137 /* check device defines and use defaults */
sam_grove 5:3f93dd1d4cb3 138 #if defined __CHECK_DEVICE_DEFINES
sam_grove 5:3f93dd1d4cb3 139 #ifndef __CM0PLUS_REV
sam_grove 5:3f93dd1d4cb3 140 #define __CM0PLUS_REV 0x0000
sam_grove 5:3f93dd1d4cb3 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
sam_grove 5:3f93dd1d4cb3 142 #endif
sam_grove 5:3f93dd1d4cb3 143
sam_grove 5:3f93dd1d4cb3 144 #ifndef __MPU_PRESENT
sam_grove 5:3f93dd1d4cb3 145 #define __MPU_PRESENT 0
sam_grove 5:3f93dd1d4cb3 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
sam_grove 5:3f93dd1d4cb3 147 #endif
sam_grove 5:3f93dd1d4cb3 148
sam_grove 5:3f93dd1d4cb3 149 #ifndef __VTOR_PRESENT
sam_grove 5:3f93dd1d4cb3 150 #define __VTOR_PRESENT 0
sam_grove 5:3f93dd1d4cb3 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
sam_grove 5:3f93dd1d4cb3 152 #endif
sam_grove 5:3f93dd1d4cb3 153
sam_grove 5:3f93dd1d4cb3 154 #ifndef __NVIC_PRIO_BITS
sam_grove 5:3f93dd1d4cb3 155 #define __NVIC_PRIO_BITS 2
sam_grove 5:3f93dd1d4cb3 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
sam_grove 5:3f93dd1d4cb3 157 #endif
sam_grove 5:3f93dd1d4cb3 158
sam_grove 5:3f93dd1d4cb3 159 #ifndef __Vendor_SysTickConfig
sam_grove 5:3f93dd1d4cb3 160 #define __Vendor_SysTickConfig 0
sam_grove 5:3f93dd1d4cb3 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
sam_grove 5:3f93dd1d4cb3 162 #endif
sam_grove 5:3f93dd1d4cb3 163 #endif
sam_grove 5:3f93dd1d4cb3 164
sam_grove 5:3f93dd1d4cb3 165 /* IO definitions (access restrictions to peripheral registers) */
sam_grove 5:3f93dd1d4cb3 166 /**
sam_grove 5:3f93dd1d4cb3 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
sam_grove 5:3f93dd1d4cb3 168
sam_grove 5:3f93dd1d4cb3 169 <strong>IO Type Qualifiers</strong> are used
sam_grove 5:3f93dd1d4cb3 170 \li to specify the access to peripheral variables.
sam_grove 5:3f93dd1d4cb3 171 \li for automatic generation of peripheral register debug information.
sam_grove 5:3f93dd1d4cb3 172 */
sam_grove 5:3f93dd1d4cb3 173 #ifdef __cplusplus
sam_grove 5:3f93dd1d4cb3 174 #define __I volatile /*!< Defines 'read only' permissions */
sam_grove 5:3f93dd1d4cb3 175 #else
sam_grove 5:3f93dd1d4cb3 176 #define __I volatile const /*!< Defines 'read only' permissions */
sam_grove 5:3f93dd1d4cb3 177 #endif
sam_grove 5:3f93dd1d4cb3 178 #define __O volatile /*!< Defines 'write only' permissions */
sam_grove 5:3f93dd1d4cb3 179 #define __IO volatile /*!< Defines 'read / write' permissions */
sam_grove 5:3f93dd1d4cb3 180
sam_grove 5:3f93dd1d4cb3 181 /*@} end of group Cortex-M0+ */
sam_grove 5:3f93dd1d4cb3 182
sam_grove 5:3f93dd1d4cb3 183
sam_grove 5:3f93dd1d4cb3 184
sam_grove 5:3f93dd1d4cb3 185 /*******************************************************************************
sam_grove 5:3f93dd1d4cb3 186 * Register Abstraction
sam_grove 5:3f93dd1d4cb3 187 Core Register contain:
sam_grove 5:3f93dd1d4cb3 188 - Core Register
sam_grove 5:3f93dd1d4cb3 189 - Core NVIC Register
sam_grove 5:3f93dd1d4cb3 190 - Core SCB Register
sam_grove 5:3f93dd1d4cb3 191 - Core SysTick Register
sam_grove 5:3f93dd1d4cb3 192 - Core MPU Register
sam_grove 5:3f93dd1d4cb3 193 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
sam_grove 5:3f93dd1d4cb3 195 \brief Type definitions and defines for Cortex-M processor based devices.
sam_grove 5:3f93dd1d4cb3 196 */
sam_grove 5:3f93dd1d4cb3 197
sam_grove 5:3f93dd1d4cb3 198 /** \ingroup CMSIS_core_register
sam_grove 5:3f93dd1d4cb3 199 \defgroup CMSIS_CORE Status and Control Registers
sam_grove 5:3f93dd1d4cb3 200 \brief Core Register type definitions.
sam_grove 5:3f93dd1d4cb3 201 @{
sam_grove 5:3f93dd1d4cb3 202 */
sam_grove 5:3f93dd1d4cb3 203
sam_grove 5:3f93dd1d4cb3 204 /** \brief Union type to access the Application Program Status Register (APSR).
sam_grove 5:3f93dd1d4cb3 205 */
sam_grove 5:3f93dd1d4cb3 206 typedef union
sam_grove 5:3f93dd1d4cb3 207 {
sam_grove 5:3f93dd1d4cb3 208 struct
sam_grove 5:3f93dd1d4cb3 209 {
sam_grove 5:3f93dd1d4cb3 210 #if (__CORTEX_M != 0x04)
sam_grove 5:3f93dd1d4cb3 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
sam_grove 5:3f93dd1d4cb3 212 #else
sam_grove 5:3f93dd1d4cb3 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
sam_grove 5:3f93dd1d4cb3 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
sam_grove 5:3f93dd1d4cb3 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
sam_grove 5:3f93dd1d4cb3 216 #endif
sam_grove 5:3f93dd1d4cb3 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
sam_grove 5:3f93dd1d4cb3 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
sam_grove 5:3f93dd1d4cb3 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
sam_grove 5:3f93dd1d4cb3 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
sam_grove 5:3f93dd1d4cb3 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
sam_grove 5:3f93dd1d4cb3 222 } b; /*!< Structure used for bit access */
sam_grove 5:3f93dd1d4cb3 223 uint32_t w; /*!< Type used for word access */
sam_grove 5:3f93dd1d4cb3 224 } APSR_Type;
sam_grove 5:3f93dd1d4cb3 225
sam_grove 5:3f93dd1d4cb3 226
sam_grove 5:3f93dd1d4cb3 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
sam_grove 5:3f93dd1d4cb3 228 */
sam_grove 5:3f93dd1d4cb3 229 typedef union
sam_grove 5:3f93dd1d4cb3 230 {
sam_grove 5:3f93dd1d4cb3 231 struct
sam_grove 5:3f93dd1d4cb3 232 {
sam_grove 5:3f93dd1d4cb3 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
sam_grove 5:3f93dd1d4cb3 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
sam_grove 5:3f93dd1d4cb3 235 } b; /*!< Structure used for bit access */
sam_grove 5:3f93dd1d4cb3 236 uint32_t w; /*!< Type used for word access */
sam_grove 5:3f93dd1d4cb3 237 } IPSR_Type;
sam_grove 5:3f93dd1d4cb3 238
sam_grove 5:3f93dd1d4cb3 239
sam_grove 5:3f93dd1d4cb3 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
sam_grove 5:3f93dd1d4cb3 241 */
sam_grove 5:3f93dd1d4cb3 242 typedef union
sam_grove 5:3f93dd1d4cb3 243 {
sam_grove 5:3f93dd1d4cb3 244 struct
sam_grove 5:3f93dd1d4cb3 245 {
sam_grove 5:3f93dd1d4cb3 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
sam_grove 5:3f93dd1d4cb3 247 #if (__CORTEX_M != 0x04)
sam_grove 5:3f93dd1d4cb3 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
sam_grove 5:3f93dd1d4cb3 249 #else
sam_grove 5:3f93dd1d4cb3 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
sam_grove 5:3f93dd1d4cb3 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
sam_grove 5:3f93dd1d4cb3 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
sam_grove 5:3f93dd1d4cb3 253 #endif
sam_grove 5:3f93dd1d4cb3 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
sam_grove 5:3f93dd1d4cb3 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
sam_grove 5:3f93dd1d4cb3 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
sam_grove 5:3f93dd1d4cb3 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
sam_grove 5:3f93dd1d4cb3 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
sam_grove 5:3f93dd1d4cb3 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
sam_grove 5:3f93dd1d4cb3 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
sam_grove 5:3f93dd1d4cb3 261 } b; /*!< Structure used for bit access */
sam_grove 5:3f93dd1d4cb3 262 uint32_t w; /*!< Type used for word access */
sam_grove 5:3f93dd1d4cb3 263 } xPSR_Type;
sam_grove 5:3f93dd1d4cb3 264
sam_grove 5:3f93dd1d4cb3 265
sam_grove 5:3f93dd1d4cb3 266 /** \brief Union type to access the Control Registers (CONTROL).
sam_grove 5:3f93dd1d4cb3 267 */
sam_grove 5:3f93dd1d4cb3 268 typedef union
sam_grove 5:3f93dd1d4cb3 269 {
sam_grove 5:3f93dd1d4cb3 270 struct
sam_grove 5:3f93dd1d4cb3 271 {
sam_grove 5:3f93dd1d4cb3 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
sam_grove 5:3f93dd1d4cb3 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
sam_grove 5:3f93dd1d4cb3 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
sam_grove 5:3f93dd1d4cb3 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
sam_grove 5:3f93dd1d4cb3 276 } b; /*!< Structure used for bit access */
sam_grove 5:3f93dd1d4cb3 277 uint32_t w; /*!< Type used for word access */
sam_grove 5:3f93dd1d4cb3 278 } CONTROL_Type;
sam_grove 5:3f93dd1d4cb3 279
sam_grove 5:3f93dd1d4cb3 280 /*@} end of group CMSIS_CORE */
sam_grove 5:3f93dd1d4cb3 281
sam_grove 5:3f93dd1d4cb3 282
sam_grove 5:3f93dd1d4cb3 283 /** \ingroup CMSIS_core_register
sam_grove 5:3f93dd1d4cb3 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
sam_grove 5:3f93dd1d4cb3 285 \brief Type definitions for the NVIC Registers
sam_grove 5:3f93dd1d4cb3 286 @{
sam_grove 5:3f93dd1d4cb3 287 */
sam_grove 5:3f93dd1d4cb3 288
sam_grove 5:3f93dd1d4cb3 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
sam_grove 5:3f93dd1d4cb3 290 */
sam_grove 5:3f93dd1d4cb3 291 typedef struct
sam_grove 5:3f93dd1d4cb3 292 {
sam_grove 5:3f93dd1d4cb3 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
sam_grove 5:3f93dd1d4cb3 294 uint32_t RESERVED0[31];
sam_grove 5:3f93dd1d4cb3 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
sam_grove 5:3f93dd1d4cb3 296 uint32_t RSERVED1[31];
sam_grove 5:3f93dd1d4cb3 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
sam_grove 5:3f93dd1d4cb3 298 uint32_t RESERVED2[31];
sam_grove 5:3f93dd1d4cb3 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
sam_grove 5:3f93dd1d4cb3 300 uint32_t RESERVED3[31];
sam_grove 5:3f93dd1d4cb3 301 uint32_t RESERVED4[64];
sam_grove 5:3f93dd1d4cb3 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
sam_grove 5:3f93dd1d4cb3 303 } NVIC_Type;
sam_grove 5:3f93dd1d4cb3 304
sam_grove 5:3f93dd1d4cb3 305 /*@} end of group CMSIS_NVIC */
sam_grove 5:3f93dd1d4cb3 306
sam_grove 5:3f93dd1d4cb3 307
sam_grove 5:3f93dd1d4cb3 308 /** \ingroup CMSIS_core_register
sam_grove 5:3f93dd1d4cb3 309 \defgroup CMSIS_SCB System Control Block (SCB)
sam_grove 5:3f93dd1d4cb3 310 \brief Type definitions for the System Control Block Registers
sam_grove 5:3f93dd1d4cb3 311 @{
sam_grove 5:3f93dd1d4cb3 312 */
sam_grove 5:3f93dd1d4cb3 313
sam_grove 5:3f93dd1d4cb3 314 /** \brief Structure type to access the System Control Block (SCB).
sam_grove 5:3f93dd1d4cb3 315 */
sam_grove 5:3f93dd1d4cb3 316 typedef struct
sam_grove 5:3f93dd1d4cb3 317 {
sam_grove 5:3f93dd1d4cb3 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
sam_grove 5:3f93dd1d4cb3 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
sam_grove 5:3f93dd1d4cb3 320 #if (__VTOR_PRESENT == 1)
sam_grove 5:3f93dd1d4cb3 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
sam_grove 5:3f93dd1d4cb3 322 #else
sam_grove 5:3f93dd1d4cb3 323 uint32_t RESERVED0;
sam_grove 5:3f93dd1d4cb3 324 #endif
sam_grove 5:3f93dd1d4cb3 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
sam_grove 5:3f93dd1d4cb3 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
sam_grove 5:3f93dd1d4cb3 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
sam_grove 5:3f93dd1d4cb3 328 uint32_t RESERVED1;
sam_grove 5:3f93dd1d4cb3 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
sam_grove 5:3f93dd1d4cb3 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
sam_grove 5:3f93dd1d4cb3 331 } SCB_Type;
sam_grove 5:3f93dd1d4cb3 332
sam_grove 5:3f93dd1d4cb3 333 /* SCB CPUID Register Definitions */
sam_grove 5:3f93dd1d4cb3 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
sam_grove 5:3f93dd1d4cb3 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
sam_grove 5:3f93dd1d4cb3 336
sam_grove 5:3f93dd1d4cb3 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
sam_grove 5:3f93dd1d4cb3 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
sam_grove 5:3f93dd1d4cb3 339
sam_grove 5:3f93dd1d4cb3 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
sam_grove 5:3f93dd1d4cb3 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
sam_grove 5:3f93dd1d4cb3 342
sam_grove 5:3f93dd1d4cb3 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
sam_grove 5:3f93dd1d4cb3 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
sam_grove 5:3f93dd1d4cb3 345
sam_grove 5:3f93dd1d4cb3 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
sam_grove 5:3f93dd1d4cb3 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
sam_grove 5:3f93dd1d4cb3 348
sam_grove 5:3f93dd1d4cb3 349 /* SCB Interrupt Control State Register Definitions */
sam_grove 5:3f93dd1d4cb3 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
sam_grove 5:3f93dd1d4cb3 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
sam_grove 5:3f93dd1d4cb3 352
sam_grove 5:3f93dd1d4cb3 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
sam_grove 5:3f93dd1d4cb3 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
sam_grove 5:3f93dd1d4cb3 355
sam_grove 5:3f93dd1d4cb3 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
sam_grove 5:3f93dd1d4cb3 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
sam_grove 5:3f93dd1d4cb3 358
sam_grove 5:3f93dd1d4cb3 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
sam_grove 5:3f93dd1d4cb3 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
sam_grove 5:3f93dd1d4cb3 361
sam_grove 5:3f93dd1d4cb3 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
sam_grove 5:3f93dd1d4cb3 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
sam_grove 5:3f93dd1d4cb3 364
sam_grove 5:3f93dd1d4cb3 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
sam_grove 5:3f93dd1d4cb3 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
sam_grove 5:3f93dd1d4cb3 367
sam_grove 5:3f93dd1d4cb3 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
sam_grove 5:3f93dd1d4cb3 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
sam_grove 5:3f93dd1d4cb3 370
sam_grove 5:3f93dd1d4cb3 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
sam_grove 5:3f93dd1d4cb3 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
sam_grove 5:3f93dd1d4cb3 373
sam_grove 5:3f93dd1d4cb3 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
sam_grove 5:3f93dd1d4cb3 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
sam_grove 5:3f93dd1d4cb3 376
sam_grove 5:3f93dd1d4cb3 377 #if (__VTOR_PRESENT == 1)
sam_grove 5:3f93dd1d4cb3 378 /* SCB Interrupt Control State Register Definitions */
sam_grove 5:3f93dd1d4cb3 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
sam_grove 5:3f93dd1d4cb3 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
sam_grove 5:3f93dd1d4cb3 381 #endif
sam_grove 5:3f93dd1d4cb3 382
sam_grove 5:3f93dd1d4cb3 383 /* SCB Application Interrupt and Reset Control Register Definitions */
sam_grove 5:3f93dd1d4cb3 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
sam_grove 5:3f93dd1d4cb3 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
sam_grove 5:3f93dd1d4cb3 386
sam_grove 5:3f93dd1d4cb3 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
sam_grove 5:3f93dd1d4cb3 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
sam_grove 5:3f93dd1d4cb3 389
sam_grove 5:3f93dd1d4cb3 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
sam_grove 5:3f93dd1d4cb3 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
sam_grove 5:3f93dd1d4cb3 392
sam_grove 5:3f93dd1d4cb3 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
sam_grove 5:3f93dd1d4cb3 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
sam_grove 5:3f93dd1d4cb3 395
sam_grove 5:3f93dd1d4cb3 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
sam_grove 5:3f93dd1d4cb3 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
sam_grove 5:3f93dd1d4cb3 398
sam_grove 5:3f93dd1d4cb3 399 /* SCB System Control Register Definitions */
sam_grove 5:3f93dd1d4cb3 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
sam_grove 5:3f93dd1d4cb3 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
sam_grove 5:3f93dd1d4cb3 402
sam_grove 5:3f93dd1d4cb3 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
sam_grove 5:3f93dd1d4cb3 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
sam_grove 5:3f93dd1d4cb3 405
sam_grove 5:3f93dd1d4cb3 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
sam_grove 5:3f93dd1d4cb3 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
sam_grove 5:3f93dd1d4cb3 408
sam_grove 5:3f93dd1d4cb3 409 /* SCB Configuration Control Register Definitions */
sam_grove 5:3f93dd1d4cb3 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
sam_grove 5:3f93dd1d4cb3 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
sam_grove 5:3f93dd1d4cb3 412
sam_grove 5:3f93dd1d4cb3 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
sam_grove 5:3f93dd1d4cb3 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
sam_grove 5:3f93dd1d4cb3 415
sam_grove 5:3f93dd1d4cb3 416 /* SCB System Handler Control and State Register Definitions */
sam_grove 5:3f93dd1d4cb3 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
sam_grove 5:3f93dd1d4cb3 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
sam_grove 5:3f93dd1d4cb3 419
sam_grove 5:3f93dd1d4cb3 420 /*@} end of group CMSIS_SCB */
sam_grove 5:3f93dd1d4cb3 421
sam_grove 5:3f93dd1d4cb3 422
sam_grove 5:3f93dd1d4cb3 423 /** \ingroup CMSIS_core_register
sam_grove 5:3f93dd1d4cb3 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
sam_grove 5:3f93dd1d4cb3 425 \brief Type definitions for the System Timer Registers.
sam_grove 5:3f93dd1d4cb3 426 @{
sam_grove 5:3f93dd1d4cb3 427 */
sam_grove 5:3f93dd1d4cb3 428
sam_grove 5:3f93dd1d4cb3 429 /** \brief Structure type to access the System Timer (SysTick).
sam_grove 5:3f93dd1d4cb3 430 */
sam_grove 5:3f93dd1d4cb3 431 typedef struct
sam_grove 5:3f93dd1d4cb3 432 {
sam_grove 5:3f93dd1d4cb3 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
sam_grove 5:3f93dd1d4cb3 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
sam_grove 5:3f93dd1d4cb3 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
sam_grove 5:3f93dd1d4cb3 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
sam_grove 5:3f93dd1d4cb3 437 } SysTick_Type;
sam_grove 5:3f93dd1d4cb3 438
sam_grove 5:3f93dd1d4cb3 439 /* SysTick Control / Status Register Definitions */
sam_grove 5:3f93dd1d4cb3 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
sam_grove 5:3f93dd1d4cb3 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
sam_grove 5:3f93dd1d4cb3 442
sam_grove 5:3f93dd1d4cb3 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
sam_grove 5:3f93dd1d4cb3 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
sam_grove 5:3f93dd1d4cb3 445
sam_grove 5:3f93dd1d4cb3 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
sam_grove 5:3f93dd1d4cb3 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
sam_grove 5:3f93dd1d4cb3 448
sam_grove 5:3f93dd1d4cb3 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
sam_grove 5:3f93dd1d4cb3 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
sam_grove 5:3f93dd1d4cb3 451
sam_grove 5:3f93dd1d4cb3 452 /* SysTick Reload Register Definitions */
sam_grove 5:3f93dd1d4cb3 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
sam_grove 5:3f93dd1d4cb3 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
sam_grove 5:3f93dd1d4cb3 455
sam_grove 5:3f93dd1d4cb3 456 /* SysTick Current Register Definitions */
sam_grove 5:3f93dd1d4cb3 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
sam_grove 5:3f93dd1d4cb3 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
sam_grove 5:3f93dd1d4cb3 459
sam_grove 5:3f93dd1d4cb3 460 /* SysTick Calibration Register Definitions */
sam_grove 5:3f93dd1d4cb3 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
sam_grove 5:3f93dd1d4cb3 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
sam_grove 5:3f93dd1d4cb3 463
sam_grove 5:3f93dd1d4cb3 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
sam_grove 5:3f93dd1d4cb3 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
sam_grove 5:3f93dd1d4cb3 466
sam_grove 5:3f93dd1d4cb3 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
sam_grove 5:3f93dd1d4cb3 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
sam_grove 5:3f93dd1d4cb3 469
sam_grove 5:3f93dd1d4cb3 470 /*@} end of group CMSIS_SysTick */
sam_grove 5:3f93dd1d4cb3 471
sam_grove 5:3f93dd1d4cb3 472 #if (__MPU_PRESENT == 1)
sam_grove 5:3f93dd1d4cb3 473 /** \ingroup CMSIS_core_register
sam_grove 5:3f93dd1d4cb3 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
sam_grove 5:3f93dd1d4cb3 475 \brief Type definitions for the Memory Protection Unit (MPU)
sam_grove 5:3f93dd1d4cb3 476 @{
sam_grove 5:3f93dd1d4cb3 477 */
sam_grove 5:3f93dd1d4cb3 478
sam_grove 5:3f93dd1d4cb3 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
sam_grove 5:3f93dd1d4cb3 480 */
sam_grove 5:3f93dd1d4cb3 481 typedef struct
sam_grove 5:3f93dd1d4cb3 482 {
sam_grove 5:3f93dd1d4cb3 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
sam_grove 5:3f93dd1d4cb3 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
sam_grove 5:3f93dd1d4cb3 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
sam_grove 5:3f93dd1d4cb3 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
sam_grove 5:3f93dd1d4cb3 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
sam_grove 5:3f93dd1d4cb3 488 } MPU_Type;
sam_grove 5:3f93dd1d4cb3 489
sam_grove 5:3f93dd1d4cb3 490 /* MPU Type Register */
sam_grove 5:3f93dd1d4cb3 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
sam_grove 5:3f93dd1d4cb3 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
sam_grove 5:3f93dd1d4cb3 493
sam_grove 5:3f93dd1d4cb3 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
sam_grove 5:3f93dd1d4cb3 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
sam_grove 5:3f93dd1d4cb3 496
sam_grove 5:3f93dd1d4cb3 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
sam_grove 5:3f93dd1d4cb3 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
sam_grove 5:3f93dd1d4cb3 499
sam_grove 5:3f93dd1d4cb3 500 /* MPU Control Register */
sam_grove 5:3f93dd1d4cb3 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
sam_grove 5:3f93dd1d4cb3 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
sam_grove 5:3f93dd1d4cb3 503
sam_grove 5:3f93dd1d4cb3 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
sam_grove 5:3f93dd1d4cb3 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
sam_grove 5:3f93dd1d4cb3 506
sam_grove 5:3f93dd1d4cb3 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
sam_grove 5:3f93dd1d4cb3 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
sam_grove 5:3f93dd1d4cb3 509
sam_grove 5:3f93dd1d4cb3 510 /* MPU Region Number Register */
sam_grove 5:3f93dd1d4cb3 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
sam_grove 5:3f93dd1d4cb3 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
sam_grove 5:3f93dd1d4cb3 513
sam_grove 5:3f93dd1d4cb3 514 /* MPU Region Base Address Register */
sam_grove 5:3f93dd1d4cb3 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
sam_grove 5:3f93dd1d4cb3 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
sam_grove 5:3f93dd1d4cb3 517
sam_grove 5:3f93dd1d4cb3 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
sam_grove 5:3f93dd1d4cb3 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
sam_grove 5:3f93dd1d4cb3 520
sam_grove 5:3f93dd1d4cb3 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
sam_grove 5:3f93dd1d4cb3 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
sam_grove 5:3f93dd1d4cb3 523
sam_grove 5:3f93dd1d4cb3 524 /* MPU Region Attribute and Size Register */
sam_grove 5:3f93dd1d4cb3 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
sam_grove 5:3f93dd1d4cb3 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
sam_grove 5:3f93dd1d4cb3 527
sam_grove 5:3f93dd1d4cb3 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
sam_grove 5:3f93dd1d4cb3 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
sam_grove 5:3f93dd1d4cb3 530
sam_grove 5:3f93dd1d4cb3 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
sam_grove 5:3f93dd1d4cb3 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
sam_grove 5:3f93dd1d4cb3 533
sam_grove 5:3f93dd1d4cb3 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
sam_grove 5:3f93dd1d4cb3 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
sam_grove 5:3f93dd1d4cb3 536
sam_grove 5:3f93dd1d4cb3 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
sam_grove 5:3f93dd1d4cb3 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
sam_grove 5:3f93dd1d4cb3 539
sam_grove 5:3f93dd1d4cb3 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
sam_grove 5:3f93dd1d4cb3 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
sam_grove 5:3f93dd1d4cb3 542
sam_grove 5:3f93dd1d4cb3 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
sam_grove 5:3f93dd1d4cb3 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
sam_grove 5:3f93dd1d4cb3 545
sam_grove 5:3f93dd1d4cb3 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
sam_grove 5:3f93dd1d4cb3 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
sam_grove 5:3f93dd1d4cb3 548
sam_grove 5:3f93dd1d4cb3 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
sam_grove 5:3f93dd1d4cb3 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
sam_grove 5:3f93dd1d4cb3 551
sam_grove 5:3f93dd1d4cb3 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
sam_grove 5:3f93dd1d4cb3 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
sam_grove 5:3f93dd1d4cb3 554
sam_grove 5:3f93dd1d4cb3 555 /*@} end of group CMSIS_MPU */
sam_grove 5:3f93dd1d4cb3 556 #endif
sam_grove 5:3f93dd1d4cb3 557
sam_grove 5:3f93dd1d4cb3 558
sam_grove 5:3f93dd1d4cb3 559 /** \ingroup CMSIS_core_register
sam_grove 5:3f93dd1d4cb3 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
sam_grove 5:3f93dd1d4cb3 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
sam_grove 5:3f93dd1d4cb3 562 are only accessible over DAP and not via processor. Therefore
sam_grove 5:3f93dd1d4cb3 563 they are not covered by the Cortex-M0 header file.
sam_grove 5:3f93dd1d4cb3 564 @{
sam_grove 5:3f93dd1d4cb3 565 */
sam_grove 5:3f93dd1d4cb3 566 /*@} end of group CMSIS_CoreDebug */
sam_grove 5:3f93dd1d4cb3 567
sam_grove 5:3f93dd1d4cb3 568
sam_grove 5:3f93dd1d4cb3 569 /** \ingroup CMSIS_core_register
sam_grove 5:3f93dd1d4cb3 570 \defgroup CMSIS_core_base Core Definitions
sam_grove 5:3f93dd1d4cb3 571 \brief Definitions for base addresses, unions, and structures.
sam_grove 5:3f93dd1d4cb3 572 @{
sam_grove 5:3f93dd1d4cb3 573 */
sam_grove 5:3f93dd1d4cb3 574
sam_grove 5:3f93dd1d4cb3 575 /* Memory mapping of Cortex-M0+ Hardware */
sam_grove 5:3f93dd1d4cb3 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
sam_grove 5:3f93dd1d4cb3 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
sam_grove 5:3f93dd1d4cb3 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
sam_grove 5:3f93dd1d4cb3 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
sam_grove 5:3f93dd1d4cb3 580
sam_grove 5:3f93dd1d4cb3 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
sam_grove 5:3f93dd1d4cb3 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
sam_grove 5:3f93dd1d4cb3 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
sam_grove 5:3f93dd1d4cb3 584
sam_grove 5:3f93dd1d4cb3 585 #if (__MPU_PRESENT == 1)
sam_grove 5:3f93dd1d4cb3 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
sam_grove 5:3f93dd1d4cb3 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
sam_grove 5:3f93dd1d4cb3 588 #endif
sam_grove 5:3f93dd1d4cb3 589
sam_grove 5:3f93dd1d4cb3 590 /*@} */
sam_grove 5:3f93dd1d4cb3 591
sam_grove 5:3f93dd1d4cb3 592
sam_grove 5:3f93dd1d4cb3 593
sam_grove 5:3f93dd1d4cb3 594 /*******************************************************************************
sam_grove 5:3f93dd1d4cb3 595 * Hardware Abstraction Layer
sam_grove 5:3f93dd1d4cb3 596 Core Function Interface contains:
sam_grove 5:3f93dd1d4cb3 597 - Core NVIC Functions
sam_grove 5:3f93dd1d4cb3 598 - Core SysTick Functions
sam_grove 5:3f93dd1d4cb3 599 - Core Register Access Functions
sam_grove 5:3f93dd1d4cb3 600 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
sam_grove 5:3f93dd1d4cb3 602 */
sam_grove 5:3f93dd1d4cb3 603
sam_grove 5:3f93dd1d4cb3 604
sam_grove 5:3f93dd1d4cb3 605
sam_grove 5:3f93dd1d4cb3 606 /* ########################## NVIC functions #################################### */
sam_grove 5:3f93dd1d4cb3 607 /** \ingroup CMSIS_Core_FunctionInterface
sam_grove 5:3f93dd1d4cb3 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
sam_grove 5:3f93dd1d4cb3 609 \brief Functions that manage interrupts and exceptions via the NVIC.
sam_grove 5:3f93dd1d4cb3 610 @{
sam_grove 5:3f93dd1d4cb3 611 */
sam_grove 5:3f93dd1d4cb3 612
sam_grove 5:3f93dd1d4cb3 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
sam_grove 5:3f93dd1d4cb3 614 /* The following MACROS handle generation of the register offset and byte masks */
sam_grove 5:3f93dd1d4cb3 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
sam_grove 5:3f93dd1d4cb3 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
sam_grove 5:3f93dd1d4cb3 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
sam_grove 5:3f93dd1d4cb3 618
sam_grove 5:3f93dd1d4cb3 619
sam_grove 5:3f93dd1d4cb3 620 /** \brief Enable External Interrupt
sam_grove 5:3f93dd1d4cb3 621
sam_grove 5:3f93dd1d4cb3 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
sam_grove 5:3f93dd1d4cb3 623
sam_grove 5:3f93dd1d4cb3 624 \param [in] IRQn External interrupt number. Value cannot be negative.
sam_grove 5:3f93dd1d4cb3 625 */
sam_grove 5:3f93dd1d4cb3 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
sam_grove 5:3f93dd1d4cb3 627 {
sam_grove 5:3f93dd1d4cb3 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
sam_grove 5:3f93dd1d4cb3 629 }
sam_grove 5:3f93dd1d4cb3 630
sam_grove 5:3f93dd1d4cb3 631
sam_grove 5:3f93dd1d4cb3 632 /** \brief Disable External Interrupt
sam_grove 5:3f93dd1d4cb3 633
sam_grove 5:3f93dd1d4cb3 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
sam_grove 5:3f93dd1d4cb3 635
sam_grove 5:3f93dd1d4cb3 636 \param [in] IRQn External interrupt number. Value cannot be negative.
sam_grove 5:3f93dd1d4cb3 637 */
sam_grove 5:3f93dd1d4cb3 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
sam_grove 5:3f93dd1d4cb3 639 {
sam_grove 5:3f93dd1d4cb3 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
sam_grove 5:3f93dd1d4cb3 641 }
sam_grove 5:3f93dd1d4cb3 642
sam_grove 5:3f93dd1d4cb3 643
sam_grove 5:3f93dd1d4cb3 644 /** \brief Get Pending Interrupt
sam_grove 5:3f93dd1d4cb3 645
sam_grove 5:3f93dd1d4cb3 646 The function reads the pending register in the NVIC and returns the pending bit
sam_grove 5:3f93dd1d4cb3 647 for the specified interrupt.
sam_grove 5:3f93dd1d4cb3 648
sam_grove 5:3f93dd1d4cb3 649 \param [in] IRQn Interrupt number.
sam_grove 5:3f93dd1d4cb3 650
sam_grove 5:3f93dd1d4cb3 651 \return 0 Interrupt status is not pending.
sam_grove 5:3f93dd1d4cb3 652 \return 1 Interrupt status is pending.
sam_grove 5:3f93dd1d4cb3 653 */
sam_grove 5:3f93dd1d4cb3 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
sam_grove 5:3f93dd1d4cb3 655 {
sam_grove 5:3f93dd1d4cb3 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
sam_grove 5:3f93dd1d4cb3 657 }
sam_grove 5:3f93dd1d4cb3 658
sam_grove 5:3f93dd1d4cb3 659
sam_grove 5:3f93dd1d4cb3 660 /** \brief Set Pending Interrupt
sam_grove 5:3f93dd1d4cb3 661
sam_grove 5:3f93dd1d4cb3 662 The function sets the pending bit of an external interrupt.
sam_grove 5:3f93dd1d4cb3 663
sam_grove 5:3f93dd1d4cb3 664 \param [in] IRQn Interrupt number. Value cannot be negative.
sam_grove 5:3f93dd1d4cb3 665 */
sam_grove 5:3f93dd1d4cb3 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
sam_grove 5:3f93dd1d4cb3 667 {
sam_grove 5:3f93dd1d4cb3 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
sam_grove 5:3f93dd1d4cb3 669 }
sam_grove 5:3f93dd1d4cb3 670
sam_grove 5:3f93dd1d4cb3 671
sam_grove 5:3f93dd1d4cb3 672 /** \brief Clear Pending Interrupt
sam_grove 5:3f93dd1d4cb3 673
sam_grove 5:3f93dd1d4cb3 674 The function clears the pending bit of an external interrupt.
sam_grove 5:3f93dd1d4cb3 675
sam_grove 5:3f93dd1d4cb3 676 \param [in] IRQn External interrupt number. Value cannot be negative.
sam_grove 5:3f93dd1d4cb3 677 */
sam_grove 5:3f93dd1d4cb3 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
sam_grove 5:3f93dd1d4cb3 679 {
sam_grove 5:3f93dd1d4cb3 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
sam_grove 5:3f93dd1d4cb3 681 }
sam_grove 5:3f93dd1d4cb3 682
sam_grove 5:3f93dd1d4cb3 683
sam_grove 5:3f93dd1d4cb3 684 /** \brief Set Interrupt Priority
sam_grove 5:3f93dd1d4cb3 685
sam_grove 5:3f93dd1d4cb3 686 The function sets the priority of an interrupt.
sam_grove 5:3f93dd1d4cb3 687
sam_grove 5:3f93dd1d4cb3 688 \note The priority cannot be set for every core interrupt.
sam_grove 5:3f93dd1d4cb3 689
sam_grove 5:3f93dd1d4cb3 690 \param [in] IRQn Interrupt number.
sam_grove 5:3f93dd1d4cb3 691 \param [in] priority Priority to set.
sam_grove 5:3f93dd1d4cb3 692 */
sam_grove 5:3f93dd1d4cb3 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
sam_grove 5:3f93dd1d4cb3 694 {
sam_grove 5:3f93dd1d4cb3 695 if(IRQn < 0) {
sam_grove 5:3f93dd1d4cb3 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
sam_grove 5:3f93dd1d4cb3 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
sam_grove 5:3f93dd1d4cb3 698 else {
sam_grove 5:3f93dd1d4cb3 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
sam_grove 5:3f93dd1d4cb3 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
sam_grove 5:3f93dd1d4cb3 701 }
sam_grove 5:3f93dd1d4cb3 702
sam_grove 5:3f93dd1d4cb3 703
sam_grove 5:3f93dd1d4cb3 704 /** \brief Get Interrupt Priority
sam_grove 5:3f93dd1d4cb3 705
sam_grove 5:3f93dd1d4cb3 706 The function reads the priority of an interrupt. The interrupt
sam_grove 5:3f93dd1d4cb3 707 number can be positive to specify an external (device specific)
sam_grove 5:3f93dd1d4cb3 708 interrupt, or negative to specify an internal (core) interrupt.
sam_grove 5:3f93dd1d4cb3 709
sam_grove 5:3f93dd1d4cb3 710
sam_grove 5:3f93dd1d4cb3 711 \param [in] IRQn Interrupt number.
sam_grove 5:3f93dd1d4cb3 712 \return Interrupt Priority. Value is aligned automatically to the implemented
sam_grove 5:3f93dd1d4cb3 713 priority bits of the microcontroller.
sam_grove 5:3f93dd1d4cb3 714 */
sam_grove 5:3f93dd1d4cb3 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
sam_grove 5:3f93dd1d4cb3 716 {
sam_grove 5:3f93dd1d4cb3 717
sam_grove 5:3f93dd1d4cb3 718 if(IRQn < 0) {
sam_grove 5:3f93dd1d4cb3 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
sam_grove 5:3f93dd1d4cb3 720 else {
sam_grove 5:3f93dd1d4cb3 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
sam_grove 5:3f93dd1d4cb3 722 }
sam_grove 5:3f93dd1d4cb3 723
sam_grove 5:3f93dd1d4cb3 724
sam_grove 5:3f93dd1d4cb3 725 /** \brief System Reset
sam_grove 5:3f93dd1d4cb3 726
sam_grove 5:3f93dd1d4cb3 727 The function initiates a system reset request to reset the MCU.
sam_grove 5:3f93dd1d4cb3 728 */
sam_grove 5:3f93dd1d4cb3 729 __STATIC_INLINE void NVIC_SystemReset(void)
sam_grove 5:3f93dd1d4cb3 730 {
sam_grove 5:3f93dd1d4cb3 731 __DSB(); /* Ensure all outstanding memory accesses included
sam_grove 5:3f93dd1d4cb3 732 buffered write are completed before reset */
sam_grove 5:3f93dd1d4cb3 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
sam_grove 5:3f93dd1d4cb3 734 SCB_AIRCR_SYSRESETREQ_Msk);
sam_grove 5:3f93dd1d4cb3 735 __DSB(); /* Ensure completion of memory access */
sam_grove 5:3f93dd1d4cb3 736 while(1); /* wait until reset */
sam_grove 5:3f93dd1d4cb3 737 }
sam_grove 5:3f93dd1d4cb3 738
sam_grove 5:3f93dd1d4cb3 739 /*@} end of CMSIS_Core_NVICFunctions */
sam_grove 5:3f93dd1d4cb3 740
sam_grove 5:3f93dd1d4cb3 741
sam_grove 5:3f93dd1d4cb3 742
sam_grove 5:3f93dd1d4cb3 743 /* ################################## SysTick function ############################################ */
sam_grove 5:3f93dd1d4cb3 744 /** \ingroup CMSIS_Core_FunctionInterface
sam_grove 5:3f93dd1d4cb3 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
sam_grove 5:3f93dd1d4cb3 746 \brief Functions that configure the System.
sam_grove 5:3f93dd1d4cb3 747 @{
sam_grove 5:3f93dd1d4cb3 748 */
sam_grove 5:3f93dd1d4cb3 749
sam_grove 5:3f93dd1d4cb3 750 #if (__Vendor_SysTickConfig == 0)
sam_grove 5:3f93dd1d4cb3 751
sam_grove 5:3f93dd1d4cb3 752 /** \brief System Tick Configuration
sam_grove 5:3f93dd1d4cb3 753
sam_grove 5:3f93dd1d4cb3 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
sam_grove 5:3f93dd1d4cb3 755 Counter is in free running mode to generate periodic interrupts.
sam_grove 5:3f93dd1d4cb3 756
sam_grove 5:3f93dd1d4cb3 757 \param [in] ticks Number of ticks between two interrupts.
sam_grove 5:3f93dd1d4cb3 758
sam_grove 5:3f93dd1d4cb3 759 \return 0 Function succeeded.
sam_grove 5:3f93dd1d4cb3 760 \return 1 Function failed.
sam_grove 5:3f93dd1d4cb3 761
sam_grove 5:3f93dd1d4cb3 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
sam_grove 5:3f93dd1d4cb3 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
sam_grove 5:3f93dd1d4cb3 764 must contain a vendor-specific implementation of this function.
sam_grove 5:3f93dd1d4cb3 765
sam_grove 5:3f93dd1d4cb3 766 */
sam_grove 5:3f93dd1d4cb3 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
sam_grove 5:3f93dd1d4cb3 768 {
sam_grove 5:3f93dd1d4cb3 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
sam_grove 5:3f93dd1d4cb3 770
sam_grove 5:3f93dd1d4cb3 771 SysTick->LOAD = ticks - 1; /* set reload register */
sam_grove 5:3f93dd1d4cb3 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
sam_grove 5:3f93dd1d4cb3 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
sam_grove 5:3f93dd1d4cb3 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
sam_grove 5:3f93dd1d4cb3 775 SysTick_CTRL_TICKINT_Msk |
sam_grove 5:3f93dd1d4cb3 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
sam_grove 5:3f93dd1d4cb3 777 return (0); /* Function successful */
sam_grove 5:3f93dd1d4cb3 778 }
sam_grove 5:3f93dd1d4cb3 779
sam_grove 5:3f93dd1d4cb3 780 #endif
sam_grove 5:3f93dd1d4cb3 781
sam_grove 5:3f93dd1d4cb3 782 /*@} end of CMSIS_Core_SysTickFunctions */
sam_grove 5:3f93dd1d4cb3 783
sam_grove 5:3f93dd1d4cb3 784
sam_grove 5:3f93dd1d4cb3 785
sam_grove 5:3f93dd1d4cb3 786
sam_grove 5:3f93dd1d4cb3 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
sam_grove 5:3f93dd1d4cb3 788
sam_grove 5:3f93dd1d4cb3 789 #endif /* __CMSIS_GENERIC */
sam_grove 5:3f93dd1d4cb3 790
sam_grove 5:3f93dd1d4cb3 791 #ifdef __cplusplus
sam_grove 5:3f93dd1d4cb3 792 }
sam_grove 5:3f93dd1d4cb3 793 #endif