Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.h@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /******************************************************************************
sam_grove 5:3f93dd1d4cb3 2 * @file: system_LPC17xx.h
sam_grove 5:3f93dd1d4cb3 3 * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
sam_grove 5:3f93dd1d4cb3 4 * for the NXP LPC17xx Device Series
sam_grove 5:3f93dd1d4cb3 5 * @version: V1.02
sam_grove 5:3f93dd1d4cb3 6 * @date: 27. July 2009
sam_grove 5:3f93dd1d4cb3 7 *----------------------------------------------------------------------------
sam_grove 5:3f93dd1d4cb3 8 *
sam_grove 5:3f93dd1d4cb3 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
sam_grove 5:3f93dd1d4cb3 10 *
sam_grove 5:3f93dd1d4cb3 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
sam_grove 5:3f93dd1d4cb3 12 * processor based microcontrollers. This file can be freely distributed
sam_grove 5:3f93dd1d4cb3 13 * within development tools that are supporting such ARM based processors.
sam_grove 5:3f93dd1d4cb3 14 *
sam_grove 5:3f93dd1d4cb3 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sam_grove 5:3f93dd1d4cb3 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sam_grove 5:3f93dd1d4cb3 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sam_grove 5:3f93dd1d4cb3 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sam_grove 5:3f93dd1d4cb3 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sam_grove 5:3f93dd1d4cb3 20 *
sam_grove 5:3f93dd1d4cb3 21 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 22
sam_grove 5:3f93dd1d4cb3 23
sam_grove 5:3f93dd1d4cb3 24 #ifndef __SYSTEM_LPC17xx_H
sam_grove 5:3f93dd1d4cb3 25 #define __SYSTEM_LPC17xx_H
sam_grove 5:3f93dd1d4cb3 26
sam_grove 5:3f93dd1d4cb3 27 #ifdef __cplusplus
sam_grove 5:3f93dd1d4cb3 28 extern "C" {
sam_grove 5:3f93dd1d4cb3 29 #endif
sam_grove 5:3f93dd1d4cb3 30
sam_grove 5:3f93dd1d4cb3 31 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
sam_grove 5:3f93dd1d4cb3 32
sam_grove 5:3f93dd1d4cb3 33
sam_grove 5:3f93dd1d4cb3 34 /**
sam_grove 5:3f93dd1d4cb3 35 * Initialize the system
sam_grove 5:3f93dd1d4cb3 36 *
sam_grove 5:3f93dd1d4cb3 37 * @param none
sam_grove 5:3f93dd1d4cb3 38 * @return none
sam_grove 5:3f93dd1d4cb3 39 *
sam_grove 5:3f93dd1d4cb3 40 * @brief Setup the microcontroller system.
sam_grove 5:3f93dd1d4cb3 41 * Initialize the System and update the SystemCoreClock variable.
sam_grove 5:3f93dd1d4cb3 42 */
sam_grove 5:3f93dd1d4cb3 43 extern void SystemInit (void);
sam_grove 5:3f93dd1d4cb3 44
sam_grove 5:3f93dd1d4cb3 45 /**
sam_grove 5:3f93dd1d4cb3 46 * Update SystemCoreClock variable
sam_grove 5:3f93dd1d4cb3 47 *
sam_grove 5:3f93dd1d4cb3 48 * @param none
sam_grove 5:3f93dd1d4cb3 49 * @return none
sam_grove 5:3f93dd1d4cb3 50 *
sam_grove 5:3f93dd1d4cb3 51 * @brief Updates the SystemCoreClock with current core Clock
sam_grove 5:3f93dd1d4cb3 52 * retrieved from cpu registers.
sam_grove 5:3f93dd1d4cb3 53 */
sam_grove 5:3f93dd1d4cb3 54 extern void SystemCoreClockUpdate (void);
sam_grove 5:3f93dd1d4cb3 55
sam_grove 5:3f93dd1d4cb3 56 #ifdef __cplusplus
sam_grove 5:3f93dd1d4cb3 57 }
sam_grove 5:3f93dd1d4cb3 58 #endif
sam_grove 5:3f93dd1d4cb3 59
sam_grove 5:3f93dd1d4cb3 60 #endif /* __SYSTEM_LPC17xx_H */