Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /**************************************************************************//**
sam_grove 5:3f93dd1d4cb3 2 * @file LPC17xx.h
sam_grove 5:3f93dd1d4cb3 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
sam_grove 5:3f93dd1d4cb3 4 * NXP LPC17xx Device Series
sam_grove 5:3f93dd1d4cb3 5 * @version: V1.09
sam_grove 5:3f93dd1d4cb3 6 * @date: 17. March 2010
sam_grove 5:3f93dd1d4cb3 7
sam_grove 5:3f93dd1d4cb3 8 *
sam_grove 5:3f93dd1d4cb3 9 * @note
sam_grove 5:3f93dd1d4cb3 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
sam_grove 5:3f93dd1d4cb3 11 *
sam_grove 5:3f93dd1d4cb3 12 * @par
sam_grove 5:3f93dd1d4cb3 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
sam_grove 5:3f93dd1d4cb3 14 * processor based microcontrollers. This file can be freely distributed
sam_grove 5:3f93dd1d4cb3 15 * within development tools that are supporting such ARM based processors.
sam_grove 5:3f93dd1d4cb3 16 *
sam_grove 5:3f93dd1d4cb3 17 * @par
sam_grove 5:3f93dd1d4cb3 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sam_grove 5:3f93dd1d4cb3 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sam_grove 5:3f93dd1d4cb3 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sam_grove 5:3f93dd1d4cb3 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sam_grove 5:3f93dd1d4cb3 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sam_grove 5:3f93dd1d4cb3 23 *
sam_grove 5:3f93dd1d4cb3 24 ******************************************************************************/
sam_grove 5:3f93dd1d4cb3 25
sam_grove 5:3f93dd1d4cb3 26
sam_grove 5:3f93dd1d4cb3 27 #ifndef __LPC17xx_H__
sam_grove 5:3f93dd1d4cb3 28 #define __LPC17xx_H__
sam_grove 5:3f93dd1d4cb3 29
sam_grove 5:3f93dd1d4cb3 30 /*
sam_grove 5:3f93dd1d4cb3 31 * ==========================================================================
sam_grove 5:3f93dd1d4cb3 32 * ---------- Interrupt Number Definition -----------------------------------
sam_grove 5:3f93dd1d4cb3 33 * ==========================================================================
sam_grove 5:3f93dd1d4cb3 34 */
sam_grove 5:3f93dd1d4cb3 35
sam_grove 5:3f93dd1d4cb3 36 typedef enum IRQn
sam_grove 5:3f93dd1d4cb3 37 {
sam_grove 5:3f93dd1d4cb3 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
sam_grove 5:3f93dd1d4cb3 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sam_grove 5:3f93dd1d4cb3 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
sam_grove 5:3f93dd1d4cb3 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
sam_grove 5:3f93dd1d4cb3 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
sam_grove 5:3f93dd1d4cb3 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
sam_grove 5:3f93dd1d4cb3 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
sam_grove 5:3f93dd1d4cb3 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
sam_grove 5:3f93dd1d4cb3 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
sam_grove 5:3f93dd1d4cb3 47
sam_grove 5:3f93dd1d4cb3 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
sam_grove 5:3f93dd1d4cb3 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
sam_grove 5:3f93dd1d4cb3 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
sam_grove 5:3f93dd1d4cb3 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
sam_grove 5:3f93dd1d4cb3 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
sam_grove 5:3f93dd1d4cb3 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
sam_grove 5:3f93dd1d4cb3 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
sam_grove 5:3f93dd1d4cb3 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
sam_grove 5:3f93dd1d4cb3 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
sam_grove 5:3f93dd1d4cb3 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
sam_grove 5:3f93dd1d4cb3 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
sam_grove 5:3f93dd1d4cb3 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
sam_grove 5:3f93dd1d4cb3 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
sam_grove 5:3f93dd1d4cb3 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
sam_grove 5:3f93dd1d4cb3 62 SPI_IRQn = 13, /*!< SPI Interrupt */
sam_grove 5:3f93dd1d4cb3 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
sam_grove 5:3f93dd1d4cb3 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
sam_grove 5:3f93dd1d4cb3 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
sam_grove 5:3f93dd1d4cb3 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
sam_grove 5:3f93dd1d4cb3 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
sam_grove 5:3f93dd1d4cb3 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
sam_grove 5:3f93dd1d4cb3 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
sam_grove 5:3f93dd1d4cb3 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
sam_grove 5:3f93dd1d4cb3 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
sam_grove 5:3f93dd1d4cb3 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
sam_grove 5:3f93dd1d4cb3 73 USB_IRQn = 24, /*!< USB Interrupt */
sam_grove 5:3f93dd1d4cb3 74 CAN_IRQn = 25, /*!< CAN Interrupt */
sam_grove 5:3f93dd1d4cb3 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
sam_grove 5:3f93dd1d4cb3 76 I2S_IRQn = 27, /*!< I2S Interrupt */
sam_grove 5:3f93dd1d4cb3 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
sam_grove 5:3f93dd1d4cb3 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
sam_grove 5:3f93dd1d4cb3 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
sam_grove 5:3f93dd1d4cb3 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
sam_grove 5:3f93dd1d4cb3 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
sam_grove 5:3f93dd1d4cb3 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
sam_grove 5:3f93dd1d4cb3 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
sam_grove 5:3f93dd1d4cb3 84 } IRQn_Type;
sam_grove 5:3f93dd1d4cb3 85
sam_grove 5:3f93dd1d4cb3 86
sam_grove 5:3f93dd1d4cb3 87 /*
sam_grove 5:3f93dd1d4cb3 88 * ==========================================================================
sam_grove 5:3f93dd1d4cb3 89 * ----------- Processor and Core Peripheral Section ------------------------
sam_grove 5:3f93dd1d4cb3 90 * ==========================================================================
sam_grove 5:3f93dd1d4cb3 91 */
sam_grove 5:3f93dd1d4cb3 92
sam_grove 5:3f93dd1d4cb3 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
sam_grove 5:3f93dd1d4cb3 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
sam_grove 5:3f93dd1d4cb3 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
sam_grove 5:3f93dd1d4cb3 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sam_grove 5:3f93dd1d4cb3 97
sam_grove 5:3f93dd1d4cb3 98
sam_grove 5:3f93dd1d4cb3 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
sam_grove 5:3f93dd1d4cb3 100 #include "system_LPC17xx.h" /* System Header */
sam_grove 5:3f93dd1d4cb3 101
sam_grove 5:3f93dd1d4cb3 102
sam_grove 5:3f93dd1d4cb3 103 /******************************************************************************/
sam_grove 5:3f93dd1d4cb3 104 /* Device Specific Peripheral registers structures */
sam_grove 5:3f93dd1d4cb3 105 /******************************************************************************/
sam_grove 5:3f93dd1d4cb3 106
sam_grove 5:3f93dd1d4cb3 107 #if defined ( __CC_ARM )
sam_grove 5:3f93dd1d4cb3 108 #pragma anon_unions
sam_grove 5:3f93dd1d4cb3 109 #endif
sam_grove 5:3f93dd1d4cb3 110
sam_grove 5:3f93dd1d4cb3 111 /*------------- System Control (SC) ------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 112 typedef struct
sam_grove 5:3f93dd1d4cb3 113 {
sam_grove 5:3f93dd1d4cb3 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
sam_grove 5:3f93dd1d4cb3 115 uint32_t RESERVED0[31];
sam_grove 5:3f93dd1d4cb3 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
sam_grove 5:3f93dd1d4cb3 117 __IO uint32_t PLL0CFG;
sam_grove 5:3f93dd1d4cb3 118 __I uint32_t PLL0STAT;
sam_grove 5:3f93dd1d4cb3 119 __O uint32_t PLL0FEED;
sam_grove 5:3f93dd1d4cb3 120 uint32_t RESERVED1[4];
sam_grove 5:3f93dd1d4cb3 121 __IO uint32_t PLL1CON;
sam_grove 5:3f93dd1d4cb3 122 __IO uint32_t PLL1CFG;
sam_grove 5:3f93dd1d4cb3 123 __I uint32_t PLL1STAT;
sam_grove 5:3f93dd1d4cb3 124 __O uint32_t PLL1FEED;
sam_grove 5:3f93dd1d4cb3 125 uint32_t RESERVED2[4];
sam_grove 5:3f93dd1d4cb3 126 __IO uint32_t PCON;
sam_grove 5:3f93dd1d4cb3 127 __IO uint32_t PCONP;
sam_grove 5:3f93dd1d4cb3 128 uint32_t RESERVED3[15];
sam_grove 5:3f93dd1d4cb3 129 __IO uint32_t CCLKCFG;
sam_grove 5:3f93dd1d4cb3 130 __IO uint32_t USBCLKCFG;
sam_grove 5:3f93dd1d4cb3 131 __IO uint32_t CLKSRCSEL;
sam_grove 5:3f93dd1d4cb3 132 __IO uint32_t CANSLEEPCLR;
sam_grove 5:3f93dd1d4cb3 133 __IO uint32_t CANWAKEFLAGS;
sam_grove 5:3f93dd1d4cb3 134 uint32_t RESERVED4[10];
sam_grove 5:3f93dd1d4cb3 135 __IO uint32_t EXTINT; /* External Interrupts */
sam_grove 5:3f93dd1d4cb3 136 uint32_t RESERVED5;
sam_grove 5:3f93dd1d4cb3 137 __IO uint32_t EXTMODE;
sam_grove 5:3f93dd1d4cb3 138 __IO uint32_t EXTPOLAR;
sam_grove 5:3f93dd1d4cb3 139 uint32_t RESERVED6[12];
sam_grove 5:3f93dd1d4cb3 140 __IO uint32_t RSID; /* Reset */
sam_grove 5:3f93dd1d4cb3 141 uint32_t RESERVED7[7];
sam_grove 5:3f93dd1d4cb3 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
sam_grove 5:3f93dd1d4cb3 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
sam_grove 5:3f93dd1d4cb3 144 __IO uint32_t PCLKSEL0;
sam_grove 5:3f93dd1d4cb3 145 __IO uint32_t PCLKSEL1;
sam_grove 5:3f93dd1d4cb3 146 uint32_t RESERVED8[4];
sam_grove 5:3f93dd1d4cb3 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
sam_grove 5:3f93dd1d4cb3 148 __IO uint32_t DMAREQSEL;
sam_grove 5:3f93dd1d4cb3 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
sam_grove 5:3f93dd1d4cb3 150 } LPC_SC_TypeDef;
sam_grove 5:3f93dd1d4cb3 151
sam_grove 5:3f93dd1d4cb3 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
sam_grove 5:3f93dd1d4cb3 153 typedef struct
sam_grove 5:3f93dd1d4cb3 154 {
sam_grove 5:3f93dd1d4cb3 155 __IO uint32_t PINSEL0;
sam_grove 5:3f93dd1d4cb3 156 __IO uint32_t PINSEL1;
sam_grove 5:3f93dd1d4cb3 157 __IO uint32_t PINSEL2;
sam_grove 5:3f93dd1d4cb3 158 __IO uint32_t PINSEL3;
sam_grove 5:3f93dd1d4cb3 159 __IO uint32_t PINSEL4;
sam_grove 5:3f93dd1d4cb3 160 __IO uint32_t PINSEL5;
sam_grove 5:3f93dd1d4cb3 161 __IO uint32_t PINSEL6;
sam_grove 5:3f93dd1d4cb3 162 __IO uint32_t PINSEL7;
sam_grove 5:3f93dd1d4cb3 163 __IO uint32_t PINSEL8;
sam_grove 5:3f93dd1d4cb3 164 __IO uint32_t PINSEL9;
sam_grove 5:3f93dd1d4cb3 165 __IO uint32_t PINSEL10;
sam_grove 5:3f93dd1d4cb3 166 uint32_t RESERVED0[5];
sam_grove 5:3f93dd1d4cb3 167 __IO uint32_t PINMODE0;
sam_grove 5:3f93dd1d4cb3 168 __IO uint32_t PINMODE1;
sam_grove 5:3f93dd1d4cb3 169 __IO uint32_t PINMODE2;
sam_grove 5:3f93dd1d4cb3 170 __IO uint32_t PINMODE3;
sam_grove 5:3f93dd1d4cb3 171 __IO uint32_t PINMODE4;
sam_grove 5:3f93dd1d4cb3 172 __IO uint32_t PINMODE5;
sam_grove 5:3f93dd1d4cb3 173 __IO uint32_t PINMODE6;
sam_grove 5:3f93dd1d4cb3 174 __IO uint32_t PINMODE7;
sam_grove 5:3f93dd1d4cb3 175 __IO uint32_t PINMODE8;
sam_grove 5:3f93dd1d4cb3 176 __IO uint32_t PINMODE9;
sam_grove 5:3f93dd1d4cb3 177 __IO uint32_t PINMODE_OD0;
sam_grove 5:3f93dd1d4cb3 178 __IO uint32_t PINMODE_OD1;
sam_grove 5:3f93dd1d4cb3 179 __IO uint32_t PINMODE_OD2;
sam_grove 5:3f93dd1d4cb3 180 __IO uint32_t PINMODE_OD3;
sam_grove 5:3f93dd1d4cb3 181 __IO uint32_t PINMODE_OD4;
sam_grove 5:3f93dd1d4cb3 182 __IO uint32_t I2CPADCFG;
sam_grove 5:3f93dd1d4cb3 183 } LPC_PINCON_TypeDef;
sam_grove 5:3f93dd1d4cb3 184
sam_grove 5:3f93dd1d4cb3 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
sam_grove 5:3f93dd1d4cb3 186 typedef struct
sam_grove 5:3f93dd1d4cb3 187 {
sam_grove 5:3f93dd1d4cb3 188 union {
sam_grove 5:3f93dd1d4cb3 189 __IO uint32_t FIODIR;
sam_grove 5:3f93dd1d4cb3 190 struct {
sam_grove 5:3f93dd1d4cb3 191 __IO uint16_t FIODIRL;
sam_grove 5:3f93dd1d4cb3 192 __IO uint16_t FIODIRH;
sam_grove 5:3f93dd1d4cb3 193 };
sam_grove 5:3f93dd1d4cb3 194 struct {
sam_grove 5:3f93dd1d4cb3 195 __IO uint8_t FIODIR0;
sam_grove 5:3f93dd1d4cb3 196 __IO uint8_t FIODIR1;
sam_grove 5:3f93dd1d4cb3 197 __IO uint8_t FIODIR2;
sam_grove 5:3f93dd1d4cb3 198 __IO uint8_t FIODIR3;
sam_grove 5:3f93dd1d4cb3 199 };
sam_grove 5:3f93dd1d4cb3 200 };
sam_grove 5:3f93dd1d4cb3 201 uint32_t RESERVED0[3];
sam_grove 5:3f93dd1d4cb3 202 union {
sam_grove 5:3f93dd1d4cb3 203 __IO uint32_t FIOMASK;
sam_grove 5:3f93dd1d4cb3 204 struct {
sam_grove 5:3f93dd1d4cb3 205 __IO uint16_t FIOMASKL;
sam_grove 5:3f93dd1d4cb3 206 __IO uint16_t FIOMASKH;
sam_grove 5:3f93dd1d4cb3 207 };
sam_grove 5:3f93dd1d4cb3 208 struct {
sam_grove 5:3f93dd1d4cb3 209 __IO uint8_t FIOMASK0;
sam_grove 5:3f93dd1d4cb3 210 __IO uint8_t FIOMASK1;
sam_grove 5:3f93dd1d4cb3 211 __IO uint8_t FIOMASK2;
sam_grove 5:3f93dd1d4cb3 212 __IO uint8_t FIOMASK3;
sam_grove 5:3f93dd1d4cb3 213 };
sam_grove 5:3f93dd1d4cb3 214 };
sam_grove 5:3f93dd1d4cb3 215 union {
sam_grove 5:3f93dd1d4cb3 216 __IO uint32_t FIOPIN;
sam_grove 5:3f93dd1d4cb3 217 struct {
sam_grove 5:3f93dd1d4cb3 218 __IO uint16_t FIOPINL;
sam_grove 5:3f93dd1d4cb3 219 __IO uint16_t FIOPINH;
sam_grove 5:3f93dd1d4cb3 220 };
sam_grove 5:3f93dd1d4cb3 221 struct {
sam_grove 5:3f93dd1d4cb3 222 __IO uint8_t FIOPIN0;
sam_grove 5:3f93dd1d4cb3 223 __IO uint8_t FIOPIN1;
sam_grove 5:3f93dd1d4cb3 224 __IO uint8_t FIOPIN2;
sam_grove 5:3f93dd1d4cb3 225 __IO uint8_t FIOPIN3;
sam_grove 5:3f93dd1d4cb3 226 };
sam_grove 5:3f93dd1d4cb3 227 };
sam_grove 5:3f93dd1d4cb3 228 union {
sam_grove 5:3f93dd1d4cb3 229 __IO uint32_t FIOSET;
sam_grove 5:3f93dd1d4cb3 230 struct {
sam_grove 5:3f93dd1d4cb3 231 __IO uint16_t FIOSETL;
sam_grove 5:3f93dd1d4cb3 232 __IO uint16_t FIOSETH;
sam_grove 5:3f93dd1d4cb3 233 };
sam_grove 5:3f93dd1d4cb3 234 struct {
sam_grove 5:3f93dd1d4cb3 235 __IO uint8_t FIOSET0;
sam_grove 5:3f93dd1d4cb3 236 __IO uint8_t FIOSET1;
sam_grove 5:3f93dd1d4cb3 237 __IO uint8_t FIOSET2;
sam_grove 5:3f93dd1d4cb3 238 __IO uint8_t FIOSET3;
sam_grove 5:3f93dd1d4cb3 239 };
sam_grove 5:3f93dd1d4cb3 240 };
sam_grove 5:3f93dd1d4cb3 241 union {
sam_grove 5:3f93dd1d4cb3 242 __O uint32_t FIOCLR;
sam_grove 5:3f93dd1d4cb3 243 struct {
sam_grove 5:3f93dd1d4cb3 244 __O uint16_t FIOCLRL;
sam_grove 5:3f93dd1d4cb3 245 __O uint16_t FIOCLRH;
sam_grove 5:3f93dd1d4cb3 246 };
sam_grove 5:3f93dd1d4cb3 247 struct {
sam_grove 5:3f93dd1d4cb3 248 __O uint8_t FIOCLR0;
sam_grove 5:3f93dd1d4cb3 249 __O uint8_t FIOCLR1;
sam_grove 5:3f93dd1d4cb3 250 __O uint8_t FIOCLR2;
sam_grove 5:3f93dd1d4cb3 251 __O uint8_t FIOCLR3;
sam_grove 5:3f93dd1d4cb3 252 };
sam_grove 5:3f93dd1d4cb3 253 };
sam_grove 5:3f93dd1d4cb3 254 } LPC_GPIO_TypeDef;
sam_grove 5:3f93dd1d4cb3 255
sam_grove 5:3f93dd1d4cb3 256 typedef struct
sam_grove 5:3f93dd1d4cb3 257 {
sam_grove 5:3f93dd1d4cb3 258 __I uint32_t IntStatus;
sam_grove 5:3f93dd1d4cb3 259 __I uint32_t IO0IntStatR;
sam_grove 5:3f93dd1d4cb3 260 __I uint32_t IO0IntStatF;
sam_grove 5:3f93dd1d4cb3 261 __O uint32_t IO0IntClr;
sam_grove 5:3f93dd1d4cb3 262 __IO uint32_t IO0IntEnR;
sam_grove 5:3f93dd1d4cb3 263 __IO uint32_t IO0IntEnF;
sam_grove 5:3f93dd1d4cb3 264 uint32_t RESERVED0[3];
sam_grove 5:3f93dd1d4cb3 265 __I uint32_t IO2IntStatR;
sam_grove 5:3f93dd1d4cb3 266 __I uint32_t IO2IntStatF;
sam_grove 5:3f93dd1d4cb3 267 __O uint32_t IO2IntClr;
sam_grove 5:3f93dd1d4cb3 268 __IO uint32_t IO2IntEnR;
sam_grove 5:3f93dd1d4cb3 269 __IO uint32_t IO2IntEnF;
sam_grove 5:3f93dd1d4cb3 270 } LPC_GPIOINT_TypeDef;
sam_grove 5:3f93dd1d4cb3 271
sam_grove 5:3f93dd1d4cb3 272 /*------------- Timer (TIM) --------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 273 typedef struct
sam_grove 5:3f93dd1d4cb3 274 {
sam_grove 5:3f93dd1d4cb3 275 __IO uint32_t IR;
sam_grove 5:3f93dd1d4cb3 276 __IO uint32_t TCR;
sam_grove 5:3f93dd1d4cb3 277 __IO uint32_t TC;
sam_grove 5:3f93dd1d4cb3 278 __IO uint32_t PR;
sam_grove 5:3f93dd1d4cb3 279 __IO uint32_t PC;
sam_grove 5:3f93dd1d4cb3 280 __IO uint32_t MCR;
sam_grove 5:3f93dd1d4cb3 281 __IO uint32_t MR0;
sam_grove 5:3f93dd1d4cb3 282 __IO uint32_t MR1;
sam_grove 5:3f93dd1d4cb3 283 __IO uint32_t MR2;
sam_grove 5:3f93dd1d4cb3 284 __IO uint32_t MR3;
sam_grove 5:3f93dd1d4cb3 285 __IO uint32_t CCR;
sam_grove 5:3f93dd1d4cb3 286 __I uint32_t CR0;
sam_grove 5:3f93dd1d4cb3 287 __I uint32_t CR1;
sam_grove 5:3f93dd1d4cb3 288 uint32_t RESERVED0[2];
sam_grove 5:3f93dd1d4cb3 289 __IO uint32_t EMR;
sam_grove 5:3f93dd1d4cb3 290 uint32_t RESERVED1[12];
sam_grove 5:3f93dd1d4cb3 291 __IO uint32_t CTCR;
sam_grove 5:3f93dd1d4cb3 292 } LPC_TIM_TypeDef;
sam_grove 5:3f93dd1d4cb3 293
sam_grove 5:3f93dd1d4cb3 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
sam_grove 5:3f93dd1d4cb3 295 typedef struct
sam_grove 5:3f93dd1d4cb3 296 {
sam_grove 5:3f93dd1d4cb3 297 __IO uint32_t IR;
sam_grove 5:3f93dd1d4cb3 298 __IO uint32_t TCR;
sam_grove 5:3f93dd1d4cb3 299 __IO uint32_t TC;
sam_grove 5:3f93dd1d4cb3 300 __IO uint32_t PR;
sam_grove 5:3f93dd1d4cb3 301 __IO uint32_t PC;
sam_grove 5:3f93dd1d4cb3 302 __IO uint32_t MCR;
sam_grove 5:3f93dd1d4cb3 303 __IO uint32_t MR0;
sam_grove 5:3f93dd1d4cb3 304 __IO uint32_t MR1;
sam_grove 5:3f93dd1d4cb3 305 __IO uint32_t MR2;
sam_grove 5:3f93dd1d4cb3 306 __IO uint32_t MR3;
sam_grove 5:3f93dd1d4cb3 307 __IO uint32_t CCR;
sam_grove 5:3f93dd1d4cb3 308 __I uint32_t CR0;
sam_grove 5:3f93dd1d4cb3 309 __I uint32_t CR1;
sam_grove 5:3f93dd1d4cb3 310 __I uint32_t CR2;
sam_grove 5:3f93dd1d4cb3 311 __I uint32_t CR3;
sam_grove 5:3f93dd1d4cb3 312 uint32_t RESERVED0;
sam_grove 5:3f93dd1d4cb3 313 __IO uint32_t MR4;
sam_grove 5:3f93dd1d4cb3 314 __IO uint32_t MR5;
sam_grove 5:3f93dd1d4cb3 315 __IO uint32_t MR6;
sam_grove 5:3f93dd1d4cb3 316 __IO uint32_t PCR;
sam_grove 5:3f93dd1d4cb3 317 __IO uint32_t LER;
sam_grove 5:3f93dd1d4cb3 318 uint32_t RESERVED1[7];
sam_grove 5:3f93dd1d4cb3 319 __IO uint32_t CTCR;
sam_grove 5:3f93dd1d4cb3 320 } LPC_PWM_TypeDef;
sam_grove 5:3f93dd1d4cb3 321
sam_grove 5:3f93dd1d4cb3 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
sam_grove 5:3f93dd1d4cb3 323 typedef struct
sam_grove 5:3f93dd1d4cb3 324 {
sam_grove 5:3f93dd1d4cb3 325 union {
sam_grove 5:3f93dd1d4cb3 326 __I uint8_t RBR;
sam_grove 5:3f93dd1d4cb3 327 __O uint8_t THR;
sam_grove 5:3f93dd1d4cb3 328 __IO uint8_t DLL;
sam_grove 5:3f93dd1d4cb3 329 uint32_t RESERVED0;
sam_grove 5:3f93dd1d4cb3 330 };
sam_grove 5:3f93dd1d4cb3 331 union {
sam_grove 5:3f93dd1d4cb3 332 __IO uint8_t DLM;
sam_grove 5:3f93dd1d4cb3 333 __IO uint32_t IER;
sam_grove 5:3f93dd1d4cb3 334 };
sam_grove 5:3f93dd1d4cb3 335 union {
sam_grove 5:3f93dd1d4cb3 336 __I uint32_t IIR;
sam_grove 5:3f93dd1d4cb3 337 __O uint8_t FCR;
sam_grove 5:3f93dd1d4cb3 338 };
sam_grove 5:3f93dd1d4cb3 339 __IO uint8_t LCR;
sam_grove 5:3f93dd1d4cb3 340 uint8_t RESERVED1[7];
sam_grove 5:3f93dd1d4cb3 341 __I uint8_t LSR;
sam_grove 5:3f93dd1d4cb3 342 uint8_t RESERVED2[7];
sam_grove 5:3f93dd1d4cb3 343 __IO uint8_t SCR;
sam_grove 5:3f93dd1d4cb3 344 uint8_t RESERVED3[3];
sam_grove 5:3f93dd1d4cb3 345 __IO uint32_t ACR;
sam_grove 5:3f93dd1d4cb3 346 __IO uint8_t ICR;
sam_grove 5:3f93dd1d4cb3 347 uint8_t RESERVED4[3];
sam_grove 5:3f93dd1d4cb3 348 __IO uint8_t FDR;
sam_grove 5:3f93dd1d4cb3 349 uint8_t RESERVED5[7];
sam_grove 5:3f93dd1d4cb3 350 __IO uint8_t TER;
sam_grove 5:3f93dd1d4cb3 351 uint8_t RESERVED6[39];
sam_grove 5:3f93dd1d4cb3 352 __IO uint32_t FIFOLVL;
sam_grove 5:3f93dd1d4cb3 353 } LPC_UART_TypeDef;
sam_grove 5:3f93dd1d4cb3 354
sam_grove 5:3f93dd1d4cb3 355 typedef struct
sam_grove 5:3f93dd1d4cb3 356 {
sam_grove 5:3f93dd1d4cb3 357 union {
sam_grove 5:3f93dd1d4cb3 358 __I uint8_t RBR;
sam_grove 5:3f93dd1d4cb3 359 __O uint8_t THR;
sam_grove 5:3f93dd1d4cb3 360 __IO uint8_t DLL;
sam_grove 5:3f93dd1d4cb3 361 uint32_t RESERVED0;
sam_grove 5:3f93dd1d4cb3 362 };
sam_grove 5:3f93dd1d4cb3 363 union {
sam_grove 5:3f93dd1d4cb3 364 __IO uint8_t DLM;
sam_grove 5:3f93dd1d4cb3 365 __IO uint32_t IER;
sam_grove 5:3f93dd1d4cb3 366 };
sam_grove 5:3f93dd1d4cb3 367 union {
sam_grove 5:3f93dd1d4cb3 368 __I uint32_t IIR;
sam_grove 5:3f93dd1d4cb3 369 __O uint8_t FCR;
sam_grove 5:3f93dd1d4cb3 370 };
sam_grove 5:3f93dd1d4cb3 371 __IO uint8_t LCR;
sam_grove 5:3f93dd1d4cb3 372 uint8_t RESERVED1[7];
sam_grove 5:3f93dd1d4cb3 373 __I uint8_t LSR;
sam_grove 5:3f93dd1d4cb3 374 uint8_t RESERVED2[7];
sam_grove 5:3f93dd1d4cb3 375 __IO uint8_t SCR;
sam_grove 5:3f93dd1d4cb3 376 uint8_t RESERVED3[3];
sam_grove 5:3f93dd1d4cb3 377 __IO uint32_t ACR;
sam_grove 5:3f93dd1d4cb3 378 __IO uint8_t ICR;
sam_grove 5:3f93dd1d4cb3 379 uint8_t RESERVED4[3];
sam_grove 5:3f93dd1d4cb3 380 __IO uint8_t FDR;
sam_grove 5:3f93dd1d4cb3 381 uint8_t RESERVED5[7];
sam_grove 5:3f93dd1d4cb3 382 __IO uint8_t TER;
sam_grove 5:3f93dd1d4cb3 383 uint8_t RESERVED6[39];
sam_grove 5:3f93dd1d4cb3 384 __IO uint32_t FIFOLVL;
sam_grove 5:3f93dd1d4cb3 385 } LPC_UART0_TypeDef;
sam_grove 5:3f93dd1d4cb3 386
sam_grove 5:3f93dd1d4cb3 387 typedef struct
sam_grove 5:3f93dd1d4cb3 388 {
sam_grove 5:3f93dd1d4cb3 389 union {
sam_grove 5:3f93dd1d4cb3 390 __I uint8_t RBR;
sam_grove 5:3f93dd1d4cb3 391 __O uint8_t THR;
sam_grove 5:3f93dd1d4cb3 392 __IO uint8_t DLL;
sam_grove 5:3f93dd1d4cb3 393 uint32_t RESERVED0;
sam_grove 5:3f93dd1d4cb3 394 };
sam_grove 5:3f93dd1d4cb3 395 union {
sam_grove 5:3f93dd1d4cb3 396 __IO uint8_t DLM;
sam_grove 5:3f93dd1d4cb3 397 __IO uint32_t IER;
sam_grove 5:3f93dd1d4cb3 398 };
sam_grove 5:3f93dd1d4cb3 399 union {
sam_grove 5:3f93dd1d4cb3 400 __I uint32_t IIR;
sam_grove 5:3f93dd1d4cb3 401 __O uint8_t FCR;
sam_grove 5:3f93dd1d4cb3 402 };
sam_grove 5:3f93dd1d4cb3 403 __IO uint8_t LCR;
sam_grove 5:3f93dd1d4cb3 404 uint8_t RESERVED1[3];
sam_grove 5:3f93dd1d4cb3 405 __IO uint8_t MCR;
sam_grove 5:3f93dd1d4cb3 406 uint8_t RESERVED2[3];
sam_grove 5:3f93dd1d4cb3 407 __I uint8_t LSR;
sam_grove 5:3f93dd1d4cb3 408 uint8_t RESERVED3[3];
sam_grove 5:3f93dd1d4cb3 409 __I uint8_t MSR;
sam_grove 5:3f93dd1d4cb3 410 uint8_t RESERVED4[3];
sam_grove 5:3f93dd1d4cb3 411 __IO uint8_t SCR;
sam_grove 5:3f93dd1d4cb3 412 uint8_t RESERVED5[3];
sam_grove 5:3f93dd1d4cb3 413 __IO uint32_t ACR;
sam_grove 5:3f93dd1d4cb3 414 uint32_t RESERVED6;
sam_grove 5:3f93dd1d4cb3 415 __IO uint32_t FDR;
sam_grove 5:3f93dd1d4cb3 416 uint32_t RESERVED7;
sam_grove 5:3f93dd1d4cb3 417 __IO uint8_t TER;
sam_grove 5:3f93dd1d4cb3 418 uint8_t RESERVED8[27];
sam_grove 5:3f93dd1d4cb3 419 __IO uint8_t RS485CTRL;
sam_grove 5:3f93dd1d4cb3 420 uint8_t RESERVED9[3];
sam_grove 5:3f93dd1d4cb3 421 __IO uint8_t ADRMATCH;
sam_grove 5:3f93dd1d4cb3 422 uint8_t RESERVED10[3];
sam_grove 5:3f93dd1d4cb3 423 __IO uint8_t RS485DLY;
sam_grove 5:3f93dd1d4cb3 424 uint8_t RESERVED11[3];
sam_grove 5:3f93dd1d4cb3 425 __IO uint32_t FIFOLVL;
sam_grove 5:3f93dd1d4cb3 426 } LPC_UART1_TypeDef;
sam_grove 5:3f93dd1d4cb3 427
sam_grove 5:3f93dd1d4cb3 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
sam_grove 5:3f93dd1d4cb3 429 typedef struct
sam_grove 5:3f93dd1d4cb3 430 {
sam_grove 5:3f93dd1d4cb3 431 __IO uint32_t SPCR;
sam_grove 5:3f93dd1d4cb3 432 __I uint32_t SPSR;
sam_grove 5:3f93dd1d4cb3 433 __IO uint32_t SPDR;
sam_grove 5:3f93dd1d4cb3 434 __IO uint32_t SPCCR;
sam_grove 5:3f93dd1d4cb3 435 uint32_t RESERVED0[3];
sam_grove 5:3f93dd1d4cb3 436 __IO uint32_t SPINT;
sam_grove 5:3f93dd1d4cb3 437 } LPC_SPI_TypeDef;
sam_grove 5:3f93dd1d4cb3 438
sam_grove 5:3f93dd1d4cb3 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
sam_grove 5:3f93dd1d4cb3 440 typedef struct
sam_grove 5:3f93dd1d4cb3 441 {
sam_grove 5:3f93dd1d4cb3 442 __IO uint32_t CR0;
sam_grove 5:3f93dd1d4cb3 443 __IO uint32_t CR1;
sam_grove 5:3f93dd1d4cb3 444 __IO uint32_t DR;
sam_grove 5:3f93dd1d4cb3 445 __I uint32_t SR;
sam_grove 5:3f93dd1d4cb3 446 __IO uint32_t CPSR;
sam_grove 5:3f93dd1d4cb3 447 __IO uint32_t IMSC;
sam_grove 5:3f93dd1d4cb3 448 __IO uint32_t RIS;
sam_grove 5:3f93dd1d4cb3 449 __IO uint32_t MIS;
sam_grove 5:3f93dd1d4cb3 450 __IO uint32_t ICR;
sam_grove 5:3f93dd1d4cb3 451 __IO uint32_t DMACR;
sam_grove 5:3f93dd1d4cb3 452 } LPC_SSP_TypeDef;
sam_grove 5:3f93dd1d4cb3 453
sam_grove 5:3f93dd1d4cb3 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
sam_grove 5:3f93dd1d4cb3 455 typedef struct
sam_grove 5:3f93dd1d4cb3 456 {
sam_grove 5:3f93dd1d4cb3 457 __IO uint32_t I2CONSET;
sam_grove 5:3f93dd1d4cb3 458 __I uint32_t I2STAT;
sam_grove 5:3f93dd1d4cb3 459 __IO uint32_t I2DAT;
sam_grove 5:3f93dd1d4cb3 460 __IO uint32_t I2ADR0;
sam_grove 5:3f93dd1d4cb3 461 __IO uint32_t I2SCLH;
sam_grove 5:3f93dd1d4cb3 462 __IO uint32_t I2SCLL;
sam_grove 5:3f93dd1d4cb3 463 __O uint32_t I2CONCLR;
sam_grove 5:3f93dd1d4cb3 464 __IO uint32_t MMCTRL;
sam_grove 5:3f93dd1d4cb3 465 __IO uint32_t I2ADR1;
sam_grove 5:3f93dd1d4cb3 466 __IO uint32_t I2ADR2;
sam_grove 5:3f93dd1d4cb3 467 __IO uint32_t I2ADR3;
sam_grove 5:3f93dd1d4cb3 468 __I uint32_t I2DATA_BUFFER;
sam_grove 5:3f93dd1d4cb3 469 __IO uint32_t I2MASK0;
sam_grove 5:3f93dd1d4cb3 470 __IO uint32_t I2MASK1;
sam_grove 5:3f93dd1d4cb3 471 __IO uint32_t I2MASK2;
sam_grove 5:3f93dd1d4cb3 472 __IO uint32_t I2MASK3;
sam_grove 5:3f93dd1d4cb3 473 } LPC_I2C_TypeDef;
sam_grove 5:3f93dd1d4cb3 474
sam_grove 5:3f93dd1d4cb3 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
sam_grove 5:3f93dd1d4cb3 476 typedef struct
sam_grove 5:3f93dd1d4cb3 477 {
sam_grove 5:3f93dd1d4cb3 478 __IO uint32_t I2SDAO;
sam_grove 5:3f93dd1d4cb3 479 __IO uint32_t I2SDAI;
sam_grove 5:3f93dd1d4cb3 480 __O uint32_t I2STXFIFO;
sam_grove 5:3f93dd1d4cb3 481 __I uint32_t I2SRXFIFO;
sam_grove 5:3f93dd1d4cb3 482 __I uint32_t I2SSTATE;
sam_grove 5:3f93dd1d4cb3 483 __IO uint32_t I2SDMA1;
sam_grove 5:3f93dd1d4cb3 484 __IO uint32_t I2SDMA2;
sam_grove 5:3f93dd1d4cb3 485 __IO uint32_t I2SIRQ;
sam_grove 5:3f93dd1d4cb3 486 __IO uint32_t I2STXRATE;
sam_grove 5:3f93dd1d4cb3 487 __IO uint32_t I2SRXRATE;
sam_grove 5:3f93dd1d4cb3 488 __IO uint32_t I2STXBITRATE;
sam_grove 5:3f93dd1d4cb3 489 __IO uint32_t I2SRXBITRATE;
sam_grove 5:3f93dd1d4cb3 490 __IO uint32_t I2STXMODE;
sam_grove 5:3f93dd1d4cb3 491 __IO uint32_t I2SRXMODE;
sam_grove 5:3f93dd1d4cb3 492 } LPC_I2S_TypeDef;
sam_grove 5:3f93dd1d4cb3 493
sam_grove 5:3f93dd1d4cb3 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
sam_grove 5:3f93dd1d4cb3 495 typedef struct
sam_grove 5:3f93dd1d4cb3 496 {
sam_grove 5:3f93dd1d4cb3 497 __IO uint32_t RICOMPVAL;
sam_grove 5:3f93dd1d4cb3 498 __IO uint32_t RIMASK;
sam_grove 5:3f93dd1d4cb3 499 __IO uint8_t RICTRL;
sam_grove 5:3f93dd1d4cb3 500 uint8_t RESERVED0[3];
sam_grove 5:3f93dd1d4cb3 501 __IO uint32_t RICOUNTER;
sam_grove 5:3f93dd1d4cb3 502 } LPC_RIT_TypeDef;
sam_grove 5:3f93dd1d4cb3 503
sam_grove 5:3f93dd1d4cb3 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
sam_grove 5:3f93dd1d4cb3 505 typedef struct
sam_grove 5:3f93dd1d4cb3 506 {
sam_grove 5:3f93dd1d4cb3 507 __IO uint8_t ILR;
sam_grove 5:3f93dd1d4cb3 508 uint8_t RESERVED0[7];
sam_grove 5:3f93dd1d4cb3 509 __IO uint8_t CCR;
sam_grove 5:3f93dd1d4cb3 510 uint8_t RESERVED1[3];
sam_grove 5:3f93dd1d4cb3 511 __IO uint8_t CIIR;
sam_grove 5:3f93dd1d4cb3 512 uint8_t RESERVED2[3];
sam_grove 5:3f93dd1d4cb3 513 __IO uint8_t AMR;
sam_grove 5:3f93dd1d4cb3 514 uint8_t RESERVED3[3];
sam_grove 5:3f93dd1d4cb3 515 __I uint32_t CTIME0;
sam_grove 5:3f93dd1d4cb3 516 __I uint32_t CTIME1;
sam_grove 5:3f93dd1d4cb3 517 __I uint32_t CTIME2;
sam_grove 5:3f93dd1d4cb3 518 __IO uint8_t SEC;
sam_grove 5:3f93dd1d4cb3 519 uint8_t RESERVED4[3];
sam_grove 5:3f93dd1d4cb3 520 __IO uint8_t MIN;
sam_grove 5:3f93dd1d4cb3 521 uint8_t RESERVED5[3];
sam_grove 5:3f93dd1d4cb3 522 __IO uint8_t HOUR;
sam_grove 5:3f93dd1d4cb3 523 uint8_t RESERVED6[3];
sam_grove 5:3f93dd1d4cb3 524 __IO uint8_t DOM;
sam_grove 5:3f93dd1d4cb3 525 uint8_t RESERVED7[3];
sam_grove 5:3f93dd1d4cb3 526 __IO uint8_t DOW;
sam_grove 5:3f93dd1d4cb3 527 uint8_t RESERVED8[3];
sam_grove 5:3f93dd1d4cb3 528 __IO uint16_t DOY;
sam_grove 5:3f93dd1d4cb3 529 uint16_t RESERVED9;
sam_grove 5:3f93dd1d4cb3 530 __IO uint8_t MONTH;
sam_grove 5:3f93dd1d4cb3 531 uint8_t RESERVED10[3];
sam_grove 5:3f93dd1d4cb3 532 __IO uint16_t YEAR;
sam_grove 5:3f93dd1d4cb3 533 uint16_t RESERVED11;
sam_grove 5:3f93dd1d4cb3 534 __IO uint32_t CALIBRATION;
sam_grove 5:3f93dd1d4cb3 535 __IO uint32_t GPREG0;
sam_grove 5:3f93dd1d4cb3 536 __IO uint32_t GPREG1;
sam_grove 5:3f93dd1d4cb3 537 __IO uint32_t GPREG2;
sam_grove 5:3f93dd1d4cb3 538 __IO uint32_t GPREG3;
sam_grove 5:3f93dd1d4cb3 539 __IO uint32_t GPREG4;
sam_grove 5:3f93dd1d4cb3 540 __IO uint8_t RTC_AUXEN;
sam_grove 5:3f93dd1d4cb3 541 uint8_t RESERVED12[3];
sam_grove 5:3f93dd1d4cb3 542 __IO uint8_t RTC_AUX;
sam_grove 5:3f93dd1d4cb3 543 uint8_t RESERVED13[3];
sam_grove 5:3f93dd1d4cb3 544 __IO uint8_t ALSEC;
sam_grove 5:3f93dd1d4cb3 545 uint8_t RESERVED14[3];
sam_grove 5:3f93dd1d4cb3 546 __IO uint8_t ALMIN;
sam_grove 5:3f93dd1d4cb3 547 uint8_t RESERVED15[3];
sam_grove 5:3f93dd1d4cb3 548 __IO uint8_t ALHOUR;
sam_grove 5:3f93dd1d4cb3 549 uint8_t RESERVED16[3];
sam_grove 5:3f93dd1d4cb3 550 __IO uint8_t ALDOM;
sam_grove 5:3f93dd1d4cb3 551 uint8_t RESERVED17[3];
sam_grove 5:3f93dd1d4cb3 552 __IO uint8_t ALDOW;
sam_grove 5:3f93dd1d4cb3 553 uint8_t RESERVED18[3];
sam_grove 5:3f93dd1d4cb3 554 __IO uint16_t ALDOY;
sam_grove 5:3f93dd1d4cb3 555 uint16_t RESERVED19;
sam_grove 5:3f93dd1d4cb3 556 __IO uint8_t ALMON;
sam_grove 5:3f93dd1d4cb3 557 uint8_t RESERVED20[3];
sam_grove 5:3f93dd1d4cb3 558 __IO uint16_t ALYEAR;
sam_grove 5:3f93dd1d4cb3 559 uint16_t RESERVED21;
sam_grove 5:3f93dd1d4cb3 560 } LPC_RTC_TypeDef;
sam_grove 5:3f93dd1d4cb3 561
sam_grove 5:3f93dd1d4cb3 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
sam_grove 5:3f93dd1d4cb3 563 typedef struct
sam_grove 5:3f93dd1d4cb3 564 {
sam_grove 5:3f93dd1d4cb3 565 __IO uint8_t WDMOD;
sam_grove 5:3f93dd1d4cb3 566 uint8_t RESERVED0[3];
sam_grove 5:3f93dd1d4cb3 567 __IO uint32_t WDTC;
sam_grove 5:3f93dd1d4cb3 568 __O uint8_t WDFEED;
sam_grove 5:3f93dd1d4cb3 569 uint8_t RESERVED1[3];
sam_grove 5:3f93dd1d4cb3 570 __I uint32_t WDTV;
sam_grove 5:3f93dd1d4cb3 571 __IO uint32_t WDCLKSEL;
sam_grove 5:3f93dd1d4cb3 572 } LPC_WDT_TypeDef;
sam_grove 5:3f93dd1d4cb3 573
sam_grove 5:3f93dd1d4cb3 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
sam_grove 5:3f93dd1d4cb3 575 typedef struct
sam_grove 5:3f93dd1d4cb3 576 {
sam_grove 5:3f93dd1d4cb3 577 __IO uint32_t ADCR;
sam_grove 5:3f93dd1d4cb3 578 __IO uint32_t ADGDR;
sam_grove 5:3f93dd1d4cb3 579 uint32_t RESERVED0;
sam_grove 5:3f93dd1d4cb3 580 __IO uint32_t ADINTEN;
sam_grove 5:3f93dd1d4cb3 581 __I uint32_t ADDR0;
sam_grove 5:3f93dd1d4cb3 582 __I uint32_t ADDR1;
sam_grove 5:3f93dd1d4cb3 583 __I uint32_t ADDR2;
sam_grove 5:3f93dd1d4cb3 584 __I uint32_t ADDR3;
sam_grove 5:3f93dd1d4cb3 585 __I uint32_t ADDR4;
sam_grove 5:3f93dd1d4cb3 586 __I uint32_t ADDR5;
sam_grove 5:3f93dd1d4cb3 587 __I uint32_t ADDR6;
sam_grove 5:3f93dd1d4cb3 588 __I uint32_t ADDR7;
sam_grove 5:3f93dd1d4cb3 589 __I uint32_t ADSTAT;
sam_grove 5:3f93dd1d4cb3 590 __IO uint32_t ADTRM;
sam_grove 5:3f93dd1d4cb3 591 } LPC_ADC_TypeDef;
sam_grove 5:3f93dd1d4cb3 592
sam_grove 5:3f93dd1d4cb3 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
sam_grove 5:3f93dd1d4cb3 594 typedef struct
sam_grove 5:3f93dd1d4cb3 595 {
sam_grove 5:3f93dd1d4cb3 596 __IO uint32_t DACR;
sam_grove 5:3f93dd1d4cb3 597 __IO uint32_t DACCTRL;
sam_grove 5:3f93dd1d4cb3 598 __IO uint16_t DACCNTVAL;
sam_grove 5:3f93dd1d4cb3 599 } LPC_DAC_TypeDef;
sam_grove 5:3f93dd1d4cb3 600
sam_grove 5:3f93dd1d4cb3 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
sam_grove 5:3f93dd1d4cb3 602 typedef struct
sam_grove 5:3f93dd1d4cb3 603 {
sam_grove 5:3f93dd1d4cb3 604 __I uint32_t MCCON;
sam_grove 5:3f93dd1d4cb3 605 __O uint32_t MCCON_SET;
sam_grove 5:3f93dd1d4cb3 606 __O uint32_t MCCON_CLR;
sam_grove 5:3f93dd1d4cb3 607 __I uint32_t MCCAPCON;
sam_grove 5:3f93dd1d4cb3 608 __O uint32_t MCCAPCON_SET;
sam_grove 5:3f93dd1d4cb3 609 __O uint32_t MCCAPCON_CLR;
sam_grove 5:3f93dd1d4cb3 610 __IO uint32_t MCTIM0;
sam_grove 5:3f93dd1d4cb3 611 __IO uint32_t MCTIM1;
sam_grove 5:3f93dd1d4cb3 612 __IO uint32_t MCTIM2;
sam_grove 5:3f93dd1d4cb3 613 __IO uint32_t MCPER0;
sam_grove 5:3f93dd1d4cb3 614 __IO uint32_t MCPER1;
sam_grove 5:3f93dd1d4cb3 615 __IO uint32_t MCPER2;
sam_grove 5:3f93dd1d4cb3 616 __IO uint32_t MCPW0;
sam_grove 5:3f93dd1d4cb3 617 __IO uint32_t MCPW1;
sam_grove 5:3f93dd1d4cb3 618 __IO uint32_t MCPW2;
sam_grove 5:3f93dd1d4cb3 619 __IO uint32_t MCDEADTIME;
sam_grove 5:3f93dd1d4cb3 620 __IO uint32_t MCCCP;
sam_grove 5:3f93dd1d4cb3 621 __IO uint32_t MCCR0;
sam_grove 5:3f93dd1d4cb3 622 __IO uint32_t MCCR1;
sam_grove 5:3f93dd1d4cb3 623 __IO uint32_t MCCR2;
sam_grove 5:3f93dd1d4cb3 624 __I uint32_t MCINTEN;
sam_grove 5:3f93dd1d4cb3 625 __O uint32_t MCINTEN_SET;
sam_grove 5:3f93dd1d4cb3 626 __O uint32_t MCINTEN_CLR;
sam_grove 5:3f93dd1d4cb3 627 __I uint32_t MCCNTCON;
sam_grove 5:3f93dd1d4cb3 628 __O uint32_t MCCNTCON_SET;
sam_grove 5:3f93dd1d4cb3 629 __O uint32_t MCCNTCON_CLR;
sam_grove 5:3f93dd1d4cb3 630 __I uint32_t MCINTFLAG;
sam_grove 5:3f93dd1d4cb3 631 __O uint32_t MCINTFLAG_SET;
sam_grove 5:3f93dd1d4cb3 632 __O uint32_t MCINTFLAG_CLR;
sam_grove 5:3f93dd1d4cb3 633 __O uint32_t MCCAP_CLR;
sam_grove 5:3f93dd1d4cb3 634 } LPC_MCPWM_TypeDef;
sam_grove 5:3f93dd1d4cb3 635
sam_grove 5:3f93dd1d4cb3 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
sam_grove 5:3f93dd1d4cb3 637 typedef struct
sam_grove 5:3f93dd1d4cb3 638 {
sam_grove 5:3f93dd1d4cb3 639 __O uint32_t QEICON;
sam_grove 5:3f93dd1d4cb3 640 __I uint32_t QEISTAT;
sam_grove 5:3f93dd1d4cb3 641 __IO uint32_t QEICONF;
sam_grove 5:3f93dd1d4cb3 642 __I uint32_t QEIPOS;
sam_grove 5:3f93dd1d4cb3 643 __IO uint32_t QEIMAXPOS;
sam_grove 5:3f93dd1d4cb3 644 __IO uint32_t CMPOS0;
sam_grove 5:3f93dd1d4cb3 645 __IO uint32_t CMPOS1;
sam_grove 5:3f93dd1d4cb3 646 __IO uint32_t CMPOS2;
sam_grove 5:3f93dd1d4cb3 647 __I uint32_t INXCNT;
sam_grove 5:3f93dd1d4cb3 648 __IO uint32_t INXCMP;
sam_grove 5:3f93dd1d4cb3 649 __IO uint32_t QEILOAD;
sam_grove 5:3f93dd1d4cb3 650 __I uint32_t QEITIME;
sam_grove 5:3f93dd1d4cb3 651 __I uint32_t QEIVEL;
sam_grove 5:3f93dd1d4cb3 652 __I uint32_t QEICAP;
sam_grove 5:3f93dd1d4cb3 653 __IO uint32_t VELCOMP;
sam_grove 5:3f93dd1d4cb3 654 __IO uint32_t FILTER;
sam_grove 5:3f93dd1d4cb3 655 uint32_t RESERVED0[998];
sam_grove 5:3f93dd1d4cb3 656 __O uint32_t QEIIEC;
sam_grove 5:3f93dd1d4cb3 657 __O uint32_t QEIIES;
sam_grove 5:3f93dd1d4cb3 658 __I uint32_t QEIINTSTAT;
sam_grove 5:3f93dd1d4cb3 659 __I uint32_t QEIIE;
sam_grove 5:3f93dd1d4cb3 660 __O uint32_t QEICLR;
sam_grove 5:3f93dd1d4cb3 661 __O uint32_t QEISET;
sam_grove 5:3f93dd1d4cb3 662 } LPC_QEI_TypeDef;
sam_grove 5:3f93dd1d4cb3 663
sam_grove 5:3f93dd1d4cb3 664 /*------------- Controller Area Network (CAN) --------------------------------*/
sam_grove 5:3f93dd1d4cb3 665 typedef struct
sam_grove 5:3f93dd1d4cb3 666 {
sam_grove 5:3f93dd1d4cb3 667 __IO uint32_t mask[512]; /* ID Masks */
sam_grove 5:3f93dd1d4cb3 668 } LPC_CANAF_RAM_TypeDef;
sam_grove 5:3f93dd1d4cb3 669
sam_grove 5:3f93dd1d4cb3 670 typedef struct /* Acceptance Filter Registers */
sam_grove 5:3f93dd1d4cb3 671 {
sam_grove 5:3f93dd1d4cb3 672 __IO uint32_t AFMR;
sam_grove 5:3f93dd1d4cb3 673 __IO uint32_t SFF_sa;
sam_grove 5:3f93dd1d4cb3 674 __IO uint32_t SFF_GRP_sa;
sam_grove 5:3f93dd1d4cb3 675 __IO uint32_t EFF_sa;
sam_grove 5:3f93dd1d4cb3 676 __IO uint32_t EFF_GRP_sa;
sam_grove 5:3f93dd1d4cb3 677 __IO uint32_t ENDofTable;
sam_grove 5:3f93dd1d4cb3 678 __I uint32_t LUTerrAd;
sam_grove 5:3f93dd1d4cb3 679 __I uint32_t LUTerr;
sam_grove 5:3f93dd1d4cb3 680 __IO uint32_t FCANIE;
sam_grove 5:3f93dd1d4cb3 681 __IO uint32_t FCANIC0;
sam_grove 5:3f93dd1d4cb3 682 __IO uint32_t FCANIC1;
sam_grove 5:3f93dd1d4cb3 683 } LPC_CANAF_TypeDef;
sam_grove 5:3f93dd1d4cb3 684
sam_grove 5:3f93dd1d4cb3 685 typedef struct /* Central Registers */
sam_grove 5:3f93dd1d4cb3 686 {
sam_grove 5:3f93dd1d4cb3 687 __I uint32_t CANTxSR;
sam_grove 5:3f93dd1d4cb3 688 __I uint32_t CANRxSR;
sam_grove 5:3f93dd1d4cb3 689 __I uint32_t CANMSR;
sam_grove 5:3f93dd1d4cb3 690 } LPC_CANCR_TypeDef;
sam_grove 5:3f93dd1d4cb3 691
sam_grove 5:3f93dd1d4cb3 692 typedef struct /* Controller Registers */
sam_grove 5:3f93dd1d4cb3 693 {
sam_grove 5:3f93dd1d4cb3 694 __IO uint32_t MOD;
sam_grove 5:3f93dd1d4cb3 695 __O uint32_t CMR;
sam_grove 5:3f93dd1d4cb3 696 __IO uint32_t GSR;
sam_grove 5:3f93dd1d4cb3 697 __I uint32_t ICR;
sam_grove 5:3f93dd1d4cb3 698 __IO uint32_t IER;
sam_grove 5:3f93dd1d4cb3 699 __IO uint32_t BTR;
sam_grove 5:3f93dd1d4cb3 700 __IO uint32_t EWL;
sam_grove 5:3f93dd1d4cb3 701 __I uint32_t SR;
sam_grove 5:3f93dd1d4cb3 702 __IO uint32_t RFS;
sam_grove 5:3f93dd1d4cb3 703 __IO uint32_t RID;
sam_grove 5:3f93dd1d4cb3 704 __IO uint32_t RDA;
sam_grove 5:3f93dd1d4cb3 705 __IO uint32_t RDB;
sam_grove 5:3f93dd1d4cb3 706 __IO uint32_t TFI1;
sam_grove 5:3f93dd1d4cb3 707 __IO uint32_t TID1;
sam_grove 5:3f93dd1d4cb3 708 __IO uint32_t TDA1;
sam_grove 5:3f93dd1d4cb3 709 __IO uint32_t TDB1;
sam_grove 5:3f93dd1d4cb3 710 __IO uint32_t TFI2;
sam_grove 5:3f93dd1d4cb3 711 __IO uint32_t TID2;
sam_grove 5:3f93dd1d4cb3 712 __IO uint32_t TDA2;
sam_grove 5:3f93dd1d4cb3 713 __IO uint32_t TDB2;
sam_grove 5:3f93dd1d4cb3 714 __IO uint32_t TFI3;
sam_grove 5:3f93dd1d4cb3 715 __IO uint32_t TID3;
sam_grove 5:3f93dd1d4cb3 716 __IO uint32_t TDA3;
sam_grove 5:3f93dd1d4cb3 717 __IO uint32_t TDB3;
sam_grove 5:3f93dd1d4cb3 718 } LPC_CAN_TypeDef;
sam_grove 5:3f93dd1d4cb3 719
sam_grove 5:3f93dd1d4cb3 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
sam_grove 5:3f93dd1d4cb3 721 typedef struct /* Common Registers */
sam_grove 5:3f93dd1d4cb3 722 {
sam_grove 5:3f93dd1d4cb3 723 __I uint32_t DMACIntStat;
sam_grove 5:3f93dd1d4cb3 724 __I uint32_t DMACIntTCStat;
sam_grove 5:3f93dd1d4cb3 725 __O uint32_t DMACIntTCClear;
sam_grove 5:3f93dd1d4cb3 726 __I uint32_t DMACIntErrStat;
sam_grove 5:3f93dd1d4cb3 727 __O uint32_t DMACIntErrClr;
sam_grove 5:3f93dd1d4cb3 728 __I uint32_t DMACRawIntTCStat;
sam_grove 5:3f93dd1d4cb3 729 __I uint32_t DMACRawIntErrStat;
sam_grove 5:3f93dd1d4cb3 730 __I uint32_t DMACEnbldChns;
sam_grove 5:3f93dd1d4cb3 731 __IO uint32_t DMACSoftBReq;
sam_grove 5:3f93dd1d4cb3 732 __IO uint32_t DMACSoftSReq;
sam_grove 5:3f93dd1d4cb3 733 __IO uint32_t DMACSoftLBReq;
sam_grove 5:3f93dd1d4cb3 734 __IO uint32_t DMACSoftLSReq;
sam_grove 5:3f93dd1d4cb3 735 __IO uint32_t DMACConfig;
sam_grove 5:3f93dd1d4cb3 736 __IO uint32_t DMACSync;
sam_grove 5:3f93dd1d4cb3 737 } LPC_GPDMA_TypeDef;
sam_grove 5:3f93dd1d4cb3 738
sam_grove 5:3f93dd1d4cb3 739 typedef struct /* Channel Registers */
sam_grove 5:3f93dd1d4cb3 740 {
sam_grove 5:3f93dd1d4cb3 741 __IO uint32_t DMACCSrcAddr;
sam_grove 5:3f93dd1d4cb3 742 __IO uint32_t DMACCDestAddr;
sam_grove 5:3f93dd1d4cb3 743 __IO uint32_t DMACCLLI;
sam_grove 5:3f93dd1d4cb3 744 __IO uint32_t DMACCControl;
sam_grove 5:3f93dd1d4cb3 745 __IO uint32_t DMACCConfig;
sam_grove 5:3f93dd1d4cb3 746 } LPC_GPDMACH_TypeDef;
sam_grove 5:3f93dd1d4cb3 747
sam_grove 5:3f93dd1d4cb3 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
sam_grove 5:3f93dd1d4cb3 749 typedef struct
sam_grove 5:3f93dd1d4cb3 750 {
sam_grove 5:3f93dd1d4cb3 751 __I uint32_t HcRevision; /* USB Host Registers */
sam_grove 5:3f93dd1d4cb3 752 __IO uint32_t HcControl;
sam_grove 5:3f93dd1d4cb3 753 __IO uint32_t HcCommandStatus;
sam_grove 5:3f93dd1d4cb3 754 __IO uint32_t HcInterruptStatus;
sam_grove 5:3f93dd1d4cb3 755 __IO uint32_t HcInterruptEnable;
sam_grove 5:3f93dd1d4cb3 756 __IO uint32_t HcInterruptDisable;
sam_grove 5:3f93dd1d4cb3 757 __IO uint32_t HcHCCA;
sam_grove 5:3f93dd1d4cb3 758 __I uint32_t HcPeriodCurrentED;
sam_grove 5:3f93dd1d4cb3 759 __IO uint32_t HcControlHeadED;
sam_grove 5:3f93dd1d4cb3 760 __IO uint32_t HcControlCurrentED;
sam_grove 5:3f93dd1d4cb3 761 __IO uint32_t HcBulkHeadED;
sam_grove 5:3f93dd1d4cb3 762 __IO uint32_t HcBulkCurrentED;
sam_grove 5:3f93dd1d4cb3 763 __I uint32_t HcDoneHead;
sam_grove 5:3f93dd1d4cb3 764 __IO uint32_t HcFmInterval;
sam_grove 5:3f93dd1d4cb3 765 __I uint32_t HcFmRemaining;
sam_grove 5:3f93dd1d4cb3 766 __I uint32_t HcFmNumber;
sam_grove 5:3f93dd1d4cb3 767 __IO uint32_t HcPeriodicStart;
sam_grove 5:3f93dd1d4cb3 768 __IO uint32_t HcLSTreshold;
sam_grove 5:3f93dd1d4cb3 769 __IO uint32_t HcRhDescriptorA;
sam_grove 5:3f93dd1d4cb3 770 __IO uint32_t HcRhDescriptorB;
sam_grove 5:3f93dd1d4cb3 771 __IO uint32_t HcRhStatus;
sam_grove 5:3f93dd1d4cb3 772 __IO uint32_t HcRhPortStatus1;
sam_grove 5:3f93dd1d4cb3 773 __IO uint32_t HcRhPortStatus2;
sam_grove 5:3f93dd1d4cb3 774 uint32_t RESERVED0[40];
sam_grove 5:3f93dd1d4cb3 775 __I uint32_t Module_ID;
sam_grove 5:3f93dd1d4cb3 776
sam_grove 5:3f93dd1d4cb3 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
sam_grove 5:3f93dd1d4cb3 778 __IO uint32_t OTGIntEn;
sam_grove 5:3f93dd1d4cb3 779 __O uint32_t OTGIntSet;
sam_grove 5:3f93dd1d4cb3 780 __O uint32_t OTGIntClr;
sam_grove 5:3f93dd1d4cb3 781 __IO uint32_t OTGStCtrl;
sam_grove 5:3f93dd1d4cb3 782 __IO uint32_t OTGTmr;
sam_grove 5:3f93dd1d4cb3 783 uint32_t RESERVED1[58];
sam_grove 5:3f93dd1d4cb3 784
sam_grove 5:3f93dd1d4cb3 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
sam_grove 5:3f93dd1d4cb3 786 __IO uint32_t USBDevIntEn;
sam_grove 5:3f93dd1d4cb3 787 __O uint32_t USBDevIntClr;
sam_grove 5:3f93dd1d4cb3 788 __O uint32_t USBDevIntSet;
sam_grove 5:3f93dd1d4cb3 789
sam_grove 5:3f93dd1d4cb3 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
sam_grove 5:3f93dd1d4cb3 791 __I uint32_t USBCmdData;
sam_grove 5:3f93dd1d4cb3 792
sam_grove 5:3f93dd1d4cb3 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
sam_grove 5:3f93dd1d4cb3 794 __O uint32_t USBTxData;
sam_grove 5:3f93dd1d4cb3 795 __I uint32_t USBRxPLen;
sam_grove 5:3f93dd1d4cb3 796 __O uint32_t USBTxPLen;
sam_grove 5:3f93dd1d4cb3 797 __IO uint32_t USBCtrl;
sam_grove 5:3f93dd1d4cb3 798 __O uint32_t USBDevIntPri;
sam_grove 5:3f93dd1d4cb3 799
sam_grove 5:3f93dd1d4cb3 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
sam_grove 5:3f93dd1d4cb3 801 __IO uint32_t USBEpIntEn;
sam_grove 5:3f93dd1d4cb3 802 __O uint32_t USBEpIntClr;
sam_grove 5:3f93dd1d4cb3 803 __O uint32_t USBEpIntSet;
sam_grove 5:3f93dd1d4cb3 804 __O uint32_t USBEpIntPri;
sam_grove 5:3f93dd1d4cb3 805
sam_grove 5:3f93dd1d4cb3 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
sam_grove 5:3f93dd1d4cb3 807 __O uint32_t USBEpInd;
sam_grove 5:3f93dd1d4cb3 808 __IO uint32_t USBMaxPSize;
sam_grove 5:3f93dd1d4cb3 809
sam_grove 5:3f93dd1d4cb3 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
sam_grove 5:3f93dd1d4cb3 811 __O uint32_t USBDMARClr;
sam_grove 5:3f93dd1d4cb3 812 __O uint32_t USBDMARSet;
sam_grove 5:3f93dd1d4cb3 813 uint32_t RESERVED2[9];
sam_grove 5:3f93dd1d4cb3 814 __IO uint32_t USBUDCAH;
sam_grove 5:3f93dd1d4cb3 815 __I uint32_t USBEpDMASt;
sam_grove 5:3f93dd1d4cb3 816 __O uint32_t USBEpDMAEn;
sam_grove 5:3f93dd1d4cb3 817 __O uint32_t USBEpDMADis;
sam_grove 5:3f93dd1d4cb3 818 __I uint32_t USBDMAIntSt;
sam_grove 5:3f93dd1d4cb3 819 __IO uint32_t USBDMAIntEn;
sam_grove 5:3f93dd1d4cb3 820 uint32_t RESERVED3[2];
sam_grove 5:3f93dd1d4cb3 821 __I uint32_t USBEoTIntSt;
sam_grove 5:3f93dd1d4cb3 822 __O uint32_t USBEoTIntClr;
sam_grove 5:3f93dd1d4cb3 823 __O uint32_t USBEoTIntSet;
sam_grove 5:3f93dd1d4cb3 824 __I uint32_t USBNDDRIntSt;
sam_grove 5:3f93dd1d4cb3 825 __O uint32_t USBNDDRIntClr;
sam_grove 5:3f93dd1d4cb3 826 __O uint32_t USBNDDRIntSet;
sam_grove 5:3f93dd1d4cb3 827 __I uint32_t USBSysErrIntSt;
sam_grove 5:3f93dd1d4cb3 828 __O uint32_t USBSysErrIntClr;
sam_grove 5:3f93dd1d4cb3 829 __O uint32_t USBSysErrIntSet;
sam_grove 5:3f93dd1d4cb3 830 uint32_t RESERVED4[15];
sam_grove 5:3f93dd1d4cb3 831
sam_grove 5:3f93dd1d4cb3 832 union {
sam_grove 5:3f93dd1d4cb3 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
sam_grove 5:3f93dd1d4cb3 834 __O uint32_t I2C_TX;
sam_grove 5:3f93dd1d4cb3 835 };
sam_grove 5:3f93dd1d4cb3 836 __I uint32_t I2C_STS;
sam_grove 5:3f93dd1d4cb3 837 __IO uint32_t I2C_CTL;
sam_grove 5:3f93dd1d4cb3 838 __IO uint32_t I2C_CLKHI;
sam_grove 5:3f93dd1d4cb3 839 __O uint32_t I2C_CLKLO;
sam_grove 5:3f93dd1d4cb3 840 uint32_t RESERVED5[824];
sam_grove 5:3f93dd1d4cb3 841
sam_grove 5:3f93dd1d4cb3 842 union {
sam_grove 5:3f93dd1d4cb3 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
sam_grove 5:3f93dd1d4cb3 844 __IO uint32_t OTGClkCtrl;
sam_grove 5:3f93dd1d4cb3 845 };
sam_grove 5:3f93dd1d4cb3 846 union {
sam_grove 5:3f93dd1d4cb3 847 __I uint32_t USBClkSt;
sam_grove 5:3f93dd1d4cb3 848 __I uint32_t OTGClkSt;
sam_grove 5:3f93dd1d4cb3 849 };
sam_grove 5:3f93dd1d4cb3 850 } LPC_USB_TypeDef;
sam_grove 5:3f93dd1d4cb3 851
sam_grove 5:3f93dd1d4cb3 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
sam_grove 5:3f93dd1d4cb3 853 typedef struct
sam_grove 5:3f93dd1d4cb3 854 {
sam_grove 5:3f93dd1d4cb3 855 __IO uint32_t MAC1; /* MAC Registers */
sam_grove 5:3f93dd1d4cb3 856 __IO uint32_t MAC2;
sam_grove 5:3f93dd1d4cb3 857 __IO uint32_t IPGT;
sam_grove 5:3f93dd1d4cb3 858 __IO uint32_t IPGR;
sam_grove 5:3f93dd1d4cb3 859 __IO uint32_t CLRT;
sam_grove 5:3f93dd1d4cb3 860 __IO uint32_t MAXF;
sam_grove 5:3f93dd1d4cb3 861 __IO uint32_t SUPP;
sam_grove 5:3f93dd1d4cb3 862 __IO uint32_t TEST;
sam_grove 5:3f93dd1d4cb3 863 __IO uint32_t MCFG;
sam_grove 5:3f93dd1d4cb3 864 __IO uint32_t MCMD;
sam_grove 5:3f93dd1d4cb3 865 __IO uint32_t MADR;
sam_grove 5:3f93dd1d4cb3 866 __O uint32_t MWTD;
sam_grove 5:3f93dd1d4cb3 867 __I uint32_t MRDD;
sam_grove 5:3f93dd1d4cb3 868 __I uint32_t MIND;
sam_grove 5:3f93dd1d4cb3 869 uint32_t RESERVED0[2];
sam_grove 5:3f93dd1d4cb3 870 __IO uint32_t SA0;
sam_grove 5:3f93dd1d4cb3 871 __IO uint32_t SA1;
sam_grove 5:3f93dd1d4cb3 872 __IO uint32_t SA2;
sam_grove 5:3f93dd1d4cb3 873 uint32_t RESERVED1[45];
sam_grove 5:3f93dd1d4cb3 874 __IO uint32_t Command; /* Control Registers */
sam_grove 5:3f93dd1d4cb3 875 __I uint32_t Status;
sam_grove 5:3f93dd1d4cb3 876 __IO uint32_t RxDescriptor;
sam_grove 5:3f93dd1d4cb3 877 __IO uint32_t RxStatus;
sam_grove 5:3f93dd1d4cb3 878 __IO uint32_t RxDescriptorNumber;
sam_grove 5:3f93dd1d4cb3 879 __I uint32_t RxProduceIndex;
sam_grove 5:3f93dd1d4cb3 880 __IO uint32_t RxConsumeIndex;
sam_grove 5:3f93dd1d4cb3 881 __IO uint32_t TxDescriptor;
sam_grove 5:3f93dd1d4cb3 882 __IO uint32_t TxStatus;
sam_grove 5:3f93dd1d4cb3 883 __IO uint32_t TxDescriptorNumber;
sam_grove 5:3f93dd1d4cb3 884 __IO uint32_t TxProduceIndex;
sam_grove 5:3f93dd1d4cb3 885 __I uint32_t TxConsumeIndex;
sam_grove 5:3f93dd1d4cb3 886 uint32_t RESERVED2[10];
sam_grove 5:3f93dd1d4cb3 887 __I uint32_t TSV0;
sam_grove 5:3f93dd1d4cb3 888 __I uint32_t TSV1;
sam_grove 5:3f93dd1d4cb3 889 __I uint32_t RSV;
sam_grove 5:3f93dd1d4cb3 890 uint32_t RESERVED3[3];
sam_grove 5:3f93dd1d4cb3 891 __IO uint32_t FlowControlCounter;
sam_grove 5:3f93dd1d4cb3 892 __I uint32_t FlowControlStatus;
sam_grove 5:3f93dd1d4cb3 893 uint32_t RESERVED4[34];
sam_grove 5:3f93dd1d4cb3 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
sam_grove 5:3f93dd1d4cb3 895 __IO uint32_t RxFilterWoLStatus;
sam_grove 5:3f93dd1d4cb3 896 __IO uint32_t RxFilterWoLClear;
sam_grove 5:3f93dd1d4cb3 897 uint32_t RESERVED5;
sam_grove 5:3f93dd1d4cb3 898 __IO uint32_t HashFilterL;
sam_grove 5:3f93dd1d4cb3 899 __IO uint32_t HashFilterH;
sam_grove 5:3f93dd1d4cb3 900 uint32_t RESERVED6[882];
sam_grove 5:3f93dd1d4cb3 901 __I uint32_t IntStatus; /* Module Control Registers */
sam_grove 5:3f93dd1d4cb3 902 __IO uint32_t IntEnable;
sam_grove 5:3f93dd1d4cb3 903 __O uint32_t IntClear;
sam_grove 5:3f93dd1d4cb3 904 __O uint32_t IntSet;
sam_grove 5:3f93dd1d4cb3 905 uint32_t RESERVED7;
sam_grove 5:3f93dd1d4cb3 906 __IO uint32_t PowerDown;
sam_grove 5:3f93dd1d4cb3 907 uint32_t RESERVED8;
sam_grove 5:3f93dd1d4cb3 908 __IO uint32_t Module_ID;
sam_grove 5:3f93dd1d4cb3 909 } LPC_EMAC_TypeDef;
sam_grove 5:3f93dd1d4cb3 910
sam_grove 5:3f93dd1d4cb3 911 #if defined ( __CC_ARM )
sam_grove 5:3f93dd1d4cb3 912 #pragma no_anon_unions
sam_grove 5:3f93dd1d4cb3 913 #endif
sam_grove 5:3f93dd1d4cb3 914
sam_grove 5:3f93dd1d4cb3 915
sam_grove 5:3f93dd1d4cb3 916 /******************************************************************************/
sam_grove 5:3f93dd1d4cb3 917 /* Peripheral memory map */
sam_grove 5:3f93dd1d4cb3 918 /******************************************************************************/
sam_grove 5:3f93dd1d4cb3 919 /* Base addresses */
sam_grove 5:3f93dd1d4cb3 920 #define LPC_FLASH_BASE (0x00000000UL)
sam_grove 5:3f93dd1d4cb3 921 #define LPC_RAM_BASE (0x10000000UL)
sam_grove 5:3f93dd1d4cb3 922 #define LPC_GPIO_BASE (0x2009C000UL)
sam_grove 5:3f93dd1d4cb3 923 #define LPC_APB0_BASE (0x40000000UL)
sam_grove 5:3f93dd1d4cb3 924 #define LPC_APB1_BASE (0x40080000UL)
sam_grove 5:3f93dd1d4cb3 925 #define LPC_AHB_BASE (0x50000000UL)
sam_grove 5:3f93dd1d4cb3 926 #define LPC_CM3_BASE (0xE0000000UL)
sam_grove 5:3f93dd1d4cb3 927
sam_grove 5:3f93dd1d4cb3 928 /* APB0 peripherals */
sam_grove 5:3f93dd1d4cb3 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
sam_grove 5:3f93dd1d4cb3 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
sam_grove 5:3f93dd1d4cb3 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
sam_grove 5:3f93dd1d4cb3 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
sam_grove 5:3f93dd1d4cb3 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
sam_grove 5:3f93dd1d4cb3 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
sam_grove 5:3f93dd1d4cb3 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
sam_grove 5:3f93dd1d4cb3 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
sam_grove 5:3f93dd1d4cb3 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
sam_grove 5:3f93dd1d4cb3 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
sam_grove 5:3f93dd1d4cb3 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
sam_grove 5:3f93dd1d4cb3 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
sam_grove 5:3f93dd1d4cb3 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
sam_grove 5:3f93dd1d4cb3 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
sam_grove 5:3f93dd1d4cb3 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
sam_grove 5:3f93dd1d4cb3 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
sam_grove 5:3f93dd1d4cb3 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
sam_grove 5:3f93dd1d4cb3 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
sam_grove 5:3f93dd1d4cb3 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
sam_grove 5:3f93dd1d4cb3 948
sam_grove 5:3f93dd1d4cb3 949 /* APB1 peripherals */
sam_grove 5:3f93dd1d4cb3 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
sam_grove 5:3f93dd1d4cb3 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
sam_grove 5:3f93dd1d4cb3 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
sam_grove 5:3f93dd1d4cb3 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
sam_grove 5:3f93dd1d4cb3 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
sam_grove 5:3f93dd1d4cb3 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
sam_grove 5:3f93dd1d4cb3 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
sam_grove 5:3f93dd1d4cb3 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
sam_grove 5:3f93dd1d4cb3 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
sam_grove 5:3f93dd1d4cb3 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
sam_grove 5:3f93dd1d4cb3 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
sam_grove 5:3f93dd1d4cb3 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
sam_grove 5:3f93dd1d4cb3 962
sam_grove 5:3f93dd1d4cb3 963 /* AHB peripherals */
sam_grove 5:3f93dd1d4cb3 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
sam_grove 5:3f93dd1d4cb3 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
sam_grove 5:3f93dd1d4cb3 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
sam_grove 5:3f93dd1d4cb3 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
sam_grove 5:3f93dd1d4cb3 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
sam_grove 5:3f93dd1d4cb3 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
sam_grove 5:3f93dd1d4cb3 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
sam_grove 5:3f93dd1d4cb3 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
sam_grove 5:3f93dd1d4cb3 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
sam_grove 5:3f93dd1d4cb3 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
sam_grove 5:3f93dd1d4cb3 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
sam_grove 5:3f93dd1d4cb3 975
sam_grove 5:3f93dd1d4cb3 976 /* GPIOs */
sam_grove 5:3f93dd1d4cb3 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
sam_grove 5:3f93dd1d4cb3 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
sam_grove 5:3f93dd1d4cb3 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
sam_grove 5:3f93dd1d4cb3 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
sam_grove 5:3f93dd1d4cb3 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
sam_grove 5:3f93dd1d4cb3 982
sam_grove 5:3f93dd1d4cb3 983
sam_grove 5:3f93dd1d4cb3 984 /******************************************************************************/
sam_grove 5:3f93dd1d4cb3 985 /* Peripheral declaration */
sam_grove 5:3f93dd1d4cb3 986 /******************************************************************************/
sam_grove 5:3f93dd1d4cb3 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
sam_grove 5:3f93dd1d4cb3 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
sam_grove 5:3f93dd1d4cb3 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
sam_grove 5:3f93dd1d4cb3 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
sam_grove 5:3f93dd1d4cb3 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
sam_grove 5:3f93dd1d4cb3 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
sam_grove 5:3f93dd1d4cb3 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
sam_grove 5:3f93dd1d4cb3 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
sam_grove 5:3f93dd1d4cb3 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
sam_grove 5:3f93dd1d4cb3 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
sam_grove 5:3f93dd1d4cb3 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
sam_grove 5:3f93dd1d4cb3 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
sam_grove 5:3f93dd1d4cb3 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
sam_grove 5:3f93dd1d4cb3 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
sam_grove 5:3f93dd1d4cb3 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
sam_grove 5:3f93dd1d4cb3 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
sam_grove 5:3f93dd1d4cb3 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
sam_grove 5:3f93dd1d4cb3 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
sam_grove 5:3f93dd1d4cb3 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
sam_grove 5:3f93dd1d4cb3 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
sam_grove 5:3f93dd1d4cb3 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
sam_grove 5:3f93dd1d4cb3 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
sam_grove 5:3f93dd1d4cb3 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
sam_grove 5:3f93dd1d4cb3 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
sam_grove 5:3f93dd1d4cb3 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
sam_grove 5:3f93dd1d4cb3 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
sam_grove 5:3f93dd1d4cb3 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
sam_grove 5:3f93dd1d4cb3 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
sam_grove 5:3f93dd1d4cb3 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
sam_grove 5:3f93dd1d4cb3 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
sam_grove 5:3f93dd1d4cb3 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
sam_grove 5:3f93dd1d4cb3 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
sam_grove 5:3f93dd1d4cb3 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
sam_grove 5:3f93dd1d4cb3 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
sam_grove 5:3f93dd1d4cb3 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
sam_grove 5:3f93dd1d4cb3 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
sam_grove 5:3f93dd1d4cb3 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
sam_grove 5:3f93dd1d4cb3 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
sam_grove 5:3f93dd1d4cb3 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
sam_grove 5:3f93dd1d4cb3 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
sam_grove 5:3f93dd1d4cb3 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
sam_grove 5:3f93dd1d4cb3 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
sam_grove 5:3f93dd1d4cb3 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
sam_grove 5:3f93dd1d4cb3 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
sam_grove 5:3f93dd1d4cb3 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
sam_grove 5:3f93dd1d4cb3 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
sam_grove 5:3f93dd1d4cb3 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
sam_grove 5:3f93dd1d4cb3 1034
sam_grove 5:3f93dd1d4cb3 1035 #endif // __LPC17xx_H__