Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-rtos/rtx/rt_HAL_CM.h@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /*----------------------------------------------------------------------------
sam_grove 5:3f93dd1d4cb3 2 * RL-ARM - RTX
sam_grove 5:3f93dd1d4cb3 3 *----------------------------------------------------------------------------
sam_grove 5:3f93dd1d4cb3 4 * Name: RT_HAL_CM.H
sam_grove 5:3f93dd1d4cb3 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
sam_grove 5:3f93dd1d4cb3 6 * Rev.: V4.60
sam_grove 5:3f93dd1d4cb3 7 *----------------------------------------------------------------------------
sam_grove 5:3f93dd1d4cb3 8 *
sam_grove 5:3f93dd1d4cb3 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
sam_grove 5:3f93dd1d4cb3 10 * All rights reserved.
sam_grove 5:3f93dd1d4cb3 11 * Redistribution and use in source and binary forms, with or without
sam_grove 5:3f93dd1d4cb3 12 * modification, are permitted provided that the following conditions are met:
sam_grove 5:3f93dd1d4cb3 13 * - Redistributions of source code must retain the above copyright
sam_grove 5:3f93dd1d4cb3 14 * notice, this list of conditions and the following disclaimer.
sam_grove 5:3f93dd1d4cb3 15 * - Redistributions in binary form must reproduce the above copyright
sam_grove 5:3f93dd1d4cb3 16 * notice, this list of conditions and the following disclaimer in the
sam_grove 5:3f93dd1d4cb3 17 * documentation and/or other materials provided with the distribution.
sam_grove 5:3f93dd1d4cb3 18 * - Neither the name of ARM nor the names of its contributors may be used
sam_grove 5:3f93dd1d4cb3 19 * to endorse or promote products derived from this software without
sam_grove 5:3f93dd1d4cb3 20 * specific prior written permission.
sam_grove 5:3f93dd1d4cb3 21 *
sam_grove 5:3f93dd1d4cb3 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sam_grove 5:3f93dd1d4cb3 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sam_grove 5:3f93dd1d4cb3 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sam_grove 5:3f93dd1d4cb3 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sam_grove 5:3f93dd1d4cb3 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sam_grove 5:3f93dd1d4cb3 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sam_grove 5:3f93dd1d4cb3 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sam_grove 5:3f93dd1d4cb3 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sam_grove 5:3f93dd1d4cb3 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sam_grove 5:3f93dd1d4cb3 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sam_grove 5:3f93dd1d4cb3 32 * POSSIBILITY OF SUCH DAMAGE.
sam_grove 5:3f93dd1d4cb3 33 *---------------------------------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 34
sam_grove 5:3f93dd1d4cb3 35 /* Definitions */
sam_grove 5:3f93dd1d4cb3 36 #define INITIAL_xPSR 0x01000000
sam_grove 5:3f93dd1d4cb3 37 #define DEMCR_TRCENA 0x01000000
sam_grove 5:3f93dd1d4cb3 38 #define ITM_ITMENA 0x00000001
sam_grove 5:3f93dd1d4cb3 39 #define MAGIC_WORD 0xE25A2EA5
sam_grove 5:3f93dd1d4cb3 40
sam_grove 5:3f93dd1d4cb3 41 #if defined (__CC_ARM) /* ARM Compiler */
sam_grove 5:3f93dd1d4cb3 42
sam_grove 5:3f93dd1d4cb3 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
sam_grove 5:3f93dd1d4cb3 44 #define __USE_EXCLUSIVE_ACCESS
sam_grove 5:3f93dd1d4cb3 45 #else
sam_grove 5:3f93dd1d4cb3 46 #undef __USE_EXCLUSIVE_ACCESS
sam_grove 5:3f93dd1d4cb3 47 #endif
sam_grove 5:3f93dd1d4cb3 48
sam_grove 5:3f93dd1d4cb3 49 #elif defined (__GNUC__) /* GNU Compiler */
sam_grove 5:3f93dd1d4cb3 50
sam_grove 5:3f93dd1d4cb3 51 #undef __USE_EXCLUSIVE_ACCESS
sam_grove 5:3f93dd1d4cb3 52
sam_grove 5:3f93dd1d4cb3 53 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
sam_grove 5:3f93dd1d4cb3 54 #define __TARGET_ARCH_6S_M 1
sam_grove 5:3f93dd1d4cb3 55 #else
sam_grove 5:3f93dd1d4cb3 56 #define __TARGET_ARCH_6S_M 0
sam_grove 5:3f93dd1d4cb3 57 #endif
sam_grove 5:3f93dd1d4cb3 58
sam_grove 5:3f93dd1d4cb3 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
sam_grove 5:3f93dd1d4cb3 60 #define __TARGET_FPU_VFP 1
sam_grove 5:3f93dd1d4cb3 61 #else
sam_grove 5:3f93dd1d4cb3 62 #define __TARGET_FPU_VFP 0
sam_grove 5:3f93dd1d4cb3 63 #endif
sam_grove 5:3f93dd1d4cb3 64
sam_grove 5:3f93dd1d4cb3 65 #define __inline inline
sam_grove 5:3f93dd1d4cb3 66 #define __weak __attribute__((weak))
sam_grove 5:3f93dd1d4cb3 67
sam_grove 5:3f93dd1d4cb3 68 #ifndef __CMSIS_GENERIC
sam_grove 5:3f93dd1d4cb3 69
sam_grove 5:3f93dd1d4cb3 70 __attribute__((always_inline)) static inline void __enable_irq(void)
sam_grove 5:3f93dd1d4cb3 71 {
sam_grove 5:3f93dd1d4cb3 72 __asm volatile ("cpsie i");
sam_grove 5:3f93dd1d4cb3 73 }
sam_grove 5:3f93dd1d4cb3 74
sam_grove 5:3f93dd1d4cb3 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
sam_grove 5:3f93dd1d4cb3 76 {
sam_grove 5:3f93dd1d4cb3 77 U32 result;
sam_grove 5:3f93dd1d4cb3 78
sam_grove 5:3f93dd1d4cb3 79 __asm volatile ("mrs %0, primask" : "=r" (result));
sam_grove 5:3f93dd1d4cb3 80 __asm volatile ("cpsid i");
sam_grove 5:3f93dd1d4cb3 81 return(result & 1);
sam_grove 5:3f93dd1d4cb3 82 }
sam_grove 5:3f93dd1d4cb3 83
sam_grove 5:3f93dd1d4cb3 84 #endif
sam_grove 5:3f93dd1d4cb3 85
sam_grove 5:3f93dd1d4cb3 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
sam_grove 5:3f93dd1d4cb3 87 {
sam_grove 5:3f93dd1d4cb3 88 U8 result;
sam_grove 5:3f93dd1d4cb3 89
sam_grove 5:3f93dd1d4cb3 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
sam_grove 5:3f93dd1d4cb3 91 return(result);
sam_grove 5:3f93dd1d4cb3 92 }
sam_grove 5:3f93dd1d4cb3 93
sam_grove 5:3f93dd1d4cb3 94 #elif defined (__ICCARM__) /* IAR Compiler */
sam_grove 5:3f93dd1d4cb3 95
sam_grove 5:3f93dd1d4cb3 96 #undef __USE_EXCLUSIVE_ACCESS
sam_grove 5:3f93dd1d4cb3 97
sam_grove 5:3f93dd1d4cb3 98 #if (__CORE__ == __ARM6M__)
sam_grove 5:3f93dd1d4cb3 99 #define __TARGET_ARCH_6S_M 1
sam_grove 5:3f93dd1d4cb3 100 #else
sam_grove 5:3f93dd1d4cb3 101 #define __TARGET_ARCH_6S_M 0
sam_grove 5:3f93dd1d4cb3 102 #endif
sam_grove 5:3f93dd1d4cb3 103
sam_grove 5:3f93dd1d4cb3 104 #if defined __ARMVFP__
sam_grove 5:3f93dd1d4cb3 105 #define __TARGET_FPU_VFP 1
sam_grove 5:3f93dd1d4cb3 106 #else
sam_grove 5:3f93dd1d4cb3 107 #define __TARGET_FPU_VFP 0
sam_grove 5:3f93dd1d4cb3 108 #endif
sam_grove 5:3f93dd1d4cb3 109
sam_grove 5:3f93dd1d4cb3 110 #define __inline inline
sam_grove 5:3f93dd1d4cb3 111
sam_grove 5:3f93dd1d4cb3 112 #ifndef __CMSIS_GENERIC
sam_grove 5:3f93dd1d4cb3 113
sam_grove 5:3f93dd1d4cb3 114 static inline void __enable_irq(void)
sam_grove 5:3f93dd1d4cb3 115 {
sam_grove 5:3f93dd1d4cb3 116 __asm volatile ("cpsie i");
sam_grove 5:3f93dd1d4cb3 117 }
sam_grove 5:3f93dd1d4cb3 118
sam_grove 5:3f93dd1d4cb3 119 static inline U32 __disable_irq(void)
sam_grove 5:3f93dd1d4cb3 120 {
sam_grove 5:3f93dd1d4cb3 121 U32 result;
sam_grove 5:3f93dd1d4cb3 122
sam_grove 5:3f93dd1d4cb3 123 __asm volatile ("mrs %0, primask" : "=r" (result));
sam_grove 5:3f93dd1d4cb3 124 __asm volatile ("cpsid i");
sam_grove 5:3f93dd1d4cb3 125 return(result & 1);
sam_grove 5:3f93dd1d4cb3 126 }
sam_grove 5:3f93dd1d4cb3 127
sam_grove 5:3f93dd1d4cb3 128 #endif
sam_grove 5:3f93dd1d4cb3 129
sam_grove 5:3f93dd1d4cb3 130 static inline U8 __clz(U32 value)
sam_grove 5:3f93dd1d4cb3 131 {
sam_grove 5:3f93dd1d4cb3 132 U8 result;
sam_grove 5:3f93dd1d4cb3 133
sam_grove 5:3f93dd1d4cb3 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
sam_grove 5:3f93dd1d4cb3 135 return(result);
sam_grove 5:3f93dd1d4cb3 136 }
sam_grove 5:3f93dd1d4cb3 137
sam_grove 5:3f93dd1d4cb3 138 #endif
sam_grove 5:3f93dd1d4cb3 139
sam_grove 5:3f93dd1d4cb3 140 /* NVIC registers */
sam_grove 5:3f93dd1d4cb3 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
sam_grove 5:3f93dd1d4cb3 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
sam_grove 5:3f93dd1d4cb3 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
sam_grove 5:3f93dd1d4cb3 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
sam_grove 5:3f93dd1d4cb3 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
sam_grove 5:3f93dd1d4cb3 146 #if (__TARGET_ARCH_6S_M)
sam_grove 5:3f93dd1d4cb3 147 #define NVIC_IP ((volatile U32 *)0xE000E400)
sam_grove 5:3f93dd1d4cb3 148 #else
sam_grove 5:3f93dd1d4cb3 149 #define NVIC_IP ((volatile U8 *)0xE000E400)
sam_grove 5:3f93dd1d4cb3 150 #endif
sam_grove 5:3f93dd1d4cb3 151 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
sam_grove 5:3f93dd1d4cb3 152 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
sam_grove 5:3f93dd1d4cb3 153 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
sam_grove 5:3f93dd1d4cb3 154 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
sam_grove 5:3f93dd1d4cb3 155
sam_grove 5:3f93dd1d4cb3 156 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
sam_grove 5:3f93dd1d4cb3 157 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
sam_grove 5:3f93dd1d4cb3 158 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
sam_grove 5:3f93dd1d4cb3 159 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
sam_grove 5:3f93dd1d4cb3 160 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
sam_grove 5:3f93dd1d4cb3 161 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
sam_grove 5:3f93dd1d4cb3 162
sam_grove 5:3f93dd1d4cb3 163 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
sam_grove 5:3f93dd1d4cb3 164 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
sam_grove 5:3f93dd1d4cb3 165 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
sam_grove 5:3f93dd1d4cb3 166 #if (__TARGET_ARCH_6S_M)
sam_grove 5:3f93dd1d4cb3 167 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
sam_grove 5:3f93dd1d4cb3 168 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
sam_grove 5:3f93dd1d4cb3 169 #else
sam_grove 5:3f93dd1d4cb3 170 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
sam_grove 5:3f93dd1d4cb3 171 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
sam_grove 5:3f93dd1d4cb3 172 #endif
sam_grove 5:3f93dd1d4cb3 173 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
sam_grove 5:3f93dd1d4cb3 174 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
sam_grove 5:3f93dd1d4cb3 175
sam_grove 5:3f93dd1d4cb3 176 /* Core Debug registers */
sam_grove 5:3f93dd1d4cb3 177 #define DEMCR (*((volatile U32 *)0xE000EDFC))
sam_grove 5:3f93dd1d4cb3 178
sam_grove 5:3f93dd1d4cb3 179 /* ITM registers */
sam_grove 5:3f93dd1d4cb3 180 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
sam_grove 5:3f93dd1d4cb3 181 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
sam_grove 5:3f93dd1d4cb3 182 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
sam_grove 5:3f93dd1d4cb3 183 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
sam_grove 5:3f93dd1d4cb3 184 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
sam_grove 5:3f93dd1d4cb3 185 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
sam_grove 5:3f93dd1d4cb3 186
sam_grove 5:3f93dd1d4cb3 187 /* Variables */
sam_grove 5:3f93dd1d4cb3 188 extern BIT dbg_msg;
sam_grove 5:3f93dd1d4cb3 189
sam_grove 5:3f93dd1d4cb3 190 /* Functions */
sam_grove 5:3f93dd1d4cb3 191 #ifdef __USE_EXCLUSIVE_ACCESS
sam_grove 5:3f93dd1d4cb3 192 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
sam_grove 5:3f93dd1d4cb3 193 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
sam_grove 5:3f93dd1d4cb3 194 #else
sam_grove 5:3f93dd1d4cb3 195 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
sam_grove 5:3f93dd1d4cb3 196 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
sam_grove 5:3f93dd1d4cb3 197 #endif
sam_grove 5:3f93dd1d4cb3 198
sam_grove 5:3f93dd1d4cb3 199 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
sam_grove 5:3f93dd1d4cb3 200 U32 cnt,c2;
sam_grove 5:3f93dd1d4cb3 201 #ifdef __USE_EXCLUSIVE_ACCESS
sam_grove 5:3f93dd1d4cb3 202 do {
sam_grove 5:3f93dd1d4cb3 203 if ((cnt = __ldrex(count)) == size) {
sam_grove 5:3f93dd1d4cb3 204 __clrex();
sam_grove 5:3f93dd1d4cb3 205 return (cnt); }
sam_grove 5:3f93dd1d4cb3 206 } while (__strex(cnt+1, count));
sam_grove 5:3f93dd1d4cb3 207 do {
sam_grove 5:3f93dd1d4cb3 208 c2 = (cnt = __ldrex(first)) + 1;
sam_grove 5:3f93dd1d4cb3 209 if (c2 == size) c2 = 0;
sam_grove 5:3f93dd1d4cb3 210 } while (__strex(c2, first));
sam_grove 5:3f93dd1d4cb3 211 #else
sam_grove 5:3f93dd1d4cb3 212 __disable_irq();
sam_grove 5:3f93dd1d4cb3 213 if ((cnt = *count) < size) {
sam_grove 5:3f93dd1d4cb3 214 *count = cnt+1;
sam_grove 5:3f93dd1d4cb3 215 c2 = (cnt = *first) + 1;
sam_grove 5:3f93dd1d4cb3 216 if (c2 == size) c2 = 0;
sam_grove 5:3f93dd1d4cb3 217 *first = c2;
sam_grove 5:3f93dd1d4cb3 218 }
sam_grove 5:3f93dd1d4cb3 219 __enable_irq ();
sam_grove 5:3f93dd1d4cb3 220 #endif
sam_grove 5:3f93dd1d4cb3 221 return (cnt);
sam_grove 5:3f93dd1d4cb3 222 }
sam_grove 5:3f93dd1d4cb3 223
sam_grove 5:3f93dd1d4cb3 224 __inline static void rt_systick_init (void) {
sam_grove 5:3f93dd1d4cb3 225 NVIC_ST_RELOAD = os_trv;
sam_grove 5:3f93dd1d4cb3 226 NVIC_ST_CURRENT = 0;
sam_grove 5:3f93dd1d4cb3 227 NVIC_ST_CTRL = 0x0007;
sam_grove 5:3f93dd1d4cb3 228 NVIC_SYS_PRI3 |= 0xFF000000;
sam_grove 5:3f93dd1d4cb3 229 }
sam_grove 5:3f93dd1d4cb3 230
sam_grove 5:3f93dd1d4cb3 231 __inline static void rt_svc_init (void) {
sam_grove 5:3f93dd1d4cb3 232 #if !(__TARGET_ARCH_6S_M)
sam_grove 5:3f93dd1d4cb3 233 int sh,prigroup;
sam_grove 5:3f93dd1d4cb3 234 #endif
sam_grove 5:3f93dd1d4cb3 235 NVIC_SYS_PRI3 |= 0x00FF0000;
sam_grove 5:3f93dd1d4cb3 236 #if (__TARGET_ARCH_6S_M)
sam_grove 5:3f93dd1d4cb3 237 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
sam_grove 5:3f93dd1d4cb3 238 #else
sam_grove 5:3f93dd1d4cb3 239 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
sam_grove 5:3f93dd1d4cb3 240 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
sam_grove 5:3f93dd1d4cb3 241 if (prigroup >= sh) {
sam_grove 5:3f93dd1d4cb3 242 sh = prigroup + 1;
sam_grove 5:3f93dd1d4cb3 243 }
sam_grove 5:3f93dd1d4cb3 244 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
sam_grove 5:3f93dd1d4cb3 245 #endif
sam_grove 5:3f93dd1d4cb3 246 }
sam_grove 5:3f93dd1d4cb3 247
sam_grove 5:3f93dd1d4cb3 248 extern void rt_set_PSP (U32 stack);
sam_grove 5:3f93dd1d4cb3 249 extern U32 rt_get_PSP (void);
sam_grove 5:3f93dd1d4cb3 250 extern void os_set_env (void);
sam_grove 5:3f93dd1d4cb3 251 extern void *_alloc_box (void *box_mem);
sam_grove 5:3f93dd1d4cb3 252 extern int _free_box (void *box_mem, void *box);
sam_grove 5:3f93dd1d4cb3 253
sam_grove 5:3f93dd1d4cb3 254 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
sam_grove 5:3f93dd1d4cb3 255 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
sam_grove 5:3f93dd1d4cb3 256 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
sam_grove 5:3f93dd1d4cb3 257
sam_grove 5:3f93dd1d4cb3 258 extern void dbg_init (void);
sam_grove 5:3f93dd1d4cb3 259 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
sam_grove 5:3f93dd1d4cb3 260 extern void dbg_task_switch (U32 task_id);
sam_grove 5:3f93dd1d4cb3 261
sam_grove 5:3f93dd1d4cb3 262 #ifdef DBG_MSG
sam_grove 5:3f93dd1d4cb3 263 #define DBG_INIT() dbg_init()
sam_grove 5:3f93dd1d4cb3 264 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
sam_grove 5:3f93dd1d4cb3 265 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
sam_grove 5:3f93dd1d4cb3 266 dbg_task_switch(task_id)
sam_grove 5:3f93dd1d4cb3 267 #else
sam_grove 5:3f93dd1d4cb3 268 #define DBG_INIT()
sam_grove 5:3f93dd1d4cb3 269 #define DBG_TASK_NOTIFY(p_tcb,create)
sam_grove 5:3f93dd1d4cb3 270 #define DBG_TASK_SWITCH(task_id)
sam_grove 5:3f93dd1d4cb3 271 #endif
sam_grove 5:3f93dd1d4cb3 272
sam_grove 5:3f93dd1d4cb3 273 /*----------------------------------------------------------------------------
sam_grove 5:3f93dd1d4cb3 274 * end of file
sam_grove 5:3f93dd1d4cb3 275 *---------------------------------------------------------------------------*/
sam_grove 5:3f93dd1d4cb3 276